From f331967b3da2511facff76a75f9b27f21df78527 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Wed, 18 Dec 2024 11:42:24 -0800
Subject: spi: mxc_spi: use proper clock for SPI bus

The mxc_get_clock function is around for compatibility with older
drivers that are not clock aware. In this case asking for the clk for
MXC_CSPI_CLK does not take into account there are multiple SPI busses on
modern IMX SoC's and it will return the clock for the first bus which
may not be used or configured.

In the case you are not using the first bus you will not get the proper
clock. Fix this by obtaining the clock rate from the bus clock.

This resolves an invalid SPI clock frequency configuration for SPI2 on a
board where SPI1 is not used.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
 drivers/spi/mxc_spi.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 9ab39a188b2..2c9b0ada87b 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -114,6 +114,9 @@ struct mxc_spi_slave {
 	u32		ctrl_reg;
 #if defined(MXC_ECSPI)
 	u32		cfg_reg;
+#endif
+#if CONFIG_IS_ENABLED(CLK)
+	struct clk	clk;
 #endif
 	int		gpio;
 	int		ss_pol;
@@ -214,7 +217,11 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
 #ifdef MXC_ECSPI
 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
 {
+#if CONFIG_IS_ENABLED(CLK)
+	u32 clk_src = clk_get_rate(&mxcs->clk);
+#else
 	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
+#endif
 	s32 reg_ctrl, reg_config;
 	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
 	u32 pre_div = 0, post_div = 0;
@@ -599,14 +606,13 @@ static int mxc_spi_probe(struct udevice *bus)
 		return -ENODEV;
 
 #if CONFIG_IS_ENABLED(CLK)
-	struct clk clk;
-	ret = clk_get_by_index(bus, 0, &clk);
+	ret = clk_get_by_index(bus, 0, &mxcs->clk);
 	if (ret)
 		return ret;
 
-	clk_enable(&clk);
+	clk_enable(&mxcs->clk);
 
-	mxcs->max_hz = clk_get_rate(&clk);
+	mxcs->max_hz = clk_get_rate(&mxcs->clk);
 #else
 	int node = dev_of_offset(bus);
 	const void *blob = gd->fdt_blob;
-- 
cgit v1.2.3


From 795a7425a73ee948a722357260adc8ce9bbeb547 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Wed, 18 Dec 2024 11:45:41 -0800
Subject: drivers: misc: gsc: add support for fan controller

Add support for Gateworks System Controller fan tach input.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
 drivers/misc/gsc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/misc/gsc.c b/drivers/misc/gsc.c
index dee0bdd9663..bab405bb722 100644
--- a/drivers/misc/gsc.c
+++ b/drivers/misc/gsc.c
@@ -330,6 +330,9 @@ static int gsc_hwmon(struct udevice *dev)
 
 			printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
 			break;
+		case 4: /* revolutions per minute */
+			printf("%-8s: %drpm\n", label, val * 30);
+			break;
 		}
 	}
 
-- 
cgit v1.2.3


From 87bdb4e8a70b37d9fb89d10a64c20a44fed7bab2 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Wed, 18 Dec 2024 11:45:42 -0800
Subject: drivers: misc: gsc: add support for prescaled

Add support for Gateworks System Controller pre-scaled ADC input.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
 drivers/misc/gsc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/misc/gsc.c b/drivers/misc/gsc.c
index bab405bb722..72a13abaaee 100644
--- a/drivers/misc/gsc.c
+++ b/drivers/misc/gsc.c
@@ -310,6 +310,7 @@ static int gsc_hwmon(struct udevice *dev)
 			printf("%-8s: %d.%ldC\n", label, val / 10, abs(val % 10));
 			break;
 		case 1: /* prescaled voltage */
+		case 3:
 			if (val != 0xffff)
 				printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
 			break;
-- 
cgit v1.2.3


From b0b8f8586f4d904f871ecd535015b07727db2e2a Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Wed, 18 Dec 2024 11:47:31 -0800
Subject: imx8m*-venice: define suitable address for SPL_LOAD_FIT_ADDRESS

define a suitable default address for CONFIG_SPL_LOAD_FIT_ADDRESS
to make it easier on folks enabling HABv4.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
 configs/imx8mm_venice_defconfig | 1 +
 configs/imx8mn_venice_defconfig | 1 +
 configs/imx8mp_venice_defconfig | 1 +
 3 files changed, 3 insertions(+)

diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
index da248e4887e..5f3c5be90ec 100644
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@@ -31,6 +31,7 @@ CONFIG_SYS_MEMTEST_END=0x80000000
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig
index 44af3e61d5d..38fc7e7f825 100644
--- a/configs/imx8mn_venice_defconfig
+++ b/configs/imx8mn_venice_defconfig
@@ -30,6 +30,7 @@ CONFIG_SYS_MEMTEST_END=0x80000000
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig
index bf296b13e2b..faf696fdbd1 100644
--- a/configs/imx8mp_venice_defconfig
+++ b/configs/imx8mp_venice_defconfig
@@ -32,6 +32,7 @@ CONFIG_SYS_MEMTEST_END=0x80000000
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
-- 
cgit v1.2.3


From 7f02219eb6acea0febd4e29cb2c5192b762ed213 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Wed, 18 Dec 2024 13:20:35 -0800
Subject: arm: dts: imx8mp-venice-gw7*xx: fix TPM reset

With an IMX8MP based SOM the SPI RST is gpio4_9 instead of gpio1_11.
Fix this.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
 arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi | 16 +++++++---------
 arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi | 16 +++++++---------
 arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi | 16 +++++++---------
 3 files changed, 21 insertions(+), 27 deletions(-)

diff --git a/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi
index 216a7a0d8d7..a291b7abab6 100644
--- a/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi
@@ -4,15 +4,6 @@
  */
 #include "imx8mp-venice-gw702x-u-boot.dtsi"
 
-&gpio1 {
-	tpm_rst {
-		gpio-hog;
-		output-high;
-		gpios = <11 GPIO_ACTIVE_HIGH>;
-		line-name = "tpm_rst#";
-	};
-};
-
 &gpio4 {
 	dio_1 {
 		gpio-hog;
@@ -21,6 +12,13 @@
 		line-name = "dio1";
 	};
 
+	tpm_rst {
+		gpio-hog;
+		output-high;
+		gpios = <9 GPIO_ACTIVE_HIGH>;
+		line-name = "tpm_rst#";
+	};
+
 	dio_0 {
 		gpio-hog;
 		input;
diff --git a/arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi
index 525316d1189..bdf5370fcdf 100644
--- a/arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi
@@ -4,15 +4,6 @@
  */
 #include "imx8mp-venice-gw702x-u-boot.dtsi"
 
-&gpio1 {
-	tpm_rst {
-		gpio-hog;
-		output-high;
-		gpios = <11 GPIO_ACTIVE_HIGH>;
-		line-name = "tpm_rst#";
-	};
-};
-
 &gpio4 {
 	dio_1 {
 		gpio-hog;
@@ -21,6 +12,13 @@
 		line-name = "dio1";
 	};
 
+	tpm_rst {
+		gpio-hog;
+		output-high;
+		gpios = <9 GPIO_ACTIVE_HIGH>;
+		line-name = "tpm_rst#";
+	};
+
 	dio_0 {
 		gpio-hog;
 		input;
diff --git a/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi
index 4d0e9a1e67c..7e6f66bd9dd 100644
--- a/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi
@@ -10,15 +10,6 @@
 	reset-post-delay-us = <300000>;
 };
 
-&gpio1 {
-	tpm_rst {
-		gpio-hog;
-		output-high;
-		gpios = <11 GPIO_ACTIVE_HIGH>;
-		line-name = "tpm_rst#";
-	};
-};
-
 &gpio4 {
 	dio_1 {
 		gpio-hog;
@@ -27,6 +18,13 @@
 		line-name = "dio1";
 	};
 
+	tpm_rst {
+		gpio-hog;
+		output-high;
+		gpios = <9 GPIO_ACTIVE_HIGH>;
+		line-name = "tpm_rst#";
+	};
+
 	dio_0 {
 		gpio-hog;
 		input;
-- 
cgit v1.2.3


From 2f74cac8c324339eaf123a2e7d602b4568d87ce1 Mon Sep 17 00:00:00 2001
From: Meng Li <meng.li@windriver.com>
Date: Mon, 23 Dec 2024 10:41:04 +0800
Subject: net: fec_mxc: add DM_FLAG_ACTIVE_DMA flag for FEC network driver

When FEC network card works as the prime one in u-boot, and is in
active status, kernel might crash during booting up stage, especially
working with grub. Because the DMA of FEC is still in active status, and
copy data into memory if there is network data received. In this case, if
kernel allocated a part of memory that has overlay with the memory
used by DMA, kernel memory may be destroyed and cause kernel crashes.
Because before kernel boots up really, u-boot dm_remove_devices_flags()
can call the remove callback of FEC driver with DM_FLAG_ACTIVE_DMA
flag. In fecmxc_remove(), phy power is disabled, so there is no data
received. In this way, it makes sure that there is no DMA action, so
that avoid kernel crashing occurs.

Signed-off-by: Meng Li <Meng.Li@windriver.com>
---
 drivers/net/fec_mxc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 7d2170ae72c..54b08482b91 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1503,4 +1503,5 @@ U_BOOT_DRIVER(fecmxc_gem) = {
 	.ops	= &fecmxc_ops,
 	.priv_auto	= sizeof(struct fec_priv),
 	.plat_auto	= sizeof(struct eth_pdata),
+	.flags = DM_FLAG_ACTIVE_DMA,
 };
-- 
cgit v1.2.3


From 6016960ceb9d3fda591cda94df3841748fb65596 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Mon, 23 Dec 2024 10:55:36 +0800
Subject: imx: Use per board ddrphy_trained_csr

Drop global ddrphy_trained_csr which maybe different with per board
ddrphy_trained_csr. DDR TOOL generates ddrphy_trained_csr for each
board, using the global ddrphy_trained_csr has risk that values may
be not up to date.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx8m/ddr.h |   3 -
 arch/arm/include/asm/arch-imx9/ddr.h  |   3 -
 drivers/ddr/imx/phy/Makefile          |   2 +-
 drivers/ddr/imx/phy/ddrphy_csr.c      | 732 ----------------------------------
 drivers/ddr/imx/phy/ddrphy_train.c    |   3 +-
 drivers/ddr/imx/phy/helper.c          |   8 +-
 6 files changed, 7 insertions(+), 744 deletions(-)
 delete mode 100644 drivers/ddr/imx/phy/ddrphy_csr.c

diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h
index 1f81d91977c..5092ccae188 100644
--- a/arch/arm/include/asm/arch-imx8m/ddr.h
+++ b/arch/arm/include/asm/arch-imx8m/ddr.h
@@ -747,7 +747,4 @@ static inline void reg32setbit(unsigned long addr, u32 bit)
 #define dwc_ddrphy_apb_rd(addr) \
 	reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr))
 
-extern struct dram_cfg_param ddrphy_trained_csr[];
-extern uint32_t ddrphy_trained_csr_num;
-
 #endif
diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h
index 2b22f3a5bea..0dd2d62b9ef 100644
--- a/arch/arm/include/asm/arch-imx9/ddr.h
+++ b/arch/arm/include/asm/arch-imx9/ddr.h
@@ -141,7 +141,4 @@ static inline void reg32setbit(unsigned long addr, u32 bit)
 #define dwc_ddrphy_apb_rd(addr) \
 	reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr))
 
-extern struct dram_cfg_param ddrphy_trained_csr[];
-extern u32 ddrphy_trained_csr_num;
-
 #endif
diff --git a/drivers/ddr/imx/phy/Makefile b/drivers/ddr/imx/phy/Makefile
index 592d0c6ebad..95c93ba16d5 100644
--- a/drivers/ddr/imx/phy/Makefile
+++ b/drivers/ddr/imx/phy/Makefile
@@ -5,5 +5,5 @@
 #
 
 ifdef CONFIG_XPL_BUILD
-obj-$(CONFIG_IMX_SNPS_DDR_PHY) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o
+obj-$(CONFIG_IMX_SNPS_DDR_PHY) += helper.o ddrphy_utils.o ddrphy_train.o
 endif
diff --git a/drivers/ddr/imx/phy/ddrphy_csr.c b/drivers/ddr/imx/phy/ddrphy_csr.c
deleted file mode 100644
index 67dd4e7059f..00000000000
--- a/drivers/ddr/imx/phy/ddrphy_csr.c
+++ /dev/null
@@ -1,732 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2018 NXP
- */
-
-#include <linux/kernel.h>
-#include <asm/arch/ddr.h>
-
-/* ddr phy trained csr */
-struct dram_cfg_param ddrphy_trained_csr[] = {
-	{ 0x200b2, 0x0 },
-	{ 0x1200b2, 0x0 },
-	{ 0x2200b2, 0x0 },
-	{ 0x200cb, 0x0 },
-	{ 0x10043, 0x0 },
-	{ 0x110043, 0x0 },
-	{ 0x210043, 0x0 },
-	{ 0x10143, 0x0 },
-	{ 0x110143, 0x0 },
-	{ 0x210143, 0x0 },
-	{ 0x11043, 0x0 },
-	{ 0x111043, 0x0 },
-	{ 0x211043, 0x0 },
-	{ 0x11143, 0x0 },
-	{ 0x111143, 0x0 },
-	{ 0x211143, 0x0 },
-	{ 0x12043, 0x0 },
-	{ 0x112043, 0x0 },
-	{ 0x212043, 0x0 },
-	{ 0x12143, 0x0 },
-	{ 0x112143, 0x0 },
-	{ 0x212143, 0x0 },
-	{ 0x13043, 0x0 },
-	{ 0x113043, 0x0 },
-	{ 0x213043, 0x0 },
-	{ 0x13143, 0x0 },
-	{ 0x113143, 0x0 },
-	{ 0x213143, 0x0 },
-	{ 0x80, 0x0 },
-	{ 0x100080, 0x0 },
-	{ 0x200080, 0x0 },
-	{ 0x1080, 0x0 },
-	{ 0x101080, 0x0 },
-	{ 0x201080, 0x0 },
-	{ 0x2080, 0x0 },
-	{ 0x102080, 0x0 },
-	{ 0x202080, 0x0 },
-	{ 0x3080, 0x0 },
-	{ 0x103080, 0x0 },
-	{ 0x203080, 0x0 },
-	{ 0x4080, 0x0 },
-	{ 0x104080, 0x0 },
-	{ 0x204080, 0x0 },
-	{ 0x5080, 0x0 },
-	{ 0x105080, 0x0 },
-	{ 0x205080, 0x0 },
-	{ 0x6080, 0x0 },
-	{ 0x106080, 0x0 },
-	{ 0x206080, 0x0 },
-	{ 0x7080, 0x0 },
-	{ 0x107080, 0x0 },
-	{ 0x207080, 0x0 },
-	{ 0x8080, 0x0 },
-	{ 0x108080, 0x0 },
-	{ 0x208080, 0x0 },
-	{ 0x9080, 0x0 },
-	{ 0x109080, 0x0 },
-	{ 0x209080, 0x0 },
-	{ 0x10080, 0x0 },
-	{ 0x110080, 0x0 },
-	{ 0x210080, 0x0 },
-	{ 0x10180, 0x0 },
-	{ 0x110180, 0x0 },
-	{ 0x210180, 0x0 },
-	{ 0x11080, 0x0 },
-	{ 0x111080, 0x0 },
-	{ 0x211080, 0x0 },
-	{ 0x11180, 0x0 },
-	{ 0x111180, 0x0 },
-	{ 0x211180, 0x0 },
-	{ 0x12080, 0x0 },
-	{ 0x112080, 0x0 },
-	{ 0x212080, 0x0 },
-	{ 0x12180, 0x0 },
-	{ 0x112180, 0x0 },
-	{ 0x212180, 0x0 },
-	{ 0x13080, 0x0 },
-	{ 0x113080, 0x0 },
-	{ 0x213080, 0x0 },
-	{ 0x13180, 0x0 },
-	{ 0x113180, 0x0 },
-	{ 0x213180, 0x0 },
-	{ 0x10081, 0x0 },
-	{ 0x110081, 0x0 },
-	{ 0x210081, 0x0 },
-	{ 0x10181, 0x0 },
-	{ 0x110181, 0x0 },
-	{ 0x210181, 0x0 },
-	{ 0x11081, 0x0 },
-	{ 0x111081, 0x0 },
-	{ 0x211081, 0x0 },
-	{ 0x11181, 0x0 },
-	{ 0x111181, 0x0 },
-	{ 0x211181, 0x0 },
-	{ 0x12081, 0x0 },
-	{ 0x112081, 0x0 },
-	{ 0x212081, 0x0 },
-	{ 0x12181, 0x0 },
-	{ 0x112181, 0x0 },
-	{ 0x212181, 0x0 },
-	{ 0x13081, 0x0 },
-	{ 0x113081, 0x0 },
-	{ 0x213081, 0x0 },
-	{ 0x13181, 0x0 },
-	{ 0x113181, 0x0 },
-	{ 0x213181, 0x0 },
-	{ 0x100d0, 0x0 },
-	{ 0x1100d0, 0x0 },
-	{ 0x2100d0, 0x0 },
-	{ 0x101d0, 0x0 },
-	{ 0x1101d0, 0x0 },
-	{ 0x2101d0, 0x0 },
-	{ 0x110d0, 0x0 },
-	{ 0x1110d0, 0x0 },
-	{ 0x2110d0, 0x0 },
-	{ 0x111d0, 0x0 },
-	{ 0x1111d0, 0x0 },
-	{ 0x2111d0, 0x0 },
-	{ 0x120d0, 0x0 },
-	{ 0x1120d0, 0x0 },
-	{ 0x2120d0, 0x0 },
-	{ 0x121d0, 0x0 },
-	{ 0x1121d0, 0x0 },
-	{ 0x2121d0, 0x0 },
-	{ 0x130d0, 0x0 },
-	{ 0x1130d0, 0x0 },
-	{ 0x2130d0, 0x0 },
-	{ 0x131d0, 0x0 },
-	{ 0x1131d0, 0x0 },
-	{ 0x2131d0, 0x0 },
-	{ 0x100d1, 0x0 },
-	{ 0x1100d1, 0x0 },
-	{ 0x2100d1, 0x0 },
-	{ 0x101d1, 0x0 },
-	{ 0x1101d1, 0x0 },
-	{ 0x2101d1, 0x0 },
-	{ 0x110d1, 0x0 },
-	{ 0x1110d1, 0x0 },
-	{ 0x2110d1, 0x0 },
-	{ 0x111d1, 0x0 },
-	{ 0x1111d1, 0x0 },
-	{ 0x2111d1, 0x0 },
-	{ 0x120d1, 0x0 },
-	{ 0x1120d1, 0x0 },
-	{ 0x2120d1, 0x0 },
-	{ 0x121d1, 0x0 },
-	{ 0x1121d1, 0x0 },
-	{ 0x2121d1, 0x0 },
-	{ 0x130d1, 0x0 },
-	{ 0x1130d1, 0x0 },
-	{ 0x2130d1, 0x0 },
-	{ 0x131d1, 0x0 },
-	{ 0x1131d1, 0x0 },
-	{ 0x2131d1, 0x0 },
-	{ 0x10068, 0x0 },
-	{ 0x10168, 0x0 },
-	{ 0x10268, 0x0 },
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-	{ 0x13440, 0x0 },
-	{ 0x13540, 0x0 },
-	{ 0x13640, 0x0 },
-	{ 0x13740, 0x0 },
-	{ 0x13840, 0x0 },
-	{ 0x13030, 0x0 },
-	{ 0x13130, 0x0 },
-	{ 0x13230, 0x0 },
-	{ 0x13330, 0x0 },
-	{ 0x13430, 0x0 },
-	{ 0x13530, 0x0 },
-	{ 0x13630, 0x0 },
-	{ 0x13730, 0x0 },
-	{ 0x13830, 0x0 },
-};
-
-uint32_t ddrphy_trained_csr_num = ARRAY_SIZE(ddrphy_trained_csr);
diff --git a/drivers/ddr/imx/phy/ddrphy_train.c b/drivers/ddr/imx/phy/ddrphy_train.c
index 2a2161dec33..1a2d071d6f1 100644
--- a/drivers/ddr/imx/phy/ddrphy_train.c
+++ b/drivers/ddr/imx/phy/ddrphy_train.c
@@ -90,7 +90,8 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing)
 	}
 
 	/* save the ddr PHY trained CSR in memory for low power use */
-	ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num);
+	ddrphy_trained_csr_save(dram_timing->ddrphy_trained_csr,
+				dram_timing->ddrphy_trained_csr_num);
 
 	return 0;
 }
diff --git a/drivers/ddr/imx/phy/helper.c b/drivers/ddr/imx/phy/helper.c
index c1fc800f191..b0dfc3a0b4f 100644
--- a/drivers/ddr/imx/phy/helper.c
+++ b/drivers/ddr/imx/phy/helper.c
@@ -181,7 +181,7 @@ void *dram_config_save(struct dram_timing_info *timing_info, unsigned long saved
 
 	saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num;
 	saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num;
-	saved_timing->ddrphy_trained_csr_num = ddrphy_trained_csr_num;
+	saved_timing->ddrphy_trained_csr_num = timing_info->ddrphy_trained_csr_num;
 	saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num;
 
 	/* save the fsp table */
@@ -209,9 +209,9 @@ void *dram_config_save(struct dram_timing_info *timing_info, unsigned long saved
 
 	/* save the ddrphy csr */
 	saved_timing->ddrphy_trained_csr = cfg;
-	for (i = 0; i < ddrphy_trained_csr_num; i++) {
-		cfg->reg = ddrphy_trained_csr[i].reg;
-		cfg->val = ddrphy_trained_csr[i].val;
+	for (i = 0; i < timing_info->ddrphy_trained_csr_num; i++) {
+		cfg->reg = timing_info->ddrphy_trained_csr[i].reg;
+		cfg->val = timing_info->ddrphy_trained_csr[i].val;
 		cfg++;
 	}
 
-- 
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