From 935e09cdcb6d6dfa41f4cd8c8a69da52ef6850ed Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sun, 9 Oct 2016 23:52:57 +0900 Subject: pinctrl: uniphier: fix unused-const-variable warnings for GCC 6.x Marek reports warnings in UniPhier pinctrl drivers when compiled by GCC 6.x, like: drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c:58:18: warning: 'usb3_muxvals' defined but not used [-Wunused-const-variable=] static const int usb3_muxvals[] = {0, 0}; ^~~~~~~~~~~~ My intention here is to compile minimum set of pin data for SPL to save memory footprint, but GCC these days is clever enough to notice unused data arrays. We can fix it by sprinkling around __maybe_unused on those arrays, but I did not do that because they are counterparts of the pinctrl drivers in Linux. All the pin data were just copy-pasted from Linux and are kept in sync for maintainability. I chose a bit tricky way to fix the issue; calculate ARRAY_SIZE of *_pins and *_muxvals and set their sum to an unused struct member. This trick will satisfy GCC because the data arrays are used anyway, but such data arrays will be dropped from the final binary because the pointers to them are not used. Signed-off-by: Masahiro Yamada Reported-by: Marek Vasut --- drivers/pinctrl/uniphier/pinctrl-uniphier.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h index 5c3db2ab605..21e2d377b4c 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h @@ -91,7 +91,12 @@ struct uniphier_pinctrl_socdata { #define __UNIPHIER_PINMUX_FUNCTION(func) #func #ifdef CONFIG_SPL_BUILD -#define UNIPHIER_PINCTRL_GROUP(grp) { .name = NULL } + /* + * a tricky way to drop unneeded *_pins and *_muxvals arrays from SPL, + * suppressing "defined but not used" warnings. + */ +#define UNIPHIER_PINCTRL_GROUP(grp) \ + { .num_pins = ARRAY_SIZE(grp##_pins) + ARRAY_SIZE(grp##_muxvals) } #define UNIPHIER_PINMUX_FUNCTION(func) NULL #else #define UNIPHIER_PINCTRL_GROUP(grp) __UNIPHIER_PINCTRL_GROUP(grp) -- cgit v1.3.1 From 0bd203bbd15ff4ef4ef6a57695e90ac8cfefb3e4 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 12 Oct 2016 21:14:38 +0900 Subject: ARM: uniphier: fix addresses of Cortex-A72 gear setting macros My mistake during copy-paste work. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/sc64-regs.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h index 780fdd176f0..b0a4281f441 100644 --- a/arch/arm/mach-uniphier/sc64-regs.h +++ b/arch/arm/mach-uniphier/sc64-regs.h @@ -63,9 +63,9 @@ #define SC_CLKCTRL7_UMC31 (1 << 1) #define SC_CLKCTRL7_UMC30 (1 << 0) -#define SC_CA72_GEARST (SC_BASE_ADDR | 0x8080) -#define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8084) -#define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8088) +#define SC_CA72_GEARST (SC_BASE_ADDR | 0x8000) +#define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8004) +#define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8008) #define SC_CA53_GEARST (SC_BASE_ADDR | 0x8080) #define SC_CA53_GEARSET (SC_BASE_ADDR | 0x8084) #define SC_CA53_GEARUPD (SC_BASE_ADDR | 0x8088) -- cgit v1.3.1 From f666a658242e94d3413b4acfc2af4b4800ab3886 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 14 Oct 2016 00:39:59 +0900 Subject: ARM: uniphier: remove unneeded CONFIG_USB_MAX_CONTROLLER_COUNT define ARCH_UNIPHIER selects DM_USB, where CONFIG_USB_MAX_CONTROLLER_COUNT is not used. Signed-off-by: Masahiro Yamada Reviewed-by: Simon Glass --- include/configs/uniphier.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 7331d133243..5be46e5c5a2 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -126,7 +126,6 @@ #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 /* USB */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4 #define CONFIG_FAT_WRITE #define CONFIG_DOS_PARTITION -- cgit v1.3.1 From 805dc44cc8afc357f7cdca8b183d0b641768bdb2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 17 Oct 2016 22:18:01 +0900 Subject: clk: uniphier: rework UniPhier clk driver The initial design of the UniPhier clk driver for U-Boot was not very nice. Here is a re-work to sync it with Linux's clk and reset drivers, maximizing the code reuse from Linux's clk data. Signed-off-by: Masahiro Yamada --- drivers/clk/uniphier/Kconfig | 15 +-- drivers/clk/uniphier/Makefile | 5 +- drivers/clk/uniphier/clk-uniphier-core.c | 170 +++++++++++++--------------- drivers/clk/uniphier/clk-uniphier-mio.c | 183 +++++++++++-------------------- drivers/clk/uniphier/clk-uniphier.h | 46 +++++--- 5 files changed, 179 insertions(+), 240 deletions(-) diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig index 0e90c01a9a9..da3e3553895 100644 --- a/drivers/clk/uniphier/Kconfig +++ b/drivers/clk/uniphier/Kconfig @@ -1,13 +1,10 @@ config CLK_UNIPHIER - bool + bool "Clock driver for UniPhier SoCs" + depends on ARCH_UNIPHIER select CLK select SPL_CLK - -menu "Clock drivers for UniPhier SoCs" - depends on CLK_UNIPHIER - -config CLK_UNIPHIER_MIO - bool "Clock driver for UniPhier Media I/O block" default y - -endmenu + help + Support for clock controllers on UniPhier SoCs. + Say Y if you want to control clocks provided by System Control + block, Media I/O block, Peripheral Block. diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile index a3168f9bc1b..ed623aa56f7 100644 --- a/drivers/clk/uniphier/Makefile +++ b/drivers/clk/uniphier/Makefile @@ -1,3 +1,2 @@ -obj-y += clk-uniphier-core.o - -obj-$(CONFIG_CLK_UNIPHIER_MIO) += clk-uniphier-mio.o +obj-y += clk-uniphier-core.o +obj-y += clk-uniphier-mio.o diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index 394832607ed..8ad0242d2a7 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -6,11 +6,11 @@ */ #include +#include +#include #include #include #include -#include -#include #include "clk-uniphier.h" @@ -18,136 +18,106 @@ * struct uniphier_clk_priv - private data for UniPhier clock driver * * @base: base address of the clock provider - * @socdata: SoC specific data + * @data: SoC specific data */ struct uniphier_clk_priv { void __iomem *base; - const struct uniphier_clk_soc_data *socdata; + const struct uniphier_clk_data *data; }; -int uniphier_clk_probe(struct udevice *dev) +static int uniphier_clk_enable(struct clk *clk) { - struct uniphier_clk_priv *priv = dev_get_priv(dev); - fdt_addr_t addr; + struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); + unsigned long id = clk->id; + const struct uniphier_clk_gate_data *p; - addr = dev_get_addr(dev->parent); - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; + for (p = priv->data->gate; p->id != UNIPHIER_CLK_ID_END; p++) { + u32 val; - priv->base = devm_ioremap(dev, addr, SZ_4K); - if (!priv->base) - return -ENOMEM; + if (p->id != id) + continue; - priv->socdata = (void *)dev_get_driver_data(dev); + val = readl(priv->base + p->reg); + val |= BIT(p->bit); + writel(val, priv->base + p->reg); - return 0; + return 0; + } + + dev_err(priv->dev, "clk_id=%lu was not handled\n", id); + return -EINVAL; } -static int uniphier_clk_enable(struct clk *clk) +static const struct uniphier_clk_mux_data * +uniphier_clk_get_mux_data(struct uniphier_clk_priv *priv, unsigned long id) { - struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); - const struct uniphier_clk_gate_data *gate = priv->socdata->gate; - unsigned int nr_gate = priv->socdata->nr_gate; - void __iomem *reg; - u32 mask, data, tmp; - int i; - - for (i = 0; i < nr_gate; i++) { - if (gate[i].index != clk->id) - continue; - - reg = priv->base + gate[i].reg; - mask = gate[i].mask; - data = gate[i].data & mask; + const struct uniphier_clk_mux_data *p; - tmp = readl(reg); - tmp &= ~mask; - tmp |= data & mask; - debug("%s: %p: %08x\n", __func__, reg, tmp); - writel(tmp, reg); + for (p = priv->data->mux; p->id != UNIPHIER_CLK_ID_END; p++) { + if (p->id == id) + return p; } - return 0; + return NULL; } static ulong uniphier_clk_get_rate(struct clk *clk) { struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); - const struct uniphier_clk_rate_data *rdata = priv->socdata->rate; - unsigned int nr_rdata = priv->socdata->nr_rate; - void __iomem *reg; - u32 mask, data; - ulong matched_rate = 0; + const struct uniphier_clk_mux_data *mux; + u32 val; int i; - for (i = 0; i < nr_rdata; i++) { - if (rdata[i].index != clk->id) - continue; + mux = uniphier_clk_get_mux_data(priv, clk->id); + if (!mux) + return 0; - if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED) - return rdata[i].rate; - - reg = priv->base + rdata[i].reg; - mask = rdata[i].mask; - data = rdata[i].data & mask; - if ((readl(reg) & mask) == data) { - if (matched_rate && rdata[i].rate != matched_rate) { - printf("failed to get clk rate for insane register values\n"); - return -EINVAL; - } - matched_rate = rdata[i].rate; - } - } + if (!mux->nr_muxs) /* fixed-rate */ + return mux->rates[0]; + + val = readl(priv->base + mux->reg); - debug("%s: rate = %lu\n", __func__, matched_rate); + for (i = 0; i < mux->nr_muxs; i++) + if ((mux->masks[i] & val) == mux->vals[i]) + return mux->rates[i]; - return matched_rate; + return -EINVAL; } static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate) { struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); - const struct uniphier_clk_rate_data *rdata = priv->socdata->rate; - unsigned int nr_rdata = priv->socdata->nr_rate; - void __iomem *reg; - u32 mask, data, tmp; + const struct uniphier_clk_mux_data *mux; + u32 val; + int i, best_rate_id = -1; ulong best_rate = 0; - int i; - /* first, decide the best match rate */ - for (i = 0; i < nr_rdata; i++) { - if (rdata[i].index != clk->id) - continue; + mux = uniphier_clk_get_mux_data(priv, clk->id); + if (!mux) + return 0; - if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED) - return 0; + if (!mux->nr_muxs) /* fixed-rate */ + return mux->rates[0]; - if (rdata[i].rate > best_rate && rdata[i].rate <= rate) - best_rate = rdata[i].rate; + /* first, decide the best match rate */ + for (i = 0; i < mux->nr_muxs; i++) { + if (mux->rates[i] > best_rate && mux->rates[i] <= rate) { + best_rate = mux->rates[i]; + best_rate_id = i; + } } - if (!best_rate) - return -ENODEV; + if (best_rate_id < 0) + return -EINVAL; + + val = readl(priv->base + mux->reg); + val &= ~mux->masks[best_rate_id]; + val |= mux->vals[best_rate_id]; + writel(val, priv->base + mux->reg); debug("%s: requested rate = %lu, set rate = %lu\n", __func__, rate, best_rate); - /* second, really set registers */ - for (i = 0; i < nr_rdata; i++) { - if (rdata[i].index != clk->id || rdata[i].rate != best_rate) - continue; - - reg = priv->base + rdata[i].reg; - mask = rdata[i].mask; - data = rdata[i].data & mask; - - tmp = readl(reg); - tmp &= ~mask; - tmp |= data; - debug("%s: %p: %08x\n", __func__, reg, tmp); - writel(tmp, reg); - } - return best_rate; } @@ -157,6 +127,24 @@ const struct clk_ops uniphier_clk_ops = { .set_rate = uniphier_clk_set_rate, }; +static int uniphier_clk_probe(struct udevice *dev) +{ + struct uniphier_clk_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + + addr = dev_get_addr(dev->parent); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = devm_ioremap(dev, addr, SZ_4K); + if (!priv->base) + return -ENOMEM; + + priv->data = (void *)dev_get_driver_data(dev); + + return 0; +} + static const struct udevice_id uniphier_clk_match[] = { { .compatible = "socionext,uniphier-sld3-mio-clock", diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c index c1e7197c1a8..18e68567092 100644 --- a/drivers/clk/uniphier/clk-uniphier-mio.c +++ b/drivers/clk/uniphier/clk-uniphier-mio.c @@ -5,136 +5,81 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include - #include "clk-uniphier.h" -#define UNIPHIER_MIO_CLK_GATE_SD(ch, idx) \ - { \ - .index = (idx), \ - .reg = 0x20 + 0x200 * (ch), \ - .mask = 0x00000100, \ - .data = 0x00000100, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x110 + 0x200 * (ch), \ - .mask = 0x00000001, \ - .data = 0x00000001, \ - } +#define UNIPHIER_MIO_CLK_SD_GATE(id, ch) \ + UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 8) -#define UNIPHIER_MIO_CLK_RATE_SD(ch, idx) \ - { \ - .index = (idx), \ - .reg = 0x30 + 0x200 * (ch), \ - .mask = 0x00031300, \ - .data = 0x00000000, \ - .rate = 44444444, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x30 + 0x200 * (ch), \ - .mask = 0x00031300, \ - .data = 0x00010000, \ - .rate = 33333333, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x30 + 0x200 * (ch), \ - .mask = 0x00031300, \ - .data = 0x00020000, \ - .rate = 50000000, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x30 + 0x200 * (ch), \ - .mask = 0x00031300, \ - .data = 0x00020000, \ - .rate = 66666666, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x30 + 0x200 * (ch), \ - .mask = 0x00031300, \ - .data = 0x00001000, \ - .rate = 100000000, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x30 + 0x200 * (ch), \ - .mask = 0x00031300, \ - .data = 0x00001100, \ - .rate = 40000000, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x30 + 0x200 * (ch), \ - .mask = 0x00031300, \ - .data = 0x00001200, \ - .rate = 25000000, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x30 + 0x200 * (ch), \ - .mask = 0x00031300, \ - .data = 0x00001300, \ - .rate = 22222222, \ - } +#define UNIPHIER_MIO_CLK_USB2(id, ch) \ + UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 28) -#define UNIPHIER_MIO_CLK_GATE_USB(ch, idx) \ - { \ - .index = (idx), \ - .reg = 0x20 + 0x200 * (ch), \ - .mask = 0x30000000, \ - .data = 0x30000000, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x110 + 0x200 * (ch), \ - .mask = 0x01000000, \ - .data = 0x01000000, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x114 + 0x200 * (ch), \ - .mask = 0x00000001, \ - .data = 0x00000001, \ - } +#define UNIPHIER_MIO_CLK_USB2_PHY(id, ch) \ + UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 29) + +#define UNIPHIER_MIO_CLK_DMAC(id) \ + UNIPHIER_CLK_GATE((id), 0x20, 25) -#define UNIPHIER_MIO_CLK_GATE_DMAC(idx) \ - { \ - .index = (idx), \ - .reg = 0x20, \ - .mask = 0x02000000, \ - .data = 0x02000000, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x110, \ - .mask = 0x00020000, \ - .data = 0x00020000, \ +#define UNIPHIER_MIO_CLK_SD_MUX(_id, ch) \ + { \ + .id = (_id), \ + .nr_muxs = 8, \ + .reg = 0x30 + 0x200 * (ch), \ + .masks = { \ + 0x00031000, \ + 0x00031000, \ + 0x00031000, \ + 0x00031000, \ + 0x00001300, \ + 0x00001300, \ + 0x00001300, \ + 0x00001300, \ + }, \ + .vals = { \ + 0x00000000, \ + 0x00010000, \ + 0x00020000, \ + 0x00030000, \ + 0x00001000, \ + 0x00001100, \ + 0x00001200, \ + 0x00001300, \ + }, \ + .rates = { \ + 44444444, \ + 33333333, \ + 50000000, \ + 66666666, \ + 100000000, \ + 40000000, \ + 25000000, \ + 22222222, \ + }, \ } static const struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = { - UNIPHIER_MIO_CLK_GATE_SD(0, 0), - UNIPHIER_MIO_CLK_GATE_SD(1, 1), - UNIPHIER_MIO_CLK_GATE_SD(2, 2), /* for PH1-Pro4 only */ - UNIPHIER_MIO_CLK_GATE_USB(0, 3), - UNIPHIER_MIO_CLK_GATE_USB(1, 4), - UNIPHIER_MIO_CLK_GATE_USB(2, 5), - UNIPHIER_MIO_CLK_GATE_DMAC(6), - UNIPHIER_MIO_CLK_GATE_USB(3, 7), /* for PH1-sLD3 only */ + UNIPHIER_MIO_CLK_SD_GATE(0, 0), + UNIPHIER_MIO_CLK_SD_GATE(1, 1), + UNIPHIER_MIO_CLK_SD_GATE(2, 2), /* for PH1-Pro4 only */ + UNIPHIER_MIO_CLK_DMAC(7), + UNIPHIER_MIO_CLK_USB2(8, 0), + UNIPHIER_MIO_CLK_USB2(9, 1), + UNIPHIER_MIO_CLK_USB2(10, 2), + UNIPHIER_MIO_CLK_USB2(11, 3), /* for PH1-sLD3 only */ + UNIPHIER_MIO_CLK_USB2_PHY(12, 0), + UNIPHIER_MIO_CLK_USB2_PHY(13, 1), + UNIPHIER_MIO_CLK_USB2_PHY(14, 2), + UNIPHIER_MIO_CLK_USB2_PHY(15, 3), /* for PH1-sLD3 only */ + UNIPHIER_CLK_END }; -static const struct uniphier_clk_rate_data uniphier_mio_clk_rate[] = { - UNIPHIER_MIO_CLK_RATE_SD(0, 0), - UNIPHIER_MIO_CLK_RATE_SD(1, 1), - UNIPHIER_MIO_CLK_RATE_SD(2, 2), /* for PH1-Pro4 only */ +static const struct uniphier_clk_mux_data uniphier_mio_clk_mux[] = { + UNIPHIER_MIO_CLK_SD_MUX(0, 0), + UNIPHIER_MIO_CLK_SD_MUX(1, 1), + UNIPHIER_MIO_CLK_SD_MUX(2, 2), /* for PH1-Pro4 only */ + UNIPHIER_CLK_END }; -const struct uniphier_clk_soc_data uniphier_mio_clk_data = { +const struct uniphier_clk_data uniphier_mio_clk_data = { .gate = uniphier_mio_clk_gate, - .nr_gate = ARRAY_SIZE(uniphier_mio_clk_gate), - .rate = uniphier_mio_clk_rate, - .nr_rate = ARRAY_SIZE(uniphier_mio_clk_rate), + .mux = uniphier_mio_clk_mux, }; diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h index 0b60337205e..f9a560ee73d 100644 --- a/drivers/clk/uniphier/clk-uniphier.h +++ b/drivers/clk/uniphier/clk-uniphier.h @@ -10,36 +10,46 @@ #include +#define UNIPHIER_CLK_MAX_NR_MUXS 8 + struct uniphier_clk_gate_data { - int index; + unsigned int id; unsigned int reg; - u32 mask; - u32 data; + unsigned int bit; }; -struct uniphier_clk_rate_data { - int index; +struct uniphier_clk_mux_data { + unsigned int id; + unsigned int nr_muxs; unsigned int reg; -#define UNIPHIER_CLK_RATE_IS_FIXED UINT_MAX - u32 mask; - u32 data; - unsigned long rate; + unsigned int masks[UNIPHIER_CLK_MAX_NR_MUXS]; + unsigned int vals[UNIPHIER_CLK_MAX_NR_MUXS]; + unsigned long rates[UNIPHIER_CLK_MAX_NR_MUXS]; }; -struct uniphier_clk_soc_data { +struct uniphier_clk_data { const struct uniphier_clk_gate_data *gate; - unsigned int nr_gate; - const struct uniphier_clk_rate_data *rate; - unsigned int nr_rate; + const struct uniphier_clk_mux_data *mux; }; -#define UNIPHIER_CLK_FIXED_RATE(i, f) \ +#define UNIPHIER_CLK_ID_END (unsigned int)(-1) + +#define UNIPHIER_CLK_END \ + { .id = UNIPHIER_CLK_ID_END } + +#define UNIPHIER_CLK_GATE(_id, _reg, _bit) \ + { \ + .id = (_id), \ + .reg = (_reg), \ + .bit = (_bit), \ + } + +#define UNIPHIER_CLK_FIXED_RATE(_id, _rate) \ { \ - .index = i, \ - .reg = UNIPHIER_CLK_RATE_IS_FIXED, \ - .rate = f, \ + .id = (_id), \ + .rates = {(_reg),}, \ } -extern const struct uniphier_clk_soc_data uniphier_mio_clk_data; +extern const struct uniphier_clk_data uniphier_mio_clk_data; #endif /* __CLK_UNIPHIER_H__ */ -- cgit v1.3.1 From 52159d27ffe6b2a1a7e874cb2fda5aadbd4f03e5 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 7 Oct 2016 16:43:00 +0900 Subject: ARM: dts: uniphier: sync DT with latest Linux Signed-off-by: Masahiro Yamada --- arch/arm/dts/Makefile | 24 +- arch/arm/dts/uniphier-common32.dtsi | 8 +- arch/arm/dts/uniphier-ld11-ref.dts | 77 +++++ arch/arm/dts/uniphier-ld11.dtsi | 323 ++++++++++++++++++ arch/arm/dts/uniphier-ld20-ref.dts | 65 ++++ arch/arm/dts/uniphier-ld20.dtsi | 324 ++++++++++++++++++ arch/arm/dts/uniphier-ld4-ref.dts | 79 +++++ arch/arm/dts/uniphier-ld4.dtsi | 337 +++++++++++++++++++ arch/arm/dts/uniphier-ld6b-ref.dts | 81 +++++ arch/arm/dts/uniphier-ld6b.dtsi | 32 ++ arch/arm/dts/uniphier-ph1-ld11-ref.dts | 76 ----- arch/arm/dts/uniphier-ph1-ld11.dtsi | 317 ------------------ arch/arm/dts/uniphier-ph1-ld20-ref.dts | 64 ---- arch/arm/dts/uniphier-ph1-ld20.dtsi | 321 ------------------ arch/arm/dts/uniphier-ph1-ld4-ref.dts | 78 ----- arch/arm/dts/uniphier-ph1-ld4.dtsi | 325 ------------------ arch/arm/dts/uniphier-ph1-ld6b-ref.dts | 80 ----- arch/arm/dts/uniphier-ph1-ld6b.dtsi | 31 -- arch/arm/dts/uniphier-ph1-pro4-ace.dts | 99 ------ arch/arm/dts/uniphier-ph1-pro4-ref.dts | 89 ----- arch/arm/dts/uniphier-ph1-pro4-sanji.dts | 106 ------ arch/arm/dts/uniphier-ph1-pro4.dtsi | 473 -------------------------- arch/arm/dts/uniphier-ph1-pro5-4kbox.dts | 65 ---- arch/arm/dts/uniphier-ph1-pro5.dtsi | 446 ------------------------ arch/arm/dts/uniphier-ph1-sld3-ref.dts | 99 ------ arch/arm/dts/uniphier-ph1-sld3.dtsi | 416 ----------------------- arch/arm/dts/uniphier-ph1-sld8-ref.dts | 82 ----- arch/arm/dts/uniphier-ph1-sld8.dtsi | 325 ------------------ arch/arm/dts/uniphier-pro4-ace.dts | 100 ++++++ arch/arm/dts/uniphier-pro4-ref.dts | 90 +++++ arch/arm/dts/uniphier-pro4-sanji.dts | 107 ++++++ arch/arm/dts/uniphier-pro4.dtsi | 484 +++++++++++++++++++++++++++ arch/arm/dts/uniphier-pro5-4kbox.dts | 66 ++++ arch/arm/dts/uniphier-pro5.dtsi | 452 +++++++++++++++++++++++++ arch/arm/dts/uniphier-proxstream2-gentil.dts | 86 ----- arch/arm/dts/uniphier-proxstream2-vodka.dts | 71 ---- arch/arm/dts/uniphier-proxstream2.dtsi | 450 ------------------------- arch/arm/dts/uniphier-pxs2-gentil.dts | 88 +++++ arch/arm/dts/uniphier-pxs2-vodka.dts | 72 ++++ arch/arm/dts/uniphier-pxs2.dtsi | 458 +++++++++++++++++++++++++ arch/arm/dts/uniphier-sld3-ref.dts | 100 ++++++ arch/arm/dts/uniphier-sld3.dtsi | 448 +++++++++++++++++++++++++ arch/arm/dts/uniphier-sld8-ref.dts | 83 +++++ arch/arm/dts/uniphier-sld8.dtsi | 337 +++++++++++++++++++ arch/arm/mach-uniphier/boards.c | 26 +- configs/uniphier_ld11_defconfig | 2 +- configs/uniphier_ld20_defconfig | 2 +- configs/uniphier_ld4_sld8_defconfig | 2 +- configs/uniphier_pro4_defconfig | 2 +- configs/uniphier_pxs2_ld6b_defconfig | 2 +- configs/uniphier_sld3_defconfig | 2 +- doc/README.uniphier | 32 +- 52 files changed, 4257 insertions(+), 4147 deletions(-) create mode 100644 arch/arm/dts/uniphier-ld11-ref.dts create mode 100644 arch/arm/dts/uniphier-ld11.dtsi create mode 100644 arch/arm/dts/uniphier-ld20-ref.dts create mode 100644 arch/arm/dts/uniphier-ld20.dtsi create mode 100644 arch/arm/dts/uniphier-ld4-ref.dts create mode 100644 arch/arm/dts/uniphier-ld4.dtsi create mode 100644 arch/arm/dts/uniphier-ld6b-ref.dts create mode 100644 arch/arm/dts/uniphier-ld6b.dtsi delete mode 100644 arch/arm/dts/uniphier-ph1-ld11-ref.dts delete mode 100644 arch/arm/dts/uniphier-ph1-ld11.dtsi delete mode 100644 arch/arm/dts/uniphier-ph1-ld20-ref.dts delete mode 100644 arch/arm/dts/uniphier-ph1-ld20.dtsi delete mode 100644 arch/arm/dts/uniphier-ph1-ld4-ref.dts delete mode 100644 arch/arm/dts/uniphier-ph1-ld4.dtsi delete mode 100644 arch/arm/dts/uniphier-ph1-ld6b-ref.dts delete mode 100644 arch/arm/dts/uniphier-ph1-ld6b.dtsi delete mode 100644 arch/arm/dts/uniphier-ph1-pro4-ace.dts delete mode 100644 arch/arm/dts/uniphier-ph1-pro4-ref.dts delete mode 100644 arch/arm/dts/uniphier-ph1-pro4-sanji.dts delete mode 100644 arch/arm/dts/uniphier-ph1-pro4.dtsi delete mode 100644 arch/arm/dts/uniphier-ph1-pro5-4kbox.dts delete mode 100644 arch/arm/dts/uniphier-ph1-pro5.dtsi delete mode 100644 arch/arm/dts/uniphier-ph1-sld3-ref.dts delete mode 100644 arch/arm/dts/uniphier-ph1-sld3.dtsi delete mode 100644 arch/arm/dts/uniphier-ph1-sld8-ref.dts delete mode 100644 arch/arm/dts/uniphier-ph1-sld8.dtsi create mode 100644 arch/arm/dts/uniphier-pro4-ace.dts create mode 100644 arch/arm/dts/uniphier-pro4-ref.dts create mode 100644 arch/arm/dts/uniphier-pro4-sanji.dts create mode 100644 arch/arm/dts/uniphier-pro4.dtsi create mode 100644 arch/arm/dts/uniphier-pro5-4kbox.dts create mode 100644 arch/arm/dts/uniphier-pro5.dtsi delete mode 100644 arch/arm/dts/uniphier-proxstream2-gentil.dts delete mode 100644 arch/arm/dts/uniphier-proxstream2-vodka.dts delete mode 100644 arch/arm/dts/uniphier-proxstream2.dtsi create mode 100644 arch/arm/dts/uniphier-pxs2-gentil.dts create mode 100644 arch/arm/dts/uniphier-pxs2-vodka.dts create mode 100644 arch/arm/dts/uniphier-pxs2.dtsi create mode 100644 arch/arm/dts/uniphier-sld3-ref.dts create mode 100644 arch/arm/dts/uniphier-sld3.dtsi create mode 100644 arch/arm/dts/uniphier-sld8-ref.dts create mode 100644 arch/arm/dts/uniphier-sld8.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8458f6bed85..8dbaea0f8d4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -79,18 +79,18 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-xp-theadorable.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ - uniphier-ph1-ld11-ref.dtb \ - uniphier-ph1-ld20-ref.dtb \ - uniphier-ph1-ld4-ref.dtb \ - uniphier-ph1-ld6b-ref.dtb \ - uniphier-ph1-pro4-ace.dtb \ - uniphier-ph1-pro4-ref.dtb \ - uniphier-ph1-pro4-sanji.dtb \ - uniphier-ph1-pro5-4kbox.dtb \ - uniphier-ph1-sld3-ref.dtb \ - uniphier-ph1-sld8-ref.dtb \ - uniphier-proxstream2-gentil.dtb \ - uniphier-proxstream2-vodka.dtb + uniphier-ld11-ref.dtb \ + uniphier-ld20-ref.dtb \ + uniphier-ld4-ref.dtb \ + uniphier-ld6b-ref.dtb \ + uniphier-pro4-ace.dtb \ + uniphier-pro4-ref.dtb \ + uniphier-pro4-sanji.dtb \ + uniphier-pro5-4kbox.dtb \ + uniphier-pxs2-gentil.dtb \ + uniphier-pxs2-vodka.dtb \ + uniphier-sld3-ref.dtb \ + uniphier-sld8-ref.dtb dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-zc706.dtb \ zynq-zed.dtb \ diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi index e4410339eb6..f87e3208309 100644 --- a/arch/arm/dts/uniphier-common32.dtsi +++ b/arch/arm/dts/uniphier-common32.dtsi @@ -1,7 +1,8 @@ /* * Device Tree Source commonly used by UniPhier ARM SoCs * - * Copyright (C) 2015 Masahiro Yamada + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada * * SPDX-License-Identifier: GPL-2.0+ X11 */ @@ -9,6 +10,11 @@ /include/ "skeleton.dtsi" / { + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { refclk: ref { #clock-cells = <0>; diff --git a/arch/arm/dts/uniphier-ld11-ref.dts b/arch/arm/dts/uniphier-ld11-ref.dts new file mode 100644 index 00000000000..ea111989768 --- /dev/null +++ b/arch/arm/dts/uniphier-ld11-ref.dts @@ -0,0 +1,77 @@ +/* + * Device Tree Source for UniPhier LD11 Reference Board + * + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; +/include/ "uniphier-ld11.dtsi" +/include/ "uniphier-ref-daughter.dtsi" +/include/ "uniphier-support-card.dtsi" + +/ { + model = "UniPhier LD11 Reference Board"; + compatible = "socionext,uniphier-ld11-ref", "socionext,uniphier-ld11"; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + }; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +ðsc { + interrupts = <0 48 4>; +}; + +&serial0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +/* for U-Boot only */ +&serial0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_system_bus { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi new file mode 100644 index 00000000000..a95cb6e97bd --- /dev/null +++ b/arch/arm/dts/uniphier-ld11.dtsi @@ -0,0 +1,323 @@ +/* + * Device Tree Source for UniPhier LD11 SoC + * + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ + +/ { + compatible = "socionext,uniphier-ld11"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0 0x000>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x80000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0 0x001>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x80000000>; + }; + }; + + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + i2c_clk: i2c_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 4>, + <1 14 4>, + <1 11 4>, + <1 10 4>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + u-boot,dm-pre-reloc; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + clock-frequency = <58820000>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + clock-frequency = <58820000>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + clock-frequency = <58820000>; + }; + + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 177 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + clock-frequency = <58820000>; + }; + + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c4: i2c@58784000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58784000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 45 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; + + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-ld11-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-ld11-peri-reset"; + #reset-cells = <1>; + }; + }; + + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 243 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 244 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; + }; + + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 245 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, + <&mio_rst 14>; + }; + + mioctrl@5b3e0000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; + reg = <0x5b3e0000 0x800>; + + mio_clk: clock { + compatible = "socionext,uniphier-ld11-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-ld11-mio-reset"; + #reset-cells = <1>; + resets = <&sys_rst 7>; + }; + }; + + soc-glue@5f800000 { + compatible = "socionext,uniphier-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + u-boot,dm-pre-reloc; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-ld11-pinctrl"; + u-boot,dm-pre-reloc; + }; + }; + + aidet@5fc20000 { + compatible = "simple-mfd", "syscon"; + reg = <0x5fc20000 0x200>; + }; + + gic: interrupt-controller@5fe00000 { + compatible = "arm,gic-v3"; + reg = <0x5fe00000 0x10000>, /* GICD */ + <0x5fe40000 0x80000>; /* GICR */ + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <1 9 4>; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-ld11-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x4000>; + + sys_clk: clock { + compatible = "socionext,uniphier-ld11-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-ld11-reset"; + #reset-cells = <1>; + }; + }; + }; +}; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/dts/uniphier-ld20-ref.dts b/arch/arm/dts/uniphier-ld20-ref.dts new file mode 100644 index 00000000000..044e0007492 --- /dev/null +++ b/arch/arm/dts/uniphier-ld20-ref.dts @@ -0,0 +1,65 @@ +/* + * Device Tree Source for UniPhier LD20 Reference Board + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; +/include/ "uniphier-ld20.dtsi" +/include/ "uniphier-ref-daughter.dtsi" +/include/ "uniphier-support-card.dtsi" + +/ { + model = "UniPhier LD20 Reference Board"; + compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20"; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + }; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0xc0000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +ðsc { + interrupts = <0 48 4>; +}; + +&serial0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +/* for U-Boot only */ +&serial0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_system_bus { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi new file mode 100644 index 00000000000..29a84aeccdd --- /dev/null +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -0,0 +1,324 @@ +/* + * Device Tree Source for UniPhier LD20 SoC + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ + +/ { + compatible = "socionext,uniphier-ld20"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu2>; + }; + core1 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x000>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x80000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0 0x001>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x80000000>; + }; + + cpu2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x80000000>; + }; + + cpu3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0 0x101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x80000000>; + }; + }; + + clocks { + refclk: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + i2c_clk: i2c_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 4>, + <1 14 4>, + <1 11 4>, + <1 10 4>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + u-boot,dm-pre-reloc; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clocks = <&peri_clk 0>; + clock-frequency = <58820000>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clocks = <&peri_clk 1>; + clock-frequency = <58820000>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clocks = <&peri_clk 2>; + clock-frequency = <58820000>; + }; + + serial3: serial@54006b00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006b00 0x40>; + interrupts = <0 177 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + clocks = <&peri_clk 3>; + clock-frequency = <58820000>; + }; + + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c4: i2c@58784000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58784000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 45 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_system_bus>; + }; + + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + mioctrl@59810000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + mio_clk: clock { + compatible = "socionext,uniphier-ld20-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-ld20-mio-reset"; + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + compatible = "socionext,uniphier-ld20-peri-clock"; + #clock-cells = <1>; + }; + + peri_rst: reset { + compatible = "socionext,uniphier-ld20-peri-reset"; + #reset-cells = <1>; + }; + }; + + sd: sdhc@5a400000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a400000 0x800>; + interrupts = <0 76 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd>; + clocks = <&mio_clk 0>; + reset-names = "host"; + resets = <&mio_rst 0>; + bus-width = <4>; + }; + + soc-glue@5f800000 { + compatible = "socionext,uniphier-soc-glue", + "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + u-boot,dm-pre-reloc; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-ld20-pinctrl"; + u-boot,dm-pre-reloc; + }; + }; + + aidet@5fc20000 { + compatible = "simple-mfd", "syscon"; + reg = <0x5fc20000 0x200>; + }; + + gic: interrupt-controller@5fe00000 { + compatible = "arm,gic-v3"; + reg = <0x5fe00000 0x10000>, /* GICD */ + <0x5fe80000 0x80000>; /* GICR */ + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <1 9 4>; + }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x4000>; + + sys_clk: clock { + compatible = "socionext,uniphier-ld20-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-ld20-reset"; + #reset-cells = <1>; + }; + }; + }; +}; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/dts/uniphier-ld4-ref.dts b/arch/arm/dts/uniphier-ld4-ref.dts new file mode 100644 index 00000000000..0f4bd9bda22 --- /dev/null +++ b/arch/arm/dts/uniphier-ld4-ref.dts @@ -0,0 +1,79 @@ +/* + * Device Tree Source for UniPhier LD4 Reference Board + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; +/include/ "uniphier-ld4.dtsi" +/include/ "uniphier-ref-daughter.dtsi" +/include/ "uniphier-support-card.dtsi" + +/ { + model = "UniPhier LD4 Reference Board"; + compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; +}; + +ðsc { + interrupts = <0 49 4>; +}; + +&serial0 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&sd { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* for U-Boot only */ +&serial0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi new file mode 100644 index 00000000000..9f555df652d --- /dev/null +++ b/arch/arm/dts/uniphier-ld4.dtsi @@ -0,0 +1,337 @@ +/* + * Device Tree Source for UniPhier LD4 SoC + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/include/ "uniphier-common32.dtsi" + +/ { + compatible = "socionext,uniphier-ld4"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + }; + + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + iobus_clk: iobus_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + }; +}; + +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(512 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; + + port0x: gpio@55000008 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000008 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port1x: gpio@55000010 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000010 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port2x: gpio@55000018 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000018 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port3x: gpio@55000020 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000020 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port4: gpio@55000028 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000028 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port5x: gpio@55000030 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000030 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port6x: gpio@55000038 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000038 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port7x: gpio@55000040 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000040 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port8x: gpio@55000048 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000048 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port9x: gpio@55000050 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000050 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port10x: gpio@55000058 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000058 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port11x: gpio@55000060 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000060 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port12x: gpio@55000068 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000068 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port13x: gpio@55000070 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000070 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port14x: gpio@55000078 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000078 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port16x: gpio@55000088 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000088 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&iobus_clk>; + clock-frequency = <400000>; + }; + + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + sd: sdhc@5a400000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a400000 0x200>; + interrupts = <0 76 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_1v8>; + clocks = <&mio_clk 0>; + reset-names = "host", "bridge"; + resets = <&mio_rst 0>, <&mio_rst 3>; + bus-width = <4>; + }; + + emmc: sdhc@5a500000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a500000 0x200>; + interrupts = <0 78 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_emmc>; + pinctrl-1 = <&pinctrl_emmc_1v8>; + clocks = <&mio_clk 1>; + reset-names = "host", "bridge", "hw-reset"; + resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; + bus-width = <8>; + non-removable; + }; + + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; + }; + + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 82 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, + <&mio_rst 14>; + }; + + aidet@61830000 { + compatible = "simple-mfd", "syscon"; + reg = <0x61830000 0x200>; + }; +}; + +&refclk { + clock-frequency = <24576000>; +}; + +&serial0 { + clock-frequency = <36864000>; +}; + +&serial1 { + clock-frequency = <36864000>; +}; + +&serial2 { + clock-frequency = <36864000>; +}; + +&serial3 { + interrupts = <0 29 4>; + clock-frequency = <36864000>; +}; + +&mio_clk { + compatible = "socionext,uniphier-ld4-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-ld4-mio-reset"; +}; + +&peri_clk { + compatible = "socionext,uniphier-ld4-peri-clock"; +}; + +&peri_rst { + compatible = "socionext,uniphier-ld4-peri-reset"; +}; + +&pinctrl { + compatible = "socionext,uniphier-ld4-pinctrl"; +}; + +&sys_clk { + compatible = "socionext,uniphier-ld4-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-ld4-reset"; +}; diff --git a/arch/arm/dts/uniphier-ld6b-ref.dts b/arch/arm/dts/uniphier-ld6b-ref.dts new file mode 100644 index 00000000000..4da3c63f736 --- /dev/null +++ b/arch/arm/dts/uniphier-ld6b-ref.dts @@ -0,0 +1,81 @@ +/* + * Device Tree Source for UniPhier LD6b Reference Board + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "uniphier-ld6b.dtsi" +/include/ "uniphier-ref-daughter.dtsi" +/include/ "uniphier-support-card.dtsi" + +/ { + model = "UniPhier LD6b Reference Board"; + compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; +}; + +ðsc { + interrupts = <0 52 4>; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&sd { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* for U-Boot only */ +&serial0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-ld6b.dtsi b/arch/arm/dts/uniphier-ld6b.dtsi new file mode 100644 index 00000000000..9870047f458 --- /dev/null +++ b/arch/arm/dts/uniphier-ld6b.dtsi @@ -0,0 +1,32 @@ +/* + * Device Tree Source for UniPhier LD6b SoC + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/* + * LD6b consists of two silicon dies: D-chip and A-chip. + * The D-chip (digital chip) is the same as the PXs2 die. + * Reuse the PXs2 device tree with some properties overridden. + */ +/include/ "uniphier-pxs2.dtsi" + +/ { + compatible = "socionext,uniphier-ld6b"; +}; + +/* UART3 unavailable: the pads are not wired to the package balls */ +&serial3 { + status = "disabled"; +}; + +/* + * LD6b and PXs2 have completely different packages, + * which makes the pinctrl driver unshareable. + */ +&pinctrl { + compatible = "socionext,uniphier-ld6b-pinctrl"; +}; diff --git a/arch/arm/dts/uniphier-ph1-ld11-ref.dts b/arch/arm/dts/uniphier-ph1-ld11-ref.dts deleted file mode 100644 index ca310267380..00000000000 --- a/arch/arm/dts/uniphier-ph1-ld11-ref.dts +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-LD11 Reference Board - * - * Copyright (C) 2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ X11 - */ - -/dts-v1/; -/include/ "uniphier-ph1-ld11.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier PH1-LD11 Reference Board"; - compatible = "socionext,ph1-ld11-ref", "socionext,ph1-ld11"; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - }; - - memory { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -ðsc { - interrupts = <0 48 4>; -}; - -&serial0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_system_bus { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-ph1-ld11.dtsi b/arch/arm/dts/uniphier-ph1-ld11.dtsi deleted file mode 100644 index 0bdbbddd9dd..00000000000 --- a/arch/arm/dts/uniphier-ph1-ld11.dtsi +++ /dev/null @@ -1,317 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-LD11 SoC - * - * Copyright (C) 2016 Socionext Inc. - * Author: Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ X11 - */ - -/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ - -/ { - compatible = "socionext,ph1-ld11"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; - reg = <0 0x000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x80000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; - reg = <0 0x001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x80000000>; - }; - }; - - clocks { - refclk: ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - i2c_clk: i2c_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 4>, - <1 14 4>, - <1 11 4>, - <1 10 4>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - u-boot,dm-pre-reloc; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - clock-frequency = <58820000>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - clock-frequency = <58820000>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - clock-frequency = <58820000>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - clock-frequency = <58820000>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c4: i2c@58784000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58784000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59800000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - perictrl@59820000 { - compatible = "socionext,uniphier-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock { - compatible = "socionext,uniphier-ld11-peri-clock"; - #clock-cells = <1>; - }; - - peri_rst: reset { - compatible = "socionext,uniphier-ld11-peri-reset"; - #reset-cells = <1>; - }; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 243 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio_clk 3>, <&mio_clk 6>; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 244 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio_clk 4>, <&mio_clk 6>; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 245 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 5>, <&mio_clk 6>; - }; - - mioctrl@5b3e0000 { - compatible = "socionext,uniphier-mioctrl", - "simple-mfd", "syscon"; - reg = <0x5b3e0000 0x800>; - - mio_clk: clock { - compatible = "socionext,uniphier-ld11-mio-clock"; - #clock-cells = <1>; - }; - - mio_rst: reset { - compatible = "socionext,uniphier-ld11-mio-reset"; - #reset-cells = <1>; - resets = <&sys_rst 7>; - }; - }; - - soc-glue@5f800000 { - compatible = "socionext,uniphier-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - u-boot,dm-pre-reloc; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-ld11-pinctrl"; - u-boot,dm-pre-reloc; - }; - }; - - aidet@5fc20000 { - compatible = "simple-mfd", "syscon"; - reg = <0x5fc20000 0x200>; - }; - - gic: interrupt-controller@5fe00000 { - compatible = "arm,gic-v3"; - reg = <0x5fe00000 0x10000>, /* GICD */ - <0x5fe40000 0x80000>; /* GICR */ - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <1 9 4>; - }; - - sysctrl@61840000 { - compatible = "socionext,uniphier-ld11-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; - - sys_clk: clock { - compatible = "socionext,uniphier-ld11-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset { - compatible = "socionext,uniphier-ld11-reset"; - #reset-cells = <1>; - }; - }; - }; -}; - -/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/dts/uniphier-ph1-ld20-ref.dts b/arch/arm/dts/uniphier-ph1-ld20-ref.dts deleted file mode 100644 index e4e8d767490..00000000000 --- a/arch/arm/dts/uniphier-ph1-ld20-ref.dts +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-LD20 Reference Board - * - * Copyright (C) 2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ X11 - */ - -/dts-v1/; -/include/ "uniphier-ph1-ld20.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier PH1-LD20 Reference Board"; - compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20"; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - }; - - memory { - device_type = "memory"; - reg = <0 0x80000000 0 0xc0000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -ðsc { - interrupts = <0 48 4>; -}; - -&serial0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_system_bus { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-ph1-ld20.dtsi b/arch/arm/dts/uniphier-ph1-ld20.dtsi deleted file mode 100644 index 7f97f8816a4..00000000000 --- a/arch/arm/dts/uniphier-ph1-ld20.dtsi +++ /dev/null @@ -1,321 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-LD20 SoC - * - * Copyright (C) 2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ X11 - */ - -/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ - -/ { - compatible = "socionext,ph1-ld20"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu2>; - }; - core1 { - cpu = <&cpu3>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0 0x000>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x80000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; - reg = <0 0x001>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x80000000>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; - reg = <0 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x80000000>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; - reg = <0 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0x80000000>; - }; - }; - - clocks { - refclk: ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - i2c_clk: i2c_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 4>, - <1 14 4>, - <1 11 4>, - <1 10 4>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - u-boot,dm-pre-reloc; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - clock-frequency = <58820000>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - clock-frequency = <58820000>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - clock-frequency = <58820000>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - clock-frequency = <58820000>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c4: i2c@58784000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58784000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59800000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - mioctrl@59810000 { - compatible = "socionext,uniphier-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - mio_clk: clock { - compatible = "socionext,uniphier-ld20-mio-clock"; - #clock-cells = <1>; - }; - - mio_rst: reset { - compatible = "socionext,uniphier-ld20-mio-reset"; - #reset-cells = <1>; - }; - }; - - perictrl@59820000 { - compatible = "socionext,uniphier-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock { - compatible = "socionext,uniphier-ld20-peri-clock"; - #clock-cells = <1>; - }; - - peri_rst: reset { - compatible = "socionext,uniphier-ld20-peri-reset"; - #reset-cells = <1>; - }; - }; - - sd: sdhc@5a400000 { - compatible = "socionext,uniphier-sdhc"; - status = "disabled"; - reg = <0x5a400000 0x800>; - interrupts = <0 76 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd>; - clocks = <&mio_clk 0>; - bus-width = <4>; - }; - - soc-glue@5f800000 { - compatible = "socionext,uniphier-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - u-boot,dm-pre-reloc; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-ld20-pinctrl"; - u-boot,dm-pre-reloc; - }; - }; - - aidet@5fc20000 { - compatible = "simple-mfd", "syscon"; - reg = <0x5fc20000 0x200>; - }; - - gic: interrupt-controller@5fe00000 { - compatible = "arm,gic-v3"; - reg = <0x5fe00000 0x10000>, /* GICD */ - <0x5fe80000 0x80000>; /* GICR */ - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <1 9 4>; - }; - - sysctrl@61840000 { - compatible = "socionext,uniphier-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; - - sys_clk: clock { - compatible = "socionext,uniphier-ld20-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset { - compatible = "socionext,uniphier-ld20-reset"; - #reset-cells = <1>; - }; - }; - }; -}; - -/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts deleted file mode 100644 index 36de7e3a0f9..00000000000 --- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-LD4 Reference Board - * - * Copyright (C) 2014-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ X11 - */ - -/dts-v1/; -/include/ "uniphier-ph1-ld4.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier PH1-LD4 Reference Board"; - compatible = "socionext,ph1-ld4-ref", "socionext,ph1-ld4"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - }; -}; - -ðsc { - interrupts = <0 49 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi deleted file mode 100644 index e4884b9516c..00000000000 --- a/arch/arm/dts/uniphier-ph1-ld4.dtsi +++ /dev/null @@ -1,325 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-LD4 SoC - * - * Copyright (C) 2014-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ X11 - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,ph1-ld4"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - iobus_clk: iobus_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(512 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - port0x: gpio@55000008 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000008 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port1x: gpio@55000010 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000010 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port2x: gpio@55000018 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000018 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port3x: gpio@55000020 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000020 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port4: gpio@55000028 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000028 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port5x: gpio@55000030 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000030 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port6x: gpio@55000038 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000038 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port7x: gpio@55000040 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000040 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port8x: gpio@55000048 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000048 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port9x: gpio@55000050 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000050 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port10x: gpio@55000058 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000058 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port11x: gpio@55000060 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000060 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port12x: gpio@55000068 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000068 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port13x: gpio@55000070 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000070 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port14x: gpio@55000078 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000078 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port16x: gpio@55000088 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000088 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&iobus_clk>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - sd: sdhc@5a400000 { - compatible = "socionext,uniphier-sdhc"; - status = "disabled"; - reg = <0x5a400000 0x200>; - interrupts = <0 76 4>; - pinctrl-names = "default", "1.8v"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_1v8>; - clocks = <&mio_clk 0>; - bus-width = <4>; - }; - - emmc: sdhc@5a500000 { - compatible = "socionext,uniphier-sdhc"; - status = "disabled"; - reg = <0x5a500000 0x200>; - interrupts = <0 78 4>; - pinctrl-names = "default", "1.8v"; - pinctrl-0 = <&pinctrl_emmc>; - pinctrl-1 = <&pinctrl_emmc_1v8>; - clocks = <&mio_clk 1>; - bus-width = <8>; - non-removable; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio_clk 3>, <&mio_clk 6>; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio_clk 4>, <&mio_clk 6>; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 5>, <&mio_clk 6>; - }; - - aidet@61830000 { - compatible = "simple-mfd", "syscon"; - reg = <0x61830000 0x200>; - }; -}; - -&refclk { - clock-frequency = <24576000>; -}; - -&serial0 { - clock-frequency = <36864000>; -}; - -&serial1 { - clock-frequency = <36864000>; -}; - -&serial2 { - clock-frequency = <36864000>; -}; - -&serial3 { - interrupts = <0 29 4>; - clock-frequency = <36864000>; -}; - -&mio_clk { - compatible = "socionext,uniphier-ld4-mio-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-ld4-mio-reset"; -}; - -&peri_clk { - compatible = "socionext,uniphier-ld4-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-ld4-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-ld4-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-ld4-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-ld4-reset"; -}; diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts deleted file mode 100644 index e29a6ea841f..00000000000 --- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-LD6b Reference Board - * - * Copyright (C) 2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/dts-v1/; -/include/ "uniphier-ph1-ld6b.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier PH1-LD6b Reference Board"; - compatible = "socionext,ph1-ld6b-ref", "socionext,ph1-ld6b"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -ðsc { - interrupts = <0 52 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-ph1-ld6b.dtsi b/arch/arm/dts/uniphier-ph1-ld6b.dtsi deleted file mode 100644 index e8110eefcec..00000000000 --- a/arch/arm/dts/uniphier-ph1-ld6b.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-LD6b SoC - * - * Copyright (C) 2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ X11 - */ - -/* - * PH1-LD6b consists of two silicon dies: D-chip and A-chip. - * The D-chip (digital chip) is the same as the ProXstream2 die. - * Reuse the ProXstream2 device tree with some properties overridden. - */ -/include/ "uniphier-proxstream2.dtsi" - -/ { - compatible = "socionext,ph1-ld6b"; -}; - -/* UART3 unavailable: the pads are not wired to the package balls */ -&serial3 { - status = "disabled"; -}; - -/* - * PH1-LD6b and ProXstream2 have completely different packages, - * which makes the pinctrl driver unshareable. - */ -&pinctrl { - compatible = "socionext,uniphier-ld6b-pinctrl"; -}; diff --git a/arch/arm/dts/uniphier-ph1-pro4-ace.dts b/arch/arm/dts/uniphier-ph1-pro4-ace.dts deleted file mode 100644 index d8740cc9d33..00000000000 --- a/arch/arm/dts/uniphier-ph1-pro4-ace.dts +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-Pro4 Ace Board - * - * Copyright (C) 2016 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ X11 - */ - -/dts-v1/; -/include/ "uniphier-ph1-pro4.dtsi" - -/ { - model = "UniPhier PH1-Pro4 Ace Board"; - compatible = "socionext,ph1-pro4-ace", "socionext,ph1-pro4"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom { - compatible = "24c64", "i2c-eeprom"; - reg = <0x54>; - u-boot,i2c-offset-len = <2>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts deleted file mode 100644 index 4a2de08e066..00000000000 --- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-Pro4 Reference Board - * - * Copyright (C) 2014-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ X11 - */ - -/dts-v1/; -/include/ "uniphier-ph1-pro4.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier PH1-Pro4 Reference Board"; - compatible = "socionext,ph1-pro4-ref", "socionext,ph1-pro4"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c5 = &i2c5; - i2c6 = &i2c6; - usb0 = &usb0; - }; -}; - -ðsc { - interrupts = <0 50 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -&sd1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts b/arch/arm/dts/uniphier-ph1-pro4-sanji.dts deleted file mode 100644 index 3f178d239ad..00000000000 --- a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-Pro4 Sanji Board - * - * Copyright (C) 2016 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ X11 - */ - -/dts-v1/; -/include/ "uniphier-ph1-pro4.dtsi" - -/ { - model = "UniPhier PH1-Pro4 Sanji Board"; - compatible = "socionext,ph1-pro4-sanji", "socionext,ph1-pro4"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom { - compatible = "24c64", "i2c-eeprom"; - reg = <0x54>; - u-boot,i2c-offset-len = <2>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&emmc { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&mio_clk { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_emmc { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi deleted file mode 100644 index 192ce841e13..00000000000 --- a/arch/arm/dts/uniphier-ph1-pro4.dtsi +++ /dev/null @@ -1,473 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-Pro4 SoC - * - * Copyright (C) 2014-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ X11 - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,ph1-pro4"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <73728000>; - }; - - i2c_clk: i2c_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(768 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - port0x: gpio@55000008 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000008 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port1x: gpio@55000010 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000010 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port2x: gpio@55000018 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000018 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port3x: gpio@55000020 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000020 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port4: gpio@55000028 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000028 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port5x: gpio@55000030 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000030 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port6x: gpio@55000038 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000038 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port7x: gpio@55000040 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000040 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port8x: gpio@55000048 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000048 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port9x: gpio@55000050 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000050 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port10x: gpio@55000058 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000058 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port11x: gpio@55000060 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000060 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port12x: gpio@55000068 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000068 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port13x: gpio@55000070 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000070 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port14x: gpio@55000078 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000078 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port17x: gpio@550000a0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000a0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port18x: gpio@550000a8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000a8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port19x: gpio@550000b0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000b0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port20x: gpio@550000b8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000b8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port21x: gpio@550000c0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000c0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port22x: gpio@550000c8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000c8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port23x: gpio@550000d0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000d0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port24x: gpio@550000d8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000d8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port25x: gpio@550000e0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000e0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port26x: gpio@550000e8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000e8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port27x: gpio@550000f0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000f0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port28x: gpio@550000f8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000f8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port29x: gpio@55000100 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000100 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port30x: gpio@55000108 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000108 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - /* i2c4 does not exist */ - - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - sd: sdhc@5a400000 { - compatible = "socionext,uniphier-sdhc"; - status = "disabled"; - reg = <0x5a400000 0x200>; - interrupts = <0 76 4>; - pinctrl-names = "default", "1.8v"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_1v8>; - clocks = <&mio_clk 0>; - bus-width = <4>; - }; - - emmc: sdhc@5a500000 { - compatible = "socionext,uniphier-sdhc"; - status = "disabled"; - reg = <0x5a500000 0x200>; - interrupts = <0 78 4>; - pinctrl-names = "default", "1.8v"; - pinctrl-0 = <&pinctrl_emmc>; - pinctrl-1 = <&pinctrl_emmc_1v8>; - clocks = <&mio_clk 1>; - bus-width = <8>; - non-removable; - }; - - sd1: sdhc@5a600000 { - compatible = "socionext,uniphier-sdhc"; - status = "disabled"; - reg = <0x5a600000 0x200>; - interrupts = <0 85 4>; - pinctrl-names = "default", "1.8v"; - pinctrl-0 = <&pinctrl_sd1>; - pinctrl-1 = <&pinctrl_sd1_1v8>; - clocks = <&mio_clk 2>; - bus-width = <4>; - }; - - usb2: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 3>, <&mio_clk 6>; - }; - - usb3: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - clocks = <&mio_clk 4>, <&mio_clk 6>; - }; - - aidet@5fc20000 { - compatible = "simple-mfd", "syscon"; - reg = <0x5fc20000 0x200>; - }; - - usb0: usb@65a00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; - status = "disabled"; - reg = <0x65a00000 0x100>; - interrupts = <0 134 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - }; - - usb1: usb@65c00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; - status = "disabled"; - reg = <0x65c00000 0x100>; - interrupts = <0 137 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - }; -}; - -&refclk { - clock-frequency = <25000000>; -}; - -&serial0 { - clock-frequency = <73728000>; -}; - -&serial1 { - clock-frequency = <73728000>; -}; - -&serial2 { - clock-frequency = <73728000>; -}; - -&serial3 { - clock-frequency = <73728000>; -}; - -&mio_clk { - compatible = "socionext,uniphier-pro4-mio-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-pro4-mio-reset"; -}; - -&peri_clk { - compatible = "socionext,uniphier-pro4-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-pro4-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-pro4-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-pro4-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-pro4-reset"; -}; diff --git a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts deleted file mode 100644 index 682b7958fa2..00000000000 --- a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-Pro5 4KBOX Board (EVB-Pro5-4KBOX-M-V0) - * - * Copyright (C) 2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/dts-v1/; -/include/ "uniphier-ph1-pro5.dtsi" - -/ { - model = "UniPhier PH1-Pro5 4KBOX Board"; - compatible = "socionext,ph1-pro5-4kbox", "socionext,ph1-pro5"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - chosen { - stdout-path = "serial1:115200n8"; - }; - - aliases { - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&emmc { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -/* for U-Boot only */ -&serial1 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart1 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi deleted file mode 100644 index 22a70b1a601..00000000000 --- a/arch/arm/dts/uniphier-ph1-pro5.dtsi +++ /dev/null @@ -1,446 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-Pro5 SoC - * - * Copyright (C) 2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ X11 - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,ph1-pro5"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - i2c_clk: i2c_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; - interrupts = <0 190 4>, <0 191 4>; - cache-unified; - cache-size = <(2 * 1024 * 1024)>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - next-level-cache = <&l3>; - }; - - l3: l3-cache@500c8000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(2 * 1024 * 1024)>; - cache-sets = <512>; - cache-line-size = <256>; - cache-level = <3>; - }; - - port0x: gpio@55000008 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000008 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port1x: gpio@55000010 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000010 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port2x: gpio@55000018 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000018 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port3x: gpio@55000020 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000020 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port4: gpio@55000028 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000028 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port5x: gpio@55000030 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000030 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port6x: gpio@55000038 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000038 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port7x: gpio@55000040 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000040 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port8x: gpio@55000048 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000048 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port9x: gpio@55000050 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000050 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port10x: gpio@55000058 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000058 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port11x: gpio@55000060 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000060 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port12x: gpio@55000068 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000068 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port13x: gpio@55000070 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000070 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port14x: gpio@55000078 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000078 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port17x: gpio@550000a0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000a0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port18x: gpio@550000a8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000a8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port19x: gpio@550000b0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000b0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port20x: gpio@550000b8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000b8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port21x: gpio@550000c0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000c0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port22x: gpio@550000c8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000c8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port23x: gpio@550000d0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000d0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port24x: gpio@550000d8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000d8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port25x: gpio@550000e0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000e0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port26x: gpio@550000e8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000e8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port27x: gpio@550000f0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000f0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port28x: gpio@550000f8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000f8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port29x: gpio@55000100 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000100 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port30x: gpio@55000108 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000108 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - /* i2c4 does not exist */ - - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - aidet@5fc20000 { - compatible = "simple-mfd", "syscon"; - reg = <0x5fc20000 0x200>; - }; - - emmc: sdhc@68400000 { - compatible = "socionext,uniphier-sdhc"; - status = "disabled"; - reg = <0x68400000 0x800>; - interrupts = <0 78 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - clocks = <&mio_clk 1>; - bus-width = <8>; - non-removable; - }; - - sd: sdhc@68800000 { - compatible = "socionext,uniphier-sdhc"; - status = "disabled"; - reg = <0x68800000 0x800>; - interrupts = <0 76 4>; - pinctrl-names = "default", "1.8v"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_1v8>; - clocks = <&mio_clk 0>; - bus-width = <4>; - }; - - usb0: usb@65a00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; - status = "disabled"; - reg = <0x65a00000 0x100>; - interrupts = <0 134 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - }; - - usb1: usb@65c00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; - status = "disabled"; - reg = <0x65c00000 0x100>; - interrupts = <0 137 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; - }; -}; - -&refclk { - clock-frequency = <20000000>; -}; - -&serial0 { - clock-frequency = <73728000>; -}; - -&serial1 { - clock-frequency = <73728000>; -}; - -&serial2 { - clock-frequency = <73728000>; -}; - -&serial3 { - clock-frequency = <73728000>; -}; - -&mio_clk { - compatible = "socionext,uniphier-pro5-mio-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-pro5-mio-reset"; -}; - -&peri_clk { - compatible = "socionext,uniphier-pro5-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-pro5-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-pro5-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-pro5-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-pro5-reset"; -}; diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts deleted file mode 100644 index 116e571e4e4..00000000000 --- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-sLD3 Reference Board - * - * Copyright (C) 2014-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ X11 - */ - -/dts-v1/; -/include/ "uniphier-ph1-sld3.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier PH1-sLD3 Reference Board"; - compatible = "socionext,ph1-sld3-ref", "socionext,ph1-sld3"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000 - 0xc0000000 0x20000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - }; -}; - -ðsc { - interrupts = <0 49 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&emmc { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_emmc { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi deleted file mode 100644 index a554b086e81..00000000000 --- a/arch/arm/dts/uniphier-ph1-sld3.dtsi +++ /dev/null @@ -1,416 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-sLD3 SoC - * - * Copyright (C) 2014-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ X11 - */ - -/include/ "skeleton.dtsi" - -/ { - compatible = "socionext,ph1-sld3"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - }; - }; - - clocks { - refclk: ref { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24576000>; - }; - - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - iobus_clk: iobus_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - u-boot,dm-pre-reloc; - - timer@20000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x20000200 0x20>; - interrupts = <1 11 0x304>; - clocks = <&arm_timer_clk>; - }; - - timer@20000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x20000600 0x20>; - interrupts = <1 13 0x304>; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@20001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x20001000 0x1000>, - <0x20000100 0x100>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clock-frequency = <36864000>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clock-frequency = <36864000>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clock-frequency = <36864000>; - }; - - port0x: gpio@55000008 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000008 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port1x: gpio@55000010 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000010 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port2x: gpio@55000018 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000018 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port3x: gpio@55000020 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000020 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port4: gpio@55000028 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000028 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port5x: gpio@55000030 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000030 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port6x: gpio@55000038 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000038 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port7x: gpio@55000040 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000040 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port8x: gpio@55000048 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000048 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port9x: gpio@55000050 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000050 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port10x: gpio@55000058 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000058 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port11x: gpio@55000060 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000060 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port12x: gpio@55000068 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000068 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port13x: gpio@55000070 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000070 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port14x: gpio@55000078 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000078 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port16x: gpio@55000088 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000088 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c4: i2c@58600000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58600000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 1>; - clocks = <&iobus_clk>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - }; - - smpctrl@59800000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - mioctrl@59810000 { - compatible = "socionext,uniphier-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - u-boot,dm-pre-reloc; - - mio_clk: clock { - compatible = "socionext,uniphier-sld3-mio-clock"; - #clock-cells = <1>; - u-boot,dm-pre-reloc; - }; - - mio_rst: reset { - compatible = "socionext,uniphier-sld3-mio-reset"; - #reset-cells = <1>; - }; - }; - - emmc: sdhc@5a400000 { - compatible = "socionext,uniphier-sdhc"; - status = "disabled"; - reg = <0x5a400000 0x200>; - interrupts = <0 78 4>; - pinctrl-names = "default", "1.8v"; - pinctrl-0 = <&pinctrl_emmc>; - pinctrl-1 = <&pinctrl_emmc_1v8>; - clocks = <&mio_clk 1>; - bus-width = <8>; - non-removable; - }; - - sd: sdhc@5a500000 { - compatible = "socionext,uniphier-sdhc"; - status = "disabled"; - reg = <0x5a500000 0x200>; - interrupts = <0 76 4>; - pinctrl-names = "default", "1.8v"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_1v8>; - clocks = <&mio_clk 0>; - bus-width = <4>; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio_clk 3>, <&mio_clk 6>; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio_clk 4>, <&mio_clk 6>; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 5>, <&mio_clk 6>; - }; - - usb3: usb@5a830100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a830100 0x100>; - interrupts = <0 83 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - clocks = <&mio_clk 7>, <&mio_clk 6>; - }; - - soc-glue@5f800000 { - compatible = "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - u-boot,dm-pre-reloc; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-sld3-pinctrl"; - u-boot,dm-pre-reloc; - }; - }; - - aidet@f1830000 { - compatible = "simple-mfd", "syscon"; - reg = <0xf1830000 0x200>; - }; - - sysctrl@f1840000 { - compatible = "socionext,uniphier-sysctrl", - "simple-mfd", "syscon"; - reg = <0xf1840000 0x4000>; - - sys_clk: clock { - compatible = "socionext,uniphier-sld3-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset { - compatible = "socionext,uniphier-sld3-reset"; - #reset-cells = <1>; - }; - }; - - nand: nand@f8000000 { - compatible = "denali,denali-nand-dt"; - reg = <0xf8000000 0x20>, <0xf8100000 0x1000>; - reg-names = "nand_data", "denali_reg"; - }; - }; -}; - -/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts deleted file mode 100644 index 9af012cab79..00000000000 --- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-sLD8 Reference Board - * - * Copyright (C) 2014-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ X11 - */ - -/dts-v1/; -/include/ "uniphier-ph1-sld8.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier PH1-sLD8 Reference Board"; - compatible = "socionext,ph1-sld8-ref", "socionext,ph1-sld8"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - }; -}; - -ðsc { - interrupts = <0 48 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -/* for U-Boot only */ -&serial0 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart0 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi deleted file mode 100644 index 1ecce5030f6..00000000000 --- a/arch/arm/dts/uniphier-ph1-sld8.dtsi +++ /dev/null @@ -1,325 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-sLD8 SoC - * - * Copyright (C) 2014-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ X11 - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,ph1-sld8"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - iobus_clk: iobus_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(256 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - port0x: gpio@55000008 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000008 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port1x: gpio@55000010 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000010 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port2x: gpio@55000018 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000018 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port3x: gpio@55000020 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000020 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port4: gpio@55000028 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000028 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port5x: gpio@55000030 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000030 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port6x: gpio@55000038 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000038 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port7x: gpio@55000040 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000040 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port8x: gpio@55000048 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000048 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port9x: gpio@55000050 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000050 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port10x: gpio@55000058 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000058 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port11x: gpio@55000060 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000060 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port12x: gpio@55000068 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000068 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port13x: gpio@55000070 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000070 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port14x: gpio@55000078 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000078 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port16x: gpio@55000088 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000088 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&iobus_clk>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - sd: sdhc@5a400000 { - compatible = "socionext,uniphier-sdhc"; - status = "disabled"; - reg = <0x5a400000 0x200>; - interrupts = <0 76 4>; - pinctrl-names = "default", "1.8v"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_1v8>; - clocks = <&mio_clk 0>; - bus-width = <4>; - }; - - emmc: sdhc@5a500000 { - compatible = "socionext,uniphier-sdhc"; - status = "disabled"; - interrupts = <0 78 4>; - reg = <0x5a500000 0x200>; - pinctrl-names = "default", "1.8v"; - pinctrl-0 = <&pinctrl_emmc>; - pinctrl-1 = <&pinctrl_emmc_1v8>; - clocks = <&mio_clk 1>; - bus-width = <8>; - non-removable; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio_clk 3>, <&mio_clk 6>; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio_clk 4>, <&mio_clk 6>; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 5>, <&mio_clk 6>; - }; - - aidet@61830000 { - compatible = "simple-mfd", "syscon"; - reg = <0x61830000 0x200>; - }; -}; - -&refclk { - clock-frequency = <25000000>; -}; - -&serial0 { - clock-frequency = <80000000>; -}; - -&serial1 { - clock-frequency = <80000000>; -}; - -&serial2 { - clock-frequency = <80000000>; -}; - -&serial3 { - interrupts = <0 29 4>; - clock-frequency = <80000000>; -}; - -&mio_clk { - compatible = "socionext,uniphier-sld8-mio-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-sld8-mio-reset"; -}; - -&peri_clk { - compatible = "socionext,uniphier-sld8-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-sld8-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-sld8-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-sld8-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-sld8-reset"; -}; diff --git a/arch/arm/dts/uniphier-pro4-ace.dts b/arch/arm/dts/uniphier-pro4-ace.dts new file mode 100644 index 00000000000..f70bc82e257 --- /dev/null +++ b/arch/arm/dts/uniphier-pro4-ace.dts @@ -0,0 +1,100 @@ +/* + * Device Tree Source for UniPhier Pro4 Ace Board + * + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; +/include/ "uniphier-pro4.dtsi" + +/ { + model = "UniPhier Pro4 Ace Board"; + compatible = "socionext,uniphier-pro4-ace", "socionext,uniphier-pro4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@54 { + compatible = "st,24c64", "i2c-eeprom"; + reg = <0x54>; + u-boot,i2c-offset-len = <2>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&sd { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +/* for U-Boot only */ +&serial0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-pro4-ref.dts b/arch/arm/dts/uniphier-pro4-ref.dts new file mode 100644 index 00000000000..2d49b3e831a --- /dev/null +++ b/arch/arm/dts/uniphier-pro4-ref.dts @@ -0,0 +1,90 @@ +/* + * Device Tree Source for UniPhier Pro4 Reference Board + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; +/include/ "uniphier-pro4.dtsi" +/include/ "uniphier-ref-daughter.dtsi" +/include/ "uniphier-support-card.dtsi" + +/ { + model = "UniPhier Pro4 Reference Board"; + compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c5 = &i2c5; + i2c6 = &i2c6; + usb0 = &usb0; + }; +}; + +ðsc { + interrupts = <0 50 4>; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&sd { + status = "okay"; +}; + +&sd1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +/* for U-Boot only */ +&serial0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-pro4-sanji.dts b/arch/arm/dts/uniphier-pro4-sanji.dts new file mode 100644 index 00000000000..d43f725b39a --- /dev/null +++ b/arch/arm/dts/uniphier-pro4-sanji.dts @@ -0,0 +1,107 @@ +/* + * Device Tree Source for UniPhier Pro4 Sanji Board + * + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; +/include/ "uniphier-pro4.dtsi" + +/ { + model = "UniPhier Pro4 Sanji Board"; + compatible = "socionext,uniphier-pro4-sanji", "socionext,uniphier-pro4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@54 { + compatible = "st,24c64", "i2c-eeprom"; + reg = <0x54>; + u-boot,i2c-offset-len = <2>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&emmc { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +/* for U-Boot only */ +&serial0 { + u-boot,dm-pre-reloc; +}; + +&mio_clk { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_emmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi new file mode 100644 index 00000000000..aa80ea4801f --- /dev/null +++ b/arch/arm/dts/uniphier-pro4.dtsi @@ -0,0 +1,484 @@ +/* + * Device Tree Source for UniPhier Pro4 SoC + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/include/ "uniphier-common32.dtsi" + +/ { + compatible = "socionext,uniphier-pro4"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + }; + + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <73728000>; + }; + + i2c_clk: i2c_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; +}; + +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(768 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; + + port0x: gpio@55000008 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000008 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port1x: gpio@55000010 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000010 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port2x: gpio@55000018 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000018 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port3x: gpio@55000020 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000020 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port4: gpio@55000028 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000028 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port5x: gpio@55000030 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000030 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port6x: gpio@55000038 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000038 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port7x: gpio@55000040 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000040 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port8x: gpio@55000048 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000048 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port9x: gpio@55000050 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000050 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port10x: gpio@55000058 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000058 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port11x: gpio@55000060 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000060 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port12x: gpio@55000068 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000068 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port13x: gpio@55000070 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000070 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port14x: gpio@55000078 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000078 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port17x: gpio@550000a0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000a0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port18x: gpio@550000a8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000a8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port19x: gpio@550000b0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000b0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port20x: gpio@550000b8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000b8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port21x: gpio@550000c0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000c0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port22x: gpio@550000c8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000c8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port23x: gpio@550000d0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000d0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port24x: gpio@550000d8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000d8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port25x: gpio@550000e0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000e0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port26x: gpio@550000e8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000e8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port27x: gpio@550000f0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000f0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port28x: gpio@550000f8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000f8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port29x: gpio@55000100 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000100 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port30x: gpio@55000108 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000108 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + /* i2c4 does not exist */ + + /* chip-internal connection for DMD */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + sd: sdhc@5a400000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a400000 0x200>; + interrupts = <0 76 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_1v8>; + clocks = <&mio_clk 0>; + reset-names = "host", "bridge"; + resets = <&mio_rst 0>, <&mio_rst 3>; + bus-width = <4>; + }; + + emmc: sdhc@5a500000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a500000 0x200>; + interrupts = <0 78 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_emmc>; + pinctrl-1 = <&pinctrl_emmc_1v8>; + clocks = <&mio_clk 1>; + reset-names = "host", "bridge", "hw-reset"; + resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; + bus-width = <8>; + non-removable; + }; + + sd1: sdhc@5a600000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a600000 0x200>; + interrupts = <0 85 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_sd1>; + pinctrl-1 = <&pinctrl_sd1_1v8>; + clocks = <&mio_clk 2>; + resets = <&mio_rst 2>, <&mio_rst 5>; + bus-width = <4>; + }; + + usb2: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; + }; + + usb3: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; + }; + + aidet@5fc20000 { + compatible = "simple-mfd", "syscon"; + reg = <0x5fc20000 0x200>; + }; + + usb0: usb@65a00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65a00000 0x100>; + interrupts = <0 134 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + }; + + usb1: usb@65c00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65c00000 0x100>; + interrupts = <0 137 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + }; +}; + +&refclk { + clock-frequency = <25000000>; +}; + +&serial0 { + clock-frequency = <73728000>; +}; + +&serial1 { + clock-frequency = <73728000>; +}; + +&serial2 { + clock-frequency = <73728000>; +}; + +&serial3 { + clock-frequency = <73728000>; +}; + +&mio_clk { + compatible = "socionext,uniphier-pro4-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-pro4-mio-reset"; +}; + +&peri_clk { + compatible = "socionext,uniphier-pro4-peri-clock"; +}; + +&peri_rst { + compatible = "socionext,uniphier-pro4-peri-reset"; +}; + +&pinctrl { + compatible = "socionext,uniphier-pro4-pinctrl"; +}; + +&sys_clk { + compatible = "socionext,uniphier-pro4-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-pro4-reset"; +}; diff --git a/arch/arm/dts/uniphier-pro5-4kbox.dts b/arch/arm/dts/uniphier-pro5-4kbox.dts new file mode 100644 index 00000000000..ffc21a7c500 --- /dev/null +++ b/arch/arm/dts/uniphier-pro5-4kbox.dts @@ -0,0 +1,66 @@ +/* + * Device Tree Source for UniPhier Pro5 4KBOX Board (EVB-Pro5-4KBOX-M-V0) + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "uniphier-pro5.dtsi" + +/ { + model = "UniPhier Pro5 4KBOX Board"; + compatible = "socionext,uniphier-pro5-4kbox", "socionext,uniphier-pro5"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + aliases { + serial1 = &serial1; + serial2 = &serial2; + i2c0 = &i2c0; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&emmc { + status = "okay"; +}; + +&sd { + status = "okay"; +}; + +/* for U-Boot only */ +&serial1 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi new file mode 100644 index 00000000000..97edc89a9cc --- /dev/null +++ b/arch/arm/dts/uniphier-pro5.dtsi @@ -0,0 +1,452 @@ +/* + * Device Tree Source for UniPhier Pro5 SoC + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/include/ "uniphier-common32.dtsi" + +/ { + compatible = "socionext,uniphier-pro5"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + }; + + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + i2c_clk: i2c_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; +}; + +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; + interrupts = <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <(2 * 1024 * 1024)>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + next-level-cache = <&l3>; + }; + + l3: l3-cache@500c8000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(2 * 1024 * 1024)>; + cache-sets = <512>; + cache-line-size = <256>; + cache-level = <3>; + }; + + port0x: gpio@55000008 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000008 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port1x: gpio@55000010 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000010 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port2x: gpio@55000018 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000018 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port3x: gpio@55000020 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000020 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port4: gpio@55000028 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000028 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port5x: gpio@55000030 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000030 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port6x: gpio@55000038 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000038 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port7x: gpio@55000040 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000040 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port8x: gpio@55000048 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000048 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port9x: gpio@55000050 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000050 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port10x: gpio@55000058 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000058 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port11x: gpio@55000060 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000060 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port12x: gpio@55000068 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000068 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port13x: gpio@55000070 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000070 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port14x: gpio@55000078 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000078 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port17x: gpio@550000a0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000a0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port18x: gpio@550000a8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000a8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port19x: gpio@550000b0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000b0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port20x: gpio@550000b8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000b8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port21x: gpio@550000c0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000c0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port22x: gpio@550000c8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000c8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port23x: gpio@550000d0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000d0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port24x: gpio@550000d8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000d8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port25x: gpio@550000e0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000e0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port26x: gpio@550000e8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000e8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port27x: gpio@550000f0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000f0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port28x: gpio@550000f8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000f8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port29x: gpio@55000100 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000100 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port30x: gpio@55000108 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000108 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + /* i2c4 does not exist */ + + /* chip-internal connection for DMD */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + aidet@5fc20000 { + compatible = "simple-mfd", "syscon"; + reg = <0x5fc20000 0x200>; + }; + + emmc: sdhc@68400000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x68400000 0x800>; + interrupts = <0 78 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emmc>; + clocks = <&mio_clk 1>; + reset-names = "host", "hw-reset"; + resets = <&mio_rst 1>, <&mio_rst 6>; + bus-width = <8>; + non-removable; + }; + + sd: sdhc@68800000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x68800000 0x800>; + interrupts = <0 76 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_1v8>; + clocks = <&mio_clk 0>; + reset-names = "host"; + resets = <&mio_rst 0>; + bus-width = <4>; + }; + + usb0: usb@65a00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65a00000 0x100>; + interrupts = <0 134 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + }; + + usb1: usb@65c00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65c00000 0x100>; + interrupts = <0 137 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; + }; +}; + +&refclk { + clock-frequency = <20000000>; +}; + +&serial0 { + clock-frequency = <73728000>; +}; + +&serial1 { + clock-frequency = <73728000>; +}; + +&serial2 { + clock-frequency = <73728000>; +}; + +&serial3 { + clock-frequency = <73728000>; +}; + +&mio_clk { + compatible = "socionext,uniphier-pro5-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-pro5-mio-reset"; +}; + +&peri_clk { + compatible = "socionext,uniphier-pro5-peri-clock"; +}; + +&peri_rst { + compatible = "socionext,uniphier-pro5-peri-reset"; +}; + +&pinctrl { + compatible = "socionext,uniphier-pro5-pinctrl"; +}; + +&sys_clk { + compatible = "socionext,uniphier-pro5-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-pro5-reset"; +}; diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts deleted file mode 100644 index 7233dc67ab3..00000000000 --- a/arch/arm/dts/uniphier-proxstream2-gentil.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Device Tree Source for UniPhier ProXstream2 Gentil Board - * - * Copyright (C) 2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/dts-v1/; -/include/ "uniphier-proxstream2.dtsi" - -/ { - model = "UniPhier ProXstream2 Gentil Board"; - compatible = "socionext,proxstream2-gentil", "socionext,proxstream2"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial2; - serial1 = &serial0; - serial2 = &serial1; - i2c0 = &i2c0; - i2c2 = &i2c2; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom { - compatible = "24c64", "i2c-eeprom"; - reg = <0x54>; - u-boot,i2c-offset-len = <2>; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&emmc { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -/* for U-Boot only */ -&serial2 { - u-boot,dm-pre-reloc; -}; - -&mio_clk { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart2 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_emmc { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts deleted file mode 100644 index 30ea27034c6..00000000000 --- a/arch/arm/dts/uniphier-proxstream2-vodka.dts +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Device Tree Source for UniPhier ProXstream2 Vodka Board - * - * Copyright (C) 2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/dts-v1/; -/include/ "uniphier-proxstream2.dtsi" - -/ { - model = "UniPhier ProXstream2 Vodka Board"; - compatible = "socionext,proxstream2-vodka", "socionext,proxstream2"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial2; - serial1 = &serial0; - serial2 = &serial1; - i2c0 = &i2c0; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&emmc { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -/* for U-Boot only */ -&serial2 { - u-boot,dm-pre-reloc; -}; - -&mio_clk { - u-boot,dm-pre-reloc; -}; - -&emmc { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart2 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_emmc { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi deleted file mode 100644 index 609cbaa9d7c..00000000000 --- a/arch/arm/dts/uniphier-proxstream2.dtsi +++ /dev/null @@ -1,450 +0,0 @@ -/* - * Device Tree Source for UniPhier ProXstream2 SoC - * - * Copyright (C) 2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ X11 - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,proxstream2"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&l2>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - next-level-cache = <&l2>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - i2c_clk: i2c_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; - cache-unified; - cache-size = <(1280 * 1024)>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - }; - - port0x: gpio@55000008 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000008 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port1x: gpio@55000010 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000010 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port2x: gpio@55000018 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000018 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port3x: gpio@55000020 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000020 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port4: gpio@55000028 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000028 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port5x: gpio@55000030 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000030 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port6x: gpio@55000038 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000038 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port7x: gpio@55000040 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000040 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port8x: gpio@55000048 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000048 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port9x: gpio@55000050 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000050 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port10x: gpio@55000058 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000058 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port12x: gpio@55000068 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000068 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port13x: gpio@55000070 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000070 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port14x: gpio@55000078 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000078 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port15x: gpio@55000080 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000080 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port16x: gpio@55000088 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000088 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port17x: gpio@550000a0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000a0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port18x: gpio@550000a8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000a8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port19x: gpio@550000b0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000b0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port20x: gpio@550000b8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000b8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port21x: gpio@550000c0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000c0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port22x: gpio@550000c8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000c8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port23x: gpio@550000d0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000d0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port24x: gpio@550000d8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000d8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port25x: gpio@550000e0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000e0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port26x: gpio@550000e8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000e8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port27x: gpio@550000f0 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000f0 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - port28x: gpio@550000f8 { - compatible = "socionext,uniphier-gpio"; - reg = <0x550000f8 0x8>; - gpio-controller; - #gpio-cells = <2>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - interrupts = <0 43 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c4: i2c@58784000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58784000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for STM */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - emmc: sdhc@5a000000 { - compatible = "socionext,uniphier-sdhc"; - status = "disabled"; - reg = <0x5a000000 0x800>; - interrupts = <0 78 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - clocks = <&mio_clk 1>; - bus-width = <8>; - non-removable; - }; - - sd: sdhc@5a400000 { - compatible = "socionext,uniphier-sdhc"; - status = "disabled"; - reg = <0x5a400000 0x800>; - interrupts = <0 76 4>; - pinctrl-names = "default", "1.8v"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_1v8>; - clocks = <&mio_clk 0>; - bus-width = <4>; - }; - - aidet@5fc20000 { - compatible = "simple-mfd", "syscon"; - reg = <0x5fc20000 0x200>; - }; - - usb0: usb@65a00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; - status = "disabled"; - reg = <0x65a00000 0x100>; - interrupts = <0 134 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; - }; - - usb1: usb@65c00000 { - compatible = "socionext,uniphier-xhci", "generic-xhci"; - status = "disabled"; - reg = <0x65c00000 0x100>; - interrupts = <0 137 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; - }; -}; - -&refclk { - clock-frequency = <25000000>; -}; - -&serial0 { - clock-frequency = <88900000>; -}; - -&serial1 { - clock-frequency = <88900000>; -}; - -&serial2 { - clock-frequency = <88900000>; -}; - -&serial3 { - clock-frequency = <88900000>; -}; - -&mio_clk { - compatible = "socionext,uniphier-pxs2-mio-clock"; -}; - -&mio_rst { - compatible = "socionext,uniphier-pxs2-mio-reset"; -}; - -&peri_clk { - compatible = "socionext,uniphier-pxs2-peri-clock"; -}; - -&peri_rst { - compatible = "socionext,uniphier-pxs2-peri-reset"; -}; - -&pinctrl { - compatible = "socionext,uniphier-pxs2-pinctrl"; -}; - -&sys_clk { - compatible = "socionext,uniphier-pxs2-clock"; -}; - -&sys_rst { - compatible = "socionext,uniphier-pxs2-reset"; -}; diff --git a/arch/arm/dts/uniphier-pxs2-gentil.dts b/arch/arm/dts/uniphier-pxs2-gentil.dts new file mode 100644 index 00000000000..a98e758f031 --- /dev/null +++ b/arch/arm/dts/uniphier-pxs2-gentil.dts @@ -0,0 +1,88 @@ +/* + * Device Tree Source for UniPhier PXs2 Gentil Board + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "uniphier-pxs2.dtsi" + +/ { + model = "UniPhier PXs2 Gentil Board"; + compatible = "socionext,uniphier-pxs2-gentil", + "socionext,uniphier-pxs2"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial2; + serial1 = &serial0; + serial2 = &serial1; + i2c0 = &i2c0; + i2c2 = &i2c2; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@54 { + compatible = "st,24c64", "i2c-eeprom"; + reg = <0x54>; + u-boot,i2c-offset-len = <2>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&emmc { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* for U-Boot only */ +&serial2 { + u-boot,dm-pre-reloc; +}; + +&mio_clk { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart2 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_emmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-pxs2-vodka.dts b/arch/arm/dts/uniphier-pxs2-vodka.dts new file mode 100644 index 00000000000..78a52a8f18f --- /dev/null +++ b/arch/arm/dts/uniphier-pxs2-vodka.dts @@ -0,0 +1,72 @@ +/* + * Device Tree Source for UniPhier PXs2 Vodka Board + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "uniphier-pxs2.dtsi" + +/ { + model = "UniPhier PXs2 Vodka Board"; + compatible = "socionext,uniphier-pxs2-vodka", "socionext,uniphier-pxs2"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial2; + serial1 = &serial0; + serial2 = &serial1; + i2c0 = &i2c0; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&emmc { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +/* for U-Boot only */ +&serial2 { + u-boot,dm-pre-reloc; +}; + +&mio_clk { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart2 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_emmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi new file mode 100644 index 00000000000..b64107b3dd4 --- /dev/null +++ b/arch/arm/dts/uniphier-pxs2.dtsi @@ -0,0 +1,458 @@ +/* + * Device Tree Source for UniPhier PXs2 SoC + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/include/ "uniphier-common32.dtsi" + +/ { + compatible = "socionext,uniphier-pxs2"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + }; + + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + i2c_clk: i2c_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; +}; + +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <(1280 * 1024)>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + }; + + port0x: gpio@55000008 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000008 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port1x: gpio@55000010 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000010 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port2x: gpio@55000018 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000018 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port3x: gpio@55000020 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000020 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port4: gpio@55000028 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000028 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port5x: gpio@55000030 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000030 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port6x: gpio@55000038 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000038 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port7x: gpio@55000040 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000040 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port8x: gpio@55000048 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000048 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port9x: gpio@55000050 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000050 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port10x: gpio@55000058 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000058 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port12x: gpio@55000068 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000068 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port13x: gpio@55000070 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000070 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port14x: gpio@55000078 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000078 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port15x: gpio@55000080 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000080 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port16x: gpio@55000088 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000088 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port17x: gpio@550000a0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000a0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port18x: gpio@550000a8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000a8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port19x: gpio@550000b0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000b0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port20x: gpio@550000b8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000b8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port21x: gpio@550000c0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000c0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port22x: gpio@550000c8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000c8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port23x: gpio@550000d0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000d0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port24x: gpio@550000d8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000d8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port25x: gpio@550000e0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000e0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port26x: gpio@550000e8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000e8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port27x: gpio@550000f0 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000f0 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port28x: gpio@550000f8 { + compatible = "socionext,uniphier-gpio"; + reg = <0x550000f8 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + interrupts = <0 43 4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c4: i2c@58784000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58784000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 45 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for STM */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + emmc: sdhc@5a000000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a000000 0x800>; + interrupts = <0 78 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emmc>; + clocks = <&mio_clk 1>; + reset-names = "host", "hw-reset"; + resets = <&mio_rst 1>, <&mio_rst 6>; + bus-width = <8>; + non-removable; + }; + + sd: sdhc@5a400000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a400000 0x800>; + interrupts = <0 76 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_1v8>; + clocks = <&mio_clk 0>; + reset-names = "host"; + resets = <&mio_rst 0>; + bus-width = <4>; + }; + + aidet@5fc20000 { + compatible = "simple-mfd", "syscon"; + reg = <0x5fc20000 0x200>; + }; + + usb0: usb@65a00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65a00000 0x100>; + interrupts = <0 134 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; + }; + + usb1: usb@65c00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65c00000 0x100>; + interrupts = <0 137 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; + }; +}; + +&refclk { + clock-frequency = <25000000>; +}; + +&serial0 { + clock-frequency = <88900000>; +}; + +&serial1 { + clock-frequency = <88900000>; +}; + +&serial2 { + clock-frequency = <88900000>; +}; + +&serial3 { + clock-frequency = <88900000>; +}; + +&mio_clk { + compatible = "socionext,uniphier-pxs2-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-pxs2-mio-reset"; +}; + +&peri_clk { + compatible = "socionext,uniphier-pxs2-peri-clock"; +}; + +&peri_rst { + compatible = "socionext,uniphier-pxs2-peri-reset"; +}; + +&pinctrl { + compatible = "socionext,uniphier-pxs2-pinctrl"; +}; + +&sys_clk { + compatible = "socionext,uniphier-pxs2-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-pxs2-reset"; +}; diff --git a/arch/arm/dts/uniphier-sld3-ref.dts b/arch/arm/dts/uniphier-sld3-ref.dts new file mode 100644 index 00000000000..f35500d4bba --- /dev/null +++ b/arch/arm/dts/uniphier-sld3-ref.dts @@ -0,0 +1,100 @@ +/* + * Device Tree Source for UniPhier sLD3 Reference Board + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; +/include/ "uniphier-sld3.dtsi" +/include/ "uniphier-ref-daughter.dtsi" +/include/ "uniphier-support-card.dtsi" + +/ { + model = "UniPhier sLD3 Reference Board"; + compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000 + 0xc0000000 0x20000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; +}; + +ðsc { + interrupts = <0 49 4>; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&emmc { + status = "okay"; +}; + +&sd { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +/* for U-Boot only */ +&serial0 { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_emmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-sld3.dtsi b/arch/arm/dts/uniphier-sld3.dtsi new file mode 100644 index 00000000000..f5c54875348 --- /dev/null +++ b/arch/arm/dts/uniphier-sld3.dtsi @@ -0,0 +1,448 @@ +/* + * Device Tree Source for UniPhier sLD3 SoC + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "socionext,uniphier-sld3"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + clocks { + refclk: ref { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + iobus_clk: iobus_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; + u-boot,dm-pre-reloc; + + timer@20000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x20000200 0x20>; + interrupts = <1 11 0x304>; + clocks = <&arm_timer_clk>; + }; + + timer@20000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x20000600 0x20>; + interrupts = <1 13 0x304>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@20001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x20001000 0x1000>, + <0x20000100 0x100>; + }; + + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, + <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(512 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + clock-frequency = <36864000>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + clock-frequency = <36864000>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + clock-frequency = <36864000>; + }; + + port0x: gpio@55000008 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000008 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port1x: gpio@55000010 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000010 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port2x: gpio@55000018 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000018 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port3x: gpio@55000020 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000020 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port4: gpio@55000028 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000028 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port5x: gpio@55000030 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000030 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port6x: gpio@55000038 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000038 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port7x: gpio@55000040 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000040 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port8x: gpio@55000048 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000048 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port9x: gpio@55000050 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000050 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port10x: gpio@55000058 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000058 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port11x: gpio@55000060 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000060 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port12x: gpio@55000068 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000068 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port13x: gpio@55000070 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000070 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port14x: gpio@55000078 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000078 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port16x: gpio@55000088 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000088 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c4: i2c@58600000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58600000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 45 1>; + clocks = <&iobus_clk>; + clock-frequency = <400000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + }; + + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + mioctrl@59810000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + u-boot,dm-pre-reloc; + + mio_clk: clock { + compatible = "socionext,uniphier-sld3-mio-clock"; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-sld3-mio-reset"; + #reset-cells = <1>; + }; + }; + + emmc: sdhc@5a400000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a400000 0x200>; + interrupts = <0 78 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_emmc>; + pinctrl-1 = <&pinctrl_emmc_1v8>; + clocks = <&mio_clk 1>; + resets = <&mio_rst 1>, <&mio_rst 4>; + bus-width = <8>; + non-removable; + }; + + sd: sdhc@5a500000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a500000 0x200>; + interrupts = <0 76 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_1v8>; + clocks = <&mio_clk 0>; + resets = <&mio_rst 0>, <&mio_rst 3>; + bus-width = <4>; + }; + + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; + }; + + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 82 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, + <&mio_rst 14>; + }; + + usb3: usb@5a830100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a830100 0x100>; + interrupts = <0 83 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>, + <&mio_rst 15>; + }; + + soc-glue@5f800000 { + compatible = "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + u-boot,dm-pre-reloc; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-sld3-pinctrl"; + u-boot,dm-pre-reloc; + }; + }; + + aidet@f1830000 { + compatible = "simple-mfd", "syscon"; + reg = <0xf1830000 0x200>; + }; + + sysctrl@f1840000 { + compatible = "socionext,uniphier-sysctrl", + "simple-mfd", "syscon"; + reg = <0xf1840000 0x4000>; + + sys_clk: clock { + compatible = "socionext,uniphier-sld3-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-sld3-reset"; + #reset-cells = <1>; + }; + }; + + nand: nand@f8000000 { + compatible = "denali,denali-nand-dt"; + reg = <0xf8000000 0x20>, <0xf8100000 0x1000>; + reg-names = "nand_data", "denali_reg"; + }; + }; +}; + +/include/ "uniphier-pinctrl.dtsi" diff --git a/arch/arm/dts/uniphier-sld8-ref.dts b/arch/arm/dts/uniphier-sld8-ref.dts new file mode 100644 index 00000000000..6c0544b908e --- /dev/null +++ b/arch/arm/dts/uniphier-sld8-ref.dts @@ -0,0 +1,83 @@ +/* + * Device Tree Source for UniPhier sLD8 Reference Board + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; +/include/ "uniphier-sld8.dtsi" +/include/ "uniphier-ref-daughter.dtsi" +/include/ "uniphier-support-card.dtsi" + +/ { + model = "UniPhier sLD8 Reference Board"; + compatible = "socionext,uniphier-sld8-ref", "socionext,uniphier-sld8"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; +}; + +ðsc { + interrupts = <0 48 4>; +}; + +&serial0 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&sd { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +/* for U-Boot only */ +&serial0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi new file mode 100644 index 00000000000..b8f6d674095 --- /dev/null +++ b/arch/arm/dts/uniphier-sld8.dtsi @@ -0,0 +1,337 @@ +/* + * Device Tree Source for UniPhier sLD8 SoC + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/include/ "uniphier-common32.dtsi" + +/ { + compatible = "socionext,uniphier-sld8"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + }; + + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + iobus_clk: iobus_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + }; +}; + +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(256 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; + + port0x: gpio@55000008 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000008 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port1x: gpio@55000010 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000010 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port2x: gpio@55000018 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000018 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port3x: gpio@55000020 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000020 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port4: gpio@55000028 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000028 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port5x: gpio@55000030 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000030 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port6x: gpio@55000038 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000038 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port7x: gpio@55000040 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000040 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port8x: gpio@55000048 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000048 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port9x: gpio@55000050 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000050 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port10x: gpio@55000058 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000058 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port11x: gpio@55000060 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000060 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port12x: gpio@55000068 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000068 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port13x: gpio@55000070 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000070 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port14x: gpio@55000078 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000078 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + port16x: gpio@55000088 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000088 0x8>; + gpio-controller; + #gpio-cells = <2>; + }; + + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&iobus_clk>; + clock-frequency = <400000>; + }; + + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + sd: sdhc@5a400000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a400000 0x200>; + interrupts = <0 76 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_1v8>; + clocks = <&mio_clk 0>; + reset-names = "host", "bridge"; + resets = <&mio_rst 0>, <&mio_rst 3>; + bus-width = <4>; + }; + + emmc: sdhc@5a500000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + interrupts = <0 78 4>; + reg = <0x5a500000 0x200>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_emmc>; + pinctrl-1 = <&pinctrl_emmc_1v8>; + clocks = <&mio_clk 1>; + reset-names = "host", "bridge", "hw-reset"; + resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; + bus-width = <8>; + non-removable; + }; + + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; + }; + + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 82 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, + <&mio_rst 14>; + }; + + aidet@61830000 { + compatible = "simple-mfd", "syscon"; + reg = <0x61830000 0x200>; + }; +}; + +&refclk { + clock-frequency = <25000000>; +}; + +&serial0 { + clock-frequency = <80000000>; +}; + +&serial1 { + clock-frequency = <80000000>; +}; + +&serial2 { + clock-frequency = <80000000>; +}; + +&serial3 { + interrupts = <0 29 4>; + clock-frequency = <80000000>; +}; + +&mio_clk { + compatible = "socionext,uniphier-sld8-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-sld8-mio-reset"; +}; + +&peri_clk { + compatible = "socionext,uniphier-sld8-peri-clock"; +}; + +&peri_rst { + compatible = "socionext,uniphier-sld8-peri-reset"; +}; + +&pinctrl { + compatible = "socionext,uniphier-sld8-pinctrl"; +}; + +&sys_clk { + compatible = "socionext,uniphier-sld8-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-sld8-reset"; +}; diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index 79b1d2013a0..059645171a7 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -250,35 +250,35 @@ struct uniphier_board_id { static const struct uniphier_board_id uniphier_boards[] = { #if defined(CONFIG_ARCH_UNIPHIER_SLD3) - { "socionext,ph1-sld3", &uniphier_sld3_data, }, + { "socionext,uniphier-sld3", &uniphier_sld3_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) - { "socionext,ph1-ld4", &uniphier_ld4_data, }, + { "socionext,uniphier-ld4", &uniphier_ld4_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO4) - { "socionext,ph1-pro4-ace", &uniphier_pro4_2g_data, }, - { "socionext,ph1-pro4-sanji", &uniphier_pro4_2g_data, }, - { "socionext,ph1-pro4", &uniphier_pro4_data, }, + { "socionext,uniphier-pro4-ace", &uniphier_pro4_2g_data, }, + { "socionext,uniphier-pro4-sanji", &uniphier_pro4_2g_data, }, + { "socionext,uniphier-pro4", &uniphier_pro4_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_SLD8) - { "socionext,ph1-sld8", &uniphier_sld8_data, }, + { "socionext,uniphier-sld8", &uniphier_sld8_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO5) - { "socionext,ph1-pro5", &uniphier_pro5_data, }, + { "socionext,uniphier-pro5", &uniphier_pro5_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PXS2) - { "socionext,proxstream2", &uniphier_pxs2_data, }, + { "socionext,uniphier-pxs2", &uniphier_pxs2_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD6B) - { "socionext,ph1-ld6b", &uniphier_ld6b_data, }, + { "socionext,uniphier-ld6b", &uniphier_ld6b_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD11) - { "socionext,ph1-ld11", &uniphier_ld11_data, }, + { "socionext,uniphier-ld11", &uniphier_ld11_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD20) - { "socionext,ph1-ld21", &uniphier_ld21_data, }, - { "socionext,ph1-ld20-ref", &uniphier_ld20_ref_data, }, - { "socionext,ph1-ld20", &uniphier_ld20_data, }, + { "socionext,uniphier-ld21", &uniphier_ld21_data, }, + { "socionext,uniphier-ld20-ref", &uniphier_ld20_ref_data, }, + { "socionext,uniphier-ld20", &uniphier_ld20_data, }, #endif }; diff --git a/configs/uniphier_ld11_defconfig b/configs/uniphier_ld11_defconfig index 864e04e6913..c0ac5ac048c 100644 --- a/configs/uniphier_ld11_defconfig +++ b/configs/uniphier_ld11_defconfig @@ -5,7 +5,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_ARCH_UNIPHIER_LD11=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 -CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld11-ref" +CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld11-ref" CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_XIMG is not set diff --git a/configs/uniphier_ld20_defconfig b/configs/uniphier_ld20_defconfig index 3fe37586f0d..3e802d3e084 100644 --- a/configs/uniphier_ld20_defconfig +++ b/configs/uniphier_ld20_defconfig @@ -5,7 +5,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_ARCH_UNIPHIER_LD20=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 -CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld20-ref" +CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref" CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_XIMG is not set diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index c18f04279d4..b141561ab3a 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -7,7 +7,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_ARCH_UNIPHIER_LD4_SLD8=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 -CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref" +CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld4-ref" CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig index 9441b053f19..f71ef56019d 100644 --- a/configs/uniphier_pro4_defconfig +++ b/configs/uniphier_pro4_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 -CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref" +CONFIG_DEFAULT_DEVICE_TREE="uniphier-pro4-ref" CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/uniphier_pxs2_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig index 0bf39f4e256..ba3867f06ac 100644 --- a/configs/uniphier_pxs2_ld6b_defconfig +++ b/configs/uniphier_pxs2_ld6b_defconfig @@ -7,7 +7,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_ARCH_UNIPHIER_PRO5_PXS2_LD6B=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 -CONFIG_DEFAULT_DEVICE_TREE="uniphier-proxstream2-vodka" +CONFIG_DEFAULT_DEVICE_TREE="uniphier-pxs2-vodka" CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/uniphier_sld3_defconfig b/configs/uniphier_sld3_defconfig index bd9c327e92c..3568f7a635e 100644 --- a/configs/uniphier_sld3_defconfig +++ b/configs/uniphier_sld3_defconfig @@ -7,7 +7,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_ARCH_UNIPHIER_SLD3=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 -CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref" +CONFIG_DEFAULT_DEVICE_TREE="uniphier-sld3-ref" CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/doc/README.uniphier b/doc/README.uniphier index 49045a02188..598ff28ccdf 100644 --- a/doc/README.uniphier +++ b/doc/README.uniphier @@ -28,45 +28,45 @@ Tested toolchains Compile the source ------------------ -PH1-sLD3 reference board: +sLD3 reference board: $ make uniphier_sld3_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- -PH1-LD4 reference board: +LD4 reference board: $ make uniphier_ld4_sld8_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- -PH1-sLD8 reference board: +sLD8 reference board: $ make uniphier_ld4_sld8_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-sld8-ref + $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-sld8-ref -PH1-Pro4 reference board: +Pro4 reference board: $ make uniphier_pro4_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- -PH1-Pro4 Ace board: +Pro4 Ace board: $ make uniphier_pro4_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-pro4-ace + $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-pro4-ace -PH1-Pro4 Sanji board: +Pro4 Sanji board: $ make uniphier_pro4_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-pro4-sanji + $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-pro4-sanji -PH1-Pro5 4KBOX Board: +Pro5 4KBOX Board: $ make uniphier_pxs2_ld6b_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-pro5-4kbox + $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-pro5-4kbox -ProXstream2 Gentil board: +PXs2 Gentil board: $ make uniphier_pxs2_ld6b_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-proxstream2-gentil + $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-pxs2-gentil -ProXstream2 Vodka board: +PXs2 Vodka board: $ make uniphier_pxs2_ld6b_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- -PH1-LD6b reference board: +LD6b reference board: $ make uniphier_pxs2_ld6b_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-ld6b-ref + $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ld6b-ref You may wish to change the "CROSS_COMPILE=arm-linux-gnueabi-" to use your favorite compiler. -- cgit v1.3.1 From 70dda1b1e8a2ed69470b4af0b3087630776e477d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 17 Oct 2016 22:18:03 +0900 Subject: ARM: uniphier: remove unnecessary EHCI reset deassertion It is now deasserted by the reset controller driver. Drop the ad-hoc code. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/clk-ld4.c | 7 +++---- arch/arm/mach-uniphier/clk/clk-pro4.c | 7 +++---- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-uniphier/clk/clk-ld4.c b/arch/arm/mach-uniphier/clk/clk-ld4.c index 8744d266e24..62b6927732a 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld4.c +++ b/arch/arm/mach-uniphier/clk/clk-ld4.c @@ -1,5 +1,7 @@ /* - * Copyright (C) 2011-2015 Masahiro Yamada + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada * * SPDX-License-Identifier: GPL-2.0+ */ @@ -18,9 +20,6 @@ void uniphier_ld4_clk_init(void) #ifdef CONFIG_UNIPHIER_ETH tmp |= SC_RSTCTRL_NRST_ETHER; #endif -#ifdef CONFIG_USB_EHCI - tmp |= SC_RSTCTRL_NRST_STDMAC; -#endif #ifdef CONFIG_NAND_DENALI tmp |= SC_RSTCTRL_NRST_NAND; #endif diff --git a/arch/arm/mach-uniphier/clk/clk-pro4.c b/arch/arm/mach-uniphier/clk/clk-pro4.c index 8746d7df518..92b73384abd 100644 --- a/arch/arm/mach-uniphier/clk/clk-pro4.c +++ b/arch/arm/mach-uniphier/clk/clk-pro4.c @@ -1,5 +1,7 @@ /* - * Copyright (C) 2011-2015 Masahiro Yamada + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada * * SPDX-License-Identifier: GPL-2.0+ */ @@ -22,9 +24,6 @@ void uniphier_pro4_clk_init(void) #ifdef CONFIG_UNIPHIER_ETH tmp |= SC_RSTCTRL_NRST_ETHER; #endif -#ifdef CONFIG_USB_EHCI - tmp |= SC_RSTCTRL_NRST_STDMAC; -#endif #ifdef CONFIG_NAND_DENALI tmp |= SC_RSTCTRL_NRST_NAND; #endif -- cgit v1.3.1 From 12a5ce72738a34eaa11b559778039f1051425dbd Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 17 Oct 2016 22:20:16 +0900 Subject: ARM: uniphier: update doc/README.uniphier - Rephrase the toolchains section. Leave only Linaro toolchains since it is the most tested these days. - Add build instruction for ARMv8 SoC boards - Add information about "ddrmphy" command Signed-off-by: Masahiro Yamada --- doc/README.uniphier | 58 +++++++++++++++++++++++++---------------------------- 1 file changed, 27 insertions(+), 31 deletions(-) diff --git a/doc/README.uniphier b/doc/README.uniphier index 598ff28ccdf..a42eaa97610 100644 --- a/doc/README.uniphier +++ b/doc/README.uniphier @@ -2,74 +2,67 @@ U-Boot for UniPhier SoC family ============================== -Tested toolchains ------------------ - - (a) Ubuntu packages (CROSS_COMPILE=arm-linux-gnueabi-) - - If you are building U-Boot on Ubuntu, its standard package is recommended. - You can install it as follows: +Recommended toolchains +---------------------- - $ sudo apt-get install gcc-arm-linux-gnueabi- - - (b) Linaro compilers (CROSS_COMPILE=arm-linux-gnueabihf-) - - You can download pre-built toolchains from: +The UniPhir platform is well tested with Linaro toolchanis. +You can download pre-built toolchains from: http://www.linaro.org/downloads/ - (c) kernel.org compilers (CROSS_COMPILE=arm-unknown-linux-gnueabi-) - - You can download pre-built toolchains from: - - ftp://www.kernel.org/pub/tools/crosstool/files/bin/ - Compile the source ------------------ sLD3 reference board: $ make uniphier_sld3_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- + $ make CROSS_COMPILE=arm-linux-gnueabihf- LD4 reference board: $ make uniphier_ld4_sld8_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- + $ make CROSS_COMPILE=arm-linux-gnueabihf- sLD8 reference board: $ make uniphier_ld4_sld8_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-sld8-ref + $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-sld8-ref Pro4 reference board: $ make uniphier_pro4_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- + $ make CROSS_COMPILE=arm-linux-gnueabihf- Pro4 Ace board: $ make uniphier_pro4_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-pro4-ace + $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro4-ace Pro4 Sanji board: $ make uniphier_pro4_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-pro4-sanji + $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro4-sanji Pro5 4KBOX Board: $ make uniphier_pxs2_ld6b_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-pro5-4kbox + $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro5-4kbox PXs2 Gentil board: $ make uniphier_pxs2_ld6b_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-pxs2-gentil + $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pxs2-gentil PXs2 Vodka board: $ make uniphier_pxs2_ld6b_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- + $ make CROSS_COMPILE=arm-linux-gnueabihf- LD6b reference board: $ make uniphier_pxs2_ld6b_defconfig - $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ld6b-ref + $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-ld6b-ref + +LD11 reference board: + $ make uniphier_ld11_defconfig + $ make CROSS_COMPILE=aarch64-linux-gnu- -You may wish to change the "CROSS_COMPILE=arm-linux-gnueabi-" -to use your favorite compiler. +LD20 reference board: + $ make uniphier_ld20_defconfig + $ make CROSS_COMPILE=aarch64-linux-gnu- + +You may wish to change the "CROSS_COMPILE=..." to use your favorite compiler. Burn U-Boot images to NAND @@ -119,6 +112,9 @@ UniPhier specific commands - ddrphy (enabled by CONFIG_CMD_DDRPHY_DUMP) shows the DDR PHY parameters set by the PHY training + - ddrmphy (enabled by CONFIG_CMD_DDRMPHY_DUMP) + shows the DDR Multi PHY parameters set by the PHY training + Supported devices ----------------- @@ -179,4 +175,4 @@ newer SoCs. Even if it is, EA[25] is not connected on most of the boards. -- Masahiro Yamada -Feb. 2016 +Oct. 2016 -- cgit v1.3.1