From b263302aa588464cec3bbdde09e2b52765dbae9e Mon Sep 17 00:00:00 2001 From: David Feng Date: Sat, 31 Jan 2015 11:55:28 +0800 Subject: ARMv8: enable pre-allocation malloc Allocate memory space for pre-allocation malloc and zero global data. This code is partly from crt0.S. Signed-off-by: David Feng --- arch/arm/include/asm/config.h | 4 ---- arch/arm/lib/crt0_64.S | 13 +++++++++++-- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index be80434dee4..7a34a0186cb 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -7,10 +7,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#ifdef __aarch64__ -#define CONFIG_SYS_GENERIC_GLOBAL_DATA -#endif - #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 77563967e51..16540114323 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -62,9 +62,18 @@ ENTRY(_main) * Set up initial C runtime environment and call board_init_f(0). */ ldr x0, =(CONFIG_SYS_INIT_SP_ADDR) - sub x0, x0, #GD_SIZE /* allocate one GD above SP */ + sub x18, x0, #GD_SIZE /* allocate one GD above SP */ + bic x18, x18, #0x7 /* 8-byte alignment for GD */ +zero_gd: + sub x0, x0, #0x8 + str xzr, [x0] + cmp x0, x18 + b.gt zero_gd +#if defined(CONFIG_SYS_MALLOC_F_LEN) + sub x0, x18, #CONFIG_SYS_MALLOC_F_LEN + str x0, [x18, #GD_MALLOC_BASE] +#endif bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ - mov x18, sp /* GD is above SP */ mov x0, #0 bl board_init_f -- cgit v1.3.1 From d8bafe1310487ba0e0785997726b4792072178d3 Mon Sep 17 00:00:00 2001 From: David Feng Date: Sat, 31 Jan 2015 11:55:29 +0800 Subject: ARMv8: enable DM in vexpress64 board Signed-off-by: David Feng --- board/armltd/vexpress64/vexpress64.c | 13 +++++++++++++ include/configs/vexpress_aemv8a.h | 13 ++++++++++++- 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index de6286435d9..071d88c07d8 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -12,9 +12,22 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; +static const struct pl01x_serial_platdata serial_platdata = { + .base = V2M_UART0, + .type = TYPE_PL011, + .clock = 2400 * 1000, +}; + +U_BOOT_DEVICE(vexpress_serials) = { + .name = "serial_pl01x", + .platdata = &serial_platdata, +}; + int board_init(void) { return 0; diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 810eef12deb..047514ad191 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -8,6 +8,8 @@ #ifndef __VEXPRESS_AEMV8A_H #define __VEXPRESS_AEMV8A_H +#define CONFIG_DM + /* We use generic board for v8 Versatile Express */ #define CONFIG_SYS_GENERIC_BOARD @@ -127,6 +129,7 @@ #define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x80000000) /* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_F_LEN 0x2000 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) /* Ethernet Configuration */ @@ -142,6 +145,14 @@ #endif /* PL011 Serial Configuration */ +#define CONFIG_BAUDRATE 115200 +#ifdef CONFIG_DM +#define CONFIG_DM_SERIAL +#define CONFIG_PL01X_SERIAL +#else +#define CONFIG_SYS_SERIAL0 V2M_UART0 +#define CONFIG_SYS_SERIAL1 V2M_UART1 +#define CONFIG_CONS_INDEX 0 #define CONFIG_PL011_SERIAL #ifdef CONFIG_TARGET_VEXPRESS64_JUNO #define CONFIG_PL011_CLOCK 7273800 @@ -150,7 +161,7 @@ #endif #define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ (void *)CONFIG_SYS_SERIAL1} -#define CONFIG_CONS_INDEX 0 +#endif #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_SERIAL0 V2M_UART0 -- cgit v1.3.1 From 0edb3a8ec9a48725bf323e99b2167318fae4315a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 25 Mar 2015 12:04:34 -0600 Subject: ARM: tegra: pinctrl: move Tegra210 code to the correct dir Patches that added the Tegra210 pinctrl driver and renamed directories arch/arm/cpu/tegra{$soc}-common -> arch/arm/mach-tegra/tegra-${soc} crossed. Move the Tegra210 pinctrl driver to the correct location. This wasn't detected since Tegra210 support is in the process of being added, and isn't buildable yet. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/cpu/tegra210-common/pinmux.c | 195 ---------------------------------- arch/arm/mach-tegra/tegra210/pinmux.c | 195 ++++++++++++++++++++++++++++++++++ 2 files changed, 195 insertions(+), 195 deletions(-) delete mode 100644 arch/arm/cpu/tegra210-common/pinmux.c create mode 100644 arch/arm/mach-tegra/tegra210/pinmux.c diff --git a/arch/arm/cpu/tegra210-common/pinmux.c b/arch/arm/cpu/tegra210-common/pinmux.c deleted file mode 100644 index a29c76b1fae..00000000000 --- a/arch/arm/cpu/tegra210-common/pinmux.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#define PIN(pin, f0, f1, f2, f3) \ - { \ - .funcs = { \ - PMUX_FUNC_##f0, \ - PMUX_FUNC_##f1, \ - PMUX_FUNC_##f2, \ - PMUX_FUNC_##f3, \ - }, \ - } - -#define PIN_RESERVED {} - -static const struct pmux_pingrp_desc tegra210_pingroups[] = { - /* pin, f0, f1, f2, f3 */ - /* Offset 0x3000 */ - PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3), - PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3), - PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3), - PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3), - PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3), - PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3), - PIN_RESERVED, - /* Offset 0x301c */ - PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN_RESERVED, - /* Offset 0x3038 */ - PIN(PEX_L0_RST_N_PA0, PE0, RSVD1, RSVD2, RSVD3), - PIN(PEX_L0_CLKREQ_N_PA1, PE0, RSVD1, RSVD2, RSVD3), - PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3), - PIN(PEX_L1_RST_N_PA3, PE1, RSVD1, RSVD2, RSVD3), - PIN(PEX_L1_CLKREQ_N_PA4, PE1, RSVD1, RSVD2, RSVD3), - PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3), - PIN(SPI1_MOSI_PC0, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI1_MISO_PC1, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI2_MOSI_PB4, SPI2, DTV, RSVD2, RSVD3), - PIN(SPI2_MISO_PB5, SPI2, DTV, RSVD2, RSVD3), - PIN(SPI2_SCK_PB6, SPI2, DTV, RSVD2, RSVD3), - PIN(SPI2_CS0_PB7, SPI2, DTV, RSVD2, RSVD3), - PIN(SPI2_CS1_PDD0, SPI2, RSVD1, RSVD2, RSVD3), - PIN(SPI4_MOSI_PC7, SPI4, RSVD1, RSVD2, RSVD3), - PIN(SPI4_MISO_PD0, SPI4, RSVD1, RSVD2, RSVD3), - PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3), - PIN(SPI4_CS0_PC6, SPI4, RSVD1, RSVD2, RSVD3), - PIN(QSPI_SCK_PEE0, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_CS_N_PEE1, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_IO0_PEE2, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_IO1_PEE3, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_IO2_PEE4, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_IO3_PEE5, QSPI, RSVD1, RSVD2, RSVD3), - PIN_RESERVED, - /* Offset 0x30a4 */ - PIN(DMIC1_CLK_PE0, DMIC1, I2S3, RSVD2, RSVD3), - PIN(DMIC1_DAT_PE1, DMIC1, I2S3, RSVD2, RSVD3), - PIN(DMIC2_CLK_PE2, DMIC2, I2S3, RSVD2, RSVD3), - PIN(DMIC2_DAT_PE3, DMIC2, I2S3, RSVD2, RSVD3), - PIN(DMIC3_CLK_PE4, DMIC3, I2S5A, RSVD2, RSVD3), - PIN(DMIC3_DAT_PE5, DMIC3, I2S5A, RSVD2, RSVD3), - PIN(GEN1_I2C_SCL_PJ1, I2C1, RSVD1, RSVD2, RSVD3), - PIN(GEN1_I2C_SDA_PJ0, I2C1, RSVD1, RSVD2, RSVD3), - PIN(GEN2_I2C_SCL_PJ2, I2C2, RSVD1, RSVD2, RSVD3), - PIN(GEN2_I2C_SDA_PJ3, I2C2, RSVD1, RSVD2, RSVD3), - PIN(GEN3_I2C_SCL_PF0, I2C3, RSVD1, RSVD2, RSVD3), - PIN(GEN3_I2C_SDA_PF1, I2C3, RSVD1, RSVD2, RSVD3), - PIN(CAM_I2C_SCL_PS2, I2C3, I2CVI, RSVD2, RSVD3), - PIN(CAM_I2C_SDA_PS3, I2C3, I2CVI, RSVD2, RSVD3), - PIN(PWR_I2C_SCL_PY3, I2CPMU, RSVD1, RSVD2, RSVD3), - PIN(PWR_I2C_SDA_PY4, I2CPMU, RSVD1, RSVD2, RSVD3), - PIN(UART1_TX_PU0, UARTA, RSVD1, RSVD2, RSVD3), - PIN(UART1_RX_PU1, UARTA, RSVD1, RSVD2, RSVD3), - PIN(UART1_RTS_PU2, UARTA, RSVD1, RSVD2, RSVD3), - PIN(UART1_CTS_PU3, UARTA, RSVD1, RSVD2, RSVD3), - PIN(UART2_TX_PG0, UARTB, I2S4A, SPDIF, UART), - PIN(UART2_RX_PG1, UARTB, I2S4A, SPDIF, UART), - PIN(UART2_RTS_PG2, UARTB, I2S4A, RSVD2, UART), - PIN(UART2_CTS_PG3, UARTB, I2S4A, RSVD2, UART), - PIN(UART3_TX_PD1, UARTC, SPI4, RSVD2, RSVD3), - PIN(UART3_RX_PD2, UARTC, SPI4, RSVD2, RSVD3), - PIN(UART3_RTS_PD3, UARTC, SPI4, RSVD2, RSVD3), - PIN(UART3_CTS_PD4, UARTC, SPI4, RSVD2, RSVD3), - PIN(UART4_TX_PI4, UARTD, UART, RSVD2, RSVD3), - PIN(UART4_RX_PI5, UARTD, UART, RSVD2, RSVD3), - PIN(UART4_RTS_PI6, UARTD, UART, RSVD2, RSVD3), - PIN(UART4_CTS_PI7, UARTD, UART, RSVD2, RSVD3), - PIN(DAP1_FS_PB0, I2S1, RSVD1, RSVD2, RSVD3), - PIN(DAP1_DIN_PB1, I2S1, RSVD1, RSVD2, RSVD3), - PIN(DAP1_DOUT_PB2, I2S1, RSVD1, RSVD2, RSVD3), - PIN(DAP1_SCLK_PB3, I2S1, RSVD1, RSVD2, RSVD3), - PIN(DAP2_FS_PAA0, I2S2, RSVD1, RSVD2, RSVD3), - PIN(DAP2_DIN_PAA2, I2S2, RSVD1, RSVD2, RSVD3), - PIN(DAP2_DOUT_PAA3, I2S2, RSVD1, RSVD2, RSVD3), - PIN(DAP2_SCLK_PAA1, I2S2, RSVD1, RSVD2, RSVD3), - PIN(DAP4_FS_PJ4, I2S4B, RSVD1, RSVD2, RSVD3), - PIN(DAP4_DIN_PJ5, I2S4B, RSVD1, RSVD2, RSVD3), - PIN(DAP4_DOUT_PJ6, I2S4B, RSVD1, RSVD2, RSVD3), - PIN(DAP4_SCLK_PJ7, I2S4B, RSVD1, RSVD2, RSVD3), - PIN(CAM1_MCLK_PS0, EXTPERIPH3, RSVD1, RSVD2, RSVD3), - PIN(CAM2_MCLK_PS1, EXTPERIPH3, RSVD1, RSVD2, RSVD3), - PIN(JTAG_RTCK, JTAG, RSVD1, RSVD2, RSVD3), - PIN(CLK_32K_IN, CLK, RSVD1, RSVD2, RSVD3), - PIN(CLK_32K_OUT_PY5, SOC, BLINK, RSVD2, RSVD3), - PIN(BATT_BCL, BCL, RSVD1, RSVD2, RSVD3), - PIN(CLK_REQ, SYS, RSVD1, RSVD2, RSVD3), - PIN(CPU_PWR_REQ, CPU, RSVD1, RSVD2, RSVD3), - PIN(PWR_INT_N, PMI, RSVD1, RSVD2, RSVD3), - PIN(SHUTDOWN, SHUTDOWN, RSVD1, RSVD2, RSVD3), - PIN(CORE_PWR_REQ, CORE, RSVD1, RSVD2, RSVD3), - PIN(AUD_MCLK_PBB0, AUD, RSVD1, RSVD2, RSVD3), - PIN(DVFS_PWM_PBB1, RSVD0, CLDVFS, SPI3, RSVD3), - PIN(DVFS_CLK_PBB2, RSVD0, CLDVFS, SPI3, RSVD3), - PIN(GPIO_X1_AUD_PBB3, RSVD0, RSVD1, SPI3, RSVD3), - PIN(GPIO_X3_AUD_PBB4, RSVD0, RSVD1, SPI3, RSVD3), - PIN(PCC7, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(HDMI_CEC_PCC0, CEC, RSVD1, RSVD2, RSVD3), - PIN(HDMI_INT_DP_HPD_PCC1, DP, RSVD1, RSVD2, RSVD3), - PIN(SPDIF_OUT_PCC2, SPDIF, RSVD1, RSVD2, RSVD3), - PIN(SPDIF_IN_PCC3, SPDIF, RSVD1, RSVD2, RSVD3), - PIN(USB_VBUS_EN0_PCC4, USB, RSVD1, RSVD2, RSVD3), - PIN(USB_VBUS_EN1_PCC5, USB, RSVD1, RSVD2, RSVD3), - PIN(DP_HPD0_PCC6, DP, RSVD1, RSVD2, RSVD3), - PIN(WIFI_EN_PH0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(WIFI_RST_PH1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(WIFI_WAKE_AP_PH2, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(AP_WAKE_BT_PH3, RSVD0, UARTB, SPDIF, RSVD3), - PIN(BT_RST_PH4, RSVD0, UARTB, SPDIF, RSVD3), - PIN(BT_WAKE_AP_PH5, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(AP_WAKE_NFC_PH7, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(NFC_EN_PI0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(NFC_INT_PI1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(GPS_EN_PI2, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(GPS_RST_PI3, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(CAM_RST_PS4, VGP1, RSVD1, RSVD2, RSVD3), - PIN(CAM_AF_EN_PS5, VIMCLK, VGP2, RSVD2, RSVD3), - PIN(CAM_FLASH_EN_PS6, VIMCLK, VGP3, RSVD2, RSVD3), - PIN(CAM1_PWDN_PS7, VGP4, RSVD1, RSVD2, RSVD3), - PIN(CAM2_PWDN_PT0, VGP5, RSVD1, RSVD2, RSVD3), - PIN(CAM1_STROBE_PT1, VGP6, RSVD1, RSVD2, RSVD3), - PIN(LCD_TE_PY2, DISPLAYA, RSVD1, RSVD2, RSVD3), - PIN(LCD_BL_PWM_PV0, DISPLAYA, PWM0, SOR0, RSVD3), - PIN(LCD_BL_EN_PV1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(LCD_RST_PV2, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(LCD_GPIO1_PV3, DISPLAYB, RSVD1, RSVD2, RSVD3), - PIN(LCD_GPIO2_PV4, DISPLAYB, PWM1, RSVD2, SOR1), - PIN(AP_READY_PV5, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(TOUCH_RST_PV6, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(TOUCH_CLK_PV7, TOUCH, RSVD1, RSVD2, RSVD3), - PIN(MODEM_WAKE_AP_PX0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(TOUCH_INT_PX1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(MOTION_INT_PX2, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(ALS_PROX_INT_PX3, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(TEMP_ALERT_PX4, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_POWER_ON_PX5, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_VOL_UP_PX6, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_VOL_DOWN_PX7, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_SLIDE_SW_PY0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_HOME_PY1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(PA6, SATA, RSVD1, RSVD2, RSVD3), - PIN(PE6, RSVD0, I2S5A, PWM2, RSVD3), - PIN(PE7, RSVD0, I2S5A, PWM3, RSVD3), - PIN(PH6, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(PK0, IQC0, I2S5B, RSVD2, RSVD3), - PIN(PK1, IQC0, I2S5B, RSVD2, RSVD3), - PIN(PK2, IQC0, I2S5B, RSVD2, RSVD3), - PIN(PK3, IQC0, I2S5B, RSVD2, RSVD3), - PIN(PK4, IQC1, RSVD1, RSVD2, RSVD3), - PIN(PK5, IQC1, RSVD1, RSVD2, RSVD3), - PIN(PK6, IQC1, RSVD1, RSVD2, RSVD3), - PIN(PK7, IQC1, RSVD1, RSVD2, RSVD3), - PIN(PL0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(PL1, SOC, RSVD1, RSVD2, RSVD3), - PIN(PZ0, VIMCLK2, RSVD1, RSVD2, RSVD3), - PIN(PZ1, VIMCLK2, SDMMC1, RSVD2, RSVD3), - PIN(PZ2, SDMMC3, CCLA, RSVD2, RSVD3), - PIN(PZ3, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(PZ4, SDMMC1, RSVD1, RSVD2, RSVD3), - PIN(PZ5, SOC, RSVD1, RSVD2, RSVD3), -}; -const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups; diff --git a/arch/arm/mach-tegra/tegra210/pinmux.c b/arch/arm/mach-tegra/tegra210/pinmux.c new file mode 100644 index 00000000000..a29c76b1fae --- /dev/null +++ b/arch/arm/mach-tegra/tegra210/pinmux.c @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define PIN(pin, f0, f1, f2, f3) \ + { \ + .funcs = { \ + PMUX_FUNC_##f0, \ + PMUX_FUNC_##f1, \ + PMUX_FUNC_##f2, \ + PMUX_FUNC_##f3, \ + }, \ + } + +#define PIN_RESERVED {} + +static const struct pmux_pingrp_desc tegra210_pingroups[] = { + /* pin, f0, f1, f2, f3 */ + /* Offset 0x3000 */ + PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3), + PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3), + PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3), + PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3), + PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3), + PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3), + PIN_RESERVED, + /* Offset 0x301c */ + PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN_RESERVED, + /* Offset 0x3038 */ + PIN(PEX_L0_RST_N_PA0, PE0, RSVD1, RSVD2, RSVD3), + PIN(PEX_L0_CLKREQ_N_PA1, PE0, RSVD1, RSVD2, RSVD3), + PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3), + PIN(PEX_L1_RST_N_PA3, PE1, RSVD1, RSVD2, RSVD3), + PIN(PEX_L1_CLKREQ_N_PA4, PE1, RSVD1, RSVD2, RSVD3), + PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3), + PIN(SPI1_MOSI_PC0, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI1_MISO_PC1, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI2_MOSI_PB4, SPI2, DTV, RSVD2, RSVD3), + PIN(SPI2_MISO_PB5, SPI2, DTV, RSVD2, RSVD3), + PIN(SPI2_SCK_PB6, SPI2, DTV, RSVD2, RSVD3), + PIN(SPI2_CS0_PB7, SPI2, DTV, RSVD2, RSVD3), + PIN(SPI2_CS1_PDD0, SPI2, RSVD1, RSVD2, RSVD3), + PIN(SPI4_MOSI_PC7, SPI4, RSVD1, RSVD2, RSVD3), + PIN(SPI4_MISO_PD0, SPI4, RSVD1, RSVD2, RSVD3), + PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3), + PIN(SPI4_CS0_PC6, SPI4, RSVD1, RSVD2, RSVD3), + PIN(QSPI_SCK_PEE0, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_CS_N_PEE1, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_IO0_PEE2, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_IO1_PEE3, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_IO2_PEE4, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_IO3_PEE5, QSPI, RSVD1, RSVD2, RSVD3), + PIN_RESERVED, + /* Offset 0x30a4 */ + PIN(DMIC1_CLK_PE0, DMIC1, I2S3, RSVD2, RSVD3), + PIN(DMIC1_DAT_PE1, DMIC1, I2S3, RSVD2, RSVD3), + PIN(DMIC2_CLK_PE2, DMIC2, I2S3, RSVD2, RSVD3), + PIN(DMIC2_DAT_PE3, DMIC2, I2S3, RSVD2, RSVD3), + PIN(DMIC3_CLK_PE4, DMIC3, I2S5A, RSVD2, RSVD3), + PIN(DMIC3_DAT_PE5, DMIC3, I2S5A, RSVD2, RSVD3), + PIN(GEN1_I2C_SCL_PJ1, I2C1, RSVD1, RSVD2, RSVD3), + PIN(GEN1_I2C_SDA_PJ0, I2C1, RSVD1, RSVD2, RSVD3), + PIN(GEN2_I2C_SCL_PJ2, I2C2, RSVD1, RSVD2, RSVD3), + PIN(GEN2_I2C_SDA_PJ3, I2C2, RSVD1, RSVD2, RSVD3), + PIN(GEN3_I2C_SCL_PF0, I2C3, RSVD1, RSVD2, RSVD3), + PIN(GEN3_I2C_SDA_PF1, I2C3, RSVD1, RSVD2, RSVD3), + PIN(CAM_I2C_SCL_PS2, I2C3, I2CVI, RSVD2, RSVD3), + PIN(CAM_I2C_SDA_PS3, I2C3, I2CVI, RSVD2, RSVD3), + PIN(PWR_I2C_SCL_PY3, I2CPMU, RSVD1, RSVD2, RSVD3), + PIN(PWR_I2C_SDA_PY4, I2CPMU, RSVD1, RSVD2, RSVD3), + PIN(UART1_TX_PU0, UARTA, RSVD1, RSVD2, RSVD3), + PIN(UART1_RX_PU1, UARTA, RSVD1, RSVD2, RSVD3), + PIN(UART1_RTS_PU2, UARTA, RSVD1, RSVD2, RSVD3), + PIN(UART1_CTS_PU3, UARTA, RSVD1, RSVD2, RSVD3), + PIN(UART2_TX_PG0, UARTB, I2S4A, SPDIF, UART), + PIN(UART2_RX_PG1, UARTB, I2S4A, SPDIF, UART), + PIN(UART2_RTS_PG2, UARTB, I2S4A, RSVD2, UART), + PIN(UART2_CTS_PG3, UARTB, I2S4A, RSVD2, UART), + PIN(UART3_TX_PD1, UARTC, SPI4, RSVD2, RSVD3), + PIN(UART3_RX_PD2, UARTC, SPI4, RSVD2, RSVD3), + PIN(UART3_RTS_PD3, UARTC, SPI4, RSVD2, RSVD3), + PIN(UART3_CTS_PD4, UARTC, SPI4, RSVD2, RSVD3), + PIN(UART4_TX_PI4, UARTD, UART, RSVD2, RSVD3), + PIN(UART4_RX_PI5, UARTD, UART, RSVD2, RSVD3), + PIN(UART4_RTS_PI6, UARTD, UART, RSVD2, RSVD3), + PIN(UART4_CTS_PI7, UARTD, UART, RSVD2, RSVD3), + PIN(DAP1_FS_PB0, I2S1, RSVD1, RSVD2, RSVD3), + PIN(DAP1_DIN_PB1, I2S1, RSVD1, RSVD2, RSVD3), + PIN(DAP1_DOUT_PB2, I2S1, RSVD1, RSVD2, RSVD3), + PIN(DAP1_SCLK_PB3, I2S1, RSVD1, RSVD2, RSVD3), + PIN(DAP2_FS_PAA0, I2S2, RSVD1, RSVD2, RSVD3), + PIN(DAP2_DIN_PAA2, I2S2, RSVD1, RSVD2, RSVD3), + PIN(DAP2_DOUT_PAA3, I2S2, RSVD1, RSVD2, RSVD3), + PIN(DAP2_SCLK_PAA1, I2S2, RSVD1, RSVD2, RSVD3), + PIN(DAP4_FS_PJ4, I2S4B, RSVD1, RSVD2, RSVD3), + PIN(DAP4_DIN_PJ5, I2S4B, RSVD1, RSVD2, RSVD3), + PIN(DAP4_DOUT_PJ6, I2S4B, RSVD1, RSVD2, RSVD3), + PIN(DAP4_SCLK_PJ7, I2S4B, RSVD1, RSVD2, RSVD3), + PIN(CAM1_MCLK_PS0, EXTPERIPH3, RSVD1, RSVD2, RSVD3), + PIN(CAM2_MCLK_PS1, EXTPERIPH3, RSVD1, RSVD2, RSVD3), + PIN(JTAG_RTCK, JTAG, RSVD1, RSVD2, RSVD3), + PIN(CLK_32K_IN, CLK, RSVD1, RSVD2, RSVD3), + PIN(CLK_32K_OUT_PY5, SOC, BLINK, RSVD2, RSVD3), + PIN(BATT_BCL, BCL, RSVD1, RSVD2, RSVD3), + PIN(CLK_REQ, SYS, RSVD1, RSVD2, RSVD3), + PIN(CPU_PWR_REQ, CPU, RSVD1, RSVD2, RSVD3), + PIN(PWR_INT_N, PMI, RSVD1, RSVD2, RSVD3), + PIN(SHUTDOWN, SHUTDOWN, RSVD1, RSVD2, RSVD3), + PIN(CORE_PWR_REQ, CORE, RSVD1, RSVD2, RSVD3), + PIN(AUD_MCLK_PBB0, AUD, RSVD1, RSVD2, RSVD3), + PIN(DVFS_PWM_PBB1, RSVD0, CLDVFS, SPI3, RSVD3), + PIN(DVFS_CLK_PBB2, RSVD0, CLDVFS, SPI3, RSVD3), + PIN(GPIO_X1_AUD_PBB3, RSVD0, RSVD1, SPI3, RSVD3), + PIN(GPIO_X3_AUD_PBB4, RSVD0, RSVD1, SPI3, RSVD3), + PIN(PCC7, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(HDMI_CEC_PCC0, CEC, RSVD1, RSVD2, RSVD3), + PIN(HDMI_INT_DP_HPD_PCC1, DP, RSVD1, RSVD2, RSVD3), + PIN(SPDIF_OUT_PCC2, SPDIF, RSVD1, RSVD2, RSVD3), + PIN(SPDIF_IN_PCC3, SPDIF, RSVD1, RSVD2, RSVD3), + PIN(USB_VBUS_EN0_PCC4, USB, RSVD1, RSVD2, RSVD3), + PIN(USB_VBUS_EN1_PCC5, USB, RSVD1, RSVD2, RSVD3), + PIN(DP_HPD0_PCC6, DP, RSVD1, RSVD2, RSVD3), + PIN(WIFI_EN_PH0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(WIFI_RST_PH1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(WIFI_WAKE_AP_PH2, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(AP_WAKE_BT_PH3, RSVD0, UARTB, SPDIF, RSVD3), + PIN(BT_RST_PH4, RSVD0, UARTB, SPDIF, RSVD3), + PIN(BT_WAKE_AP_PH5, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(AP_WAKE_NFC_PH7, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(NFC_EN_PI0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(NFC_INT_PI1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(GPS_EN_PI2, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(GPS_RST_PI3, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(CAM_RST_PS4, VGP1, RSVD1, RSVD2, RSVD3), + PIN(CAM_AF_EN_PS5, VIMCLK, VGP2, RSVD2, RSVD3), + PIN(CAM_FLASH_EN_PS6, VIMCLK, VGP3, RSVD2, RSVD3), + PIN(CAM1_PWDN_PS7, VGP4, RSVD1, RSVD2, RSVD3), + PIN(CAM2_PWDN_PT0, VGP5, RSVD1, RSVD2, RSVD3), + PIN(CAM1_STROBE_PT1, VGP6, RSVD1, RSVD2, RSVD3), + PIN(LCD_TE_PY2, DISPLAYA, RSVD1, RSVD2, RSVD3), + PIN(LCD_BL_PWM_PV0, DISPLAYA, PWM0, SOR0, RSVD3), + PIN(LCD_BL_EN_PV1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(LCD_RST_PV2, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(LCD_GPIO1_PV3, DISPLAYB, RSVD1, RSVD2, RSVD3), + PIN(LCD_GPIO2_PV4, DISPLAYB, PWM1, RSVD2, SOR1), + PIN(AP_READY_PV5, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(TOUCH_RST_PV6, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(TOUCH_CLK_PV7, TOUCH, RSVD1, RSVD2, RSVD3), + PIN(MODEM_WAKE_AP_PX0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(TOUCH_INT_PX1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(MOTION_INT_PX2, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(ALS_PROX_INT_PX3, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(TEMP_ALERT_PX4, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_POWER_ON_PX5, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_VOL_UP_PX6, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_VOL_DOWN_PX7, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_SLIDE_SW_PY0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_HOME_PY1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(PA6, SATA, RSVD1, RSVD2, RSVD3), + PIN(PE6, RSVD0, I2S5A, PWM2, RSVD3), + PIN(PE7, RSVD0, I2S5A, PWM3, RSVD3), + PIN(PH6, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(PK0, IQC0, I2S5B, RSVD2, RSVD3), + PIN(PK1, IQC0, I2S5B, RSVD2, RSVD3), + PIN(PK2, IQC0, I2S5B, RSVD2, RSVD3), + PIN(PK3, IQC0, I2S5B, RSVD2, RSVD3), + PIN(PK4, IQC1, RSVD1, RSVD2, RSVD3), + PIN(PK5, IQC1, RSVD1, RSVD2, RSVD3), + PIN(PK6, IQC1, RSVD1, RSVD2, RSVD3), + PIN(PK7, IQC1, RSVD1, RSVD2, RSVD3), + PIN(PL0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(PL1, SOC, RSVD1, RSVD2, RSVD3), + PIN(PZ0, VIMCLK2, RSVD1, RSVD2, RSVD3), + PIN(PZ1, VIMCLK2, SDMMC1, RSVD2, RSVD3), + PIN(PZ2, SDMMC3, CCLA, RSVD2, RSVD3), + PIN(PZ3, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(PZ4, SDMMC1, RSVD1, RSVD2, RSVD3), + PIN(PZ5, SOC, RSVD1, RSVD2, RSVD3), +}; +const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups; -- cgit v1.3.1 From c21478bc6e527f57cb2e3251c7d6baa3e54514c2 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 25 Mar 2015 12:04:35 -0600 Subject: ARM: tegra: pinctrl: minor cleanup Move struct pmux_pingrp_desc type and tegra_soc_pingroups variable declaration together with other pin/mux level definitions. Now the whole file is grouped/ordered pin/mux-related then drvgrp-related definitions. Fix typo in ifdef comment. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/pinmux.h | 20 ++++++++++---------- arch/arm/mach-tegra/pinmux-common.c | 2 +- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index 4212e576993..e3eb706fcb8 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -170,6 +170,16 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, int len); +struct pmux_pingrp_desc { + u8 funcs[4]; +#if defined(CONFIG_TEGRA20) + u8 ctl_id; + u8 pull_id; +#endif /* CONFIG_TEGRA20 */ +}; + +extern const struct pmux_pingrp_desc *tegra_soc_pingroups; + #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS #define PMUX_SLWF_MIN 0 @@ -219,14 +229,4 @@ void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, #endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ -struct pmux_pingrp_desc { - u8 funcs[4]; -#if defined(CONFIG_TEGRA20) - u8 ctl_id; - u8 pull_id; -#endif /* CONFIG_TEGRA20 */ -}; - -extern const struct pmux_pingrp_desc *tegra_soc_pingroups; - #endif /* _TEGRA_PINMUX_H_ */ diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index 912f65e98b0..96dbb5e89b7 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -695,4 +695,4 @@ void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, for (i = 0; i < len; i++) pinmux_config_drvgrp(&config[i]); } -#endif /* TEGRA_PMX_HAS_DRVGRPS */ +#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ -- cgit v1.3.1 From 5ee7ec7bafe6d02ebacdde06bb536f55cff4cdd8 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 25 Mar 2015 12:04:36 -0600 Subject: ARM: tegra: pinctrl: add support for MIPI PAD control groups Some pinmux controls are in a different register set. Add support for manipulating those in a similar way to existing pins/groups. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/pinmux.h | 16 +++++++++ arch/arm/mach-tegra/pinmux-common.c | 57 ++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index e3eb706fcb8..3cc52dd7731 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -229,4 +229,20 @@ void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, #endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ +#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS +struct pmux_mipipadctrlgrp_config { + u32 grp:16; /* pin group PMUX_MIPIPADCTRLGRP_x */ + u32 func:8; /* function to assign PMUX_FUNC_... */ +}; + +void pinmux_config_mipipadctrlgrp_table( + const struct pmux_mipipadctrlgrp_config *config, int len); + +struct pmux_mipipadctrlgrp_desc { + u8 funcs[2]; +}; + +extern const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups; +#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */ + #endif /* _TEGRA_PINMUX_H_ */ diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index 96dbb5e89b7..b4a1432afcb 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -108,6 +108,8 @@ #define DRV_REG(group) _R(TEGRA_PMX_SOC_DRV_GROUP_BASE_REG + ((group) * 4)) +#define MIPIPADCTRL_REG(group) _R(TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG + ((group) * 4)) + /* * We could force arch-tegraNN/pinmux.h to define all of these. However, * that's a lot of defines, and for now it's manageable to just put a @@ -696,3 +698,58 @@ void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, pinmux_config_drvgrp(&config[i]); } #endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ + +#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS + +#define pmux_mipipadctrlgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_MIPIPADCTRLGRP_COUNT)) + +static void pinmux_mipipadctrl_set_func(enum pmux_mipipadctrlgrp grp, + enum pmux_func func) +{ + u32 *reg = MIPIPADCTRL_REG(grp); + int i, mux = -1; + u32 val; + + if (func == PMUX_FUNC_DEFAULT) + return; + + /* Error check grp and func */ + assert(pmux_mipipadctrlgrp_isvalid(grp)); + assert(pmux_func_isvalid(func)); + + if (func >= PMUX_FUNC_RSVD1) { + mux = (func - PMUX_FUNC_RSVD1) & 1; + } else { + /* Search for the appropriate function */ + for (i = 0; i < 2; i++) { + if (tegra_soc_mipipadctrl_groups[grp].funcs[i] + == func) { + mux = i; + break; + } + } + } + assert(mux != -1); + + val = readl(reg); + val &= ~(1 << 1); + val |= (mux << 1); + writel(val, reg); +} + +static void pinmux_config_mipipadctrlgrp(const struct pmux_mipipadctrlgrp_config *config) +{ + enum pmux_mipipadctrlgrp grp = config->grp; + + pinmux_mipipadctrl_set_func(grp, config->func); +} + +void pinmux_config_mipipadctrlgrp_table( + const struct pmux_mipipadctrlgrp_config *config, int len) +{ + int i; + + for (i = 0; i < len; i++) + pinmux_config_mipipadctrlgrp(&config[i]); +} +#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */ -- cgit v1.3.1 From 89d9437356ce9121f99889c11b55ed28fb8851b2 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 25 Mar 2015 12:04:37 -0600 Subject: ARM: tegra: enable MIPI PAD CTRL support for Tegra124 This allows selection between CSI and DSI_B on the MIPI pads. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra124/pinmux.h | 9 +++++++++ arch/arm/mach-tegra/tegra124/pinmux.c | 17 +++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h index 78bc9e6f178..9fcbb0f80b4 100644 --- a/arch/arm/include/asm/arch-tegra124/pinmux.h +++ b/arch/arm/include/asm/arch-tegra124/pinmux.h @@ -246,6 +246,11 @@ enum pmux_drvgrp { PMUX_DRVGRP_COUNT, }; +enum pmux_mipipadctrlgrp { + PMUX_MIPIPADCTRLGRP_DSI_B, + PMUX_MIPIPADCTRLGRP_COUNT, +}; + enum pmux_func { PMUX_FUNC_DEFAULT, PMUX_FUNC_BLINK, @@ -255,6 +260,7 @@ enum pmux_func { PMUX_FUNC_CLK, PMUX_FUNC_CLK12, PMUX_FUNC_CPU, + PMUX_FUNC_CSI, PMUX_FUNC_DAP, PMUX_FUNC_DAP1, PMUX_FUNC_DAP2, @@ -263,6 +269,7 @@ enum pmux_func { PMUX_FUNC_DISPLAYA_ALT, PMUX_FUNC_DISPLAYB, PMUX_FUNC_DP, + PMUX_FUNC_DSI_B, PMUX_FUNC_DTV, PMUX_FUNC_EXTPERIPH1, PMUX_FUNC_EXTPERIPH2, @@ -336,8 +343,10 @@ enum pmux_func { }; #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 +#define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING #define TEGRA_PMX_SOC_HAS_DRVGRPS +#define TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS #define TEGRA_PMX_GRPS_HAVE_LPMD #define TEGRA_PMX_GRPS_HAVE_SCHMT #define TEGRA_PMX_GRPS_HAVE_HSM diff --git a/arch/arm/mach-tegra/tegra124/pinmux.c b/arch/arm/mach-tegra/tegra124/pinmux.c index c6685eaae1e..4629b4676c4 100644 --- a/arch/arm/mach-tegra/tegra124/pinmux.c +++ b/arch/arm/mach-tegra/tegra124/pinmux.c @@ -304,3 +304,20 @@ static const struct pmux_pingrp_desc tegra124_pingroups[] = { PIN(DP_HPD_PFF0, DP, RSVD2, RSVD3, RSVD4), }; const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra124_pingroups; + +#define MIPIPADCTRL_GRP(grp, f0, f1) \ + { \ + .funcs = { \ + PMUX_FUNC_##f0, \ + PMUX_FUNC_##f1, \ + }, \ + } + +#define MIPIPADCTRL_RESERVED {} + +static const struct pmux_mipipadctrlgrp_desc tegra124_mipipadctrl_groups[] = { + /* pin, f0, f1 */ + /* Offset 0x820 */ + MIPIPADCTRL_GRP(DSI_B, CSI, DSI_B), +}; +const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups = tegra124_mipipadctrl_groups; -- cgit v1.3.1 From a101638ece27fe8c4b42c654c047d0eacc92b1a8 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 9 Mar 2015 19:12:56 -0600 Subject: tegra: seaboard: Remove unused CONFIG_UART_DISABLE_GPIO This CONFIG is not used, so drop it. Signed-off-by: Simon Glass Tested-by: Stephen Warren Acked-by: Stephen Warren Signed-off-by: Tom Warren --- include/configs/seaboard.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 4442064db91..78ff651d061 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -27,9 +27,6 @@ #define CONFIG_TEGRA_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -/* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */ -#define CONFIG_UART_DISABLE_GPIO GPIO_PI3 - #define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD /* I2C */ -- cgit v1.3.1 From 37220efab846ece7cdfc7a8fba3d8294adc6093d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 9 Mar 2015 19:12:57 -0600 Subject: tegra: seaboard: Correct the gpio_request() call Requesting a GPIO without a name is not supposed anymore. This causes the request to fail. Add a name so that the serial console works on seaboard. Signed-off-by: Simon Glass Reported-by: Stephen Warren Signed-off-by: Tom Warren --- board/nvidia/seaboard/seaboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 25480e481d2..2d07001800e 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -20,7 +20,7 @@ void gpio_early_init_uart(void) { /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */ - gpio_request(GPIO_PI3, NULL); + gpio_request(GPIO_PI3, "uart_en"); gpio_direction_output(GPIO_PI3, 0); } #endif -- cgit v1.3.1 From d1db97aaa43d6ae5e1e790e872f79d36d8809660 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 26 Mar 2015 01:31:53 +0100 Subject: ARM: tegra: get rid of colibri_t20-common As a preparatory step to renaming the board folder as well first get rid of the colibri_t20-common after having integrated it into colibri_t20_iris for now. While at it also migrate to using NVIDIA's common.mk magic. Signed-off-by: Marcel Ziswiler Signed-off-by: Tom Warren --- .../colibri_t20-common/colibri_t20-common.c | 35 ------------------ .../colibri_t20-common/colibri_t20-common.h | 7 ---- board/toradex/colibri_t20_iris/Makefile | 4 +-- board/toradex/colibri_t20_iris/colibri_t20_iris.c | 42 +++++++++++++++------- 4 files changed, 31 insertions(+), 57 deletions(-) delete mode 100644 board/toradex/colibri_t20-common/colibri_t20-common.c delete mode 100644 board/toradex/colibri_t20-common/colibri_t20-common.h diff --git a/board/toradex/colibri_t20-common/colibri_t20-common.c b/board/toradex/colibri_t20-common/colibri_t20-common.c deleted file mode 100644 index 58a9916f0ad..00000000000 --- a/board/toradex/colibri_t20-common/colibri_t20-common.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2012 Lucas Stach - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#include "colibri_t20-common.h" - -#ifdef CONFIG_USB_EHCI_TEGRA -void colibri_t20_common_pin_mux_usb(void) -{ - /* module internal USB bus to connect ethernet chipset */ - funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); - /* ULPI reference clock output */ - pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); - pinmux_tristate_disable(PMUX_PINGRP_CDEV2); - /* PHY reset GPIO */ - pinmux_tristate_disable(PMUX_PINGRP_UAC); - /* VBus GPIO */ - pinmux_tristate_disable(PMUX_PINGRP_DTE); -} -#endif - -#ifdef CONFIG_TEGRA_NAND -void pin_mux_nand(void) -{ - funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT); -} -#endif diff --git a/board/toradex/colibri_t20-common/colibri_t20-common.h b/board/toradex/colibri_t20-common/colibri_t20-common.h deleted file mode 100644 index 1fe53f6073c..00000000000 --- a/board/toradex/colibri_t20-common/colibri_t20-common.h +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (C) 2012 Lucas Stach - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -void colibri_t20_common_pin_mux_usb(void); diff --git a/board/toradex/colibri_t20_iris/Makefile b/board/toradex/colibri_t20_iris/Makefile index ebeac70ea14..f286aec041b 100644 --- a/board/toradex/colibri_t20_iris/Makefile +++ b/board/toradex/colibri_t20_iris/Makefile @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := ../../nvidia/common/board.o -obj-y += ../colibri_t20-common/colibri_t20-common.o +include $(srctree)/board/nvidia/common/common.mk + obj-y += colibri_t20_iris.o diff --git a/board/toradex/colibri_t20_iris/colibri_t20_iris.c b/board/toradex/colibri_t20_iris/colibri_t20_iris.c index 49c74f34f1e..46560948a64 100644 --- a/board/toradex/colibri_t20_iris/colibri_t20_iris.c +++ b/board/toradex/colibri_t20_iris/colibri_t20_iris.c @@ -5,23 +5,11 @@ */ #include -#include #include #include #include #include - -#include "../colibri_t20-common/colibri_t20-common.h" - -#ifdef CONFIG_USB_EHCI_TEGRA -void pin_mux_usb(void) -{ - colibri_t20_common_pin_mux_usb(); - - /* USB 1 aka Tegra USB port 3 VBus*/ - pinmux_tristate_disable(PMUX_PINGRP_SPIG); -} -#endif +#include #ifdef CONFIG_TEGRA_MMC /* @@ -34,3 +22,31 @@ void pin_mux_mmc(void) pinmux_tristate_disable(PMUX_PINGRP_GMB); } #endif + +#ifdef CONFIG_TEGRA_NAND +void pin_mux_nand(void) +{ + funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT); +} +#endif + +#ifdef CONFIG_USB_EHCI_TEGRA +void pin_mux_usb(void) +{ + /* module internal USB bus to connect ethernet chipset */ + funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); + + /* ULPI reference clock output */ + pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); + pinmux_tristate_disable(PMUX_PINGRP_CDEV2); + + /* PHY reset GPIO */ + pinmux_tristate_disable(PMUX_PINGRP_UAC); + + /* VBus GPIO */ + pinmux_tristate_disable(PMUX_PINGRP_DTE); + + /* USB 1 aka Tegra USB port 3 VBus */ + pinmux_tristate_disable(PMUX_PINGRP_SPIG); +} +#endif -- cgit v1.3.1 From e57c6e5b50d330516e30f61b824613d551316086 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 26 Mar 2015 01:31:54 +0100 Subject: ARM: tegra: rename colibri_t20 board/configuration/device-tree In accordance with our other modules supported by U-Boot and as agreed upon for Apalis/Colibri T30 get rid of the carrier board in the board/ configuration/device-tree naming. While at it also bring the prompt more in line with our other products. Signed-off-by: Marcel Ziswiler Signed-off-by: Tom Warren --- arch/arm/dts/Makefile | 2 +- arch/arm/dts/tegra20-colibri.dts | 49 ++++++++++++++++++ arch/arm/dts/tegra20-colibri_t20_iris.dts | 49 ------------------ arch/arm/mach-tegra/tegra20/Kconfig | 4 +- board/toradex/colibri_t20/Kconfig | 12 +++++ board/toradex/colibri_t20/MAINTAINERS | 7 +++ board/toradex/colibri_t20/Makefile | 9 ++++ board/toradex/colibri_t20/colibri_t20.c | 52 +++++++++++++++++++ board/toradex/colibri_t20_iris/Kconfig | 12 ----- board/toradex/colibri_t20_iris/MAINTAINERS | 6 --- board/toradex/colibri_t20_iris/Makefile | 9 ---- board/toradex/colibri_t20_iris/colibri_t20_iris.c | 52 ------------------- configs/colibri_t20_defconfig | 5 ++ configs/colibri_t20_iris_defconfig | 5 -- include/configs/colibri_t20.h | 61 +++++++++++++++++++++++ include/configs/colibri_t20_iris.h | 61 ----------------------- tools/buildman/README | 2 +- 17 files changed, 199 insertions(+), 198 deletions(-) create mode 100644 arch/arm/dts/tegra20-colibri.dts delete mode 100644 arch/arm/dts/tegra20-colibri_t20_iris.dts create mode 100644 board/toradex/colibri_t20/Kconfig create mode 100644 board/toradex/colibri_t20/MAINTAINERS create mode 100644 board/toradex/colibri_t20/Makefile create mode 100644 board/toradex/colibri_t20/colibri_t20.c delete mode 100644 board/toradex/colibri_t20_iris/Kconfig delete mode 100644 board/toradex/colibri_t20_iris/MAINTAINERS delete mode 100644 board/toradex/colibri_t20_iris/Makefile delete mode 100644 board/toradex/colibri_t20_iris/colibri_t20_iris.c create mode 100644 configs/colibri_t20_defconfig delete mode 100644 configs/colibri_t20_iris_defconfig create mode 100644 include/configs/colibri_t20.h delete mode 100644 include/configs/colibri_t20_iris.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cbe5b867559..f897e6d969b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -24,7 +24,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-trimslice.dtb \ tegra20-ventana.dtb \ tegra20-whistler.dtb \ - tegra20-colibri_t20_iris.dtb \ + tegra20-colibri.dtb \ tegra30-apalis.dtb \ tegra30-beaver.dtb \ tegra30-cardhu.dtb \ diff --git a/arch/arm/dts/tegra20-colibri.dts b/arch/arm/dts/tegra20-colibri.dts new file mode 100644 index 00000000000..3131b9201b7 --- /dev/null +++ b/arch/arm/dts/tegra20-colibri.dts @@ -0,0 +1,49 @@ +/dts-v1/; + +#include "tegra20.dtsi" + +/ { + model = "Toradex Colibri T20"; + compatible = "toradex,t20", "nvidia,tegra20"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + usb0 = "/usb@c5008000"; + usb1 = "/usb@c5000000"; + usb2 = "/usb@c5004000"; + sdhci0 = "/sdhci@c8000600"; + }; + + usb@c5000000 { + dr_mode = "otg"; + }; + + usb@c5004000 { + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; + }; + + usb@c5008000 { + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + }; + + nand-controller@70008000 { + nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; + nvidia,width = <8>; + nvidia,timing = <15 100 25 80 25 10 15 10 100>; + + nand@0 { + reg = <0>; + compatible = "nand-flash"; + }; + }; + + sdhci@c8000600 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + bus-width = <4>; + }; +}; diff --git a/arch/arm/dts/tegra20-colibri_t20_iris.dts b/arch/arm/dts/tegra20-colibri_t20_iris.dts deleted file mode 100644 index 3131b9201b7..00000000000 --- a/arch/arm/dts/tegra20-colibri_t20_iris.dts +++ /dev/null @@ -1,49 +0,0 @@ -/dts-v1/; - -#include "tegra20.dtsi" - -/ { - model = "Toradex Colibri T20"; - compatible = "toradex,t20", "nvidia,tegra20"; - - chosen { - stdout-path = &uarta; - }; - - aliases { - usb0 = "/usb@c5008000"; - usb1 = "/usb@c5000000"; - usb2 = "/usb@c5004000"; - sdhci0 = "/sdhci@c8000600"; - }; - - usb@c5000000 { - dr_mode = "otg"; - }; - - usb@c5004000 { - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; - nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; - }; - - usb@c5008000 { - nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - }; - - nand-controller@70008000 { - nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; - nvidia,width = <8>; - nvidia,timing = <15 100 25 80 25 10 15 10 100>; - - nand@0 { - reg = <0>; - compatible = "nand-flash"; - }; - }; - - sdhci@c8000600 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; - bus-width = <4>; - }; -}; diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index a354e2ad1f6..7f09f819cc0 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -30,7 +30,7 @@ config TARGET_VENTANA config TARGET_WHISTLER bool "NVIDIA Tegra20 Whistler evaluation board" -config TARGET_COLIBRI_T20_IRIS +config TARGET_COLIBRI_T20 bool "Toradex Colibri T20 board" endchoice @@ -47,6 +47,6 @@ source "board/avionic-design/tec/Kconfig" source "board/compulab/trimslice/Kconfig" source "board/nvidia/ventana/Kconfig" source "board/nvidia/whistler/Kconfig" -source "board/toradex/colibri_t20_iris/Kconfig" +source "board/toradex/colibri_t20/Kconfig" endif diff --git a/board/toradex/colibri_t20/Kconfig b/board/toradex/colibri_t20/Kconfig new file mode 100644 index 00000000000..7f373b2d26b --- /dev/null +++ b/board/toradex/colibri_t20/Kconfig @@ -0,0 +1,12 @@ +if TARGET_COLIBRI_T20 + +config SYS_BOARD + default "colibri_t20" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "colibri_t20" + +endif diff --git a/board/toradex/colibri_t20/MAINTAINERS b/board/toradex/colibri_t20/MAINTAINERS new file mode 100644 index 00000000000..b251c000fe0 --- /dev/null +++ b/board/toradex/colibri_t20/MAINTAINERS @@ -0,0 +1,7 @@ +COLIBRI_T20 +M: Lucas Stach +S: Maintained +F: board/toradex/colibri_t20/ +F: include/configs/colibri_t20.h +F: configs/colibri_t20_defconfig +F: arch/arm/dts/tegra20-colibri.dtb diff --git a/board/toradex/colibri_t20/Makefile b/board/toradex/colibri_t20/Makefile new file mode 100644 index 00000000000..86f78d9d9d6 --- /dev/null +++ b/board/toradex/colibri_t20/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2012 Lucas Stach +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(srctree)/board/nvidia/common/common.mk + +obj-y += colibri_t20.o diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c new file mode 100644 index 00000000000..46560948a64 --- /dev/null +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2012 Lucas Stach + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_TEGRA_MMC +/* + * Routine: pin_mux_mmc + * Description: setup the pin muxes/tristate values for the SDMMC(s) + */ +void pin_mux_mmc(void) +{ + funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); + pinmux_tristate_disable(PMUX_PINGRP_GMB); +} +#endif + +#ifdef CONFIG_TEGRA_NAND +void pin_mux_nand(void) +{ + funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT); +} +#endif + +#ifdef CONFIG_USB_EHCI_TEGRA +void pin_mux_usb(void) +{ + /* module internal USB bus to connect ethernet chipset */ + funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); + + /* ULPI reference clock output */ + pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); + pinmux_tristate_disable(PMUX_PINGRP_CDEV2); + + /* PHY reset GPIO */ + pinmux_tristate_disable(PMUX_PINGRP_UAC); + + /* VBus GPIO */ + pinmux_tristate_disable(PMUX_PINGRP_DTE); + + /* USB 1 aka Tegra USB port 3 VBus */ + pinmux_tristate_disable(PMUX_PINGRP_SPIG); +} +#endif diff --git a/board/toradex/colibri_t20_iris/Kconfig b/board/toradex/colibri_t20_iris/Kconfig deleted file mode 100644 index 4bf727809ea..00000000000 --- a/board/toradex/colibri_t20_iris/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_COLIBRI_T20_IRIS - -config SYS_BOARD - default "colibri_t20_iris" - -config SYS_VENDOR - default "toradex" - -config SYS_CONFIG_NAME - default "colibri_t20_iris" - -endif diff --git a/board/toradex/colibri_t20_iris/MAINTAINERS b/board/toradex/colibri_t20_iris/MAINTAINERS deleted file mode 100644 index c68955bfa98..00000000000 --- a/board/toradex/colibri_t20_iris/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -COLIBRI_T20_IRIS BOARD -M: Lucas Stach -S: Maintained -F: board/toradex/colibri_t20_iris/ -F: include/configs/colibri_t20_iris.h -F: configs/colibri_t20_iris_defconfig diff --git a/board/toradex/colibri_t20_iris/Makefile b/board/toradex/colibri_t20_iris/Makefile deleted file mode 100644 index f286aec041b..00000000000 --- a/board/toradex/colibri_t20_iris/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2012 Lucas Stach -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(srctree)/board/nvidia/common/common.mk - -obj-y += colibri_t20_iris.o diff --git a/board/toradex/colibri_t20_iris/colibri_t20_iris.c b/board/toradex/colibri_t20_iris/colibri_t20_iris.c deleted file mode 100644 index 46560948a64..00000000000 --- a/board/toradex/colibri_t20_iris/colibri_t20_iris.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2012 Lucas Stach - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_TEGRA_MMC -/* - * Routine: pin_mux_mmc - * Description: setup the pin muxes/tristate values for the SDMMC(s) - */ -void pin_mux_mmc(void) -{ - funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); - pinmux_tristate_disable(PMUX_PINGRP_GMB); -} -#endif - -#ifdef CONFIG_TEGRA_NAND -void pin_mux_nand(void) -{ - funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT); -} -#endif - -#ifdef CONFIG_USB_EHCI_TEGRA -void pin_mux_usb(void) -{ - /* module internal USB bus to connect ethernet chipset */ - funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); - - /* ULPI reference clock output */ - pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); - pinmux_tristate_disable(PMUX_PINGRP_CDEV2); - - /* PHY reset GPIO */ - pinmux_tristate_disable(PMUX_PINGRP_UAC); - - /* VBus GPIO */ - pinmux_tristate_disable(PMUX_PINGRP_DTE); - - /* USB 1 aka Tegra USB port 3 VBus */ - pinmux_tristate_disable(PMUX_PINGRP_SPIG); -} -#endif diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig new file mode 100644 index 00000000000..89875672b55 --- /dev/null +++ b/configs/colibri_t20_defconfig @@ -0,0 +1,5 @@ +CONFIG_ARM=y +CONFIG_TEGRA=y +CONFIG_TEGRA20=y +CONFIG_TARGET_COLIBRI_T20=y +CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri" diff --git a/configs/colibri_t20_iris_defconfig b/configs/colibri_t20_iris_defconfig deleted file mode 100644 index a14d55a08b6..00000000000 --- a/configs/colibri_t20_iris_defconfig +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_ARM=y -CONFIG_TEGRA=y -CONFIG_TEGRA20=y -CONFIG_TARGET_COLIBRI_T20_IRIS=y -CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri_t20_iris" diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h new file mode 100644 index 00000000000..e80e9ed037e --- /dev/null +++ b/include/configs/colibri_t20.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2012 Lucas Stach + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra20-common.h" + +/* High-level configuration options */ +#define V_PROMPT "Colibri T20 # " +#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T20" + +/* Board-specific serial config */ +#define CONFIG_TEGRA_ENABLE_UARTA +#define CONFIG_TEGRA_UARTA_SDIO1 +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +/* SD/MMC support */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* USB host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_ULPI +#define CONFIG_USB_ULPI_VIEWPORT +#define CONFIG_USB_STORAGE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING + +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_TEGRA_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (SZ_2M) +#undef CONFIG_ENV_SIZE /* undef size from tegra20-common.h */ +#define CONFIG_ENV_SIZE (SZ_64K) + +/* Debug commands */ +#define CONFIG_CMD_BDI +#define CONFIG_CMD_CACHE + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/colibri_t20_iris.h b/include/configs/colibri_t20_iris.h deleted file mode 100644 index 4888c945fe2..00000000000 --- a/include/configs/colibri_t20_iris.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2012 Lucas Stach - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" - -/* High-level configuration options */ -#define V_PROMPT "Tegra20 (Colibri) # " -#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T20 on Iris" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_TEGRA_UARTA_SDIO1 -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -/* SD/MMC support */ -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_TEGRA_MMC -#define CONFIG_CMD_MMC - -/* USB host support */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_TEGRA -#define CONFIG_USB_ULPI -#define CONFIG_USB_ULPI_VIEWPORT -#define CONFIG_USB_STORAGE -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 -#define CONFIG_CMD_USB - -/* USB networking support */ -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_CMD_NET -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING - -/* NAND support */ -#define CONFIG_CMD_NAND -#define CONFIG_TEGRA_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */ -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET (SZ_2M) -#undef CONFIG_ENV_SIZE /* undef size from tegra20-common.h */ -#define CONFIG_ENV_SIZE (SZ_64K) - -/* Debug commands */ -#define CONFIG_CMD_BDI -#define CONFIG_CMD_CACHE - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/tools/buildman/README b/tools/buildman/README index cf7bf5c17e1..e870d54c1ff 100644 --- a/tools/buildman/README +++ b/tools/buildman/README @@ -613,7 +613,7 @@ $ ./tools/buildman/buildman -b us-mem4 -sSdB run_list_real 1996 2000 +4 do_nandboot 760 756 -4 do_mem_crc 168 68 -100 - colibri_t20_iris: all -9 rodata -29 text +20 + colibri_t20 : all -9 rodata -29 text +20 u-boot: add: 1/0, grow: 2/-3 bytes: 140/-112 (28) function old new delta hash_command 80 160 +80 -- cgit v1.3.1 From 1ed056e84db0ea5c4365a5e0a79dd94ff1bc4b0b Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 26 Mar 2015 02:16:33 +0100 Subject: ARM: tegra: fix colibri_t20 machine type A while ago I got Russell to change the machine type of our Colibri T20 from COLIBRI_TEGRA2 to COLIBRI_T20 which at least in parts is also reflected in his machine registry: http://www.arm.linux.org.uk/developer/machines/list.php?id=3323 For us it is really very beneficial to actually still be able to boot downstream L4T kernel with its working hardware accelerated graphics/multimedia stack albeit it being proprietary/closed-source. Signed-off-by: Marcel Ziswiler Acked-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/mach-types.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index d4a447b2b8a..c424a224427 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -936,7 +936,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_CWME9210 3320 #define MACH_TYPE_CWME9210JS 3321 #define MACH_TYPE_PGS_SITARA 3322 -#define MACH_TYPE_COLIBRI_TEGRA2 3323 +#define MACH_TYPE_COLIBRI_T20 3323 #define MACH_TYPE_W21 3324 #define MACH_TYPE_POLYSAT1 3325 #define MACH_TYPE_DATAWAY 3326 @@ -12197,16 +12197,16 @@ extern unsigned int __machine_arch_type; # define machine_is_pgs_v1() (0) #endif -#ifdef CONFIG_MACH_COLIBRI_TEGRA2 +#ifdef CONFIG_MACH_COLIBRI_T20 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_COLIBRI_TEGRA2 +# define machine_arch_type MACH_TYPE_COLIBRI_T20 # endif -# define machine_is_colibri_tegra2() (machine_arch_type == MACH_TYPE_COLIBRI_TEGRA2) +# define machine_is_colibri_t20() (machine_arch_type == MACH_TYPE_COLIBRI_T20) #else -# define machine_is_colibri_tegra2() (0) +# define machine_is_colibri_t20() (0) #endif #ifdef CONFIG_MACH_W21 -- cgit v1.3.1 From 00a5270bd843f436d2c60d2a8512a302061596f5 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 26 Mar 2015 02:17:07 +0100 Subject: ARM: tegra: fix colibri_t20 asix reset Fix ASIX USB to Ethernet chip reset. Signed-off-by: Marcel Ziswiler Acked-by: Stephen Warren Signed-off-by: Tom Warren --- board/toradex/colibri_t20/colibri_t20.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 46560948a64..5d8bdecb8e1 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -46,7 +46,14 @@ void pin_mux_usb(void) /* VBus GPIO */ pinmux_tristate_disable(PMUX_PINGRP_DTE); - /* USB 1 aka Tegra USB port 3 VBus */ + /* Reset ASIX using LAN_RESET */ + gpio_request(GPIO_PV4, "LAN_RESET"); + gpio_direction_output(GPIO_PV4, 0); + pinmux_tristate_disable(PMUX_PINGRP_GPV); + udelay(5); + gpio_set_value(GPIO_PV4, 1); + + /* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */ pinmux_tristate_disable(PMUX_PINGRP_SPIG); } #endif -- cgit v1.3.1 From e979a808612f0209ce43eddbb8bf46fe2bdf9fb8 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 26 Mar 2015 02:17:27 +0100 Subject: ARM: tegra: update colibri_t20 configuration Bring the Colibri T20 configuration in-line with Apalis/Colibri T30. Signed-off-by: Marcel Ziswiler Signed-off-by: Tom Warren --- include/configs/colibri_t20.h | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index e80e9ed037e..c17f245a17f 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -14,9 +14,12 @@ #define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T20" /* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_TEGRA_UARTA_SDIO1 -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T20 /* SD/MMC support */ #define CONFIG_MMC @@ -29,17 +32,17 @@ #define CONFIG_USB_EHCI_TEGRA #define CONFIG_USB_ULPI #define CONFIG_USB_ULPI_VIEWPORT -#define CONFIG_USB_STORAGE #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_USB_STORAGE #define CONFIG_CMD_USB /* USB networking support */ #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX + +/* General networking support */ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING /* NAND support */ #define CONFIG_CMD_NAND @@ -56,6 +59,26 @@ #define CONFIG_CMD_BDI #define CONFIG_CMD_CACHE +/* Miscellaneous commands */ +#define CONFIG_CMD_SETEXPR +#define CONFIG_FAT_WRITE + +/* Increase console I/O buffer size */ +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 1024 + +/* Increase arguments buffer size */ +#undef CONFIG_SYS_BARGSIZE +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Increase print buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Increase maximum number of arguments */ +#undef CONFIG_SYS_MAXARGS +#define CONFIG_SYS_MAXARGS 32 + +#include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" #endif /* __CONFIG_H */ -- cgit v1.3.1 From 9b219d4dfb1f358fa0dfa03f6e529c82f9299dd2 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 27 Mar 2015 01:31:44 +0100 Subject: tegra: pinmux: fix FUNCMUX_NDFLASH_KBC_8_BIT Even the 8-bit case needs KBCB configured, as pin D7 is located in this pingroup. Please note that pingroup ATC seems to come out of reset with its config set to NAND so one needs to explicitly configure some other function to this group in order to avoid clashing settings which is outside the scope of this patch. Signed-off-by: Lucas Stach Signed-off-by: Marcel Ziswiler Tested-by: Marcel Ziswiler Signed-off-by: Tom Warren --- arch/arm/mach-tegra/tegra20/funcmux.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-tegra/tegra20/funcmux.c b/arch/arm/mach-tegra/tegra20/funcmux.c index 0df4a0738de..44a85c5f1dc 100644 --- a/arch/arm/mach-tegra/tegra20/funcmux.c +++ b/arch/arm/mach-tegra/tegra20/funcmux.c @@ -252,12 +252,14 @@ int funcmux_select(enum periph_id id, int config) break; case FUNCMUX_NDFLASH_KBC_8_BIT: pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND); + pinmux_set_func(PMUX_PINGRP_KBCB, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND); pinmux_tristate_disable(PMUX_PINGRP_KBCA); + pinmux_tristate_disable(PMUX_PINGRP_KBCB); pinmux_tristate_disable(PMUX_PINGRP_KBCC); pinmux_tristate_disable(PMUX_PINGRP_KBCD); pinmux_tristate_disable(PMUX_PINGRP_KBCE); -- cgit v1.3.1 From 76a30fedd44428c7108084266389c9b4ba5678c8 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 27 Mar 2015 01:31:45 +0100 Subject: ARM: tegra: colibri_t20: fix nand pinmux Pingroup ATC seems to come out of reset with config set to NAND, so we need to explicitly configure some other function to this group in order to avoid clashing settings. Signed-off-by: Marcel Ziswiler Signed-off-by: Tom Warren --- board/toradex/colibri_t20/colibri_t20.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 5d8bdecb8e1..8ae9ccf5384 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -27,6 +27,12 @@ void pin_mux_mmc(void) void pin_mux_nand(void) { funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT); + + /* + * configure pingroup ATC to something unrelated to + * avoid ATC overriding KBC + */ + pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI); } #endif -- cgit v1.3.1