From 6a77840b2f01e98bbad157fd1984a2dce2a3eecd Mon Sep 17 00:00:00 2001 From: Julien Stephan Date: Tue, 28 Jul 2026 14:28:23 +0200 Subject: clk: mediatek: mt8188: fix top0 gate polarity Gates in top0_cg_regs are active-high. The GATE_TOP0/GATE_TOP0E macros set CLK_GATE_NO_SETCLR flags, which treat them as active-low. Enabling the clock is currently disabling them. Switch both macros to CLK_GATE_NO_SETCLR_INV to use the correct active-high semantics. Signed-off-by: Julien Stephan Fixes: 11f3cc46322a ("clk: mediatek: add MT8188 clock driver") Link: https://patch.msgid.link/20260728-mt8188-clk-fix-top0-gate-polarity-v1-1-56bc92ba6055@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mt8188.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c index 56a98e9ac4f..0829ebf4f9a 100644 --- a/drivers/clk/mediatek/clk-mt8188.c +++ b/drivers/clk/mediatek/clk-mt8188.c @@ -1363,7 +1363,7 @@ static const struct mtk_gate_regs top1_cg_regs = { .parent = _parent, \ .regs = &top0_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ } #define GATE_TOP0E(_id, _parent, _shift) { \ @@ -1371,7 +1371,7 @@ static const struct mtk_gate_regs top1_cg_regs = { .parent = _parent, \ .regs = &top0_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_EXT, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_EXT, \ } #define GATE_TOP1(_id, _parent, _shift) { \ -- cgit v1.3.1