From f079d8059da9eae96c1a4738e2f42c2679d9e09f Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Tue, 9 Dec 2025 21:03:40 +0000 Subject: rockchip: rk3568-nanopi-r5: Drop duplicated/extra sdhci The pinctrl settings are now upstream, with the upstream voltage supplies, and the HS200 mode is confirmed to work fine but the HS400 mode had reported issues so let's just consume what the upstream DT has now as it's all known good. Reported-by: Dusty Mabe Tested-by: Dusty Mabe Signed-off-by: Peter Robinson Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/20251209210347.492763-1-pbrobinson@gmail.com Signed-off-by: Quentin Schulz --- arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi index 64c43374c04..7e24be1a5e7 100644 --- a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi +++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi @@ -12,14 +12,6 @@ /delete-property/ vpcie3v3-supply; }; -&sdhci { - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; -}; - &vcc5v0_usb_host { /delete-property/ regulator-always-on; /delete-property/ regulator-boot-on; -- cgit v1.3.1 From 1998fe69f7e124f0e6b1c6d0c9012a618e91c730 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Sun, 10 May 2026 16:17:13 -0500 Subject: board: rockchip: add Anbernic RG-DS Add support for the Anbernic RG-DS dual-screen handheld gaming device. Link: https://anbernic.com/products/rgds Signed-off-by: Chris Morgan Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang Link: https://patch.msgid.link/20260510211713.68312-1-macroalpha82@gmail.com [conflict resolution in doc/board/rockchip/rockchip.rst due to commit b5deaa71fbe5 ("board: rockchip: Add support for 9Tripod X3568 v4")] Signed-off-by: Quentin Schulz --- arch/arm/dts/rk3568-anbernic-rg-ds-u-boot.dtsi | 41 +++++++++++++++ arch/arm/mach-rockchip/rk3568/Kconfig | 7 +++ board/anbernic/rg-ds_rk3568/Kconfig | 12 +++++ board/anbernic/rg-ds_rk3568/MAINTAINERS | 7 +++ configs/anbernic-rg-ds-rk3568_defconfig | 73 ++++++++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + include/configs/anbernic-rg-ds-rk3568.h | 12 +++++ 7 files changed, 153 insertions(+) create mode 100644 arch/arm/dts/rk3568-anbernic-rg-ds-u-boot.dtsi create mode 100644 board/anbernic/rg-ds_rk3568/Kconfig create mode 100644 board/anbernic/rg-ds_rk3568/MAINTAINERS create mode 100644 configs/anbernic-rg-ds-rk3568_defconfig create mode 100644 include/configs/anbernic-rg-ds-rk3568.h diff --git a/arch/arm/dts/rk3568-anbernic-rg-ds-u-boot.dtsi b/arch/arm/dts/rk3568-anbernic-rg-ds-u-boot.dtsi new file mode 100644 index 00000000000..7944610827f --- /dev/null +++ b/arch/arm/dts/rk3568-anbernic-rg-ds-u-boot.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3568-u-boot.dtsi" + +&gpio0 { + bootph-pre-ram; +}; + +&i2c0 { + bootph-pre-ram; +}; + +&i2c0_xfer { + bootph-pre-ram; +}; + +&i2s1m0_mclk { + bootph-pre-ram; +}; + +&pmic_int_l { + bootph-pre-ram; +}; + +&rk817 { + regulators { + bootph-pre-ram; + }; +}; + +&sdmmc_pwren_l { + bootph-pre-ram; +}; + +&vcc3v3_sd { + bootph-pre-ram; +}; + +&vccio_sd { + bootph-pre-ram; +}; diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index 2730220a18e..ec22898137e 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -8,6 +8,12 @@ config TARGET_EVB_RK3568 help RK3568 EVB is a evaluation board for Rockchp RK3568. +config TARGET_ANBERNIC_RG_DS_RK3568 + bool "Anbernic RG DS" + help + Anbernic RG DS gaming device with Rockchip RK3568 and dual + displays. + config TARGET_ANBERNIC_RGXX3_RK3566 bool "Anbernic RGXX3" help @@ -71,6 +77,7 @@ config SYS_SOC default "rk3568" source "board/rockchip/evb_rk3568/Kconfig" +source "board/anbernic/rg-ds_rk3568/Kconfig" source "board/anbernic/rgxx3_rk3566/Kconfig" source "board/hardkernel/odroid_m1/Kconfig" source "board/hardkernel/odroid_m1s/Kconfig" diff --git a/board/anbernic/rg-ds_rk3568/Kconfig b/board/anbernic/rg-ds_rk3568/Kconfig new file mode 100644 index 00000000000..8676940651a --- /dev/null +++ b/board/anbernic/rg-ds_rk3568/Kconfig @@ -0,0 +1,12 @@ +if TARGET_RG_DS_RK3568 + +config SYS_BOARD + default "rg-ds_rk3568" + +config SYS_VENDOR + default "anbernic" + +config SYS_CONFIG_NAME + default "anbernic-rg-ds-rk3568" + +endif diff --git a/board/anbernic/rg-ds_rk3568/MAINTAINERS b/board/anbernic/rg-ds_rk3568/MAINTAINERS new file mode 100644 index 00000000000..7b9b546f7bc --- /dev/null +++ b/board/anbernic/rg-ds_rk3568/MAINTAINERS @@ -0,0 +1,7 @@ +ANBERNIC-RG-DS-RK3568 +M: Chris Morgan +S: Maintained +F: arch/arm/dts/rk3568-anbernic-rg-ds-u-boot.dtsi +F: board/anbernic/rg-ds_rk3568 +F: configs/anbernic-rg-ds-rk3568_defconfig +F: include/configs/anbernic-rg-ds-rk3568.h diff --git a/configs/anbernic-rg-ds-rk3568_defconfig b/configs/anbernic-rg-ds-rk3568_defconfig new file mode 100644 index 00000000000..399a216a7c9 --- /dev/null +++ b/configs/anbernic-rg-ds-rk3568_defconfig @@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-anbernic-rg-ds" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_ANBERNIC_RG_DS_RK3568=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-anbernic-rg-ds.dtb" +# CONFIG_CONSOLE_MUX is not set +CONFIG_BOARD_TYPES=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_RNG_SEED=y +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_POWER=y +CONFIG_SPL_ATF=y +CONFIG_CMD_PWM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_CLS is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_LIST="rockchip/rk3568-anbernic-rg-ds" +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +# CONFIG_NET is not set +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_ADC=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_FAN53555=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +# CONFIG_RAM_ROCKCHIP_DEBUG is not set +CONFIG_BAUDRATE=1500000 +# CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_REGEX=y +# CONFIG_RSA is not set +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index f77f1e78f38..0c0cde7ec38 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -127,6 +127,7 @@ List of mainline supported Rockchip boards: * rk3568 - 9Tripod X3568 v4 (9tripod-x3568-v4-rk3568) + - Anbernic RG-DS (anbernic-rg-ds-rk3568) - Rockchip Evb-RK3568 (evb-rk3568) - Banana Pi BPI-R2 Pro (bpi-r2-pro-rk3568) - EmbedFire LubanCat 2 (lubancat-2-rk3568) diff --git a/include/configs/anbernic-rg-ds-rk3568.h b/include/configs/anbernic-rg-ds-rk3568.h new file mode 100644 index 00000000000..3c5bed952ef --- /dev/null +++ b/include/configs/anbernic-rg-ds-rk3568.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ANBERNIC_RG_DS_RK3568_H +#define __ANBERNIC_RG_DS_RK3568_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#endif -- cgit v1.3.1 From 3bc0f812735350831c6b63fa163c02ecdf61694c Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sun, 19 Jul 2026 02:52:11 +0100 Subject: rockchip: only build GPT capsule update helpers with PARTITION_TYPE_GUID The GPT-based capsule update helpers match updatable images by partition type GUID and fail to build if PARTITION_TYPE_GUID is not enabled: arch/arm/mach-rockchip/board.c:50:29: error: 'struct disk_partition' has no member named 'type_guid' Boards which keep their firmware on SPI-NOR use a static dfu_string instead of scanning GPT partitions and have no use for this code, so guard it accordingly. Signed-off-by: Daniel Golle Reviewed-by: Quentin Schulz Fixes: bea9267d7e6d ("rockchip: capsule: Add functions for supporting capsule updates") Link: https://patch.msgid.link/af0ac32e2bf603c39f490f15fe62319fd73c5282.1784423864.git.daniel@makrotopia.org Signed-off-by: Quentin Schulz --- arch/arm/mach-rockchip/board.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 2e6bb38b923..98c890d3bdc 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -35,7 +35,8 @@ #include #include -#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION) +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION) && \ + IS_ENABLED(CONFIG_PARTITION_TYPE_GUID) #define DFU_ALT_BUF_LEN SZ_1K @@ -193,7 +194,8 @@ int board_late_init(void) { setup_boot_mode(); -#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION) +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION) && \ + IS_ENABLED(CONFIG_PARTITION_TYPE_GUID) gpt_capsule_update_setup(); #endif -- cgit v1.3.1 From 30675622843da663933fa4e1a84296d9fd63980a Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 20 Jul 2026 11:42:01 +0200 Subject: MAINTAINERS: update ARM ROCKCHIP entry to list Simon as reviewer From his own recollection[1], Simon hasn't done PRs since Kever took over, 7 years ago. Moreover, he doesn't have rights to push to the Rockchip custodian tree on the old source.denx.de or the new git.u-boot-project.org. Therefore, let's reflect the reality and make Simon a reviewer as requested on the mailing list[1]. We thank him for the many years of being a custodian and reviewer for anything-Rockchip. [1] https://lore.kernel.org/u-boot/CAFLszTjXkx0Jw0yjNXXwdXrQYre7Lcs59m_Bc27QW0n0c+WaJw@mail.gmail.com/ Signed-off-by: Quentin Schulz Link: https://patch.msgid.link/20260720-sjg-no-rk-cust-v1-1-38eebe54c349@cherry.de Signed-off-by: Quentin Schulz --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index e5b2a2e373c..d9ff6b4f828 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -554,9 +554,9 @@ F: drivers/sysinfo/rcar3.c F: drivers/usb/host/xhci-rcar* ARM ROCKCHIP -M: Simon Glass M: Quentin Schulz M: Kever Yang +R: Simon Glass S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-rockchip.git # Exclude from N: px5 matches -- cgit v1.3.1 From e504d9cffbafbd4dd267ab9a73bf1ee58d89e8e1 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 9 Jun 2026 22:22:58 +0200 Subject: rockchip: pinctrl: replace RK_FUNC_n defines The use of RK_FUNC_n defines is deprecated in the upstream rockchip.h file. Replace all them by the function number. Signed-off-by: Johan Jonker Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/51cb65e5-1702-467f-b961-c9cdd029056f@gmail.com Signed-off-by: Quentin Schulz --- arch/arm/dts/rk3368-sheep.dts | 2 +- doc/develop/driver-model/serial-howto.rst | 4 +- drivers/pinctrl/rockchip/pinctrl-rk3568.c | 186 +++++++++++++++--------------- include/dt-bindings/pinctrl/rockchip.h | 6 - 4 files changed, 96 insertions(+), 102 deletions(-) diff --git a/arch/arm/dts/rk3368-sheep.dts b/arch/arm/dts/rk3368-sheep.dts index 120dec1a3de..723f78b46d5 100644 --- a/arch/arm/dts/rk3368-sheep.dts +++ b/arch/arm/dts/rk3368-sheep.dts @@ -250,7 +250,7 @@ pmic { pmic_sleep: pmic-sleep { - rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 0 2 &pcfg_pull_none>; }; pmic_int: pmic-int { diff --git a/doc/develop/driver-model/serial-howto.rst b/doc/develop/driver-model/serial-howto.rst index 17b53e3cabf..8ca9a016f9a 100644 --- a/doc/develop/driver-model/serial-howto.rst +++ b/doc/develop/driver-model/serial-howto.rst @@ -97,8 +97,8 @@ Here are some things you might need to consider: uart2: uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_up>, - <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, + <1 RK_PC3 2 &pcfg_pull_none>; }; ... }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c index c8a91b8bb6e..f8899443d52 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3568.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c @@ -12,99 +12,99 @@ #include "pinctrl-rockchip.h" static struct rockchip_mux_route_data rk3568_mux_route_data[] = { - MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(1, 0, 0)), /* PWM0 IO mux selection M0 */ - MR_PMUGRF(RK_GPIO0, RK_PC7, RK_FUNC_2, 0x0110, RK_GENMASK_VAL(1, 0, 1)), /* PWM0 IO mux selection M1 */ - MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(3, 2, 0)), /* PWM1 IO mux selection M0 */ - MR_PMUGRF(RK_GPIO0, RK_PB5, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(3, 2, 1)), /* PWM1 IO mux selection M1 */ - MR_PMUGRF(RK_GPIO0, RK_PC1, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(5, 4, 0)), /* PWM2 IO mux selection M0 */ - MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(5, 4, 1)), /* PWM2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)), /* CAN1 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)), /* CAN2 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)), /* CAN2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)), /* EDPDP_HPDIN IO mux selection M0 */ - MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)), /* EDPDP_HPDIN IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 0)), /* GMAC1 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PA7, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 1)), /* GMAC1 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO4, RK_PD1, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 0)), /* HDMITX IO mux selection M0 */ - MR_TOPGRF(RK_GPIO0, RK_PC7, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 1)), /* HDMITX IO mux selection M1 */ - MR_TOPGRF(RK_GPIO0, RK_PB6, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 0)), /* I2C2 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PB4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 1)), /* I2C2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PA0, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(0, 0, 0)), /* I2C3 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(0, 0, 1)), /* I2C3 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO4, RK_PB2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(2, 2, 0)), /* I2C4 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_5, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO1, RK_PD6, RK_FUNC_4, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PB5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC0, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC6, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PD3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(0, 0, 1)), /* SPI0 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PB5, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 0)), /* SPI1 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PC3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 1)), /* SPI1 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(4, 4, 0)), /* SPI2 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(4, 4, 1)), /* SPI2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(12, 12, 1)), /* UART3 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(14, 14, 0)), /* UART4 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(14, 14, 1)), /* UART4 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PA2, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(0, 0, 0)), /* UART5 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PC2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(0, 0, 1)), /* UART5 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PA4, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 0)), /* UART6 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO4, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */ - MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 1)), /* UART9 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO4, RK_PA4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 2)), /* UART9 IO mux selection M2 */ - MR_TOPGRF(RK_GPIO1, RK_PA2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(11, 10, 0)), /* I2S1 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(11, 10, 1)), /* I2S1 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(11, 10, 2)), /* I2S1 IO mux selection M2 */ - MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(12, 12, 0)), /* I2S2 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */ - MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */ - MR_TOPGRF(RK_GPIO4, RK_PA0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 2)), /* PDM IO mux selection M2 */ - MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */ - MR_TOPGRF(RK_GPIO0, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PD2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux selection M2 */ - MR_TOPGRF(RK_GPIO0, RK_PA6, RK_FUNC_2, 0x0314, RK_GENMASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux selection M2 */ + MR_PMUGRF(RK_GPIO0, RK_PB7, 1, 0x0110, RK_GENMASK_VAL(1, 0, 0)), /* PWM0 IO mux selection M0 */ + MR_PMUGRF(RK_GPIO0, RK_PC7, 2, 0x0110, RK_GENMASK_VAL(1, 0, 1)), /* PWM0 IO mux selection M1 */ + MR_PMUGRF(RK_GPIO0, RK_PC0, 1, 0x0110, RK_GENMASK_VAL(3, 2, 0)), /* PWM1 IO mux selection M0 */ + MR_PMUGRF(RK_GPIO0, RK_PB5, 4, 0x0110, RK_GENMASK_VAL(3, 2, 1)), /* PWM1 IO mux selection M1 */ + MR_PMUGRF(RK_GPIO0, RK_PC1, 1, 0x0110, RK_GENMASK_VAL(5, 4, 0)), /* PWM2 IO mux selection M0 */ + MR_PMUGRF(RK_GPIO0, RK_PB6, 4, 0x0110, RK_GENMASK_VAL(5, 4, 1)), /* PWM2 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO0, RK_PB3, 2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO2, RK_PA1, 4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO1, RK_PA1, 3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC3, 3, 0x0300, RK_GENMASK_VAL(2, 2, 1)), /* CAN1 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO4, RK_PB5, 3, 0x0300, RK_GENMASK_VAL(4, 4, 0)), /* CAN2 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO2, RK_PB2, 4, 0x0300, RK_GENMASK_VAL(4, 4, 1)), /* CAN2 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO4, RK_PC4, 1, 0x0300, RK_GENMASK_VAL(6, 6, 0)), /* EDPDP_HPDIN IO mux selection M0 */ + MR_TOPGRF(RK_GPIO0, RK_PC2, 2, 0x0300, RK_GENMASK_VAL(6, 6, 1)), /* EDPDP_HPDIN IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PB1, 3, 0x0300, RK_GENMASK_VAL(8, 8, 0)), /* GMAC1 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PA7, 3, 0x0300, RK_GENMASK_VAL(8, 8, 1)), /* GMAC1 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO4, RK_PD1, 1, 0x0300, RK_GENMASK_VAL(10, 10, 0)), /* HDMITX IO mux selection M0 */ + MR_TOPGRF(RK_GPIO0, RK_PC7, 1, 0x0300, RK_GENMASK_VAL(10, 10, 1)), /* HDMITX IO mux selection M1 */ + MR_TOPGRF(RK_GPIO0, RK_PB6, 1, 0x0300, RK_GENMASK_VAL(14, 14, 0)), /* I2C2 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PB4, 1, 0x0300, RK_GENMASK_VAL(14, 14, 1)), /* I2C2 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO1, RK_PA0, 1, 0x0304, RK_GENMASK_VAL(0, 0, 0)), /* I2C3 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PB6, 4, 0x0304, RK_GENMASK_VAL(0, 0, 1)), /* I2C3 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO4, RK_PB2, 1, 0x0304, RK_GENMASK_VAL(2, 2, 0)), /* I2C4 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO2, RK_PB1, 2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PB4, 4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PD0, 2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PB1, 5, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO1, RK_PD5, 4, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PB2, 5, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO1, RK_PD6, 4, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PB5, 5, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO2, RK_PA1, 2, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PB6, 5, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC0, 3, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PB7, 2, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC5, 1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PC0, 2, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC6, 1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PC4, 1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC2, 1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PC5, 1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC3, 1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PD2, 3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PA5, 5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO0, RK_PB5, 2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD3, 3, 0x030c, RK_GENMASK_VAL(0, 0, 1)), /* SPI0 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO2, RK_PB5, 3, 0x030c, RK_GENMASK_VAL(2, 2, 0)), /* SPI1 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PC3, 3, 0x030c, RK_GENMASK_VAL(2, 2, 1)), /* SPI1 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO2, RK_PC1, 4, 0x030c, RK_GENMASK_VAL(4, 4, 0)), /* SPI2 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PA0, 3, 0x030c, RK_GENMASK_VAL(4, 4, 1)), /* SPI2 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO4, RK_PB3, 4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC2, 2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO2, RK_PB4, 2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PD6, 4, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO0, RK_PD1, 1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO1, RK_PD5, 2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO1, RK_PA1, 2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PB7, 4, 0x030c, RK_GENMASK_VAL(12, 12, 1)), /* UART3 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO1, RK_PA6, 2, 0x030c, RK_GENMASK_VAL(14, 14, 0)), /* UART4 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PB2, 4, 0x030c, RK_GENMASK_VAL(14, 14, 1)), /* UART4 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO2, RK_PA2, 3, 0x0310, RK_GENMASK_VAL(0, 0, 0)), /* UART5 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PC2, 4, 0x0310, RK_GENMASK_VAL(0, 0, 1)), /* UART5 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO2, RK_PA4, 3, 0x0310, RK_GENMASK_VAL(2, 2, 0)), /* UART6 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO1, RK_PD5, 3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO2, RK_PA6, 3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PC4, 4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO4, RK_PA2, 4, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */ + MR_TOPGRF(RK_GPIO2, RK_PC5, 3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD7, 4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO2, RK_PB0, 3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC5, 4, 0x0310, RK_GENMASK_VAL(9, 8, 1)), /* UART9 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO4, RK_PA4, 4, 0x0310, RK_GENMASK_VAL(9, 8, 2)), /* UART9 IO mux selection M2 */ + MR_TOPGRF(RK_GPIO1, RK_PA2, 1, 0x0310, RK_GENMASK_VAL(11, 10, 0)), /* I2S1 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PC6, 4, 0x0310, RK_GENMASK_VAL(11, 10, 1)), /* I2S1 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO2, RK_PD0, 5, 0x0310, RK_GENMASK_VAL(11, 10, 2)), /* I2S1 IO mux selection M2 */ + MR_TOPGRF(RK_GPIO2, RK_PC1, 1, 0x0310, RK_GENMASK_VAL(12, 12, 0)), /* I2S2 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PB6, 5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PA2, 4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO4, RK_PC2, 5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO1, RK_PA4, 3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */ + MR_TOPGRF(RK_GPIO1, RK_PA6, 3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */ + MR_TOPGRF(RK_GPIO3, RK_PD6, 5, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */ + MR_TOPGRF(RK_GPIO4, RK_PA0, 4, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */ + MR_TOPGRF(RK_GPIO3, RK_PC4, 5, 0x0314, RK_GENMASK_VAL(1, 0, 2)), /* PDM IO mux selection M2 */ + MR_TOPGRF(RK_GPIO0, RK_PA5, 3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD0, 4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO1, RK_PB0, 4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */ + MR_TOPGRF(RK_GPIO0, RK_PA4, 3, 0x0314, RK_GENMASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD2, 4, 0x0314, RK_GENMASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO1, RK_PA5, 4, 0x0314, RK_GENMASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux selection M2 */ + MR_TOPGRF(RK_GPIO0, RK_PA6, 2, 0x0314, RK_GENMASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux selection M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD4, 4, 0x0314, RK_GENMASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux selection M1 */ + MR_TOPGRF(RK_GPIO4, RK_PC2, 4, 0x0314, RK_GENMASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux selection M2 */ }; static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h index 1c28d6cb1fa..1636ec99eb6 100644 --- a/include/dt-bindings/pinctrl/rockchip.h +++ b/include/dt-bindings/pinctrl/rockchip.h @@ -50,11 +50,5 @@ #define RK_PD7 31 #define RK_FUNC_GPIO 0 -#define RK_FUNC_1 1 -#define RK_FUNC_2 2 -#define RK_FUNC_3 3 -#define RK_FUNC_4 4 -#define RK_FUNC_5 5 -#define RK_FUNC_6 6 #endif -- cgit v1.3.1 From 2f783e53754b383e037ffc32e074e9b121386c9e Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 9 Jun 2026 22:23:14 +0200 Subject: rockchip: pinctrl: replace RK_GPIOn defines The use of RK_GPIOn defines is deprecated in the upstream rockchip.h file. Replace all them by the gpio number. Signed-off-by: Johan Jonker Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/6bcf3192-82dc-464e-92f6-b9758f6c8422@gmail.com Signed-off-by: Quentin Schulz --- drivers/pinctrl/rockchip/pinctrl-rk3568.c | 186 +++++++++++++++--------------- drivers/pinctrl/rockchip/pinctrl-rv1126.c | 134 ++++++++++----------- include/dt-bindings/pinctrl/rockchip.h | 7 -- 3 files changed, 160 insertions(+), 167 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3568.c b/drivers/pinctrl/rockchip/pinctrl-rk3568.c index f8899443d52..514481530fa 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3568.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c @@ -12,99 +12,99 @@ #include "pinctrl-rockchip.h" static struct rockchip_mux_route_data rk3568_mux_route_data[] = { - MR_PMUGRF(RK_GPIO0, RK_PB7, 1, 0x0110, RK_GENMASK_VAL(1, 0, 0)), /* PWM0 IO mux selection M0 */ - MR_PMUGRF(RK_GPIO0, RK_PC7, 2, 0x0110, RK_GENMASK_VAL(1, 0, 1)), /* PWM0 IO mux selection M1 */ - MR_PMUGRF(RK_GPIO0, RK_PC0, 1, 0x0110, RK_GENMASK_VAL(3, 2, 0)), /* PWM1 IO mux selection M0 */ - MR_PMUGRF(RK_GPIO0, RK_PB5, 4, 0x0110, RK_GENMASK_VAL(3, 2, 1)), /* PWM1 IO mux selection M1 */ - MR_PMUGRF(RK_GPIO0, RK_PC1, 1, 0x0110, RK_GENMASK_VAL(5, 4, 0)), /* PWM2 IO mux selection M0 */ - MR_PMUGRF(RK_GPIO0, RK_PB6, 4, 0x0110, RK_GENMASK_VAL(5, 4, 1)), /* PWM2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO0, RK_PB3, 2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PA1, 4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PA1, 3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC3, 3, 0x0300, RK_GENMASK_VAL(2, 2, 1)), /* CAN1 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO4, RK_PB5, 3, 0x0300, RK_GENMASK_VAL(4, 4, 0)), /* CAN2 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PB2, 4, 0x0300, RK_GENMASK_VAL(4, 4, 1)), /* CAN2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO4, RK_PC4, 1, 0x0300, RK_GENMASK_VAL(6, 6, 0)), /* EDPDP_HPDIN IO mux selection M0 */ - MR_TOPGRF(RK_GPIO0, RK_PC2, 2, 0x0300, RK_GENMASK_VAL(6, 6, 1)), /* EDPDP_HPDIN IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PB1, 3, 0x0300, RK_GENMASK_VAL(8, 8, 0)), /* GMAC1 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PA7, 3, 0x0300, RK_GENMASK_VAL(8, 8, 1)), /* GMAC1 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO4, RK_PD1, 1, 0x0300, RK_GENMASK_VAL(10, 10, 0)), /* HDMITX IO mux selection M0 */ - MR_TOPGRF(RK_GPIO0, RK_PC7, 1, 0x0300, RK_GENMASK_VAL(10, 10, 1)), /* HDMITX IO mux selection M1 */ - MR_TOPGRF(RK_GPIO0, RK_PB6, 1, 0x0300, RK_GENMASK_VAL(14, 14, 0)), /* I2C2 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PB4, 1, 0x0300, RK_GENMASK_VAL(14, 14, 1)), /* I2C2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PA0, 1, 0x0304, RK_GENMASK_VAL(0, 0, 0)), /* I2C3 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PB6, 4, 0x0304, RK_GENMASK_VAL(0, 0, 1)), /* I2C3 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO4, RK_PB2, 1, 0x0304, RK_GENMASK_VAL(2, 2, 0)), /* I2C4 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PB1, 2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PB4, 4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PD0, 2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PB1, 5, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO1, RK_PD5, 4, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PB2, 5, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO1, RK_PD6, 4, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PB5, 5, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PA1, 2, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PB6, 5, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC0, 3, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PB7, 2, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC5, 1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PC0, 2, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC6, 1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PC4, 1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC2, 1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PC5, 1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC3, 1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD2, 3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PA5, 5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO0, RK_PB5, 2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PD3, 3, 0x030c, RK_GENMASK_VAL(0, 0, 1)), /* SPI0 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PB5, 3, 0x030c, RK_GENMASK_VAL(2, 2, 0)), /* SPI1 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PC3, 3, 0x030c, RK_GENMASK_VAL(2, 2, 1)), /* SPI1 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PC1, 4, 0x030c, RK_GENMASK_VAL(4, 4, 0)), /* SPI2 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PA0, 3, 0x030c, RK_GENMASK_VAL(4, 4, 1)), /* SPI2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO4, RK_PB3, 4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC2, 2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PB4, 2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD6, 4, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO0, RK_PD1, 1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO1, RK_PD5, 2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PA1, 2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PB7, 4, 0x030c, RK_GENMASK_VAL(12, 12, 1)), /* UART3 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PA6, 2, 0x030c, RK_GENMASK_VAL(14, 14, 0)), /* UART4 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PB2, 4, 0x030c, RK_GENMASK_VAL(14, 14, 1)), /* UART4 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PA2, 3, 0x0310, RK_GENMASK_VAL(0, 0, 0)), /* UART5 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PC2, 4, 0x0310, RK_GENMASK_VAL(0, 0, 1)), /* UART5 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PA4, 3, 0x0310, RK_GENMASK_VAL(2, 2, 0)), /* UART6 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO1, RK_PD5, 3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PA6, 3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PC4, 4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO4, RK_PA2, 4, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */ - MR_TOPGRF(RK_GPIO2, RK_PC5, 3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PD7, 4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PB0, 3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC5, 4, 0x0310, RK_GENMASK_VAL(9, 8, 1)), /* UART9 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO4, RK_PA4, 4, 0x0310, RK_GENMASK_VAL(9, 8, 2)), /* UART9 IO mux selection M2 */ - MR_TOPGRF(RK_GPIO1, RK_PA2, 1, 0x0310, RK_GENMASK_VAL(11, 10, 0)), /* I2S1 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PC6, 4, 0x0310, RK_GENMASK_VAL(11, 10, 1)), /* I2S1 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO2, RK_PD0, 5, 0x0310, RK_GENMASK_VAL(11, 10, 2)), /* I2S1 IO mux selection M2 */ - MR_TOPGRF(RK_GPIO2, RK_PC1, 1, 0x0310, RK_GENMASK_VAL(12, 12, 0)), /* I2S2 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PB6, 5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PA2, 4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO4, RK_PC2, 5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PA4, 3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */ - MR_TOPGRF(RK_GPIO1, RK_PA6, 3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */ - MR_TOPGRF(RK_GPIO3, RK_PD6, 5, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */ - MR_TOPGRF(RK_GPIO4, RK_PA0, 4, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */ - MR_TOPGRF(RK_GPIO3, RK_PC4, 5, 0x0314, RK_GENMASK_VAL(1, 0, 2)), /* PDM IO mux selection M2 */ - MR_TOPGRF(RK_GPIO0, RK_PA5, 3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PD0, 4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PB0, 4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */ - MR_TOPGRF(RK_GPIO0, RK_PA4, 3, 0x0314, RK_GENMASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PD2, 4, 0x0314, RK_GENMASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO1, RK_PA5, 4, 0x0314, RK_GENMASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux selection M2 */ - MR_TOPGRF(RK_GPIO0, RK_PA6, 2, 0x0314, RK_GENMASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux selection M0 */ - MR_TOPGRF(RK_GPIO2, RK_PD4, 4, 0x0314, RK_GENMASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux selection M1 */ - MR_TOPGRF(RK_GPIO4, RK_PC2, 4, 0x0314, RK_GENMASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux selection M2 */ + MR_PMUGRF(0, RK_PB7, 1, 0x0110, RK_GENMASK_VAL(1, 0, 0)), /* PWM0 IO mux selection M0 */ + MR_PMUGRF(0, RK_PC7, 2, 0x0110, RK_GENMASK_VAL(1, 0, 1)), /* PWM0 IO mux selection M1 */ + MR_PMUGRF(0, RK_PC0, 1, 0x0110, RK_GENMASK_VAL(3, 2, 0)), /* PWM1 IO mux selection M0 */ + MR_PMUGRF(0, RK_PB5, 4, 0x0110, RK_GENMASK_VAL(3, 2, 1)), /* PWM1 IO mux selection M1 */ + MR_PMUGRF(0, RK_PC1, 1, 0x0110, RK_GENMASK_VAL(5, 4, 0)), /* PWM2 IO mux selection M0 */ + MR_PMUGRF(0, RK_PB6, 4, 0x0110, RK_GENMASK_VAL(5, 4, 1)), /* PWM2 IO mux selection M1 */ + MR_TOPGRF(0, RK_PB3, 2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */ + MR_TOPGRF(2, RK_PA1, 4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */ + MR_TOPGRF(1, RK_PA1, 3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */ + MR_TOPGRF(4, RK_PC3, 3, 0x0300, RK_GENMASK_VAL(2, 2, 1)), /* CAN1 IO mux selection M1 */ + MR_TOPGRF(4, RK_PB5, 3, 0x0300, RK_GENMASK_VAL(4, 4, 0)), /* CAN2 IO mux selection M0 */ + MR_TOPGRF(2, RK_PB2, 4, 0x0300, RK_GENMASK_VAL(4, 4, 1)), /* CAN2 IO mux selection M1 */ + MR_TOPGRF(4, RK_PC4, 1, 0x0300, RK_GENMASK_VAL(6, 6, 0)), /* EDPDP_HPDIN IO mux selection M0 */ + MR_TOPGRF(0, RK_PC2, 2, 0x0300, RK_GENMASK_VAL(6, 6, 1)), /* EDPDP_HPDIN IO mux selection M1 */ + MR_TOPGRF(3, RK_PB1, 3, 0x0300, RK_GENMASK_VAL(8, 8, 0)), /* GMAC1 IO mux selection M0 */ + MR_TOPGRF(4, RK_PA7, 3, 0x0300, RK_GENMASK_VAL(8, 8, 1)), /* GMAC1 IO mux selection M1 */ + MR_TOPGRF(4, RK_PD1, 1, 0x0300, RK_GENMASK_VAL(10, 10, 0)), /* HDMITX IO mux selection M0 */ + MR_TOPGRF(0, RK_PC7, 1, 0x0300, RK_GENMASK_VAL(10, 10, 1)), /* HDMITX IO mux selection M1 */ + MR_TOPGRF(0, RK_PB6, 1, 0x0300, RK_GENMASK_VAL(14, 14, 0)), /* I2C2 IO mux selection M0 */ + MR_TOPGRF(4, RK_PB4, 1, 0x0300, RK_GENMASK_VAL(14, 14, 1)), /* I2C2 IO mux selection M1 */ + MR_TOPGRF(1, RK_PA0, 1, 0x0304, RK_GENMASK_VAL(0, 0, 0)), /* I2C3 IO mux selection M0 */ + MR_TOPGRF(3, RK_PB6, 4, 0x0304, RK_GENMASK_VAL(0, 0, 1)), /* I2C3 IO mux selection M1 */ + MR_TOPGRF(4, RK_PB2, 1, 0x0304, RK_GENMASK_VAL(2, 2, 0)), /* I2C4 IO mux selection M0 */ + MR_TOPGRF(2, RK_PB1, 2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */ + MR_TOPGRF(3, RK_PB4, 4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */ + MR_TOPGRF(4, RK_PD0, 2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */ + MR_TOPGRF(3, RK_PB1, 5, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */ + MR_TOPGRF(1, RK_PD5, 4, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */ + MR_TOPGRF(3, RK_PB2, 5, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */ + MR_TOPGRF(1, RK_PD6, 4, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */ + MR_TOPGRF(3, RK_PB5, 5, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */ + MR_TOPGRF(2, RK_PA1, 2, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */ + MR_TOPGRF(3, RK_PB6, 5, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */ + MR_TOPGRF(4, RK_PC0, 3, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */ + MR_TOPGRF(3, RK_PB7, 2, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */ + MR_TOPGRF(4, RK_PC5, 1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */ + MR_TOPGRF(3, RK_PC0, 2, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */ + MR_TOPGRF(4, RK_PC6, 1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */ + MR_TOPGRF(3, RK_PC4, 1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */ + MR_TOPGRF(4, RK_PC2, 1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */ + MR_TOPGRF(3, RK_PC5, 1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */ + MR_TOPGRF(4, RK_PC3, 1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */ + MR_TOPGRF(3, RK_PD2, 3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */ + MR_TOPGRF(3, RK_PA5, 5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */ + MR_TOPGRF(0, RK_PB5, 2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */ + MR_TOPGRF(2, RK_PD3, 3, 0x030c, RK_GENMASK_VAL(0, 0, 1)), /* SPI0 IO mux selection M1 */ + MR_TOPGRF(2, RK_PB5, 3, 0x030c, RK_GENMASK_VAL(2, 2, 0)), /* SPI1 IO mux selection M0 */ + MR_TOPGRF(3, RK_PC3, 3, 0x030c, RK_GENMASK_VAL(2, 2, 1)), /* SPI1 IO mux selection M1 */ + MR_TOPGRF(2, RK_PC1, 4, 0x030c, RK_GENMASK_VAL(4, 4, 0)), /* SPI2 IO mux selection M0 */ + MR_TOPGRF(3, RK_PA0, 3, 0x030c, RK_GENMASK_VAL(4, 4, 1)), /* SPI2 IO mux selection M1 */ + MR_TOPGRF(4, RK_PB3, 4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */ + MR_TOPGRF(4, RK_PC2, 2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */ + MR_TOPGRF(2, RK_PB4, 2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */ + MR_TOPGRF(3, RK_PD6, 4, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */ + MR_TOPGRF(0, RK_PD1, 1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */ + MR_TOPGRF(1, RK_PD5, 2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */ + MR_TOPGRF(1, RK_PA1, 2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */ + MR_TOPGRF(3, RK_PB7, 4, 0x030c, RK_GENMASK_VAL(12, 12, 1)), /* UART3 IO mux selection M1 */ + MR_TOPGRF(1, RK_PA6, 2, 0x030c, RK_GENMASK_VAL(14, 14, 0)), /* UART4 IO mux selection M0 */ + MR_TOPGRF(3, RK_PB2, 4, 0x030c, RK_GENMASK_VAL(14, 14, 1)), /* UART4 IO mux selection M1 */ + MR_TOPGRF(2, RK_PA2, 3, 0x0310, RK_GENMASK_VAL(0, 0, 0)), /* UART5 IO mux selection M0 */ + MR_TOPGRF(3, RK_PC2, 4, 0x0310, RK_GENMASK_VAL(0, 0, 1)), /* UART5 IO mux selection M1 */ + MR_TOPGRF(2, RK_PA4, 3, 0x0310, RK_GENMASK_VAL(2, 2, 0)), /* UART6 IO mux selection M0 */ + MR_TOPGRF(1, RK_PD5, 3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */ + MR_TOPGRF(2, RK_PA6, 3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */ + MR_TOPGRF(3, RK_PC4, 4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */ + MR_TOPGRF(4, RK_PA2, 4, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */ + MR_TOPGRF(2, RK_PC5, 3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */ + MR_TOPGRF(2, RK_PD7, 4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */ + MR_TOPGRF(2, RK_PB0, 3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */ + MR_TOPGRF(4, RK_PC5, 4, 0x0310, RK_GENMASK_VAL(9, 8, 1)), /* UART9 IO mux selection M1 */ + MR_TOPGRF(4, RK_PA4, 4, 0x0310, RK_GENMASK_VAL(9, 8, 2)), /* UART9 IO mux selection M2 */ + MR_TOPGRF(1, RK_PA2, 1, 0x0310, RK_GENMASK_VAL(11, 10, 0)), /* I2S1 IO mux selection M0 */ + MR_TOPGRF(3, RK_PC6, 4, 0x0310, RK_GENMASK_VAL(11, 10, 1)), /* I2S1 IO mux selection M1 */ + MR_TOPGRF(2, RK_PD0, 5, 0x0310, RK_GENMASK_VAL(11, 10, 2)), /* I2S1 IO mux selection M2 */ + MR_TOPGRF(2, RK_PC1, 1, 0x0310, RK_GENMASK_VAL(12, 12, 0)), /* I2S2 IO mux selection M0 */ + MR_TOPGRF(4, RK_PB6, 5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */ + MR_TOPGRF(3, RK_PA2, 4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */ + MR_TOPGRF(4, RK_PC2, 5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */ + MR_TOPGRF(1, RK_PA4, 3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */ + MR_TOPGRF(1, RK_PA6, 3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */ + MR_TOPGRF(3, RK_PD6, 5, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */ + MR_TOPGRF(4, RK_PA0, 4, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */ + MR_TOPGRF(3, RK_PC4, 5, 0x0314, RK_GENMASK_VAL(1, 0, 2)), /* PDM IO mux selection M2 */ + MR_TOPGRF(0, RK_PA5, 3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */ + MR_TOPGRF(2, RK_PD0, 4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */ + MR_TOPGRF(1, RK_PB0, 4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */ + MR_TOPGRF(0, RK_PA4, 3, 0x0314, RK_GENMASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux selection M0 */ + MR_TOPGRF(2, RK_PD2, 4, 0x0314, RK_GENMASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux selection M1 */ + MR_TOPGRF(1, RK_PA5, 4, 0x0314, RK_GENMASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux selection M2 */ + MR_TOPGRF(0, RK_PA6, 2, 0x0314, RK_GENMASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux selection M0 */ + MR_TOPGRF(2, RK_PD4, 4, 0x0314, RK_GENMASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux selection M1 */ + MR_TOPGRF(4, RK_PC2, 4, 0x0314, RK_GENMASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux selection M2 */ }; static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1126.c b/drivers/pinctrl/rockchip/pinctrl-rv1126.c index 3878a5420dc..88966ef34a6 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rv1126.c +++ b/drivers/pinctrl/rockchip/pinctrl-rv1126.c @@ -45,101 +45,101 @@ static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { }; static struct rockchip_mux_route_data rv1126_mux_route_data[] = { - MR_TOPGRF(RK_GPIO3, RK_PD2, 1, 0x10260, RK_GENMASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */ - MR_TOPGRF(RK_GPIO3, RK_PB0, 3, 0x10260, RK_GENMASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */ + MR_TOPGRF(3, RK_PD2, 1, 0x10260, RK_GENMASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */ + MR_TOPGRF(3, RK_PB0, 3, 0x10260, RK_GENMASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */ - MR_TOPGRF(RK_GPIO0, RK_PD4, 4, 0x10260, RK_GENMASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */ - MR_TOPGRF(RK_GPIO1, RK_PD5, 2, 0x10260, RK_GENMASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */ - MR_TOPGRF(RK_GPIO2, RK_PC7, 6, 0x10260, RK_GENMASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */ + MR_TOPGRF(0, RK_PD4, 4, 0x10260, RK_GENMASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */ + MR_TOPGRF(1, RK_PD5, 2, 0x10260, RK_GENMASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */ + MR_TOPGRF(2, RK_PC7, 6, 0x10260, RK_GENMASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */ - MR_TOPGRF(RK_GPIO1, RK_PD0, 1, 0x10260, RK_GENMASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */ - MR_TOPGRF(RK_GPIO2, RK_PB3, 2, 0x10260, RK_GENMASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */ + MR_TOPGRF(1, RK_PD0, 1, 0x10260, RK_GENMASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */ + MR_TOPGRF(2, RK_PB3, 2, 0x10260, RK_GENMASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */ - MR_TOPGRF(RK_GPIO3, RK_PD4, 2, 0x10260, RK_GENMASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */ - MR_TOPGRF(RK_GPIO3, RK_PC0, 3, 0x10260, RK_GENMASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */ + MR_TOPGRF(3, RK_PD4, 2, 0x10260, RK_GENMASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */ + MR_TOPGRF(3, RK_PC0, 3, 0x10260, RK_GENMASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */ - MR_TOPGRF(RK_GPIO3, RK_PC6, 1, 0x10264, RK_GENMASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */ - MR_TOPGRF(RK_GPIO2, RK_PD1, 3, 0x10264, RK_GENMASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */ + MR_TOPGRF(3, RK_PC6, 1, 0x10264, RK_GENMASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */ + MR_TOPGRF(2, RK_PD1, 3, 0x10264, RK_GENMASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */ - MR_TOPGRF(RK_GPIO3, RK_PA4, 5, 0x10264, RK_GENMASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */ - MR_TOPGRF(RK_GPIO2, RK_PD4, 7, 0x10264, RK_GENMASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */ - MR_TOPGRF(RK_GPIO1, RK_PD6, 3, 0x10264, RK_GENMASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */ + MR_TOPGRF(3, RK_PA4, 5, 0x10264, RK_GENMASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */ + MR_TOPGRF(2, RK_PD4, 7, 0x10264, RK_GENMASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */ + MR_TOPGRF(1, RK_PD6, 3, 0x10264, RK_GENMASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */ - MR_TOPGRF(RK_GPIO3, RK_PA0, 7, 0x10264, RK_GENMASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */ - MR_TOPGRF(RK_GPIO4, RK_PA0, 4, 0x10264, RK_GENMASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */ + MR_TOPGRF(3, RK_PA0, 7, 0x10264, RK_GENMASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */ + MR_TOPGRF(4, RK_PA0, 4, 0x10264, RK_GENMASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */ - MR_TOPGRF(RK_GPIO2, RK_PA5, 7, 0x10264, RK_GENMASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */ - MR_TOPGRF(RK_GPIO3, RK_PB0, 5, 0x10264, RK_GENMASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */ - MR_TOPGRF(RK_GPIO1, RK_PD0, 4, 0x10264, RK_GENMASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */ + MR_TOPGRF(2, RK_PA5, 7, 0x10264, RK_GENMASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */ + MR_TOPGRF(3, RK_PB0, 5, 0x10264, RK_GENMASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */ + MR_TOPGRF(1, RK_PD0, 4, 0x10264, RK_GENMASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */ - MR_TOPGRF(RK_GPIO3, RK_PC0, 5, 0x10264, RK_GENMASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */ - MR_TOPGRF(RK_GPIO1, RK_PC6, 3, 0x10264, RK_GENMASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */ - MR_TOPGRF(RK_GPIO2, RK_PD5, 6, 0x10264, RK_GENMASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */ + MR_TOPGRF(3, RK_PC0, 5, 0x10264, RK_GENMASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */ + MR_TOPGRF(1, RK_PC6, 3, 0x10264, RK_GENMASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */ + MR_TOPGRF(2, RK_PD5, 6, 0x10264, RK_GENMASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */ - MR_TOPGRF(RK_GPIO3, RK_PC0, 2, 0x10264, RK_GENMASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */ - MR_TOPGRF(RK_GPIO2, RK_PB7, 2, 0x10264, RK_GENMASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */ + MR_TOPGRF(3, RK_PC0, 2, 0x10264, RK_GENMASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */ + MR_TOPGRF(2, RK_PB7, 2, 0x10264, RK_GENMASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */ - MR_TOPGRF(RK_GPIO3, RK_PA1, 3, 0x10264, RK_GENMASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */ - MR_TOPGRF(RK_GPIO3, RK_PA7, 5, 0x10264, RK_GENMASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */ + MR_TOPGRF(3, RK_PA1, 3, 0x10264, RK_GENMASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */ + MR_TOPGRF(3, RK_PA7, 5, 0x10264, RK_GENMASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */ - MR_TOPGRF(RK_GPIO3, RK_PA4, 6, 0x10268, RK_GENMASK_VAL(0, 0, 0)), /* PWM8_M0 */ - MR_TOPGRF(RK_GPIO2, RK_PD7, 5, 0x10268, RK_GENMASK_VAL(0, 0, 1)), /* PWM8_M1 */ + MR_TOPGRF(3, RK_PA4, 6, 0x10268, RK_GENMASK_VAL(0, 0, 0)), /* PWM8_M0 */ + MR_TOPGRF(2, RK_PD7, 5, 0x10268, RK_GENMASK_VAL(0, 0, 1)), /* PWM8_M1 */ - MR_TOPGRF(RK_GPIO3, RK_PA5, 6, 0x10268, RK_GENMASK_VAL(2, 2, 0)), /* PWM9_M0 */ - MR_TOPGRF(RK_GPIO2, RK_PD6, 5, 0x10268, RK_GENMASK_VAL(2, 2, 1)), /* PWM9_M1 */ + MR_TOPGRF(3, RK_PA5, 6, 0x10268, RK_GENMASK_VAL(2, 2, 0)), /* PWM9_M0 */ + MR_TOPGRF(2, RK_PD6, 5, 0x10268, RK_GENMASK_VAL(2, 2, 1)), /* PWM9_M1 */ - MR_TOPGRF(RK_GPIO3, RK_PA6, 6, 0x10268, RK_GENMASK_VAL(4, 4, 0)), /* PWM10_M0 */ - MR_TOPGRF(RK_GPIO2, RK_PD5, 5, 0x10268, RK_GENMASK_VAL(4, 4, 1)), /* PWM10_M1 */ + MR_TOPGRF(3, RK_PA6, 6, 0x10268, RK_GENMASK_VAL(4, 4, 0)), /* PWM10_M0 */ + MR_TOPGRF(2, RK_PD5, 5, 0x10268, RK_GENMASK_VAL(4, 4, 1)), /* PWM10_M1 */ - MR_TOPGRF(RK_GPIO3, RK_PA7, 6, 0x10268, RK_GENMASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */ - MR_TOPGRF(RK_GPIO3, RK_PA1, 5, 0x10268, RK_GENMASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */ + MR_TOPGRF(3, RK_PA7, 6, 0x10268, RK_GENMASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */ + MR_TOPGRF(3, RK_PA1, 5, 0x10268, RK_GENMASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */ - MR_TOPGRF(RK_GPIO1, RK_PA5, 3, 0x10268, RK_GENMASK_VAL(8, 8, 0)), /* UART2_TX_M0 */ - MR_TOPGRF(RK_GPIO3, RK_PA2, 1, 0x10268, RK_GENMASK_VAL(8, 8, 1)), /* UART2_TX_M1 */ + MR_TOPGRF(1, RK_PA5, 3, 0x10268, RK_GENMASK_VAL(8, 8, 0)), /* UART2_TX_M0 */ + MR_TOPGRF(3, RK_PA2, 1, 0x10268, RK_GENMASK_VAL(8, 8, 1)), /* UART2_TX_M1 */ - MR_TOPGRF(RK_GPIO3, RK_PC6, 3, 0x10268, RK_GENMASK_VAL(11, 10, 0)), /* UART3_TX_M0 */ - MR_TOPGRF(RK_GPIO1, RK_PA7, 2, 0x10268, RK_GENMASK_VAL(11, 10, 1)), /* UART3_TX_M1 */ - MR_TOPGRF(RK_GPIO3, RK_PA0, 4, 0x10268, RK_GENMASK_VAL(11, 10, 2)), /* UART3_TX_M2 */ + MR_TOPGRF(3, RK_PC6, 3, 0x10268, RK_GENMASK_VAL(11, 10, 0)), /* UART3_TX_M0 */ + MR_TOPGRF(1, RK_PA7, 2, 0x10268, RK_GENMASK_VAL(11, 10, 1)), /* UART3_TX_M1 */ + MR_TOPGRF(3, RK_PA0, 4, 0x10268, RK_GENMASK_VAL(11, 10, 2)), /* UART3_TX_M2 */ - MR_TOPGRF(RK_GPIO3, RK_PA4, 4, 0x10268, RK_GENMASK_VAL(13, 12, 0)), /* UART4_TX_M0 */ - MR_TOPGRF(RK_GPIO2, RK_PA6, 4, 0x10268, RK_GENMASK_VAL(13, 12, 1)), /* UART4_TX_M1 */ - MR_TOPGRF(RK_GPIO1, RK_PD5, 3, 0x10268, RK_GENMASK_VAL(13, 12, 2)), /* UART4_TX_M2 */ + MR_TOPGRF(3, RK_PA4, 4, 0x10268, RK_GENMASK_VAL(13, 12, 0)), /* UART4_TX_M0 */ + MR_TOPGRF(2, RK_PA6, 4, 0x10268, RK_GENMASK_VAL(13, 12, 1)), /* UART4_TX_M1 */ + MR_TOPGRF(1, RK_PD5, 3, 0x10268, RK_GENMASK_VAL(13, 12, 2)), /* UART4_TX_M2 */ - MR_TOPGRF(RK_GPIO3, RK_PA6, 4, 0x10268, RK_GENMASK_VAL(15, 14, 0)), /* UART5_TX_M0 */ - MR_TOPGRF(RK_GPIO2, RK_PB0, 4, 0x10268, RK_GENMASK_VAL(15, 14, 1)), /* UART5_TX_M1 */ - MR_TOPGRF(RK_GPIO2, RK_PA0, 3, 0x10268, RK_GENMASK_VAL(15, 14, 2)), /* UART5_TX_M2 */ + MR_TOPGRF(3, RK_PA6, 4, 0x10268, RK_GENMASK_VAL(15, 14, 0)), /* UART5_TX_M0 */ + MR_TOPGRF(2, RK_PB0, 4, 0x10268, RK_GENMASK_VAL(15, 14, 1)), /* UART5_TX_M1 */ + MR_TOPGRF(2, RK_PA0, 3, 0x10268, RK_GENMASK_VAL(15, 14, 2)), /* UART5_TX_M2 */ - MR_PMUGRF(RK_GPIO0, RK_PB6, 3, 0x0114, RK_GENMASK_VAL(0, 0, 0)), /* PWM0_M0 */ - MR_PMUGRF(RK_GPIO2, RK_PB3, 5, 0x0114, RK_GENMASK_VAL(0, 0, 1)), /* PWM0_M1 */ + MR_PMUGRF(0, RK_PB6, 3, 0x0114, RK_GENMASK_VAL(0, 0, 0)), /* PWM0_M0 */ + MR_PMUGRF(2, RK_PB3, 5, 0x0114, RK_GENMASK_VAL(0, 0, 1)), /* PWM0_M1 */ - MR_PMUGRF(RK_GPIO0, RK_PB7, 3, 0x0114, RK_GENMASK_VAL(2, 2, 0)), /* PWM1_M0 */ - MR_PMUGRF(RK_GPIO2, RK_PB2, 5, 0x0114, RK_GENMASK_VAL(2, 2, 1)), /* PWM1_M1 */ + MR_PMUGRF(0, RK_PB7, 3, 0x0114, RK_GENMASK_VAL(2, 2, 0)), /* PWM1_M0 */ + MR_PMUGRF(2, RK_PB2, 5, 0x0114, RK_GENMASK_VAL(2, 2, 1)), /* PWM1_M1 */ - MR_PMUGRF(RK_GPIO0, RK_PC0, 3, 0x0114, RK_GENMASK_VAL(4, 4, 0)), /* PWM2_M0 */ - MR_PMUGRF(RK_GPIO2, RK_PB1, 5, 0x0114, RK_GENMASK_VAL(4, 4, 1)), /* PWM2_M1 */ + MR_PMUGRF(0, RK_PC0, 3, 0x0114, RK_GENMASK_VAL(4, 4, 0)), /* PWM2_M0 */ + MR_PMUGRF(2, RK_PB1, 5, 0x0114, RK_GENMASK_VAL(4, 4, 1)), /* PWM2_M1 */ - MR_PMUGRF(RK_GPIO0, RK_PC1, 3, 0x0114, RK_GENMASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */ - MR_PMUGRF(RK_GPIO2, RK_PB0, 5, 0x0114, RK_GENMASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */ + MR_PMUGRF(0, RK_PC1, 3, 0x0114, RK_GENMASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */ + MR_PMUGRF(2, RK_PB0, 5, 0x0114, RK_GENMASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */ - MR_PMUGRF(RK_GPIO0, RK_PC2, 3, 0x0114, RK_GENMASK_VAL(8, 8, 0)), /* PWM4_M0 */ - MR_PMUGRF(RK_GPIO2, RK_PA7, 5, 0x0114, RK_GENMASK_VAL(8, 8, 1)), /* PWM4_M1 */ + MR_PMUGRF(0, RK_PC2, 3, 0x0114, RK_GENMASK_VAL(8, 8, 0)), /* PWM4_M0 */ + MR_PMUGRF(2, RK_PA7, 5, 0x0114, RK_GENMASK_VAL(8, 8, 1)), /* PWM4_M1 */ - MR_PMUGRF(RK_GPIO0, RK_PC3, 3, 0x0114, RK_GENMASK_VAL(10, 10, 0)), /* PWM5_M0 */ - MR_PMUGRF(RK_GPIO2, RK_PA6, 5, 0x0114, RK_GENMASK_VAL(10, 10, 1)), /* PWM5_M1 */ + MR_PMUGRF(0, RK_PC3, 3, 0x0114, RK_GENMASK_VAL(10, 10, 0)), /* PWM5_M0 */ + MR_PMUGRF(2, RK_PA6, 5, 0x0114, RK_GENMASK_VAL(10, 10, 1)), /* PWM5_M1 */ - MR_PMUGRF(RK_GPIO0, RK_PB2, 3, 0x0114, RK_GENMASK_VAL(12, 12, 0)), /* PWM6_M0 */ - MR_PMUGRF(RK_GPIO2, RK_PD4, 5, 0x0114, RK_GENMASK_VAL(12, 12, 1)), /* PWM6_M1 */ + MR_PMUGRF(0, RK_PB2, 3, 0x0114, RK_GENMASK_VAL(12, 12, 0)), /* PWM6_M0 */ + MR_PMUGRF(2, RK_PD4, 5, 0x0114, RK_GENMASK_VAL(12, 12, 1)), /* PWM6_M1 */ - MR_PMUGRF(RK_GPIO0, RK_PB1, 3, 0x0114, RK_GENMASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */ - MR_PMUGRF(RK_GPIO3, RK_PA0, 5, 0x0114, RK_GENMASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */ + MR_PMUGRF(0, RK_PB1, 3, 0x0114, RK_GENMASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */ + MR_PMUGRF(3, RK_PA0, 5, 0x0114, RK_GENMASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */ - MR_PMUGRF(RK_GPIO0, RK_PB0, 1, 0x0118, RK_GENMASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */ - MR_PMUGRF(RK_GPIO2, RK_PA1, 1, 0x0118, RK_GENMASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */ - MR_PMUGRF(RK_GPIO2, RK_PB2, 6, 0x0118, RK_GENMASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */ + MR_PMUGRF(0, RK_PB0, 1, 0x0118, RK_GENMASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */ + MR_PMUGRF(2, RK_PA1, 1, 0x0118, RK_GENMASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */ + MR_PMUGRF(2, RK_PB2, 6, 0x0118, RK_GENMASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */ - MR_PMUGRF(RK_GPIO0, RK_PB6, 2, 0x0118, RK_GENMASK_VAL(2, 2, 0)), /* UART1_TX_M0 */ - MR_PMUGRF(RK_GPIO1, RK_PD0, 5, 0x0118, RK_GENMASK_VAL(2, 2, 1)), /* UART1_TX_M1 */ - MR_PMUGRF(RK_GPIO0, RK_PC3, 1, 0x0118, RK_GENMASK_VAL(4, 4, 1)), /* I2C2 */ + MR_PMUGRF(0, RK_PB6, 2, 0x0118, RK_GENMASK_VAL(2, 2, 0)), /* UART1_TX_M0 */ + MR_PMUGRF(1, RK_PD0, 5, 0x0118, RK_GENMASK_VAL(2, 2, 1)), /* UART1_TX_M1 */ + MR_PMUGRF(0, RK_PC3, 1, 0x0118, RK_GENMASK_VAL(4, 4, 1)), /* I2C2 */ }; static int rv1126_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h index 1636ec99eb6..88544766f18 100644 --- a/include/dt-bindings/pinctrl/rockchip.h +++ b/include/dt-bindings/pinctrl/rockchip.h @@ -9,13 +9,6 @@ #ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ #define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ -#define RK_GPIO0 0 -#define RK_GPIO1 1 -#define RK_GPIO2 2 -#define RK_GPIO3 3 -#define RK_GPIO4 4 -#define RK_GPIO6 6 - #define RK_PA0 0 #define RK_PA1 1 #define RK_PA2 2 -- cgit v1.3.1 From 51947d401762b908e3ded680a491e119e76c6acd Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 9 Jun 2026 22:23:30 +0200 Subject: rockchip: pinctrl: use include from dts/upstream Use Rockchip pinctrl include from dts/upstream and remove what is now redundant. Signed-off-by: Johan Jonker Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/5c0bc31f-047b-4b51-999f-7f6cebd8378b@gmail.com Signed-off-by: Quentin Schulz --- include/dt-bindings/pinctrl/rockchip.h | 47 ---------------------------------- 1 file changed, 47 deletions(-) delete mode 100644 include/dt-bindings/pinctrl/rockchip.h diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h deleted file mode 100644 index 88544766f18..00000000000 --- a/include/dt-bindings/pinctrl/rockchip.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Header providing constants for Rockchip pinctrl bindings. - * - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ -#define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ - -#define RK_PA0 0 -#define RK_PA1 1 -#define RK_PA2 2 -#define RK_PA3 3 -#define RK_PA4 4 -#define RK_PA5 5 -#define RK_PA6 6 -#define RK_PA7 7 -#define RK_PB0 8 -#define RK_PB1 9 -#define RK_PB2 10 -#define RK_PB3 11 -#define RK_PB4 12 -#define RK_PB5 13 -#define RK_PB6 14 -#define RK_PB7 15 -#define RK_PC0 16 -#define RK_PC1 17 -#define RK_PC2 18 -#define RK_PC3 19 -#define RK_PC4 20 -#define RK_PC5 21 -#define RK_PC6 22 -#define RK_PC7 23 -#define RK_PD0 24 -#define RK_PD1 25 -#define RK_PD2 26 -#define RK_PD3 27 -#define RK_PD4 28 -#define RK_PD5 29 -#define RK_PD6 30 -#define RK_PD7 31 - -#define RK_FUNC_GPIO 0 - -#endif -- cgit v1.3.1 From 15387d5a90af01eb52f0c18cd83e358ba19c0a7d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 22 Jul 2026 15:40:24 -0300 Subject: rockchip: rk3588s: Add support for ROC-RK3588S-PC The ROC-RK3588S-PC board is an SBC made by Firefly, based on the RK3588S SoC. Add support for it. Signed-off-by: Fabio Estevam Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/20260722184024.1210447-1-festevam@gmail.com [s/ROC-PC-RK3588S/ROC-RK3588S-PC/ in commit log and diff] Signed-off-by: Quentin Schulz --- arch/arm/mach-rockchip/rk3588/Kconfig | 7 +++ board/firefly/roc-pc-rk3588s/Kconfig | 12 +++++ board/firefly/roc-pc-rk3588s/MAINTAINERS | 6 +++ configs/roc-pc-rk3588s_defconfig | 81 ++++++++++++++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + include/configs/roc-pc-rk3588s.h | 8 ++++ 6 files changed, 115 insertions(+) create mode 100644 board/firefly/roc-pc-rk3588s/Kconfig create mode 100644 board/firefly/roc-pc-rk3588s/MAINTAINERS create mode 100644 configs/roc-pc-rk3588s_defconfig create mode 100644 include/configs/roc-pc-rk3588s.h diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 675f13ab66d..841ae490e85 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -208,6 +208,12 @@ config TARGET_RK3588_NEU6 IO board and Neu6a needs to mount on top of this IO board in order to create complete Edgeble Neural Compute Module 6B(Neu6B) IO platform. +config TARGET_ROC_PC_RK3588S + bool "Firefly ROC PC RK3588S" + help + ROC-PC-RK3588S is a single board computer from Firefly + using the Rockchip RK3588S. + config TARGET_ROCK5A_RK3588 bool "Radxa ROCK5A RK3588 board" help @@ -421,6 +427,7 @@ config SYS_SOC source "board/armsom/sige7-rk3588/Kconfig" source "board/coolpi/genbook_cm5_rk3588/Kconfig" source "board/edgeble/neural-compute-module-6/Kconfig" +source "board/firefly/roc-pc-rk3588s/Kconfig" source "board/friendlyelec/cm3588-nas-rk3588/Kconfig" source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig" diff --git a/board/firefly/roc-pc-rk3588s/Kconfig b/board/firefly/roc-pc-rk3588s/Kconfig new file mode 100644 index 00000000000..bded7a2fcba --- /dev/null +++ b/board/firefly/roc-pc-rk3588s/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ROC_PC_RK3588S + +config SYS_BOARD + default "roc-pc-rk3588s" + +config SYS_VENDOR + default "firefly" + +config SYS_CONFIG_NAME + default "roc-pc-rk3588s" + +endif diff --git a/board/firefly/roc-pc-rk3588s/MAINTAINERS b/board/firefly/roc-pc-rk3588s/MAINTAINERS new file mode 100644 index 00000000000..de631519311 --- /dev/null +++ b/board/firefly/roc-pc-rk3588s/MAINTAINERS @@ -0,0 +1,6 @@ +ROC-RK3588S-PC +M: Fabio Estevam +S: Maintained +F: board/firefly/roc-pc-rk3588s/ +F: configs/roc-pc-rk3588s_defconfig +F: include/configs/roc-pc-rk3588s.h diff --git a/configs/roc-pc-rk3588s_defconfig b/configs/roc-pc-rk3588s_defconfig new file mode 100644 index 00000000000..226243d7977 --- /dev/null +++ b/configs/roc-pc-rk3588s_defconfig @@ -0,0 +1,81 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-roc-pc" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_ROC_PC_RK3588S=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_ENV_OFFSET_REDUND=0x400000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-roc-pc.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_REDUNDANT=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 0c0cde7ec38..2e2741bc7cc 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -156,6 +156,7 @@ List of mainline supported Rockchip boards: - Rockchip EVB (evb-rk3588) - Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588) - Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588) + - Firefly ROC-RK3588S-PC (roc-pc-rk3588s) - FriendlyElec CM3588 NAS (cm3588-nas-rk3588) - FriendlyElec NanoPC-T6 (nanopc-t6-rk3588) - FriendlyElec NanoPi R6C (nanopi-r6c-rk3588s) diff --git a/include/configs/roc-pc-rk3588s.h b/include/configs/roc-pc-rk3588s.h new file mode 100644 index 00000000000..c9316687c38 --- /dev/null +++ b/include/configs/roc-pc-rk3588s.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ROC_PC_RK3588S_H +#define __ROC_PC_RK3588S_H + +#include + +#endif /* __ROC_PC_RK3588S_H */ -- cgit v1.3.1 From d97d3df79e7bd7021dac0a1974c314c5acb07ac3 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 23 Jul 2026 17:22:59 +0200 Subject: mtd: nand: raw: rockchip_nfc: fix ecc setup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A Rockchip NAND Flash Controller (NFC) supports multiple flash devices. The SoC boot ROM only checks for NAND chip 0 and with reduced ECC strength. Currently only the read page functions have this condition check added in the U-Boot driver. In single- and multi-chip nodes with rockchip,boot-blks and rockchip,boot-ecc-strength set, the chips that aren't chip 0 will thus have an ECC mismatch when writing and reading. Fix by adding the same condition to all read and write page functions by dropping the existing 'selected_bank == 0' check and use the NAND_IS_BOOT_MEDIUM option that was introduced to U-Boot more recently than this driver to behave identically to the Linux driver. NAND_IS_BOOT_MEDIUM is automatically set when nand-is-boot-medium property is set in the Device Tree, which is a requirement for rockchip,boot-blks and rockchip,boot-ecc-strength and will thus apply to all chips in single- and multi-chips nodes, regardless of the CS. Fixes: b12dc5d6fa76 ("mtd: nand: NFC drivers for RK3308, RK2928 and others") Signed-off-by: Johan Jonker Tested-by: Hüseyin BIYIK Reviewed-by: Simon Glass Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/5690db1e-4de5-44bc-a9c0-58ad23662753@gmail.com Signed-off-by: Quentin Schulz --- drivers/mtd/nand/raw/rockchip_nfc.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c b/drivers/mtd/nand/raw/rockchip_nfc.c index ea8e67d1a23..d23a651f369 100644 --- a/drivers/mtd/nand/raw/rockchip_nfc.c +++ b/drivers/mtd/nand/raw/rockchip_nfc.c @@ -440,7 +440,8 @@ static int rk_nfc_write_page_raw(struct mtd_info *mtd, int i, pages_per_blk; pages_per_blk = mtd->erasesize / mtd->writesize; - if ((page < (pages_per_blk * rknand->boot_blks)) && + if ((chip->options & NAND_IS_BOOT_MEDIUM) && + (page < (pages_per_blk * rknand->boot_blks)) && rknand->boot_ecc != ecc->strength) { /* * There's currently no method to notify the MTD framework that @@ -560,7 +561,8 @@ static int rk_nfc_write_page_hwecc(struct mtd_info *mtd, * * Configure the ECC algorithm supported by the boot ROM. */ - if (page < (pages_per_blk * rknand->boot_blks)) { + if ((page < (pages_per_blk * rknand->boot_blks)) && + (chip->options & NAND_IS_BOOT_MEDIUM)) { boot_rom_mode = 1; if (rknand->boot_ecc != ecc->strength) rk_nfc_hw_ecc_setup(chip, rknand->boot_ecc); @@ -624,8 +626,8 @@ static int rk_nfc_read_page_raw(struct mtd_info *mtd, int i, pages_per_blk; pages_per_blk = mtd->erasesize / mtd->writesize; - if ((page < (pages_per_blk * rknand->boot_blks)) && - nfc->selected_bank == 0 && + if ((chip->options & NAND_IS_BOOT_MEDIUM) && + (page < (pages_per_blk * rknand->boot_blks)) && rknand->boot_ecc != ecc->strength) { /* * There's currently no method to notify the MTD framework that @@ -700,8 +702,8 @@ static int rk_nfc_read_page_hwecc(struct mtd_info *mtd, * are used by the boot ROM. * Configure the ECC algorithm supported by the boot ROM. */ - if (page < (pages_per_blk * rknand->boot_blks) && - nfc->selected_bank == 0) { + if ((page < (pages_per_blk * rknand->boot_blks)) && + (chip->options & NAND_IS_BOOT_MEDIUM)) { boot_rom_mode = 1; if (rknand->boot_ecc != ecc->strength) rk_nfc_hw_ecc_setup(chip, rknand->boot_ecc); -- cgit v1.3.1