From 70cee8ab03c3252d17cb0c10bfe80cbda7ef4bb9 Mon Sep 17 00:00:00 2001 From: Raymond Mao Date: Tue, 30 Jun 2026 09:19:07 +0800 Subject: dts: k1: enable clocks in SPL Make the K1 clock controllers visible to SPL by tagging the four root fixed clocks (osc_32k, vctcxo_{1,3,24}m) and the four syscon nodes (mpmu, pll, apmu, apbc) with bootph-pre-ram in the BPI-F3 U-Boot overlay. Signed-off-by: Raymond Mao Signed-off-by: Guodong Xu Tested-by: Songsong Zhang --- arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi | 32 +++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi index ef63b43f69f..e140c07b834 100644 --- a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi +++ b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi @@ -15,3 +15,35 @@ &uart0 { bootph-pre-ram; }; + +&osc_32k { + bootph-pre-ram; +}; + +&vctcxo_1m { + bootph-pre-ram; +}; + +&vctcxo_3m { + bootph-pre-ram; +}; + +&vctcxo_24m { + bootph-pre-ram; +}; + +&syscon_mpmu { + bootph-pre-ram; +}; + +&pll { + bootph-pre-ram; +}; + +&syscon_apmu { + bootph-pre-ram; +}; + +&syscon_apbc { + bootph-pre-ram; +}; -- cgit v1.3.1