From b8b88e6aff3ea7346a39bfbb27124b275ce56666 Mon Sep 17 00:00:00 2001 From: David Rivshin Date: Mon, 18 Feb 2019 18:04:29 -0500 Subject: spi: omap3: fix set_wordlen() reading from incorrect address for CHCONF _omap3_spi_set_wordlen() indexed the regs->channel[] array with the old wordlen (instead of the chipselect number) when reading the current CHCONF register value. This meant it read from the wrong memory location, modified that value, and then wrote it back to the correct CHCONF register. The end result is that most slave configuration settings would be lost, such as clock divisor, clock/chipselect polarities, etc. Fixes: 77b8d04854f4 ("spi: omap3: Convert to driver model") Signed-off-by: David Rivshin --- drivers/spi/omap3_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index c7fcf050a58..ff4c700645c 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -415,7 +415,7 @@ static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv) unsigned int confr; /* McSPI individual channel configuration */ - confr = readl(&priv->regs->channel[priv->wordlen].chconf); + confr = readl(&priv->regs->channel[priv->cs].chconf); /* wordlength */ confr &= ~OMAP3_MCSPI_CHCONF_WL_MASK; -- cgit v1.3.1 From 86dc480d73776e6628ea39a5429f160ffdc2ec85 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 19 Feb 2019 01:43:51 +0100 Subject: ARM: cache: Fix incorrect bitwise operation The loop implemented in the code is supposed to check whether the PL310 operation register has any bit from the mask set. Currently, the code checks whether the PL310 operation register has any bit set AND whether the mask is non-zero, which is incorrect. Fix the conditional. Signed-off-by: Marek Vasut Cc: Dalon Westergreen Cc: Dinh Nguyen Cc: Tom Rini Fixes: 93bc21930a1b ("armv7: add PL310 support to u-boot") Reviewed-by: Simon Goldschmidt Reviewed-by: Dinh Nguyen --- arch/arm/lib/cache-pl310.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c index 1296ba6efda..bbaaaa4157a 100644 --- a/arch/arm/lib/cache-pl310.c +++ b/arch/arm/lib/cache-pl310.c @@ -33,7 +33,7 @@ static void pl310_background_op_all_ways(u32 *op_reg) /* Invalidate all ways */ writel(way_mask, op_reg); /* Wait for all ways to be invalidated */ - while (readl(op_reg) && way_mask) + while (readl(op_reg) & way_mask) ; pl310_cache_sync(); } -- cgit v1.3.1 From 0a8573052afcee0b026073ae8625679ed1765556 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 21 Feb 2019 07:48:54 +0100 Subject: .gitignore: Ignore regenerated *.dtbo files *.dtbo are dt overlays files which should be also ignored as *.dtb. Signed-off-by: Michal Simek --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 8d18d6f49bc..3df3139d236 100644 --- a/.gitignore +++ b/.gitignore @@ -10,6 +10,7 @@ *.bin *.cfgout *.dtb +*.dtbo *.dtb.S *.elf *.exe -- cgit v1.3.1 From a319229fdaced1aa74f8d7a0ffa1194f352a5a38 Mon Sep 17 00:00:00 2001 From: Felix Brack Date: Mon, 25 Feb 2019 16:38:23 +0100 Subject: arm: pdu001: Fix order of include files Fix the order of include files according to U-Boot coding style. Signed-off-by: Felix Brack --- board/eets/pdu001/mux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/eets/pdu001/mux.c b/board/eets/pdu001/mux.c index f1d38e9b74d..f0f9e262ebd 100644 --- a/board/eets/pdu001/mux.c +++ b/board/eets/pdu001/mux.c @@ -8,11 +8,11 @@ */ #include +#include #include #include #include #include -#include #include "board.h" static struct module_pin_mux uart0_pin_mux[] = { -- cgit v1.3.1 From 7274b7638a3ed03f64faff185253b2bccf557877 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 25 Feb 2019 19:42:48 +0100 Subject: fs: fat: fix link error when building with DEBUG=1 When compiling with DEBUG=1 an error fs/fat/fat_write.c:831: undefined reference to `__aeabi_ldivmod' occurred. We should use do_div() instead of the modulus operator. filesize and cur_pos cannot be negative. So let's use u64 to avoid warnings. Fixes: cb8af8af5ba0 ("fs: fat: support write with non-zero offset") Signed-off-by: Heinrich Schuchardt --- fs/fat/fat_write.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index 3272412ca9f..852f874e581 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -696,11 +696,11 @@ static int set_contents(fsdata *mydata, dir_entry *dentptr, loff_t pos, __u8 *buffer, loff_t maxsize, loff_t *gotsize) { - loff_t filesize; unsigned int bytesperclust = mydata->clust_size * mydata->sect_size; __u32 curclust = START(dentptr); __u32 endclust = 0, newclust = 0; - loff_t cur_pos, offset, actsize, wsize; + u64 cur_pos, filesize; + loff_t offset, actsize, wsize; *gotsize = 0; filesize = pos + maxsize; @@ -828,7 +828,7 @@ set_contents(fsdata *mydata, dir_entry *dentptr, loff_t pos, __u8 *buffer, curclust = endclust; filesize -= cur_pos; - assert(!(cur_pos % bytesperclust)); + assert(!do_div(cur_pos, bytesperclust)); set_clusters: /* allocate and write */ -- cgit v1.3.1 From 3a29afcbbfd8eb6d58f06b1717807c036971ca58 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 26 Feb 2019 13:09:00 +0100 Subject: doc: binding: rename directory ram to memory-controller Alignment with kernel directory name as it have already bindings for DDR controllers in the directory: Documentation/devicetree/bindings/memory-controller PS: the drivers using RAM u-class should be associated with this binding directory Signed-off-by: Patrick Delaunay --- .../memory-controllers/k3-am654-ddrss.txt | 46 ++++ .../memory-controllers/st,stm32-fmc.txt | 58 ++++ .../memory-controllers/st,stm32mp1-ddr.txt | 299 +++++++++++++++++++++ doc/device-tree-bindings/ram/k3-am654-ddrss.txt | 46 ---- doc/device-tree-bindings/ram/st,stm32-fmc.txt | 58 ---- doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt | 299 --------------------- 6 files changed, 403 insertions(+), 403 deletions(-) create mode 100644 doc/device-tree-bindings/memory-controllers/k3-am654-ddrss.txt create mode 100644 doc/device-tree-bindings/memory-controllers/st,stm32-fmc.txt create mode 100644 doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt delete mode 100644 doc/device-tree-bindings/ram/k3-am654-ddrss.txt delete mode 100644 doc/device-tree-bindings/ram/st,stm32-fmc.txt delete mode 100644 doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt diff --git a/doc/device-tree-bindings/memory-controllers/k3-am654-ddrss.txt b/doc/device-tree-bindings/memory-controllers/k3-am654-ddrss.txt new file mode 100644 index 00000000000..4ed731c5242 --- /dev/null +++ b/doc/device-tree-bindings/memory-controllers/k3-am654-ddrss.txt @@ -0,0 +1,46 @@ +Texas Instruments' K3 AM654 DDRSS +================================= + +K3 based AM654 devices has DDR memory subsystem that comprises +Synopys DDR controller, Synopsis DDR phy and wrapper logic to +integrate these blocks into the device. This DDR subsystem +provides an interface to external SDRAM devices. This DDRSS driver +adds support for the initialization of the external SDRAM devices by +configuring the DDRSS registers and using the buitin PHY +initialization routines. + +DDRSS device node: +================== +Required properties: +-------------------- +- compatible: Shall be: "ti,am654-ddrss" +- reg-names ss - Map the sub system wrapper logic region + ctl - Map the controller region + phy - Map the PHY region +- reg: Contains the register map per reg-names. +- power-domains: Should contain a phandle to a PM domain provider node + and an args specifier containing the DDRSS device id + value. This property is as per the binding, + doc/device-tree-bindings/power/ti,sci-pm-domain.txt +- clocks: Must contain an entry for enabling DDR clock. Should + be defined as per the appropriate clock bindings consumer + usage in doc/device-tree-bindings/clock/ti,sci-clk.txt + + +Optional Properties: +-------------------- +- clock-frequency: Frequency at which DDR pll should be locked. + If not provided, default frequency will be used. + +Example (AM65x): +================ + memory-controller: memory-controller@298e000 { + compatible = "ti,am654-ddrss"; + reg = <0x0298e000 0x200>, + <0x02980000 0x4000>, + <0x02988000 0x2000>; + reg-names = "ss", "ctl", "phy"; + clocks = <&k3_clks 20 0>; + power-domains = <&k3_pds 20>; + u-boot,dm-spl; + }; diff --git a/doc/device-tree-bindings/memory-controllers/st,stm32-fmc.txt b/doc/device-tree-bindings/memory-controllers/st,stm32-fmc.txt new file mode 100644 index 00000000000..99f76d515fb --- /dev/null +++ b/doc/device-tree-bindings/memory-controllers/st,stm32-fmc.txt @@ -0,0 +1,58 @@ +ST, stm32 flexible memory controller Drive +Required properties: +- compatible : "st,stm32-fmc" +- reg : fmc controller base address +- clocks : fmc controller clock +u-boot,dm-pre-reloc: flag to initialize memory before relocation. + +on-board sdram memory attributes: +- st,sdram-control : parameters for sdram configuration, in this order: + number of columns + number of rows + memory width + number of intenal banks in memory + cas latency + read burst enable or disable + read pipe delay + +- st,sdram-timing: timings for sdram, in this order: + tmrd + txsr + tras + trc + trp + trcd + +There is device tree include file at : +include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing +parameters as MACROS. + +Example: + fmc: fmc@A0000000 { + compatible = "st,stm32-fmc"; + reg = <0xA0000000 0x1000>; + clocks = <&rcc 0 64>; + u-boot,dm-pre-reloc; + }; + + &fmc { + pinctrl-0 = <&fmc_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* sdram memory configuration from sdram datasheet */ + bank1: bank@0 { + st,sdram-control = /bits/ 8 ; + st,sdram-timing = /bits/ 8 ; + }; + + /* sdram memory configuration from sdram datasheet */ + bank2: bank@1 { + st,sdram-control = /bits/ 8 ; + st,sdram-timing = /bits/ 8 ; + }; + } diff --git a/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt b/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt new file mode 100644 index 00000000000..3028636c451 --- /dev/null +++ b/doc/device-tree-bindings/memory-controllers/st,stm32mp1-ddr.txt @@ -0,0 +1,299 @@ +ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC) + +-------------------- +Required properties: +-------------------- +- compatible : Should be "st,stm32mp1-ddr" +- reg : controleur (DDRCTRL) and phy (DDRPHYC) base address +- clocks : controller clocks handle +- clock-names : associated controller clock names + the "ddrphyc" clock is used to check the DDR frequency + at phy level according the expected value in "mem-speed" field + +the next attributes are DDR parameters, they are generated by DDR tools +included in STM32 Cube tool + +info attributes: +---------------- +- st,mem-name : name for DDR configuration, simple string for information +- st,mem-speed : DDR expected speed for the setting in MHz +- st,mem-size : DDR mem size in byte + + +controlleur attributes: +----------------------- +- st,ctl-reg : controleur values depending of the DDR type + (DDR3/LPDDR2/LPDDR3) + for STM32MP15x: 25 values are requested in this order + MSTR + MRCTRL0 + MRCTRL1 + DERATEEN + DERATEINT + PWRCTL + PWRTMG + HWLPCTL + RFSHCTL0 + RFSHCTL3 + CRCPARCTL0 + ZQCTL0 + DFITMG0 + DFITMG1 + DFILPCFG0 + DFIUPD0 + DFIUPD1 + DFIUPD2 + DFIPHYMSTR + ODTMAP + DBG0 + DBG1 + DBGCMD + POISONCFG + PCCFG + +- st,ctl-timing : controleur values depending of frequency and timing parameter + of DDR + for STM32MP15x: 12 values are requested in this order + RFSHTMG + DRAMTMG0 + DRAMTMG1 + DRAMTMG2 + DRAMTMG3 + DRAMTMG4 + DRAMTMG5 + DRAMTMG6 + DRAMTMG7 + DRAMTMG8 + DRAMTMG14 + ODTCFG + +- st,ctl-map : controleur values depending of address mapping + for STM32MP15x: 9 values are requested in this order + ADDRMAP1 + ADDRMAP2 + ADDRMAP3 + ADDRMAP4 + ADDRMAP5 + ADDRMAP6 + ADDRMAP9 + ADDRMAP10 + ADDRMAP11 + +- st,ctl-perf : controleur values depending of performance and scheduling + for STM32MP15x: 17 values are requested in this order + SCHED + SCHED1 + PERFHPR1 + PERFLPR1 + PERFWR1 + PCFGR_0 + PCFGW_0 + PCFGQOS0_0 + PCFGQOS1_0 + PCFGWQOS0_0 + PCFGWQOS1_0 + PCFGR_1 + PCFGW_1 + PCFGQOS0_1 + PCFGQOS1_1 + PCFGWQOS0_1 + PCFGWQOS1_1 + +phyc attributes: +---------------- +- st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3) + for STM32MP15x: 10 values are requested in this order + PGCR + ACIOCR + DXCCR + DSGCR + DCR + ODTCR + ZQ0CR1 + DX0GCR + DX1GCR + DX2GCR + DX3GCR + +- st,phy-timing : phy values depending of frequency and timing parameter of DDR + for STM32MP15x: 10 values are requested in this order + PTR0 + PTR1 + PTR2 + DTPR0 + DTPR1 + DTPR2 + MR0 + MR1 + MR2 + MR3 + +- st,phy-cal : phy cal depending of calibration or tuning of DDR + for STM32MP15x: 12 values are requested in this order + DX0DLLCR + DX0DQTR + DX0DQSTR + DX1DLLCR + DX1DQTR + DX1DQSTR + DX2DLLCR + DX2DQTR + DX2DQSTR + DX3DLLCR + DX3DQTR + DX3DQSTR + +Example: + +/ { + soc { + u-boot,dm-spl; + + ddr: ddr@0x5A003000{ + u-boot,dm-spl; + u-boot,dm-pre-reloc; + + compatible = "st,stm32mp1-ddr"; + + reg = <0x5A003000 0x550 + 0x5A004000 0x234>; + + clocks = <&rcc_clk AXIDCG>, + <&rcc_clk DDRC1>, + <&rcc_clk DDRC2>, + <&rcc_clk DDRPHYC>, + <&rcc_clk DDRCAPB>, + <&rcc_clk DDRPHYCAPB>; + + clock-names = "axidcg", + "ddrc1", + "ddrc2", + "ddrphyc", + "ddrcapb", + "ddrphycapb"; + + st,mem-name = "DDR3 2x4Gb 533MHz"; + st,mem-speed = <533>; + st,mem-size = <0x40000000>; + + st,ctl-reg = < + 0x00040401 /*MSTR*/ + 0x00000010 /*MRCTRL0*/ + 0x00000000 /*MRCTRL1*/ + 0x00000000 /*DERATEEN*/ + 0x00800000 /*DERATEINT*/ + 0x00000000 /*PWRCTL*/ + 0x00400010 /*PWRTMG*/ + 0x00000000 /*HWLPCTL*/ + 0x00210000 /*RFSHCTL0*/ + 0x00000000 /*RFSHCTL3*/ + 0x00000000 /*CRCPARCTL0*/ + 0xC2000040 /*ZQCTL0*/ + 0x02050105 /*DFITMG0*/ + 0x00000202 /*DFITMG1*/ + 0x07000000 /*DFILPCFG0*/ + 0xC0400003 /*DFIUPD0*/ + 0x00000000 /*DFIUPD1*/ + 0x00000000 /*DFIUPD2*/ + 0x00000000 /*DFIPHYMSTR*/ + 0x00000001 /*ODTMAP*/ + 0x00000000 /*DBG0*/ + 0x00000000 /*DBG1*/ + 0x00000000 /*DBGCMD*/ + 0x00000000 /*POISONCFG*/ + 0x00000010 /*PCCFG*/ + >; + + st,ctl-timing = < + 0x0080008A /*RFSHTMG*/ + 0x121B2414 /*DRAMTMG0*/ + 0x000D041B /*DRAMTMG1*/ + 0x0607080E /*DRAMTMG2*/ + 0x0050400C /*DRAMTMG3*/ + 0x07040407 /*DRAMTMG4*/ + 0x06060303 /*DRAMTMG5*/ + 0x02020002 /*DRAMTMG6*/ + 0x00000202 /*DRAMTMG7*/ + 0x00001005 /*DRAMTMG8*/ + 0x000D041B /*DRAMTMG1*/4 + 0x06000600 /*ODTCFG*/ + >; + + st,ctl-map = < + 0x00080808 /*ADDRMAP1*/ + 0x00000000 /*ADDRMAP2*/ + 0x00000000 /*ADDRMAP3*/ + 0x00001F1F /*ADDRMAP4*/ + 0x07070707 /*ADDRMAP5*/ + 0x0F070707 /*ADDRMAP6*/ + 0x00000000 /*ADDRMAP9*/ + 0x00000000 /*ADDRMAP10*/ + 0x00000000 /*ADDRMAP11*/ + >; + + st,ctl-perf = < + 0x00001201 /*SCHED*/ + 0x00001201 /*SCHED*/1 + 0x01000001 /*PERFHPR1*/ + 0x08000200 /*PERFLPR1*/ + 0x08000400 /*PERFWR1*/ + 0x00010000 /*PCFGR_0*/ + 0x00000000 /*PCFGW_0*/ + 0x02100B03 /*PCFGQOS0_0*/ + 0x00800100 /*PCFGQOS1_0*/ + 0x01100B03 /*PCFGWQOS0_0*/ + 0x01000200 /*PCFGWQOS1_0*/ + 0x00010000 /*PCFGR_1*/ + 0x00000000 /*PCFGW_1*/ + 0x02100B03 /*PCFGQOS0_1*/ + 0x00800000 /*PCFGQOS1_1*/ + 0x01100B03 /*PCFGWQOS0_1*/ + 0x01000200 /*PCFGWQOS1_1*/ + >; + + st,phy-reg = < + 0x01442E02 /*PGCR*/ + 0x10400812 /*ACIOCR*/ + 0x00000C40 /*DXCCR*/ + 0xF200001F /*DSGCR*/ + 0x0000000B /*DCR*/ + 0x00010000 /*ODTCR*/ + 0x0000007B /*ZQ0CR1*/ + 0x0000CE81 /*DX0GCR*/ + 0x0000CE81 /*DX1GCR*/ + 0x0000CE81 /*DX2GCR*/ + 0x0000CE81 /*DX3GCR*/ + >; + + st,phy-timing = < + 0x0022A41B /*PTR0*/ + 0x047C0740 /*PTR1*/ + 0x042D9C80 /*PTR2*/ + 0x369477D0 /*DTPR0*/ + 0x098A00D8 /*DTPR1*/ + 0x10023600 /*DTPR2*/ + 0x00000830 /*MR0*/ + 0x00000000 /*MR1*/ + 0x00000208 /*MR2*/ + 0x00000000 /*MR3*/ + >; + + st,phy-cal = < + 0x40000000 /*DX0DLLCR*/ + 0xFFFFFFFF /*DX0DQTR*/ + 0x3DB02000 /*DX0DQSTR*/ + 0x40000000 /*DX1DLLCR*/ + 0xFFFFFFFF /*DX1DQTR*/ + 0x3DB02000 /*DX1DQSTR*/ + 0x40000000 /*DX2DLLCR*/ + 0xFFFFFFFF /*DX2DQTR*/ + 0x3DB02000 /*DX2DQSTR*/ + 0x40000000 /*DX3DLLCR*/ + 0xFFFFFFFF /*DX3DQTR*/ + 0x3DB02000 /*DX3DQSTR*/ + >; + + status = "okay"; + }; + }; +}; diff --git a/doc/device-tree-bindings/ram/k3-am654-ddrss.txt b/doc/device-tree-bindings/ram/k3-am654-ddrss.txt deleted file mode 100644 index 4ed731c5242..00000000000 --- a/doc/device-tree-bindings/ram/k3-am654-ddrss.txt +++ /dev/null @@ -1,46 +0,0 @@ -Texas Instruments' K3 AM654 DDRSS -================================= - -K3 based AM654 devices has DDR memory subsystem that comprises -Synopys DDR controller, Synopsis DDR phy and wrapper logic to -integrate these blocks into the device. This DDR subsystem -provides an interface to external SDRAM devices. This DDRSS driver -adds support for the initialization of the external SDRAM devices by -configuring the DDRSS registers and using the buitin PHY -initialization routines. - -DDRSS device node: -================== -Required properties: --------------------- -- compatible: Shall be: "ti,am654-ddrss" -- reg-names ss - Map the sub system wrapper logic region - ctl - Map the controller region - phy - Map the PHY region -- reg: Contains the register map per reg-names. -- power-domains: Should contain a phandle to a PM domain provider node - and an args specifier containing the DDRSS device id - value. This property is as per the binding, - doc/device-tree-bindings/power/ti,sci-pm-domain.txt -- clocks: Must contain an entry for enabling DDR clock. Should - be defined as per the appropriate clock bindings consumer - usage in doc/device-tree-bindings/clock/ti,sci-clk.txt - - -Optional Properties: --------------------- -- clock-frequency: Frequency at which DDR pll should be locked. - If not provided, default frequency will be used. - -Example (AM65x): -================ - memory-controller: memory-controller@298e000 { - compatible = "ti,am654-ddrss"; - reg = <0x0298e000 0x200>, - <0x02980000 0x4000>, - <0x02988000 0x2000>; - reg-names = "ss", "ctl", "phy"; - clocks = <&k3_clks 20 0>; - power-domains = <&k3_pds 20>; - u-boot,dm-spl; - }; diff --git a/doc/device-tree-bindings/ram/st,stm32-fmc.txt b/doc/device-tree-bindings/ram/st,stm32-fmc.txt deleted file mode 100644 index 99f76d515fb..00000000000 --- a/doc/device-tree-bindings/ram/st,stm32-fmc.txt +++ /dev/null @@ -1,58 +0,0 @@ -ST, stm32 flexible memory controller Drive -Required properties: -- compatible : "st,stm32-fmc" -- reg : fmc controller base address -- clocks : fmc controller clock -u-boot,dm-pre-reloc: flag to initialize memory before relocation. - -on-board sdram memory attributes: -- st,sdram-control : parameters for sdram configuration, in this order: - number of columns - number of rows - memory width - number of intenal banks in memory - cas latency - read burst enable or disable - read pipe delay - -- st,sdram-timing: timings for sdram, in this order: - tmrd - txsr - tras - trc - trp - trcd - -There is device tree include file at : -include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing -parameters as MACROS. - -Example: - fmc: fmc@A0000000 { - compatible = "st,stm32-fmc"; - reg = <0xA0000000 0x1000>; - clocks = <&rcc 0 64>; - u-boot,dm-pre-reloc; - }; - - &fmc { - pinctrl-0 = <&fmc_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* sdram memory configuration from sdram datasheet */ - bank1: bank@0 { - st,sdram-control = /bits/ 8 ; - st,sdram-timing = /bits/ 8 ; - }; - - /* sdram memory configuration from sdram datasheet */ - bank2: bank@1 { - st,sdram-control = /bits/ 8 ; - st,sdram-timing = /bits/ 8 ; - }; - } diff --git a/doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt b/doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt deleted file mode 100644 index 3028636c451..00000000000 --- a/doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt +++ /dev/null @@ -1,299 +0,0 @@ -ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC) - --------------------- -Required properties: --------------------- -- compatible : Should be "st,stm32mp1-ddr" -- reg : controleur (DDRCTRL) and phy (DDRPHYC) base address -- clocks : controller clocks handle -- clock-names : associated controller clock names - the "ddrphyc" clock is used to check the DDR frequency - at phy level according the expected value in "mem-speed" field - -the next attributes are DDR parameters, they are generated by DDR tools -included in STM32 Cube tool - -info attributes: ----------------- -- st,mem-name : name for DDR configuration, simple string for information -- st,mem-speed : DDR expected speed for the setting in MHz -- st,mem-size : DDR mem size in byte - - -controlleur attributes: ------------------------ -- st,ctl-reg : controleur values depending of the DDR type - (DDR3/LPDDR2/LPDDR3) - for STM32MP15x: 25 values are requested in this order - MSTR - MRCTRL0 - MRCTRL1 - DERATEEN - DERATEINT - PWRCTL - PWRTMG - HWLPCTL - RFSHCTL0 - RFSHCTL3 - CRCPARCTL0 - ZQCTL0 - DFITMG0 - DFITMG1 - DFILPCFG0 - DFIUPD0 - DFIUPD1 - DFIUPD2 - DFIPHYMSTR - ODTMAP - DBG0 - DBG1 - DBGCMD - POISONCFG - PCCFG - -- st,ctl-timing : controleur values depending of frequency and timing parameter - of DDR - for STM32MP15x: 12 values are requested in this order - RFSHTMG - DRAMTMG0 - DRAMTMG1 - DRAMTMG2 - DRAMTMG3 - DRAMTMG4 - DRAMTMG5 - DRAMTMG6 - DRAMTMG7 - DRAMTMG8 - DRAMTMG14 - ODTCFG - -- st,ctl-map : controleur values depending of address mapping - for STM32MP15x: 9 values are requested in this order - ADDRMAP1 - ADDRMAP2 - ADDRMAP3 - ADDRMAP4 - ADDRMAP5 - ADDRMAP6 - ADDRMAP9 - ADDRMAP10 - ADDRMAP11 - -- st,ctl-perf : controleur values depending of performance and scheduling - for STM32MP15x: 17 values are requested in this order - SCHED - SCHED1 - PERFHPR1 - PERFLPR1 - PERFWR1 - PCFGR_0 - PCFGW_0 - PCFGQOS0_0 - PCFGQOS1_0 - PCFGWQOS0_0 - PCFGWQOS1_0 - PCFGR_1 - PCFGW_1 - PCFGQOS0_1 - PCFGQOS1_1 - PCFGWQOS0_1 - PCFGWQOS1_1 - -phyc attributes: ----------------- -- st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3) - for STM32MP15x: 10 values are requested in this order - PGCR - ACIOCR - DXCCR - DSGCR - DCR - ODTCR - ZQ0CR1 - DX0GCR - DX1GCR - DX2GCR - DX3GCR - -- st,phy-timing : phy values depending of frequency and timing parameter of DDR - for STM32MP15x: 10 values are requested in this order - PTR0 - PTR1 - PTR2 - DTPR0 - DTPR1 - DTPR2 - MR0 - MR1 - MR2 - MR3 - -- st,phy-cal : phy cal depending of calibration or tuning of DDR - for STM32MP15x: 12 values are requested in this order - DX0DLLCR - DX0DQTR - DX0DQSTR - DX1DLLCR - DX1DQTR - DX1DQSTR - DX2DLLCR - DX2DQTR - DX2DQSTR - DX3DLLCR - DX3DQTR - DX3DQSTR - -Example: - -/ { - soc { - u-boot,dm-spl; - - ddr: ddr@0x5A003000{ - u-boot,dm-spl; - u-boot,dm-pre-reloc; - - compatible = "st,stm32mp1-ddr"; - - reg = <0x5A003000 0x550 - 0x5A004000 0x234>; - - clocks = <&rcc_clk AXIDCG>, - <&rcc_clk DDRC1>, - <&rcc_clk DDRC2>, - <&rcc_clk DDRPHYC>, - <&rcc_clk DDRCAPB>, - <&rcc_clk DDRPHYCAPB>; - - clock-names = "axidcg", - "ddrc1", - "ddrc2", - "ddrphyc", - "ddrcapb", - "ddrphycapb"; - - st,mem-name = "DDR3 2x4Gb 533MHz"; - st,mem-speed = <533>; - st,mem-size = <0x40000000>; - - st,ctl-reg = < - 0x00040401 /*MSTR*/ - 0x00000010 /*MRCTRL0*/ - 0x00000000 /*MRCTRL1*/ - 0x00000000 /*DERATEEN*/ - 0x00800000 /*DERATEINT*/ - 0x00000000 /*PWRCTL*/ - 0x00400010 /*PWRTMG*/ - 0x00000000 /*HWLPCTL*/ - 0x00210000 /*RFSHCTL0*/ - 0x00000000 /*RFSHCTL3*/ - 0x00000000 /*CRCPARCTL0*/ - 0xC2000040 /*ZQCTL0*/ - 0x02050105 /*DFITMG0*/ - 0x00000202 /*DFITMG1*/ - 0x07000000 /*DFILPCFG0*/ - 0xC0400003 /*DFIUPD0*/ - 0x00000000 /*DFIUPD1*/ - 0x00000000 /*DFIUPD2*/ - 0x00000000 /*DFIPHYMSTR*/ - 0x00000001 /*ODTMAP*/ - 0x00000000 /*DBG0*/ - 0x00000000 /*DBG1*/ - 0x00000000 /*DBGCMD*/ - 0x00000000 /*POISONCFG*/ - 0x00000010 /*PCCFG*/ - >; - - st,ctl-timing = < - 0x0080008A /*RFSHTMG*/ - 0x121B2414 /*DRAMTMG0*/ - 0x000D041B /*DRAMTMG1*/ - 0x0607080E /*DRAMTMG2*/ - 0x0050400C /*DRAMTMG3*/ - 0x07040407 /*DRAMTMG4*/ - 0x06060303 /*DRAMTMG5*/ - 0x02020002 /*DRAMTMG6*/ - 0x00000202 /*DRAMTMG7*/ - 0x00001005 /*DRAMTMG8*/ - 0x000D041B /*DRAMTMG1*/4 - 0x06000600 /*ODTCFG*/ - >; - - st,ctl-map = < - 0x00080808 /*ADDRMAP1*/ - 0x00000000 /*ADDRMAP2*/ - 0x00000000 /*ADDRMAP3*/ - 0x00001F1F /*ADDRMAP4*/ - 0x07070707 /*ADDRMAP5*/ - 0x0F070707 /*ADDRMAP6*/ - 0x00000000 /*ADDRMAP9*/ - 0x00000000 /*ADDRMAP10*/ - 0x00000000 /*ADDRMAP11*/ - >; - - st,ctl-perf = < - 0x00001201 /*SCHED*/ - 0x00001201 /*SCHED*/1 - 0x01000001 /*PERFHPR1*/ - 0x08000200 /*PERFLPR1*/ - 0x08000400 /*PERFWR1*/ - 0x00010000 /*PCFGR_0*/ - 0x00000000 /*PCFGW_0*/ - 0x02100B03 /*PCFGQOS0_0*/ - 0x00800100 /*PCFGQOS1_0*/ - 0x01100B03 /*PCFGWQOS0_0*/ - 0x01000200 /*PCFGWQOS1_0*/ - 0x00010000 /*PCFGR_1*/ - 0x00000000 /*PCFGW_1*/ - 0x02100B03 /*PCFGQOS0_1*/ - 0x00800000 /*PCFGQOS1_1*/ - 0x01100B03 /*PCFGWQOS0_1*/ - 0x01000200 /*PCFGWQOS1_1*/ - >; - - st,phy-reg = < - 0x01442E02 /*PGCR*/ - 0x10400812 /*ACIOCR*/ - 0x00000C40 /*DXCCR*/ - 0xF200001F /*DSGCR*/ - 0x0000000B /*DCR*/ - 0x00010000 /*ODTCR*/ - 0x0000007B /*ZQ0CR1*/ - 0x0000CE81 /*DX0GCR*/ - 0x0000CE81 /*DX1GCR*/ - 0x0000CE81 /*DX2GCR*/ - 0x0000CE81 /*DX3GCR*/ - >; - - st,phy-timing = < - 0x0022A41B /*PTR0*/ - 0x047C0740 /*PTR1*/ - 0x042D9C80 /*PTR2*/ - 0x369477D0 /*DTPR0*/ - 0x098A00D8 /*DTPR1*/ - 0x10023600 /*DTPR2*/ - 0x00000830 /*MR0*/ - 0x00000000 /*MR1*/ - 0x00000208 /*MR2*/ - 0x00000000 /*MR3*/ - >; - - st,phy-cal = < - 0x40000000 /*DX0DLLCR*/ - 0xFFFFFFFF /*DX0DQTR*/ - 0x3DB02000 /*DX0DQSTR*/ - 0x40000000 /*DX1DLLCR*/ - 0xFFFFFFFF /*DX1DQTR*/ - 0x3DB02000 /*DX1DQSTR*/ - 0x40000000 /*DX2DLLCR*/ - 0xFFFFFFFF /*DX2DQTR*/ - 0x3DB02000 /*DX2DQSTR*/ - 0x40000000 /*DX3DLLCR*/ - 0xFFFFFFFF /*DX3DQTR*/ - 0x3DB02000 /*DX3DQSTR*/ - >; - - status = "okay"; - }; - }; -}; -- cgit v1.3.1 From 2737dfe096b6c34654734a5a4dc5f4b4962c5617 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 26 Feb 2019 12:20:25 -0700 Subject: kbuild: make arch-dtbs target PHONY Without this, the arch-dtbs target only gets evaluated when building U-Boot the first time, not when re-building (incrementally building) U-Boot. Thus incremental builds ignore changes to DTB files. Signed-off-by: Stephen Warren Reviewed-by: Masahiro Yamada --- dts/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/dts/Makefile b/dts/Makefile index a7a604303cc..4970223b3d2 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -40,6 +40,7 @@ endif echo >&2; \ /bin/false) +PHONY += arch-dtbs arch-dtbs: $(Q)$(MAKE) $(build)=$(ARCH_PATH) dtbs -- cgit v1.3.1 From 8422ad51652f8f33acd3f03f24ec2aea73083eb7 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 26 Feb 2019 12:20:26 -0700 Subject: kbuild: fix DTB .cmd source variable *.dts are processed using a custom command, then the C pre-processor is run on them, then they are compiled using dtc. Thus, the dependency files generated by both cpp and dtc reference a temporary file name rather than the actual source file. While this information isn't used for any purpose by the build system, and hence this causes no functional issue, it does cause the dependency files to contain invalid and confusing data, which is unhelpful while debugging build problems. Fix this using sed. Signed-off-by: Stephen Warren Reviewed-by: Masahiro Yamada --- scripts/Makefile.lib | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 704d644f6fa..ec5c41ec561 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -301,7 +301,8 @@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \ $(DTC) -O dtb -o $@ -b 0 \ -i $(dir $<) $(DTC_FLAGS) \ -d $(depfile).dtc.tmp $(dtc-tmp) ; \ - cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) + cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) ; \ + sed -i "s:$(pre-tmp):$(<):" $(depfile) $(obj)/%.dtb: $(src)/%.dts FORCE $(call if_changed_dep,dtc) -- cgit v1.3.1 From 438dcabb75d6b9b0e7f887befb753d1863f14deb Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Tue, 26 Feb 2019 22:27:52 +0100 Subject: spl: add debug print for early malloc usage To find out how big the early malloc heap must be in SPL, add a debug print statement that dumps its usage before switching to relocated heap in spl_relocate_stack_gd() via CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN. Signed-off-by: Simon Goldschmidt --- common/spl/spl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/common/spl/spl.c b/common/spl/spl.c index 2e2af1b28ee..88d4b8a9bf1 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -728,6 +728,8 @@ ulong spl_relocate_stack_gd(void) #if defined(CONFIG_SPL_SYS_MALLOC_SIMPLE) && CONFIG_VAL(SYS_MALLOC_F_LEN) if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) { + debug("SPL malloc() before relocation used 0x%lx bytes (%ld KB)\n", + gd->malloc_ptr, gd->malloc_ptr / 1024); ptr -= CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN; gd->malloc_base = ptr; gd->malloc_limit = CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN; -- cgit v1.3.1