From 6cc155fb43907fbe87713d4d4b64d7d9672b4f9f Mon Sep 17 00:00:00 2001 From: Trapti Damodar Balgi Date: Tue, 9 Jun 2026 09:48:15 +0200 Subject: arm64: zynqmp-dlc21-revA: Update GPIO line names mapping Update the gpio-line-names property to reflect the latest GPIO mapping, including PMOD and VCCO labels. Signed-off-by: Trapti Damodar Balgi Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/c204b6474c821a0b46b94fa87ee69a6693fd8686.1780991287.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-dlc21-revA.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts index d48b6f3a8ec..25cd0a09c94 100644 --- a/arch/arm/dts/zynqmp-dlc21-revA.dts +++ b/arch/arm/dts/zynqmp-dlc21-revA.dts @@ -119,10 +119,10 @@ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ - "", "", "", "", "", /* 80 - 84 */ - "", "", "", "", "", /* 85 - 89 */ - "", "", "", "", "", /* 90 - 94 */ - "", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ + "", "", "", "", "PMOD_0", /* 80 - 84 */ + "PMOD_1", "PMOD_2", "PMOD_3", "PMOD_4", "PMOD_5", /* 85 -89 */ + "PMOD_6", "PMOD_7", "", "", "", /* 90 - 94 */ + "", "", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ -- cgit v1.3.1 From 336ac1481725741adeee40c9754b645e09aaffed Mon Sep 17 00:00:00 2001 From: Trapti Damodar Balgi Date: Tue, 9 Jun 2026 09:48:16 +0200 Subject: arm64: zynqmp-dlc21-revA: add mac nvmem cell for gem0 Enable nvmem support for MAC address retrieval from EEPROM for ethernet@ff0b0000. Add nvmem-cells and nvmem-cell-names to the GEM0 node, and define a mac-address@20 cell under the EEPROM node on I2C0. This allows U-Boot to read the MAC address from EEPROM at offset 0x20. Signed-off-by: Trapti Damodar Balgi Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/49490b1d510f27f47e71e86c7d1f29478111ef81.1780991287.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-dlc21-revA.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts index 25cd0a09c94..83c39ce1a26 100644 --- a/arch/arm/dts/zynqmp-dlc21-revA.dts +++ b/arch/arm/dts/zynqmp-dlc21-revA.dts @@ -90,6 +90,9 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ + nvmem-cells = <ð_mac>; + nvmem-cell-names = "mac-address"; + mdio: mdio { #address-cells = <1>; #size-cells = <0>; @@ -153,6 +156,12 @@ eeprom: eeprom@50 { /* u46 */ compatible = "atmel,24c32"; reg = <0x50>; + #address-cells = <1>; + #size-cells = <1>; + + eth_mac: mac-address@20 { + reg = <0x20 0x6>; + }; }; /* u138 - TUSB320IRWBR - for USB-C */ }; -- cgit v1.3.1 From fc7640cbde149a22ad05bcf2bf5407b1f6a5c23f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 9 Jun 2026 09:48:17 +0200 Subject: arm64: zynqmp: Drop incorrect #phy-cells from ethernet-phy nodes The #phy-cells property is meant for generic PHY providers (Documentation/devicetree/bindings/phy/phy-bindings.txt) and is not a valid property for ethernet-phy nodes. Its presence triggers a dt-validate warning: ethernet-phy@x (ethernet-phy-id001c.c816): Unevaluated properties are not allowed ('#phy-cells' was unexpected) Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/d50e4ed12227609f3f827acde885c1d37782b8a9.1780991287.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sc-revB.dts | 1 - arch/arm/dts/zynqmp-sc-revC.dts | 1 - arch/arm/dts/zynqmp-sck-kd-g-revA.dtso | 1 - arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 2 -- arch/arm/dts/zynqmp-sck-kr-g-revB.dtso | 2 -- arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 1 - arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 1 - arch/arm/dts/zynqmp-zcu102-revA.dts | 1 - arch/arm/dts/zynqmp-zcu102-revB.dts | 1 - arch/arm/dts/zynqmp-zcu104-revA.dts | 1 - arch/arm/dts/zynqmp-zcu104-revC.dts | 1 - arch/arm/dts/zynqmp-zcu106-revA.dts | 1 - arch/arm/dts/zynqmp-zcu111-revA.dts | 1 - arch/arm/dts/zynqmp-zcu208-revA.dts | 1 - arch/arm/dts/zynqmp-zcu216-revA.dts | 1 - arch/arm/dts/zynqmp-zcu670-revA.dts | 1 - arch/arm/dts/zynqmp-zcu670-revB.dts | 1 - 17 files changed, 19 deletions(-) diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts index 6181072c1da..4367136cae8 100644 --- a/arch/arm/dts/zynqmp-sc-revB.dts +++ b/arch/arm/dts/zynqmp-sc-revB.dts @@ -136,7 +136,6 @@ #size-cells = <0>; phy0: ethernet-phy@1 { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = ; diff --git a/arch/arm/dts/zynqmp-sc-revC.dts b/arch/arm/dts/zynqmp-sc-revC.dts index 530a4a5f080..b9b192f0986 100644 --- a/arch/arm/dts/zynqmp-sc-revC.dts +++ b/arch/arm/dts/zynqmp-sc-revC.dts @@ -23,7 +23,6 @@ #size-cells = <0>; phy0: ethernet-phy@1 { /* ADI1300 */ - #phy-cells = <1>; compatible = "ethernet-phy-id0283.bc30"; reg = <1>; adi,rx-internal-delay-ps = <2400>; diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index 8342479b108..021bf8ac26e 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -148,7 +148,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@8 { /* Adin u31 */ - #phy-cells = <1>; compatible = "ethernet-phy-id0283.bc30"; reg = <8>; adi,rx-internal-delay-ps = <2000>; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index db042ffb4f3..048aeb1e765 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -265,7 +265,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@4 { /* u81 */ - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <4>; ti,rx-internal-delay = ; @@ -277,7 +276,6 @@ reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; }; phy1: ethernet-phy@8 { /* u36 */ - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <8>; ti,rx-internal-delay = ; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index e3567d0abfe..2eef6ba7df7 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -266,7 +266,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@4 { /* u81 */ - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <4>; ti,rx-internal-delay = ; @@ -278,7 +277,6 @@ reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; }; phy1: ethernet-phy@8 { /* u36 */ - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <8>; ti,rx-internal-delay = ; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index f93c7460a55..ea947cd2dc0 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -209,7 +209,6 @@ #size-cells = <0>; phy0: ethernet-phy@1 { - #phy-cells = <1>; reg = <1>; compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = ; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index 70de6933600..ea7b9253468 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -200,7 +200,6 @@ #size-cells = <0>; phy0: ethernet-phy@1 { - #phy-cells = <1>; reg = <1>; compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = ; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 6b1aea95e65..3d71742fcbe 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -217,7 +217,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@21 { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <21>; ti,rx-internal-delay = <0x8>; diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index 3c28130909b..bad59d7b1d2 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -19,7 +19,6 @@ phy-handle = <&phyc>; mdio: mdio { phyc: ethernet-phy@c { - #phy-cells = <0x1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 0bfeed4293c..b4e62bf6bb6 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -126,7 +126,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index a7387f4a0e6..f7a91402a09 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -131,7 +131,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 7b1097579fc..5eb5f77220d 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -217,7 +217,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; reg = <0xc>; compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = <0x8>; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index ba1b6339100..72d331a740f 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -189,7 +189,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 888f711aad9..70b1e81e304 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -176,7 +176,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index ccdbf8967aa..bc0ca24ff05 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -183,7 +183,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts b/arch/arm/dts/zynqmp-zcu670-revA.dts index 058d6b2e648..1215babe214 100644 --- a/arch/arm/dts/zynqmp-zcu670-revA.dts +++ b/arch/arm/dts/zynqmp-zcu670-revA.dts @@ -185,7 +185,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts b/arch/arm/dts/zynqmp-zcu670-revB.dts index 010d412b202..e91f280e457 100644 --- a/arch/arm/dts/zynqmp-zcu670-revB.dts +++ b/arch/arm/dts/zynqmp-zcu670-revB.dts @@ -185,7 +185,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; -- cgit v1.3.1 From d110d5886762616c8d9c99ad24e2e913f97765e5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 9 Jun 2026 09:48:18 +0200 Subject: arm64: zynqmp: Use fixed-partitions for MTD Describe flash and NAND MTD partitions using the fixed-partitions compatible under a dedicated partitions subnode. U-Boot only creates slave MTD devices from this binding in add_mtd_partitions_of(), so mtd list can show named partitions. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/a9e72b2c62e1b2e5c485302a861e5bae55ec2b83.1780991287.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sc-revB.dts | 170 +++++++++++---------- .../dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts | 38 ++--- arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts | 14 +- arch/arm/dts/zynqmp-vpk120-revA.dts | 14 +- arch/arm/dts/zynqmp-zc1232-revA.dts | 40 ++--- arch/arm/dts/zynqmp-zc1254-revA.dts | 38 ++--- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 38 ++--- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 136 +++++++++-------- arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 109 ++++++------- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 38 ++--- arch/arm/dts/zynqmp-zcu102-revA.dts | 38 ++--- arch/arm/dts/zynqmp-zcu104-revA.dts | 38 ++--- arch/arm/dts/zynqmp-zcu104-revC.dts | 38 ++--- arch/arm/dts/zynqmp-zcu106-revA.dts | 38 ++--- arch/arm/dts/zynqmp-zcu111-revA.dts | 38 ++--- arch/arm/dts/zynqmp-zcu1275-revA.dts | 38 ++--- arch/arm/dts/zynqmp-zcu1275-revB.dts | 38 ++--- 17 files changed, 491 insertions(+), 410 deletions(-) diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts index 4367136cae8..afaecfa5a27 100644 --- a/arch/arm/dts/zynqmp-sc-revB.dts +++ b/arch/arm/dts/zynqmp-sc-revB.dts @@ -193,93 +193,97 @@ /* QSPI should also have PINCTRL setup */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ - partition@0 { - label = "Image Selector"; - reg = <0x0 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@80000 { - label = "Image Selector Golden"; - reg = <0x80000 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@100000 { - label = "Persistent Register"; - reg = <0x100000 0x20000>; /* 128KB */ - }; - partition@120000 { - label = "Persistent Register Backup"; - reg = <0x120000 0x20000>; /* 128KB */ - }; - partition@140000 { - label = "Open_1"; - reg = <0x140000 0xc0000>; /* 768KB */ - }; - partition@200000 { - label = "Image A (FSBL, PMU, ATF, U-Boot)"; - reg = <0x200000 0xd00000>; /* 13MB */ - }; - partition@f00000 { - label = "ImgSel Image A Catch"; - reg = <0xf00000 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@f80000 { - label = "Image B (FSBL, PMU, ATF, U-Boot)"; - reg = <0xf80000 0xd00000>; /* 13MB */ - }; - partition@1c80000 { - label = "ImgSel Image B Catch"; - reg = <0x1c80000 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@1d00000 { - label = "Open_2"; - reg = <0x1d00000 0x100000>; /* 1MB */ - }; - partition@1e00000 { - label = "Recovery Image"; - reg = <0x1e00000 0x200000>; /* 2MB */ - read-only; - lock; - }; - partition@2000000 { - label = "Recovery Image Backup"; - reg = <0x2000000 0x200000>; /* 2MB */ - read-only; - lock; - }; - partition@2200000 { - label = "U-Boot storage variables"; - reg = <0x2200000 0x20000>; /* 128KB */ - }; - partition@2220000 { - label = "U-Boot storage variables backup"; - reg = <0x2220000 0x20000>; /* 128KB */ - }; - partition@2240000 { - label = "SHA256"; - reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ - read-only; - lock; - }; - partition@2280000 { - label = "Secure OS Storage"; - reg = <0x2280000 0x20000>; /* 128KB */ - }; - partition@22a0000 { - label = "User"; - reg = <0x22a0000 0x1d60000>; /* 29.375 MB */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Image Selector"; + reg = <0x0 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@80000 { + label = "Image Selector Golden"; + reg = <0x80000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@100000 { + label = "Persistent Register"; + reg = <0x100000 0x20000>; /* 128KB */ + }; + partition@120000 { + label = "Persistent Register Backup"; + reg = <0x120000 0x20000>; /* 128KB */ + }; + partition@140000 { + label = "Open_1"; + reg = <0x140000 0xc0000>; /* 768KB */ + }; + partition@200000 { + label = "Image A (FSBL, PMU, ATF, U-Boot)"; + reg = <0x200000 0xd00000>; /* 13MB */ + }; + partition@f00000 { + label = "ImgSel Image A Catch"; + reg = <0xf00000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@f80000 { + label = "Image B (FSBL, PMU, ATF, U-Boot)"; + reg = <0xf80000 0xd00000>; /* 13MB */ + }; + partition@1c80000 { + label = "ImgSel Image B Catch"; + reg = <0x1c80000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@1d00000 { + label = "Open_2"; + reg = <0x1d00000 0x100000>; /* 1MB */ + }; + partition@1e00000 { + label = "Recovery Image"; + reg = <0x1e00000 0x200000>; /* 2MB */ + read-only; + lock; + }; + partition@2000000 { + label = "Recovery Image Backup"; + reg = <0x2000000 0x200000>; /* 2MB */ + read-only; + lock; + }; + partition@2200000 { + label = "U-Boot storage variables"; + reg = <0x2200000 0x20000>; /* 128KB */ + }; + partition@2220000 { + label = "U-Boot storage variables backup"; + reg = <0x2220000 0x20000>; /* 128KB */ + }; + partition@2240000 { + label = "SHA256"; + reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ + read-only; + lock; + }; + partition@2280000 { + label = "Secure OS Storage"; + reg = <0x2280000 0x20000>; /* 128KB */ + }; + partition@22a0000 { + label = "User"; + reg = <0x22a0000 0x1d60000>; /* 29.375 MB */ + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts index 2037686b9b4..1dc0414b33d 100644 --- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts +++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts @@ -63,23 +63,27 @@ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <166000000>; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "qspi-boot-bin"; - reg = <0x00000 0x60000>; - }; - partition@60000 { - label = "qspi-u-boot-itb"; - reg = <0x60000 0x100000>; - }; - partition@160000 { - label = "qspi-u-boot-env"; - reg = <0x160000 0x20000>; - }; - partition@200000 { - label = "qspi-rootfs"; - reg = <0x200000 0x1e00000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "qspi-boot-bin"; + reg = <0x00000 0x60000>; + }; + partition@60000 { + label = "qspi-u-boot-itb"; + reg = <0x60000 0x100000>; + }; + partition@160000 { + label = "qspi-u-boot-env"; + reg = <0x160000 0x20000>; + }; + partition@200000 { + label = "qspi-rootfs"; + reg = <0x200000 0x1e00000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts index e9c6d249a8d..94167770ed6 100644 --- a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts +++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts @@ -88,15 +88,19 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; /* maybe 4 here */ spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; - partition@0 { /* for testing purpose */ - label = "qspi"; - reg = <0 0x4000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi"; + reg = <0 0x4000000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts index bd1e2557187..3e461d9c4d0 100644 --- a/arch/arm/dts/zynqmp-vpk120-revA.dts +++ b/arch/arm/dts/zynqmp-vpk120-revA.dts @@ -88,15 +88,19 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; - partition@0 { /* for testing purpose */ - label = "qspi"; - reg = <0 0x4000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi"; + reg = <0 0x4000000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts index 9dcb9095371..34e5b6edab1 100644 --- a/arch/arm/dts/zynqmp-zc1232-revA.dts +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -40,28 +40,32 @@ &qspi { status = "okay"; flash@0 { - compatible = "m25p80", "jedec,spi-nor"; /* 32MB FIXME */ - #address-cells = <1>; - #size-cells = <1>; + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts index cf3e9583204..827143377b9 100644 --- a/arch/arm/dts/zynqmp-zc1254-revA.dts +++ b/arch/arm/dts/zynqmp-zc1254-revA.dts @@ -42,27 +42,31 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 32f317f3df4..33efdbf0e25 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -357,28 +357,32 @@ num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index e3d5cf972e8..13c304520a6 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -138,8 +138,6 @@ nand@0 { reg = <0x0>; - #address-cells = <0x2>; - #size-cells = <0x1>; nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-0"; @@ -147,35 +145,39 @@ nand-ecc-strength = <24>; nand-on-flash-bbt; - partition@0 { /* for testing purpose */ - label = "nand-fsbl-uboot"; - reg = <0x0 0x0 0x400000>; - }; - partition@1 { /* for testing purpose */ - label = "nand-linux"; - reg = <0x0 0x400000 0x1400000>; - }; - partition@2 { /* for testing purpose */ - label = "nand-device-tree"; - reg = <0x0 0x1800000 0x400000>; - }; - partition@3 { /* for testing purpose */ - label = "nand-rootfs"; - reg = <0x0 0x1c00000 0x1400000>; - }; - partition@4 { /* for testing purpose */ - label = "nand-bitstream"; - reg = <0x0 0x3000000 0x400000>; - }; - partition@5 { /* for testing purpose */ - label = "nand-misc"; - reg = <0x0 0x3400000 0xfcc00000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "nand-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand-rootfs"; + reg = <0x0 0x1c00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand-misc"; + reg = <0x0 0x3400000 0xfcc00000>; + }; }; }; nand@1 { reg = <0x1>; - #address-cells = <0x2>; - #size-cells = <0x1>; nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-1"; @@ -183,29 +185,35 @@ nand-ecc-strength = <24>; nand-on-flash-bbt; - partition@0 { /* for testing purpose */ - label = "nand1-fsbl-uboot"; - reg = <0x0 0x0 0x400000>; - }; - partition@1 { /* for testing purpose */ - label = "nand1-linux"; - reg = <0x0 0x400000 0x1400000>; - }; - partition@2 { /* for testing purpose */ - label = "nand1-device-tree"; - reg = <0x0 0x1800000 0x400000>; - }; - partition@3 { /* for testing purpose */ - label = "nand1-rootfs"; - reg = <0x0 0x1c00000 0x1400000>; - }; - partition@4 { /* for testing purpose */ - label = "nand1-bitstream"; - reg = <0x0 0x3000000 0x400000>; - }; - partition@5 { /* for testing purpose */ - label = "nand1-misc"; - reg = <0x0 0x3400000 0xfcc00000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "nand1-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand1-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand1-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand1-rootfs"; + reg = <0x0 0x1c00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand1-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand1-misc"; + reg = <0x0 0x3400000 0xfcc00000>; + }; }; }; }; @@ -503,15 +511,18 @@ pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "sst,sst25wf080", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - label = "spi0-data"; - reg = <0x0 0x100000>; + partition@0 { + label = "spi0-data"; + reg = <0x0 0x100000>; + }; }; }; }; @@ -523,15 +534,18 @@ pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; spi-max-frequency = <20000000>; reg = <0>; - - partition@0 { - label = "spi1-data"; - reg = <0x0 0x84000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "spi1-data"; + reg = <0x0 0x84000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index a8856c20f5b..796669fc92c 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -133,8 +133,6 @@ nand@0 { reg = <0x0>; - #address-cells = <0x2>; - #size-cells = <0x1>; nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-0"; @@ -142,65 +140,74 @@ nand-ecc-strength = <24>; nand-on-flash-bbt; - partition@0 { /* for testing purpose */ - label = "nand-fsbl-uboot"; - reg = <0x0 0x0 0x400000>; - }; - partition@1 { /* for testing purpose */ - label = "nand-linux"; - reg = <0x0 0x400000 0x1400000>; - }; - partition@2 { /* for testing purpose */ - label = "nand-device-tree"; - reg = <0x0 0x1800000 0x400000>; - }; - partition@3 { /* for testing purpose */ - label = "nand-rootfs"; - reg = <0x0 0x1c00000 0x1400000>; - }; - partition@4 { /* for testing purpose */ - label = "nand-bitstream"; - reg = <0x0 0x3000000 0x400000>; - }; - partition@5 { /* for testing purpose */ - label = "nand-misc"; - reg = <0x0 0x3400000 0xfcc00000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "nand-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand-rootfs"; + reg = <0x0 0x1c00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand-misc"; + reg = <0x0 0x3400000 0xfcc00000>; + }; }; }; nand@1 { reg = <0x1>; - #address-cells = <0x2>; - #size-cells = <0x1>; nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-1"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; nand-on-flash-bbt; - - partition@0 { /* for testing purpose */ - label = "nand1-fsbl-uboot"; - reg = <0x0 0x0 0x400000>; - }; - partition@1 { /* for testing purpose */ - label = "nand1-linux"; - reg = <0x0 0x400000 0x1400000>; - }; - partition@2 { /* for testing purpose */ - label = "nand1-device-tree"; - reg = <0x0 0x1800000 0x400000>; - }; - partition@3 { /* for testing purpose */ - label = "nand1-rootfs"; - reg = <0x0 0x1c00000 0x1400000>; - }; - partition@4 { /* for testing purpose */ - label = "nand1-bitstream"; - reg = <0x0 0x3000000 0x400000>; - }; - partition@5 { /* for testing purpose */ - label = "nand1-misc"; - reg = <0x0 0x3400000 0xfcc00000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "nand1-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand1-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand1-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand1-rootfs"; + reg = <0x0 0x1c00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand1-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand1-misc"; + reg = <0x0 0x3400000 0xfcc00000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 3b03b39e456..cd80aed9a38 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -174,27 +174,31 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 3d71742fcbe..9590dd1cd92 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -986,28 +986,32 @@ num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index b4e62bf6bb6..3fe7cb410bc 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -452,27 +452,31 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index f7a91402a09..21ce50e1da9 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -464,27 +464,31 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 5eb5f77220d..0ac1472c55d 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -980,28 +980,32 @@ num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 72d331a740f..7894daeca94 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -803,28 +803,32 @@ num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index cc9f5b16025..b9d51fadc2a 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -46,27 +46,31 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index f78da036280..f26d9843243 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -73,27 +73,31 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; -- cgit v1.3.1 From 085a5acd9d102ad174d9653a7ef7bf6128e3aa87 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 9 Jun 2026 09:48:19 +0200 Subject: arm64: zynqmp: Add CMA reserved-memory for runtime FPGA loading Add CMA (Contiguous Memory Allocator) reserved-memory regions to all Xilinx arm64 board device trees to support runtime FPGA programming. The CMA pool uses dynamic allocation constrained to the low 2 GB DDR region via alloc-ranges so that the kernel places it within the 32-bit addressable space. CMA sizes are chosen per silicon family to accommodate the maximum PL bitstream/PDI size: - Kria K24 SOM: 64 MB - ZynqMP boards: 128 MB For Kria K24 SOM the CMA inherited from K26 is overridden to 64 MB. For Kria SOMs, the CMA node is added to the SOM DTS only, not to carrier board overlays. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/837e21582e886f1be9f95901109745ac5a8b2a25.1780991287.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sm-k24-revA.dts | 7 ++++++- arch/arm/dts/zynqmp-sm-k26-revA.dts | 11 ++++++++++- arch/arm/dts/zynqmp-zc1232-revA.dts | 15 +++++++++++++++ arch/arm/dts/zynqmp-zc1254-revA.dts | 15 +++++++++++++++ arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 17 ++++++++++++++++- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 17 ++++++++++++++++- arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 15 +++++++++++++++ arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 15 +++++++++++++++ arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 15 +++++++++++++++ arch/arm/dts/zynqmp-zcu100-revC.dts | 17 ++++++++++++++++- arch/arm/dts/zynqmp-zcu102-revA.dts | 17 ++++++++++++++++- arch/arm/dts/zynqmp-zcu104-revA.dts | 17 ++++++++++++++++- arch/arm/dts/zynqmp-zcu104-revC.dts | 17 ++++++++++++++++- arch/arm/dts/zynqmp-zcu106-revA.dts | 17 ++++++++++++++++- arch/arm/dts/zynqmp-zcu111-revA.dts | 17 ++++++++++++++++- arch/arm/dts/zynqmp-zcu1275-revA.dts | 15 +++++++++++++++ arch/arm/dts/zynqmp-zcu1275-revB.dts | 15 +++++++++++++++ arch/arm/dts/zynqmp-zcu1285-revA.dts | 15 +++++++++++++++ arch/arm/dts/zynqmp-zcu208-revA.dts | 15 +++++++++++++++ arch/arm/dts/zynqmp-zcu216-revA.dts | 15 +++++++++++++++ arch/arm/dts/zynqmp-zcu670-revA.dts | 17 ++++++++++++++++- arch/arm/dts/zynqmp-zcu670-revB.dts | 17 ++++++++++++++++- 22 files changed, 326 insertions(+), 12 deletions(-) diff --git a/arch/arm/dts/zynqmp-sm-k24-revA.dts b/arch/arm/dts/zynqmp-sm-k24-revA.dts index 653bd936226..34ee6af801d 100644 --- a/arch/arm/dts/zynqmp-sm-k24-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k24-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP SM-K24 RevA * * (C) Copyright 2020 - 2021, Xilinx, Inc. - * (C) Copyright 2022, Advanced Micro Devices, Inc. + * (C) Copyright 2022-2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -21,3 +21,8 @@ reg = <0 0 0 0x80000000>; }; }; + +&cma { + size = <0x0 0x4000000>; + alignment = <0x0 0x4000000>; +}; diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 0abec77b3f3..c7fe253244f 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A * * (C) Copyright 2020 - 2021, Xilinx, Inc. - * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc. + * (C) Copyright 2023 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -61,6 +61,15 @@ reg = <0x0 0x7ff00000 0x0 0x100000>; no-map; }; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; }; gpio-keys { diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts index 34e5b6edab1..f0e2a0b4588 100644 --- a/arch/arm/dts/zynqmp-zc1232-revA.dts +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -31,6 +31,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &dcc { diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts index 827143377b9..e92caefd3aa 100644 --- a/arch/arm/dts/zynqmp-zc1254-revA.dts +++ b/arch/arm/dts/zynqmp-zc1254-revA.dts @@ -32,6 +32,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &dcc { diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 33efdbf0e25..2897c423f82 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -41,6 +41,21 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + clock_si5338_0: clk27 { /* u55 SI5338-GM */ compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 13c304520a6..0b1185d862c 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -39,6 +39,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &can0 { diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index 796669fc92c..bfcc92cedfa 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -39,6 +39,21 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + clock_si5338_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index cd80aed9a38..9b59952993f 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -38,6 +38,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &can0 { diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 53aa3dca1dc..722b2e833b4 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -37,6 +37,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &fpd_dma_chan1 { diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 4ec8a400494..62f94da334d 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek * Nathalie Chan King Choy @@ -47,6 +47,21 @@ reg = <0x0 0x0 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 9590dd1cd92..a0ef866a259 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -45,6 +45,21 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 3fe7cb410bc..4479ff73514 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -43,6 +43,21 @@ reg = <0x0 0x0 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + clock_8t49n287_5: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 21ce50e1da9..0caedc40a51 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -43,6 +43,21 @@ reg = <0x0 0x0 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + ina226 { compatible = "iio-hwmon"; io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 0ac1472c55d..c0bc46faee4 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -45,6 +45,21 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 7894daeca94..f38edd6145f 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -45,6 +45,21 @@ /* Another 4GB connected to PL */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index b9d51fadc2a..1a49ae3ba4e 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -32,6 +32,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &dcc { diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index f26d9843243..1b6f7a605d6 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -35,6 +35,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &dcc { diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts index 86a3217f9ab..b2d71f0f455 100644 --- a/arch/arm/dts/zynqmp-zcu1285-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -36,6 +36,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &dcc { diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 70b1e81e304..3c3c94dcadf 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -43,6 +43,21 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index bc0ca24ff05..b0f0a74f711 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -43,6 +43,21 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts b/arch/arm/dts/zynqmp-zcu670-revA.dts index 1215babe214..c5b70972ef5 100644 --- a/arch/arm/dts/zynqmp-zcu670-revA.dts +++ b/arch/arm/dts/zynqmp-zcu670-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU670 (67DR) * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -46,6 +46,21 @@ /* Another 4GB connected to PL */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts b/arch/arm/dts/zynqmp-zcu670-revB.dts index e91f280e457..cd96a7a0d13 100644 --- a/arch/arm/dts/zynqmp-zcu670-revB.dts +++ b/arch/arm/dts/zynqmp-zcu670-revB.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU670 (67DR) revB * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -46,6 +46,21 @@ /* Another 4GB connected to PL */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; -- cgit v1.3.1 From af7a1a6f24411d2bd6d8f39efe8ff486c0e3da55 Mon Sep 17 00:00:00 2001 From: Shaikh Mohammed Suhan Date: Tue, 9 Jun 2026 09:48:20 +0200 Subject: arm64: zynqmp: add USB hub supply regulators Add fixed supply regulators for the onboard USB hub (USB2744) used on Kria platforms. The USB hub requires two always-on power rails: - vdd: 3.3V main supply - vdd2: auxiliary supply Model these rails as fixed regulators and reference them from the hub node to accurately describe the hardware. Signed-off-by: Shaikh Mohammed Suhan Reviewed-by: Radhey Shyam Pandey Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/541ee484c0f73fda630022528ddc56d01a481bca.1780991287.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sck-kd-g-revA.dtso | 20 ++++++++++++++++++++ arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 22 ++++++++++++++++++++++ arch/arm/dts/zynqmp-sck-kr-g-revB.dtso | 22 ++++++++++++++++++++++ arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 20 ++++++++++++++++++++ arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 20 ++++++++++++++++++++ 5 files changed, 104 insertions(+) diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index 021bf8ac26e..02b9d82eb7c 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -50,6 +50,24 @@ gpio-controller; gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; }; + + vdd_usb_hub: regulator-vdd-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb_hub"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd2_usb_hub: regulator-vdd2-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd2_usb_hub"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; }; &can0 { @@ -124,6 +142,8 @@ peer-hub = <&hub_3_0>; i2c-bus = <&hub>; reset-gpios = <&slg_delay 0 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index 048aeb1e765..47f0fb5f74f 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -85,6 +85,24 @@ gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>, <&slg7xl45106 4 GPIO_ACTIVE_LOW>; }; + + vdd_usb_hub: regulator-vdd-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb_hub"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd2_usb_hub: regulator-vdd2-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd2_usb_hub"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; }; &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ @@ -196,6 +214,8 @@ peer-hub = <&hub_3_0>; i2c-bus = <&hub_1>; reset-gpios = <&slg_delay 0 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ @@ -233,6 +253,8 @@ peer-hub = <&hub1_3_0>; i2c-bus = <&hub_2>; reset-gpios = <&slg_delay 1 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index 2eef6ba7df7..b3c75f67bbd 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -86,6 +86,24 @@ gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>, <&slg7xl45106 4 GPIO_ACTIVE_LOW>; }; + + vdd_usb_hub: regulator-vdd-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb_hub"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd2_usb_hub: regulator-vdd2-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd2_usb_hub"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; }; &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ @@ -197,6 +215,8 @@ peer-hub = <&hub_3_0>; i2c-bus = <&hub_1>; reset-gpios = <&slg_delay 0 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ @@ -234,6 +254,8 @@ peer-hub = <&hub1_3_0>; i2c-bus = <&hub_2>; reset-gpios = <&slg_delay 1 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index ea947cd2dc0..3c551f30315 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -85,6 +85,24 @@ gpio-controller; gpios = <&gpio 44 GPIO_ACTIVE_LOW>; }; + + vdd_usb_hub: regulator-vdd-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb_hub"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd2_usb_hub: regulator-vdd2-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd2_usb_hub"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ @@ -169,6 +187,8 @@ reg = <1>; peer-hub = <&hub_3_0>; reset-gpios = <&slg_delay 0 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index ea7b9253468..a60bd7b7bdb 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -81,6 +81,24 @@ gpio-controller; gpios = <&gpio 44 GPIO_ACTIVE_LOW>; }; + + vdd_usb_hub: regulator-vdd-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb_hub"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd2_usb_hub: regulator-vdd2-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd2_usb_hub"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ @@ -156,6 +174,8 @@ peer-hub = <&hub_3_0>; i2c-bus = <&hub>; reset-gpios = <&slg_delay 0 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ -- cgit v1.3.1 From ed507e78666a1ac0a81bcff0d051ab2a792e2743 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 9 Jun 2026 09:48:21 +0200 Subject: arm64: zynqmp: dts: Fix file descriptions to match actual filenames Fix descriptions that don't match their filenames: - zynqmp-sc-vpk180-revB.dtso: described as revA instead of revB - zynqmp-sck-kv-g-revB.dtso: described as revA instead of revB Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/456e4ff541c60355aa3d35627ec481263113349e.1780991287.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sc-vpk180-revB.dtso | 2 +- arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso index 74e1c5c6dc9..6a5ada34ed7 100644 --- a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso +++ b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * dts file for Xilinx ZynqMP VPK180 revA + * dts file for Xilinx ZynqMP VPK180 revB * * (C) Copyright 2021 - 2022, Xilinx, Inc. * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index a60bd7b7bdb..0fa5a990adc 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * dts file for KV260 revA Carrier Card + * dts file for KV260 revB Carrier Card * * (C) Copyright 2020 - 2022, Xilinx, Inc. * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. -- cgit v1.3.1 From 262eed542619d7202a3ead470b59911d5c14733b Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 9 Jun 2026 09:48:22 +0200 Subject: arm64: dts: xilinx: Drop "label" property on dlg, slg7xl45106 The "label" property is not documented for the dlg,slg7xl45106. Nor is it common to use for GPIO controllers. So drop it. Signed-off-by: Rob Herring (Arm) Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/32c5b160de5b8e5ffb91366cbafac0b5fd5c834a.1780991287.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sck-kd-g-revA.dtso | 1 - arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 1 - arch/arm/dts/zynqmp-sck-kr-g-revB.dtso | 1 - 3 files changed, 3 deletions(-) diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index 02b9d82eb7c..a32073fa040 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -94,7 +94,6 @@ slg7xl45106: gpio@11 { /* u13 - reset logic */ compatible = "dlg,slg7xl45106"; reg = <0x11>; - label = "resetchip"; gpio-controller; #gpio-cells = <2>; gpio-line-names = "USB0_PHY_RESET_B", "", diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index 47f0fb5f74f..2bc28b7baf8 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -123,7 +123,6 @@ slg7xl45106: gpio@11 { /* u19 - reset logic */ compatible = "dlg,slg7xl45106"; reg = <0x11>; - label = "resetchip"; gpio-controller; #gpio-cells = <2>; gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index b3c75f67bbd..f1114a35aae 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -124,7 +124,6 @@ slg7xl45106: gpio@11 { /* u19 - reset logic */ compatible = "dlg,slg7xl45106"; reg = <0x11>; - label = "resetchip"; gpio-controller; #gpio-cells = <2>; gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", -- cgit v1.3.1 From 0659f97f1879a4987503494925a153c8c7ad9173 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 9 Jun 2026 09:48:23 +0200 Subject: arm64: zynqmp: Sync compatible string format There is no reason to have non zynqmp-sc compatible string for overlays which can be applied only with SCs. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/4192927ae769e74e4ddbc1cc9814ed0305b64a5d.1780991287.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sc-vek280-revA.dtso | 5 ++--- arch/arm/dts/zynqmp-sc-vek280-revB.dtso | 5 ++--- arch/arm/dts/zynqmp-sc-vhk158-revA.dtso | 5 ++--- arch/arm/dts/zynqmp-sc-vpk120-revB.dtso | 5 ++--- arch/arm/dts/zynqmp-sc-vpk180-revA.dtso | 5 ++--- arch/arm/dts/zynqmp-sc-vpk180-revB.dtso | 5 ++--- 6 files changed, 12 insertions(+), 18 deletions(-) diff --git a/arch/arm/dts/zynqmp-sc-vek280-revA.dtso b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso index e94b784e8e1..7212ee9df86 100644 --- a/arch/arm/dts/zynqmp-sc-vek280-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP VEK280 revA * - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -13,8 +13,7 @@ /plugin/; &{/} { - compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-vek280-revA", - "xlnx,zynqmp-vek280", "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-sc-vek280", "xlnx,zynqmp"; vc7_xin: vc7-xin { compatible = "fixed-clock"; diff --git a/arch/arm/dts/zynqmp-sc-vek280-revB.dtso b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso index a3983f330d0..a57e9b50b20 100644 --- a/arch/arm/dts/zynqmp-sc-vek280-revB.dtso +++ b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP VEK280 revB * - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -10,6 +10,5 @@ #include "zynqmp-sc-vek280-revA.dtso" &{/} { - compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB", - "xlnx,zynqmp-vek280", "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-sc-vek280", "xlnx,zynqmp"; }; diff --git a/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso index fd25731b0b4..2fe35596143 100644 --- a/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP VHK158 revA * * (C) Copyright 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -14,8 +14,7 @@ /plugin/; &{/} { - compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-vhk158-revA", - "xlnx,zynqmp-vhk158", "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-sc-vhk158", "xlnx,zynqmp"; vc7_xin: vc7-xin { compatible = "fixed-clock"; diff --git a/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso index 29b3a73fde0..ae0691c0127 100644 --- a/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso +++ b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP VPK120 revB * * (C) Copyright 2021 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -14,8 +14,7 @@ /plugin/; &{/} { - compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-vpk120-revB", - "xlnx,zynqmp-vpk120", "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-sc-vpk120", "xlnx,zynqmp"; }; &i2c0 { diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso index 10466ce99de..9b6534f6383 100644 --- a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP VPK180 revA * * (C) Copyright 2021 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -14,8 +14,7 @@ /plugin/; &{/} { - compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-vpk180-revA", - "xlnx,zynqmp-vpk180", "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-sc-vpk180", "xlnx,zynqmp"; vc7_xin: vc7-xin { compatible = "fixed-clock"; diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso index 6a5ada34ed7..941d26c025a 100644 --- a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso +++ b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP VPK180 revB * * (C) Copyright 2021 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -14,8 +14,7 @@ /plugin/; &{/} { - compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-vpk180-revB", - "xlnx,zynqmp-vpk180", "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-sc-vpk180", "xlnx,zynqmp"; vc7_xin: vc7-xin { compatible = "fixed-clock"; -- cgit v1.3.1 From d6e7db8f11fde6d79c5e9b5a41ba8a9625b113a8 Mon Sep 17 00:00:00 2001 From: Suraj Kakade Date: Wed, 10 Jun 2026 16:35:31 +0530 Subject: amd: versal2: detect spi env bus from boot mode Add spi_get_env_dev() to dynamically detect the correct SPI bus based on the actual boot mode at runtime. This ensures environment variables are always loaded from the correct SPI flash controller regardless of the bus numbering. For example, on some Versal Gen 2 boards, SPI is disabled in DTS leaving bus 0 empty in DM. Only QSPI is enabled at bus 1. The default CONFIG_ENV_SPI_BUS=0 causes U-Boot to search for environment at bus 0 which does not exist, triggering the warning "spi_flash_probe_bus_cs() failed, using default environment". Signed-off-by: Suraj Kakade Link: https://lore.kernel.org/r/20260610110557.2183203-1-suraj.hanumantkakade@amd.com Signed-off-by: Michal Simek --- board/amd/versal2/board.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index ec28e60c410..6e4f0c6e9b8 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -605,3 +605,31 @@ void set_dfu_alt_info(char *interface, char *devstr) env_set("dfu_alt_info", buf); } #endif + +int spi_get_env_dev(void) +{ + struct udevice *dev; + const char *name; + int bootseq; + + switch (versal2_get_bootmode()) { + case QSPI_MODE_24BIT: + case QSPI_MODE_32BIT: + name = "spi@f1030000"; + break; + case OSPI_MODE: + name = "spi@f1010000"; + break; + default: + return -1; + } + + if (uclass_get_device_by_name(UCLASS_SPI, name, &dev)) { + debug("SPI driver for %s is not present\n", name); + return -1; + } + + bootseq = dev_seq(dev); + debug("bootseq %d\n", bootseq); + return bootseq; +} -- cgit v1.3.1 From cea8f9407c538e7b3a590d718180864596fc4110 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 11 Jun 2026 14:10:25 +0200 Subject: arm64: versal2: Drop static DDR MMU mappings DDR coverage is already populated later from the DRAM banks discovered by mem_map_fill(). Drop the stale static mappings so the MMU table matches address map more closely. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/156e48d8228acfeba8866618038b48cd51490ea7.1781179823.git.michal.simek@amd.com --- arch/arm/mach-versal2/cpu.c | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c index f65c231bdab..d66109abd78 100644 --- a/arch/arm/mach-versal2/cpu.c +++ b/arch/arm/mach-versal2/cpu.c @@ -19,9 +19,9 @@ DECLARE_GLOBAL_DATA_PTR; #if CONFIG_IS_ENABLED(PCIE_DW_AMD) -#define VERSAL2_MEM_MAP_USED 6 +#define VERSAL2_MEM_MAP_USED 4 #else -#define VERSAL2_MEM_MAP_USED 5 +#define VERSAL2_MEM_MAP_USED 3 #endif #define DRAM_BANKS CONFIG_NR_DRAM_BANKS @@ -51,19 +51,6 @@ static struct mm_region versal2_mem_map[VERSAL2_MEM_MAP_MAX] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x600000000UL, - .phys = 0x600000000UL, - .size = 0x800000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xe00000000UL, - .phys = 0xe00000000UL, - .size = 0xf200000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN #if CONFIG_IS_ENABLED(PCIE_DW_AMD) }, { /* PCIe DBI (1 MB) and config space (255 MB) are contiguous */ -- cgit v1.3.1 From 71c54b9769bfe43c72908678921537819cf38db6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 11 Jun 2026 14:10:26 +0200 Subject: arm64: versal: Drop static DDR and PCIe MMU mappings AM011 Versal ACAP TRM, Table 43, defines: - 0x006_0000_0000 - 0x007_FFFF_FFFF PCIe region 1 - 0x008_0000_0000 - 0x00F_FFFF_FFFF DDR controller 0 region 1 - 0x040_0000_0000 - 0x04F_FFFF_FFFF HBM0 - 0x050_0000_0000 - 0x05F_FFFF_FFFF HBM1 - 0x060_0000_0000 - 0x06F_FFFF_FFFF HBM2 - 0x070_0000_0000 - 0x07F_FFFF_FFFF HBM3 - 0x080_0000_0000 - 0x0BF_FFFF_FFFF PCIe region 2 - 0x0C0_0000_0000 - 0x0FF_FFFF_FFFF DDR controller 0 region 2 The old static normal-memory mapping spans PCIe, while DDR coverage is already populated later from the DRAM banks discovered by mem_map_fill(). Drop the stale static mapping so the MMU table matches the Versal address map. Also matting was using wrong attributes. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/6fad36f9e7abdfee2fd29943f3a5b63d1421eaf9.1781179823.git.michal.simek@amd.com --- arch/arm/mach-versal/cpu.c | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 0dd5cc153c4..7ffd35fe89c 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2016 - 2018 Xilinx, Inc. + * (C) Copyright 2026, Advanced Micro Devices, Inc. + * * Michal Simek */ @@ -16,7 +18,7 @@ DECLARE_GLOBAL_DATA_PTR; -#define VERSAL_MEM_MAP_USED 5 +#define VERSAL_MEM_MAP_USED 3 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS @@ -44,26 +46,13 @@ static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { + }, { /* FPD_AXI_PL_high */ .virt = 0x400000000UL, .phys = 0x400000000UL, .size = 0x200000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x600000000UL, - .phys = 0x600000000UL, - .size = 0x800000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xe00000000UL, - .phys = 0xe00000000UL, - .size = 0xf200000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN } }; -- cgit v1.3.1 From cc0d3f546063383b6547ffe850f61818eae8c700 Mon Sep 17 00:00:00 2001 From: "Erich E. Hoover" Date: Fri, 12 Jun 2026 09:04:54 -0600 Subject: mkimage: allow zynqmpbif to use a register initialization file The ZynqMP Boot Image Format allows specifying the register initialization file with the "[init]" attribute. Since this feature is already supported by the "zynqmpimage" backend, this commit leverages that existing capability to add support for the "[init]" attribute in the zynqmpbif backend: https://docs.amd.com/r/en-US/ug1283-bootgen-user-guide/init This currently uses the same register initialization file format as zynqmpimage (ASCII text hex values with each line composed of a pair of register address and value), for example: === 0xff003248 0x12345678 === It is not, yet, compatible with the format used by bootgen: https://docs.amd.com/r/en-US/ug1283-bootgen-user-guide/Initialization-Pairs-and-INT-File-Attribute Use this feature, with other zynqmpbif options, like so: === image : { [init] reginit.int [bootloader] fsbl.elf [pmufw_image] pmufw.elf [destination_cpu=a53-0, exception_level=el-3] bl31.elf [destination_cpu=a53-0, exception_level=el-2, load=0x08000000, startup=0x08000000] u-boot.bin } === Signed-off-by: Erich E. Hoover Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20260612150454.2194375-1-erich.e.hoover@gmail.com --- tools/zynqmpbif.c | 12 ++++++++++++ tools/zynqmpimage.c | 4 ++-- tools/zynqmpimage.h | 2 ++ 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/tools/zynqmpbif.c b/tools/zynqmpbif.c index 82ce0ac1a52..50d76b03476 100644 --- a/tools/zynqmpbif.c +++ b/tools/zynqmpbif.c @@ -191,6 +191,7 @@ static char *parse_partition_owner(char *line, struct bif_entry *bf) } static const struct bif_flags bif_flags[] = { + { "init", BIF_FLAG_INIT }, { "fsbl_config", BIF_FLAG_FSBL_CONFIG }, { "trustzone", BIF_FLAG_TZ }, { "pmufw_image", BIF_FLAG_PMUFW_IMAGE }, @@ -316,6 +317,15 @@ static int bif_add_pmufw(struct bif_entry *bf, const char *data, size_t len) return 0; } +static int bif_add_reginit(struct bif_entry *init) +{ + /* User can pass in text file with init list */ + if (strlen(init->filename)) + zynqmpimage_parse_initparams(bif_output.header, init->filename); + + return 0; +} + static int bif_add_part(struct bif_entry *bf, const char *data, size_t len) { size_t parthdr_offset = 0; @@ -340,6 +350,8 @@ static int bif_add_part(struct bif_entry *bf, const char *data, size_t len) if (bf->flags & (1ULL << BIF_FLAG_PMUFW_IMAGE)) return bif_add_pmufw(bf, data, len); + else if (bf->flags & (1ULL << BIF_FLAG_INIT)) + return bif_add_reginit(bf); r = bif_add_blob(data, len, &bf->offset); if (r) diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c index 4db9877127e..eb79c0696cc 100644 --- a/tools/zynqmpimage.c +++ b/tools/zynqmpimage.c @@ -400,8 +400,8 @@ static void zynqmpimage_pmufw(struct zynqmp_header *zynqhdr, fclose(fpmu); } -static void zynqmpimage_parse_initparams(struct zynqmp_header *zynqhdr, - const char *filename) +void zynqmpimage_parse_initparams(struct zynqmp_header *zynqhdr, + const char *filename) { FILE *fp; struct zynqmp_reginit reginit; diff --git a/tools/zynqmpimage.h b/tools/zynqmpimage.h index 7c47dc0763b..867fc5294a3 100644 --- a/tools/zynqmpimage.h +++ b/tools/zynqmpimage.h @@ -142,6 +142,8 @@ struct zynqmp_header { void zynqmpimage_default_header(struct zynqmp_header *ptr); void zynqmpimage_print_header(const void *ptr, struct image_tool_params *params); +void zynqmpimage_parse_initparams(struct zynqmp_header *zynqhdr, + const char *filename); static inline struct image_header_table * zynqmp_get_iht(const struct zynqmp_header *zynqhdr) -- cgit v1.3.1 From e1c01da69fb03a590c90fe3b5ff8b12980b6209c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 17 Jun 2026 04:48:46 +0200 Subject: MAINTAINERS: Replace Zynq/ZynqMP with N: Use N: to match on all zynq/zynqmp files, drop the large list of entries which represent the same set of relevant files and miss a few in the process. Combine Zynq and ZynqMP entries into single entry to further cut down the duplication. Signed-off-by: Marek Vasut Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20260617024902.153555-1-marek.vasut+renesas@mailbox.org --- MAINTAINERS | 56 ++++---------------------------------------------------- 1 file changed, 4 insertions(+), 52 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8086eed7b9f..030f92a84f9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -881,72 +881,24 @@ T: git git://github.com/ARM-software/u-boot.git F: drivers/misc/vexpress_config.c N: vexpress -ARM ZYNQ +ARM ZYNQ and ZYNQMP M: Michal Simek +M: Michal Simek S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git -F: arch/arm/mach-zynq/ F: doc/board/xilinx/ F: doc/device-tree-bindings/video/syncoam,seps525.txt -F: drivers/clk/clk_zynq.c -F: drivers/fpga/zynqpl.c -F: drivers/gpio/zynq_gpio.c -F: drivers/i2c/i2c-cdns.c -F: drivers/i2c/muxes/pca954x.c -F: drivers/i2c/zynq_i2c.c -F: drivers/mmc/zynq_sdhci.c -F: drivers/mtd/nand/raw/zynq_nand.c -F: drivers/net/phy/ethernet_id.c -F: drivers/net/phy/xilinx_phy.c -F: drivers/net/zynq_gem.c -F: drivers/pinctrl/pinctrl-zynqmp.c -F: drivers/serial/serial_zynq.c -F: drivers/spi/zynq_qspi.c -F: drivers/spi/zynq_spi.c -F: drivers/usb/host/ehci-zynq.c -F: drivers/watchdog/cdns_wdt.c -F: include/zynqpl.h -F: tools/zynqimage.c -N: zynq - -ARM ZYNQMP -M: Michal Simek -S: Maintained -T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git -F: arch/arm/mach-zynqmp/ -F: drivers/bootcount/bootcount_zynqmp.c -F: drivers/clk/clk_zynqmp.c -F: driver/firmware/firmware-zynqmp.c -F: drivers/fpga/zynqpl.c F: drivers/gpio/gpio_slg7xl45106.c -F: drivers/gpio/zynq_gpio.c -F: drivers/gpio/zynqmp_gpio_modepin.c F: drivers/i2c/i2c-cdns.c F: drivers/i2c/muxes/pca954x.c -F: drivers/i2c/zynq_i2c.c -F: drivers/mailbox/zynqmp-ipi.c -F: drivers/mmc/zynq_sdhci.c -F: drivers/mtd/nand/raw/zynq_nand.c +F: drivers/net/phy/ethernet_id.c F: drivers/net/phy/xilinx_phy.c -F: drivers/net/zynq_gem.c -F: drivers/phy/phy-zynqmp.c -F: drivers/power/domain/zynqmp-power-domain.c F: drivers/pwm/pwm-cadence-ttc.c -F: drivers/serial/serial_zynq.c -F: drivers/reset/reset-zynqmp.c -F: drivers/rtc/zynqmp_rtc.c -F: drivers/soc/soc_xilinx_zynqmp.c -F: drivers/spi/zynq_qspi.c -F: drivers/spi/zynq_spi.c F: drivers/timer/cadence-ttc.c F: drivers/video/seps525.c -F: drivers/video/zynqmp/ F: drivers/watchdog/cdns_wdt.c -F: include/zynqmppl.h -F: include/zynqmp_firmware.h -F: tools/zynqmp* N: ultra96 -N: zynqmp +N: zynq ARM ZYNQMP R5 M: Michal Simek -- cgit v1.3.1 From f436398f469b20a822ee84aab96ff6594a5fbd0c Mon Sep 17 00:00:00 2001 From: Pranav Tilak Date: Tue, 23 Jun 2026 09:23:51 +0530 Subject: ufs: amd-versal2: Fix missing .priv_auto in driver registration Add missing .priv_auto field to the driver. Without it, struct ufs_versal2_priv is never properly allocated and dev_get_priv() returns NULL, leading to DDR corruption at low DDR addresses. Fixes: b5ac5f030720 ("ufs: ufs-amd-versal2: Add support for AMD UFS controller") Signed-off-by: Pranav Tilak Reviewed-by: Neil Armstrong Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20260623035411.2088224-1-pranav.vinaytilak@amd.com --- drivers/ufs/ufs-amd-versal2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/ufs/ufs-amd-versal2.c b/drivers/ufs/ufs-amd-versal2.c index 6c949b2ca76..3369d32d924 100644 --- a/drivers/ufs/ufs-amd-versal2.c +++ b/drivers/ufs/ufs-amd-versal2.c @@ -563,4 +563,5 @@ U_BOOT_DRIVER(ufs_versal2_pltfm) = { .id = UCLASS_UFS, .of_match = ufs_versal2_ids, .probe = ufs_versal2_probe, + .priv_auto = sizeof(struct ufs_versal2_priv), }; -- cgit v1.3.1 From 7edbbfca632a97104b9bbe0ba6ba7accea395822 Mon Sep 17 00:00:00 2001 From: Danish Ahmad Rosdi Date: Mon, 8 Jun 2026 17:45:47 +0800 Subject: drivers: fpga: Use FPGA_INTEL_SDM_MAILBOX conditional instead of Agilex/Stratix10 Replace the conditional compilation checks for CONFIG_ARCH_SOCFPGA_AGILEX and CONFIG_ARCH_SOCFPGA_STRATIX10 with CONFIG_FPGA_INTEL_SDM_MAILBOX. Signed-off-by: Danish Ahmad Rosdi Signed-off-by: Chen Huei Lok Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20260608094547.3026-1-chen.huei.lok@altera.com --- drivers/fpga/altera.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 822183c5785..69d7111a5f1 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -12,8 +12,7 @@ /* * Altera FPGA support */ -#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) +#if IS_ENABLED(CONFIG_FPGA_INTEL_SDM_MAILBOX) #include #endif #include @@ -48,8 +47,7 @@ static const struct altera_fpga { #endif }; -#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) +#if IS_ENABLED(CONFIG_FPGA_INTEL_SDM_MAILBOX) int fpga_is_partial_data(int devnum, size_t img_len) { /* -- cgit v1.3.1 From 1d24edabfed9d32be7e35a53946ae177d4b4121a Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Tue, 23 Jun 2026 20:38:22 +0530 Subject: soc: xilinx: zynqmp: Add TCG variant detection for ZU3TCG The XCZU3TCG device shares IDCODE 0x04718093 with XCZU3TEG but has the GPU disable eFuse bit set (Consumer Grade, no GPU). Previously, the TEG detection branch appended "teg" unconditionally, causing U-Boot to report the device as zu3teg and failing bitstream ID checks for xczu3tcg bitstreams. Check EFUSE_GPU_DIS_MASK in the TEG branch to distinguish the two sub-variants, mirroring the existing EG/CG detection logic: - GPU disabled -> TCG family -> "zu3tcg" - GPU enabled -> TEG family -> "zu3teg" Fixes: fa2f0c97af96 ("soc: zynqmp: Add the IDcode for TEG variant") Signed-off-by: Padmarao Begari Signed-off-by: Michal Simek Link: https://patch.msgid.link/20260623150943.2662500-1-padmarao.begari@amd.com --- drivers/soc/soc_xilinx_zynqmp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index 4abc73013eb..0e13e230914 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -358,7 +358,9 @@ static int soc_xilinx_zynqmp_detect_machine(struct udevice *dev, u32 idcode, } else if (device->variants & ZYNQMP_VARIANT_DR_SE) { strlcat(priv->machine, "dr_SE", sizeof(priv->machine)); } else if (device->variants & ZYNQMP_VARIANT_TEG) { - strlcat(priv->machine, "teg", sizeof(priv->machine)); + /* Devices with TEG variant might be TEG or TCG family */ + strlcat(priv->machine, (idcode2 & EFUSE_GPU_DIS_MASK) ? + "tcg" : "teg", sizeof(priv->machine)); } return 0; -- cgit v1.3.1 From 5979d3d44e5fe1e4f8827b585b92a0c17532edd9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 Jun 2026 14:53:26 +0200 Subject: arm: xilinx: Guard mach sys_proto.h against multiple inclusion The Versal and Versal Gen 2 mach sys_proto.h headers lacked an include guard. mach-versal/sys_proto.h additionally defines enum tcm_mode, so including it twice in one translation unit fails to build with a redeclaration error. This is about to happen in firmware-zynqmp.c, which needs the SoC prototypes unconditionally for the upcoming weak/strong multiboot and bootmode accessors. Add the standard _ASM_ARCH_SYS_PROTO_H guard, as already used by mach-zynqmp, so the header can be included more than once. Signed-off-by: Michal Simek Link: https://patch.msgid.link/1bf5b1d49abb271c2c5e7135837b740179b95553.1782219202.git.michal.simek@amd.com --- arch/arm/mach-versal/include/mach/sys_proto.h | 5 +++++ arch/arm/mach-versal2/include/mach/sys_proto.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h index a6dfa556966..b53e616e47b 100644 --- a/arch/arm/mach-versal/include/mach/sys_proto.h +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -3,6 +3,9 @@ * Copyright 2016 - 2018 Xilinx, Inc. */ +#ifndef _ASM_ARCH_SYS_PROTO_H +#define _ASM_ARCH_SYS_PROTO_H + #include enum tcm_mode { @@ -13,3 +16,5 @@ enum tcm_mode { void initialize_tcm(enum tcm_mode mode); void tcm_init(enum tcm_mode mode); void mem_map_fill(void); + +#endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-versal2/include/mach/sys_proto.h b/arch/arm/mach-versal2/include/mach/sys_proto.h index cee13488620..3ed0b25be80 100644 --- a/arch/arm/mach-versal2/include/mach/sys_proto.h +++ b/arch/arm/mach-versal2/include/mach/sys_proto.h @@ -4,8 +4,13 @@ * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. */ +#ifndef _ASM_ARCH_SYS_PROTO_H +#define _ASM_ARCH_SYS_PROTO_H + #include #include void mem_map_fill(struct mm_region *bank_info, u32 num_banks); void fill_bd_mem_info(void); + +#endif /* _ASM_ARCH_SYS_PROTO_H */ -- cgit v1.3.1 From da4783f7835630141d684369518141d1b0e86fe1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 Jun 2026 14:53:27 +0200 Subject: arm64: versal2: Decouple multiboot register access from firmware versal2_multi_boot() in board code selected between the firmware call zynqmp_pm_get_pmc_multi_boot_reg() and a direct readl() based on an IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) check. Generic board code should not carry firmware-specific ifdefs, and this becomes harder to maintain once SCMI introduces yet another access method. Introduce an overridable accessor versal2_pmc_multi_boot(). The weak default lives in arch/arm/mach-versal2 and performs the plain MMIO read (used at EL3 and when no firmware is present). When CONFIG_ZYNQMP_FIRMWARE is enabled, firmware-zynqmp.c provides a strong definition that issues the firmware call, falling back to the direct read at EL3 where the SMC path to firmware is unavailable. The shared MMIO read is factored into versal2_multi_boot_reg() so the firmware override does not duplicate it. versal2_multi_boot() keeps the generic JTAG/QEMU workaround and simply calls the accessor, so board code no longer references the firmware interface and the now unused zynqmp_firmware.h include is dropped. The firmware-vs-MMIO decision is selected at link time, and adding SCMI later only requires a third strong definition with no board-code changes. Signed-off-by: Michal Simek Link: https://patch.msgid.link/0033a1fa8efb4ae0c3ac6a6f5c5c1b4e0f22f02c.1782219202.git.michal.simek@amd.com --- arch/arm/mach-versal2/cpu.c | 10 ++++++++++ arch/arm/mach-versal2/include/mach/sys_proto.h | 5 +++++ board/amd/versal2/board.c | 9 +-------- drivers/firmware/firmware-zynqmp.c | 13 +++++++++++++ 4 files changed, 29 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c index d66109abd78..9991d6bbab0 100644 --- a/arch/arm/mach-versal2/cpu.c +++ b/arch/arm/mach-versal2/cpu.c @@ -127,6 +127,16 @@ u64 get_page_table_size(void) } #endif +u32 versal2_multi_boot_reg(void) +{ + return readl(PMC_MULTI_BOOT_REG) & PMC_MULTI_BOOT_MASK; +} + +u32 __weak versal2_pmc_multi_boot(void) +{ + return versal2_multi_boot_reg(); +} + U_BOOT_DRVINFO(soc_amd_versal2) = { .name = "soc_amd_versal2", }; diff --git a/arch/arm/mach-versal2/include/mach/sys_proto.h b/arch/arm/mach-versal2/include/mach/sys_proto.h index 3ed0b25be80..e0576754836 100644 --- a/arch/arm/mach-versal2/include/mach/sys_proto.h +++ b/arch/arm/mach-versal2/include/mach/sys_proto.h @@ -13,4 +13,9 @@ void mem_map_fill(struct mm_region *bank_info, u32 num_banks); void fill_bd_mem_info(void); +/* Overridable PMC multiboot accessor: weak MMIO default, firmware override */ +u32 versal2_pmc_multi_boot(void); +/* Direct MMIO read of the multiboot register (EL3 / no-firmware path) */ +u32 versal2_multi_boot_reg(void); + #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index 6e4f0c6e9b8..06d144db4f0 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -29,7 +29,6 @@ #include #include #include -#include #include "../../xilinx/common/board.h" #include @@ -195,18 +194,12 @@ static u8 versal2_get_bootmode(void) static u32 versal2_multi_boot(void) { u8 bootmode = versal2_get_bootmode(); - u32 reg = 0; /* Mostly workaround for QEMU CI pipeline */ if (bootmode == JTAG_MODE) return 0; - if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) - reg = zynqmp_pm_get_pmc_multi_boot_reg(); - else - reg = readl(PMC_MULTI_BOOT_REG); - - return reg & PMC_MULTI_BOOT_MASK; + return versal2_pmc_multi_boot(); } static int boot_targets_setup(void) diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index ea14ed4ef95..70d205ff3ef 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -16,6 +17,7 @@ #include #include #include +#include #include #if defined(CONFIG_ZYNQMP_IPI) @@ -326,6 +328,17 @@ u32 zynqmp_pm_get_pmc_multi_boot_reg(void) } #endif +#if defined(CONFIG_ARCH_VERSAL2) +u32 versal2_pmc_multi_boot(void) +{ + /* At EL3 the SMC path to firmware is unavailable, read directly */ + if (current_el() == 3) + return versal2_multi_boot_reg(); + + return zynqmp_pm_get_pmc_multi_boot_reg() & PMC_MULTI_BOOT_MASK; +} +#endif + int zynqmp_pm_feature(const u32 api_id) { int ret; -- cgit v1.3.1 From 789a48719480095645cd9ac7b6447b473764f5a7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 Jun 2026 14:53:28 +0200 Subject: arm64: versal2: Move bootmode decoding out of board code versal2_get_bootmode() lived in board code and accessed the CRP boot mode register with a direct readl(). To keep generic board code free of SoC register details and ready for firmware/SCMI based access, move the whole function, including the alt-shift and mask decoding, into arch/arm/mach-versal2 as a __weak default. Board code now simply calls versal2_get_bootmode(). When a firmware based implementation is available and tested it can provide a strong definition that overrides the weak one at link time; until then only the weak MMIO version is built. Signed-off-by: Michal Simek Link: https://patch.msgid.link/f3274ec77218373bc0452f6795a3ad6016be0058.1782219202.git.michal.simek@amd.com --- arch/arm/mach-versal2/cpu.c | 15 +++++++++++++++ arch/arm/mach-versal2/include/mach/sys_proto.h | 2 ++ board/amd/versal2/board.c | 15 --------------- 3 files changed, 17 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c index 9991d6bbab0..2b30a81d250 100644 --- a/arch/arm/mach-versal2/cpu.c +++ b/arch/arm/mach-versal2/cpu.c @@ -137,6 +137,21 @@ u32 __weak versal2_pmc_multi_boot(void) return versal2_multi_boot_reg(); } +u8 __weak versal2_get_bootmode(void) +{ + u8 bootmode; + u32 reg; + + reg = readl(&crp_base->boot_mode_usr); + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + bootmode = reg & BOOT_MODES_MASK; + + return bootmode; +} + U_BOOT_DRVINFO(soc_amd_versal2) = { .name = "soc_amd_versal2", }; diff --git a/arch/arm/mach-versal2/include/mach/sys_proto.h b/arch/arm/mach-versal2/include/mach/sys_proto.h index e0576754836..b3118c208e8 100644 --- a/arch/arm/mach-versal2/include/mach/sys_proto.h +++ b/arch/arm/mach-versal2/include/mach/sys_proto.h @@ -17,5 +17,7 @@ void fill_bd_mem_info(void); u32 versal2_pmc_multi_boot(void); /* Direct MMIO read of the multiboot register (EL3 / no-firmware path) */ u32 versal2_multi_boot_reg(void); +/* Weak bootmode decode (MMIO default); a firmware/SCMI build may override */ +u8 versal2_get_bootmode(void); #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index 06d144db4f0..c4e88440d64 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -176,21 +176,6 @@ int board_early_init_r(void) return 0; } -static u8 versal2_get_bootmode(void) -{ - u8 bootmode; - u32 reg = 0; - - reg = readl(&crp_base->boot_mode_usr); - - if (reg >> BOOT_MODE_ALT_SHIFT) - reg >>= BOOT_MODE_ALT_SHIFT; - - bootmode = reg & BOOT_MODES_MASK; - - return bootmode; -} - static u32 versal2_multi_boot(void) { u8 bootmode = versal2_get_bootmode(); -- cgit v1.3.1 From b444110e51f09444f55367c18168ef04fcb1b6a2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 Jun 2026 14:53:29 +0200 Subject: arm64: versal: Decouple multiboot register access from firmware versal_multi_boot() in board code selected between the firmware call zynqmp_pm_get_pmc_multi_boot_reg() and a direct readl() based on an IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) check. Generic board code should not carry firmware-specific ifdefs, and this becomes harder to maintain once SCMI introduces yet another access method. Introduce an overridable accessor versal_pmc_multi_boot(). The weak default lives in arch/arm/mach-versal and performs the plain MMIO read (used at EL3 and when no firmware is present). When CONFIG_ZYNQMP_FIRMWARE is enabled, firmware-zynqmp.c provides a strong definition that issues the firmware call, falling back to the direct read at EL3 where the SMC path to firmware is unavailable. The shared MMIO read is factored into versal_multi_boot_reg() so the firmware override does not duplicate it. versal_multi_boot() keeps the generic JTAG/QEMU workaround and simply calls the accessor, so board code no longer references the firmware interface for the multiboot register. The firmware-vs-MMIO decision is selected at link time, and adding SCMI later only requires a third strong definition with no board-code changes. Signed-off-by: Michal Simek Link: https://patch.msgid.link/199ef6a1411c54f154fe4a43b5fef166b9927f7a.1782219202.git.michal.simek@amd.com --- arch/arm/mach-versal/cpu.c | 10 ++++++++++ arch/arm/mach-versal/include/mach/sys_proto.h | 5 +++++ board/xilinx/versal/board.c | 8 +------- drivers/firmware/firmware-zynqmp.c | 11 +++++++++++ 4 files changed, 27 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 7ffd35fe89c..7ad93982e8d 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -110,6 +110,16 @@ int arm_reserve_mmu(void) } #endif +u32 versal_multi_boot_reg(void) +{ + return readl(PMC_MULTI_BOOT_REG) & PMC_MULTI_BOOT_MASK; +} + +u32 __weak versal_pmc_multi_boot(void) +{ + return versal_multi_boot_reg(); +} + U_BOOT_DRVINFO(soc_xilinx_versal) = { .name = "soc_xilinx_versal", }; diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h index b53e616e47b..d7ab2549658 100644 --- a/arch/arm/mach-versal/include/mach/sys_proto.h +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -17,4 +17,9 @@ void initialize_tcm(enum tcm_mode mode); void tcm_init(enum tcm_mode mode); void mem_map_fill(void); +/* Overridable PMC multiboot accessor: weak MMIO default, firmware override */ +u32 versal_pmc_multi_boot(void); +/* Direct MMIO read of the multiboot register (EL3 / no-firmware path) */ +u32 versal_multi_boot_reg(void); + #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 8666f2ceff4..110490b9672 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -62,18 +62,12 @@ static u8 versal_get_bootmode(void) static u32 versal_multi_boot(void) { u8 bootmode = versal_get_bootmode(); - u32 reg = 0; /* Mostly workaround for QEMU CI pipeline */ if (bootmode == JTAG_MODE) return 0; - if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) - reg = zynqmp_pm_get_pmc_multi_boot_reg(); - else - reg = readl(PMC_MULTI_BOOT_REG); - - return reg & PMC_MULTI_BOOT_MASK; + return versal_pmc_multi_boot(); } int board_init(void) diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 70d205ff3ef..c8943b8d23a 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -328,6 +328,17 @@ u32 zynqmp_pm_get_pmc_multi_boot_reg(void) } #endif +#if defined(CONFIG_ARCH_VERSAL) +u32 versal_pmc_multi_boot(void) +{ + /* At EL3 the SMC path to firmware is unavailable, read directly */ + if (current_el() == 3) + return versal_multi_boot_reg(); + + return zynqmp_pm_get_pmc_multi_boot_reg() & PMC_MULTI_BOOT_MASK; +} +#endif + #if defined(CONFIG_ARCH_VERSAL2) u32 versal2_pmc_multi_boot(void) { -- cgit v1.3.1 From 70236dca329910b05bf35b3e05fd460d6e9d2d76 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 Jun 2026 14:53:30 +0200 Subject: arm64: versal: Move bootmode decoding out of board code versal_get_bootmode() lived in board code and open-coded the IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) selection between the firmware call zynqmp_pm_get_bootmode_reg() and a direct readl(). To keep generic board code free of firmware specifics and SoC register details and ready for SCMI, move the whole function, including the alt-shift and mask decoding, behind an overridable hook. The weak versal_get_bootmode() in arch/arm/mach-versal does the plain MMIO read via versal_bootmode_reg() and decodes it (used at EL3 and without firmware). When CONFIG_ZYNQMP_FIRMWARE is enabled, firmware-zynqmp.c provides a strong definition that reads the register through the firmware call, falling back to the direct read at EL3 where the SMC path to firmware is unavailable. This preserves the existing firmware-based bootmode behaviour while removing the firmware interface from board code; the now unused zynqmp_firmware.h include is dropped. Signed-off-by: Michal Simek Link: https://patch.msgid.link/d60073feed8da8d3aff9eabee6ab132e0bbd0f8e.1782219202.git.michal.simek@amd.com --- arch/arm/mach-versal/cpu.c | 15 +++++++++++++++ arch/arm/mach-versal/include/mach/sys_proto.h | 4 ++++ board/xilinx/versal/board.c | 20 -------------------- drivers/firmware/firmware-zynqmp.c | 16 ++++++++++++++++ 4 files changed, 35 insertions(+), 20 deletions(-) diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 7ad93982e8d..5cb013d5f2e 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -120,6 +120,21 @@ u32 __weak versal_pmc_multi_boot(void) return versal_multi_boot_reg(); } +u32 versal_bootmode_reg(void) +{ + return readl(&crp_base->boot_mode_usr); +} + +u8 __weak versal_get_bootmode(void) +{ + u32 reg = versal_bootmode_reg(); + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + return reg & BOOT_MODES_MASK; +} + U_BOOT_DRVINFO(soc_xilinx_versal) = { .name = "soc_xilinx_versal", }; diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h index d7ab2549658..f8836db5ef0 100644 --- a/arch/arm/mach-versal/include/mach/sys_proto.h +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -21,5 +21,9 @@ void mem_map_fill(void); u32 versal_pmc_multi_boot(void); /* Direct MMIO read of the multiboot register (EL3 / no-firmware path) */ u32 versal_multi_boot_reg(void); +/* Overridable bootmode decode: weak MMIO default, firmware override */ +u8 versal_get_bootmode(void); +/* Direct MMIO read of the bootmode register (EL3 / no-firmware path) */ +u32 versal_bootmode_reg(void); #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 110490b9672..d0c15fed1e9 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -28,7 +28,6 @@ #include #include #include -#include #include "../common/board.h" DECLARE_GLOBAL_DATA_PTR; @@ -40,25 +39,6 @@ static xilinx_desc versalpl = { }; #endif -static u8 versal_get_bootmode(void) -{ - u8 bootmode; - u32 reg = 0; - - if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) { - reg = zynqmp_pm_get_bootmode_reg(); - } else { - reg = readl(&crp_base->boot_mode_usr); - } - - if (reg >> BOOT_MODE_ALT_SHIFT) - reg >>= BOOT_MODE_ALT_SHIFT; - - bootmode = reg & BOOT_MODES_MASK; - - return bootmode; -} - static u32 versal_multi_boot(void) { u8 bootmode = versal_get_bootmode(); diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index c8943b8d23a..f3ca0b08762 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -337,6 +337,22 @@ u32 versal_pmc_multi_boot(void) return zynqmp_pm_get_pmc_multi_boot_reg() & PMC_MULTI_BOOT_MASK; } + +u8 versal_get_bootmode(void) +{ + u32 reg; + + /* At EL3 the SMC path to firmware is unavailable, read directly */ + if (current_el() == 3) + reg = versal_bootmode_reg(); + else + reg = zynqmp_pm_get_bootmode_reg(); + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + return reg & BOOT_MODES_MASK; +} #endif #if defined(CONFIG_ARCH_VERSAL2) -- cgit v1.3.1 From 8a2586c3ef8cba7b5ef7a65229f322831f268b7c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 Jun 2026 14:53:31 +0200 Subject: arm64: versal: Move board_early_init_r clock setup to mach code board_early_init_r() programmed the IOU switch clock and the system timestamp counter directly with readl()/writel() in board code. This is SoC register setup rather than board policy, and the same block is duplicated across the Xilinx SoCs. Move it into versal_timer_setup() in arch/arm/mach-versal so the board hook only keeps the EL3 guard and calls the helper. Signed-off-by: Michal Simek Link: https://patch.msgid.link/2234d746ab5b8240e88b1a629d51f93751ee3b60.1782219202.git.michal.simek@amd.com --- arch/arm/mach-versal/cpu.c | 43 +++++++++++++++++++++++++++ arch/arm/mach-versal/include/mach/sys_proto.h | 2 ++ board/xilinx/versal/board.c | 38 +---------------------- 3 files changed, 46 insertions(+), 37 deletions(-) diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 5cb013d5f2e..7521d45bc1a 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -7,6 +7,8 @@ */ #include +#include +#include #include #include #include @@ -120,6 +122,47 @@ u32 __weak versal_pmc_multi_boot(void) return versal_multi_boot_reg(); } +void versal_timer_setup(void) +{ + u32 val; + + debug("iou_switch ctrl div0 %x\n", + readl(&crlapb_base->iou_switch_ctrl)); + + writel(IOU_SWITCH_CTRL_CLKACT_BIT | + (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), + &crlapb_base->iou_switch_ctrl); + + /* Global timer init - Program time stamp reference clk */ + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + debug("ref ctrl 0x%x\n", + readl(&crlapb_base->timestamp_ref_ctrl)); + + /* Clear reset of timestamp reg */ + writel(0, &crlapb_base->rst_timestamp); + + /* + * Program freq register in System counter and + * enable system counter. + */ + writel(CONFIG_COUNTER_FREQUENCY, + &iou_scntr_secure->base_frequency_id_register); + + debug("counter val 0x%x\n", + readl(&iou_scntr_secure->base_frequency_id_register)); + + writel(IOU_SCNTRS_CONTROL_EN, + &iou_scntr_secure->counter_control_register); + + debug("scntrs control 0x%x\n", + readl(&iou_scntr_secure->counter_control_register)); + debug("timer 0x%llx\n", get_ticks()); + debug("timer 0x%llx\n", get_ticks()); +} + u32 versal_bootmode_reg(void) { return readl(&crp_base->boot_mode_usr); diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h index f8836db5ef0..cb373e6fad9 100644 --- a/arch/arm/mach-versal/include/mach/sys_proto.h +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -25,5 +25,7 @@ u32 versal_multi_boot_reg(void); u8 versal_get_bootmode(void); /* Direct MMIO read of the bootmode register (EL3 / no-firmware path) */ u32 versal_bootmode_reg(void); +/* EL3 clock/timer register setup, called from board_early_init_r() */ +void versal_timer_setup(void); #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index d0c15fed1e9..0537517b1b2 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -68,46 +68,10 @@ int board_init(void) int board_early_init_r(void) { - u32 val; - if (current_el() != 3) return 0; - debug("iou_switch ctrl div0 %x\n", - readl(&crlapb_base->iou_switch_ctrl)); - - writel(IOU_SWITCH_CTRL_CLKACT_BIT | - (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), - &crlapb_base->iou_switch_ctrl); - - /* Global timer init - Program time stamp reference clk */ - val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; - writel(val, &crlapb_base->timestamp_ref_ctrl); - - debug("ref ctrl 0x%x\n", - readl(&crlapb_base->timestamp_ref_ctrl)); - - /* Clear reset of timestamp reg */ - writel(0, &crlapb_base->rst_timestamp); - - /* - * Program freq register in System counter and - * enable system counter. - */ - writel(CONFIG_COUNTER_FREQUENCY, - &iou_scntr_secure->base_frequency_id_register); - - debug("counter val 0x%x\n", - readl(&iou_scntr_secure->base_frequency_id_register)); - - writel(IOU_SCNTRS_CONTROL_EN, - &iou_scntr_secure->counter_control_register); - - debug("scntrs control 0x%x\n", - readl(&iou_scntr_secure->counter_control_register)); - debug("timer 0x%llx\n", get_ticks()); - debug("timer 0x%llx\n", get_ticks()); + versal_timer_setup(); return 0; } -- cgit v1.3.1 From ae8f2474fe6aad8dc3cbc0f940bf8643611bc7b7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 Jun 2026 14:53:32 +0200 Subject: arm64: versal2: Move board_early_init_r clock setup to mach code board_early_init_r() programmed the IOU switch clock and the system timestamp counter directly with readl()/writel() in board code. This is SoC register setup rather than board policy, and the same block is duplicated across the Xilinx SoCs. Move it into versal2_timer_setup() in arch/arm/mach-versal2 so the board hook only keeps the EL3 guard and calls the helper. Signed-off-by: Michal Simek Link: https://patch.msgid.link/08e835a183c39de6f666375ac390eee6a8f3f12e.1782219202.git.michal.simek@amd.com --- arch/arm/mach-versal2/cpu.c | 43 ++++++++++++++++++++++++++ arch/arm/mach-versal2/include/mach/sys_proto.h | 2 ++ board/amd/versal2/board.c | 38 +---------------------- 3 files changed, 46 insertions(+), 37 deletions(-) diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c index 2b30a81d250..07bb1a61b17 100644 --- a/arch/arm/mach-versal2/cpu.c +++ b/arch/arm/mach-versal2/cpu.c @@ -7,6 +7,8 @@ */ #include +#include +#include #include #include #include @@ -152,6 +154,47 @@ u8 __weak versal2_get_bootmode(void) return bootmode; } +void versal2_timer_setup(void) +{ + u32 val; + + debug("iou_switch ctrl div0 %x\n", + readl(&crlapb_base->iou_switch_ctrl)); + + writel(IOU_SWITCH_CTRL_CLKACT_BIT | + (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), + &crlapb_base->iou_switch_ctrl); + + /* Global timer init - Program time stamp reference clk */ + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + debug("ref ctrl 0x%x\n", + readl(&crlapb_base->timestamp_ref_ctrl)); + + /* Clear reset of timestamp reg */ + writel(0, &crlapb_base->rst_timestamp); + + /* + * Program freq register in System counter and + * enable system counter. + */ + writel(CONFIG_COUNTER_FREQUENCY, + &iou_scntr_secure->base_frequency_id_register); + + debug("counter val 0x%x\n", + readl(&iou_scntr_secure->base_frequency_id_register)); + + writel(IOU_SCNTRS_CONTROL_EN, + &iou_scntr_secure->counter_control_register); + + debug("scntrs control 0x%x\n", + readl(&iou_scntr_secure->counter_control_register)); + debug("timer 0x%llx\n", get_ticks()); + debug("timer 0x%llx\n", get_ticks()); +} + U_BOOT_DRVINFO(soc_amd_versal2) = { .name = "soc_amd_versal2", }; diff --git a/arch/arm/mach-versal2/include/mach/sys_proto.h b/arch/arm/mach-versal2/include/mach/sys_proto.h index b3118c208e8..b8d12d1dd3b 100644 --- a/arch/arm/mach-versal2/include/mach/sys_proto.h +++ b/arch/arm/mach-versal2/include/mach/sys_proto.h @@ -19,5 +19,7 @@ u32 versal2_pmc_multi_boot(void); u32 versal2_multi_boot_reg(void); /* Weak bootmode decode (MMIO default); a firmware/SCMI build may override */ u8 versal2_get_bootmode(void); +/* EL3 clock/timer register setup, called from board_early_init_r() */ +void versal2_timer_setup(void); #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index c4e88440d64..7f2fb4c1ec6 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -132,46 +132,10 @@ bool soc_detection(void) int board_early_init_r(void) { - u32 val; - if (current_el() != 3) return 0; - debug("iou_switch ctrl div0 %x\n", - readl(&crlapb_base->iou_switch_ctrl)); - - writel(IOU_SWITCH_CTRL_CLKACT_BIT | - (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), - &crlapb_base->iou_switch_ctrl); - - /* Global timer init - Program time stamp reference clk */ - val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; - writel(val, &crlapb_base->timestamp_ref_ctrl); - - debug("ref ctrl 0x%x\n", - readl(&crlapb_base->timestamp_ref_ctrl)); - - /* Clear reset of timestamp reg */ - writel(0, &crlapb_base->rst_timestamp); - - /* - * Program freq register in System counter and - * enable system counter. - */ - writel(CONFIG_COUNTER_FREQUENCY, - &iou_scntr_secure->base_frequency_id_register); - - debug("counter val 0x%x\n", - readl(&iou_scntr_secure->base_frequency_id_register)); - - writel(IOU_SCNTRS_CONTROL_EN, - &iou_scntr_secure->counter_control_register); - - debug("scntrs control 0x%x\n", - readl(&iou_scntr_secure->counter_control_register)); - debug("timer 0x%llx\n", get_ticks()); - debug("timer 0x%llx\n", get_ticks()); + versal2_timer_setup(); return 0; } -- cgit v1.3.1 From d885e802ce8722a4dae77255b7aa16ccaf7976d8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 Jun 2026 14:53:33 +0200 Subject: arm64: versal-net: Move board_early_init_r clock setup to mach code board_early_init_r() programmed the IOU switch clock and the system timestamp counter directly with readl()/writel() in board code. This is SoC register setup rather than board policy, and the same block is duplicated across the Xilinx SoCs. Move it into versal_net_timer_setup() in arch/arm/mach-versal-net so the board hook only keeps the EL3 guard and calls the helper. Signed-off-by: Michal Simek Link: https://patch.msgid.link/10dd9f35d03be0402ce13475f20b2cd3761189a6.1782219202.git.michal.simek@amd.com --- arch/arm/mach-versal-net/cpu.c | 43 +++++++++++++++++++++++ arch/arm/mach-versal-net/include/mach/sys_proto.h | 2 ++ board/xilinx/versal-net/board.c | 38 +------------------- 3 files changed, 46 insertions(+), 37 deletions(-) diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c index 78ead1f45f6..bce66124c47 100644 --- a/arch/arm/mach-versal-net/cpu.c +++ b/arch/arm/mach-versal-net/cpu.c @@ -7,6 +7,8 @@ */ #include +#include +#include #include #include #include @@ -88,6 +90,47 @@ u64 get_page_table_size(void) return 0x14000; } +void versal_net_timer_setup(void) +{ + u32 val; + + debug("iou_switch ctrl div0 %x\n", + readl(&crlapb_base->iou_switch_ctrl)); + + writel(IOU_SWITCH_CTRL_CLKACT_BIT | + (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), + &crlapb_base->iou_switch_ctrl); + + /* Global timer init - Program time stamp reference clk */ + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + debug("ref ctrl 0x%x\n", + readl(&crlapb_base->timestamp_ref_ctrl)); + + /* Clear reset of timestamp reg */ + writel(0, &crlapb_base->rst_timestamp); + + /* + * Program freq register in System counter and + * enable system counter. + */ + writel(CONFIG_COUNTER_FREQUENCY, + &iou_scntr_secure->base_frequency_id_register); + + debug("counter val 0x%x\n", + readl(&iou_scntr_secure->base_frequency_id_register)); + + writel(IOU_SCNTRS_CONTROL_EN, + &iou_scntr_secure->counter_control_register); + + debug("scntrs control 0x%x\n", + readl(&iou_scntr_secure->counter_control_register)); + debug("timer 0x%llx\n", get_ticks()); + debug("timer 0x%llx\n", get_ticks()); +} + U_BOOT_DRVINFO(soc_xilinx_versal_net) = { .name = "soc_xilinx_versal_net", }; diff --git a/arch/arm/mach-versal-net/include/mach/sys_proto.h b/arch/arm/mach-versal-net/include/mach/sys_proto.h index 23374d10a6b..33253ca88bf 100644 --- a/arch/arm/mach-versal-net/include/mach/sys_proto.h +++ b/arch/arm/mach-versal-net/include/mach/sys_proto.h @@ -7,3 +7,5 @@ #include void mem_map_fill(void); +/* EL3 clock/timer register setup, called from board_early_init_r() */ +void versal_net_timer_setup(void); diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index 65b2a451ad7..a40039a1dc8 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -148,46 +148,10 @@ int board_early_init_f(void) int board_early_init_r(void) { - u32 val; - if (current_el() != 3) return 0; - debug("iou_switch ctrl div0 %x\n", - readl(&crlapb_base->iou_switch_ctrl)); - - writel(IOU_SWITCH_CTRL_CLKACT_BIT | - (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), - &crlapb_base->iou_switch_ctrl); - - /* Global timer init - Program time stamp reference clk */ - val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; - writel(val, &crlapb_base->timestamp_ref_ctrl); - - debug("ref ctrl 0x%x\n", - readl(&crlapb_base->timestamp_ref_ctrl)); - - /* Clear reset of timestamp reg */ - writel(0, &crlapb_base->rst_timestamp); - - /* - * Program freq register in System counter and - * enable system counter. - */ - writel(CONFIG_COUNTER_FREQUENCY, - &iou_scntr_secure->base_frequency_id_register); - - debug("counter val 0x%x\n", - readl(&iou_scntr_secure->base_frequency_id_register)); - - writel(IOU_SCNTRS_CONTROL_EN, - &iou_scntr_secure->counter_control_register); - - debug("scntrs control 0x%x\n", - readl(&iou_scntr_secure->counter_control_register)); - debug("timer 0x%llx\n", get_ticks()); - debug("timer 0x%llx\n", get_ticks()); + versal_net_timer_setup(); return 0; } -- cgit v1.3.1 From 722cd61c35444835dbfbd0d2a25b2593eae3fe3f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 Jun 2026 14:53:34 +0200 Subject: arm64: zynqmp: Move board_early_init_r clock setup to mach code board_early_init_r() programmed the system timestamp counter directly with readl()/writel() in board code. This is SoC register setup rather than board policy, and similar code exists across the Xilinx SoCs. Move it into zynqmp_timer_setup() in arch/arm/mach-zynqmp so the board hook only keeps the EL3 guard and calls the helper. The asm/arch/clk.h include (for zynqmp_get_system_timer_freq()) moves to cpu.c along with the code. Signed-off-by: Michal Simek Link: https://patch.msgid.link/2d8f2419fab314b4ff8fd53b846e1dd6151586d3.1782219202.git.michal.simek@amd.com --- arch/arm/mach-zynqmp/cpu.c | 22 ++++++++++++++++++++++ arch/arm/mach-zynqmp/include/mach/sys_proto.h | 2 ++ board/xilinx/zynqmp/zynqmp.c | 18 +----------------- 3 files changed, 25 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 3dc47e5d48e..e6f2e0b3ee0 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -234,6 +235,27 @@ int zynqmp_mmio_read(const u32 address, u32 *value) return ret; } +void zynqmp_timer_setup(void) +{ + u32 val; + + val = readl(&crlapb_base->timestamp_ref_ctrl); + val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; + + if (!val) { + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + /* Program freq register in System counter */ + writel(zynqmp_get_system_timer_freq(), + &iou_scntr_secure->base_frequency_id_register); + /* And enable system counter */ + writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, + &iou_scntr_secure->counter_control_register); + } +} + U_BOOT_DRVINFO(soc_xilinx_zynqmp) = { .name = "soc_xilinx_zynqmp", }; diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index b6a41df1da4..723e7593cf7 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -54,5 +54,7 @@ void mem_map_fill(void); #if defined(CONFIG_DEFINE_TCM_OCM_MMAP) void tcm_init(enum tcm_mode mode); #endif +/* EL3 clock/timer register setup, called from board_early_init_r() */ +void zynqmp_timer_setup(void); #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index a12c039d8c9..5d13881f3ec 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include @@ -214,26 +213,11 @@ int board_init(void) int board_early_init_r(void) { - u32 val; - if (current_el() != 3) return 0; - val = readl(&crlapb_base->timestamp_ref_ctrl); - val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; - - if (!val) { - val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; - writel(val, &crlapb_base->timestamp_ref_ctrl); + zynqmp_timer_setup(); - /* Program freq register in System counter */ - writel(zynqmp_get_system_timer_freq(), - &iou_scntr_secure->base_frequency_id_register); - /* And enable system counter */ - writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, - &iou_scntr_secure->counter_control_register); - } return 0; } -- cgit v1.3.1 From ad911ccef01f023087d1df1e980d6a3b5d940938 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 Jun 2026 14:53:35 +0200 Subject: arm64: versal2: Move SoC detection out of board code soc_detection() and soc_name_decode() read the PMC_TAP version/idcode registers and decode the platform. This is SoC information rather than board policy, and a firmware interface could provide it instead, so it does not belong in board code. Move both functions, together with the shared platform_id and platform_version state, into arch/arm/mach-versal2 where they still override the weak stubs in the Xilinx common board code. The board file drops the now unused linux/bitfield.h include. Signed-off-by: Michal Simek Link: https://patch.msgid.link/c332ab27f66f1c808f32a4bcb453d9e8da543331.1782219202.git.michal.simek@amd.com --- arch/arm/mach-versal2/cpu.c | 75 +++++++++++++++++++++++++++++++++++++++++++++ board/amd/versal2/board.c | 71 ------------------------------------------ 2 files changed, 75 insertions(+), 71 deletions(-) diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c index 07bb1a61b17..6cc6592b0fc 100644 --- a/arch/arm/mach-versal2/cpu.c +++ b/arch/arm/mach-versal2/cpu.c @@ -8,15 +8,21 @@ #include #include +#include #include +#include #include #include #include #include +#include #include #include #include #include +#include +#include +#include "../../../board/xilinx/common/board.h" DECLARE_GLOBAL_DATA_PTR; @@ -195,6 +201,75 @@ void versal2_timer_setup(void) debug("timer 0x%llx\n", get_ticks()); } +static u32 platform_id, platform_version; + +char *soc_name_decode(void) +{ + char *name, *platform_name; + + switch (platform_id) { + case VERSAL2_SPP: + platform_name = "spp"; + break; + case VERSAL2_EMU: + platform_name = "emu"; + break; + case VERSAL2_SPP_MMD: + platform_name = "spp-mmd"; + break; + case VERSAL2_EMU_MMD: + platform_name = "emu-mmd"; + break; + case VERSAL2_QEMU: + platform_name = "qemu"; + break; + default: + return NULL; + } + + /* + * --rev.-el are 9 chars + * max platform name is emu-mmd which is 7 chars + * platform version number are 1+1 + * el is 1 char + * Plus 1 char for NULL byte + */ + name = calloc(1, strlen(CONFIG_SYS_BOARD) + 20); + if (!name) + return NULL; + + sprintf(name, "%s-%s-rev%d.%d-el%d", CONFIG_SYS_BOARD, + platform_name, platform_version / 10, + platform_version % 10, current_el()); + + return name; +} + +bool soc_detection(void) +{ + u32 version, ps_version; + + version = readl(PMC_TAP_VERSION); + platform_id = FIELD_GET(PLATFORM_MASK, version); + ps_version = FIELD_GET(PS_VERSION_MASK, version); + + debug("idcode %x, version %x, usercode %x\n", + readl(PMC_TAP_IDCODE), version, + readl(PMC_TAP_USERCODE)); + + debug("pmc_ver %lx, ps version %x, rtl version %lx\n", + FIELD_GET(PMC_VERSION_MASK, version), + ps_version, + FIELD_GET(RTL_VERSION_MASK, version)); + + platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); + + debug("Platform id: %d version: %d.%d\n", platform_id, + platform_version / 10, platform_version % 10); + + return true; +} + U_BOOT_DRVINFO(soc_amd_versal2) = { .name = "soc_amd_versal2", }; diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index 7f2fb4c1ec6..2afd283b8dd 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -31,8 +31,6 @@ #include #include "../../xilinx/common/board.h" -#include -#include #include #include #include @@ -61,75 +59,6 @@ int board_init(void) return 0; } -static u32 platform_id, platform_version; - -char *soc_name_decode(void) -{ - char *name, *platform_name; - - switch (platform_id) { - case VERSAL2_SPP: - platform_name = "spp"; - break; - case VERSAL2_EMU: - platform_name = "emu"; - break; - case VERSAL2_SPP_MMD: - platform_name = "spp-mmd"; - break; - case VERSAL2_EMU_MMD: - platform_name = "emu-mmd"; - break; - case VERSAL2_QEMU: - platform_name = "qemu"; - break; - default: - return NULL; - } - - /* - * --rev.-el are 9 chars - * max platform name is emu-mmd which is 7 chars - * platform version number are 1+1 - * el is 1 char - * Plus 1 char for NULL byte - */ - name = calloc(1, strlen(CONFIG_SYS_BOARD) + 20); - if (!name) - return NULL; - - sprintf(name, "%s-%s-rev%d.%d-el%d", CONFIG_SYS_BOARD, - platform_name, platform_version / 10, - platform_version % 10, current_el()); - - return name; -} - -bool soc_detection(void) -{ - u32 version, ps_version; - - version = readl(PMC_TAP_VERSION); - platform_id = FIELD_GET(PLATFORM_MASK, version); - ps_version = FIELD_GET(PS_VERSION_MASK, version); - - debug("idcode %x, version %x, usercode %x\n", - readl(PMC_TAP_IDCODE), version, - readl(PMC_TAP_USERCODE)); - - debug("pmc_ver %lx, ps version %x, rtl version %lx\n", - FIELD_GET(PMC_VERSION_MASK, version), - ps_version, - FIELD_GET(RTL_VERSION_MASK, version)); - - platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); - - debug("Platform id: %d version: %d.%d\n", platform_id, - platform_version / 10, platform_version % 10); - - return true; -} - int board_early_init_r(void) { if (current_el() != 3) -- cgit v1.3.1 From 4b3ead85ddf03ccf2eef2b81bdd0e1af34f0f651 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 Jun 2026 14:53:36 +0200 Subject: arm64: versal-net: Move SoC detection out of board code soc_detection() and soc_name_decode() read the PMC_TAP version/idcode registers and decode the platform. This is SoC information rather than board policy, and a firmware interface could provide it instead, so it does not belong in board code. Move both functions, together with the shared platform_id and platform_version state, into arch/arm/mach-versal-net where they still override the weak stubs in the Xilinx common board code. The board file drops the now unused linux/bitfield.h include. Signed-off-by: Michal Simek Link: https://patch.msgid.link/8757111cb254543d61541fb030d51f62c3c555a8.1782219202.git.michal.simek@amd.com --- arch/arm/mach-versal-net/cpu.c | 91 +++++++++++++++++++++++++++++++++++++++++ board/xilinx/versal-net/board.c | 87 --------------------------------------- 2 files changed, 91 insertions(+), 87 deletions(-) diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c index bce66124c47..2974d89f902 100644 --- a/arch/arm/mach-versal-net/cpu.c +++ b/arch/arm/mach-versal-net/cpu.c @@ -8,7 +8,9 @@ #include #include +#include #include +#include #include #include #include @@ -17,6 +19,9 @@ #include #include #include +#include +#include +#include "../../../board/xilinx/common/board.h" DECLARE_GLOBAL_DATA_PTR; @@ -131,6 +136,92 @@ void versal_net_timer_setup(void) debug("timer 0x%llx\n", get_ticks()); } +static u32 platform_id, platform_version; + +char *soc_name_decode(void) +{ + char *name, *platform_name; + + switch (platform_id) { + case VERSAL_NET_SPP: + platform_name = "ipp"; + break; + case VERSAL_NET_EMU: + platform_name = "emu"; + break; + case VERSAL_NET_QEMU: + platform_name = "qemu"; + break; + default: + return NULL; + } + + /* + * --rev. are 6 chars + * max platform name is qemu which is 4 chars + * platform version number are 1+1 + * Plus 1 char for \n + */ + name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13); + if (!name) + return NULL; + + sprintf(name, "%s-%s-rev%d.%d", CONFIG_SYS_BOARD, + platform_name, platform_version / 10, + platform_version % 10); + + return name; +} + +bool soc_detection(void) +{ + u32 version, ps_version; + + version = readl(PMC_TAP_VERSION); + platform_id = FIELD_GET(PLATFORM_MASK, version); + ps_version = FIELD_GET(PS_VERSION_MASK, version); + + debug("idcode %x, version %x, usercode %x\n", + readl(PMC_TAP_IDCODE), version, + readl(PMC_TAP_USERCODE)); + + debug("pmc_ver %lx, ps version %x, rtl version %lx\n", + FIELD_GET(PMC_VERSION_MASK, version), + ps_version, + FIELD_GET(RTL_VERSION_MASK, version)); + + platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); + + if (platform_id == VERSAL_NET_SPP || + platform_id == VERSAL_NET_EMU) { + if (ps_version == PS_VERSION_PRODUCTION) { + /* + * ES1 version ends at 1.9 version where there was +9 + * used because of IPP/SPP conversion. Production + * version have platform_version started from 0 again + * that's why adding +20 to continue with the same line. + * It means the last ES1 version ends at 1.9 version and + * new PRODUCTION line starts at 2.0. + */ + platform_version += 20; + } else { + /* + * 9 is diff for + * 0 means 0.9 version + * 1 means 1.0 version + * 2 means 1.1 version + * etc, + */ + platform_version += 9; + } + } + + debug("Platform id: %d version: %d.%d\n", platform_id, + platform_version / 10, platform_version % 10); + + return true; +} + U_BOOT_DRVINFO(soc_xilinx_versal_net) = { .name = "soc_xilinx_versal_net", }; diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index a40039a1dc8..3c69edc2260 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -25,7 +25,6 @@ #include #include "../common/board.h" -#include #include #include @@ -49,92 +48,6 @@ int board_init(void) return 0; } -static u32 platform_id, platform_version; - -char *soc_name_decode(void) -{ - char *name, *platform_name; - - switch (platform_id) { - case VERSAL_NET_SPP: - platform_name = "ipp"; - break; - case VERSAL_NET_EMU: - platform_name = "emu"; - break; - case VERSAL_NET_QEMU: - platform_name = "qemu"; - break; - default: - return NULL; - } - - /* - * --rev. are 6 chars - * max platform name is qemu which is 4 chars - * platform version number are 1+1 - * Plus 1 char for \n - */ - name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13); - if (!name) - return NULL; - - sprintf(name, "%s-%s-rev%d.%d", CONFIG_SYS_BOARD, - platform_name, platform_version / 10, - platform_version % 10); - - return name; -} - -bool soc_detection(void) -{ - u32 version, ps_version; - - version = readl(PMC_TAP_VERSION); - platform_id = FIELD_GET(PLATFORM_MASK, version); - ps_version = FIELD_GET(PS_VERSION_MASK, version); - - debug("idcode %x, version %x, usercode %x\n", - readl(PMC_TAP_IDCODE), version, - readl(PMC_TAP_USERCODE)); - - debug("pmc_ver %lx, ps version %x, rtl version %lx\n", - FIELD_GET(PMC_VERSION_MASK, version), - ps_version, - FIELD_GET(RTL_VERSION_MASK, version)); - - platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); - - if (platform_id == VERSAL_NET_SPP || - platform_id == VERSAL_NET_EMU) { - if (ps_version == PS_VERSION_PRODUCTION) { - /* - * ES1 version ends at 1.9 version where there was +9 - * used because of IPP/SPP conversion. Production - * version have platform_version started from 0 again - * that's why adding +20 to continue with the same line. - * It means the last ES1 version ends at 1.9 version and - * new PRODUCTION line starts at 2.0. - */ - platform_version += 20; - } else { - /* - * 9 is diff for - * 0 means 0.9 version - * 1 means 1.0 version - * 2 means 1.1 version - * etc, - */ - platform_version += 9; - } - } - - debug("Platform id: %d version: %d.%d\n", platform_id, - platform_version / 10, platform_version % 10); - - return true; -} - int board_early_init_f(void) { if (IS_ENABLED(CONFIG_DEBUG_UART)) { -- cgit v1.3.1 From 9048a9c44d5ffc99a38227df4167d401f7129aae Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 Jun 2026 14:53:37 +0200 Subject: arm64: versal-net: Move bootmode decoding out of board code versal_net_get_bootmode() open-coded the IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) selection between the firmware call zynqmp_pm_get_bootmode_reg() and a direct readl() in board code. Like the Versal change, move the whole function behind an overridable hook so generic board code stays free of firmware specifics and is ready for SCMI. The weak versal_net_get_bootmode() in arch/arm/mach-versal-net does the plain MMIO read via versal_net_bootmode_reg() and decodes it (used at EL3 and without firmware). When CONFIG_ZYNQMP_FIRMWARE is enabled, firmware-zynqmp.c provides a strong definition that reads the register through the firmware call, falling back to the direct read at EL3 where the SMC path to firmware is unavailable. This preserves the existing firmware-based bootmode behaviour while removing the firmware interface from board code; the now unused zynqmp_firmware.h include is dropped. Signed-off-by: Michal Simek Link: https://patch.msgid.link/be67e9c6d0bc36840a46594413886d2003967c64.1782219202.git.michal.simek@amd.com --- arch/arm/mach-versal-net/cpu.c | 15 +++++++++++++++ arch/arm/mach-versal-net/include/mach/sys_proto.h | 4 ++++ board/xilinx/versal-net/board.c | 20 -------------------- drivers/firmware/firmware-zynqmp.c | 18 ++++++++++++++++++ 4 files changed, 37 insertions(+), 20 deletions(-) diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c index 2974d89f902..7df7c49ac71 100644 --- a/arch/arm/mach-versal-net/cpu.c +++ b/arch/arm/mach-versal-net/cpu.c @@ -136,6 +136,21 @@ void versal_net_timer_setup(void) debug("timer 0x%llx\n", get_ticks()); } +u32 versal_net_bootmode_reg(void) +{ + return readl(&crp_base->boot_mode_usr); +} + +u8 __weak versal_net_get_bootmode(void) +{ + u32 reg = versal_net_bootmode_reg(); + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + return reg & BOOT_MODES_MASK; +} + static u32 platform_id, platform_version; char *soc_name_decode(void) diff --git a/arch/arm/mach-versal-net/include/mach/sys_proto.h b/arch/arm/mach-versal-net/include/mach/sys_proto.h index 33253ca88bf..4907dae1108 100644 --- a/arch/arm/mach-versal-net/include/mach/sys_proto.h +++ b/arch/arm/mach-versal-net/include/mach/sys_proto.h @@ -9,3 +9,7 @@ void mem_map_fill(void); /* EL3 clock/timer register setup, called from board_early_init_r() */ void versal_net_timer_setup(void); +/* Overridable bootmode decode: weak MMIO default, firmware override */ +u8 versal_net_get_bootmode(void); +/* Direct MMIO read of the bootmode register (EL3 / no-firmware path) */ +u32 versal_net_bootmode_reg(void); diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index 3c69edc2260..bb099c1e7ca 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include "../common/board.h" @@ -69,25 +68,6 @@ int board_early_init_r(void) return 0; } -static u8 versal_net_get_bootmode(void) -{ - u8 bootmode; - u32 reg = 0; - - if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) { - reg = zynqmp_pm_get_bootmode_reg(); - } else { - reg = readl(&crp_base->boot_mode_usr); - } - - if (reg >> BOOT_MODE_ALT_SHIFT) - reg >>= BOOT_MODE_ALT_SHIFT; - - bootmode = reg & BOOT_MODES_MASK; - - return bootmode; -} - int spi_get_env_dev(void) { struct udevice *dev; diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index f3ca0b08762..4c4f4c19ae4 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -355,6 +355,24 @@ u8 versal_get_bootmode(void) } #endif +#if defined(CONFIG_ARCH_VERSAL_NET) +u8 versal_net_get_bootmode(void) +{ + u32 reg; + + /* At EL3 the SMC path to firmware is unavailable, read directly */ + if (current_el() == 3) + reg = versal_net_bootmode_reg(); + else + reg = zynqmp_pm_get_bootmode_reg(); + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + return reg & BOOT_MODES_MASK; +} +#endif + #if defined(CONFIG_ARCH_VERSAL2) u32 versal2_pmc_multi_boot(void) { -- cgit v1.3.1 From 4b62fc1b7e9e6ead90bbc5a5c9e82b8ee03fbfef Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 Jun 2026 14:53:38 +0200 Subject: arm64: zynqmp: Decouple MMIO accessors from firmware zynqmp_mmio_read() and zynqmp_mmio_write() selected between direct MMIO and the firmware (PM_MMIO_READ/WRITE) interface with an in-function IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) / current_el() check. Generic arch code should not carry firmware-specific ifdefs, and with SCMI the access method changes again. Split the accessors like the multiboot and bootmode hooks: the weak default in arch/arm/mach-zynqmp does the direct MMIO access (used in SPL, at EL3 and when no firmware is present), while firmware-zynqmp.c provides a strong definition that issues the firmware call and falls back to the direct access in SPL/EL3 where the SMC path is unavailable. The raw MMIO primitives zynqmp_mmio_rawread() and zynqmp_mmio_rawwrite() are exported for the shared fallback, and the read-modify-write helper now uses the raw read instead of routing through the firmware-aware accessor. The firmware-vs-MMIO decision is selected at link time, so adding SCMI later only requires a third strong definition with no changes to generic code. Signed-off-by: Michal Simek Link: https://patch.msgid.link/d532df144d2c8e34be835bad6d0de3b26befdf01.1782219202.git.michal.simek@amd.com --- arch/arm/mach-zynqmp/cpu.c | 49 ++++++++------------------- arch/arm/mach-zynqmp/include/mach/sys_proto.h | 3 ++ drivers/firmware/firmware-zynqmp.c | 31 +++++++++++++++++ 3 files changed, 48 insertions(+), 35 deletions(-) diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index e6f2e0b3ee0..088cc962189 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -172,15 +172,19 @@ unsigned int zynqmp_get_silicon_version(void) return ZYNQMP_CSU_VERSION_SILICON; } -static int zynqmp_mmio_rawwrite(const u32 address, - const u32 mask, - const u32 value) +int zynqmp_mmio_rawread(const u32 address, u32 *value) +{ + *value = readl((ulong)address); + return 0; +} + +int zynqmp_mmio_rawwrite(const u32 address, const u32 mask, const u32 value) { u32 data; u32 value_local = value; int ret; - ret = zynqmp_mmio_read(address, &data); + ret = zynqmp_mmio_rawread(address, &data); if (ret) return ret; @@ -191,48 +195,23 @@ static int zynqmp_mmio_rawwrite(const u32 address, return 0; } -static int zynqmp_mmio_rawread(const u32 address, u32 *value) -{ - *value = readl((ulong)address); - return 0; -} - -int zynqmp_mmio_write(const u32 address, - const u32 mask, - const u32 value) +int __weak zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value) { if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) return zynqmp_mmio_rawwrite(address, mask, value); -#if defined(CONFIG_ZYNQMP_FIRMWARE) - else - return xilinx_pm_request(PM_MMIO_WRITE, address, mask, - value, 0, 0, 0, NULL); -#endif return -EINVAL; } -int zynqmp_mmio_read(const u32 address, u32 *value) +int __weak zynqmp_mmio_read(const u32 address, u32 *value) { - u32 ret = -EINVAL; - if (!value) - return ret; - - if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) { - ret = zynqmp_mmio_rawread(address, value); - } -#if defined(CONFIG_ZYNQMP_FIRMWARE) - else { - u32 ret_payload[PAYLOAD_ARG_CNT]; + return -EINVAL; - ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0, - 0, 0, 0, ret_payload); - *value = ret_payload[1]; - } -#endif + if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) + return zynqmp_mmio_rawread(address, value); - return ret; + return -EINVAL; } void zynqmp_timer_setup(void) diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index 723e7593cf7..d2bb10ffcbb 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -56,5 +56,8 @@ void tcm_init(enum tcm_mode mode); #endif /* EL3 clock/timer register setup, called from board_early_init_r() */ void zynqmp_timer_setup(void); +/* Direct MMIO accessors (EL3/SPL or no-firmware path) */ +int zynqmp_mmio_rawread(const u32 address, u32 *value); +int zynqmp_mmio_rawwrite(const u32 address, const u32 mask, const u32 value); #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 4c4f4c19ae4..6052a31b5b4 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -373,6 +373,37 @@ u8 versal_net_get_bootmode(void) } #endif +#if defined(CONFIG_ARCH_ZYNQMP) +int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value) +{ + /* At EL3 or in SPL the firmware (SMC) path is unavailable */ + if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) + return zynqmp_mmio_rawwrite(address, mask, value); + + return xilinx_pm_request(PM_MMIO_WRITE, address, mask, value, + 0, 0, 0, NULL); +} + +int zynqmp_mmio_read(const u32 address, u32 *value) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + if (!value) + return -EINVAL; + + /* At EL3 or in SPL the firmware (SMC) path is unavailable */ + if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) + return zynqmp_mmio_rawread(address, value); + + ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0, 0, 0, 0, + ret_payload); + *value = ret_payload[1]; + + return ret; +} +#endif + #if defined(CONFIG_ARCH_VERSAL2) u32 versal2_pmc_multi_boot(void) { -- cgit v1.3.1 From fb3801be128c9d0bf34a1797141a972b0759cb25 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 Jun 2026 14:53:39 +0200 Subject: arm64: versal-net: Deduplicate SPI bootmode handling spi_get_env_dev() and boot_targets_setup() both decoded the QSPI/OSPI boot modes into a SPI device sequence number with identical uclass_get_device_by_name() lookups. Factor that logic into a single spi_get_bootseq() helper that takes the bootmode and returns the device sequence. spi_get_env_dev() becomes a thin wrapper around it, and boot_targets_setup() calls it for the QSPI/OSPI cases instead of open-coding the lookups. Passing the bootmode in avoids reading the bootmode register twice in boot_targets_setup(). No functional change. Signed-off-by: Michal Simek Link: https://patch.msgid.link/f98037220a20c441f0ea964f94647948bc035997.1782219202.git.michal.simek@amd.com --- board/xilinx/versal-net/board.c | 38 ++++++++++---------------------------- 1 file changed, 10 insertions(+), 28 deletions(-) diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index bb099c1e7ca..5ad8c8d6426 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -68,12 +68,12 @@ int board_early_init_r(void) return 0; } -int spi_get_env_dev(void) +static int spi_get_bootseq(u8 bootmode) { struct udevice *dev; int bootseq = -1; - switch (versal_net_get_bootmode()) { + switch (bootmode) { case QSPI_MODE_24BIT: puts("QSPI_MODE_24\n"); if (uclass_get_device_by_name(UCLASS_SPI, @@ -109,6 +109,11 @@ int spi_get_env_dev(void) return bootseq; } +int spi_get_env_dev(void) +{ + return spi_get_bootseq(versal_net_get_bootmode()); +} + static int boot_targets_setup(void) { u8 bootmode; @@ -133,34 +138,11 @@ static int boot_targets_setup(void) mode = "jtag pxe dhcp"; break; case QSPI_MODE_24BIT: - puts("QSPI_MODE_24\n"); - if (uclass_get_device_by_name(UCLASS_SPI, - "spi@f1030000", &dev)) { - debug("QSPI driver for QSPI device is not present\n"); - break; - } - mode = "xspi"; - bootseq = dev_seq(dev); - break; case QSPI_MODE_32BIT: - puts("QSPI_MODE_32\n"); - if (uclass_get_device_by_name(UCLASS_SPI, - "spi@f1030000", &dev)) { - debug("QSPI driver for QSPI device is not present\n"); - break; - } - mode = "xspi"; - bootseq = dev_seq(dev); - break; case OSPI_MODE: - puts("OSPI_MODE\n"); - if (uclass_get_device_by_name(UCLASS_SPI, - "spi@f1010000", &dev)) { - debug("OSPI driver for OSPI device is not present\n"); - break; - } - mode = "xspi"; - bootseq = dev_seq(dev); + bootseq = spi_get_bootseq(bootmode); + if (bootseq >= 0) + mode = "xspi"; break; case EMMC_MODE: puts("EMMC_MODE\n"); -- cgit v1.3.1 From d9938274747cafa24af47d404e78001396f7fdf0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 Jun 2026 14:53:40 +0200 Subject: arm64: versal-net: Simplify spi_get_bootseq() bootmode switch The QSPI and OSPI cases only differ in the SPI device name. Pick the name in the switch and perform a single uclass_get_device_by_name() lookup afterwards, instead of repeating the lookup and dev_seq() in every case. No functional change. Signed-off-by: Michal Simek Link: https://patch.msgid.link/191f0f583e2d02c184ea2a2a2fe0ef473ca9fe61.1782219202.git.michal.simek@amd.com --- board/xilinx/versal-net/board.c | 33 +++++++++++++-------------------- 1 file changed, 13 insertions(+), 20 deletions(-) diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index 5ad8c8d6426..50dd49927be 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -71,41 +71,34 @@ int board_early_init_r(void) static int spi_get_bootseq(u8 bootmode) { struct udevice *dev; - int bootseq = -1; + const char *name; + int bootseq; switch (bootmode) { case QSPI_MODE_24BIT: puts("QSPI_MODE_24\n"); - if (uclass_get_device_by_name(UCLASS_SPI, - "spi@f1030000", &dev)) { - debug("QSPI driver for QSPI device is not present\n"); - break; - } - bootseq = dev_seq(dev); + name = "spi@f1030000"; break; case QSPI_MODE_32BIT: puts("QSPI_MODE_32\n"); - if (uclass_get_device_by_name(UCLASS_SPI, - "spi@f1030000", &dev)) { - debug("QSPI driver for QSPI device is not present\n"); - break; - } - bootseq = dev_seq(dev); + name = "spi@f1030000"; break; case OSPI_MODE: puts("OSPI_MODE\n"); - if (uclass_get_device_by_name(UCLASS_SPI, - "spi@f1010000", &dev)) { - debug("OSPI driver for OSPI device is not present\n"); - break; - } - bootseq = dev_seq(dev); + name = "spi@f1010000"; break; default: - break; + return -1; } + if (uclass_get_device_by_name(UCLASS_SPI, name, &dev)) { + debug("SPI driver for %s is not present\n", name); + return -1; + } + + bootseq = dev_seq(dev); debug("bootseq %d\n", bootseq); + return bootseq; } -- cgit v1.3.1 From e8f4248fc344b60a153b6163fcdd1c5f6aeb740b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 Jun 2026 14:53:41 +0200 Subject: arm64: versal-net: Do not print bootmode from spi_get_env_dev() spi_get_bootseq() printed the QSPI/OSPI mode banner, which is noise when called from spi_get_env_dev() during environment setup. The banner is only meaningful for the "Bootmode:" announcement in boot_targets_setup(). Make spi_get_bootseq() a pure lookup that returns the banner string through an optional output argument instead of printing it. spi_get_env_dev() passes NULL and stays silent, while boot_targets_setup() prints the returned mode name as before. Signed-off-by: Michal Simek Link: https://patch.msgid.link/ae257af9d2fe026306b32c647e406450319a3c7a.1782219202.git.michal.simek@amd.com --- board/xilinx/versal-net/board.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index 50dd49927be..687d042d106 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -68,7 +68,7 @@ int board_early_init_r(void) return 0; } -static int spi_get_bootseq(u8 bootmode) +static int spi_get_bootseq(u8 bootmode, const char **modename) { struct udevice *dev; const char *name; @@ -76,15 +76,18 @@ static int spi_get_bootseq(u8 bootmode) switch (bootmode) { case QSPI_MODE_24BIT: - puts("QSPI_MODE_24\n"); + if (modename) + *modename = "QSPI_MODE_24\n"; name = "spi@f1030000"; break; case QSPI_MODE_32BIT: - puts("QSPI_MODE_32\n"); + if (modename) + *modename = "QSPI_MODE_32\n"; name = "spi@f1030000"; break; case OSPI_MODE: - puts("OSPI_MODE\n"); + if (modename) + *modename = "OSPI_MODE\n"; name = "spi@f1010000"; break; default: @@ -104,7 +107,7 @@ static int spi_get_bootseq(u8 bootmode) int spi_get_env_dev(void) { - return spi_get_bootseq(versal_net_get_bootmode()); + return spi_get_bootseq(versal_net_get_bootmode(), NULL); } static int boot_targets_setup(void) @@ -115,6 +118,7 @@ static int boot_targets_setup(void) int bootseq_len = 0; int env_targets_len = 0; const char *mode = NULL; + const char *modename = NULL; char *new_targets; char *env_targets; @@ -133,7 +137,9 @@ static int boot_targets_setup(void) case QSPI_MODE_24BIT: case QSPI_MODE_32BIT: case OSPI_MODE: - bootseq = spi_get_bootseq(bootmode); + bootseq = spi_get_bootseq(bootmode, &modename); + if (modename) + puts(modename); if (bootseq >= 0) mode = "xspi"; break; -- cgit v1.3.1 From d18ebbf33950d33d2292bd26b597493b66a2a991 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 Jun 2026 14:53:42 +0200 Subject: arm64: versal-net: Look up eMMC device in boot_targets_setup() The EMMC_MODE case set bootseq from dev_seq(dev) without ever assigning dev, so it used an uninitialized pointer and produced a bogus device sequence in boot_targets. eMMC is wired to the SD1 controller (mmc@f1050000, see versal-net-mini-emmc.dts). Look that device up like the SD cases do before using its sequence number. Signed-off-by: Michal Simek Link: https://patch.msgid.link/bf779dcdd30c900d7614c0fa8382cb3f4cb57c20.1782219202.git.michal.simek@amd.com --- board/xilinx/versal-net/board.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index 687d042d106..9c0490cba98 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -145,6 +145,11 @@ static int boot_targets_setup(void) break; case EMMC_MODE: puts("EMMC_MODE\n"); + if (uclass_get_device_by_name(UCLASS_MMC, + "mmc@f1050000", &dev)) { + debug("eMMC driver for eMMC device is not present\n"); + break; + } mode = "mmc"; bootseq = dev_seq(dev); break; -- cgit v1.3.1 From bbc71f8c28c11fc3fca44371c347b000500509f2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 23 Jun 2026 14:53:43 +0200 Subject: arm64: versal-net: Add mmc_get_env_dev() and deduplicate MMC handling The SD and eMMC cases in boot_targets_setup() duplicated the MMC device lookup, and versal-net relied on the weak mmc_get_env_dev() default instead of selecting the device matching the boot mode (unlike versal and zynqmp). Factor the lookup into mmc_get_bootseq(), mirroring spi_get_bootseq(): it maps the boot mode to the MMC node and returns the device sequence, optionally handing back the mode banner so only boot_targets_setup() prints it. mmc_get_env_dev() is now provided as a thin wrapper, and the SD/eMMC cases call the helper instead of open-coding the lookups. The local udevice pointer in boot_targets_setup() is no longer needed. Signed-off-by: Michal Simek Link: https://patch.msgid.link/7750a79c17146c66adeb83ad6d1bfa78b22ec8fa.1782219202.git.michal.simek@amd.com --- board/xilinx/versal-net/board.c | 80 ++++++++++++++++++++++++----------------- 1 file changed, 47 insertions(+), 33 deletions(-) diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index 9c0490cba98..ddac92660df 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -110,10 +111,48 @@ int spi_get_env_dev(void) return spi_get_bootseq(versal_net_get_bootmode(), NULL); } +static int mmc_get_bootseq(u8 bootmode, const char **modename) +{ + struct udevice *dev; + const char *name; + + switch (bootmode) { + case SD_MODE: + if (modename) + *modename = "SD_MODE\n"; + name = "mmc@f1040000"; + break; + case EMMC_MODE: + if (modename) + *modename = "EMMC_MODE\n"; + name = "mmc@f1050000"; + break; + case SD_MODE1: + case SD1_LSHFT_MODE: + if (modename) + *modename = "SD_MODE1\n"; + name = "mmc@f1050000"; + break; + default: + return -1; + } + + if (uclass_get_device_by_name(UCLASS_MMC, name, &dev)) { + debug("MMC driver for %s is not present\n", name); + return -1; + } + + return dev_seq(dev); +} + +int mmc_get_env_dev(void) +{ + return mmc_get_bootseq(versal_net_get_bootmode(), NULL); +} + static int boot_targets_setup(void) { u8 bootmode; - struct udevice *dev; int bootseq = -1; int bootseq_len = 0; int env_targets_len = 0; @@ -143,45 +182,20 @@ static int boot_targets_setup(void) if (bootseq >= 0) mode = "xspi"; break; - case EMMC_MODE: - puts("EMMC_MODE\n"); - if (uclass_get_device_by_name(UCLASS_MMC, - "mmc@f1050000", &dev)) { - debug("eMMC driver for eMMC device is not present\n"); - break; - } - mode = "mmc"; - bootseq = dev_seq(dev); - break; case SELECTMAP_MODE: puts("SELECTMAP_MODE\n"); break; - case SD_MODE: - puts("SD_MODE\n"); - if (uclass_get_device_by_name(UCLASS_MMC, - "mmc@f1040000", &dev)) { - debug("SD0 driver for SD0 device is not present\n"); - break; - } - debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev)); - - mode = "mmc"; - bootseq = dev_seq(dev); - break; case SD1_LSHFT_MODE: puts("LVL_SHFT_"); fallthrough; + case SD_MODE: + case EMMC_MODE: case SD_MODE1: - puts("SD_MODE1\n"); - if (uclass_get_device_by_name(UCLASS_MMC, - "mmc@f1050000", &dev)) { - debug("SD1 driver for SD1 device is not present\n"); - break; - } - debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev)); - - mode = "mmc"; - bootseq = dev_seq(dev); + bootseq = mmc_get_bootseq(bootmode, &modename); + if (modename) + puts(modename); + if (bootseq >= 0) + mode = "mmc"; break; default: printf("Invalid Boot Mode:0x%x\n", bootmode); -- cgit v1.3.1 From f717b9cf3918aa709af4b44b9ef46759abb9d2e5 Mon Sep 17 00:00:00 2001 From: Harini T Date: Mon, 29 Jun 2026 11:46:33 +0200 Subject: arch: arm: dts: Add RTC clock nodes for ZynqMP platform Add fixed RTC clock nodes at 32.768 kHz for ZynqMP. The RTC driver uses this clock to calculate the calibration value, replacing the deprecated calibration device tree property. Signed-off-by: Harini T Reviewed-by: Tomas Melin Signed-off-by: Michal Simek Link: https://patch.msgid.link/8838c8c4fcd0dfe151bcee2a6c4da51df81e23cb.1782726386.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-clk-ccf.dtsi | 15 ++++++++++++++- arch/arm/dts/zynqmp.dtsi | 1 - 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 482f432ba7f..877962df2b3 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -3,7 +3,7 @@ * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -49,6 +49,14 @@ clock-frequency = <27000000>; clock-output-names = "aux_ref_clk"; }; + + rtc_clk: rtc-clk { + bootph-all; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "rtc_clk"; + }; }; &zynqmp_firmware { @@ -302,3 +310,8 @@ <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ }; + +&rtc { + clocks = <&rtc_clk>; + clock-names = "rtc"; +}; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 13cfca66657..c225eb219f4 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -1006,7 +1006,6 @@ interrupts = , ; interrupt-names = "alarm", "sec"; - calibration = <0x7FFF>; }; sata: ahci@fd0c0000 { -- cgit v1.3.1 From fa1a638e7dc084765eaefc44c7ab376c7d6bd675 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 29 Jun 2026 11:46:34 +0200 Subject: arm64: zynqmp: Disable ina226 iio-hwmon nodes ina226 IIO driver doesn't need to be enabled by default in Linux that's why disable iio-hwmon nodes to avoid warnings about it. Reviewed-by: Tomas Melin Signed-off-by: Michal Simek Link: https://patch.msgid.link/deb2e92d5030a31dbb91b36fa77de3ad2de38a71.1782726386.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 20 ++++++++++++++++++++ arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 6 ++++++ arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 6 ++++++ arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 5 +++++ arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 5 +++++ arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso | 16 ++++++++++++++++ arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso | 16 ++++++++++++++++ arch/arm/dts/zynqmp-zcu100-revC.dts | 2 ++ arch/arm/dts/zynqmp-zcu102-revA.dts | 18 ++++++++++++++++++ arch/arm/dts/zynqmp-zcu104-revC.dts | 1 + arch/arm/dts/zynqmp-zcu106-revA.dts | 18 ++++++++++++++++++ arch/arm/dts/zynqmp-zcu111-revA.dts | 14 ++++++++++++++ arch/arm/dts/zynqmp-zcu208-revA.dts | 14 ++++++++++++++ arch/arm/dts/zynqmp-zcu216-revA.dts | 14 ++++++++++++++ arch/arm/dts/zynqmp-zcu670-revA.dts | 14 ++++++++++++++ arch/arm/dts/zynqmp-zcu670-revB.dts | 14 ++++++++++++++ 16 files changed, 183 insertions(+) diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index aebceb20736..824d189d246 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -51,83 +51,103 @@ ina226-vccint { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vcc-soc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>; }; ina226-vcc-pmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc-pslp { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>; }; ina226-vcc-psfp { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>; }; ina226-vccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>; }; ina226-vccaux-pmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>; }; ina226-vcco-500 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>; }; ina226-vcco-501 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>; }; ina226-vcco-502 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>; }; ina226-vcco-503 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>; }; ina226-vcc-1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>; }; ina226-vcc-3v3 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>; }; ina226-vcc-1v2-ddr4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>; }; ina226-vcc-1v1-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtyavcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>; }; ina226-mgtyavtt { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>; }; ina226-mgtyvccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>; }; }; diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index 7c9764c31f7..bf4ea35067c 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -40,26 +40,32 @@ ina226-u74 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; ina226-u78 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u79 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u82 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>; }; ina226-u84 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; }; diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index f9d7528ff2e..2bf6af9c065 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -45,27 +45,33 @@ ina226-vcc-aux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; ina226-vcc0v6-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>; }; }; diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index b4da0d341c3..fbeae394c62 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -45,22 +45,27 @@ ina226-vcc-aux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index 729efd4098c..33a86fad604 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -45,22 +45,27 @@ ina226-vcc-aux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; diff --git a/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso index 4d0f10e13c3..8bb4dd6e3e7 100644 --- a/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso @@ -18,66 +18,82 @@ ina226-u19 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_soc_ina 0>, <&vcc_soc_ina 1>, <&vcc_soc_ina 2>; }; ina226-u287 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>; }; ina226-u288 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_pslp_ina 0>, <&vcc_pslp_ina 1>, <&vcc_pslp_ina 2>; }; ina226-u289 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>; }; ina226-u290 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccaux_pmc_ina 0>, <&vccaux_pmc_ina 1>, <&vccaux_pmc_ina 2>; }; ina226-u291 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>; }; ina226-u292 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>; }; ina226-u293 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>; }; ina226-u294 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>; }; ina226-u295 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ddr5_rdimm_ina 0>, <&vcc_ddr5_rdimm_ina 1>, <&vcc_ddr5_rdimm_ina 2>; }; ina226-u298 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&lp5_1v0_ina 0>, <&lp5_1v0_ina 1>, <&lp5_1v0_ina 2>; }; ina226-u296 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_fmc_ina 0>, <&vcc_fmc_ina 1>, <&vcc_fmc_ina 2>; }; ina226-u299 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>m_avcc_ina 0>, <>m_avcc_ina 1>, <>m_avcc_ina 2>; }; ina226-u300 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>m_avtt_ina 0>, <>m_avtt_ina 1>, <>m_avtt_ina 2>; }; ina226-u301 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>m_avccaux_ina 0>, <>m_avccaux_ina 1>, <>m_avccaux_ina 2>; }; ina226-u297 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_mipi_ina 0>, <&vcc_mipi_ina 1>, <&vcc_mipi_ina 2>; }; }; diff --git a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso index 5a4e5f09250..39be25be8f6 100644 --- a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso @@ -22,66 +22,82 @@ ina226-u1700 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>; }; ina226-u1732 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_lpd_ina 0>, <&vcc_lpd_ina 1>, <&vcc_lpd_ina 2>; }; ina226-u1733 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>; }; ina226-u1736 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccaux_lpd_ina 0>, <&vccaux_lpd_ina 1>, <&vccaux_lpd_ina 2>; }; ina226-u1737 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>; }; ina226-u1739 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>; }; ina226-u1741 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>; }; ina226-u1743 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>; }; ina226-u1745 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_700_ina 0>, <&vcco_700_ina 1>, <&vcco_700_ina 2>; }; ina226-u1747 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_706_ina 0>, <&vcco_706_ina 1>, <&vcco_706_ina 2>; }; ina226-u1750 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>yp_avcc_ina 0>, <>yp_avcc_ina 1>, <>yp_avcc_ina 2>; }; ina226-u1752 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>yp_avtt_ina 0>, <>yp_avtt_ina 1>, <>yp_avtt_ina 2>; }; ina226-u1754 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>yp_avccaux_ina 0>, <>yp_avccaux_ina 1>, <>yp_avccaux_ina 2>; }; ina226-u1756 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>m_avcc_ina 0>, <>m_avcc_ina 1>, <>m_avcc_ina 2>; }; ina226-u1758 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>m_avtt_ina 0>, <>m_avtt_ina 1>, <>m_avtt_ina 2>; }; ina226-u1760 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>m_avccaux_ina 0>, <>m_avccaux_ina 1>, <>m_avccaux_ina 2>; }; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 62f94da334d..81353b60b38 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -76,6 +76,7 @@ iio-hwmon { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, @@ -135,6 +136,7 @@ ina226 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index a0ef866a259..4d5f4754171 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -83,74 +83,92 @@ ina226-u76 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 0caedc40a51..0f1b1fd92a7 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -60,6 +60,7 @@ ina226 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; }; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index c0bc46faee4..ad76159084e 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -83,74 +83,92 @@ ina226-u76 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index f38edd6145f..a9a47360237 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -83,58 +83,72 @@ ina226-u67 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; }; ina226-u59 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; }; ina226-u61 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u60 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u64 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; ina226-u69 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; }; ina226-u66 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; }; ina226-u65 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u63 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u3 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; }; ina226-u71 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; }; ina226-u77 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u73 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; }; ina226-u79 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 3c3c94dcadf..60231d7d3a2 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -81,61 +81,75 @@ ina226-vccint { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index b0f0a74f711..bfe6f97a760 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -81,61 +81,75 @@ ina226-vccint { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts b/arch/arm/dts/zynqmp-zcu670-revA.dts index c5b70972ef5..08e88745477 100644 --- a/arch/arm/dts/zynqmp-zcu670-revA.dts +++ b/arch/arm/dts/zynqmp-zcu670-revA.dts @@ -84,61 +84,75 @@ ina226-vccint { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts b/arch/arm/dts/zynqmp-zcu670-revB.dts index cd96a7a0d13..5c9195239f1 100644 --- a/arch/arm/dts/zynqmp-zcu670-revB.dts +++ b/arch/arm/dts/zynqmp-zcu670-revB.dts @@ -84,61 +84,75 @@ ina226-vccint { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; -- cgit v1.3.1 From ad1d2c9d20fc543dbe6ff1621a295f780ed70cff Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 29 Jun 2026 11:46:35 +0200 Subject: arm64: xilinx: Add missing newline in kr260-revA Add missing newline available in Linux already. Reviewed-by: Tomas Melin Signed-off-by: Michal Simek Link: https://patch.msgid.link/ab6f006ee87efb54ee17f24a12c9f31aafc2f2ae.1782726386.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index 2bc28b7baf8..31b3c3582c2 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -66,6 +66,7 @@ #clock-cells = <0>; clock-frequency = <25000000>; }; + dpcon { compatible = "dp-connector"; label = "P11"; -- cgit v1.3.1 From 34c89c840c33dd154746ebdc9bbf2e4f3614d292 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 29 Jun 2026 11:46:36 +0200 Subject: arm: dts: zynqmp: Fix space indentation to use tabs Fix indentation issues where spaces were used instead of tabs in several ZynqMP device tree overlay files. Device tree files should use tabs for indentation to maintain consistency with the kernel coding style. Reviewed-by: Tomas Melin Signed-off-by: Michal Simek Link: https://patch.msgid.link/0dc7b65ebd48676719ace15a505ecec2f324822a.1782726386.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso | 4 +-- arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 40 +++++++++++++------------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso index 8bb4dd6e3e7..58be0e1c890 100644 --- a/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP VM-P-M1369-00 * - * Copyright (C) 2024, Advanced Micro Devices, Inc. + * Copyright (C) 2024-2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -409,7 +409,7 @@ }; /* connected via J425 connector - ucd90320: power-sequencer@73 { // u16 + ucd90320: power-sequencer@73 { // u16 compatible = "ti,ucd90320"; reg = <0x73>; };*/ diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index 3c551f30315..967548744d5 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -246,23 +246,23 @@ status = "okay"; pinctrl_gpio0_default: gpio0-default { - conf { - groups = "gpio0_38_grp"; - bias-pull-up; - power-source = ; - }; - - mux { - groups = "gpio0_38_grp"; - function = "gpio0"; - }; - - conf-tx { - pins = "MIO38"; - bias-disable; - output-enable; - }; - }; + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = ; + }; + + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; + + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; pinctrl_uart1_default: uart1-default { conf { @@ -421,9 +421,9 @@ }; &gpio { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio0_default>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; }; &uart1 { -- cgit v1.3.1