From 2a5f7fd30c19c6be5a1717cb81586c7bea12594a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 9 Dec 2022 13:56:37 +0100 Subject: arm64: zynqmp: Sync #dma-cells property location Sync property location with Linux kernel done by Linux commit (1ff2d58e60c8093e9be935b1f191341c0cda957a). Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/e09ad90ea610a81528ef5ecbc931bc9791b1c653.1670590595.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index b210bc4b87e..9434c48e4f5 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -280,10 +280,10 @@ interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware PD_GDMA>; - #dma-cells = <1>; }; fpd_dma_chan2: dma-controller@fd510000 { @@ -293,10 +293,10 @@ interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware PD_GDMA>; - #dma-cells = <1>; }; fpd_dma_chan3: dma-controller@fd520000 { @@ -306,10 +306,10 @@ interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware PD_GDMA>; - #dma-cells = <1>; }; fpd_dma_chan4: dma-controller@fd530000 { @@ -319,10 +319,10 @@ interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware PD_GDMA>; - #dma-cells = <1>; }; fpd_dma_chan5: dma-controller@fd540000 { @@ -332,10 +332,10 @@ interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware PD_GDMA>; - #dma-cells = <1>; }; fpd_dma_chan6: dma-controller@fd550000 { @@ -345,10 +345,10 @@ interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware PD_GDMA>; - #dma-cells = <1>; }; fpd_dma_chan7: dma-controller@fd560000 { @@ -358,10 +358,10 @@ interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware PD_GDMA>; - #dma-cells = <1>; }; fpd_dma_chan8: dma-controller@fd570000 { @@ -371,10 +371,10 @@ interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware PD_GDMA>; - #dma-cells = <1>; }; gic: interrupt-controller@f9010000 { @@ -411,10 +411,10 @@ interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; iommus = <&smmu 0x868>; power-domains = <&zynqmp_firmware PD_ADMA>; - #dma-cells = <1>; }; lpd_dma_chan2: dma-controller@ffa90000 { @@ -424,10 +424,10 @@ interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; iommus = <&smmu 0x869>; power-domains = <&zynqmp_firmware PD_ADMA>; - #dma-cells = <1>; }; lpd_dma_chan3: dma-controller@ffaa0000 { @@ -437,10 +437,10 @@ interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; iommus = <&smmu 0x86a>; power-domains = <&zynqmp_firmware PD_ADMA>; - #dma-cells = <1>; }; lpd_dma_chan4: dma-controller@ffab0000 { @@ -450,10 +450,10 @@ interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; iommus = <&smmu 0x86b>; power-domains = <&zynqmp_firmware PD_ADMA>; - #dma-cells = <1>; }; lpd_dma_chan5: dma-controller@ffac0000 { @@ -463,10 +463,10 @@ interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; iommus = <&smmu 0x86c>; power-domains = <&zynqmp_firmware PD_ADMA>; - #dma-cells = <1>; }; lpd_dma_chan6: dma-controller@ffad0000 { @@ -476,10 +476,10 @@ interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; iommus = <&smmu 0x86d>; power-domains = <&zynqmp_firmware PD_ADMA>; - #dma-cells = <1>; }; lpd_dma_chan7: dma-controller@ffae0000 { @@ -489,10 +489,10 @@ interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; iommus = <&smmu 0x86e>; power-domains = <&zynqmp_firmware PD_ADMA>; - #dma-cells = <1>; }; lpd_dma_chan8: dma-controller@ffaf0000 { @@ -502,10 +502,10 @@ interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; iommus = <&smmu 0x86f>; power-domains = <&zynqmp_firmware PD_ADMA>; - #dma-cells = <1>; }; mc: memory-controller@fd070000 { -- cgit v1.3.1 From e6a01d5102c3e9a577b423d1ccebe20b1ef3a92e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 9 Dec 2022 13:56:38 +0100 Subject: arm64: zynqmp: Added GEM reset definitions The Cadence GEM/MACB driver now utilizes the platform-level reset on the ZynqMP platform. Add reset definitions to the ZynqMP platform device tree to allow this to be used. Linux upstream commit (e461bd6f43f4e568f7436a8b6bc21c4ce6914c36). Signed-off-by: Robert Hancock Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/14e3637735dbc626659e96d142f04a63398362f8.1670590595.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 9434c48e4f5..e2eb27b3151 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -540,6 +540,7 @@ iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; + reset-names = "gem0_rst"; }; gem1: ethernet@ff0c0000 { @@ -554,6 +555,7 @@ iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; + reset-names = "gem1_rst"; }; gem2: ethernet@ff0d0000 { @@ -568,6 +570,7 @@ iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; + reset-names = "gem2_rst"; }; gem3: ethernet@ff0e0000 { @@ -582,6 +585,7 @@ iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; + reset-names = "gem3_rst"; }; gpio: gpio@ff0a0000 { -- cgit v1.3.1 From 8dfdb6958b3727ca90cc9eb373e3969ff3f65f91 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 9 Dec 2022 13:56:39 +0100 Subject: arm64: zynqmp: Fix AMS device tree node Aligned node description with the Linux kernel. Node has been added by kernel commit (271c1fa01c2307cf74f4656390d6299991119c3e). Signed-off-by: Robert Hancock Signed-off-by: Michal Simek Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/74188b64cf615100345d058e026cb0d2de0e089b.1670590595.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index e2eb27b3151..4e1113db1a7 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -938,21 +938,23 @@ interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; reg-names = "ams-base"; - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; #io-channel-cells = <1>; - ranges; + ranges = <0 0 0xffa50800 0x800>; - ams_ps: ams_ps@ffa50800 { + ams_ps: ams_ps@0 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; - reg = <0x0 0xffa50800 0x0 0x400>; + reg = <0x0 0x400>; }; - ams_pl: ams_pl@ffa50c00 { + ams_pl: ams_pl@400 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; - reg = <0x0 0xffa50c00 0x0 0x400>; + reg = <0x400 0x400>; + #address-cells = <1>; + #size-cells = <0>; }; }; -- cgit v1.3.1 From b1d3e7fd9a33ff14561a09d7eb23451af5a7e9d6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 9 Dec 2022 13:56:40 +0100 Subject: arm64: zynqmp: Align gpio-key node names with dtschema MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). It is based on kernel commit (228e8a88b1915a2b467c83d8d0976605f1272fae). Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/ae23999097553acb21dfca9288a913bb8b24587a.1670590595.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sm-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu100-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu106-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu111-revA.dts | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index bae24aabdbd..aafaaec3f1c 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -53,7 +53,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - fwuen { + key-fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; linux,code = ; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 5e7bc7384fc..eea703ab67e 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -49,7 +49,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw4 { + switch-4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 9d8e551ed27..d78bfb8987f 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -47,7 +47,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw19 { + switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 4858b4d1f5e..266c24e4125 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -47,7 +47,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw19 { + switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 2e95f22c3f0..8535cc08913 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -47,7 +47,7 @@ gpio-keys { compatible = "gpio-keys"; autorepeat; - sw19 { + switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; -- cgit v1.3.1 From a30a3ec888a6c2364da7c990ab16b3b74fe38b15 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 9 Dec 2022 13:56:41 +0100 Subject: arm64: zynqmp: Remove id from usb node name There is no reason to have number in usb node name. This is also sync up patch with upstream kernel. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/7b13db34031af88a5738d2ec2e05d2498ea8c869.1670590595.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 4e1113db1a7..34504a8cbb9 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -846,7 +846,7 @@ power-domains = <&zynqmp_firmware PD_UART_1>; }; - usb0: usb0@ff9d0000 { + usb0: usb@ff9d0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; @@ -879,7 +879,7 @@ }; }; - usb1: usb1@ff9e0000 { + usb1: usb@ff9e0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; -- cgit v1.3.1 From 4b422a12df73aacd961318b99072470e5b15755e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 9 Dec 2022 16:19:29 +0100 Subject: net: zynq_gem: Add support for new compatible str with xlnx prefix cdns prefix was deprecated and replaced by xlnx one. Acked-by: Krzysztof Kozlowski Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/7d1312d741349451b36558baa3e9132247303992.1670599167.git.michal.simek@amd.com --- drivers/net/zynq_gem.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 507b19b7597..fe98bcfb2b6 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -821,7 +821,8 @@ static int zynq_gem_probe(struct udevice *dev) if (priv->interface == PHY_INTERFACE_MODE_SGMII && phy.dev) { if (IS_ENABLED(CONFIG_DM_ETH_PHY)) { - if (device_is_compatible(dev, "cdns,zynqmp-gem")) { + if (device_is_compatible(dev, "cdns,zynqmp-gem") || + device_is_compatible(dev, "xlnx,zynqmp-gem")) { ret = gem_zynqmp_set_dynamic_config(dev); if (ret) { dev_err @@ -922,8 +923,11 @@ static int zynq_gem_of_to_plat(struct udevice *dev) } static const struct udevice_id zynq_gem_ids[] = { + { .compatible = "xlnx,versal-gem", .data = RXCLK_EN }, { .compatible = "cdns,versal-gem", .data = RXCLK_EN }, + { .compatible = "xlnx,zynqmp-gem" }, { .compatible = "cdns,zynqmp-gem" }, + { .compatible = "xlnx,zynq-gem" }, { .compatible = "cdns,zynq-gem" }, { .compatible = "cdns,gem" }, { } -- cgit v1.3.1 From ef440787dab9998cf07278e1940bdf750a12d5f8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 12 Dec 2022 15:06:13 +0100 Subject: arm64: zynqmp: Remove unused USB DT properties xlnx,usb-polarity, xlnx,usb-reset-mode and snps,mask_phy_reset are not documented in dt binding and also there is no code associated with them that's why remove them. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/369139fafa1745252ef687e31aebf6bcc2080a32.1670853972.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-dlc21-revA.dts | 4 ---- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 2 -- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 4 ---- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 4 ---- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 4 ---- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 4 ---- 6 files changed, 22 deletions(-) diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts index 0461219ca3e..bf0d89a5fcb 100644 --- a/arch/arm/dts/zynqmp-dlc21-revA.dts +++ b/arch/arm/dts/zynqmp-dlc21-revA.dts @@ -154,8 +154,6 @@ &usb0 { status = "okay"; - xlnx,usb-polarity = <0>; - xlnx,usb-reset-mode = <0>; }; &dwc3_0 { @@ -170,8 +168,6 @@ &usb1 { status = "disabled"; /* Any unknown issue with USB-C */ - xlnx,usb-polarity = <0>; - xlnx,usb-reset-mode = <0>; }; &dwc3_1 { diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index e00428351cb..02d2427809d 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -303,8 +303,6 @@ &usb0 { /* USB0 MIO52-63 */ status = "okay"; - xlnx,usb-polarity = <0>; - xlnx,usb-reset-mode = <0>; }; &dwc3_0 { diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 1fa023ffb13..2d7fe592c8f 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -461,8 +461,6 @@ &usb0 { status = "okay"; - xlnx,usb-polarity = <0>; - xlnx,usb-reset-mode = <0>; }; &dwc3_0 { @@ -474,8 +472,6 @@ &usb1 { status = "disabled"; /* not at mem board */ - xlnx,usb-polarity = <0>; - xlnx,usb-reset-mode = <0>; }; &dwc3_1 { diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index 2271a6a4906..e46748d32c0 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -463,8 +463,6 @@ &usb0 { status = "okay"; - xlnx,usb-polarity = <0>; - xlnx,usb-reset-mode = <0>; }; &dwc3_0 { @@ -476,8 +474,6 @@ &usb1 { status = "disabled"; /* not at mem board */ - xlnx,usb-polarity = <0>; - xlnx,usb-reset-mode = <0>; }; &dwc3_1 { diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index a89046a818f..f564817e2c8 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -457,8 +457,6 @@ &usb0 { status = "okay"; - xlnx,usb-polarity = <0>; - xlnx,usb-reset-mode = <0>; }; &dwc3_0 { @@ -470,8 +468,6 @@ &usb1 { status = "disabled"; /* not at mem board */ - xlnx,usb-polarity = <0>; - xlnx,usb-reset-mode = <0>; }; &dwc3_1 { diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index b3fe42faeee..d63deb83e3c 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -543,8 +543,6 @@ &usb0 { status = "okay"; - xlnx,usb-polarity = <0>; - xlnx,usb-reset-mode = <0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; @@ -559,8 +557,6 @@ &usb1 { status = "okay"; - xlnx,usb-polarity = <0>; - xlnx,usb-reset-mode = <0>; }; &dwc3_1 { -- cgit v1.3.1 From 4664a63cc7365dc48f0ba682cc3a194b19a13842 Mon Sep 17 00:00:00 2001 From: Harini Katakam Date: Mon, 12 Dec 2022 15:14:17 +0100 Subject: arm64: zynqmp: Describe TI phy as ethernet phy ID on ZCU102 RevB & up TI phy requires a reset before PHY address detection to make sure correct strapping via MIO is detected. Facilitate the same using ethernet-phy-id compatible string. GPIO reset entry will be added in a separate commit. This support is present in RevA but needs to be extended to RevB/1.0/1.1 versions which are built on top. Fixes: 13622c7a9dfa ("arm64: zynqmp: Describe TI phy as ethernet-phy-id") Signed-off-by: Harini Katakam Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/6d500a83a787316353d4b26c75d1b51d29e3730e.1670854455.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-zcu102-revB.dts | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index 2422558b748..b2f0b113317 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -16,16 +16,20 @@ &gem3 { phy-handle = <&phyc>; - phyc: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ + mdio: mdio { + phyc: ethernet-phy@c { + #phy-cells = <0x1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ + }; + /* Cleanup from RevA */ + /delete-node/ ethernet-phy@21; }; - /* Cleanup from RevA */ - /delete-node/ ethernet-phy@21; }; /* Fix collision with u61 */ -- cgit v1.3.1 From fd5f2718d3fd8e4ce8bbfbae085f432875fc4bdd Mon Sep 17 00:00:00 2001 From: Harini Katakam Date: Mon, 12 Dec 2022 15:14:18 +0100 Subject: arm64: zynqmp: Enable TI phy reset via GPIO Add DT property to support reset of TI PHY connected to GEM. This is present in RevA DT but needs to be extended RevB/1.0/1.1 versions which are built on top. Fixes: 2b1db7b18c97 ("arm64: zynqmp: Wire GEM reset gpio") Signed-off-by: Harini Katakam Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/7b093616ddea269043cbbb1e3806644d5a4b23be.1670854455.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-zcu102-revB.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index b2f0b113317..de3b5ab9d93 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -25,7 +25,7 @@ ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; - /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; /* Cleanup from RevA */ /delete-node/ ethernet-phy@21; -- cgit v1.3.1 From 67ac851488a1314e7410917b1abdc35400787f40 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 12 Dec 2022 15:27:40 +0100 Subject: arm64: zynqmp: Remove unused snps,refclk_fladj property The commit c55ac51a550c ("usb: dwc3: Program GFLADJ") hopefully fixed issues around fladj logic. This DT property was used in Xilinx stack only that's why remove because it is not needed anymore. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/9bdbd1156b19e28cdebeca29149268b0579a8b6a.1670855257.git.michal.simek@amd.com --- arch/arm/dts/zynqmp.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 34504a8cbb9..0a06c73390b 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -870,7 +870,6 @@ interrupts = <0 65 4>, <0 69 4>, <0 75 4>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; - snps,refclk_fladj; clock-names = "ref"; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; @@ -902,7 +901,6 @@ interrupts = <0 70 4>, <0 74 4>, <0 76 4>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; - snps,refclk_fladj; clock-names = "ref"; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; -- cgit v1.3.1 From e72023c490668299cbab3a8d5f100cbdf0d6124d Mon Sep 17 00:00:00 2001 From: Victor Lim Date: Mon, 9 Jan 2023 15:49:43 -0800 Subject: mtd: spi-nor-ids: add gigadevice part # adding gigadevice part numbers Signed-off-by: Victor Lim Link: https://lore.kernel.org/r/20230109234946.14540-2-vlim@gigadevice.com Signed-off-by: Michal Simek --- drivers/mtd/spi/spi-nor-ids.c | 68 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 5f8f3ec955d..f97e10da876 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -118,6 +118,36 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + /* adding these 3V QSPI flash parts */ + {INFO("gd25b256", 0xc84019, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES) }, + {INFO("gd25b512", 0xc8471A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55b01g", 0xc8471B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55b02g", 0xc8471C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25f64", 0xc84317, 0, 64 * 1024, 128, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, + {INFO("gd25f128", 0xc84318, 0, 64 * 1024, 256, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, + {INFO("gd25f256", 0xc84319, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55f512", 0xc8431A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25t512", 0xc8461A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55t01g", 0xc8461B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55t02g", 0xc8461C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + /* adding these 3V OSPI flash parts */ + {INFO("gd25x512", 0xc8481A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + {INFO("gd55x01g", 0xc8481B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + {INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, { INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | @@ -128,10 +158,48 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + /* adding these 1.8V QSPI flash parts */ + {INFO("gd25lb256", 0xc86719, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lb512", 0xc8671A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lb01g", 0xc8671B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lb02g", 0xc8671C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lf80", 0xc86314, 0, 64 * 1024, 16, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, + {INFO("gd25lf16", 0xc86315, 0, 64 * 1024, 32, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, + {INFO("gd25lf32", 0xc86316, 0, 64 * 1024, 64, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, + {INFO("gd25lf64", 0xc86317, 0, 64 * 1024, 128, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, + {INFO("gd25lf128", 0xc86318, 0, 64 * 1024, 256, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, + {INFO("gd25lf255", 0xc86319, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lf511", 0xc8631A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lt256", 0xc86619, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lt512", 0xc8661A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lt01g", 0xc8661B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lt02g", 0xc8661C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, + /* adding these 1.8V OSPI flash parts */ + {INFO("gd25lx512", 0xc8681A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lx01g", 0xc8681B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lx02g", 0xc8681C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ -- cgit v1.3.1 From a2478acdbcca0e92eab6b37779ca7feea4eff126 Mon Sep 17 00:00:00 2001 From: Victor Lim Date: Mon, 9 Jan 2023 15:49:44 -0800 Subject: configs: zynq: enable gigadevice enabling gigadevice in the related files Signed-off-by: Victor Lim Link: https://lore.kernel.org/r/20230109234946.14540-3-vlim@gigadevice.com Signed-off-by: Michal Simek --- configs/xilinx_zynq_virt_defconfig | 1 + configs/zynq_cse_qspi_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 610d9de2a63..0ae771da817 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -119,6 +119,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ZYNQ=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SF_DEFAULT_SPEED=30000000 +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index c623caf5648..bebbb3435f1 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -82,6 +82,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y # CONFIG_MMC is not set CONFIG_SF_DEFAULT_SPEED=30000000 +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y -- cgit v1.3.1 From be44bf6305256756d309dc0716eff6e2b9c7d2ad Mon Sep 17 00:00:00 2001 From: Victor Lim Date: Mon, 9 Jan 2023 15:49:45 -0800 Subject: arm64: zynqmp: enable gigadevice enabling gigadevice in the related files Signed-off-by: Victor Lim Link: https://lore.kernel.org/r/20230109234946.14540-4-vlim@gigadevice.com Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_mini_qspi_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index 6861f739808..7ef62dbcdab 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -79,6 +79,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y # CONFIG_MMC is not set # CONFIG_SPI_FLASH_SMART_HWCAPS is not set # CONFIG_SPI_FLASH_UNLOCK_ALL is not set +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index ab2a5426518..c40490a9f80 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -159,6 +159,7 @@ CONFIG_NAND_ARASAN=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SYS_NAND_MAX_CHIPS=2 CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y -- cgit v1.3.1 From 3800958a6f0a3092a02c8049fce28c2d86e3ac8e Mon Sep 17 00:00:00 2001 From: Victor Lim Date: Mon, 9 Jan 2023 15:49:46 -0800 Subject: xilinx: versal: enable gigadevice enabling gigadevice in the related files Signed-off-by: Victor Lim Link: https://lore.kernel.org/r/20230109234946.14540-5-vlim@gigadevice.com Signed-off-by: Michal Simek --- configs/xilinx_versal_mini_qspi_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig index 9ca9b7e68ad..11aff80f14f 100644 --- a/configs/xilinx_versal_mini_qspi_defconfig +++ b/configs/xilinx_versal_mini_qspi_defconfig @@ -62,6 +62,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 # CONFIG_SPI_FLASH_SMART_HWCAPS is not set # CONFIG_SPI_FLASH_UNLOCK_ALL is not set +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y -- cgit v1.3.1 From 66b39c1a8c7d56db35db0571b1d84518c948b5af Mon Sep 17 00:00:00 2001 From: Luca Ceresoli Date: Wed, 11 Jan 2023 09:25:54 +0100 Subject: arm64: zynqmp: remove Avnet UltraZed-EV Starter Kit Nobody seems interested and able to keep this board supported, and xilinx_zynqmp_virt_defconfig is supposed to be enough for any zynqmp board. See the discussion at: https://lore.kernel.org/u-boot/CAPnjgZ3hHbyiFf=_Lp-Wz_XOWBkV-3vK4Q3xp=7bcERw-spNpA@mail.gmail.com/T/#m76d726f1ab3f7074c8105c9a2af2110ac7d18708 Signed-off-by: Luca Ceresoli Link: https://lore.kernel.org/r/20230111082554.1930782-1-luca.ceresoli@bootlin.com Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 - ...vnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts | 59 -- arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi | 56 -- board/xilinx/zynqmp/MAINTAINERS | 6 - .../psu_init_gpl.c | 655 --------------------- ...ltrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig | 83 --- 6 files changed, 860 deletions(-) delete mode 100644 arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts delete mode 100644 arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi delete mode 100644 board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c delete mode 100644 configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b3baaf48290..79bec315a2a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -336,7 +336,6 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zybo-z7.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ avnet-ultra96-rev1.dtb \ - avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \ zynqmp-a2197-revA.dtb \ zynqmp-dlc21-revA.dtb \ zynqmp-e-a2197-00-revA.dtb \ diff --git a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts deleted file mode 100644 index 6d1448e8697..00000000000 --- a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 - -/* - * UltraZed-EV Carrier Card v1 (based on the UltraZed-EV SoM) - * http://ultrazed.org/product/ultrazed-ev-carrier-card - */ - -/dts-v1/; - -#include "avnet-ultrazedev-som-v1.0.dtsi" - -/ { - model = "Avnet UltraZed EV Carrier Card v1.0"; - compatible = "avnet,ultrazedev-cc-v1.0-ultrazedev-som-v1.0", - "xlnx,zynqmp"; - chosen { - stdout-path = "serial0:115200n8"; - }; - aliases { - ethernet0 = &gem3; - nvmem0 = &eeprom; - serial0 = &uart0; - }; -}; - -&uart0 { - device_type = "serial"; - status = "okay"; -}; - -&i2c_cc { - /* Microchip 24AA025E48T-I/OT: 2K I2C Serial EEPROM with EUI-48 */ - eeprom: eeprom@51 { - compatible = "atmel,24c02"; - reg = <0x51>; - }; - - /* IDT Versa Clock 5P49V5935B */ - vc5: clock-generator@6a { - compatible = "idt,5p49v5935"; - reg = <0x6a>; - #clock-cells = <1>; - }; -}; - -/* Ethernet RJ-45 */ -&gem3 { - status = "okay"; -}; - -/* microSD card slot */ -&sdhci1 { - status = "okay"; - xlnx,mio-bank = <1>; - clock-frequency = <199998000>; - max-frequency = <50000000>; - no-1-8-v; - disable-wp; -}; diff --git a/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi b/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi deleted file mode 100644 index cbcb290a5c8..00000000000 --- a/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 - -/* - * UltraZed-EV SoM v1 - * http://ultrazed.org/product/ultrazed-ev - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" - -/ { - model = "Avnet UltraZed EV SoM v1.0"; - compatible = "avnet,ultrazedev-som-v1.0", "xlnx,zynqmp"; - memory { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>, /* 2 GB @ offset 0 */ - <0x8 0x0 0x0 0x80000000>; /* 2 GB @ offset 32GB */ - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - - i2cswitch@70 { - compatible = "nxp,pca9543"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - /* I2C connected to Carrier Card via JX3A1/JX3C1 */ - i2c_cc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -/* Marvell 88E1512-A0-NNP2I000 Ethernet PHY */ -&gem3 { - phy-mode = "rgmii-id"; - phy-handle = <&gem3phy>; - gem3phy: ethernet-phy@0 { - reg = <0>; - }; -}; - -/* Micron MTFC8GAKAJCN-4M 8 GB eMMC */ -&sdhci0 { - status = "okay"; - xlnx,mio-bank = <0>; - clock-frequency = <199998000>; -}; diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS index 07b91b81c95..a4527f8959a 100644 --- a/board/xilinx/zynqmp/MAINTAINERS +++ b/board/xilinx/zynqmp/MAINTAINERS @@ -9,9 +9,3 @@ F: board/xilinx/zynqmp/ F: include/configs/xilinx_zynqmp* F: configs/xilinx_zynqmp* F: configs/avnet_ultra96_rev1_defconfig - -ARM ZYNQMP AVNET ULTRAZED EV BOARD -M: Luca Ceresoli -S: Maintained -F: arch/arm/dts/avnet-ultrazedev-* -F: configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig diff --git a/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c b/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c deleted file mode 100644 index d030e79770c..00000000000 --- a/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c +++ /dev/null @@ -1,655 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (c) Copyright 2015 Xilinx, Inc. All rights reserved. - */ - -#include -#include - -static unsigned long psu_pll_init_data(void) -{ - psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U); - psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); - mask_poll(0xFF5E0040, 0x00000002U); - psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); - psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U); - psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U); - psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); - mask_poll(0xFF5E0040, 0x00000001U); - psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014200U); - psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000001U); - psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); - psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014800U); - psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000002U); - psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); - psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U); - psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U); - psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); - mask_poll(0xFD1A0044, 0x00000004U); - psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); - psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); - - return 1; -} - -static unsigned long psu_clock_init_data(void) -{ - psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U); - psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); - psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); - psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U); - psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); - psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010602U); - psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010602U); - psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U); - psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); - psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); - psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); - psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); - psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); - psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U); - psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); - psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); - psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U); - psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U); - psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U); - psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); - psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); - psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); - psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000303U); - psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); - psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); - psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); - - return 1; -} - -static unsigned long psu_ddr_init_data(void) -{ - psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); - psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U); - psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); - psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U); - psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); - psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); - psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00409410U); - psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); - psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); - psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); - psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x009280D2U); - psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); - psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); - psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); - psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0048051FU); - psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020126U); - psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); - psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002705U); - psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09340301U); - psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00280200U); - psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); - psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); - psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); - psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); - psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); - psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x131C2813U); - psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041CU); - psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0808050FU); - psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); - psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U); - psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); - psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); - psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); - psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x05050D08U); - psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002040CU); - psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1308010EU); - psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); - psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); - psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201C9C2U); - psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048C820DU); - psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); - psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); - psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); - psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); - psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); - psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); - psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000A0BU); - psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); - psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); - psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U); - psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); - psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U); - psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); - psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U); - psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U); - psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); - psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F08U); - psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U); - psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U); - psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U); - psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U); - psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); - psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); - psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); - psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); - psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); - psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); - psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); - psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); - psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); - psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); - psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); - psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); - psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); - psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); - psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); - psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); - psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); - psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); - psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); - psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); - psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); - psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); - psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); - psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); - psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); - psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F12090U); - psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); - psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); - psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x4B025810U); - psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xEA601518U); - psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x000E0000U); - psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); - psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000DDU); - psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); - psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x08261009U); - psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28380008U); - psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U); - psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); - psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01A42B08U); - psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00371009U); - psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00001010U); - psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); - psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); - psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000300U); - psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000834U); - psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); - psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000028U); - psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); - psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); - psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); - psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); - psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); - psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); - psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); - psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); - psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); - psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); - psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); - psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); - psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); - psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); - psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); - psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); - psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); - psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); - psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); - psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AEA58U); - psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); - psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); - psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); - psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); - psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU); - psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU); - psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU); - psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU); - psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U); - psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU); - psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU); - psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U); - psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU); - psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); - psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); - psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U); - psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); - psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU); - psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); - psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); - psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); - psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); - psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U); - psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU); - psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); - psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x000E0000U); - psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x000E0000U); - psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x000E0000U); - psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); - psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x000E0000U); - psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); - psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); - psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); - psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x200E0000U); - psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); - psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); - psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); - psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x000E0000U); - psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); - - return 1; -} - -static unsigned long psu_ddr_qos_init_data(void) -{ - return 1; -} - -static unsigned long psu_mio_init_data(void) -{ - psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180060, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180064, 0x000000FEU, 0x00000040U); - psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U); - psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U); - psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U); - psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U); - psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180080, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180084, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); - psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); - psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); - psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); - psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50000000U); - psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02006U); - psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); - psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); - psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); - psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); - - return 1; -} - -static unsigned long psu_peripherals_pre_init_data(void) -{ - psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); - - return 1; -} - -static unsigned long psu_peripherals_init_data(void) -{ - psu_mask_write(0xFD1A0100, 0x000F807EU, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); - psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); - psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); - psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U); - psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U); - psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U); - psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U); - psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U); - psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); - psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); - psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U); - psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); - psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); - psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); - psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); - psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); - psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); - psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); - psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); - - mask_delay(1); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); - - mask_delay(5); - psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); - psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000020U); - psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000020U); - psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U); - mask_delay(1); - psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0000U); - mask_delay(5); - - return 1; -} - -static unsigned long psu_afi_config(void) -{ - psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); - psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); - psu_mask_write(0xFD615000, 0x00000F00U, 0x00000A00U); - - return 1; -} - -static unsigned long psu_ddr_phybringup_data(void) -{ - unsigned int regval = 0; - unsigned int pll_retry = 10; - unsigned int pll_locked = 0; - - while ((pll_retry > 0) && (!pll_locked)) { - Xil_Out32(0xFD080004, 0x00040010); - Xil_Out32(0xFD080004, 0x00040011); - - while ((Xil_In32(0xFD080030) & 0x1) != 1) - ; - pll_locked = (Xil_In32(0xFD080030) & 0x80000000) - >> 31; - pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) - >> 16; - pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) - >> 16; - pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) - >> 16; - pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) - >> 16; - pll_retry--; - } - Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); - if (!pll_locked) - return 0; - - Xil_Out32(0xFD080004U, 0x00040063U); - - while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) - ; - prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); - - while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) - ; - Xil_Out32(0xFD0701B0U, 0x00000001U); - Xil_Out32(0xFD070320U, 0x00000001U); - while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) - ; - prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); - Xil_Out32(0xFD080004, 0x0004FE01); - regval = Xil_In32(0xFD080030); - while (regval != 0x80000FFF) - regval = Xil_In32(0xFD080030); - regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); - if (regval != 0) - return 0; - - Xil_Out32(0xFD080200U, 0x100091C7U); - int cur_R006_tREFPRD; - - cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; - prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); - - prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); - prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); - prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); - - Xil_Out32(0xFD080004, 0x00060001); - regval = Xil_In32(0xFD080030); - while ((regval & 0x80004001) != 0x80004001) - regval = Xil_In32(0xFD080030); - - prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); - prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); - prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); - - Xil_Out32(0xFD080200U, 0x800091C7U); - prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); - - Xil_Out32(0xFD080004, 0x0000C001); - regval = Xil_In32(0xFD080030); - while ((regval & 0x80000C01) != 0x80000C01) - regval = Xil_In32(0xFD080030); - - Xil_Out32(0xFD070180U, 0x01000040U); - Xil_Out32(0xFD070060U, 0x00000000U); - prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); - - return 1; -} - -static void init_peripheral(void) -{ - psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU); -} - -int psu_init(void) -{ - int status = 1; - - status &= psu_mio_init_data(); - status &= psu_peripherals_pre_init_data(); - status &= psu_pll_init_data(); - status &= psu_clock_init_data(); - status &= psu_ddr_init_data(); - status &= psu_ddr_phybringup_data(); - status &= psu_peripherals_init_data(); - init_peripheral(); - - status &= psu_afi_config(); - psu_ddr_qos_init_data(); - - if (status == 0) - return 1; - return 0; -} diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig deleted file mode 100644 index 0a3d710a8b1..00000000000 --- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig +++ /dev/null @@ -1,83 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_LEN=0x4008000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0" -CONFIG_SPL=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI=y -CONFIG_SYS_LOAD_ADDR=0x8000000 -CONFIG_DEBUG_UART=y -CONFIG_SYS_MEMTEST_START=0x00000000 -CONFIG_SYS_MEMTEST_END=0x00001000 -CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8000000 -CONFIG_REMAKE_ELF=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000 -CONFIG_BOOTDELAY=0 -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_CLOCKS=y -CONFIG_SPL_MAX_SIZE=0x40000 -CONFIG_SPL_BSS_MAX_SIZE=0x80000 -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_STACK=0xfffffffc -CONFIG_SYS_SPL_MALLOC=y -CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y -CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x20000000 -CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 -CONFIG_SPL_FS_LOAD_KERNEL_NAME="atf-uboot.ub" -CONFIG_SPL_FS_LOAD_ARGS_NAME="u-boot.bin" -CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_SPL_ARGS_ADDR=0x8000000 -CONFIG_SYS_MAXARGS=64 -CONFIG_SYS_PBSIZE=2073 -CONFIG_SYS_BOOTM_LEN=0x6400000 -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SPI=y -CONFIG_BOOTP_MAY_FAIL=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_CLK_ZYNQMP=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ARM_DCC=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_PANIC_HANG=y -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y -- cgit v1.3.1 From 537ca0bee6e6ffd83926521e03c90bbc42cf65e2 Mon Sep 17 00:00:00 2001 From: Neal Frager Date: Wed, 21 Dec 2022 07:54:46 +0000 Subject: makefile: add multi_dtb_fit dep With certain gcc compilers, the u-boot.itb is built immediately after dtb generation. If CONFIG_MULTI_DTB_FIT is used, it is possible that the fit-dtb.blob is not finished in time. This patch adds a necessary dependency to guarantee that the fit-dtb.blob is built before attempting to build the u-boot.itb. Signed-off-by: Neal Frager Reviewed-by: Simon Glass Link: https://lore.kernel.org/r/20221221075446.47141-1-neal.frager@amd.com Signed-off-by: Michal Simek --- Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile b/Makefile index a4a14d5d35a..b23bdc54406 100644 --- a/Makefile +++ b/Makefile @@ -1449,6 +1449,7 @@ MKIMAGEFLAGS_u-boot.itb += -B 0x8 ifdef U_BOOT_ITS u-boot.itb: u-boot-nodtb.bin \ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SANDBOX),dts/dt.dtb) \ + $(if $(CONFIG_MULTI_DTB_FIT),$(FINAL_DTB_CONTAINER)) \ $(U_BOOT_ITS) FORCE $(call if_changed,mkfitimage) $(BOARD_SIZE_CHECK) -- cgit v1.3.1 From 2732035da9d7e4792a4705c5f81d09dc58de9c29 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 19 Dec 2022 16:26:59 +0100 Subject: board: presidio-asic: Remove CONFIG_TARGET_VENUS Symbol is not defined anywhere that's why remove it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/e34404488b2b46cbb2a10c1663e809ff34287a66.1671463617.git.michal.simek@amd.com --- board/cortina/presidio-asic/lowlevel_init.S | 2 -- 1 file changed, 2 deletions(-) diff --git a/board/cortina/presidio-asic/lowlevel_init.S b/board/cortina/presidio-asic/lowlevel_init.S index 8d8842ebedf..220ec79e87e 100644 --- a/board/cortina/presidio-asic/lowlevel_init.S +++ b/board/cortina/presidio-asic/lowlevel_init.S @@ -34,10 +34,8 @@ skip_smp_setup: #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) branch_if_slave x0, 1f -#ifndef CONFIG_TARGET_VENUS ldr x0, =GICD_BASE bl gic_init_secure -#endif 1: #if defined(CONFIG_GICV3) ldr x0, =GICR_BASE -- cgit v1.3.1 From 29b58bba91147c3c03dcb998a1efe4a4d026d7e1 Mon Sep 17 00:00:00 2001 From: Jay Buddhabhatti Date: Tue, 10 Jan 2023 08:23:44 +0100 Subject: clk: versal: Return error in case if clock setup failed Currently probe is getting success even if clock setup is failed because of that u-boot is trying to access invalid clocks. So return error if clock setup failed. Signed-off-by: Jay Buddhabhatti Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/fa78e71211e5f68f8dc1353b357f96e6283f65a8.1673335422.git.michal.simek@amd.com --- drivers/clk/clk_versal.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 76fde00491b..faebbab1c6d 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -657,7 +657,9 @@ static int versal_clk_probe(struct udevice *dev) if (ret < 0) return -EINVAL; - versal_clock_setup(); + ret = versal_clock_setup(); + if (ret < 0) + return ret; priv->clk = clock; -- cgit v1.3.1 From 724379d9afc850de2767094987a761f096af7718 Mon Sep 17 00:00:00 2001 From: Ashok Reddy Soma Date: Tue, 10 Jan 2023 08:44:07 +0100 Subject: xilinx: versal-net: Add support for timer and start it Add support for starting timer by setting up time stamp generator registers. This is done only for EL3 i.e. mini U-Boot case. For other cases, it will be done TF-A. Add COUNTER_FREQUENCY and IOU_SWITCH_DIVISOR0 to Kconfig so that they can be tuned as required. Signed-off-by: Ashok Reddy Soma Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/fcd8b0dc4b45a11f5e753afff42f84738ac813da.1673336645.git.michal.simek@amd.com --- arch/arm/mach-versal-net/Kconfig | 12 +++++++ arch/arm/mach-versal-net/include/mach/hardware.h | 30 +++++++++++++++++ board/xilinx/versal-net/board.c | 41 ++++++++++++++++++++++++ configs/xilinx_versal_net_mini_defconfig | 1 + configs/xilinx_versal_net_virt_defconfig | 1 + 5 files changed, 85 insertions(+) diff --git a/arch/arm/mach-versal-net/Kconfig b/arch/arm/mach-versal-net/Kconfig index 62825e189fe..edff5b039e9 100644 --- a/arch/arm/mach-versal-net/Kconfig +++ b/arch/arm/mach-versal-net/Kconfig @@ -21,6 +21,18 @@ config SYS_CONFIG_NAME Based on this option include/configs/.h header will be used for board configuration. +config COUNTER_FREQUENCY + int "Timer clock frequency" + default 0 + help + Setup time clock frequency for certain platform + +config IOU_SWITCH_DIVISOR0 + hex "IOU switch divisor0" + default 0x20 + help + Setup time clock divisor for input clock. + config SYS_MEM_RSVD_FOR_MMU bool "Reserve memory for MMU Table" help diff --git a/arch/arm/mach-versal-net/include/mach/hardware.h b/arch/arm/mach-versal-net/include/mach/hardware.h index 808ce48fd14..c5e4e22040e 100644 --- a/arch/arm/mach-versal-net/include/mach/hardware.h +++ b/arch/arm/mach-versal-net/include/mach/hardware.h @@ -8,6 +8,36 @@ #include #endif +struct crlapb_regs { + u32 reserved0[67]; + u32 cpu_r5_ctrl; + u32 reserved; + u32 iou_switch_ctrl; /* 0x114 */ + u32 reserved1[13]; + u32 timestamp_ref_ctrl; /* 0x14c */ + u32 reserved3[108]; + u32 rst_cpu_r5; + u32 reserved2[17]; + u32 rst_timestamp; /* 0x348 */ +}; + +struct iou_scntrs_regs { + u32 counter_control_register; /* 0x0 */ + u32 reserved0[7]; + u32 base_frequency_id_register; /* 0x20 */ +}; + +#define VERSAL_NET_CRL_APB_BASEADDR 0xEB5E0000 +#define VERSAL_NET_IOU_SCNTR_SECURE 0xEC920000 + +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT BIT(25) +#define IOU_SWITCH_CTRL_CLKACT_BIT BIT(25) +#define IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 +#define IOU_SCNTRS_CONTROL_EN 1 + +#define crlapb_base ((struct crlapb_regs *)VERSAL_NET_CRL_APB_BASEADDR) +#define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_NET_IOU_SCNTR_SECURE) + #define PMC_TAP 0xF11A0000 #define PMC_TAP_IDCODE (PMC_TAP + 0) diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index 760031927f7..5fb71107ddc 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -121,6 +121,47 @@ int board_early_init_f(void) int board_early_init_r(void) { + u32 val; + + if (current_el() != 3) + return 0; + + debug("iou_switch ctrl div0 %x\n", + readl(&crlapb_base->iou_switch_ctrl)); + + writel(IOU_SWITCH_CTRL_CLKACT_BIT | + (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), + &crlapb_base->iou_switch_ctrl); + + /* Global timer init - Program time stamp reference clk */ + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + debug("ref ctrl 0x%x\n", + readl(&crlapb_base->timestamp_ref_ctrl)); + + /* Clear reset of timestamp reg */ + writel(0, &crlapb_base->rst_timestamp); + + /* + * Program freq register in System counter and + * enable system counter. + */ + writel(CONFIG_COUNTER_FREQUENCY, + &iou_scntr_secure->base_frequency_id_register); + + debug("counter val 0x%x\n", + readl(&iou_scntr_secure->base_frequency_id_register)); + + writel(IOU_SCNTRS_CONTROL_EN, + &iou_scntr_secure->counter_control_register); + + debug("scntrs control 0x%x\n", + readl(&iou_scntr_secure->counter_control_register)); + debug("timer 0x%llx\n", get_ticks()); + debug("timer 0x%llx\n", get_ticks()); + return 0; } diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig index c5fa431a8c9..5bad1791964 100644 --- a/configs/xilinx_versal_net_mini_defconfig +++ b/configs/xilinx_versal_net_mini_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="xilinx_versal_net_mini" CONFIG_SYS_ICACHE_OFF=y # CONFIG_ARM64_CRC32 is not set +CONFIG_COUNTER_FREQUENCY=100000000 # CONFIG_ARM64_SUPPORT_AARCH32 is not set CONFIG_ARCH_VERSAL_NET=y CONFIG_TEXT_BASE=0xBBF10000 diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 2fdf99f7cbb..729c6ad4503 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_COUNTER_FREQUENCY=100000000 CONFIG_POSITION_INDEPENDENT=y CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 CONFIG_ARCH_VERSAL_NET=y -- cgit v1.3.1 From 8174cd21163a4bc1095a50b6ac1a08a37f366c92 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 6 Jan 2023 09:38:52 +0100 Subject: xilinx: common: Add support for partial string match in board_fit_config_name_match() Board name in FIT image can use U-Boot regular expressions SLRE to instruct U-Boot to handle all revisions for certain board. For example when name (description property) is saying "zynqmp-zcu104-revA" only description with this name is selected. When zynqmp-zcu104.* is described then all board revisions will be handled by this fragment. Xilinx normally have some board revisions which are SW compatible to each other. That's why make sense to define board name with revisions first follow by generic description with '.*' at the end like this: config_1 { description = "zynqmp-zcu104-rev[AB]"; fdt = "zynqmp-zcu104-revA"; }; config_2 { description = "zynqmp-zcu104.*"; fdt = "zynqmp-zcu104-revC"; }; Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/d67683a3c5d0435a5070e622f7a9a38e19c64cf5.1672994329.git.michal.simek@amd.com --- board/xilinx/common/board.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 59d87f23520..823d703ea93 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -1,7 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2014 - 2020 Xilinx, Inc. - * Michal Simek + * (C) Copyright 2014 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek */ #include @@ -22,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -468,6 +471,21 @@ int __maybe_unused board_fit_config_name_match(const char *name) { debug("%s: Check %s, default %s\n", __func__, name, board_name); +#if !defined(CONFIG_SPL_BUILD) + if (CONFIG_IS_ENABLED(REGEX)) { + struct slre slre; + int ret; + + ret = slre_compile(&slre, name); + if (ret) { + ret = slre_match(&slre, board_name, strlen(board_name), + NULL); + debug("%s: name match ret = %d\n", __func__, ret); + return !ret; + } + } +#endif + if (!strcmp(name, board_name)) return 0; -- cgit v1.3.1 From 988b3fa08da197e97363f4caff37a6568dfc07fc Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 18 Jan 2023 09:25:26 +0100 Subject: soc: zynqmp: Fix IDcode for xck24 ID code was added by commit ddf8deabc39d ("arm64: zynqmp: Add support for SVD devices") based on documentation but after receiving part new ID code came up. That's why fix IDcode to match xck24 module. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/7b39aeeec211458ba4132a10beb7ad295eedb87f.1674030324.git.michal.simek@amd.com --- drivers/soc/soc_xilinx_zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index a51bcdb478f..afa277f6049 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -186,7 +186,7 @@ static const struct zynqmp_device zynqmp_devices[] = { .variants = ZYNQMP_VARIANT_DR, }, { - .id = 0x04714093, + .id = 0x04712093, .device = 24, .variants = 0, }, -- cgit v1.3.1 From 36c9f4ad12f0d739fac32ff6162ad3f42edd2876 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 18 Jan 2023 12:12:57 +0100 Subject: arm64: zynqmp: Remove xilinx_zynqmp_mini_emmc/qspi.h configs The commit eaf6ea6a1dc1 ("Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.h") moved custom init stack pointer address to Kconfig which ends up in situation that xilinx_zynqmp_mini_emmc/qspi.h are not needed anymore. That's why remove files and move defconfigs directly to xilinx_zynqmp_mini.h configuration. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/61ae40cf63aabd08adb386c870d3392b0b606fc9.1674040373.git.michal.simek@amd.com --- configs/xilinx_zynqmp_mini_defconfig | 2 +- configs/xilinx_zynqmp_mini_emmc0_defconfig | 2 +- configs/xilinx_zynqmp_mini_emmc1_defconfig | 2 +- configs/xilinx_zynqmp_mini_qspi_defconfig | 2 +- include/configs/xilinx_zynqmp_mini_emmc.h | 15 --------------- include/configs/xilinx_zynqmp_mini_qspi.h | 15 --------------- 6 files changed, 4 insertions(+), 34 deletions(-) delete mode 100644 include/configs/xilinx_zynqmp_mini_emmc.h delete mode 100644 include/configs/xilinx_zynqmp_mini_qspi.h diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index d8b3aab94f1..9680d9b1c2f 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -1,5 +1,5 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_qspi" +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini" CONFIG_SYS_ICACHE_OFF=y CONFIG_ARCH_ZYNQMP=y CONFIG_TEXT_BASE=0xFFFC0000 diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index a1ee98dfc25..93aaa9304b3 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -1,5 +1,5 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc" +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini" CONFIG_SYS_ICACHE_OFF=y CONFIG_ARCH_ZYNQMP=y CONFIG_TEXT_BASE=0x10000 diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index 88c95d4ce2a..81ea67acedb 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -1,5 +1,5 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc" +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini" CONFIG_SYS_ICACHE_OFF=y CONFIG_ARCH_ZYNQMP=y CONFIG_TEXT_BASE=0x10000 diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index 7ef62dbcdab..046cbcf30b6 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -1,5 +1,5 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_qspi" +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini" CONFIG_SYS_ICACHE_OFF=y CONFIG_ARCH_ZYNQMP=y CONFIG_TEXT_BASE=0xFFFC0000 diff --git a/include/configs/xilinx_zynqmp_mini_emmc.h b/include/configs/xilinx_zynqmp_mini_emmc.h deleted file mode 100644 index f423ddd08ec..00000000000 --- a/include/configs/xilinx_zynqmp_mini_emmc.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Xilinx ZynqMP eMMC Flash utility - * - * (C) Copyright 2018 Xilinx, Inc. - * Michal Simek - * Siva Durga Prasad Paladugu - */ - -#ifndef __CONFIG_ZYNQMP_MINI_EMMC_H -#define __CONFIG_ZYNQMP_MINI_EMMC_H - -#include - -#endif /* __CONFIG_ZYNQMP_MINI_EMMC_H */ diff --git a/include/configs/xilinx_zynqmp_mini_qspi.h b/include/configs/xilinx_zynqmp_mini_qspi.h deleted file mode 100644 index 5bea1c9908c..00000000000 --- a/include/configs/xilinx_zynqmp_mini_qspi.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Xilinx ZynqMP QSPI Flash utility - * - * (C) Copyright 2018 Xilinx, Inc. - * Michal Simek - * Siva Durga Prasad Paladugu - */ - -#ifndef __CONFIG_ZYNQMP_MINI_QSPI_H -#define __CONFIG_ZYNQMP_MINI_QSPI_H - -#include - -#endif /* __CONFIG_ZYNQMP_MINI_QSPI_H */ -- cgit v1.3.1 From 00ce57e4b948c07095dada9704ef05a60e4b4bff Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 18 Jan 2023 12:26:43 +0100 Subject: arm64: versal: Remove xilinx_versal_mini_qspi.h configs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The commit eaf6ea6a1dc1 ("Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.h") moved custom init stack pointer address to Kconfig which ends up in situation that xilinx_versal_mini_qspi.h is not needed anymore. That's why remove the file and move defconfigs directly to xilinx_versal_mini.h configuration. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/2d7276ab8d4cb1d245b64287fb59c79325513f22.1674041200.git.michal.simek@amd.com --- configs/xilinx_versal_mini_defconfig | 2 +- configs/xilinx_versal_mini_ospi_defconfig | 2 +- configs/xilinx_versal_mini_qspi_defconfig | 2 +- include/configs/xilinx_versal_mini_qspi.h | 15 --------------- 4 files changed, 3 insertions(+), 18 deletions(-) delete mode 100644 include/configs/xilinx_versal_mini_qspi.h diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig index 3c5ab01aa9e..463aee410ef 100644 --- a/configs/xilinx_versal_mini_defconfig +++ b/configs/xilinx_versal_mini_defconfig @@ -1,5 +1,5 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini_qspi" +CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini" CONFIG_SYS_ICACHE_OFF=y CONFIG_COUNTER_FREQUENCY=100000000 CONFIG_ARCH_VERSAL=y diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig index abcd20ba857..f9fdf61747d 100644 --- a/configs/xilinx_versal_mini_ospi_defconfig +++ b/configs/xilinx_versal_mini_ospi_defconfig @@ -1,5 +1,5 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini_qspi" +CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini" CONFIG_COUNTER_FREQUENCY=100000000 CONFIG_ARCH_VERSAL=y CONFIG_TEXT_BASE=0xFFFC0000 diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig index 11aff80f14f..9fc3eb69e7e 100644 --- a/configs/xilinx_versal_mini_qspi_defconfig +++ b/configs/xilinx_versal_mini_qspi_defconfig @@ -1,5 +1,5 @@ CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini_qspi" +CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini" CONFIG_COUNTER_FREQUENCY=100000000 CONFIG_ARCH_VERSAL=y CONFIG_TEXT_BASE=0xFFFC0000 diff --git a/include/configs/xilinx_versal_mini_qspi.h b/include/configs/xilinx_versal_mini_qspi.h deleted file mode 100644 index e2f2df29354..00000000000 --- a/include/configs/xilinx_versal_mini_qspi.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Configuration for Xilinx Versal QSPI Flash utility - * - * (C) Copyright 2018-2019 Xilinx, Inc. - * Michal Simek - * Siva Durga Prasad Paladugu - */ - -#ifndef __CONFIG_VERSAL_MINI_QSPI_H -#define __CONFIG_VERSAL_MINI_QSPI_H - -#include - -#endif /* __CONFIG_VERSAL_MINI_QSPI_H */ -- cgit v1.3.1 From 8489b6d2e3d174a20af75d7f58ba11a59c2e2ff7 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 18 Jan 2023 13:04:14 +0100 Subject: arm64: zynqmp: Fill model name for SOM CCs When U-Boot do DTB reselection origin model for SOM is used and from log it is not visible if DTB was switched or not. That's why add model directly to CC (carrier card) to show new model if reselection was successful. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/49ba1007218496c48d287454e84a5b8c08abc692.1674043452.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 1 + arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 1 + arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 1 + arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts index 735c1e3d1a8..83c65029c75 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts @@ -18,6 +18,7 @@ &{/} { compatible = "xlnx,zynqmp-sk-kr260-revA", "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; + model = "ZynqMP KR260 revA"; ina260-u14 { compatible = "iio-hwmon"; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts index 63590619d43..f41a2f830ca 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts @@ -18,6 +18,7 @@ &{/} { compatible = "xlnx,zynqmp-sk-kr260-revB", "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; + model = "ZynqMP KR260 revB"; ina260-u14 { compatible = "iio-hwmon"; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts index b714bd3eb1b..0be5b29c051 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts @@ -25,6 +25,7 @@ "xlnx,zynqmp-sk-kv260-revY", "xlnx,zynqmp-sk-kv260-revZ", "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; + model = "ZynqMP KV260 revA"; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index a1d8f9f0e51..fca57a6d91e 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -19,6 +19,7 @@ compatible = "xlnx,zynqmp-sk-kv260-rev1", "xlnx,zynqmp-sk-kv260-revB", "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; + model = "ZynqMP KV260 revB"; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ -- cgit v1.3.1 From 2fe2be2d279cc4bd62b12126668b298adcea4e54 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 18 Jan 2023 13:11:59 +0100 Subject: arm64: zynqmp: Add support for Kria K24 SOM SOM itself from PS point of view is using the same configuration as K26 that's why reuse that files and only change compatible strings. The reason for creating own set of files is just in case when versions start to diverge because of HW change, supply chain issue, etc. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/61f877ec0b480c5bd368a1211fc73ff7465016bd.1674043915.git.michal.simek@amd.com --- arch/arm/dts/Makefile | 2 + arch/arm/dts/zynqmp-sm-k24-revA.dts | 22 + arch/arm/dts/zynqmp-smk-k24-revA.dts | 21 + .../zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c | 1061 ++++++++++++++++++++ board/xilinx/zynqmp/zynqmp-smk-k24-revA | 1 + 5 files changed, 1107 insertions(+) create mode 100644 arch/arm/dts/zynqmp-sm-k24-revA.dts create mode 100644 arch/arm/dts/zynqmp-smk-k24-revA.dts create mode 100644 board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c create mode 120000 board/xilinx/zynqmp/zynqmp-smk-k24-revA diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 79bec315a2a..82aa4508873 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -349,6 +349,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-mini-emmc1.dtb \ zynqmp-mini-nand.dtb \ zynqmp-mini-qspi.dtb \ + zynqmp-sm-k24-revA.dtb \ + zynqmp-smk-k24-revA.dtb \ zynqmp-sm-k26-revA.dtb \ zynqmp-smk-k26-revA.dtb \ zynqmp-sck-kr-g-revA.dtbo \ diff --git a/arch/arm/dts/zynqmp-sm-k24-revA.dts b/arch/arm/dts/zynqmp-sm-k24-revA.dts new file mode 100644 index 00000000000..24514409cb9 --- /dev/null +++ b/arch/arm/dts/zynqmp-sm-k24-revA.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP SM-K24 RevA + * + * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2022, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include "zynqmp-sm-k26-revA.dts" + +/ { + model = "ZynqMP SM-K24 RevA"; + compatible = "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", + "xlnx,zynqmp"; + + memory@0 { + device_type = "memory"; /* 2GB */ + reg = <0 0 0 0x80000000>; + }; +}; diff --git a/arch/arm/dts/zynqmp-smk-k24-revA.dts b/arch/arm/dts/zynqmp-smk-k24-revA.dts new file mode 100644 index 00000000000..7308983b15a --- /dev/null +++ b/arch/arm/dts/zynqmp-smk-k24-revA.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP SMK-K24 RevA + * + * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2022, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include "zynqmp-sm-k24-revA.dts" + +/ { + model = "ZynqMP SMK-K24 RevA"; + compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24", + "xlnx,zynqmp"; +}; + +&sdhci0 { + status = "disabled"; +}; diff --git a/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c new file mode 100644 index 00000000000..45102302dc2 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-sm-k24-revA/psu_init_gpl.c @@ -0,0 +1,1061 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + */ + +#include +#include + +static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly, + int d_lock_cnt, int d_lfhf, int d_cp, int d_res) +{ + unsigned int pll_ctrl_regval; + unsigned int pll_status_regval; + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00010000U); + pll_ctrl_regval = pll_ctrl_regval | (div2 << 16); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0xFE000000U); + pll_ctrl_regval = pll_ctrl_regval | (d_lock_dly << 25); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x007FE000U); + pll_ctrl_regval = pll_ctrl_regval | (d_lock_cnt << 13); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000C00U); + pll_ctrl_regval = pll_ctrl_regval | (d_lfhf << 10); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x000001E0U); + pll_ctrl_regval = pll_ctrl_regval | (d_cp << 5); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); + pll_ctrl_regval = pll_ctrl_regval & (~0x0000000FU); + pll_ctrl_regval = pll_ctrl_regval | (d_res << 0); + Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00007F00U); + pll_ctrl_regval = pll_ctrl_regval | (ddr_pll_fbdiv << 8); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U); + pll_ctrl_regval = pll_ctrl_regval | (1 << 3); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U); + pll_ctrl_regval = pll_ctrl_regval | (1 << 0); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U); + pll_ctrl_regval = pll_ctrl_regval | (0 << 0); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); + + pll_status_regval = 0x00000000; + while ((pll_status_regval & 0x00000002U) != 0x00000002U) + pll_status_regval = Xil_In32(((0xFD1A0000U) + 0x00000044)); + + pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); + pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U); + pll_ctrl_regval = pll_ctrl_regval | (0 << 3); + Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); +} + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014F00U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x8000FB15U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U); + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); + psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011603U); + psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011403U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000203U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000300U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC1081020U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000202U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00501B9BU); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00408093U); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00030403U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00680000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x0034001BU); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x13151117U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040422U); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x050A170FU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00F08000U); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x0A04060CU); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01040808U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010005U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000401U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040606U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x820D0010U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x01B64228U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x04918208U); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x83FF0003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000F06U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x06060606U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F07C30U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E5U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x0B2E1708U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x282A0711U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F012EU); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01262B0BU); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x0043260BU); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000A14U); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000034U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x0000001BU); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000056U); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8C58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F504U); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F504U); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00BD00U); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_ddr_qos_init_data(void) +{ + psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180090, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180094, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50000000U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02020U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x00080814U); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x03F7F7EBU); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x00FC000BU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x0357FFFFU, 0x0357FFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x0357FFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x0303FFF4U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_pre_init_data(void) +{ + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x0001807CU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U); + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000010U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000004U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + + mask_delay(1); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); + + mask_delay(5); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U); + psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U); + psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); + psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U); + psu_mask_write(0xFD402868, 0x00000082U, 0x00000002U); + psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); + psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U); + psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U); + psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU); + psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U); + psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU); + psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U); + psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); + psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); + psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); + psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + + serdes_illcalib(0, 0, 3, 0, 4, 0, 4, 0); + psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U); + psu_mask_write(0xFD410014, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U); + psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U); + psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U); + psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U); + psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U); + + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); + psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); + psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + mask_poll(0xFD4063E4, 0x00000010U); + mask_poll(0xFD40A3E4, 0x00000010U); + + return 1; +} + +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U); + + return 1; +} + +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018); + int cur_PLLCR0; + + cur_PLLCR0 = (Xil_In32(0xFD080068U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL0PLLCR0; + + cur_DX8SL0PLLCR0 = (Xil_In32(0xFD081404U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL1PLLCR0; + + cur_DX8SL1PLLCR0 = (Xil_In32(0xFD081444U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL2PLLCR0; + + cur_DX8SL2PLLCR0 = (Xil_In32(0xFD081484U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL3PLLCR0; + + cur_DX8SL3PLLCR0 = (Xil_In32(0xFD0814C4U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SL4PLLCR0; + + cur_DX8SL4PLLCR0 = (Xil_In32(0xFD081504U) & 0xFFFFFFFFU) >> 0x00000000U; + int cur_DX8SLBPLLCR0; + + cur_DX8SLBPLLCR0 = (Xil_In32(0xFD0817C4U) & 0xFFFFFFFFU) >> 0x00000000U; + Xil_Out32(0xFD080068, 0x02120000); + Xil_Out32(0xFD081404, 0x02120000); + Xil_Out32(0xFD081444, 0x02120000); + Xil_Out32(0xFD081484, 0x02120000); + Xil_Out32(0xFD0814C4, 0x02120000); + Xil_Out32(0xFD081504, 0x02120000); + Xil_Out32(0xFD0817C4, 0x02120000); + int cur_div2; + + cur_div2 = (Xil_In32(0xFD1A002CU) & 0x00010000U) >> 0x00000010U; + int cur_fbdiv; + + cur_fbdiv = (Xil_In32(0xFD1A002CU) & 0x00007F00U) >> 0x00000008U; + dpll_prog(1, 49, 63, 625, 3, 3, 2); + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018); + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; + pll_retry--; + } + Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); + if (!pll_locked) + return 0; + + Xil_Out32(0xFD080004U, 0x00040063U); + Xil_Out32(0xFD0800C0U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD070010U, 0x80000018U); + Xil_Out32(0xFD0701B0U, 0x00000005U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000331U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000B36U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000C56U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000E19U); + Xil_Out32(0xFD070010U, 0x80000018U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00001616U); + Xil_Out32(0xFD070010U, 0x80000018U); + Xil_Out32(0xFD070010U, 0x80000010U); + Xil_Out32(0xFD0701B0U, 0x00000005U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U); + prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000001U); + prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U); + prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U); + prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000002U); + prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U); + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018); + + Xil_Out32(0xFD080068, cur_PLLCR0); + Xil_Out32(0xFD081404, cur_DX8SL0PLLCR0); + Xil_Out32(0xFD081444, cur_DX8SL1PLLCR0); + Xil_Out32(0xFD081484, cur_DX8SL2PLLCR0); + Xil_Out32(0xFD0814C4, cur_DX8SL3PLLCR0); + Xil_Out32(0xFD081504, cur_DX8SL4PLLCR0); + Xil_Out32(0xFD0817C4, cur_DX8SLBPLLCR0); + for (int tp = 0; tp < 20; tp++) + regval = Xil_In32(0xFD070018); + + dpll_prog(cur_div2, cur_fbdiv, 63, 625, 3, 3, 2); + for (int tp = 0; tp < 2000; tp++) + regval = Xil_In32(0xFD070018); + + prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000000U); + prog_reg(0xFD080004U, 0x00040000U, 0x00000012U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000040U, 0x00000006U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000020U, 0x00000005U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000010U, 0x00000004U, 0x00000001U); + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + for (int tp = 0; tp < 2000; tp++) + regval = Xil_In32(0xFD070018); + + prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000000U); + prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U); + prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U); + prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000003U); + prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U); + for (int tp = 0; tp < 2000; tp++) + regval = Xil_In32(0xFD070018); + + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0014FE01); + + regval = Xil_In32(0xFD080030); + while (regval != 0x8000007E) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD080200U, 0x000091C7U); + regval = Xil_In32(0xFD080030); + while (regval != 0x80008FFF) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD080200U, 0x800091C7U); + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; + + Xil_Out32(0xFD080200U, 0x800091C7U); + int cur_R006_tREFPRD; + + cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + regval = Xil_In32(0xFD080030); + + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + regval = Xil_In32(0xFD080030); + + prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U); + prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U); + prog_reg(0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U); + prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U); + Xil_Out32(0xFD070180U, 0x020D0010U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + for (int tp = 0; tp < 4000; tp++) + regval = Xil_In32(0xFD070018); + + prog_reg(0xFD080090U, 0x00000FC0U, 0x00000006U, 0x00000007U); + prog_reg(0xFD080090U, 0x00000004U, 0x00000002U, 0x00000001U); + prog_reg(0xFD08070CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD08080CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD08090CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD080A0CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD080F0CU, 0x02000000U, 0x00000019U, 0x00000000U); + prog_reg(0xFD080200U, 0x00000010U, 0x00000004U, 0x00000001U); + prog_reg(0xFD080250U, 0x00000002U, 0x00000001U, 0x00000000U); + prog_reg(0xFD080250U, 0x0000000CU, 0x00000002U, 0x00000001U); + prog_reg(0xFD080250U, 0x000000F0U, 0x00000004U, 0x00000000U); + prog_reg(0xFD080250U, 0x00300000U, 0x00000014U, 0x00000001U); + prog_reg(0xFD080250U, 0xF0000000U, 0x0000001CU, 0x00000002U); + prog_reg(0xFD08070CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD08080CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD08090CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080A0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080B0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080C0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080D0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080E0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080F0CU, 0x08000000U, 0x0000001BU, 0x00000000U); + prog_reg(0xFD080254U, 0x000000FFU, 0x00000000U, 0x00000001U); + prog_reg(0xFD080254U, 0x000F0000U, 0x00000010U, 0x0000000AU); + prog_reg(0xFD080250U, 0x00000001U, 0x00000000U, 0x00000001U); + + return 1; +} + +static void init_peripheral(void) +{ + psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU); +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_peripherals_pre_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + init_peripheral(); + + status &= psu_afi_config(); + psu_ddr_qos_init_data(); + + if (status == 0) + return 1; + return 0; +} diff --git a/board/xilinx/zynqmp/zynqmp-smk-k24-revA b/board/xilinx/zynqmp/zynqmp-smk-k24-revA new file mode 120000 index 00000000000..89e45cd4bd4 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-smk-k24-revA @@ -0,0 +1 @@ +zynqmp-sm-k24-revA \ No newline at end of file -- cgit v1.3.1 From 4dd5a9fcb5b1f314d6e56e9a2bedb7e8dbc31bb3 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Wed, 25 Jan 2023 18:41:55 +0200 Subject: microblaze: spl: wrap spl_start_uboot() in SPL_OS_BOOT ifdefs Make spl_start_uboot() available only if CONFIG_SPL_OS_BOOT is enabled, since it is only used for falcon mode. Signed-off-by: Ovidiu Panait Link: https://lore.kernel.org/r/20230125164157.1638680-1-ovpanait@gmail.com Signed-off-by: Michal Simek --- arch/microblaze/cpu/spl.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c index cea6d56f16f..b9ff9c37022 100644 --- a/arch/microblaze/cpu/spl.c +++ b/arch/microblaze/cpu/spl.c @@ -41,17 +41,15 @@ void __noreturn jump_to_image_linux(struct spl_image_info *spl_image) image_entry(NULL, 0, (ulong)spl_image->arg); } -#endif /* CONFIG_SPL_OS_BOOT */ int spl_start_uboot(void) { -#ifdef CONFIG_SPL_OS_BOOT if (boot_linux) return 0; -#endif return 1; } +#endif /* CONFIG_SPL_OS_BOOT */ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { -- cgit v1.3.1 From 8e2378e559a2792c5d730e6a65bec964b56b5c33 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Wed, 25 Jan 2023 18:41:56 +0200 Subject: microblaze: spl: drop boot_linux Drop boot_linux variable as it is not assigned anywhere. Now that there is no variable controlling linux boot in spl_start_uboot(), make this function always return false when falcon mode is enabled. Signed-off-by: Ovidiu Panait Link: https://lore.kernel.org/r/20230125164157.1638680-2-ovpanait@gmail.com Signed-off-by: Michal Simek --- arch/microblaze/cpu/spl.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c index b9ff9c37022..eaa095ba99f 100644 --- a/arch/microblaze/cpu/spl.c +++ b/arch/microblaze/cpu/spl.c @@ -14,8 +14,6 @@ #include #include -bool boot_linux; - void board_boot_order(u32 *spl_boot_list) { spl_boot_list[0] = BOOT_DEVICE_NOR; @@ -44,10 +42,7 @@ void __noreturn jump_to_image_linux(struct spl_image_info *spl_image) int spl_start_uboot(void) { - if (boot_linux) - return 0; - - return 1; + return 0; } #endif /* CONFIG_SPL_OS_BOOT */ -- cgit v1.3.1 From 2ec3609d109e32cb9adb434d1f2e8bd278af8b6e Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Wed, 25 Jan 2023 18:41:57 +0200 Subject: microblaze: spl: disable falcon mode by default Drop falcon mode configs from microblaze-generic_defconfig, so that a defconfig build will still boot into u-boot proper. Signed-off-by: Ovidiu Panait Link: https://lore.kernel.org/r/20230125164157.1638680-3-ovpanait@gmail.com Signed-off-by: Michal Simek --- configs/microblaze-generic_defconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index be349418050..438540fbe4d 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -33,9 +33,6 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK=0x100000 CONFIG_SPL_NOR_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_SPL_ARGS_ADDR=0x2a000000 -CONFIG_SYS_OS_BASE=0x2c060000 CONFIG_SYS_MAXARGS=15 CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=544 -- cgit v1.3.1 From cd04c959267500ca7011e94de9218547ab4ca910 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 19 Jan 2023 10:46:59 +0100 Subject: arm64: versal-net: Enable remaking ELF from bin U-Boot is composing u-boot.bin from u-boot-nodtb.bin with appended dts/dt.dtb. It means U-Boot doesn't have DTB inside. When REMAKE_ELF is enabled make will also create u-boot.elf which is recreated from u-boot.bin. Below is build output for mini configuration how ELF is recreated. cat arch/arm/dts/versal-net-mini.dtb > dts/dt.dtb cat u-boot-nodtb.bin dts/dt.dtb > u-boot-dtb.bin cp dts/dt.dtb u-boot.dtb cp u-boot-dtb.bin u-boot.bin aarch64-linux-gnu-objcopy -I binary -B aarch64 -O elf64-littleaarch64 u-boot.bin u-boot-elf.o aarch64-linux-gnu-ld.bfd u-boot-elf.o -o u-boot.elf -EL -T u-boot-elf.lds --defsym="_start"=0xBBF00000 -Ttext=0xBBF00000 It is useful to have u-boot.elf present because Xilinx XSDB debugger can load ELF file and user doesn't need to specify loading address for u-boot.bin. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/ca550c5c4bf908e757a49a83fdfab0e7100de45e.1674121617.git.michal.simek@amd.com --- configs/xilinx_versal_net_mini_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig index 5bad1791964..0ff5268bc34 100644 --- a/configs/xilinx_versal_net_mini_defconfig +++ b/configs/xilinx_versal_net_mini_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF10000 # CONFIG_EXPERT is not set +CONFIG_REMAKE_ELF=y # CONFIG_LEGACY_IMAGE_FORMAT is not set # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set # CONFIG_AUTOBOOT is not set -- cgit v1.3.1 From fb737f1ed86c87a64e6626975cf51dd70a405cd2 Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Thu, 19 Jan 2023 22:36:14 -0700 Subject: xilinx: common: Include header file to fix warning Prototype is missing for board_get_usable_ram_top, which is pointed by below sparse warning. Include init.h header file to fix this. warning: no previous prototype for 'board_get_usable_ram_top' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230120053617.32463-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- board/xilinx/common/board.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 823d703ea93..52a38147ed2 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include -- cgit v1.3.1 From 508e1aa58c8f02a6b1a1013e3ff79d3e76015104 Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Thu, 19 Jan 2023 22:36:15 -0700 Subject: gpio: zynqmp: Handle error from get_gpio_modepin There is a unused variable ret, due to which we are getting sparse warning as below. warning: variable 'ret' set but not used [-Wunused-but-set-variable]. Return ret incase of error. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230120053617.32463-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/gpio/zynqmp_gpio_modepin.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpio/zynqmp_gpio_modepin.c b/drivers/gpio/zynqmp_gpio_modepin.c index 078fd833959..e9565ff5430 100644 --- a/drivers/gpio/zynqmp_gpio_modepin.c +++ b/drivers/gpio/zynqmp_gpio_modepin.c @@ -48,6 +48,9 @@ static int modepin_gpio_set_value(struct udevice *dev, unsigned int offset, int ret; ret = get_gpio_modepin(ret_payload); + if (ret) + return ret; + if (value) out_val = OUTVAL(offset) | ret_payload[1]; else -- cgit v1.3.1 From 1d15612b99ad102cce8279bc31e9417cca95a7a4 Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Thu, 19 Jan 2023 22:36:16 -0700 Subject: xilinx: versal: Add missing header Add missing prototype to fix the sparse warning, warning: no previous prototype for 'do_go_exec' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230120053617.32463-4-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- board/xilinx/versal/board.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index f9f5457ed20..4cdc2ecd1d2 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -4,6 +4,7 @@ * Michal Simek */ +#include #include #include #include -- cgit v1.3.1 From b387c258240c761f61fbcd0c9b33039275219002 Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Thu, 19 Jan 2023 22:36:17 -0700 Subject: drivers: mmc: Change datatype of tuning_loop_counter to int tuning_loop_counter is of char type, which is not capable of handling the entire data range of this variable. This is pointed by below sparse warning. Change datatype to int to fix this. warning: comparison is always false due to limited range of data type. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20230120053617.32463-5-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek --- drivers/mmc/zynq_sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 7dcf6ad8422..be4075c97a4 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -249,7 +249,7 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) u32 ctrl; struct sdhci_host *host; struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev); - char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; + int tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; dev_dbg(mmc->dev, "%s\n", __func__); -- cgit v1.3.1 From a33ad8051e0fdcc2af34259006c470899ad8cd77 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 25 Jan 2023 08:09:08 +0100 Subject: net: zynq_gem: Wait for SGMII PCS link in zynq_gem_init() In our system using ZynqMP with an external SGMII PHY it's necessary to wait for the PCS link and auto negotiation to finish before the xfer starts. Otherwise the first packet(s) might get dropped, resulting in a delay at the start of the ethernet transfers. This is only done when the PHY link is already up, which is done in phy_startup(). As waiting for the PHY link bits via pcsstatus does not make much sense, when the link is not available in general (e.g. no cable connected). This patch adds the necessary code including a minimal delay of 1 ms which fixes problems of dropped first packages. Signed-off-by: Stefan Roese Cc: Michal Simek Cc: Katakam Harini Cc: Ramon Fried Cc: Sean Anderson Link: https://lore.kernel.org/r/20230125070908.1343256-1-sr@denx.de Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 36 +++++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index fe98bcfb2b6..cc49788012f 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -125,6 +125,10 @@ */ #define PHY_DETECT_MASK 0x1808 +/* PCS (SGMII) Link Status */ +#define ZYNQ_GEM_PCSSTATUS_LINK BIT(2) +#define ZYNQ_GEM_PCSSTATUS_ANEG_COMPL BIT(5) + /* TX BD status masks */ #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 @@ -164,7 +168,8 @@ struct zynq_gem_regs { u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ u32 reserved9[20]; u32 pcscntrl; - u32 rserved12[36]; + u32 pcsstatus; + u32 rserved12[35]; u32 dcfg6; /* 0x294 Design config reg6 */ u32 reserved7[106]; u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ @@ -491,12 +496,37 @@ static int zynq_gem_init(struct udevice *dev) * Must be written after PCS_SEL is set in nwconfig, * otherwise writes will not take effect. */ - if (priv->phydev->phy_id != PHY_FIXED_ID) + if (priv->phydev->phy_id != PHY_FIXED_ID) { writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, ®s->pcscntrl); - else + /* + * When the PHY link is already up, the PCS link needs + * to get re-checked + */ + if (priv->phydev->link) { + u32 pcsstatus; + + pcsstatus = ZYNQ_GEM_PCSSTATUS_LINK | + ZYNQ_GEM_PCSSTATUS_ANEG_COMPL; + ret = wait_for_bit_le32(®s->pcsstatus, + pcsstatus, + true, 5000, true); + if (ret) { + dev_warn(dev, + "no PCS (SGMII) link\n"); + } else { + /* + * Some additional minimal delay seems + * to be needed so that the first + * packet will be sent correctly + */ + mdelay(1); + } + } + } else { writel(readl(®s->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL, ®s->pcscntrl); + } } #endif -- cgit v1.3.1 From b86b135fc67e3b726d69c6f5fe92139e5a2d7a01 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 24 Jan 2023 16:19:26 +0100 Subject: xilinx: board: Use ETH_ALEN macro for mac address size Use predefined macro for eth_mac legacy format. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/382d4bff370894164fad3c30ac0400b25142b544.1674573561.git.michal.simek@amd.com --- board/xilinx/common/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 52a38147ed2..6cdb0004f5c 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -86,7 +86,7 @@ static struct xilinx_board_description *board_info; struct xilinx_legacy_format { char board_sn[18]; /* 0x0 */ char unused0[14]; /* 0x12 */ - char eth_mac[6]; /* 0x20 */ + char eth_mac[ETH_ALEN]; /* 0x20 */ char unused1[170]; /* 0x26 */ char board_name[11]; /* 0xd0 */ char unused2[5]; /* 0xdc */ -- cgit v1.3.1 From e6c62537dbf5bb8b43dbe8c89d1bb61c647b6b24 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 24 Jan 2023 16:19:27 +0100 Subject: xilinx: board: Fix xilinx_eeprom_legacy_cleanup() When ethernet mac address contains 0x20 or 0xff MAC address is changed and bytes are converted to zeros. That's why fix decoding algorithm to ignore fields where MAC address is stored and all non printable chars (including space) are zeroed. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/2802cf1086b14c181356810006fe886f950a36f3.1674573561.git.michal.simek@amd.com --- board/xilinx/common/board.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 6cdb0004f5c..ed393f73773 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -102,9 +102,13 @@ static void xilinx_eeprom_legacy_cleanup(char *eeprom, int size) for (i = 0; i < size; i++) { byte = eeprom[i]; - /* Remove all ffs and spaces */ - if (byte == 0xff || byte == ' ') + /* Remove all non printable chars but ignore MAC address */ + if ((i < offsetof(struct xilinx_legacy_format, eth_mac) || + i >= offsetof(struct xilinx_legacy_format, unused1)) && + (byte < '!' || byte > '~')) { eeprom[i] = 0; + continue; + } /* Convert strings to lower case */ if (byte >= 'A' && byte <= 'Z') -- cgit v1.3.1 From 5563167e6e612e87be1722f28881e835d8836a1d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 24 Jan 2023 16:19:28 +0100 Subject: xilinx: board: Update logic in xilinx_read_eeprom_legacy When eeprom has random content printing random chars can stuck U-Boot. That's why update legacy eeprom format decoding algorithm to copy only maximum amount of chars allocated for fields. And also print them directly from desc structure. Previous algorithm was printing strings first directly from eeprom content and then copy them to desc structure. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/42065fcbb1a10581f9f4f091d64b43c01fe595c6.1674573561.git.michal.simek@amd.com --- board/xilinx/common/board.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index ed393f73773..fbc76eef20d 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -141,21 +141,25 @@ static int xilinx_read_eeprom_legacy(struct udevice *dev, char *name, xilinx_eeprom_legacy_cleanup((char *)eeprom_content, size); - printf("Xilinx I2C Legacy format at %s:\n", name); - printf(" Board name:\t%s\n", eeprom_content->board_name); - printf(" Board rev:\t%s\n", eeprom_content->board_revision); - printf(" Board SN:\t%s\n", eeprom_content->board_sn); + /* Terminating \0 chars are the part of desc fields already */ + strlcpy(desc->name, eeprom_content->board_name, + sizeof(eeprom_content->board_name) + 1); + strlcpy(desc->revision, eeprom_content->board_revision, + sizeof(eeprom_content->board_revision) + 1); + strlcpy(desc->serial, eeprom_content->board_sn, + sizeof(eeprom_content->board_sn) + 1); eth_valid = is_valid_ethaddr((const u8 *)eeprom_content->eth_mac); if (eth_valid) - printf(" Ethernet mac:\t%pM\n", eeprom_content->eth_mac); + memcpy(desc->mac_addr[0], eeprom_content->eth_mac, ETH_ALEN); + + printf("Xilinx I2C Legacy format at %s:\n", name); + printf(" Board name:\t%s\n", desc->name); + printf(" Board rev:\t%s\n", desc->revision); + printf(" Board SN:\t%s\n", desc->serial); - /* Terminating \0 chars ensure end of string */ - strcpy(desc->name, eeprom_content->board_name); - strcpy(desc->revision, eeprom_content->board_revision); - strcpy(desc->serial, eeprom_content->board_sn); if (eth_valid) - memcpy(desc->mac_addr[0], eeprom_content->eth_mac, ETH_ALEN); + printf(" Ethernet mac:\t%pM\n", desc->mac_addr); desc->header = EEPROM_HEADER_MAGIC; -- cgit v1.3.1 From f0f86d39fec73479d4904e6d5b9db01a29597d58 Mon Sep 17 00:00:00 2001 From: Algapally Santosh Sagar Date: Wed, 25 Jan 2023 13:06:21 +0100 Subject: fru: ops: Display FRU fields properly for 0xc1 fields FRU data is not displayed properly in case of 0xc1 fields. The 0xC1 can be used in two cases. 1. Char record type 8-bit ASCII + Latin 1 with length of 1. (For example board revision 'A') 2. C1h (type/length byte encoded to indicate no more info fields). which can follow by 00h to fill all remaining unused space Hence removed the check end-of-the field c1 to allow c1 fields. "ASCII+LATIN1" is defined as the printable characters from the first set of 256 characters of Unicode 6.2 (U+0000h through U+00FFh, inclusive) expressed as an eight-bit value. (Unicode follows ISO/IEC 8859-1 in the layout of printable characters up to U+00FFh). So, print only printable chars and limit range from 0x20 ' ' to 0x7e '-' which will be also indication if 0xc1 behaves as record with one char or end of record. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/4198d73de600627872c80a5b07e5068502c589d7.1674648379.git.michal.simek@amd.com --- board/xilinx/common/fru_ops.c | 43 ++++++++++++++++++++++++++++--------------- 1 file changed, 28 insertions(+), 15 deletions(-) diff --git a/board/xilinx/common/fru_ops.c b/board/xilinx/common/fru_ops.c index c4f009affc5..167252c240c 100644 --- a/board/xilinx/common/fru_ops.c +++ b/board/xilinx/common/fru_ops.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* - * (C) Copyright 2019 - 2020 Xilinx, Inc. + * (C) Copyright 2019 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. */ #include @@ -61,9 +62,6 @@ static int fru_check_type_len(u8 type_len, u8 language, u8 *type) { int len; - if (type_len == FRU_TYPELEN_EOF) - return -EINVAL; - *type = (type_len & FRU_TYPELEN_CODE_MASK) >> FRU_TYPELEN_TYPE_SHIFT; len = type_len & FRU_TYPELEN_LEN_MASK; @@ -172,9 +170,16 @@ static int fru_parse_board(unsigned long addr) { u8 i, type; int len; - u8 *data, *term, *limit; + u8 *data, *term, *limit, *next_addr, *eof; memcpy(&fru_data.brd.ver, (void *)addr, 6); + + /* + * eof marks the last data byte (without checksum). That's why checksum + * is address length - 1 and last data byte is length - 2. + */ + eof = (u8 *)(fru_data.brd.len * 8 + addr - 2); + addr += 6; data = (u8 *)&fru_data.brd.manufacturer_type_len; @@ -184,10 +189,21 @@ static int fru_parse_board(unsigned long addr) for (i = 0; ; i++, data += FRU_BOARD_MAX_LEN) { len = fru_check_type_len(*(u8 *)addr, fru_data.brd.lang_code, &type); + next_addr = (u8 *)addr + 1; + + if ((u8 *)addr >= eof) { + debug("Reach EOF record: addr %lx, eof %lx\n", addr, + (unsigned long)eof); + break; + } + /* - * Stop cature if it end of fields + * Stop capture if the type is ASCII and valid field length + * is 1 (0xc1) and next FRU data is less than 0x20 (space " ") + * or it is 0x7f (delete 'DEL'). */ - if (len == -EINVAL) + if (type == FRU_TYPELEN_TYPE_ASCII8 && len == 1 && + (*next_addr < 0x20 || *next_addr == 0x7F)) break; /* Stop when amount of chars is more then fields to record */ @@ -332,9 +348,11 @@ static int fru_display_board(struct fru_board_data *brd, int verbose) for (u8 i = 0; i < (sizeof(boardinfo) / sizeof(*boardinfo)); i++) { len = fru_check_type_len(*data++, brd->lang_code, &type); - if (len == -EINVAL) { - printf("**** EOF for Board Area ****\n"); - break; + + /* Empty record has no len/type filled */ + if (!len) { + debug("%s not found\n", boardinfo[i]); + continue; } if (type <= FRU_TYPELEN_TYPE_ASCII8 && @@ -344,11 +362,6 @@ static int fru_display_board(struct fru_board_data *brd, int verbose) else debug("Type code: %s\n", typecode[type + 1]); - if (!len) { - debug("%s not found\n", boardinfo[i]); - continue; - } - switch (type) { case FRU_TYPELEN_TYPE_BINARY: debug("Length: %d\n", len); -- cgit v1.3.1