From 6e45549f4dac42748d66462e04f940ef6737289d Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Tue, 17 Dec 2024 16:39:16 +0800 Subject: clk: mediatek: mt7629: fix parent clock of some top clock muxes According to the mt7629 programming guide, the CLK_TOP_F10M_REF_SEL shares the same parent selection with CLK_TOP_IRRX_SEL, while the present parent selection for CLK_TOP_F10M_REF_SEL is actually used for CLK_TOP_SGMII_REF_1_SEL. Signed-off-by: Weijie Gao --- drivers/clk/mediatek/clk-mt7629.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 0c796a1788a..380ab9b9b0b 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -186,7 +186,7 @@ static const int pwm_parents[] = { CLK_TOP_UNIVPLL2_D4 }; -static const int f10m_ref_parents[] = { +static const int sgmii_ref_1_parents[] = { CLK_XTAL, CLK_TOP_SGMIIPLL_D2 }; @@ -369,7 +369,7 @@ static const struct mtk_composite top_muxes[] = { /* CLK_CFG_1 */ MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), - MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15), + MUX_GATE(CLK_TOP_F10M_REF_SEL, irrx_parents, 0x50, 8, 1, 15), MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), @@ -412,7 +412,7 @@ static const struct mtk_composite top_muxes[] = { /* CLK_CFG_8 */ MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7), - MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, f10m_ref_parents, 0xC0, 8, 1, 15), + MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, sgmii_ref_1_parents, 0xC0, 8, 1, 15), MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23), }; -- cgit v1.3.1 From ba365c3d23411620d86b5baf621c8f5a4000ab33 Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Tue, 17 Dec 2024 16:39:20 +0800 Subject: arm: dts: mt7629: fix sgmii clock selection for ethernet Setup correct parent of clock CLK_TOP_SGMII_REF_1_SEL to allow sgmiisys1 work correctly. Signed-off-by: Weijie Gao --- arch/arm/dts/mt7629.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi index 7dea7809c70..cd8277deafe 100644 --- a/arch/arm/dts/mt7629.dtsi +++ b/arch/arm/dts/mt7629.dtsi @@ -314,8 +314,10 @@ "sgmii2_cdr_ref", "sgmii2_cdr_fb", "sgmii_ck", "eth2pll"; assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>, - <&topckgen CLK_TOP_F10M_REF_SEL>; + <&topckgen CLK_TOP_F10M_REF_SEL>, + <&topckgen CLK_TOP_SGMII_REF_1_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>, + <&topckgen CLK_TOP_SYSPLL4_D16>, <&topckgen CLK_TOP_SGMIIPLL_D2>; power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>; resets = <ðsys ETHSYS_FE_RST>; -- cgit v1.3.1 From 0d4d8e6f47ef22ea6b3041b4c0cb27b4ed4bf188 Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Tue, 17 Dec 2024 16:39:23 +0800 Subject: net: mediatek: use correct register field for SGMII speed selection The register field for SGMII speed selection is a 2-bit field with value 0 for 1Gbps and 1 for 2.5Gbps (2/3 are reserved). So it's necessary to set both bits instead of just setting/clearing only the lower bit. Signed-off-by: Weijie Gao --- drivers/net/mtk_eth.c | 12 ++++++------ drivers/net/mtk_eth.h | 3 ++- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index 5098afef8a8..5af406edad1 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -835,8 +835,8 @@ static int mt7531_port_sgmii_init(struct mtk_eth_priv *priv, } /* Set SGMII GEN2 speed(2.5G) */ - mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), - SGMSYS_SPEED_2500, SGMSYS_SPEED_2500); + mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK, + FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); /* Disable SGMII AN */ mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port), @@ -1281,8 +1281,7 @@ static int mtk_phy_probe(struct udevice *dev) static void mtk_sgmii_an_init(struct mtk_eth_priv *priv) { /* Set SGMII GEN1 speed(1G) */ - clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, - SGMSYS_SPEED_2500, 0); + clrbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, SGMSYS_SPEED_MASK); /* Enable SGMII AN */ setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, @@ -1305,8 +1304,9 @@ static void mtk_sgmii_an_init(struct mtk_eth_priv *priv) static void mtk_sgmii_force_init(struct mtk_eth_priv *priv) { /* Set SGMII GEN2 speed(2.5G) */ - setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, - SGMSYS_SPEED_2500); + clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, + SGMSYS_SPEED_MASK, + FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500)); /* Disable SGMII AN */ clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h index fd31c782c7f..4f9ae52f973 100644 --- a/drivers/net/mtk_eth.h +++ b/drivers/net/mtk_eth.h @@ -108,7 +108,8 @@ enum mkt_eth_capabilities { #define SGMSYS_GEN2_SPEED 0x2028 #define SGMSYS_GEN2_SPEED_V2 0x128 -#define SGMSYS_SPEED_2500 BIT(2) +#define SGMSYS_SPEED_MASK GENMASK(3, 2) +#define SGMSYS_SPEED_2500 1 /* USXGMII subsystem config registers */ /* Register to control USXGMII XFI PLL digital */ -- cgit v1.3.1 From 7562da9454c1a6eff3db3b41c183e03039e855e6 Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Tue, 17 Dec 2024 16:39:27 +0800 Subject: net: mediatek: correct register name of ethsys syscfg1 The SYSCFG0 should be SYSCFG1 according to the programming guide. Signed-off-by: Weijie Gao --- drivers/net/mtk_eth.c | 14 +++++++------- drivers/net/mtk_eth.h | 12 ++++++------ 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index 5af406edad1..b8cb1f64995 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -1450,8 +1450,8 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) } ge_mode = GE_MODE_RGMII; - mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M, - SYSCFG0_SGMII_SEL(priv->gmac_id)); + mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, SYSCFG1_SGMII_SEL_M, + SYSCFG1_SGMII_SEL(priv->gmac_id)); if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) mtk_sgmii_an_init(priv); else @@ -1469,9 +1469,9 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) } /* set the gmac to the right mode */ - mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, - SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id), - ge_mode << SYSCFG0_GE_MODE_S(priv->gmac_id)); + mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, + SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), + ge_mode << SYSCFG1_GE_MODE_S(priv->gmac_id)); if (priv->force_mode) { mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | @@ -1527,8 +1527,8 @@ static void mtk_xmac_init(struct mtk_eth_priv *priv) } /* Set GMAC to the correct mode */ - mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, - SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id), + mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, + SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), 0); if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII && diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h index 4f9ae52f973..896dd6636c7 100644 --- a/drivers/net/mtk_eth.h +++ b/drivers/net/mtk_eth.h @@ -65,11 +65,11 @@ enum mkt_eth_capabilities { /* Ethernet subsystem registers */ -#define ETHSYS_SYSCFG0_REG 0x14 -#define SYSCFG0_GE_MODE_S(n) (12 + ((n) * 2)) -#define SYSCFG0_GE_MODE_M 0x3 -#define SYSCFG0_SGMII_SEL_M (0x3 << 8) -#define SYSCFG0_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8)) +#define ETHSYS_SYSCFG1_REG 0x14 +#define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2)) +#define SYSCFG1_GE_MODE_M 0x3 +#define SYSCFG1_SGMII_SEL_M (0x3 << 8) +#define SYSCFG1_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8)) #define ETHSYS_CLKCFG0_REG 0x2c #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) @@ -84,7 +84,7 @@ enum mkt_eth_capabilities { #define QPHY_SEL_MASK 0x3 #define SGMII_QPHY_SEL 0x2 -/* SYSCFG0_GE_MODE: GE Modes */ +/* SYSCFG1_GE_MODE: GE Modes */ #define GE_MODE_RGMII 0 #define GE_MODE_MII 1 #define GE_MODE_MII_PHY 2 -- cgit v1.3.1 From 82f05bc48821f3709f22f3d1f6e45290547f74be Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Tue, 17 Dec 2024 16:39:41 +0800 Subject: net: mediatek: fix sgmii selection for mt7622 Unlike other platforms, mt7622 has only one SGMII and it can be attached to either gmac1 or gmac2. So the register field of the sgmii selection differs from other platforms as newer platforms can control each sgmii individually. This patch adds a new capability for mt7622 to handle this case. Signed-off-by: Weijie Gao --- drivers/net/mtk_eth.c | 10 ++++++++-- drivers/net/mtk_eth.h | 8 ++++++-- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index b8cb1f64995..592764df3d1 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -1434,7 +1434,7 @@ static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv) static void mtk_mac_init(struct mtk_eth_priv *priv) { - int i, ge_mode = 0; + int i, sgmii_sel_mask = 0, ge_mode = 0; u32 mcr; switch (priv->phy_interface) { @@ -1450,8 +1450,13 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) } ge_mode = GE_MODE_RGMII; - mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, SYSCFG1_SGMII_SEL_M, + + if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII)) + sgmii_sel_mask = SYSCFG1_SGMII_SEL_M; + + mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, sgmii_sel_mask, SYSCFG1_SGMII_SEL(priv->gmac_id)); + if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) mtk_sgmii_an_init(priv); else @@ -2112,6 +2117,7 @@ static const struct mtk_soc_data mt7623_data = { }; static const struct mtk_soc_data mt7622_data = { + .caps = MT7622_CAPS, .ana_rgc3 = 0x2028, .gdma_count = 2, .pdma_base = PDMA_V1_BASE, diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h index 896dd6636c7..ad079b5263b 100644 --- a/drivers/net/mtk_eth.h +++ b/drivers/net/mtk_eth.h @@ -23,6 +23,7 @@ enum mkt_eth_capabilities { /* PATH BITS */ MTK_ETH_PATH_GMAC1_TRGMII_BIT, MTK_ETH_PATH_GMAC2_SGMII_BIT, + MTK_ETH_PATH_MT7622_SGMII_BIT, }; #define MTK_TRGMII BIT(MTK_TRGMII_BIT) @@ -36,6 +37,7 @@ enum mkt_eth_capabilities { #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) +#define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT) #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) @@ -45,6 +47,8 @@ enum mkt_eth_capabilities { #define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK) +#define MT7622_CAPS (MTK_ETH_PATH_MT7622_SGMII) + #define MT7623_CAPS (MTK_GMAC1_TRGMII) #define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2) @@ -68,8 +72,8 @@ enum mkt_eth_capabilities { #define ETHSYS_SYSCFG1_REG 0x14 #define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2)) #define SYSCFG1_GE_MODE_M 0x3 -#define SYSCFG1_SGMII_SEL_M (0x3 << 8) -#define SYSCFG1_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8)) +#define SYSCFG1_SGMII_SEL_M GENMASK(9, 8) +#define SYSCFG1_SGMII_SEL(gmac) BIT(9 - (gmac)) #define ETHSYS_CLKCFG0_REG 0x2c #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) -- cgit v1.3.1 From d8d7e566545f836dd49611cafbf44eef56434e08 Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Tue, 17 Dec 2024 16:39:46 +0800 Subject: net: mediatek: fix gmac2 usability for mt7629 MT7629 need extra setting for gmac2 to work. So additional capability is added for mt7629 to handle this case. Signed-off-by: Weijie Gao --- drivers/net/mtk_eth.c | 6 ++++++ drivers/net/mtk_eth.h | 7 +++++++ 2 files changed, 13 insertions(+) diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index 592764df3d1..39519fe05fe 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -1437,6 +1437,11 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) int i, sgmii_sel_mask = 0, ge_mode = 0; u32 mcr; + if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7629_GMAC2)) { + mtk_infra_rmw(priv, MT7629_INFRA_MISC2_REG, + INFRA_MISC2_BONDING_OPTION, priv->gmac_id); + } + switch (priv->phy_interface) { case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII: @@ -2101,6 +2106,7 @@ static const struct mtk_soc_data mt7981_data = { }; static const struct mtk_soc_data mt7629_data = { + .caps = MT7629_CAPS, .ana_rgc3 = 0x128, .gdma_count = 2, .pdma_base = PDMA_V1_BASE, diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h index ad079b5263b..1aa037907c5 100644 --- a/drivers/net/mtk_eth.h +++ b/drivers/net/mtk_eth.h @@ -24,6 +24,7 @@ enum mkt_eth_capabilities { MTK_ETH_PATH_GMAC1_TRGMII_BIT, MTK_ETH_PATH_GMAC2_SGMII_BIT, MTK_ETH_PATH_MT7622_SGMII_BIT, + MTK_ETH_PATH_MT7629_GMAC2_BIT, }; #define MTK_TRGMII BIT(MTK_TRGMII_BIT) @@ -38,6 +39,7 @@ enum mkt_eth_capabilities { #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) #define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT) +#define MTK_ETH_PATH_MT7629_GMAC2 BIT(MTK_ETH_PATH_MT7629_GMAC2_BIT) #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) @@ -51,6 +53,8 @@ enum mkt_eth_capabilities { #define MT7623_CAPS (MTK_GMAC1_TRGMII) +#define MT7629_CAPS (MTK_ETH_PATH_MT7629_GMAC2 | MTK_INFRA) + #define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2) #define MT7986_CAPS (MTK_NETSYS_V2) @@ -88,6 +92,9 @@ enum mkt_eth_capabilities { #define QPHY_SEL_MASK 0x3 #define SGMII_QPHY_SEL 0x2 +#define MT7629_INFRA_MISC2_REG 0x70c +#define INFRA_MISC2_BONDING_OPTION GENMASK(15, 0) + /* SYSCFG1_GE_MODE: GE Modes */ #define GE_MODE_RGMII 0 #define GE_MODE_MII 1 -- cgit v1.3.1 From ad0c47109e4c9f6297aa247d8bbf7131438bc435 Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Tue, 17 Dec 2024 16:39:50 +0800 Subject: net: mediatek: add support for 10GBASE-R This patch adds support for 10GBASE-R interface mode Signed-off-by: Bo-Cun Chen Signed-off-by: Weijie Gao --- drivers/net/mtk_eth.c | 83 +++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 81 insertions(+), 2 deletions(-) diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index 39519fe05fe..5c210fd3e14 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -1246,6 +1246,7 @@ static int mtk_phy_start(struct mtk_eth_priv *priv) if (!priv->force_mode) { if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || priv->phy_interface == PHY_INTERFACE_MODE_XGMII) mtk_xphy_link_adjust(priv); else @@ -1425,6 +1426,71 @@ static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv) udelay(400); } +static void mtk_usxgmii_setup_phya_force_10000(struct mtk_eth_priv *priv) +{ + regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6C); + regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B); + regmap_write(priv->usxgmii_regmap, 0x80C, 0xB0000000); + ndelay(1020); + regmap_write(priv->usxgmii_regmap, 0x80C, 0x90000000); + ndelay(1020); + + regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C); + regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA); + regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707); + regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F); + regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032); + regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA); + regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B); + regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF); + regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA); + regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F); + regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68); + regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166); + regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF); + regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D); + regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909); + regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000); + regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000); + regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06); + regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C); + regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000); + regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342); + regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20); + regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800); + ndelay(1020); + regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020); + regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01); + regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884); + regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002); + regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220); + regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01); + regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600); + regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x47684100); + regmap_write(priv->xfi_pextp_regmap, 0x3050, 0x00000000); + regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x00000000); + regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00); + if (priv->gmac_id == 2) + regmap_write(priv->xfi_pextp_regmap, 0xA008, 0x0007B400); + regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000); + regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800); + udelay(150); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111); + ndelay(1020); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101); + udelay(15); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111); + ndelay(1020); + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101); + udelay(100); + regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030); + regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00); + regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000); + udelay(400); +} + static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv) { mtk_xfi_pll_enable(priv); @@ -1432,6 +1498,13 @@ static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv) mtk_usxgmii_setup_phya_an_10000(priv); } +static void mtk_10gbaser_init(struct mtk_eth_priv *priv) +{ + mtk_xfi_pll_enable(priv); + mtk_usxgmii_reset(priv); + mtk_usxgmii_setup_phya_force_10000(priv); +} + static void mtk_mac_init(struct mtk_eth_priv *priv) { int i, sgmii_sel_mask = 0, ge_mode = 0; @@ -1532,6 +1605,9 @@ static void mtk_xmac_init(struct mtk_eth_priv *priv) case PHY_INTERFACE_MODE_USXGMII: mtk_usxgmii_an_init(priv); break; + case PHY_INTERFACE_MODE_10GBASER: + mtk_10gbaser_init(priv); + break; default: break; } @@ -1541,7 +1617,8 @@ static void mtk_xmac_init(struct mtk_eth_priv *priv) SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id), 0); - if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII && + if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && priv->gmac_id == 1) { mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX, NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL); @@ -1843,6 +1920,7 @@ static int mtk_eth_probe(struct udevice *dev) /* Set MAC mode */ if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || priv->phy_interface == PHY_INTERFACE_MODE_XGMII) mtk_xmac_init(priv); else @@ -1977,7 +2055,8 @@ static int mtk_eth_of_to_plat(struct udevice *dev) /* Upstream linux use mediatek,pnswap instead of pn_swap */ priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") || ofnode_read_bool(args.node, "mediatek,pnswap"); - } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII) { + } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) { /* get corresponding usxgmii phandle */ ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys", NULL, 0, 0, &args); -- cgit v1.3.1 From 5ac929fd1ab1d0dc77b9167952aea7cafdb8619f Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Tue, 17 Dec 2024 16:39:55 +0800 Subject: net: mediatek: make sgmii/usxgmii optional Not all platforms supports sgmii and/or usxgmii. So we add Kconfig options for these features and enable them only for supported platforms. Signed-off-by: Weijie Gao --- drivers/net/Kconfig | 12 ++++++++++++ drivers/net/mtk_eth.c | 39 +++++++++++++++++++++++++++++---------- 2 files changed, 41 insertions(+), 10 deletions(-) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 576cd2d50ad..5a57d05d977 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -975,6 +975,18 @@ config MEDIATEK_ETH This Driver support MediaTek Ethernet GMAC Say Y to enable support for the MediaTek Ethernet GMAC. +if MEDIATEK_ETH + +config MTK_ETH_SGMII + bool + default y if ARCH_MEDIATEK && !TARGET_MT7623 + +config MTK_ETH_XGMII + bool + default y if TARGET_MT7987 || TARGET_MT7988 + +endif # MEDIATEK_ETH + config HIFEMAC_ETH bool "HiSilicon Fast Ethernet Controller" select DM_CLK diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index 5c210fd3e14..d3f29e4a0d0 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -1505,7 +1505,7 @@ static void mtk_10gbaser_init(struct mtk_eth_priv *priv) mtk_usxgmii_setup_phya_force_10000(priv); } -static void mtk_mac_init(struct mtk_eth_priv *priv) +static int mtk_mac_init(struct mtk_eth_priv *priv) { int i, sgmii_sel_mask = 0, ge_mode = 0; u32 mcr; @@ -1522,13 +1522,16 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) break; case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_2500BASEX: + if (!IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { + printf("Error: SGMII is not supported on this platform\n"); + return -ENOTSUPP; + } + if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) { mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK, SGMII_QPHY_SEL); } - ge_mode = GE_MODE_RGMII; - if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII)) sgmii_sel_mask = SYSCFG1_SGMII_SEL_M; @@ -1539,6 +1542,8 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) mtk_sgmii_an_init(priv); else mtk_sgmii_force_init(priv); + + ge_mode = GE_MODE_RGMII; break; case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: @@ -1595,12 +1600,19 @@ static void mtk_mac_init(struct mtk_eth_priv *priv) RX_RST | RXC_DQSISEL); mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0); } + + return 0; } -static void mtk_xmac_init(struct mtk_eth_priv *priv) +static int mtk_xmac_init(struct mtk_eth_priv *priv) { u32 force_link = 0; + if (!IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { + printf("Error: 10Gb interface is not supported on this platform\n"); + return -ENOTSUPP; + } + switch (priv->phy_interface) { case PHY_INTERFACE_MODE_USXGMII: mtk_usxgmii_an_init(priv); @@ -1633,6 +1645,8 @@ static void mtk_xmac_init(struct mtk_eth_priv *priv) /* Force GMAC link down */ mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE); + + return 0; } static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) @@ -1922,9 +1936,12 @@ static int mtk_eth_probe(struct udevice *dev) if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || priv->phy_interface == PHY_INTERFACE_MODE_XGMII) - mtk_xmac_init(priv); + ret = mtk_xmac_init(priv); else - mtk_mac_init(priv); + ret = mtk_mac_init(priv); + + if (ret) + return ret; /* Probe phy if switch is not specified */ if (priv->sw == SW_NONE) @@ -2032,8 +2049,9 @@ static int mtk_eth_of_to_plat(struct udevice *dev) } } - if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII || - priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { + if ((priv->phy_interface == PHY_INTERFACE_MODE_SGMII || + priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) && + IS_ENABLED(CONFIG_MTK_ETH_SGMII)) { /* get corresponding sgmii phandle */ ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys", NULL, 0, 0, &args); @@ -2055,8 +2073,9 @@ static int mtk_eth_of_to_plat(struct udevice *dev) /* Upstream linux use mediatek,pnswap instead of pn_swap */ priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") || ofnode_read_bool(args.node, "mediatek,pnswap"); - } else if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || - priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) { + } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) && + IS_ENABLED(CONFIG_MTK_ETH_XGMII)) { /* get corresponding usxgmii phandle */ ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys", NULL, 0, 0, &args); -- cgit v1.3.1 From b9dfb5636bc5eb9b783b88b8388dc7d1f41d6498 Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Tue, 17 Dec 2024 16:39:59 +0800 Subject: net: mediatek: don't enable GDMA cpu bridge unconditionally for NETSYSv3 Enable GDMA cpu bridge only when 10Gb interface is enabled for GMAC other than GMAC0, or when MT7988 internal switch is used. Signed-off-by: Weijie Gao --- drivers/net/mtk_eth.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index d3f29e4a0d0..888e8c1e855 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -1762,10 +1762,16 @@ static int mtk_eth_start(struct udevice *dev) if (priv->sw == SW_MT7988 && priv->gmac_id == 0) { mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_BRIDGE_TO_CPU); - } - mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, - GDMA_CPU_BRIDGE_EN); + mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, + GDMA_CPU_BRIDGE_EN); + } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII || + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER || + priv->phy_interface == PHY_INTERFACE_MODE_XGMII) && + priv->gmac_id != 0) { + mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG, + GDMA_CPU_BRIDGE_EN); + } } udelay(500); -- cgit v1.3.1 From c949686e558e00cbb8c38f7c060701006d70cea8 Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Tue, 17 Dec 2024 16:40:03 +0800 Subject: net: mediatek: fix usability with wget command The wget command currently cannot work correctly with mtk_eth driver. This patch fixed this by increase DMA ring size and invalidate ring data after use. Signed-off-by: Weijie Gao --- drivers/net/mtk_eth.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c index 888e8c1e855..454caa3cd3a 100644 --- a/drivers/net/mtk_eth.c +++ b/drivers/net/mtk_eth.c @@ -29,8 +29,8 @@ #include "mtk_eth.h" -#define NUM_TX_DESC 24 -#define NUM_RX_DESC 24 +#define NUM_TX_DESC 32 +#define NUM_RX_DESC 32 #define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN) #define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN) #define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE) @@ -1897,6 +1897,9 @@ static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length) rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size; + invalidate_dcache_range((ulong)rxd->rxd1, + (ulong)rxd->rxd1 + PKTSIZE_ALIGN); + if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) || MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN); -- cgit v1.3.1