From a6caca94fc77dbe1db9484915241f77909aa43e3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 15 Sep 2025 15:01:09 -0600 Subject: MAINTAINERS: Update Luka Perkov's roles Per a private email, drop Luka Perkov from MAINTAINERS entries. Reviewed-by: Tony Dinh Signed-off-by: Tom Rini --- MAINTAINERS | 1 - board/Marvell/mvebu_armada-8k/MAINTAINERS | 1 - board/iomega/iconnect/MAINTAINERS | 1 - board/mikrotik/crs3xx-98dx3236/MAINTAINERS | 4 ---- board/zyxel/nsa310s/MAINTAINERS | 1 - 5 files changed, 8 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 3fb163aa1db..1b41f57a58b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -346,7 +346,6 @@ F: drivers/spi/gxp_spi.c ARM IPQ40XX M: Robert Marko -M: Luka Perkov S: Maintained F: arch/arm/mach-ipq40xx/ F: include/dt-bindings/clock/qcom,gcc-ipq4019.h diff --git a/board/Marvell/mvebu_armada-8k/MAINTAINERS b/board/Marvell/mvebu_armada-8k/MAINTAINERS index 55e485faa96..15660cd17d4 100644 --- a/board/Marvell/mvebu_armada-8k/MAINTAINERS +++ b/board/Marvell/mvebu_armada-8k/MAINTAINERS @@ -13,7 +13,6 @@ F: configs/mvebu_mcbin-88f8040_defconfig Puzzle-M801 BOARD M: Luka Kovacic -M: Luka Perkov S: Maintained F: configs/mvebu_puzzle-m801-88f8040_defconfig F: arch/arm/dts/armada-8040-puzzle-m801.dts diff --git a/board/iomega/iconnect/MAINTAINERS b/board/iomega/iconnect/MAINTAINERS index a1b018e8169..d9093b28ef0 100644 --- a/board/iomega/iconnect/MAINTAINERS +++ b/board/iomega/iconnect/MAINTAINERS @@ -1,6 +1,5 @@ ICONNECT BOARD M: Tony Dinh -M: Luka Perkov S: Maintained F: board/iomega/iconnect/ F: include/configs/iconnect.h diff --git a/board/mikrotik/crs3xx-98dx3236/MAINTAINERS b/board/mikrotik/crs3xx-98dx3236/MAINTAINERS index 906ff98970b..04423556924 100644 --- a/board/mikrotik/crs3xx-98dx3236/MAINTAINERS +++ b/board/mikrotik/crs3xx-98dx3236/MAINTAINERS @@ -1,13 +1,11 @@ CRS3XX-98DX3236 BOARD M: Luka Kovacic -M: Luka Perkov S: Maintained F: board/mikrotik/crs3xx-98dx3236/ F: include/configs/crs3xx-98dx3236.h CRS305-1G-4S BOARD M: Luka Kovacic -M: Luka Perkov S: Maintained F: configs/crs305-1g-4s_defconfig F: configs/crs305-1g-4s-bit_defconfig @@ -16,7 +14,6 @@ F: arch/arm/dts/armada-xp-crs305-1g-4s-bit.dts CRS326-24G-2S BOARD M: Luka Kovacic -M: Luka Perkov S: Maintained F: configs/crs326-24g-2s_defconfig F: configs/crs326-24g-2s-bit_defconfig @@ -25,7 +22,6 @@ F: arch/arm/dts/armada-xp-crs326-24g-2s-bit.dts CRS328-4C-20S-4S BOARD M: Luka Kovacic -M: Luka Perkov S: Maintained F: configs/crs328-4c-20s-4s_defconfig F: configs/crs328-4c-20s-4s-bit_defconfig diff --git a/board/zyxel/nsa310s/MAINTAINERS b/board/zyxel/nsa310s/MAINTAINERS index 11106acf3e9..865c98f7724 100644 --- a/board/zyxel/nsa310s/MAINTAINERS +++ b/board/zyxel/nsa310s/MAINTAINERS @@ -1,6 +1,5 @@ NSA310S BOARD M: Tony Dinh -M: Luka Perkov S: Maintained F: board/zyxel/nsa310s/ F: include/configs/nsa310s.h -- cgit v1.3.1 From d3074f3d699d188bbeb68feacc473d8bc53ce762 Mon Sep 17 00:00:00 2001 From: Raymond Mao Date: Fri, 19 Sep 2025 14:04:51 -0700 Subject: MAINTAINERS: Add myself into the list for MbedTLS Add myself into the list for MbedTLS. Signed-off-by: Raymond Mao Acked-by: Ilias Apalodimas --- MAINTAINERS | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 1b41f57a58b..8dfe2fd6ca0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1291,6 +1291,11 @@ T: git git://github.com/ARM-software/u-boot.git F: drivers/video/mali_dp.c F: drivers/i2c/i2c-versatile.c +MBEDTLS +M: Raymond Mao +S: Maintained +F: lib/mbedtls/ + MEMBUF M: Simon Glass S: Maintained -- cgit v1.3.1 From ac046ad1873cb3d85f4c81c0bed592a4ed7a5903 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Fri, 19 Sep 2025 08:39:47 +0200 Subject: board: phytec: phycore_am6xx: Update scriptaddr After switching our boards to standard boot, we observed that the kernel hangs when booting with the "script" boot method over the network. The original scriptaddr value was copied from ti_common.env and remained unused for some time. On phycore-am62x and phycore-am62ax, however, this address conflicts with the current location where ATF is loaded (CONFIG_K3_ATF_LOAD_ADDR). Move scriptaddr to 0x89100000, directly after fdtoverlay_addr_r. The phycore-am64x is not affected by this issue, but we update it as well to keep all phycore-am6xx boards consistent. Signed-off-by: Wadim Egorov Reviewed-by: Anshul Dalal --- board/phytec/phycore_am62ax/phycore_am62ax.env | 2 +- board/phytec/phycore_am62x/phycore_am62x.env | 2 +- board/phytec/phycore_am64x/phycore_am64x.env | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/phytec/phycore_am62ax/phycore_am62ax.env b/board/phytec/phycore_am62ax/phycore_am62ax.env index ff4ab8c87b8..47e90f1b7c6 100644 --- a/board/phytec/phycore_am62ax/phycore_am62ax.env +++ b/board/phytec/phycore_am62ax/phycore_am62ax.env @@ -5,7 +5,7 @@ fdtaddr=0x88000000 loadaddr=0x82000000 -scriptaddr=0x80000000 +scriptaddr=0x89100000 fdt_addr_r=0x88000000 kernel_addr_r=0x82000000 ramdisk_addr_r=0x88080000 diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env index ff4ab8c87b8..47e90f1b7c6 100644 --- a/board/phytec/phycore_am62x/phycore_am62x.env +++ b/board/phytec/phycore_am62x/phycore_am62x.env @@ -5,7 +5,7 @@ fdtaddr=0x88000000 loadaddr=0x82000000 -scriptaddr=0x80000000 +scriptaddr=0x89100000 fdt_addr_r=0x88000000 kernel_addr_r=0x82000000 ramdisk_addr_r=0x88080000 diff --git a/board/phytec/phycore_am64x/phycore_am64x.env b/board/phytec/phycore_am64x/phycore_am64x.env index cbaf45b3ace..f4136ed237d 100644 --- a/board/phytec/phycore_am64x/phycore_am64x.env +++ b/board/phytec/phycore_am64x/phycore_am64x.env @@ -4,7 +4,7 @@ fdtaddr=0x88000000 loadaddr=0x82000000 -scriptaddr=0x80000000 +scriptaddr=0x89100000 fdt_addr_r=0x88000000 kernel_addr_r=0x82000000 ramdisk_addr_r=0x88080000 -- cgit v1.3.1 From 96971e5090cd6975023d0556b3d47b195442902e Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Fri, 19 Sep 2025 08:39:48 +0200 Subject: board: phytec: common: Fix missing newline in error message The error message in phytec_get_product_name() was missing a newline, causing log output to be concatenated with subsequent messages. Add the newline to improve readability. Signed-off-by: Wadim Egorov --- board/phytec/common/phytec_som_detection.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index 4d7c9b9f80f..136f4486eb0 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -309,7 +309,7 @@ static int phytec_get_product_name(struct phytec_eeprom_data *data, som_type = 1; break; default: - pr_err("%s: Invalid SOM type: %i", __func__, api2->som_type); + pr_err("%s: Invalid SOM type: %i\n", __func__, api2->som_type); return -EINVAL; }; -- cgit v1.3.1 From 9c7e61fccc65974fc970c587bddcd5857b334852 Mon Sep 17 00:00:00 2001 From: Mathieu Othacehe Date: Mon, 22 Sep 2025 18:29:00 +0200 Subject: board: rzg2l: Check the DTB pointer passed by the TF-A. On the RZG2L platform, the advised TF-A (https://github.com/renesas-rz/rzg_trusted-firmware-a/tree/v2.5/rzg2l) does not pass any DTB blob to U-Boot. On the other hand, the RZG2L part of U-Boot expects a DTB to be passed. It means that if one flashes the latest TF-A as well as the mainline U-Boot, it will crash trying to dereference the NULL DTB pointer before outputing anything. Check if the DTB pointer is NULL before trying to use it. Signed-off-by: Mathieu Othacehe Reviewed-by: Marek Vasut --- arch/arm/mach-renesas/cpu_info-rzg2l.c | 2 +- board/renesas/rzg2l/rzg2l.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-renesas/cpu_info-rzg2l.c b/arch/arm/mach-renesas/cpu_info-rzg2l.c index ab95ce76388..a9cb9f72dd3 100644 --- a/arch/arm/mach-renesas/cpu_info-rzg2l.c +++ b/arch/arm/mach-renesas/cpu_info-rzg2l.c @@ -30,7 +30,7 @@ static const struct tfa_info *get_tfa_info(void) { void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]); - if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) { + if (atf_fdt_blob && fdt_magic(atf_fdt_blob) == FDT_MAGIC) { unsigned int i; for (i = 0; i < ARRAY_SIZE(tfa_info); i++) { if (!fdt_node_check_compatible(atf_fdt_blob, 0, diff --git a/board/renesas/rzg2l/rzg2l.c b/board/renesas/rzg2l/rzg2l.c index 509c5dbb156..3c8f8d04cbd 100644 --- a/board/renesas/rzg2l/rzg2l.c +++ b/board/renesas/rzg2l/rzg2l.c @@ -22,7 +22,7 @@ int board_fit_config_name_match(const char *name) { void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]); - if (fdt_magic(atf_fdt_blob) != FDT_MAGIC) + if (!atf_fdt_blob || fdt_magic(atf_fdt_blob) != FDT_MAGIC) return -1; if (is_rzg2l_board("renesas,r9a07g044l2")) @@ -36,7 +36,7 @@ static void apply_atf_overlay(void *fdt_blob) { void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]); - if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) + if (atf_fdt_blob && fdt_magic(atf_fdt_blob) == FDT_MAGIC) fdt_overlay_apply_node(fdt_blob, 0, atf_fdt_blob, 0); } -- cgit v1.3.1 From eb69747cd231767098d4ad7957fbedad6a42af99 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 24 Sep 2025 03:47:12 +0200 Subject: pci: pcie-rcar-gen4: Fix inverted break condition in PHY initialization R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 4581 Figure 104.3b Initial Setting of PCIEC(example), third quarter of the figure indicates that register 0xf8 should be polled until bit 18 becomes set to 1. Register 0xf8 bit 18 is 0 immediately after write to PCIERSTCTRL1 and is set to 1 in less than 1 ms afterward. The current readl_poll_timeout() break condition is inverted and returns when register 0xf8 bit 18 is set to 0, which in most cases means immediately. In case CONFIG_DEBUG_LOCK_ALLOC=y , the timing changes just enough for the first readl_poll_timeout() poll to already read register 0xf8 bit 18 as 1 and afterward never read register 0xf8 bit 18 as 0, which leads to timeout and failure to start the PCIe controller. Fix this by inverting the poll condition to match the reference manual initialization sequence. Signed-off-by: Marek Vasut --- drivers/pci/pci-rcar-gen4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci-rcar-gen4.c b/drivers/pci/pci-rcar-gen4.c index 41f0d958447..70a000861ef 100644 --- a/drivers/pci/pci-rcar-gen4.c +++ b/drivers/pci/pci-rcar-gen4.c @@ -243,7 +243,7 @@ static int rcar_gen4_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool enable clrbits_le32(rcar->app_base + PCIERSTCTRL1, APP_HOLD_PHY_RST); - ret = readl_poll_timeout(rcar->phy_base + 0x0f8, val, !(val & BIT(18)), 10000); + ret = readl_poll_timeout(rcar->phy_base + 0x0f8, val, val & BIT(18), 10000); if (ret < 0) return ret; -- cgit v1.3.1 From 38541b5db5b1de67f5fbab3d9971ac7ba818cb46 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 24 Sep 2025 03:47:13 +0200 Subject: pci: pcie-rcar-gen4: Assure reset occurs before DBI access Assure the reset is latched and the core is ready for DBI access. On R-Car V4H, the PCIe reset is asynchronized and does not take effect immediately, but needs a short time to complete. In case DBI access happens in that short time, that access generates an SError. Make sure that condition can never happen, read back the state of the reset which should turn the asynchronized reset into synchronized one, and wait a little over 1ms to add additional safety margin. Signed-off-by: Marek Vasut --- drivers/pci/pci-rcar-gen4.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/pci-rcar-gen4.c b/drivers/pci/pci-rcar-gen4.c index 70a000861ef..6e093829861 100644 --- a/drivers/pci/pci-rcar-gen4.c +++ b/drivers/pci/pci-rcar-gen4.c @@ -314,6 +314,9 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar) if (ret) goto err_unprepare; + reset_status(&rcar->pwr_rst); + mdelay(1); + rcar_gen4_pcie_additional_common_init(rcar); return 0; -- cgit v1.3.1 From 19c292a8c5d0e2d0b85279d22643c6a4f6db9139 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 24 Sep 2025 03:47:14 +0200 Subject: pci: pcie-rcar-gen4: Add missing 1ms delay after PWR reset assertion R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 585 Figure 9.3.2 Software Reset flow (B) indicates that for peripherals in HSC domain, after reset has been asserted by writing a matching reset bit into register SRCR, it is mandatory to wait 1ms. Because it is the controller driver which can determine whether or not the controller is in HSC domain based on its compatible string, add the missing delay into the controller driver. This 1ms delay is documented on R-Car V4H and V4M, it is currently unclear whether S4 is affected as well. This patch does apply the extra delay on R-Car S4 as well. Signed-off-by: Marek Vasut --- drivers/pci/pci-rcar-gen4.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/pci-rcar-gen4.c b/drivers/pci/pci-rcar-gen4.c index 6e093829861..1f41ce28b0b 100644 --- a/drivers/pci/pci-rcar-gen4.c +++ b/drivers/pci/pci-rcar-gen4.c @@ -306,6 +306,8 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar) if (ret) goto err_unprepare; + mdelay(1); + setbits_le32(rcar->app_base + PCIEMSR0, DEVICE_TYPE_RC | ((rcar->num_lanes < 4) ? BIFUR_MOD_SET_ON : 0)); -- cgit v1.3.1 From 5074fd5f722079dfccd92df854400e7dbb045464 Mon Sep 17 00:00:00 2001 From: Jerome Forissier Date: Thu, 25 Sep 2025 17:38:16 +0200 Subject: MAINTAINERS: update NETWORK and NETWORK (LWIP) Add myself as a maintainer of the NETWORK subsystem since: - I have effectively been handling net patches in my patchwork queue and sending pull requests to Tom, - I do have push access to the u-boot-net custodian tree. Also, add u-boot-net as the SCM tree for NETWORK (LWIP) since it is where lwIP-related patches end up too. Signed-off-by: Jerome Forissier CC: Ramon Fried CC: Joe Hershberger CC: Tom Rini --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8dfe2fd6ca0..229de32c70f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1414,6 +1414,7 @@ F: drivers/mmc/ NETWORK M: Joe Hershberger M: Ramon Fried +M: Jerome Forissier S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-net.git F: drivers/net/ @@ -1423,6 +1424,7 @@ F: net/ NETWORK (LWIP) M: Jerome Forissier S: Maintained +T: git https://source.denx.de/u-boot/custodians/u-boot-net.git F: cmd/lwip/ F: cmd/net-lwip.c F: configs/qemu_arm64_lwip_defconfig -- cgit v1.3.1 From 9a20a4fba587956225ebaf3878f48e70a2f42ced Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 26 Sep 2025 09:57:47 +0800 Subject: MAINTAINERS: Update MMC/POWER/FREESCALE QORIQ - Update MMC entry to match 'mmc' using 'N' - Add myself as POWER maintainer for regulator and pmic patches. I have started to handle relevant patches. - Update QORIQ maintainer. Priyanka has moved to work on other stuff, I have been handling this for quite some time. Signed-off-by: Peng Fan --- MAINTAINERS | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 229de32c70f..1db1070d5f8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1223,7 +1223,7 @@ S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-freebsd.git FREESCALE QORIQ -M: Priyanka Jain +M: Peng Fan S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git F: drivers/watchdog/sp805_wdt.c @@ -1410,6 +1410,7 @@ M: Jaehoon Chung S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-mmc.git F: drivers/mmc/ +N: mmc NETWORK M: Joe Hershberger @@ -1517,6 +1518,7 @@ F: test/cmd/pci_mps.c POWER M: Jaehoon Chung +M: Peng Fan S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-pmic.git F: drivers/power/ -- cgit v1.3.1 From 9b45d574af1b64fcd997f08fe702a2d0ecfccbe4 Mon Sep 17 00:00:00 2001 From: Yegor Yefremov Date: Thu, 25 Sep 2025 22:51:50 +0200 Subject: spl: nand: initialize writesize for am335x Initialize mtd->writesize in nand_init() as otherwise nand_page_size() returns 0 and this affects NAND read operations. Signed-off-by: Yegor Yefremov --- drivers/mtd/nand/raw/am335x_spl_bch.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/nand/raw/am335x_spl_bch.c b/drivers/mtd/nand/raw/am335x_spl_bch.c index 4b50f351d35..a77206d3815 100644 --- a/drivers/mtd/nand/raw/am335x_spl_bch.c +++ b/drivers/mtd/nand/raw/am335x_spl_bch.c @@ -212,6 +212,8 @@ void nand_init(void) if (nand_chip.select_chip) nand_chip.select_chip(mtd, 0); + mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE; + /* NAND chip may require reset after power-on */ nand_command(0, 0, 0, NAND_CMD_RESET); } -- cgit v1.3.1 From fa1922846bfbb92a84d5d726ca3846e540a3028f Mon Sep 17 00:00:00 2001 From: Sidharth Seela Date: Thu, 4 Sep 2025 01:50:42 +0530 Subject: doc: board: ti: am335x_evm: Add documentation Link: https://lore.kernel.org/u-boot/20250829191830.GZ124814@bill-the-cat/ Add documentation for config changes required to enable Falcon SD-FAT boot. Signed-off-by: Sidharth Seela Cc: Tom Rini --- doc/board/ti/am335x_evm.rst | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/doc/board/ti/am335x_evm.rst b/doc/board/ti/am335x_evm.rst index 7a3125d705b..40e144948a3 100644 --- a/doc/board/ti/am335x_evm.rst +++ b/doc/board/ti/am335x_evm.rst @@ -354,6 +354,16 @@ first. Falcon Mode: FAT SD cards ------------------------- +Compile with additional changes in config variables in menuconfig: + +:: + + CONFIG_SPL_LEGACY_IMAGE_FORMAT=y # to support non-FIT images + CONFIG_LEGACY_IMAGE_FORMAT=y # if commented then SPL Legacy support stops + # CONFIG_SPL_ENV_IS_NOWHERE is not set + CONFIG_SPL_ENV_IS_IN_FAT=y + + In this case the additional file is written to the filesystem. In this example we assume that the uImage and device tree to be used are already on the FAT filesystem (only the uImage MUST be for this to function -- cgit v1.3.1 From 9585c8f45f44f976c359286d71f1b8f2ae6fdf5f Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Wed, 10 Sep 2025 09:40:39 -0600 Subject: doc: memory: Restore missing diagram When applying the patch that became commit a2d881f5bcd3 ("doc: memory: Add documentation for system RAM") one of the diagrams was missed. Re-add this missing file. Reported-by: Adriano Carvalho Fixes: a2d881f5bcd3 doc: memory: Add documentation for system RAM Signed-off-by: Neha Malcom Francis [trini: Take Neha's original svg and re-apply it] Signed-off-by: Tom Rini --- .gitattributes | 1 - doc/develop/pics/spl_before_reloc.svg | 4 ++++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/.gitattributes b/.gitattributes index 735b13da278..7a7c4163560 100644 --- a/.gitattributes +++ b/.gitattributes @@ -6,4 +6,3 @@ *.ttf binary *.gz binary *.png binary -*.svg binary diff --git a/doc/develop/pics/spl_before_reloc.svg b/doc/develop/pics/spl_before_reloc.svg index e69de29bb2d..f3a42ab7792 100644 --- a/doc/develop/pics/spl_before_reloc.svg +++ b/doc/develop/pics/spl_before_reloc.svg @@ -0,0 +1,4 @@ + + + +
Stack
Global Data
SPL BSS
Heap
0x0
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK
gd->malloc_base
CONFIG_SPL_STACK or CONFIG_SYS_INIT_SP_ADDR
gd, gd->start_addr_sp
CONFIG_SYS_MALLOC_F_LEN
CONFIG_SPL_BSS_MAX_SIZE
Ready RAM (SRAM, locked cache etc.) SPL before relocation
CONFIG_SPL_BSS_START_ADDR
 \ No newline at end of file -- cgit v1.3.1 From e59e10240c69ecae8ef55e4bbb2e9a6cf5c24cef Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 12 Sep 2025 17:02:52 -0600 Subject: doc: Remove README.commands.itest We currently document this command in doc/usage/cmd/itest.rst and this documentation is more comprehensive than the older README file. Delete the older file. Signed-off-by: Tom Rini Reviewed-by: Heinrich Schuchardt --- doc/README.commands.itest | 16 ---------------- 1 file changed, 16 deletions(-) delete mode 100644 doc/README.commands.itest diff --git a/doc/README.commands.itest b/doc/README.commands.itest deleted file mode 100644 index 5e0fe86247a..00000000000 --- a/doc/README.commands.itest +++ /dev/null @@ -1,16 +0,0 @@ -A slow day today so here is a revised itest command with provisional -support for comparing strings as well :-)) - -Now table driven to allow the operators --eq, -ne, -lt, -gt, -le, -ge, ==, !=, <>, <, >, <=, >= - -Uses the expected command modifier for integer compares of width 1, 2 or -4 bytes of .b, .w, .l and the new modifer of .s for a string compare. -String comparison is over the length of the shorter, this hopefully -avoids missing terminators when using an indirect pointer. - -eg. -if itest.l *40000 == 12345678 then; .... -if itest.w *40000 != 1234 then; .... -if itest.b *40000 >= 12 then; .... -if itest.s *40000 -eq hello then; .... -- cgit v1.3.1 From 75ef35b57849c07708934ed820fed4e3e8bbcc83 Mon Sep 17 00:00:00 2001 From: Ricardo Simoes Date: Mon, 15 Sep 2025 16:40:33 +0200 Subject: doc: environment: clarify env precedence Since commit 5cf6a06a it is possible to have both text-based and old-style C environment files. But so far the environment documentation has not reflected this change. This commit fixes that. Signed-off-by: Ricardo Simoes Signed-off-by: Mark Jonas --- doc/usage/environment.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst index 77197d79380..3764f65c221 100644 --- a/doc/usage/environment.rst +++ b/doc/usage/environment.rst @@ -99,9 +99,6 @@ For this particular issue you can use ``DEFAULT_DEVICE_TREE`` instead:: There is no general way to remove quotes. -If CONFIG_ENV_SOURCE_FILE is empty and the default filename is not present, then -the old-style C environment is used instead. See below. - Old-style C environment ----------------------- @@ -114,6 +111,9 @@ Board maintainers are encouraged to migrate to the text-based environment as it is easier to maintain. The distro-board script still requires the old-style environments, so use :doc:`/develop/bootstd/index` instead. +If both the text-based environment file and the old-style C environment are +defined, the variables from the old-style C environment will override those set +in the text-based environment file. List of environment variables ----------------------------- -- cgit v1.3.1 From 0e4fad5f419eb55b0e141c8c229e520724c5b378 Mon Sep 17 00:00:00 2001 From: Anshul Dalal Date: Wed, 17 Sep 2025 18:57:31 +0530 Subject: doc: memory: fix encodings for spl layout diagrams The commit 284ef1bbcefc ("doc: memory: Add documentation for system RAM") added documentation for U-Boot's memory usage along with diagrams showcasing the SPL's memory usage. Although the SVGs for the diagrams were improperly encoded. Therefore, this patch fixes the older SVGs with one's with better encoding and reduced size created using inkscape[1]. [1]: https://inkscape.org/ Reported-by: Alexander Dahl Fixes: 284ef1bbcefc ("doc: memory: Add documentation for system RAM") Signed-off-by: Anshul Dalal --- doc/develop/pics/spl_after_reloc.svg | 297 +++++++++++++++++++++++++- doc/develop/pics/spl_before_reloc.svg | 390 +++++++++++++++++++++++++++++++++- 2 files changed, 679 insertions(+), 8 deletions(-) diff --git a/doc/develop/pics/spl_after_reloc.svg b/doc/develop/pics/spl_after_reloc.svg index 93e3d599526..052ae3fcc8f 100644 --- a/doc/develop/pics/spl_after_reloc.svg +++ b/doc/develop/pics/spl_after_reloc.svg @@ -1,4 +1,293 @@ - - - -
Heap (simple_malloc)
Global Data
Stack
0x0
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN
gd->malloc_base
gd, gd->start_addr_sp
CONFIG_SPL_STACK_R_ADDR
DRAM SPL after relocation
SPL BSS
CONFIG_SPL_BSS_MAX_SIZE
CONFIG_SPL_BSS_START_ADDR
 \ No newline at end of file + + + + + + + + + + + + + + + + + + + + + + + + + + + + DRAM SPL after relocation + + + Heap (simple_malloc) + Global Data + Stack + SPL BSS + + + + + + + gd, gd->start_addr_sp + CONFIG_SPL_STACK_R_ADDR + CONFIG_SPL_BSS_START_ADDR + CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN + 0x0 + + + gd->malloc_base + + + CONFIG_SPL_BSS_MAX_SIZE + + + diff --git a/doc/develop/pics/spl_before_reloc.svg b/doc/develop/pics/spl_before_reloc.svg index f3a42ab7792..7b967097ff9 100644 --- a/doc/develop/pics/spl_before_reloc.svg +++ b/doc/develop/pics/spl_before_reloc.svg @@ -1,4 +1,386 @@ - - - -
Stack
Global Data
SPL BSS
Heap
0x0
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK
gd->malloc_base
CONFIG_SPL_STACK or CONFIG_SYS_INIT_SP_ADDR
gd, gd->start_addr_sp
CONFIG_SYS_MALLOC_F_LEN
CONFIG_SPL_BSS_MAX_SIZE
Ready RAM (SRAM, locked cache etc.) SPL before relocation
CONFIG_SPL_BSS_START_ADDR
 \ No newline at end of file + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Ready RAM (SRAM, locked cache etc.) SPL before relocation + + + Stack + Global Data + Heap + SPL BSS + + + + + + + + + + gd, gd->start_addr_sp + gd->malloc_base + CONFIG_SPL_STACK orCONFIG_SYS_INIT_SP_ADDR + CONFIG_SPL_BSS_START_ADDR + CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK + 0x0 + + + + + CONFIG_SYS_MALLOC_F_LEN + CONFIG_SPL_BSS_MAX_SIZE + + + -- cgit v1.3.1 From 77493c488bafafe7b347f38cc3df7ad395f810e1 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Thu, 18 Sep 2025 18:37:56 -0700 Subject: doc: build: documentation: add description of KDOC_WERROR Describe KDOC_WERROR and recommend when building documentation for a patch submission. Signed-off-by: E Shattow --- doc/build/documentation.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/doc/build/documentation.rst b/doc/build/documentation.rst index 098c96a4c4f..b55a4666643 100644 --- a/doc/build/documentation.rst +++ b/doc/build/documentation.rst @@ -16,6 +16,9 @@ the following dependencies are needed to build the documentation: * texinfo (if building the `Infodoc documentation`_) +When submitting patches for documentation always build with KDOC_WERROR=1 to +treat warnings as errors. + HTML documentation ------------------ -- cgit v1.3.1 From 7b5e66a2b3a2501dcff077fcc26ea55d6c5fba6e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 23 Sep 2025 11:54:29 -0600 Subject: doc: develop: process: Add note about asking for feedback It can be unclear to contributors what to do if they haven't gotten any feedback on patches they have submitted. Add a sentence saying that if they feel it's been too long without any comment, it's OK to reply again. Signed-off-by: Tom Rini --- doc/develop/process.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/doc/develop/process.rst b/doc/develop/process.rst index 0c6fb31e87b..4bfbf0eb9c6 100644 --- a/doc/develop/process.rst +++ b/doc/develop/process.rst @@ -139,7 +139,9 @@ comments). Even a "I have no time now, will look into it later" message is better than nothing. Also, if there are remarks to a patch, these should leave no doubt if they were just comments and the patch will be accepted anyway, or if the patch should be -reworked/resubmitted, or if it was rejected. +reworked/resubmitted, or if it was rejected. However, if a submitter +feels it has been too long since posting their patch and not received +any feedback, it is OK to follow-up and ask. Review Process, Git Tags ------------------------ -- cgit v1.3.1 From c9aad6dbd97b44fccaf761a1f07932ae567d76b7 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Tue, 23 Sep 2025 15:30:50 -0700 Subject: doc: Update mentions of README.fdt-control Update documents 'README.fdt-control' reference to replacement 'control.rst': doc/arch/nios2.rst dts/Makefile Also convert some adjacent pathname mentions to rST links where applicable Fixes: 3e9fddfc4f14 "doc: Move devicetree control doc to rST" Signed-off-by: E Shattow --- doc/arch/nios2.rst | 2 +- doc/develop/devicetree/control.rst | 2 +- doc/develop/driver-model/ethernet.rst | 2 +- doc/develop/spl.rst | 2 +- doc/usage/fit/overlay-fdt-boot.rst | 2 +- dts/Makefile | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/doc/arch/nios2.rst b/doc/arch/nios2.rst index 34a75e7fb00..90b4ddf387b 100644 --- a/doc/arch/nios2.rst +++ b/doc/arch/nios2.rst @@ -13,7 +13,7 @@ Please refer to the link for Linux port and toolchains: http://rocketboards.org/foswiki/view/Documentation/NiosIILinuxUserManual The Nios II port of u-boot is controlled by device tree. Please check -out doc/README.fdt-control. +out :doc:`/develop/devicetree/control`. To add a new board/configuration (eg, mysystem) to u-boot, you will need three files. diff --git a/doc/develop/devicetree/control.rst b/doc/develop/devicetree/control.rst index 0233945f8b6..8811e1d5c23 100644 --- a/doc/develop/devicetree/control.rst +++ b/doc/develop/devicetree/control.rst @@ -282,7 +282,7 @@ U-Boot can be divided into three phases: TPL, SPL and U-Boot proper. The full devicetree is available to U-Boot proper, but normally only a subset (or none at all) is available to TPL and SPL. See 'Pre-Relocation Support' and -'SPL Support' in doc/driver-model/design.rst for more details. +'SPL Support' in :doc:`/develop/driver-model/design` for more details. Using several DTBs in the SPL (SPL_MULTI_DTB_FIT Kconfig option) diff --git a/doc/develop/driver-model/ethernet.rst b/doc/develop/driver-model/ethernet.rst index 73c3a728dbf..2e1df744d4a 100644 --- a/doc/develop/driver-model/ethernet.rst +++ b/doc/develop/driver-model/ethernet.rst @@ -8,7 +8,7 @@ own ethernet device driver. Here we will describe a new pseudo 'APE' driver. Most existing drivers do already - and new network driver MUST - use the U-Boot core driver model. Generic information about this can be found in -doc/driver-model/design.rst, this document will thus focus on the network +:doc:`/develop/driver-model/design`, this document will thus focus on the network specific code parts. Some drivers are still using the old Ethernet interface, differences between the two and hints about porting will be handled at the end. diff --git a/doc/develop/spl.rst b/doc/develop/spl.rst index 7f2eac50806..08b51172014 100644 --- a/doc/develop/spl.rst +++ b/doc/develop/spl.rst @@ -145,7 +145,7 @@ fdtgrep is also used to remove: 'bootph-verify' (VPL)) All the nodes remaining in the SPL devicetree are bound -(see doc/driver-model/design.rst). +(see :doc:`/develop/driver-model/design`). NOTE: U-Boot migrated to a new schema for the u-boot,dm-* tags in 2023. Please update to use the new bootph-* tags as described in the diff --git a/doc/usage/fit/overlay-fdt-boot.rst b/doc/usage/fit/overlay-fdt-boot.rst index 3d7296ad913..d687e98ea2a 100644 --- a/doc/usage/fit/overlay-fdt-boot.rst +++ b/doc/usage/fit/overlay-fdt-boot.rst @@ -13,7 +13,7 @@ that matches the desired configuration. This document focuses on specifically using overlays as part of a FIT image. General information regarding overlays including its syntax and building it -can be found in doc/README.fdt-overlays +can be found in :doc:`/usage/fdt_overlays` Configuration without overlays ------------------------------ diff --git a/dts/Makefile b/dts/Makefile index 86bf8dc2156..fd4ae31a533 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -3,7 +3,7 @@ # Copyright (c) 2011 The Chromium OS Authors. # This Makefile builds the internal U-Boot fdt if CONFIG_OF_CONTROL is -# enabled. See doc/README.fdt-control for more details. +# enabled. See doc/develop/devicetree/control.rst for more details. DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%) ifeq ($(DEVICE_TREE),) -- cgit v1.3.1 From a0fe8cedcbe8c76403a77e57eac228b8f778a3ae Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 24 Sep 2025 16:18:18 +0200 Subject: efi_loader: Cleanup UEFI Variables menu selection There are 3 options listed between choice/endchoice FILE/TEE/NO_STORE. There is no reason to add other config with dependencies between choice/endchoice because they can never be selected because they depends on only that 3 options which can be selected. That's why move additional configuration with dependency below choice section. Signed-off-by: Michal Simek --- lib/efi_loader/Kconfig | 50 +++++++++++++++++++++++++------------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 900113ca3e9..13e44be1d06 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -123,22 +123,6 @@ config EFI_VARIABLE_FILE_STORE Select this option if you want non-volatile UEFI variables to be stored as file /ubootefi.var on the EFI system partition. -config EFI_RT_VOLATILE_STORE - bool "Allow variable runtime services in volatile storage (e.g RAM)" - depends on EFI_VARIABLE_FILE_STORE - help - When EFI variables are stored on file we don't allow SetVariableRT, - since the OS doesn't know how to write that file. At the same time - we copy runtime variables in DRAM and support GetVariableRT - - Enable this option to allow SetVariableRT on the RAM backend of - the EFI variable storage. The OS will be responsible for syncing - the RAM contents to the file, otherwise any changes made during - runtime won't persist reboots. - Authenticated variables are not supported. Note that this will - violate the EFI spec since writing auth variables will return - EFI_INVALID_PARAMETER - config EFI_MM_COMM_TEE bool "UEFI variables storage service via the trusted world" depends on OPTEE @@ -157,6 +141,31 @@ config EFI_MM_COMM_TEE MM buffer. The data is copied by u-boot to the shared buffer before issuing the door bell event. +config EFI_VARIABLE_NO_STORE + bool "Don't persist non-volatile UEFI variables" + help + If you choose this option, non-volatile variables cannot be persisted. + You could still provide non-volatile variables via + EFI_VARIABLES_PRESEED. + +endchoice + +config EFI_RT_VOLATILE_STORE + bool "Allow variable runtime services in volatile storage (e.g RAM)" + depends on EFI_VARIABLE_FILE_STORE + help + When EFI variables are stored on file we don't allow SetVariableRT, + since the OS doesn't know how to write that file. At the same time + we copy runtime variables in DRAM and support GetVariableRT + + Enable this option to allow SetVariableRT on the RAM backend of + the EFI variable storage. The OS will be responsible for syncing + the RAM contents to the file, otherwise any changes made during + runtime won't persist reboots. + Authenticated variables are not supported. Note that this will + violate the EFI spec since writing auth variables will return + EFI_INVALID_PARAMETER + config FFA_SHARED_MM_BUF_SIZE int "Memory size of the shared MM communication buffer" depends on EFI_MM_COMM_TEE && ARM_FFA_TRANSPORT @@ -184,15 +193,6 @@ config FFA_SHARED_MM_BUF_ADDR the MM SP in secure world. It is assumed that the MM SP knows the address of the shared MM communication buffer. -config EFI_VARIABLE_NO_STORE - bool "Don't persist non-volatile UEFI variables" - help - If you choose this option, non-volatile variables cannot be persisted. - You could still provide non-volatile variables via - EFI_VARIABLES_PRESEED. - -endchoice - config EFI_VARIABLES_PRESEED bool "Initial values for UEFI variables" depends on !COMPILE_TEST -- cgit v1.3.1 From 522a58af836598918758b41b110a73f35b9335ba Mon Sep 17 00:00:00 2001 From: Maksim Kiselev Date: Fri, 26 Sep 2025 13:05:26 +0300 Subject: i2c: designware_i2c: Don't warn if reset DT property is not present If reset property is missing in DT, then we get this warning: designware_i2c@0: Can't get reset: -2 Avoid this by checking if reset DT property is present, first. Fixes: 622597dee4f ("i2c: designware: add reset ctrl to driver") Signed-off-by: Maksim Kiselev Reviewed-by: Heiko Schocher Reviewed-by: Peng Fan --- drivers/i2c/designware_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index a54976e7889..8ad716f410e 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -764,7 +764,7 @@ int designware_i2c_of_to_plat(struct udevice *bus) ret = reset_get_bulk(bus, &priv->resets); if (ret) { - if (ret != -ENOTSUPP) + if (ret != -ENOTSUPP && ret != -ENOENT) dev_warn(bus, "Can't get reset: %d\n", ret); } else { reset_deassert_bulk(&priv->resets); -- cgit v1.3.1 From 26efc940c865a04d345ac9d39f71746fc2821da6 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Wed, 17 Jul 2024 23:12:59 +0800 Subject: b4-config: configure `b4` for U-Boot `b4` is a commandline tool to make patch-based development easier. Provide a .b4-config file to match U-Boot's development preference about who is cc'd on patch submission. Signed-off-by: Jiaxun Yang [trini: Reword slightly] --- .b4-config | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 .b4-config diff --git a/.b4-config b/.b4-config new file mode 100644 index 00000000000..6ba10cf9b50 --- /dev/null +++ b/.b4-config @@ -0,0 +1,7 @@ +# Configuration for the `b4` tool +# See https://b4.docs.kernel.org/en/latest/config.html + +[b4] + send-series-to = u-boot@lists.denx.de + send-auto-to-cmd = echo "" + send-auto-cc-cmd = scripts/get_maintainer.pl -- cgit v1.3.1 From a239b0b0b6dbe6a168969b8cd6e600cf85db278d Mon Sep 17 00:00:00 2001 From: "Daniel P. Berrangé" Date: Fri, 26 Sep 2025 10:45:46 +0100 Subject: Add symlink from gpl-2.0.txt to a COPYING file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While it is good that the "Licenses/" directory contains the text for all licenses that are applicable to u-boot code, it is harder to determine at a glance what the default and/or preferred license is. While humans can look at the Licenses/README file, this is not machine parseable, making it tricky for license detection tools to automatically determine/report on the overall / aggregate u-boot license. The project previously had a top level COPYING file containing a short blurb, followed by the GPL license text. This was removed back in commit eca3aeb352c964bdb28b8e191d6326370245e03f when the "Licenses/" directory was introduced. For the benefit of automated tools, it is helpful to retain a top level COPYING file in the repository. Rather than duplicate the license text, however, a symlink from the Licenses/gpl-2.0.txt file should suffice. Signed-off-by: Daniel P. Berrangé Reported-by: Alex Bennée Acked-by: Tom Rini --- COPYING | 1 + 1 file changed, 1 insertion(+) create mode 120000 COPYING diff --git a/COPYING b/COPYING new file mode 120000 index 00000000000..1ed3ba6a13c --- /dev/null +++ b/COPYING @@ -0,0 +1 @@ +Licenses/gpl-2.0.txt \ No newline at end of file -- cgit v1.3.1 From f0e722def6c7b33f5918603e4f5f275d05cc4319 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Fri, 8 Aug 2025 02:40:03 -0700 Subject: arch: arm: dts: agilex5: Disable cache allocation for reads In order to circumvent CCU NOC issue in Agilex5, it is recommended to disable cache allocation for reads. This prevents hang issues caused by CCP (Common Cache Pipe) Fill Done FIFO overflow. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index 402f0bec173..d51a9e2ff7f 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -209,7 +209,7 @@ /* DMIUSMCTCR */ <0x00000300 0x00000001 0x00000003>, <0x00000300 0x00000003 0x00000003>, - <0x00000308 0x00000004 0x0000001F>; + <0x00000308 0x0000000C 0x0000001F>; bootph-all; }; @@ -220,7 +220,7 @@ /* DMIUSMCTCR */ <0x00000300 0x00000001 0x00000003>, <0x00000300 0x00000003 0x00000003>, - <0x00000308 0x00000004 0x0000001F>; + <0x00000308 0x0000000C 0x0000001F>; bootph-all; }; }; -- cgit v1.3.1 From f6dbe41638be6de0071d84073483dc9aaefbdadd Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Mon, 18 Aug 2025 21:17:44 -0700 Subject: arch: arm: dts: stratix10: Add NAND IP to base dtsi Add NAND node to the base stratix10 dtsi file. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- arch/arm/dts/socfpga_stratix10.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index eb82d663204..ea80d1bed15 100644 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -232,6 +232,18 @@ status = "disabled"; }; + nand: nand@ffb90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-denali-nand"; + reg = <0xffb90000 0x10000>, + <0xffb80000 0x1000>; + reg-names = "nand_data", "denali_reg"; + interrupts = <0 97 4>; + resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; + status = "disabled"; + }; + ocram: sram@ffe00000 { compatible = "mmio-sram"; reg = <0xffe00000 0x100000>; -- cgit v1.3.1 From 27e13c9c8d07e6dc626a7f553e7690c6fe4e1cd0 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Mon, 18 Aug 2025 21:25:55 -0700 Subject: arch: arm: socfpga: Remove speed and mode from flash probe Change is to allow the user to choose speed and mode values from dts or the default ones. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- arch/arm/mach-socfpga/misc_arria10.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index c442af02888..7e0f3875b7c 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -214,10 +214,7 @@ int qspi_flash_software_reset(void) /* Get the flash info */ ret = spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS, - CONFIG_SF_DEFAULT_SPEED, - CONFIG_SF_DEFAULT_MODE, &flash); - if (ret) { debug("Failed to initialize SPI flash at "); debug("%u:%u (error %d)\n", CONFIG_SF_DEFAULT_BUS, -- cgit v1.3.1 From 26ffc37787e6107878ac2ec9d46a8c01bb731e89 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Mon, 18 Aug 2025 21:16:04 -0700 Subject: arm: dts: socfpga: Enable driver model for watchdog timer All SoCFPGA platforms are switching to CONFIG_WDT (driver model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Status of watchdog is enabled to assist with this switching. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- arch/arm/dts/socfpga_stratix10_socdk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index e6d8fe6a907..864f4093ef8 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -137,3 +137,7 @@ &usb0 { status = "okay"; }; + +&watchdog0 { + status = "okay"; +}; -- cgit v1.3.1 From 2a7771166ea903726c8d9d919ddcd5526c882459 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Fri, 8 Aug 2025 02:30:41 -0700 Subject: configs: Simplify Agilex7 VAB defconfig To ensure unintentional bugs occurring because of config changes in master defconfig and its VAB variants, VAB defconfig files now include the master defconfig and enable config values specific to VAB functionality only. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- configs/socfpga_agilex_vab_defconfig | 94 +----------------------------------- 1 file changed, 2 insertions(+), 92 deletions(-) diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig index edce692ecd1..4607dc73343 100644 --- a/configs/socfpga_agilex_vab_defconfig +++ b/configs/socfpga_agilex_vab_defconfig @@ -1,93 +1,3 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=400000000 -CONFIG_ARCH_SOCFPGA=y -CONFIG_TEXT_BASE=0x200000 -CONFIG_SYS_MALLOC_LEN=0x500000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 -CONFIG_SF_DEFAULT_MODE=0x2003 -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x200 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="intel/socfpga_agilex_socdk" -CONFIG_DM_RESET=y -CONFIG_SPL_STACK=0xffe3f000 -CONFIG_SPL_TEXT_BASE=0xFFE00000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x3ff00000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 -CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_SYS_LOAD_ADDR=0x02000000 +#include + CONFIG_SOCFPGA_SECURE_VAB_AUTH=y -CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y -CONFIG_IDENT_STRING="socfpga_agilex" -CONFIG_SPL_FS_FAT=y -CONFIG_REMAKE_ELF=y -CONFIG_FIT=y -CONFIG_SPL_FIT_SIGNATURE=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000 -CONFIG_BOOTDELAY=5 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="earlycon" -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot" -CONFIG_SYS_PBSIZE=2082 -CONFIG_SPL_MAX_SIZE=0x40000 -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_HAVE_INIT_STACK=y -CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000 -CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 -CONFIG_SPL_CACHE=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_OF_UPSTREAM=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SPL_ALTERA_SDRAM=y -CONFIG_DWAPB_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_DW=y -CONFIG_SYS_MMC_MAX_BLK_COUNT=256 -CONFIG_MMC_DW=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_MII=y -CONFIG_SYS_NS16550_MEM32=y -CONFIG_SPI=y -CONFIG_CADENCE_QSPI=y -CONFIG_DESIGNWARE_SPI=y -CONFIG_USB=y -CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y -CONFIG_DESIGNWARE_WATCHDOG=y -CONFIG_WDT=y -# CONFIG_SPL_USE_TINY_PRINTF is not set -CONFIG_PANIC_HANG=y -CONFIG_SPL_CRC32=y -- cgit v1.3.1 From 65261e83f3b1fd5e17ff361d167ae035e2954502 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Mon, 18 Aug 2025 21:24:04 -0700 Subject: configs: socfpga: Add CRC32 support CRC32 support for SoC64 devices is added. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- configs/socfpga_agilex_defconfig | 1 + configs/socfpga_n5x_defconfig | 1 + configs/socfpga_stratix10_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 1c3664bc0d7..44c12db08b5 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -38,6 +38,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 +CONFIG_SPL_CRC32=y CONFIG_SPL_CACHE=y CONFIG_SPL_MTD=y CONFIG_SPL_SPI_FLASH_MTD=y diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig index 879556614f6..d501fcddf3d 100644 --- a/configs/socfpga_n5x_defconfig +++ b/configs/socfpga_n5x_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 CONFIG_SPL_CACHE=y +CONFIG_SPL_CRC32=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000 CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 90134d8f3f3..fe191d09714 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -41,6 +41,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 +CONFIG_SPL_CRC32=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C00000 CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" -- cgit v1.3.1 From 3d084d91eda63fde4a159bc866816c9c6b1ae6ce Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Mon, 18 Aug 2025 21:34:40 -0700 Subject: configs: socfpga: Remove SYS_BOOTM_LEN from N5X VAB config Remove the current CONFIG_SYS_BOOTM_LEN in N5X VAB defconfig. Previously, the size was set to 32MB, but due to larger kernel image, 64MB size is required. This 64MB configuration has been set as default in the Kconfig. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- configs/socfpga_n5x_vab_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig index 5d51c4786c0..a4798e2f953 100644 --- a/configs/socfpga_n5x_vab_defconfig +++ b/configs/socfpga_n5x_vab_defconfig @@ -18,7 +18,6 @@ CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x3ff00000 CONFIG_SPL_BSS_MAX_SIZE=0x100000 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SOCFPGA_SECURE_VAB_AUTH=y CONFIG_TARGET_SOCFPGA_N5X_SOCDK=y CONFIG_IDENT_STRING="socfpga_n5x" -- cgit v1.3.1 From 5d2ef97c66f0a432c859cfdf64ef696017619ad6 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Fri, 8 Aug 2025 02:36:59 -0700 Subject: drivers: ddr: altera: Check IOSSM mailbox compatibility Compatibility check of IOSSM mailbox with U-Boot is performed by verifying the mailbox specification version. If check fails, appropriate error message is displayed. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- drivers/ddr/altera/iossm_mailbox.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c index 21f94959a04..2a2f86a650e 100644 --- a/drivers/ddr/altera/iossm_mailbox.c +++ b/drivers/ddr/altera/iossm_mailbox.c @@ -38,6 +38,8 @@ #define IOSSM_STATUS_CMD_RESPONSE_ERROR(n) FIELD_GET(IOSSM_STATUS_CMD_RESPONSE_ERROR_MASK, n) #define IOSSM_STATUS_GENERAL_ERROR_MASK GENMASK(4, 1) #define IOSSM_STATUS_GENERAL_ERROR(n) FIELD_GET(IOSSM_STATUS_GENERAL_ERROR_MASK, n) +#define IOSSM_MAILBOX_SPEC_VERSION_MASK GENMASK(2, 0) +#define IOSSM_MAILBOX_SPEC_VERSION(n) FIELD_GET(IOSSM_MAILBOX_SPEC_VERSION_MASK, n) /* Offset of Mailbox Read-only Registers */ #define IOSSM_MAILBOX_HEADER_OFFSET 0x0 @@ -383,6 +385,23 @@ err: return ret; } +static bool is_mailbox_spec_compatible(struct io96b_info *io96b_ctrl) +{ + u32 mailbox_header; + u8 mailbox_spec_ver; + + mailbox_header = readl(io96b_ctrl->io96b[0].io96b_csr_addr + + IOSSM_MAILBOX_HEADER_OFFSET); + mailbox_spec_ver = IOSSM_MAILBOX_SPEC_VERSION(mailbox_header); + printf("%s: IOSSM mailbox version: %d\n", __func__, mailbox_spec_ver); + + /* for now there are two mailbox spec versions, 0 and 1; only version 1 is compatible */ + if (!mailbox_spec_ver) + return false; + + return true; +} + /* * Initial function to be called to set memory interface IP type and instance ID * IP type and instance ID need to be determined before sending mailbox command @@ -392,6 +411,11 @@ void io96b_mb_init(struct io96b_info *io96b_ctrl) int i, j; u32 mem_intf_info_0, mem_intf_info_1; + if (!is_mailbox_spec_compatible(io96b_ctrl)) { + printf("DDR: Failed to get compatible mailbox version\n"); + hang(); + } + debug("%s: num_instance %d\n", __func__, io96b_ctrl->num_instance); for (i = 0; i < io96b_ctrl->num_instance; i++) { -- cgit v1.3.1 From 63ef1c7a7391e7440bdfbffedd2cc5d9007707cd Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Fri, 8 Aug 2025 02:42:42 -0700 Subject: drivers: ddr: altera: Correct DDR calibration status check Bit 3 of the seq2core register is no longer set to indicate calibration completion. Instead, added polling of the seq2core register until it reads 0b00000111, signaling that the Nios processor has started the calibration process. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- drivers/ddr/altera/sdram_soc64.c | 6 +++--- drivers/ddr/altera/sdram_soc64.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index f8fc92060db..2d0093c591c 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -85,11 +85,11 @@ int emif_reset(struct altera_sdram_plat *plat) debug("DDR: Triggerring emif reset\n"); hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL); - /* if seq2core[3] = 0, we are good */ + /* if seq2core[2:0] = 0b0000_0111, we are good */ ret = wait_for_bit_le32((const void *)(plat->hmc + RSTHANDSHAKESTAT), - DDR_HMC_SEQ2CORE_INT_RESP_MASK, - false, 1000, false); + DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK, + true, 1000, false); if (ret) { printf("DDR: failed to get ack from EMIF\n"); return ret; diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 6031cef560e..6fe0653922c 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -77,7 +77,7 @@ struct altera_sdram_plat { #define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) #define DDR_HMC_RSTHANDSHAKE_MASK 0x0000000f #define DDR_HMC_CORE2SEQ_INT_REQ 0x0000000f -#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) +#define DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK GENMASK(2, 0) #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f #define DDR_HMC_ERRINTEN_INTMASK \ -- cgit v1.3.1 From fb7aa75561b7d05c37dfc9f3d7f73d1838622517 Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Thu, 28 Aug 2025 20:42:59 -0700 Subject: arm: socfpga: Define Use FPGA switch handoff section size for Agilex5 Agilex5 FPGA switch section in the handoff data is larger by 32 bytes than the default value as these extra sections contains I3C0 and I3C1 register offsets and values with 4 bytes each. This requires 4 more times of reading the FPGA switch section of the handoff data to fully populate the handoff data table in the memory during runtime. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index 9ef82cf46c0..b8f2f73e283 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -98,6 +98,8 @@ #define SOC64_HANDOFF_IOCTL_LEN 96 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) #define SOC64_HANDOFF_FPGA_LEN 42 +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SOC64_HANDOFF_FPGA_LEN 44 #else #define SOC64_HANDOFF_FPGA_LEN 40 #endif -- cgit v1.3.1 From f4db066455119d944adda481b5d3415fe79ba858 Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Mon, 22 Sep 2025 18:31:47 -0700 Subject: arm: socfpga: mailbox: Remove CONFIG_CADENCE_QSPI guard from QSPI mailbox API declarations The QSPI mailbox API function declarations (mbox_qspi_close and mbox_qspi_open) in mailbox_s10.h were guarded by CONFIG_CADENCE_QSPI preprocessor conditional. This prevented their prototypes from being visible to code that may use the stub implementations when CONFIG_CADENCE_QSPI is disabled. Remove the CONFIG_CADENCE_QSPI preprocessor conditional so these functions are always declared, regardless of the configuration. This avoids potential build or linkage errors when stubs are used. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h index 2099c51b682..1a461de4819 100644 --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h @@ -398,10 +398,8 @@ int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len); int mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len); int mbox_init(void); -#ifdef CONFIG_CADENCE_QSPI int mbox_qspi_close(void); int mbox_qspi_open(void); -#endif int mbox_reset_cold(void); int mbox_hps_stage_notify(u32 execution_stage); -- cgit v1.3.1 From 36e013490ed40af227f206b2906e30ad877a7854 Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Thu, 14 Aug 2025 20:40:22 -0700 Subject: configs: agilex5: Increase watchdog timeout Linux kernel will fail to boot due to exceeding timeout trying to probe I3C device. Increasing the watchdog timeout 30 seconds will give enough time for Linux to probe the I3C device and will be able to boot up successfully. User is expected to fine tune the watchdog timeout for the complete boot in production. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- configs/socfpga_agilex5_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index b373201dbaa..846c18eed27 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x9ff00000 CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_WATCHDOG_TIMEOUT_MSECS=30000 CONFIG_TARGET_SOCFPGA_AGILEX5_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex5" CONFIG_SPL_FS_FAT=y -- cgit v1.3.1 From 8d28f121d3794613a2ab6799d54f743e439763ab Mon Sep 17 00:00:00 2001 From: Boon Khai Ng Date: Thu, 14 Aug 2025 11:17:39 +0800 Subject: arch: arm: mach-socfpga: smc: Add dcache flushing and invalidation in smc_send_mailbox() Adding the dcache flushing and invalidation in the smc_send_mailbox() At the same time replace the use of u64 with uintptr_t to ensure compatibility across different architectures and correct the pointer arithmetic for buffer end address calculation. Signed-off-by: Mahesh Rao Signed-off-by: Boon Khai Ng Reviewed-by: Tien Fong Chee Reviewed-by: Tien Fong Chee --- arch/arm/mach-socfpga/smc_api.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c index b212a94b321..a531030f5be 100644 --- a/arch/arm/mach-socfpga/smc_api.c +++ b/arch/arm/mach-socfpga/smc_api.c @@ -57,6 +57,7 @@ int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, resp, ARRAY_SIZE(resp)); if (ret == INTEL_SIP_SMC_STATUS_OK && resp_buf && resp_buf_len) { + invalidate_dcache_range((uintptr_t)resp_buf, (uintptr_t)(resp_buf + *resp_buf_len)); if (!resp[0]) *resp_buf_len = resp[1]; } -- cgit v1.3.1 From c4e9554015ebe919a480a54e508461af7a3e9fc8 Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Mon, 8 Sep 2025 19:11:14 -0700 Subject: include: dt-bindings: clk: agilex: Add Agilex clock definitions header file Introduce header file to define the clock indexes for the Agilex platform. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- include/dt-bindings/clock/agilex-clock.h | 71 ++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 include/dt-bindings/clock/agilex-clock.h diff --git a/include/dt-bindings/clock/agilex-clock.h b/include/dt-bindings/clock/agilex-clock.h new file mode 100644 index 00000000000..a6252180516 --- /dev/null +++ b/include/dt-bindings/clock/agilex-clock.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2025 Altera Corporation + */ + +#ifndef __AGILEX_CLOCK_H +#define __AGILEX_CLOCK_H + +/* fixed rate clocks */ +#define AGILEX_OSC1 0 +#define AGILEX_CB_INTOSC_HS_DIV2_CLK 1 +#define AGILEX_CB_INTOSC_LS_CLK 2 +#define AGILEX_L4_SYS_FREE_CLK 3 +#define AGILEX_F2S_FREE_CLK 4 + +/* PLL clocks */ +#define AGILEX_MAIN_PLL_CLK 5 +#define AGILEX_MAIN_PLL_C0_CLK 6 +#define AGILEX_MAIN_PLL_C1_CLK 7 +#define AGILEX_MAIN_PLL_C2_CLK 8 +#define AGILEX_MAIN_PLL_C3_CLK 9 +#define AGILEX_PERIPH_PLL_CLK 10 +#define AGILEX_PERIPH_PLL_C0_CLK 11 +#define AGILEX_PERIPH_PLL_C1_CLK 12 +#define AGILEX_PERIPH_PLL_C2_CLK 13 +#define AGILEX_PERIPH_PLL_C3_CLK 14 +#define AGILEX_MPU_FREE_CLK 15 +#define AGILEX_MPU_CCU_CLK 16 +#define AGILEX_BOOT_CLK 17 + +/* fixed factor clocks */ +#define AGILEX_L3_MAIN_FREE_CLK 18 +#define AGILEX_NOC_FREE_CLK 19 +#define AGILEX_S2F_USR0_CLK 20 +#define AGILEX_NOC_CLK 21 +#define AGILEX_EMAC_A_FREE_CLK 22 +#define AGILEX_EMAC_B_FREE_CLK 23 +#define AGILEX_EMAC_PTP_FREE_CLK 24 +#define AGILEX_GPIO_DB_FREE_CLK 25 +#define AGILEX_SDMMC_FREE_CLK 26 +#define AGILEX_S2F_USER0_FREE_CLK 27 +#define AGILEX_S2F_USER1_FREE_CLK 28 +#define AGILEX_PSI_REF_FREE_CLK 29 + +/* Gate clocks */ +#define AGILEX_MPU_CLK 30 +#define AGILEX_MPU_PERIPH_CLK 31 +#define AGILEX_L4_MAIN_CLK 32 +#define AGILEX_L4_MP_CLK 33 +#define AGILEX_L4_SP_CLK 34 +#define AGILEX_CS_AT_CLK 35 +#define AGILEX_CS_TRACE_CLK 36 +#define AGILEX_CS_PDBG_CLK 37 +#define AGILEX_CS_TIMER_CLK 38 +#define AGILEX_S2F_USER0_CLK 39 +#define AGILEX_EMAC0_CLK 40 +#define AGILEX_EMAC1_CLK 41 +#define AGILEX_EMAC2_CLK 42 +#define AGILEX_EMAC_PTP_CLK 43 +#define AGILEX_GPIO_DB_CLK 44 +#define AGILEX_NAND_CLK 45 +#define AGILEX_PSI_REF_CLK 46 +#define AGILEX_S2F_USER1_CLK 47 +#define AGILEX_SDMMC_CLK 48 +#define AGILEX_SPI_M_CLK 49 +#define AGILEX_USB_CLK 50 +#define AGILEX_NAND_X_CLK 51 +#define AGILEX_NAND_ECC_CLK 52 +#define AGILEX_NUM_CLKS 53 + +#endif /* __AGILEX_CLOCK_H */ -- cgit v1.3.1 From 38d49808d4cd51e8972bfe7478db03325118d553 Mon Sep 17 00:00:00 2001 From: Boon Khai Ng Date: Thu, 14 Aug 2025 11:17:40 +0800 Subject: cache: Check dcache availability before calling cache functions When the data cache (dcache) is disabled, calling related status functions can lead to compilation errors due to undefined references. Adding a !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) check before invoking dcache_status() (used in common/memsize.c:get_ram_size()) and mmu_status() (from arch/arm/include/asm/io.h). Without this check, builds with dcache disabled will fail to compile. Signed-off-by: Boon Khai Ng Reviewed-by: Tom Rini --- arch/arm/include/asm/io.h | 28 ++++++++++++++++------------ common/memsize.c | 5 ++++- 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 85ec0e6937e..cebed7397d4 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -386,12 +386,14 @@ void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count) count--; } - if (mmu_status()) { - while (count >= 8) { - *(u64 *)to = __raw_readq(from); - from += 8; - to += 8; - count -= 8; + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { + if (mmu_status()) { + while (count >= 8) { + *(u64 *)to = __raw_readq(from); + from += 8; + to += 8; + count -= 8; + } } } @@ -416,12 +418,14 @@ void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count) count--; } - if (mmu_status()) { - while (count >= 8) { - __raw_writeq(*(u64 *)from, to); - from += 8; - to += 8; - count -= 8; + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { + if (mmu_status()) { + while (count >= 8) { + __raw_writeq(*(u64 *)from, to); + from += 8; + to += 8; + count -= 8; + } } } diff --git a/common/memsize.c b/common/memsize.c index 86109579c95..3c3ae6f1eba 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -52,7 +52,10 @@ long get_ram_size(long *base, long maxsize) long val; long size; int i = 0; - int dcache_en = dcache_status(); + int dcache_en = 0; + + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + dcache_en = dcache_status(); for (cnt = (maxsize / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) { addr = base + cnt; /* pointer arith! */ -- cgit v1.3.1 From 022b2159b5d24556b7623906de147260fe46e0f2 Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Mon, 8 Sep 2025 19:11:15 -0700 Subject: drivers: clk: agilex: Support for enable/disable API Update Agilex clock driver to support enabling or disabling the peripheral clocks via clock driver model APIs. The caller will pass the clock ID to this driver and the driver will then proceed to manipulate the desired bit in the Agilex clock manager peripheral PLL register based on the given clock ID. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- drivers/clk/altera/clk-agilex.c | 120 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/altera/clk-agilex.h | 20 +++++++ 2 files changed, 140 insertions(+) diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index 242740a4b00..46b04895cc5 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -22,6 +22,8 @@ DECLARE_GLOBAL_DATA_PTR; struct socfpga_clk_plat { void __iomem *regs; + int pllgrp; + int bitmask; }; /* @@ -643,8 +645,125 @@ static ulong socfpga_clk_get_rate(struct clk *clk) } } +static int bitmask_from_clk_id(struct clk *clk) +{ + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev); + + switch (clk->id) { + case AGILEX_MPU_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK; + break; + case AGILEX_L4_MAIN_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK; + break; + case AGILEX_L4_MP_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK; + break; + case AGILEX_L4_SP_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK; + break; + case AGILEX_CS_AT_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK; + break; + case AGILEX_CS_TRACE_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK; + break; + case AGILEX_CS_PDBG_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK; + break; + case AGILEX_CS_TIMER_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK; + break; + case AGILEX_S2F_USER0_CLK: + plat->pllgrp = CLKMGR_MAINPLL_EN; + plat->bitmask = CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK; + break; + case AGILEX_EMAC0_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK; + break; + case AGILEX_EMAC1_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK; + break; + case AGILEX_EMAC2_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK; + break; + case AGILEX_EMAC_PTP_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK; + break; + case AGILEX_GPIO_DB_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK; + break; + case AGILEX_SDMMC_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK; + break; + case AGILEX_S2F_USER1_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK; + break; + case AGILEX_PSI_REF_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK; + break; + case AGILEX_USB_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_USBCLK_MASK; + break; + case AGILEX_SPI_M_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK; + break; + case AGILEX_NAND_CLK: + plat->pllgrp = CLKMGR_PERPLL_EN; + plat->bitmask = CLKMGR_PERPLLGRP_EN_NANDCLK_MASK; + break; + default: + return -ENXIO; + } + + return 0; +} + static int socfpga_clk_enable(struct clk *clk) { + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev); + uintptr_t base_addr = (uintptr_t)plat->regs; + int ret; + + ret = bitmask_from_clk_id(clk); + if (ret) + return ret; + + setbits_le32(base_addr + plat->pllgrp, plat->bitmask); + + return 0; +} + +static int socfpga_clk_disable(struct clk *clk) +{ + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev); + uintptr_t base_addr = (uintptr_t)plat->regs; + int ret; + + ret = bitmask_from_clk_id(clk); + if (ret) + return ret; + + clrbits_le32(base_addr + plat->pllgrp, plat->bitmask); + return 0; } @@ -672,6 +791,7 @@ static int socfpga_clk_of_to_plat(struct udevice *dev) static struct clk_ops socfpga_clk_ops = { .enable = socfpga_clk_enable, + .disable = socfpga_clk_disable, .get_rate = socfpga_clk_get_rate, }; diff --git a/drivers/clk/altera/clk-agilex.h b/drivers/clk/altera/clk-agilex.h index b3e8841a512..be639957940 100644 --- a/drivers/clk/altera/clk-agilex.h +++ b/drivers/clk/altera/clk-agilex.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019 Intel Corporation + * Copyright (C) 2025 Altera Corporation */ #ifndef _CLK_AGILEX_ @@ -210,7 +211,26 @@ struct cm_config { #define CLKMGR_LOSTLOCK_SET_MASK BIT(0) +#define CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK BIT(0) +#define CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK BIT(1) +#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK BIT(2) +#define CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK BIT(3) +#define CLKMGR_MAINPLLGRP_EN_CSCLK_MASK BIT(4) +#define CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK BIT(5) +#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK BIT(6) + +#define CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK BIT(0) +#define CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK BIT(1) +#define CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK BIT(2) +#define CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK BIT(3) +#define CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK BIT(4) #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5) +#define CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK BIT(6) +#define CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK BIT(7) +#define CLKMGR_PERPLLGRP_EN_USBCLK_MASK BIT(8) +#define CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK BIT(9) +#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK BIT(10) + #define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET 26 #define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK BIT(26) #define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET 27 -- cgit v1.3.1 From 190a339ae345c5653aca5557e713af6a9227f29e Mon Sep 17 00:00:00 2001 From: Boon Khai Ng Date: Thu, 14 Aug 2025 11:17:41 +0800 Subject: configs: agilex5: Enable config SPL_SYS_DCACHE_OFF Add SPL_SYS_DCACHE_OFF to Agilex5 defconfig to disable data cache for SPL Signed-off-by: Tanmay Kathpalia Signed-off-by: Boon Khai Ng Reviewed-by: Tien Fong Chee --- configs/socfpga_agilex5_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 846c18eed27..24c95eb39d5 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -46,6 +46,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x9fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 CONFIG_SPL_CACHE=y +CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_SPL_MTD=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_SPI_FLASH_MTD=y -- cgit v1.3.1 From ab27182cac8ff14621c73c6609aaf3036fab1c0a Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Mon, 8 Sep 2025 19:11:16 -0700 Subject: mmc: socfpga_dw_mmc: Enable/disable SDMMC clock via API Update the driver to enable or disable the SDMMC clock via clock driver model API instead of doing it in the driver itself. This allows for scalability of the driver for various SoCFPGA devices. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- drivers/mmc/socfpga_dw_mmc.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 3b86bc9b18c..db4e0129c2e 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -29,7 +29,9 @@ struct socfpga_dwmci_plat { /* socfpga implmentation specific driver private data */ struct dwmci_socfpga_priv_data { + struct udevice *dev; struct dwmci_host host; + struct clk mmc_clk_ciu; unsigned int drvsel; unsigned int smplsel; }; @@ -51,28 +53,23 @@ static void socfpga_dwmci_reset(struct udevice *dev) static int socfpga_dwmci_clksel(struct dwmci_host *host) { struct dwmci_socfpga_priv_data *priv = host->priv; + int ret; + u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) | ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT); - /* Get clock manager base address */ - struct udevice *clkmgr_dev; - int ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@ffd10000", &clkmgr_dev); - + ret = clk_get_by_name(priv->dev, "ciu", &priv->mmc_clk_ciu); if (ret) { - printf("Failed to get clkmgr device: %d\n", ret); + debug("%s: Failed to get SDMMC clock from dts\n", __func__); return ret; } - fdt_addr_t clkmgr_base = dev_read_addr(clkmgr_dev); - - if (clkmgr_base == FDT_ADDR_T_NONE) { - printf("Failed to read base address from clkmgr DT node\n"); - return -EINVAL; - } - /* Disable SDMMC clock. */ - clrbits_le32(clkmgr_base + CLKMGR_PERPLL_EN, - CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); + ret = clk_disable(&priv->mmc_clk_ciu); + if (ret) { + printf("%s: Failed to disable SDMMC clock\n", __func__); + return ret; + } debug("%s: drvsel %d smplsel %d\n", __func__, priv->drvsel, priv->smplsel); @@ -92,8 +89,11 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host) #endif /* Enable SDMMC clock */ - setbits_le32(clkmgr_base + CLKMGR_PERPLL_EN, - CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); + ret = clk_enable(&priv->mmc_clk_ciu); + if (ret) { + printf("%s: Failed to enable SDMMC clock\n", __func__); + return ret; + } return 0; } @@ -169,6 +169,7 @@ static int socfpga_dwmmc_probe(struct udevice *dev) struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; + priv->dev = dev; int ret; ret = socfpga_dwmmc_get_clk_rate(dev); -- cgit v1.3.1 From 924a9fc4021cf4899c6b1e26d28336f412aa296f Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Wed, 10 Sep 2025 22:21:11 -0700 Subject: drivers: clk: agilex: Fix EMAC clock source selection Fix the incorrect bit masking and bit shift used to compute EMAC control which in turn is used to select EMAC clock from EMAC source A or B. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- drivers/clk/altera/clk-agilex.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index 46b04895cc5..19c4e8220db 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -546,14 +546,14 @@ static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id) /* Get EMAC clock source */ ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL); if (emac_id == AGILEX_EMAC0_CLK) - ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) & - CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK; + ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK) >> + CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET; else if (emac_id == AGILEX_EMAC1_CLK) - ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) & - CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK; + ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK) >> + CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET; else if (emac_id == AGILEX_EMAC2_CLK) - ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) & - CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK; + ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK) >> + CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET; else return 0; -- cgit v1.3.1 From 2ff686bcfd14689de3d6a6da9c35340449025ef5 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Wed, 10 Sep 2025 22:21:12 -0700 Subject: drivers: clk: agilex: Use FIELD_GET during EMAC clock selection FIELD_GET() macro is used during EMAC clock source selection for better code readability and maintainability. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- drivers/clk/altera/clk-agilex.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index 19c4e8220db..fdbf834bb2f 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -546,14 +547,11 @@ static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id) /* Get EMAC clock source */ ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL); if (emac_id == AGILEX_EMAC0_CLK) - ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK) >> - CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET; + ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK, ctl); else if (emac_id == AGILEX_EMAC1_CLK) - ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK) >> - CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET; + ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK, ctl); else if (emac_id == AGILEX_EMAC2_CLK) - ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK) >> - CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET; + ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK, ctl); else return 0; -- cgit v1.3.1 From e3a11a240add752f092092fd514af68f441aab31 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Wed, 24 Sep 2025 00:49:08 -0700 Subject: arch: arm: dts: Enable USB3.1 for Agilex5 USB 3.1 node is enabled for Agilex5. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- arch/arm/dts/socfpga_agilex5_socdk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts index 2ab143e38f8..886cc89fdb6 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk.dts +++ b/arch/arm/dts/socfpga_agilex5_socdk.dts @@ -87,6 +87,10 @@ disable-over-current; }; +&usb31 { + status = "okay"; +}; + &watchdog0 { status = "okay"; }; -- cgit v1.3.1 From 61c4768d83fc3f7ce21b151a6e1b02397d788926 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Wed, 24 Sep 2025 00:49:09 -0700 Subject: configs: Enable USB DWC3 host drivers for Agilex5 Required USB DWC3 host driver configurations are enabled for Agilex5. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- configs/socfpga_agilex5_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 24c95eb39d5..da9241b765a 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -103,7 +103,9 @@ CONFIG_TIMER=y CONFIG_DESIGNWARE_APB_TIMER=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set -- cgit v1.3.1 From 060ed1bbbe0fd1a8583d09d7766cf3f194b23edc Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Wed, 24 Sep 2025 00:49:10 -0700 Subject: configs: Increase USB Hub debounce timeout in Agilex5 Some legacy USB mass storage devices during connection were observed to have debounce issues. Hence, increasing the default USB Hub debounce timeout value to handle this issue for devices connected to Agilex5 boards. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- configs/socfpga_agilex5_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index da9241b765a..9ca1910d53f 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -106,6 +106,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC2=y CONFIG_USB_DWC3=y +CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=3000 CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set -- cgit v1.3.1 From da57acb4c396cfc978c0652fec9dfb17a4f67ad8 Mon Sep 17 00:00:00 2001 From: Naresh Kumar Ravulapalli Date: Wed, 24 Sep 2025 00:49:11 -0700 Subject: arch: arm: socfpga: Configure USB3 System Manager registers For successful reset staggering pulse operation, reset pulse override bit is set. Port overcurrent bit 1, which in reality reflects PIPE power present signal is set to avoid giving false information of Vbus status to HPS controller. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee --- .../include/mach/system_manager_soc64.h | 12 +++++++++++ arch/arm/mach-socfpga/system_manager_soc64.c | 24 ++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 054a28d845d..f768a3a55cb 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -33,6 +33,7 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_ECC_INTMASK_CLR 0x98 #define SYSMGR_SOC64_ECC_INTMASK_SERR 0x9C #define SYSMGR_SOC64_ECC_INTMASK_DERR 0xA0 +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0 0x1F0 #define SYSMGR_SOC64_MPFE_CONFIG 0x228 #define SYSMGR_SOC64_BOOT_SCRATCH_POR0 0x258 #define SYSMGR_SOC64_BOOT_SCRATCH_POR1 0x25C @@ -47,6 +48,17 @@ void populate_sysmgr_pinmux(void); #define ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK BIT(0) #define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_USER_MODE_MASK BIT(0) #define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_MASK BIT(1) + +/* + * Bits for SYSMGR_SOC64_USB3_MISC_CTRL_REG0 + * Bits[14:13] Port Overcurrent + * Bit[12] Reset Pulse Override + */ +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_PORT_OVR_CURR GENMASK(14, 13) +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_RESET_PUL_OVR BIT(12) +#define SET_USB3_MISC_CTRL_REG0_PORT_RESET_PUL_OVR 1 +/* BIT 1 actually reflects PIPE power present signal */ +#define SET_USB3_MISC_CTRL_REG0_PORT_OVR_CURR_BIT_1 2 #else #define SYSMGR_SOC64_NAND_AXUSER 0x5c #define SYSMGR_SOC64_DMA_L3MASTER 0x74 diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c b/arch/arm/mach-socfpga/system_manager_soc64.c index 4b42158be9d..913f93c8f94 100644 --- a/arch/arm/mach-socfpga/system_manager_soc64.c +++ b/arch/arm/mach-socfpga/system_manager_soc64.c @@ -8,9 +8,29 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +/* + * Setting RESET_PULSE_OVERRIDE bit for successful reset staggering pulse + * generation and setting PORT_OVERCURRENT bit so that until we turn on the + * Vbus, it doesn't give false information about Vbus to the HPS controller. + */ +static void sysmgr_config_usb3(void) +{ + u32 reg_val = 0; + + reg_val = readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_USB3_MISC_CTRL_REG0); + reg_val |= FIELD_PREP(SYSMGR_SOC64_USB3_MISC_CTRL_REG0_RESET_PUL_OVR, + SET_USB3_MISC_CTRL_REG0_PORT_RESET_PUL_OVR); + reg_val |= FIELD_PREP(SYSMGR_SOC64_USB3_MISC_CTRL_REG0_PORT_OVR_CURR, + SET_USB3_MISC_CTRL_REG0_PORT_OVR_CURR_BIT_1); + writel(reg_val, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_USB3_MISC_CTRL_REG0); +} +#endif + /* * Configure all the pin muxes */ @@ -18,6 +38,10 @@ void sysmgr_pinmux_init(void) { populate_sysmgr_pinmux(); populate_sysmgr_fpgaintf_module(); + +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + sysmgr_config_usb3(); +#endif } /* -- cgit v1.3.1