From bacb61a06fd36661959ee8109e50f7e6eda76be1 Mon Sep 17 00:00:00 2001 From: Hiago De Franco Date: Thu, 23 Jul 2026 11:44:34 -0300 Subject: board: sophgo: move ethernet driver to common directory This will make easier for future boards to reuse the same driver (e.g. Milk-V Duo 256MB). Signed-off-by: Hiago De Franco Acked-by: Leo Yu-Chi Liang --- board/sophgo/common/ethernet.c | 79 ++++++++++++++++++++++++++++++++++++++ board/sophgo/common/ethernet.h | 11 ++++++ board/sophgo/milkv_duo/MAINTAINERS | 1 + board/sophgo/milkv_duo/Makefile | 2 +- board/sophgo/milkv_duo/board.c | 2 +- board/sophgo/milkv_duo/ethernet.c | 79 -------------------------------------- board/sophgo/milkv_duo/ethernet.h | 11 ------ 7 files changed, 93 insertions(+), 92 deletions(-) create mode 100644 board/sophgo/common/ethernet.c create mode 100644 board/sophgo/common/ethernet.h delete mode 100644 board/sophgo/milkv_duo/ethernet.c delete mode 100644 board/sophgo/milkv_duo/ethernet.h diff --git a/board/sophgo/common/ethernet.c b/board/sophgo/common/ethernet.c new file mode 100644 index 00000000000..e997ce1037f --- /dev/null +++ b/board/sophgo/common/ethernet.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024, Kongyang Liu + */ + +#include +#include +#include + +#define REG_EPHY_TOP_WRAP (u32 *)0x03009800 +#define REG_EPHY_BASE (u32 *)0x03009000 + +#define REG_EPHY_CTL REG_EPHY_TOP_WRAP +#define REG_EPHY_APB_RW_SEL REG_EPHY_TOP_WRAP + 1 + +/* Page 0 register */ +#define REG_PHY_ID1 REG_EPHY_BASE + MII_PHYSID1 +#define REG_PHY_ID2 REG_EPHY_BASE + MII_PHYSID2 +#define REG_PHY_PAGE_SEL REG_EPHY_BASE + 0x1f + +/* Page 5 register */ +#define REG_PD_EN_CTL REG_EPHY_BASE + 0x10 + +/* REG_EPHY_CTL */ +#define REG_EPHY_SHUTDOWN BIT(0) +#define REG_EPHY_ANA_RST_N BIT(1) +#define REG_EPHY_DIG_RST_N BIT(2) +#define REG_EPHY_MAIN_RST_N BIT(3) + +/* REG_PD_EN_CTL */ +#define REG_EN_ETH_TXRT BIT(0) +#define REG_EN_ETH_CLK100M BIT(1) +#define REG_EN_ETH_CLK125M BIT(2) +#define REG_EN_ETH_PLL_LCKDET BIT(3) +#define REG_EN_ETH_RXADC BIT(4) +#define REG_EN_ETH_RXPGA BIT(5) +#define REG_EN_ETH_RXRT BIT(6) +#define REG_EN_ETH_TXCROSSOVER BIT(7) +#define REG_PD_ETH_PLL BIT(8) +#define REG_PD_ETH_TXDAC BIT(9) +#define REG_PD_ETH_TXDACBST BIT(10) +#define REG_PD_ETH_TXECHO BIT(11) +#define REG_PD_ETH_TXDRV_NMOS BIT(12) +#define REG_PD_ETH_TXLDO BIT(13) + +void cv1800b_ephy_init(void) +{ + u32 reg; + u32 phy_id = 1; + + /* enable direct memory access for phy register */ + writel(1, REG_EPHY_APB_RW_SEL); + + reg = readl(REG_EPHY_CTL); + reg &= ~REG_EPHY_SHUTDOWN; + reg |= REG_EPHY_ANA_RST_N | REG_EPHY_DIG_RST_N | REG_EPHY_MAIN_RST_N; + writel(reg, REG_EPHY_CTL); + + /* switch to page 5 */ + writel(5 << 8, REG_PHY_PAGE_SEL); + reg = readl(REG_PD_EN_CTL); + reg &= ~(REG_PD_ETH_TXLDO | REG_PD_ETH_TXDRV_NMOS | REG_PD_ETH_TXDAC | REG_PD_ETH_PLL); + reg |= REG_EN_ETH_TXRT | REG_EN_ETH_CLK100M | REG_EN_ETH_CLK125M + | REG_EN_ETH_PLL_LCKDET | REG_EN_ETH_RXADC | REG_EN_ETH_RXPGA | REG_EN_ETH_RXRT; + writel(reg, REG_PD_EN_CTL); + + /* switch to page 0 */ + writel(0 << 8, REG_PHY_PAGE_SEL); + /* + * As the phy_id in the cv1800b PHY register is initialized to 0, it + * is necessary to manually initialize the phy_id to an arbitrary + * value so that it could corresponds to the generic PHY driver. + */ + writel(phy_id >> 16, REG_PHY_ID1); + writel(phy_id & 0xffff, REG_PHY_ID2); + + /* switch to MDIO control */ + writel(0, REG_EPHY_APB_RW_SEL); +} diff --git a/board/sophgo/common/ethernet.h b/board/sophgo/common/ethernet.h new file mode 100644 index 00000000000..7b21f1b0f66 --- /dev/null +++ b/board/sophgo/common/ethernet.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024, Kongyang Liu + */ + +#ifndef __CV1800B_ETHERNET_H +#define __CV1800B_ETHERNET_H + +void cv1800b_ephy_init(void); + +#endif diff --git a/board/sophgo/milkv_duo/MAINTAINERS b/board/sophgo/milkv_duo/MAINTAINERS index 651a0592f7a..6941dc5b376 100644 --- a/board/sophgo/milkv_duo/MAINTAINERS +++ b/board/sophgo/milkv_duo/MAINTAINERS @@ -2,5 +2,6 @@ Milk-V Duo M: Kongyang Liu S: Maintained F: board/sophgo/milkv_duo/ +F: board/sophgo/common/ F: configs/milkv_duo_defconfig F: doc/board/sophgo/milkv_duo.rst diff --git a/board/sophgo/milkv_duo/Makefile b/board/sophgo/milkv_duo/Makefile index 18ada7d72ff..aa321d15687 100644 --- a/board/sophgo/milkv_duo/Makefile +++ b/board/sophgo/milkv_duo/Makefile @@ -3,4 +3,4 @@ # Copyright (c) 2024, Kongyang Liu obj-y += board.o -obj-$(CONFIG_NET_LEGACY) += ethernet.o +obj-$(CONFIG_NET_LEGACY) += ../common/ethernet.o diff --git a/board/sophgo/milkv_duo/board.c b/board/sophgo/milkv_duo/board.c index f0944859b58..34339c42925 100644 --- a/board/sophgo/milkv_duo/board.c +++ b/board/sophgo/milkv_duo/board.c @@ -5,7 +5,7 @@ #include -#include "ethernet.h" +#include "../common/ethernet.h" int board_init(void) { diff --git a/board/sophgo/milkv_duo/ethernet.c b/board/sophgo/milkv_duo/ethernet.c deleted file mode 100644 index e997ce1037f..00000000000 --- a/board/sophgo/milkv_duo/ethernet.c +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2024, Kongyang Liu - */ - -#include -#include -#include - -#define REG_EPHY_TOP_WRAP (u32 *)0x03009800 -#define REG_EPHY_BASE (u32 *)0x03009000 - -#define REG_EPHY_CTL REG_EPHY_TOP_WRAP -#define REG_EPHY_APB_RW_SEL REG_EPHY_TOP_WRAP + 1 - -/* Page 0 register */ -#define REG_PHY_ID1 REG_EPHY_BASE + MII_PHYSID1 -#define REG_PHY_ID2 REG_EPHY_BASE + MII_PHYSID2 -#define REG_PHY_PAGE_SEL REG_EPHY_BASE + 0x1f - -/* Page 5 register */ -#define REG_PD_EN_CTL REG_EPHY_BASE + 0x10 - -/* REG_EPHY_CTL */ -#define REG_EPHY_SHUTDOWN BIT(0) -#define REG_EPHY_ANA_RST_N BIT(1) -#define REG_EPHY_DIG_RST_N BIT(2) -#define REG_EPHY_MAIN_RST_N BIT(3) - -/* REG_PD_EN_CTL */ -#define REG_EN_ETH_TXRT BIT(0) -#define REG_EN_ETH_CLK100M BIT(1) -#define REG_EN_ETH_CLK125M BIT(2) -#define REG_EN_ETH_PLL_LCKDET BIT(3) -#define REG_EN_ETH_RXADC BIT(4) -#define REG_EN_ETH_RXPGA BIT(5) -#define REG_EN_ETH_RXRT BIT(6) -#define REG_EN_ETH_TXCROSSOVER BIT(7) -#define REG_PD_ETH_PLL BIT(8) -#define REG_PD_ETH_TXDAC BIT(9) -#define REG_PD_ETH_TXDACBST BIT(10) -#define REG_PD_ETH_TXECHO BIT(11) -#define REG_PD_ETH_TXDRV_NMOS BIT(12) -#define REG_PD_ETH_TXLDO BIT(13) - -void cv1800b_ephy_init(void) -{ - u32 reg; - u32 phy_id = 1; - - /* enable direct memory access for phy register */ - writel(1, REG_EPHY_APB_RW_SEL); - - reg = readl(REG_EPHY_CTL); - reg &= ~REG_EPHY_SHUTDOWN; - reg |= REG_EPHY_ANA_RST_N | REG_EPHY_DIG_RST_N | REG_EPHY_MAIN_RST_N; - writel(reg, REG_EPHY_CTL); - - /* switch to page 5 */ - writel(5 << 8, REG_PHY_PAGE_SEL); - reg = readl(REG_PD_EN_CTL); - reg &= ~(REG_PD_ETH_TXLDO | REG_PD_ETH_TXDRV_NMOS | REG_PD_ETH_TXDAC | REG_PD_ETH_PLL); - reg |= REG_EN_ETH_TXRT | REG_EN_ETH_CLK100M | REG_EN_ETH_CLK125M - | REG_EN_ETH_PLL_LCKDET | REG_EN_ETH_RXADC | REG_EN_ETH_RXPGA | REG_EN_ETH_RXRT; - writel(reg, REG_PD_EN_CTL); - - /* switch to page 0 */ - writel(0 << 8, REG_PHY_PAGE_SEL); - /* - * As the phy_id in the cv1800b PHY register is initialized to 0, it - * is necessary to manually initialize the phy_id to an arbitrary - * value so that it could corresponds to the generic PHY driver. - */ - writel(phy_id >> 16, REG_PHY_ID1); - writel(phy_id & 0xffff, REG_PHY_ID2); - - /* switch to MDIO control */ - writel(0, REG_EPHY_APB_RW_SEL); -} diff --git a/board/sophgo/milkv_duo/ethernet.h b/board/sophgo/milkv_duo/ethernet.h deleted file mode 100644 index 7b21f1b0f66..00000000000 --- a/board/sophgo/milkv_duo/ethernet.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2024, Kongyang Liu - */ - -#ifndef __CV1800B_ETHERNET_H -#define __CV1800B_ETHERNET_H - -void cv1800b_ephy_init(void); - -#endif -- cgit v1.3.1