From 2247b8aa20b117b1df3a7be295771c5ac3a7fb6e Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 9 Nov 2024 21:04:09 +0000 Subject: rockchip: rk3288: Use rk3288-power.h from dts/upstream power/rk3288-power.h in include/dt-bindings is identical to the version in dts/upstream, remove the copy from include/dt-bindings to only use the version from dts/upstream. No functional change to board DTs is intended with this removal. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- include/dt-bindings/power/rk3288-power.h | 32 -------------------------------- 1 file changed, 32 deletions(-) delete mode 100644 include/dt-bindings/power/rk3288-power.h diff --git a/include/dt-bindings/power/rk3288-power.h b/include/dt-bindings/power/rk3288-power.h deleted file mode 100644 index f710b56ccd8..00000000000 --- a/include/dt-bindings/power/rk3288-power.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3288_POWER_H__ -#define __DT_BINDINGS_POWER_RK3288_POWER_H__ - -/** - * RK3288 Power Domain and Voltage Domain Summary. - */ - -/* VD_CORE */ -#define RK3288_PD_A17_0 0 -#define RK3288_PD_A17_1 1 -#define RK3288_PD_A17_2 2 -#define RK3288_PD_A17_3 3 -#define RK3288_PD_SCU 4 -#define RK3288_PD_DEBUG 5 -#define RK3288_PD_MEM 6 - -/* VD_LOGIC */ -#define RK3288_PD_BUS 7 -#define RK3288_PD_PERI 8 -#define RK3288_PD_VIO 9 -#define RK3288_PD_ALIVE 10 -#define RK3288_PD_HEVC 11 -#define RK3288_PD_VIDEO 12 - -/* VD_GPU */ -#define RK3288_PD_GPU 13 - -/* VD_PMU */ -#define RK3288_PD_PMU 14 - -#endif -- cgit v1.3.1 From c63eae2817195f4b315c8b19a0055e10ca062e84 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 9 Nov 2024 21:04:10 +0000 Subject: rockchip: clk: rk3288: Drop use of SCLK_MAC_PLL The SCLK_MAC_PLL id is not exported or referenced upstream. It is also not referenced in vendor U-Boot or vendor kernel 4.4, 4.19, 5.10 or 6.1. Relax the check for parent id SCLK_MAC_PLL when using internal clock source for gmac to allow use of clock/rk3288-cru.h from dts/upstream. All in-tree and upstream rk3288 DTs use an external clock as parent, so no functional change to boards is expected with this change. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3288.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 43c44fadbe7..a4ff1c41abb 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -903,11 +903,11 @@ static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *pa int ret; /* - * If the requested parent is in the same clock-controller and - * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal - * clock. + * If the requested parent is in the same clock-controller the + * likely parent is the unexported SCLK_MAC_PLL ("mac_pll_src"), + * switch to the internal clock. */ - if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) { + if (parent->dev == clk->dev) { debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__); rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0); return 0; -- cgit v1.3.1 From 934a2d49f8aae45a844013910bafbd9bb18193c5 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 9 Nov 2024 21:04:12 +0000 Subject: rockchip: rk3288: Use rk3288.dtsi from dts/upstream rk3288.dtsi from arch/arm/dts is almost identical to the rk3288.dtsi from dts/upstream, it differs only with a minor change in hdmi port nodes, something that does not affect U-Boot. Remove arch/arm/dts/rk3288.dtsi to use rk3288.dtsi from dts/upstream. Also drop gpio aliases from -u-boot.dtsi that has been part of rk3288.dtsi for some time. No functional change to board DTs is intended with this removal. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-u-boot.dtsi | 9 - arch/arm/dts/rk3288.dtsi | 2035 --------------------------------------- 2 files changed, 2044 deletions(-) delete mode 100644 arch/arm/dts/rk3288.dtsi diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index a43d320ade7..48131da78ca 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -7,15 +7,6 @@ / { aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - gpio5 = &gpio5; - gpio6 = &gpio6; - gpio7 = &gpio7; - gpio8 = &gpio8; mmc0 = &emmc; mmc1 = &sdmmc; mmc2 = &sdio0; diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi deleted file mode 100644 index ead343dc3df..00000000000 --- a/arch/arm/dts/rk3288.dtsi +++ /dev/null @@ -1,2035 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - - compatible = "rockchip,rk3288"; - - interrupt-parent = <&gic>; - - aliases { - ethernet0 = &gmac; - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - gpio5 = &gpio5; - gpio6 = &gpio6; - gpio7 = &gpio7; - gpio8 = &gpio8; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - mshc0 = &emmc; - mshc1 = &sdmmc; - mshc2 = &sdio0; - mshc3 = &sdio1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - }; - - arm-pmu { - compatible = "arm,cortex-a12-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3066-smp"; - rockchip,pmu = <&pmu>; - - cpu0: cpu@500 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x500>; - resets = <&cru SRST_CORE0>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - dynamic-power-coefficient = <370>; - }; - cpu1: cpu@501 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x501>; - resets = <&cru SRST_CORE1>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - dynamic-power-coefficient = <370>; - }; - cpu2: cpu@502 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x502>; - resets = <&cru SRST_CORE2>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - dynamic-power-coefficient = <370>; - }; - cpu3: cpu@503 { - device_type = "cpu"; - compatible = "arm,cortex-a12"; - reg = <0x503>; - resets = <&cru SRST_CORE3>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - dynamic-power-coefficient = <370>; - }; - }; - - cpu_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-126000000 { - opp-hz = /bits/ 64 <126000000>; - opp-microvolt = <900000>; - }; - opp-216000000 { - opp-hz = /bits/ 64 <216000000>; - opp-microvolt = <900000>; - }; - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - opp-microvolt = <900000>; - }; - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <900000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000>; - }; - opp-696000000 { - opp-hz = /bits/ 64 <696000000>; - opp-microvolt = <950000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1050000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1100000>; - }; - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1200000>; - }; - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <1300000>; - }; - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1350000>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* - * The rk3288 cannot use the memory area above 0xfe000000 - * for dma operations for some reason. While there is - * probably a better solution available somewhere, we - * haven't found it yet and while devices with 2GB of ram - * are not affected, this issue prevents 4GB from booting. - * So to make these devices at least bootable, block - * this area for the time being until the real solution - * is found. - */ - dma-unusable@fe000000 { - reg = <0x0 0xfe000000 0x0 0x1000000>; - }; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - arm,no-tick-in-suspend; - }; - - timer: timer@ff810000 { - compatible = "rockchip,rk3288-timer"; - reg = <0x0 0xff810000 0x0 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER>, <&xin24m>; - clock-names = "pclk", "timer"; - }; - - display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vopl_out>, <&vopb_out>; - }; - - sdmmc: mmc@ff0c0000 { - compatible = "rockchip,rk3288-dw-mshc"; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x0 0xff0c0000 0x0 0x4000>; - resets = <&cru SRST_MMC0>; - reset-names = "reset"; - status = "disabled"; - }; - - sdio0: mmc@ff0d0000 { - compatible = "rockchip,rk3288-dw-mshc"; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, - <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x0 0xff0d0000 0x0 0x4000>; - resets = <&cru SRST_SDIO0>; - reset-names = "reset"; - status = "disabled"; - }; - - sdio1: mmc@ff0e0000 { - compatible = "rockchip,rk3288-dw-mshc"; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, - <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x0 0xff0e0000 0x0 0x4000>; - resets = <&cru SRST_SDIO1>; - reset-names = "reset"; - status = "disabled"; - }; - - emmc: mmc@ff0f0000 { - compatible = "rockchip,rk3288-dw-mshc"; - max-frequency = <150000000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x0 0xff0f0000 0x0 0x4000>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - saradc: saradc@ff100000 { - compatible = "rockchip,saradc"; - reg = <0x0 0xff100000 0x0 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - spi0: spi@ff110000 { - compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac_peri 11>, <&dmac_peri 12>; - dma-names = "tx", "rx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; - reg = <0x0 0xff110000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@ff120000 { - compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac_peri 13>, <&dmac_peri 14>; - dma-names = "tx", "rx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; - reg = <0x0 0xff120000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@ff130000 { - compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac_peri 15>, <&dmac_peri 16>; - dma-names = "tx", "rx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; - reg = <0x0 0xff130000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@ff140000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff140000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c3: i2c@ff150000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff150000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - i2c4: i2c@ff160000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff160000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C4>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; - status = "disabled"; - }; - - i2c5: i2c@ff170000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff170000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C5>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_xfer>; - status = "disabled"; - }; - - uart0: serial@ff180000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff180000 0x0 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac_peri 1>, <&dmac_peri 2>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; - status = "disabled"; - }; - - uart1: serial@ff190000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff190000 0x0 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac_peri 3>, <&dmac_peri 4>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - status = "disabled"; - }; - - uart2: serial@ff690000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff690000 0x0 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - status = "disabled"; - }; - - uart3: serial@ff1b0000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff1b0000 0x0 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac_peri 7>, <&dmac_peri 8>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; - status = "disabled"; - }; - - uart4: serial@ff1c0000 { - compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff1c0000 0x0 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac_peri 9>, <&dmac_peri 10>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer>; - status = "disabled"; - }; - - dmac_peri: dma-controller@ff250000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff250000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC2>; - clock-names = "apb_pclk"; - }; - - thermal-zones { - reserve_thermal: reserve-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 0>; - }; - - cpu_thermal: cpu-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 1>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>, - <&cpu1 THERMAL_NO_LIMIT 6>, - <&cpu2 THERMAL_NO_LIMIT 6>, - <&cpu3 THERMAL_NO_LIMIT 6>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu_thermal: gpu-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 2>; - - trips { - gpu_alert0: gpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_crit: gpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_alert0>; - cooling-device = - <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@ff280000 { - compatible = "rockchip,rk3288-tsadc"; - reg = <0x0 0xff280000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_pin>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_pin>; - #thermal-sensor-cells = <1>; - rockchip,grf = <&grf>; - rockchip,hw-tshut-temp = <95000>; - status = "disabled"; - }; - - gmac: ethernet@ff290000 { - compatible = "rockchip,rk3288-gmac"; - reg = <0x0 0xff290000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_MAC>, - <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, - <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, - <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; - clock-names = "stmmaceth", - "mac_clk_rx", "mac_clk_tx", - "clk_mac_ref", "clk_mac_refout", - "aclk_mac", "pclk_mac"; - resets = <&cru SRST_MAC>; - reset-names = "stmmaceth"; - status = "disabled"; - }; - - usb_host0_ehci: usb@ff500000 { - compatible = "generic-ehci"; - reg = <0x0 0xff500000 0x0 0x100>; - interrupts = ; - clocks = <&cru HCLK_USBHOST0>; - phys = <&usbphy1>; - phy-names = "usb"; - status = "disabled"; - }; - - /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */ - usb_host0_ohci: usb@ff520000 { - compatible = "generic-ohci"; - reg = <0x0 0xff520000 0x0 0x100>; - interrupts = ; - clocks = <&cru HCLK_USBHOST0>; - phys = <&usbphy1>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1: usb@ff540000 { - compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff540000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USBHOST1>; - clock-names = "otg"; - dr_mode = "host"; - phys = <&usbphy2>; - phy-names = "usb2-phy"; - snps,reset-phy-on-wake; - status = "disabled"; - }; - - usb_otg: usb@ff580000 { - compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff580000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG0>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <275>; - g-tx-fifo-size = <256 128 128 64 64 32>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_hsic: usb@ff5c0000 { - compatible = "generic-ehci"; - reg = <0x0 0xff5c0000 0x0 0x100>; - interrupts = ; - clocks = <&cru HCLK_HSIC>; - status = "disabled"; - }; - - dmac_bus_ns: dma-controller@ff600000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff600000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - i2c0: i2c@ff650000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff650000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - i2c2: i2c@ff660000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x0 0xff660000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - pwm0: pwm@ff680000 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x0 0xff680000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - clocks = <&cru PCLK_RKPWM>; - status = "disabled"; - }; - - pwm1: pwm@ff680010 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x0 0xff680010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - clocks = <&cru PCLK_RKPWM>; - status = "disabled"; - }; - - pwm2: pwm@ff680020 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x0 0xff680020 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - clocks = <&cru PCLK_RKPWM>; - status = "disabled"; - }; - - pwm3: pwm@ff680030 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x0 0xff680030 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - clocks = <&cru PCLK_RKPWM>; - status = "disabled"; - }; - - bus_intmem: sram@ff700000 { - compatible = "mmio-sram"; - reg = <0x0 0xff700000 0x0 0x18000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0xff700000 0x18000>; - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x00 0x10>; - }; - }; - - pmu_sram: sram@ff720000 { - compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; - reg = <0x0 0xff720000 0x0 0x1000>; - }; - - pmu: power-management@ff730000 { - compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xff730000 0x0 0x100>; - - power: power-controller { - compatible = "rockchip,rk3288-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - assigned-clocks = <&cru SCLK_EDP_24M>; - assigned-clock-parents = <&xin24m>; - - /* - * Note: Although SCLK_* are the working clocks - * of device without including on the NOC, needed for - * synchronous reset. - * - * The clocks on the which NOC: - * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. - * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. - * ACLK_RGA is on ACLK_RGA_NIU. - * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. - * - * Which clock are device clocks: - * clocks devices - * *_IEP IEP:Image Enhancement Processor - * *_ISP ISP:Image Signal Processing - * *_VIP VIP:Video Input Processor - * *_VOP* VOP:Visual Output Processor - * *_RGA RGA - * *_EDP* EDP - * *_LVDS_* LVDS - * *_HDMI HDMI - * *_MIPI_* MIPI - */ - power-domain@RK3288_PD_VIO { - reg = ; - clocks = <&cru ACLK_IEP>, - <&cru ACLK_ISP>, - <&cru ACLK_RGA>, - <&cru ACLK_VIP>, - <&cru ACLK_VOP0>, - <&cru ACLK_VOP1>, - <&cru DCLK_VOP0>, - <&cru DCLK_VOP1>, - <&cru HCLK_IEP>, - <&cru HCLK_ISP>, - <&cru HCLK_RGA>, - <&cru HCLK_VIP>, - <&cru HCLK_VOP0>, - <&cru HCLK_VOP1>, - <&cru PCLK_EDP_CTRL>, - <&cru PCLK_HDMI_CTRL>, - <&cru PCLK_LVDS_PHY>, - <&cru PCLK_MIPI_CSI>, - <&cru PCLK_MIPI_DSI0>, - <&cru PCLK_MIPI_DSI1>, - <&cru SCLK_EDP_24M>, - <&cru SCLK_EDP>, - <&cru SCLK_ISP_JPE>, - <&cru SCLK_ISP>, - <&cru SCLK_RGA>; - pm_qos = <&qos_vio0_iep>, - <&qos_vio1_vop>, - <&qos_vio1_isp_w0>, - <&qos_vio1_isp_w1>, - <&qos_vio0_vop>, - <&qos_vio0_vip>, - <&qos_vio2_rga_r>, - <&qos_vio2_rga_w>, - <&qos_vio1_isp_r>; - #power-domain-cells = <0>; - }; - - /* - * Note: The following 3 are HEVC(H.265) clocks, - * and on the ACLK_HEVC_NIU (NOC). - */ - power-domain@RK3288_PD_HEVC { - reg = ; - clocks = <&cru ACLK_HEVC>, - <&cru SCLK_HEVC_CABAC>, - <&cru SCLK_HEVC_CORE>; - pm_qos = <&qos_hevc_r>, - <&qos_hevc_w>; - #power-domain-cells = <0>; - }; - - /* - * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC - * (video endecoder & decoder) clocks that on the - * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). - */ - power-domain@RK3288_PD_VIDEO { - reg = ; - clocks = <&cru ACLK_VCODEC>, - <&cru HCLK_VCODEC>; - pm_qos = <&qos_video>; - #power-domain-cells = <0>; - }; - - /* - * Note: ACLK_GPU is the GPU clock, - * and on the ACLK_GPU_NIU (NOC). - */ - power-domain@RK3288_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu_r>, - <&qos_gpu_w>; - #power-domain-cells = <0>; - }; - }; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x94>; - mode-normal = ; - mode-recovery = ; - mode-bootloader = ; - mode-loader = ; - }; - }; - - sgrf: syscon@ff740000 { - compatible = "rockchip,rk3288-sgrf", "syscon"; - reg = <0x0 0xff740000 0x0 0x1000>; - }; - - cru: clock-controller@ff760000 { - compatible = "rockchip,rk3288-cru"; - reg = <0x0 0xff760000 0x0 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru PLL_NPLL>, <&cru ACLK_CPU>, - <&cru HCLK_CPU>, <&cru PCLK_CPU>, - <&cru ACLK_PERI>, <&cru HCLK_PERI>, - <&cru PCLK_PERI>; - assigned-clock-rates = <594000000>, <400000000>, - <500000000>, <300000000>, - <150000000>, <75000000>, - <300000000>, <150000000>, - <75000000>; - }; - - grf: syscon@ff770000 { - compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff770000 0x0 0x1000>; - - edp_phy: edp-phy { - compatible = "rockchip,rk3288-dp-phy"; - clocks = <&cru SCLK_EDP_24M>; - clock-names = "24m"; - #phy-cells = <0>; - status = "disabled"; - }; - - io_domains: io-domains { - compatible = "rockchip,rk3288-io-voltage-domain"; - status = "disabled"; - }; - - usbphy: usbphy { - compatible = "rockchip,rk3288-usb-phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@320 { - #phy-cells = <0>; - reg = <0x320>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - resets = <&cru SRST_USBOTG_PHY>; - reset-names = "phy-reset"; - }; - - usbphy1: usb-phy@334 { - #phy-cells = <0>; - reg = <0x334>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - resets = <&cru SRST_USBHOST0_PHY>; - reset-names = "phy-reset"; - }; - - usbphy2: usb-phy@348 { - #phy-cells = <0>; - reg = <0x348>; - clocks = <&cru SCLK_OTGPHY2>; - clock-names = "phyclk"; - #clock-cells = <0>; - resets = <&cru SRST_USBHOST1_PHY>; - reset-names = "phy-reset"; - }; - }; - }; - - wdt: watchdog@ff800000 { - compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; - reg = <0x0 0xff800000 0x0 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = ; - status = "disabled"; - }; - - spdif: sound@ff8b0000 { - compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; - reg = <0x0 0xff8b0000 0x0 0x10000>; - #sound-dai-cells = <0>; - clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>; - clock-names = "mclk", "hclk"; - dmas = <&dmac_bus_s 3>; - dma-names = "tx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - i2s: i2s@ff890000 { - compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff890000 0x0 0x10000>; - #sound-dai-cells = <0>; - interrupts = ; - clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - rockchip,playback-channels = <8>; - rockchip,capture-channels = <2>; - status = "disabled"; - }; - - crypto: crypto@ff8a0000 { - compatible = "rockchip,rk3288-crypto"; - reg = <0x0 0xff8a0000 0x0 0x4000>; - interrupts = ; - clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, - <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; - clock-names = "aclk", "hclk", "sclk", "apb_pclk"; - resets = <&cru SRST_CRYPTO>; - reset-names = "crypto-rst"; - }; - - iep_mmu: iommu@ff900800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff900800 0x0 0x40>; - interrupts = ; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - isp_mmu: iommu@ff914000 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; - interrupts = ; - clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - rockchip,disable-mmu-reset; - status = "disabled"; - }; - - rga: rga@ff920000 { - compatible = "rockchip,rk3288-rga"; - reg = <0x0 0xff920000 0x0 0x180>; - interrupts = ; - clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; - clock-names = "aclk", "hclk", "sclk"; - power-domains = <&power RK3288_PD_VIO>; - resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; - reset-names = "core", "axi", "ahb"; - }; - - vopb: vop@ff930000 { - compatible = "rockchip,rk3288-vop"; - reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3288_PD_VIO>; - resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopb_mmu>; - status = "disabled"; - - vopb_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopb_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vopb>; - }; - - vopb_out_edp: endpoint@1 { - reg = <1>; - remote-endpoint = <&edp_in_vopb>; - }; - - vopb_out_mipi: endpoint@2 { - reg = <2>; - remote-endpoint = <&mipi_in_vopb>; - }; - - vopb_out_lvds: endpoint@3 { - reg = <3>; - remote-endpoint = <&lvds_in_vopb>; - }; - }; - }; - - vopb_mmu: iommu@ff930300 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff930300 0x0 0x100>; - interrupts = ; - clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3288_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - vopl: vop@ff940000 { - compatible = "rockchip,rk3288-vop"; - reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3288_PD_VIO>; - resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopl_mmu>; - status = "disabled"; - - vopl_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopl_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vopl>; - }; - - vopl_out_edp: endpoint@1 { - reg = <1>; - remote-endpoint = <&edp_in_vopl>; - }; - - vopl_out_mipi: endpoint@2 { - reg = <2>; - remote-endpoint = <&mipi_in_vopl>; - }; - - vopl_out_lvds: endpoint@3 { - reg = <3>; - remote-endpoint = <&lvds_in_vopl>; - }; - }; - }; - - vopl_mmu: iommu@ff940300 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff940300 0x0 0x100>; - interrupts = ; - clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3288_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - mipi_dsi: dsi@ff960000 { - compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; - reg = <0x0 0xff960000 0x0 0x4000>; - interrupts = ; - clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; - clock-names = "ref", "pclk"; - power-domains = <&power RK3288_PD_VIO>; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mipi_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_mipi>; - }; - - mipi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_mipi>; - }; - }; - - mipi_out: port@1 { - reg = <1>; - }; - }; - }; - - lvds: lvds@ff96c000 { - compatible = "rockchip,rk3288-lvds"; - reg = <0x0 0xff96c000 0x0 0x4000>; - clocks = <&cru PCLK_LVDS_PHY>; - clock-names = "pclk_lvds"; - pinctrl-names = "lcdc"; - pinctrl-0 = <&lcdc_ctl>; - power-domains = <&power RK3288_PD_VIO>; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - lvds_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - lvds_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_lvds>; - }; - - lvds_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_lvds>; - }; - }; - - lvds_out: port@1 { - reg = <1>; - }; - }; - }; - - edp: dp@ff970000 { - compatible = "rockchip,rk3288-dp"; - reg = <0x0 0xff970000 0x0 0x4000>; - interrupts = ; - clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; - clock-names = "dp", "pclk"; - phys = <&edp_phy>; - phy-names = "dp"; - power-domains = <&power RK3288_PD_VIO>; - resets = <&cru SRST_EDP>; - reset-names = "dp"; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - edp_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - edp_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_edp>; - }; - - edp_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_edp>; - }; - }; - - edp_out: port@1 { - reg = <1>; - }; - }; - }; - - hdmi: hdmi@ff980000 { - compatible = "rockchip,rk3288-dw-hdmi"; - reg = <0x0 0xff980000 0x0 0x20000>; - reg-io-width = <4>; - #sound-dai-cells = <0>; - rockchip,grf = <&grf>; - interrupts = ; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; - clock-names = "iahb", "isfr", "cec"; - power-domains = <&power RK3288_PD_VIO>; - status = "disabled"; - - ports { - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_hdmi>; - }; - hdmi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_hdmi>; - }; - }; - }; - }; - - vpu: video-codec@ff9a0000 { - compatible = "rockchip,rk3288-vpu"; - reg = <0x0 0xff9a0000 0x0 0x800>; - interrupts = , - ; - interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "hclk"; - iommus = <&vpu_mmu>; - power-domains = <&power RK3288_PD_VIDEO>; - }; - - vpu_mmu: iommu@ff9a0800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff9a0800 0x0 0x100>; - interrupts = ; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3288_PD_VIDEO>; - }; - - hevc_mmu: iommu@ff9c0440 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; - interrupts = ; - clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - status = "disabled"; - }; - - gpu: gpu@ffa30000 { - compatible = "rockchip,rk3288-mali", "arm,mali-t760"; - reg = <0x0 0xffa30000 0x0 0x10000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&cru ACLK_GPU>; - operating-points-v2 = <&gpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - power-domains = <&power RK3288_PD_GPU>; - status = "disabled"; - }; - - gpu_opp_table: opp-table-1 { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <950000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <950000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <1000000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1100000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1250000>; - }; - }; - - qos_gpu_r: qos@ffaa0000 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaa0000 0x0 0x20>; - }; - - qos_gpu_w: qos@ffaa0080 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaa0080 0x0 0x20>; - }; - - qos_vio1_vop: qos@ffad0000 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0000 0x0 0x20>; - }; - - qos_vio1_isp_w0: qos@ffad0100 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0100 0x0 0x20>; - }; - - qos_vio1_isp_w1: qos@ffad0180 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0180 0x0 0x20>; - }; - - qos_vio0_vop: qos@ffad0400 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0400 0x0 0x20>; - }; - - qos_vio0_vip: qos@ffad0480 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0480 0x0 0x20>; - }; - - qos_vio0_iep: qos@ffad0500 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0500 0x0 0x20>; - }; - - qos_vio2_rga_r: qos@ffad0800 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0800 0x0 0x20>; - }; - - qos_vio2_rga_w: qos@ffad0880 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0880 0x0 0x20>; - }; - - qos_vio1_isp_r: qos@ffad0900 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0900 0x0 0x20>; - }; - - qos_video: qos@ffae0000 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffae0000 0x0 0x20>; - }; - - qos_hevc_r: qos@ffaf0000 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaf0000 0x0 0x20>; - }; - - qos_hevc_w: qos@ffaf0080 { - compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaf0080 0x0 0x20>; - }; - - dmac_bus_s: dma-controller@ffb20000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xffb20000 0x0 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - }; - - efuse: efuse@ffb40000 { - compatible = "rockchip,rk3288-efuse"; - reg = <0x0 0xffb40000 0x0 0x20>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE256>; - clock-names = "pclk_efuse"; - - cpu_id: cpu-id@7 { - reg = <0x07 0x10>; - }; - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - gic: interrupt-controller@ffc01000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x0 0xffc01000 0x0 0x1000>, - <0x0 0xffc02000 0x0 0x2000>, - <0x0 0xffc04000 0x0 0x2000>, - <0x0 0xffc06000 0x0 0x2000>; - interrupts = ; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3288-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio@ff750000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff750000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@ff780000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff780000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@ff790000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff790000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@ff7a0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7a0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@ff7b0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7b0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@ff7c0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7c0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO5>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@ff7d0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7d0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO6>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio@ff7e0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7e0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO7>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio8: gpio@ff7f0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff7f0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO8>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - hdmi { - hdmi_cec_c0: hdmi-cec-c0 { - rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>; - }; - - hdmi_cec_c7: hdmi-cec-c7 { - rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>; - }; - - hdmi_ddc: hdmi-ddc { - rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>, - <7 RK_PC4 2 &pcfg_pull_none>; - }; - - hdmi_ddc_unwedge: hdmi-ddc-unwedge { - rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>, - <7 RK_PC4 2 &pcfg_pull_none>; - }; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_12ma: pcfg-pull-none-12ma { - bias-disable; - drive-strength = <12>; - }; - - suspend { - global_pwroff: global-pwroff { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>; - }; - - ddrio_pwroff: ddrio-pwroff { - rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; - }; - - ddr0_retention: ddr0-retention { - rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>; - }; - - ddr1_retention: ddr1-retention { - rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; - }; - }; - - edp { - edp_hpd: edp-hpd { - rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>, - <0 RK_PC0 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>, - <8 RK_PA5 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>, - <6 RK_PB2 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PC1 1 &pcfg_pull_none>; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>, - <7 RK_PC2 1 &pcfg_pull_none>; - }; - }; - - i2c5 { - i2c5_xfer: i2c5-xfer { - rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>, - <7 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - i2s0 { - i2s0_bus: i2s0-bus { - rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>, - <6 RK_PA1 1 &pcfg_pull_none>, - <6 RK_PA2 1 &pcfg_pull_none>, - <6 RK_PA3 1 &pcfg_pull_none>, - <6 RK_PA4 1 &pcfg_pull_none>, - <6 RK_PB0 1 &pcfg_pull_none>; - }; - }; - - lcdc { - lcdc_ctl: lcdc-ctl { - rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, - <1 RK_PD1 1 &pcfg_pull_none>, - <1 RK_PD2 1 &pcfg_pull_none>, - <1 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>, - <6 RK_PC1 1 &pcfg_pull_up>, - <6 RK_PC2 1 &pcfg_pull_up>, - <6 RK_PC3 1 &pcfg_pull_up>; - }; - }; - - sdio0 { - sdio0_bus1: sdio0-bus1 { - rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>; - }; - - sdio0_bus4: sdio0-bus4 { - rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>, - <4 RK_PC5 1 &pcfg_pull_up>, - <4 RK_PC6 1 &pcfg_pull_up>, - <4 RK_PC7 1 &pcfg_pull_up>; - }; - - sdio0_cmd: sdio0-cmd { - rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>; - }; - - sdio0_clk: sdio0-clk { - rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>; - }; - - sdio0_cd: sdio0-cd { - rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>; - }; - - sdio0_wp: sdio0-wp { - rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>; - }; - - sdio0_pwr: sdio0-pwr { - rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>; - }; - - sdio0_bkpwr: sdio0-bkpwr { - rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>; - }; - - sdio0_int: sdio0-int { - rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>; - }; - }; - - sdio1 { - sdio1_bus1: sdio1-bus1 { - rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>; - }; - - sdio1_bus4: sdio1-bus4 { - rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>, - <3 RK_PD1 4 &pcfg_pull_up>, - <3 RK_PD2 4 &pcfg_pull_up>, - <3 RK_PD3 4 &pcfg_pull_up>; - }; - - sdio1_cd: sdio1-cd { - rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>; - }; - - sdio1_wp: sdio1-wp { - rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>; - }; - - sdio1_bkpwr: sdio1-bkpwr { - rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>; - }; - - sdio1_int: sdio1-int { - rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>; - }; - - sdio1_cmd: sdio1-cmd { - rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>; - }; - - sdio1_clk: sdio1-clk { - rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>; - }; - - sdio1_pwr: sdio1-pwr { - rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>; - }; - - emmc_pwr: emmc-pwr { - rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>; - }; - - emmc_bus4: emmc-bus4 { - rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, - <3 RK_PA1 2 &pcfg_pull_up>, - <3 RK_PA2 2 &pcfg_pull_up>, - <3 RK_PA3 2 &pcfg_pull_up>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, - <3 RK_PA1 2 &pcfg_pull_up>, - <3 RK_PA2 2 &pcfg_pull_up>, - <3 RK_PA3 2 &pcfg_pull_up>, - <3 RK_PA4 2 &pcfg_pull_up>, - <3 RK_PA5 2 &pcfg_pull_up>, - <3 RK_PA6 2 &pcfg_pull_up>, - <3 RK_PA7 2 &pcfg_pull_up>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>; - }; - }; - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>; - }; - }; - - spi2 { - spi2_cs1: spi2-cs1 { - rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>; - }; - spi2_clk: spi2-clk { - rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>; - }; - spi2_cs0: spi2-cs0 { - rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>; - }; - spi2_rx: spi2-rx { - rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>; - }; - spi2_tx: spi2-tx { - rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>, - <4 RK_PC1 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>, - <5 RK_PB1 1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>, - <7 RK_PC7 1 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>, - <7 RK_PB0 1 &pcfg_pull_none>; - }; - - uart3_cts: uart3-cts { - rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>; - }; - - uart3_rts: uart3-rts { - rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>; - }; - }; - - uart4 { - uart4_xfer: uart4-xfer { - rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>, - <5 RK_PB6 3 &pcfg_pull_none>; - }; - - uart4_cts: uart4-cts { - rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>; - }; - - uart4_rts: uart4-rts { - rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>; - }; - }; - - tsadc { - otp_pin: otp-pin { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>; - }; - }; - - gmac { - rgmii_pins: rgmii-pins { - rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, - <3 RK_PD7 3 &pcfg_pull_none>, - <3 RK_PD2 3 &pcfg_pull_none>, - <3 RK_PD3 3 &pcfg_pull_none>, - <3 RK_PD4 3 &pcfg_pull_none_12ma>, - <3 RK_PD5 3 &pcfg_pull_none_12ma>, - <3 RK_PD0 3 &pcfg_pull_none_12ma>, - <3 RK_PD1 3 &pcfg_pull_none_12ma>, - <4 RK_PA0 3 &pcfg_pull_none>, - <4 RK_PA5 3 &pcfg_pull_none>, - <4 RK_PA6 3 &pcfg_pull_none>, - <4 RK_PB1 3 &pcfg_pull_none_12ma>, - <4 RK_PA4 3 &pcfg_pull_none_12ma>, - <4 RK_PA1 3 &pcfg_pull_none>, - <4 RK_PA3 3 &pcfg_pull_none>; - }; - - rmii_pins: rmii-pins { - rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, - <3 RK_PD7 3 &pcfg_pull_none>, - <3 RK_PD4 3 &pcfg_pull_none>, - <3 RK_PD5 3 &pcfg_pull_none>, - <4 RK_PA0 3 &pcfg_pull_none>, - <4 RK_PA5 3 &pcfg_pull_none>, - <4 RK_PA4 3 &pcfg_pull_none>, - <4 RK_PA1 3 &pcfg_pull_none>, - <4 RK_PA2 3 &pcfg_pull_none>, - <4 RK_PA3 3 &pcfg_pull_none>; - }; - }; - - spdif { - spdif_tx: spdif-tx { - rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>; - }; - }; - }; -}; -- cgit v1.3.1 From 8b6227c2299a622a7c3821eb45088dd735e46ee1 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 4 Nov 2024 20:25:40 +0000 Subject: rockchip: rk3288: Fix bootph prop for vop nodes The vop nodes does not need to be included in xPL control FDT, they only need to be included at U-Boot proper pre-reloc phase. Change to use bootph-some-ram prop to fix this. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index 48131da78ca..2205caabc51 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -119,11 +119,11 @@ }; &vopb { - bootph-all; + bootph-some-ram; }; &vopl { - bootph-all; + bootph-some-ram; }; &xin24m { -- cgit v1.3.1 From 4d1c5a838a15035089f81fbd0b324ee72a3f03b2 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 16:00:24 +0000 Subject: board: rockchip: rk3288-tinker: Add myself as reviewer to MAINTAINERS Add myself as a reviewer for Tinker Board and S variant so that I can help with review and testing of defconfig and device tree changes. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- board/rockchip/tinker_rk3288/MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/rockchip/tinker_rk3288/MAINTAINERS b/board/rockchip/tinker_rk3288/MAINTAINERS index 3869d5dc853..a5cae55d428 100644 --- a/board/rockchip/tinker_rk3288/MAINTAINERS +++ b/board/rockchip/tinker_rk3288/MAINTAINERS @@ -1,5 +1,6 @@ TINKER-RK3288 M: Lin Huang +R: Jonas Karlman S: Maintained F: arch/arm/dts/rk3288-tinker.dts F: arch/arm/dts/rk3288-tinker.dtsi @@ -12,6 +13,7 @@ F: configs/tinker-rk3288_defconfig TINKER-S-RK3288 M: Michael Trimarchi +R: Jonas Karlman S: Maintained F: board/rockchip/tinker_rk3288 F: include/configs/tinker_rk3288.h -- cgit v1.3.1 From cabe2ef76669dc2cf4d3bba9cd47d1675d31f0a4 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 16:00:25 +0000 Subject: rockchip: rk3288-tinker: Sort u-boot.dtsi nodes alphabetically Sort the nodes in rk3288-tinker u-boot.dtsi files in alphabetical order. This has no intended change to board DTs and only rearrange nodes in preparation for future changes. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-tinker-s-u-boot.dtsi | 8 +++--- arch/arm/dts/rk3288-tinker-u-boot.dtsi | 44 ++++++++++++++++---------------- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/arch/arm/dts/rk3288-tinker-s-u-boot.dtsi b/arch/arm/dts/rk3288-tinker-s-u-boot.dtsi index b4c5483146a..a782f2f9804 100644 --- a/arch/arm/dts/rk3288-tinker-s-u-boot.dtsi +++ b/arch/arm/dts/rk3288-tinker-s-u-boot.dtsi @@ -17,18 +17,18 @@ bootph-pre-ram; }; -&emmc_clk { +&emmc_bus8 { bootph-pre-ram; }; -&emmc_cmd { +&emmc_clk { bootph-pre-ram; }; -&emmc_pwr { +&emmc_cmd { bootph-pre-ram; }; -&emmc_bus8 { +&emmc_pwr { bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3288-tinker-u-boot.dtsi b/arch/arm/dts/rk3288-tinker-u-boot.dtsi index 0cf1b696d16..032dac221c2 100644 --- a/arch/arm/dts/rk3288-tinker-u-boot.dtsi +++ b/arch/arm/dts/rk3288-tinker-u-boot.dtsi @@ -17,6 +17,10 @@ rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; }; +&gpio7 { + bootph-pre-ram; +}; + &i2c2 { m24c08@50 { compatible = "at,24c08", "i2c-eeprom"; @@ -24,31 +28,15 @@ }; }; -&pinctrl { - bootph-all; -}; - -&uart2 { - bootph-all; -}; - -&uart2_xfer { - bootph-all; -}; - -&sdmmc { - bootph-pre-ram; -}; - -&gpio7 { +&pcfg_pull_none { bootph-pre-ram; }; -&vcc_sd { +&pcfg_pull_none_drv_8ma { bootph-pre-ram; }; -&pcfg_pull_none_drv_8ma { +&pcfg_pull_up { bootph-pre-ram; }; @@ -56,11 +44,11 @@ bootph-pre-ram; }; -&pcfg_pull_none { - bootph-pre-ram; +&pinctrl { + bootph-all; }; -&pcfg_pull_up { +&sdmmc { bootph-pre-ram; }; @@ -83,3 +71,15 @@ &sdmmc_pwr { bootph-pre-ram; }; + +&uart2 { + bootph-all; +}; + +&uart2_xfer { + bootph-all; +}; + +&vcc_sd { + bootph-pre-ram; +}; -- cgit v1.3.1 From 7f13ffa280abcae6d518e2f784c8836d04057b46 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 16:00:26 +0000 Subject: rockchip: rk3288-tinker: Only include required DT nodes in TPL Drop the unneeded bootph-all prop from dmc node, it is already defined in soc u-boot.dtsi. Remove booth-all prop from gpio7 node, this node is not needed in TPL. Adjust bootph props to include pinctrl related nodes for UART2. Remove the explicit bootph-all prop from the pinctrl node, any bootph- prop will automatically be propagated to the pinctrl node. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-tinker-u-boot.dtsi | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/rk3288-tinker-u-boot.dtsi b/arch/arm/dts/rk3288-tinker-u-boot.dtsi index 032dac221c2..1665e4f5d10 100644 --- a/arch/arm/dts/rk3288-tinker-u-boot.dtsi +++ b/arch/arm/dts/rk3288-tinker-u-boot.dtsi @@ -6,7 +6,6 @@ #include "rk3288-u-boot.dtsi" &dmc { - bootph-all; rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 @@ -18,6 +17,7 @@ }; &gpio7 { + /delete-property/ bootph-all; bootph-pre-ram; }; @@ -29,7 +29,7 @@ }; &pcfg_pull_none { - bootph-pre-ram; + bootph-all; }; &pcfg_pull_none_drv_8ma { @@ -37,17 +37,13 @@ }; &pcfg_pull_up { - bootph-pre-ram; + bootph-all; }; &pcfg_pull_up_drv_8ma { bootph-pre-ram; }; -&pinctrl { - bootph-all; -}; - &sdmmc { bootph-pre-ram; }; @@ -77,7 +73,8 @@ }; &uart2_xfer { - bootph-all; + bootph-pre-sram; + bootph-pre-ram; }; &vcc_sd { -- cgit v1.3.1 From fcd494919276c945208ff70a914af1969e21e02d Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 16:00:27 +0000 Subject: rockchip: rk3288-tinker: Drop unused vcc_sd regulator from SPL The sdmmc power come from vcc33_sd pmic regulator and not from the vcc_sd fixed regulator, as currently defined in the in-tree DT. Drop vcc_sd and the related gpio7 and sdmmc_pwr nodes from being included in SPL along with any related Kconfig option. Also enable SPL_DM_SEQ_ALIAS to ensure aliases is handled correctly in SPL. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-tinker-u-boot.dtsi | 9 --------- configs/tinker-rk3288_defconfig | 7 +------ configs/tinker-s-rk3288_defconfig | 7 +------ 3 files changed, 2 insertions(+), 21 deletions(-) diff --git a/arch/arm/dts/rk3288-tinker-u-boot.dtsi b/arch/arm/dts/rk3288-tinker-u-boot.dtsi index 1665e4f5d10..4f230739f1c 100644 --- a/arch/arm/dts/rk3288-tinker-u-boot.dtsi +++ b/arch/arm/dts/rk3288-tinker-u-boot.dtsi @@ -18,7 +18,6 @@ &gpio7 { /delete-property/ bootph-all; - bootph-pre-ram; }; &i2c2 { @@ -64,10 +63,6 @@ bootph-pre-ram; }; -&sdmmc_pwr { - bootph-pre-ram; -}; - &uart2 { bootph-all; }; @@ -76,7 +71,3 @@ bootph-pre-sram; bootph-pre-ram; }; - -&vcc_sd { - bootph-pre-ram; -}; diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 42dbef9c2c3..aff820ebfdd 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -4,7 +4,6 @@ CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SYS_ARCH_TIMER=y CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x01000000 -CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 @@ -33,8 +32,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_I2C=y -CONFIG_SPL_POWER=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -54,6 +51,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -74,10 +72,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y -CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y -CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index e62a03e066c..6aef775a571 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_ARCH_TIMER=y CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x01000000 CONFIG_SYS_MALLOC_F_LEN=0x4000 -CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 @@ -33,8 +32,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_I2C=y -CONFIG_SPL_POWER=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -55,6 +52,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -75,10 +73,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y -CONFIG_SPL_PMIC_RK8XX=y -CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y -CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y -- cgit v1.3.1 From 5b95daa832f3ca3bc68528bcc237fea2e6357055 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 16:00:28 +0000 Subject: rockchip: rk3288-tinker: Include mmc nodes in pre-reloc for env load Include mmc related nodes in U-Boot proper pre-reloc phase to ensure environment can be loaded from mmc devices. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-tinker-s-u-boot.dtsi | 5 +++++ arch/arm/dts/rk3288-tinker-u-boot.dtsi | 7 +++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/dts/rk3288-tinker-s-u-boot.dtsi b/arch/arm/dts/rk3288-tinker-s-u-boot.dtsi index a782f2f9804..614d47ce180 100644 --- a/arch/arm/dts/rk3288-tinker-s-u-boot.dtsi +++ b/arch/arm/dts/rk3288-tinker-s-u-boot.dtsi @@ -15,20 +15,25 @@ &emmc { bootph-pre-ram; + bootph-some-ram; }; &emmc_bus8 { bootph-pre-ram; + bootph-some-ram; }; &emmc_clk { bootph-pre-ram; + bootph-some-ram; }; &emmc_cmd { bootph-pre-ram; + bootph-some-ram; }; &emmc_pwr { bootph-pre-ram; + bootph-some-ram; }; diff --git a/arch/arm/dts/rk3288-tinker-u-boot.dtsi b/arch/arm/dts/rk3288-tinker-u-boot.dtsi index 4f230739f1c..7568b149534 100644 --- a/arch/arm/dts/rk3288-tinker-u-boot.dtsi +++ b/arch/arm/dts/rk3288-tinker-u-boot.dtsi @@ -33,6 +33,7 @@ &pcfg_pull_none_drv_8ma { bootph-pre-ram; + bootph-some-ram; }; &pcfg_pull_up { @@ -41,26 +42,32 @@ &pcfg_pull_up_drv_8ma { bootph-pre-ram; + bootph-some-ram; }; &sdmmc { bootph-pre-ram; + bootph-some-ram; }; &sdmmc_bus4 { bootph-pre-ram; + bootph-some-ram; }; &sdmmc_cd { bootph-pre-ram; + bootph-some-ram; }; &sdmmc_clk { bootph-pre-ram; + bootph-some-ram; }; &sdmmc_cmd { bootph-pre-ram; + bootph-some-ram; }; &uart2 { -- cgit v1.3.1 From b8ff4be966b9b4655a0ae1b4758d9f755947e4f0 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 16:00:29 +0000 Subject: rockchip: rk3288-tinker: Set cpuid and serial env var Enable MISC_INIT_R and ROCKCHIP_EFUSE to read cpuid from efuse and set the cpuid# and serial# env vars. Change to read mac address from eeprom in rockchip_early_misc_init_r() to ensure the ethaddr env var is set before rockchip_setup_macaddr() try to set ethaddr based on cpuid. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- board/rockchip/tinker_rk3288/tinker-rk3288.c | 2 +- configs/tinker-rk3288_defconfig | 2 ++ configs/tinker-s-rk3288_defconfig | 2 ++ 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/board/rockchip/tinker_rk3288/tinker-rk3288.c b/board/rockchip/tinker_rk3288/tinker-rk3288.c index e966e9f201a..dfd553d1aa5 100644 --- a/board/rockchip/tinker_rk3288/tinker-rk3288.c +++ b/board/rockchip/tinker_rk3288/tinker-rk3288.c @@ -22,7 +22,7 @@ static int get_ethaddr_from_eeprom(u8 *addr) return i2c_eeprom_read(dev, 0, addr, 6); } -int rk3288_board_late_init(void) +int rockchip_early_misc_init_r(void) { u8 ethaddr[6]; diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index aff820ebfdd..851c312d4db 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -29,6 +29,7 @@ CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb" CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set @@ -63,6 +64,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_I2C_EEPROM=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index 6aef775a571..2269d04ee64 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -29,6 +29,7 @@ CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb" CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set @@ -64,6 +65,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_I2C_EEPROM=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y -- cgit v1.3.1 From ab0841336851d8983f53dbd726960344f19ab089 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 16:00:30 +0000 Subject: rockchip: rk3288-tinker: Sync defconfig options from rk3288-tinker-s Add missing Kconfig options used by the rk3288-tinker-s variant. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- configs/tinker-rk3288_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 851c312d4db..0c2fd573b67 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -41,6 +41,7 @@ CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y @@ -92,8 +93,10 @@ CONFIG_USB_ETHER_SMSC95XX=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set CONFIG_DISPLAY=y CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y -- cgit v1.3.1 From 826267d3eaa825b290457975f80983497f9ac001 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 16:00:31 +0000 Subject: rockchip: rk3288-tinker: Use common bss and stack addresses Migrate to use common bss, stack and malloc heap size and addresses to unify memory use in TPL, SPL and pre-reloc. Ensure SYS_MALLOC_F_LEN and TPL variant stay at 0x2000 and is unaffected on other boards not changed to use common malloc heap size. ENV_OFFSET is using the default value of 0x3f8000 and is also dropped. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3288/Kconfig | 6 +++++- configs/tinker-rk3288_defconfig | 10 ---------- configs/tinker-s-rk3288_defconfig | 10 ---------- 3 files changed, 5 insertions(+), 21 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 69a5614b449..672d634f7fb 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -132,6 +132,7 @@ config TARGET_ROCK2 config TARGET_TINKER_RK3288 bool "Tinker-RK3288" select BOARD_LATE_INIT + select ROCKCHIP_COMMON_STACK_ADDR select TPL help Tinker is a RK3288-based development board with 2 USB ports, HDMI, @@ -160,7 +161,7 @@ config SYS_SOC default "rk3288" config SYS_MALLOC_F_LEN - default 0x2000 + default 0x2000 if !SPL_SHARES_INIT_SP_ADDR config SPL_DRIVERS_MISC default y @@ -177,6 +178,9 @@ config SPL_SERIAL config TPL_STACK default 0xff718000 +config TPL_SYS_MALLOC_F_LEN + default 0x2000 + config TPL_TEXT_BASE default 0xff704000 diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 0c2fd573b67..0f3d47e1a4f 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -5,19 +5,11 @@ CONFIG_SYS_ARCH_TIMER=y CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x01000000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker" CONFIG_DM_RESET=y -CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_TINKER_RK3288=y -CONFIG_SPL_STACK_R_ADDR=0x80000 -CONFIG_SPL_STACK=0xff718000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_SPL_SIZE_LIMIT=0x4b000 @@ -31,8 +23,6 @@ CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_NO_BSS_LIMIT=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index 2269d04ee64..a013571b257 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -4,20 +4,12 @@ CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SYS_ARCH_TIMER=y CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x01000000 -CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker-s" CONFIG_DM_RESET=y -CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_TINKER_RK3288=y -CONFIG_SPL_STACK_R_ADDR=0x800000 -CONFIG_SPL_STACK=0xff718000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_SPL_SIZE_LIMIT=0x4b000 @@ -31,8 +23,6 @@ CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_NO_BSS_LIMIT=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y -- cgit v1.3.1 From 4ae0e5cd4dce7c67283e7a1951b2cefabcb477af Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 16:00:32 +0000 Subject: rockchip: rk3288-tinker: Drop use of silent console and late boardinfo Current use of SILENT_CONSOLE hide valuable information when something goes wrong during boot, drop this Kconfig option to allow user to see e.g. from what media U-Boot proper is loaded from. A second Model line is printed on console due to DISPLAY_BOARDINFO_LATE, drop this Kconfig option to remove the second redundant line. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- configs/tinker-rk3288_defconfig | 2 -- configs/tinker-s-rk3288_defconfig | 2 -- 2 files changed, 4 deletions(-) diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 0f3d47e1a4f..fb42b8bcb00 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -19,8 +19,6 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb" -CONFIG_SILENT_CONSOLE=y -CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_CMD_GPIO=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index a013571b257..f3a392688f0 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -19,8 +19,6 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb" -CONFIG_SILENT_CONSOLE=y -CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_CMD_GPIO=y -- cgit v1.3.1 From c33c245e30667ee0f69edba1f50ee696e2aaaf43 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 16:00:33 +0000 Subject: rockchip: rk3288-tinker: Drop USE_PREBOOT Kconfig option After the migration to use standard boot, storage media should automatically be initialized in the order listed in boot_targets env. Drop USE_PREBOOT to speed up boot with ~12 seconds when booting from e.g. SD-card or eMMC. Before: 3,048,599 2,056 main_loop 3,050,717 2,118 usb_start 15,070,499 12,019,782 cli_loop After: 3,058,244 2,054 main_loop 3,063,260 5,016 cli_loop Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- configs/tinker-rk3288_defconfig | 1 - configs/tinker-s-rk3288_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index fb42b8bcb00..1007d9ca9e1 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -17,7 +17,6 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb" CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index f3a392688f0..47d089ff478 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -17,7 +17,6 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb" CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 -- cgit v1.3.1 From a0a880942b03fb1e6b8abe1d83ed20bf6c55a8b8 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 16:00:34 +0000 Subject: rockchip: rk3288-tinker: Migrate to OF_UPSTREAM The device tree for ASUS Tinker Board and S variant in dts/upstream can be used as-is by U-Boot, migrate board to OF_UPSTREAM. The change to use DT from dts/upstream will include minor changes and fixes related to leds and regulators. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 2 - arch/arm/dts/rk3288-tinker-s.dts | 29 -- arch/arm/dts/rk3288-tinker.dts | 33 -- arch/arm/dts/rk3288-tinker.dtsi | 533 ------------------------------- board/rockchip/tinker_rk3288/MAINTAINERS | 5 +- configs/tinker-rk3288_defconfig | 6 +- configs/tinker-s-rk3288_defconfig | 6 +- 7 files changed, 9 insertions(+), 605 deletions(-) delete mode 100644 arch/arm/dts/rk3288-tinker-s.dts delete mode 100644 arch/arm/dts/rk3288-tinker.dts delete mode 100644 arch/arm/dts/rk3288-tinker.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 23b537a2fcb..dca96f30ea3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -74,8 +74,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-popmetal.dtb \ rk3288-rock2-square.dtb \ rk3288-rock-pi-n8.dtb \ - rk3288-tinker.dtb \ - rk3288-tinker-s.dtb \ rk3288-veyron-jerry.dtb \ rk3288-veyron-mickey.dtb \ rk3288-veyron-minnie.dtb \ diff --git a/arch/arm/dts/rk3288-tinker-s.dts b/arch/arm/dts/rk3288-tinker-s.dts deleted file mode 100644 index cc7ac5f8811..00000000000 --- a/arch/arm/dts/rk3288-tinker-s.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. - */ - -/dts-v1/; - -#include "rk3288-tinker.dtsi" - -/ { - model = "Rockchip RK3288 Asus Tinker Board S"; - compatible = "asus,rk3288-tinker-s", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; - max-frequency = <150000000>; - mmc-hs200-1_8v; - mmc-ddr-1_8v; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-tinker.dts b/arch/arm/dts/rk3288-tinker.dts deleted file mode 100644 index 8b1848c310e..00000000000 --- a/arch/arm/dts/rk3288-tinker.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include "rk3288-tinker.dtsi" - -/ { - model = "Tinker-RK3288"; - compatible = "rockchip,rk3288-tinker", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; -}; - -&pinctrl { - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&usb_host1 { - vbus-supply = <&vcc5v0_host>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-tinker.dtsi b/arch/arm/dts/rk3288-tinker.dtsi deleted file mode 100644 index 62b4beb2510..00000000000 --- a/arch/arm/dts/rk3288-tinker.dtsi +++ /dev/null @@ -1,533 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include "rk3288.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&pwrbtn>; - - button@0 { - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - label = "GPIO Key Power"; - linux,code = ; - linux,input-type = <1>; - gpio-key,wakeup = <1>; - debounce-interval = <100>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - pwr-led { - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - act-led { - gpios=<&gpio2 3 GPIO_ACTIVE_LOW>; - linux,default-trigger="mmc0"; - }; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* - * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from - * vcc_io directly. Those boards won't be able to power cycle SD cards - * but it shouldn't hurt to toggle this pin there anyway. - */ - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc5v0_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc5v0_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; /* wp not hooked up */ - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "okay"; - supports-sd; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; -}; - -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&gmac { - phy-supply = <&vcc33_lan>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio4 7 0>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - rk808: pmic@1b { - compatible = "rockchip,rk808"; - reg = <0x1b>; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &global_pwroff>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "xin32k", "rk808-clkout2"; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_18>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc11-supply = <&vcc_sys>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vcc18_ldo1>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1350000>; - regulator-name = "vdd_arm"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc18_ldo1: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_ldo1"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc33_mipi: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33_mipi"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc18_codec: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_codec"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc18_lcd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc33_sd: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc33_sd"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc33_lan: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc33_lan"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; - headset: nau8825@1a { - compatible = "nuvoton,nau8825"; - #sound-dai-cells = <0>; - reg = <0x1a>; - interrupt-parent = <&gpio6>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - nuvoton,jkdet-enable = <1>; - nuvoton,jkdet-pull-enable = <1>; - nuvoton,jkdet-pull-up = <0>; - nuvoton,jkdet-polarity = <1>; - nuvoton,vref-impedance = <2>; - nuvoton,micbias-voltage = <6>; - nuvoton,sar-threshold-num = <4>; - nuvoton,sar-threshold = <0xa 0x14 0x26 0x73>; - nuvoton,sar-hysteresis = <0>; - nuvoton,sar-voltage = <6>; - nuvoton,sar-compare-time = <0>; - nuvoton,sar-sampling-time = <0>; - nuvoton,short-key-debounce = <3>; - nuvoton,jack-insert-debounce = <7>; - nuvoton,jack-eject-debounce = <7>; - clock-names = "mclk"; - clocks = <&cru SCLK_I2S0_OUT>; - }; -}; - -&i2c5 { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -&pwm0 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc18_ldo1>; - status ="okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; - -&usb_otg { - status= "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&pinctrl { - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - backlight { - bl_en: bl-en { - rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - buttons { - pwrbtn: pwrbtn { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - eth_phy { - eth_phy_pwr: eth-phy-pwr { - rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = ; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on EVB board so bump up to 8ma. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pwr_3g: pwr-3g { - rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/board/rockchip/tinker_rk3288/MAINTAINERS b/board/rockchip/tinker_rk3288/MAINTAINERS index a5cae55d428..ab1ce72a77b 100644 --- a/board/rockchip/tinker_rk3288/MAINTAINERS +++ b/board/rockchip/tinker_rk3288/MAINTAINERS @@ -2,10 +2,6 @@ TINKER-RK3288 M: Lin Huang R: Jonas Karlman S: Maintained -F: arch/arm/dts/rk3288-tinker.dts -F: arch/arm/dts/rk3288-tinker.dtsi -F: arch/arm/dts/rk3288-tinker-s.dts -F: arch/arm/dts/rk3288-tinker-s-u-boot.dtsi F: arch/arm/dts/rk3288-tinker-u-boot.dtsi F: board/rockchip/tinker_rk3288 F: include/configs/tinker_rk3288.h @@ -15,6 +11,7 @@ TINKER-S-RK3288 M: Michael Trimarchi R: Jonas Karlman S: Maintained +F: arch/arm/dts/rk3288-tinker-s-u-boot.dtsi F: board/rockchip/tinker_rk3288 F: include/configs/tinker_rk3288.h F: configs/tinker-s-rk3288_defconfig diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 1007d9ca9e1..b7636fe581f 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -6,7 +6,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x01000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-tinker" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_TINKER_RK3288=y @@ -17,7 +17,7 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-tinker.dtb" CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_CMD_GPIO=y @@ -36,6 +36,8 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index 47d089ff478..e50424746c8 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -6,7 +6,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x01000000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker-s" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-tinker-s" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_TINKER_RK3288=y @@ -17,7 +17,7 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-tinker-s.dtb" CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_CMD_GPIO=y @@ -36,6 +36,8 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -- cgit v1.3.1 From 57237c7f41d21b09c95421e00f6dd370a550a257 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 16:00:35 +0000 Subject: rockchip: rk3288-tinker: Fix slow Ethernet initializion For some reason the Ethernet PHY reset delay is set to 1 second, this cause an unneccecery long boot delay. Tinker Board use RTL8211E or RTL8211F Ethernet PHY, datasheet list an initial 10ms delay and then a 30-76ms delay before accessing registers. Change to use 80ms delay instead of a full second to speed up Ethernet initializion in U-Boot. Also enable PHY_REALTEK, DM_ETH_PHY and PHY_GIGE to improve Ethernet PHY support in U-Boot. Before: 1,404,971 960,924 eth_common_init 2,438,830 1,033,859 eth_initialize 2,444,449 5,619 main_loop 2,445,153 704 cli_loop After: 1,404,987 960,710 eth_common_init 1,519,110 114,123 eth_initialize 1,524,734 5,624 main_loop 1,525,452 718 cli_loop Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-tinker-u-boot.dtsi | 4 ++++ configs/tinker-rk3288_defconfig | 3 +++ configs/tinker-s-rk3288_defconfig | 3 +++ 3 files changed, 10 insertions(+) diff --git a/arch/arm/dts/rk3288-tinker-u-boot.dtsi b/arch/arm/dts/rk3288-tinker-u-boot.dtsi index 7568b149534..a6f6f14df93 100644 --- a/arch/arm/dts/rk3288-tinker-u-boot.dtsi +++ b/arch/arm/dts/rk3288-tinker-u-boot.dtsi @@ -16,6 +16,10 @@ rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; }; +&gmac { + snps,reset-delays-us = <0 10000 80000>; +}; + &gpio7 { /delete-property/ bootph-all; }; diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index b7636fe581f..05dca105d60 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -58,6 +58,9 @@ CONFIG_ROCKCHIP_EFUSE=y CONFIG_I2C_EEPROM=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index e50424746c8..1bee0d094c8 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -58,6 +58,9 @@ CONFIG_ROCKCHIP_EFUSE=y CONFIG_I2C_EEPROM=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y -- cgit v1.3.1 From 39c9a94ea68ad02922336ecdf557af9fe95ce672 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 16:00:36 +0000 Subject: rockchip: rk3288-tinker: Change to use FIT Change to use FIT and FIT_SIGNATURE when loading U-Boot proper in SPL to allow checksum validation and fallback loading of FIT from a different mmc device. Checksum validation of FIT adds around 140 ms to boot time: Before: Mark Elapsed Stage 0 0 reset 13 13 TPL 6,957 6,944 end tpl 25,102 18,145 SPL 131,932 106,830 end phase 132,137 205 board_init_f 444,277 312,140 board_init_r 1,404,987 960,710 eth_common_init 1,519,110 114,123 eth_initialize 1,524,734 5,624 main_loop 1,525,452 718 cli_loop After: Mark Elapsed Stage 0 0 reset 13 13 TPL 6,957 6,944 end tpl 35,744 28,787 SPL 271,220 235,476 end phase 271,420 200 board_init_f 588,474 317,054 board_init_r 1,548,950 960,476 eth_common_init 1,663,105 114,155 eth_initialize 1,668,734 5,629 main_loop 1,669,417 683 cli_loop Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- configs/tinker-rk3288_defconfig | 7 +++++++ configs/tinker-s-rk3288_defconfig | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 05dca105d60..bc5379d4343 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -17,9 +17,15 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-tinker.dtb" CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -91,4 +97,5 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_CMD_DHRYSTONE=y +CONFIG_SPL_CRC32=y CONFIG_ERRNO_STR=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index 1bee0d094c8..f0c8cc5bbc1 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -17,9 +17,15 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-tinker-s.dtb" CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -91,4 +97,5 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_CMD_DHRYSTONE=y +CONFIG_SPL_CRC32=y CONFIG_ERRNO_STR=y -- cgit v1.3.1 From 98ba08b6c53c78cdf6d8cf881ece3eb8e8b40efd Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 21:51:37 +0000 Subject: rockchip: rk3288-miqi: Sort u-boot.dtsi nodes alphabetically Sort the nodes in rk3288-miqi-u-boot.dtsi in alphabetical order. This has no intended change to board DT, this only rearrange nodes in preparation for future changes. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-miqi-u-boot.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/rk3288-miqi-u-boot.dtsi b/arch/arm/dts/rk3288-miqi-u-boot.dtsi index 43cb48bd032..ca839390ce7 100644 --- a/arch/arm/dts/rk3288-miqi-u-boot.dtsi +++ b/arch/arm/dts/rk3288-miqi-u-boot.dtsi @@ -25,11 +25,11 @@ rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; }; -&pinctrl { +&emmc { bootph-all; }; -&uart2 { +&pinctrl { bootph-all; }; @@ -37,10 +37,6 @@ bootph-all; }; -&emmc { - bootph-all; -}; - &sdmmc_bus4 { bootph-pre-ram; }; @@ -56,3 +52,7 @@ &sdmmc_pwr { bootph-pre-ram; }; + +&uart2 { + bootph-all; +}; -- cgit v1.3.1 From 0bcaa88245bbc0fff4ed7d94fb307c3448461cb7 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 21:51:38 +0000 Subject: rockchip: rk3288-miqi: Remove unused work led node from xPL The work led is not used in xPL on rk3288-miqi, remove bootph props from the work led node to exclude it from xPL control FDT. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-miqi-u-boot.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm/dts/rk3288-miqi-u-boot.dtsi b/arch/arm/dts/rk3288-miqi-u-boot.dtsi index ca839390ce7..721d0208693 100644 --- a/arch/arm/dts/rk3288-miqi-u-boot.dtsi +++ b/arch/arm/dts/rk3288-miqi-u-boot.dtsi @@ -4,15 +4,6 @@ */ #include "rk3288-u-boot.dtsi" -/ { - leds { - bootph-all; - - work { - bootph-all; - }; - }; -}; &dmc { rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa -- cgit v1.3.1 From 8d001223252f166a65019173d02bf25af7f9674f Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 21:51:39 +0000 Subject: rockchip: rk3288-miqi: Set ethaddr env based on cpuid Enable Kconfig options to read cpuid from efuse and set cpuid#, serial# and ethaddr env vars based on the value read from efuse. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- configs/miqi-rk3288_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 420a8bd1e79..23d67283a7b 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -27,6 +27,7 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb" +CONFIG_MISC_INIT_R=y CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_PAD_TO=0x7f8000 @@ -50,7 +51,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -61,6 +61,8 @@ CONFIG_SPL_CLK=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y -- cgit v1.3.1 From 68412a237f4db3b7541c4a565287e61a377f6f8b Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 21:51:40 +0000 Subject: rockchip: rk3288-miqi: Use TPL with common bss and stack addresses Migrate to use TPL, common bss, stack and malloc heap size and addresses to unify memory use in TPL, SPL and pre-reloc. ENV_OFFSET is using the default value of 0x3f8000 and is also dropped. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3288/Kconfig | 2 ++ configs/miqi-rk3288_defconfig | 15 ++------------- 2 files changed, 4 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 672d634f7fb..ff16d258b4f 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -86,6 +86,8 @@ config TARGET_FIREFLY_RK3288 config TARGET_MIQI_RK3288 bool "MiQi-RK3288" select BOARD_LATE_INIT + select ROCKCHIP_COMMON_STACK_ADDR + select TPL help MiQi-RK3288 is a RK3288-based development board with 4 USB 2.0 ports, HDMI, micro-SD card, 16 GB eMMC and Gigabit Ethernet. It diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 23d67283a7b..2bb8bf2ac06 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -1,24 +1,15 @@ CONFIG_ARM=y CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y +CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SYS_ARCH_TIMER=y CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00000000 +CONFIG_TEXT_BASE=0x01000000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-miqi" CONFIG_DM_RESET=y -CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_MIQI_RK3288=y -CONFIG_SPL_STACK_R_ADDR=0x80000 -CONFIG_SPL_STACK=0xff718000 -CONFIG_SPL_TEXT_BASE=0xff704000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART_BASE=0xff690000 @@ -31,8 +22,6 @@ CONFIG_MISC_INIT_R=y CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_NO_BSS_LIMIT=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y -- cgit v1.3.1 From 7e94567e10ef12924013ea8657c0c2fba870160c Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 21:51:41 +0000 Subject: rockchip: rk3288-miqi: Include required DT nodes in xPL Add bootph- props to emmc, sdmmc, uart and related pinctrl nodes to ensure devices and pinctrl can be used in xPL and U-Boot pre-reloc. Remove the explicit bootph-all prop from the pinctrl node, any bootph- prop will automatically be propagated to the pinctrl node. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-miqi-u-boot.dtsi | 57 ++++++++++++++++++++++++++++++++++-- configs/miqi-rk3288_defconfig | 2 +- 2 files changed, 56 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/rk3288-miqi-u-boot.dtsi b/arch/arm/dts/rk3288-miqi-u-boot.dtsi index 721d0208693..05e07425c75 100644 --- a/arch/arm/dts/rk3288-miqi-u-boot.dtsi +++ b/arch/arm/dts/rk3288-miqi-u-boot.dtsi @@ -17,27 +17,75 @@ }; &emmc { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_bus8 { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_cmd { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_pwr { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio7 { + /delete-property/ bootph-all; +}; + +&pcfg_pull_none { bootph-all; }; -&pinctrl { +&pcfg_pull_none_12ma { + bootph-pre-ram; + bootph-some-ram; +}; + +&pcfg_pull_up { bootph-all; }; +&pcfg_pull_up_drv_12ma { + bootph-pre-ram; + bootph-some-ram; +}; + &sdmmc { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &sdmmc_bus4 { bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_cd { + bootph-pre-ram; + bootph-some-ram; }; &sdmmc_clk { bootph-pre-ram; + bootph-some-ram; }; &sdmmc_cmd { bootph-pre-ram; + bootph-some-ram; }; &sdmmc_pwr { @@ -47,3 +95,8 @@ &uart2 { bootph-all; }; + +&uart2_xfer { + bootph-pre-sram; + bootph-pre-ram; +}; diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 2bb8bf2ac06..0e3c2b38f22 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y -- cgit v1.3.1 From a9ad8e143f4bbf301f9c491e24d445b1b752602f Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 21:51:42 +0000 Subject: rockchip: rk3288-miqi: Include sdmmc regulator in SPL Add bootph props and enable related Kconfig options to include the sdmmc regulator in SPL. Also enable SPL_DM_SEQ_ALIAS to ensure aliases is handled correctly in SPL. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-miqi-u-boot.dtsi | 5 +++++ configs/miqi-rk3288_defconfig | 3 +++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/dts/rk3288-miqi-u-boot.dtsi b/arch/arm/dts/rk3288-miqi-u-boot.dtsi index 05e07425c75..4361b35d6c8 100644 --- a/arch/arm/dts/rk3288-miqi-u-boot.dtsi +++ b/arch/arm/dts/rk3288-miqi-u-boot.dtsi @@ -43,6 +43,7 @@ &gpio7 { /delete-property/ bootph-all; + bootph-pre-ram; }; &pcfg_pull_none { @@ -100,3 +101,7 @@ bootph-pre-sram; bootph-pre-ram; }; + +&vcc_sd { + bootph-pre-ram; +}; diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 0e3c2b38f22..87fd256c8a5 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -4,6 +4,7 @@ CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SYS_ARCH_TIMER=y CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x01000000 +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-miqi" @@ -40,6 +41,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -62,6 +64,7 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_ACT8846=y CONFIG_REGULATOR_ACT8846=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y -- cgit v1.3.1 From 1e4806defdb9880b6449815c18d93fc7bf28e51e Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 21:51:43 +0000 Subject: rockchip: rk3288-miqi: Drop use of silent console and late boardinfo Current use of SILENT_CONSOLE hide valuable information when something goes wrong during boot, drop this Kconfig option to allow user to see e.g. from what media U-Boot proper is loaded from. A second Model line is printed on console due to DISPLAY_BOARDINFO_LATE, drop this Kconfig option to remove the second redundant line. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- configs/miqi-rk3288_defconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 87fd256c8a5..678d6fb3371 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -20,8 +20,6 @@ CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb" CONFIG_MISC_INIT_R=y -CONFIG_SILENT_CONSOLE=y -CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y -- cgit v1.3.1 From e4b4ed9651861808bca75bc03cd89a5f121490b7 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 21:51:44 +0000 Subject: rockchip: rk3288-miqi: Drop USE_PREBOOT Kconfig option After the migration to use standard boot, storage media devices should automatically be initialized in the order listed in boot_targets env. Drop USE_PREBOOT to speed up boot when booting from SD-card or eMMC. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- configs/miqi-rk3288_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 678d6fb3371..1643f277680 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -17,7 +17,6 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb" CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 -- cgit v1.3.1 From c33617d3bba599fb11014c9a0a604b907971c665 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 21:51:45 +0000 Subject: rockchip: rk3288-miqi: Migrate to OF_UPSTREAM The device tree for mqmaker MiQi in dts/upstream can be used as-is by U-Boot, migrate board to OF_UPSTREAM. The change to use DT from dts/upstream will include minor changes and fixes related to work led and usb otg. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 - arch/arm/dts/rk3288-miqi.dts | 16 -- arch/arm/dts/rk3288-miqi.dtsi | 417 ---------------------------------- board/mqmaker/miqi_rk3288/MAINTAINERS | 1 - configs/miqi-rk3288_defconfig | 6 +- 5 files changed, 4 insertions(+), 437 deletions(-) delete mode 100644 arch/arm/dts/rk3288-miqi.dts delete mode 100644 arch/arm/dts/rk3288-miqi.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index dca96f30ea3..93656e53610 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -70,7 +70,6 @@ dtb-$(CONFIG_ROCKCHIP_RK322X) += \ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-evb.dtb \ rk3288-firefly.dtb \ - rk3288-miqi.dtb \ rk3288-popmetal.dtb \ rk3288-rock2-square.dtb \ rk3288-rock-pi-n8.dtb \ diff --git a/arch/arm/dts/rk3288-miqi.dts b/arch/arm/dts/rk3288-miqi.dts deleted file mode 100644 index 4a2f249e1b1..00000000000 --- a/arch/arm/dts/rk3288-miqi.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include "rk3288-miqi.dtsi" - -/ { - model = "mqmaker MiQi"; - compatible = "mqmaker,miqi", "rockchip,rk3288"; - - chosen { - stdout-path = "serial2:115200n8"; - }; -}; diff --git a/arch/arm/dts/rk3288-miqi.dtsi b/arch/arm/dts/rk3288-miqi.dtsi deleted file mode 100644 index c56e1109e3a..00000000000 --- a/arch/arm/dts/rk3288-miqi.dtsi +++ /dev/null @@ -1,417 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright (c) 2016 Heiko Stuebner - */ - -#include "rk3288.dtsi" - -/ { - memory { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - leds { - compatible = "gpio-leds"; - - work { - gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; - label = "miqi:green:user"; - linux,default-trigger = "default-on"; - pinctrl-names = "default"; - pinctrl-0 = <&led_ctl>; - }; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - fcs,suspend-voltage-selector = <1>; - reg = <0x40>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <300>; - regulator-ramp-delay = <8000>; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - fcs,suspend-voltage-selector = <1>; - reg = <0x41>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_vsel>; - system-power-controller; - - vp1-supply = <&vcc_sys>; - vp2-supply = <&vcc_sys>; - vp3-supply = <&vcc_sys>; - vp4-supply = <&vcc_sys>; - inl1-supply = <&vcc_sys>; - inl2-supply = <&vcc_sys>; - inl3-supply = <&vcc_20>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "vcc_ddr"; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "vcc_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "vdd10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_18: REG7 { - regulator-name = "vcca_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcca_33: REG8 { - regulator-name = "vcca_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_lan: REG9 { - regulator-name = "vcc_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_10: REG10 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&io_domains { - audio-supply = <&vcca_33>; - flash0-supply = <&vcc_flash>; - flash1-supply = <&vcc_lan>; - gpio30-supply = <&vcc_io>; - gpio1830-supply = <&vcc_io>; - lcdc-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; - wifi-supply = <&vcc_18>; - status = "okay"; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - act8846 { - pmic_int: pmic-int { - rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - pmic_sleep: pmic-sleep { - rockchip,pins = <0 0 RK_FUNC_GPIO &pcfg_output_low>; - }; - - pmic_vsel: pmic-vsel { - rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - leds { - led_ctl: led-ctl { - rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on firefly board so bump up to 12ma. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, - <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host1 { - vbus-supply = <&vcc_host>; - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/board/mqmaker/miqi_rk3288/MAINTAINERS b/board/mqmaker/miqi_rk3288/MAINTAINERS index 1cb5f790fe7..d7e55b02fe3 100644 --- a/board/mqmaker/miqi_rk3288/MAINTAINERS +++ b/board/mqmaker/miqi_rk3288/MAINTAINERS @@ -1,7 +1,6 @@ MIQI M: Jernej Skrabec S: Maintained -F: arch/arm/dts/rk3288-miqi.dts F: arch/arm/dts/rk3288-miqi-u-boot.dtsi F: board/mqmaker/miqi_rk3288 F: include/configs/miqi_rk3288.h diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 1643f277680..ee991714973 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -7,7 +7,7 @@ CONFIG_TEXT_BASE=0x01000000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_DEFAULT_DEVICE_TREE="rk3288-miqi" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-miqi" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_MIQI_RK3288=y @@ -17,7 +17,7 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-miqi.dtb" CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_CMD_GPIO=y @@ -35,6 +35,8 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -- cgit v1.3.1 From 61f4e5f9cfa77d0b4f8fd69f6e7c3fd4cc5b519c Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 21:51:46 +0000 Subject: rockchip: rk3288-miqi: Fix slow Ethernet initializion For some reason the Ethernet PHY reset delay is set to 1 second, this cause an unneccecery long boot delay. MiQi use RTL8211 Ethernet PHY, datasheet list an initial 10ms delay and then a 30-76ms delay before accessing registers. Change to use 80ms delay instead of a full second to speed up Ethernet initializion in U-Boot. Also enable PHY_REALTEK, DM_ETH_PHY and PHY_GIGE to improve Ethernet PHY support in U-Boot. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-miqi-u-boot.dtsi | 4 ++++ configs/miqi-rk3288_defconfig | 3 +++ 2 files changed, 7 insertions(+) diff --git a/arch/arm/dts/rk3288-miqi-u-boot.dtsi b/arch/arm/dts/rk3288-miqi-u-boot.dtsi index 4361b35d6c8..e5c7e761c46 100644 --- a/arch/arm/dts/rk3288-miqi-u-boot.dtsi +++ b/arch/arm/dts/rk3288-miqi-u-boot.dtsi @@ -41,6 +41,10 @@ bootph-some-ram; }; +&gmac { + snps,reset-delays-us = <0 10000 80000>; +}; + &gpio7 { /delete-property/ bootph-all; bootph-pre-ram; diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index ee991714973..55e8d30f675 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -55,6 +55,9 @@ CONFIG_MISC=y CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y -- cgit v1.3.1 From 60649ea8aa6e03437d0dc2a0e031f8a1a7fa5f84 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 5 Nov 2024 21:51:47 +0000 Subject: rockchip: rk3288-miqi: Change to use FIT Change to use FIT and FIT_SIGNATURE when loading U-Boot proper in SPL to allow checksum validation and fallback loading of FIT from a different mmc device. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- configs/miqi-rk3288_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 55e8d30f675..166468fd4e7 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -17,9 +17,15 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-miqi.dtb" CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -89,4 +95,5 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_CMD_DHRYSTONE=y +CONFIG_SPL_CRC32=y CONFIG_ERRNO_STR=y -- cgit v1.3.1 From c99039867468468dbd27cd594be6ef66c37be56c Mon Sep 17 00:00:00 2001 From: Jacobe Zang Date: Tue, 19 Nov 2024 15:46:47 +0800 Subject: board: rockchip: add Khadas Edge2 RK3588 board Khadas Edge2 is a Rockchip RK3588S based SBC (Single Board Computer) by Khadas. There are tree variants depending on the DRAM size : 8G and 16G. Specification: Rockchip RK3588S SoC 4x ARM Cortex-A76, 4x ARM Cortex-A55 8/16GB memory LPDDR4x Mali G610MP4 GPU 3x MIPI CSI 4x lanes 2x MIPI-DSI DPHY 4x lanes 32/64GB eMMC 1x USB 2.0, 1x USB 3.0, 2x USB-Type-C 1x HDMI 2.1 output, 1x DP 1.4 output USB PD over USB Type-C Kernel commit: 04d552993522 ("arm64: dts: rockchip: Add Khadas edge2 board") Signed-off-by: Jacobe Zang --- arch/arm/mach-rockchip/rk3588/Kconfig | 23 +++ board/khadas/khadas-edge2-rk3588s/Kconfig | 12 ++ board/khadas/khadas-edge2-rk3588s/MAINTAINERS | 6 + configs/khadas-edge2-rk3588s_defconfig | 215 ++++++++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + include/configs/khadas-edge2-rk3588s.h | 15 ++ 6 files changed, 272 insertions(+) create mode 100644 board/khadas/khadas-edge2-rk3588s/Kconfig create mode 100644 board/khadas/khadas-edge2-rk3588s/MAINTAINERS create mode 100644 configs/khadas-edge2-rk3588s_defconfig create mode 100644 include/configs/khadas-edge2-rk3588s.h diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index b5a0e624a53..7d817e7f1bd 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -74,6 +74,28 @@ config TARGET_JAGUAR_RK3588 - fan controller (AMC6821 emulation) * 80-pin Mezzanine connector +config TARGET_KHADAS_EDGE2_RK3588 + bool "Khadas Edge2 RK3588 board" + select BOARD_LATE_INIT + help + Khadas Edge2 is a Rockchip RK3588S based SBC (Single Board Computer) + by Khadas. + + There are tree variants depending on the DRAM size : 8G and 16G. + + Specification: + + Rockchip RK3588S SoC + 4x ARM Cortex-A76, 4x ARM Cortex-A55 + 8/16GB memory LPDDR4x + Mali G610MP4 GPU + 3x MIPI CSI 4x lanes + 2x MIPI-DSI DPHY 4x lanes + 32/64GB eMMC + 1x USB 2.0, 1x USB 3.0, 2x USB-Type-C + 1x HDMI 2.1 output, 1x DP 1.4 output + USB PD over USB Type-C + config TARGET_NANOPCT6_RK3588 bool "FriendlyElec NanoPC-T6 RK3588 board" select BOARD_LATE_INIT @@ -393,6 +415,7 @@ source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig" source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig" source "board/hardkernel/odroid_m2/Kconfig" source "board/indiedroid/nova/Kconfig" +source "board/khadas/khadas-edge2-rk3588s/Kconfig" source "board/pine64/quartzpro64-rk3588/Kconfig" source "board/turing/turing-rk1-rk3588/Kconfig" source "board/radxa/rock5a-rk3588s/Kconfig" diff --git a/board/khadas/khadas-edge2-rk3588s/Kconfig b/board/khadas/khadas-edge2-rk3588s/Kconfig new file mode 100644 index 00000000000..dd7b6cd8054 --- /dev/null +++ b/board/khadas/khadas-edge2-rk3588s/Kconfig @@ -0,0 +1,12 @@ +if TARGET_KHADAS_EDGE2_RK3588 + +config SYS_BOARD + default "khadas-edge2-rk3588s" + +config SYS_VENDOR + default "khadas" + +config SYS_CONFIG_NAME + default "khadas-edge2-rk3588s" + +endif diff --git a/board/khadas/khadas-edge2-rk3588s/MAINTAINERS b/board/khadas/khadas-edge2-rk3588s/MAINTAINERS new file mode 100644 index 00000000000..3f16923b0f2 --- /dev/null +++ b/board/khadas/khadas-edge2-rk3588s/MAINTAINERS @@ -0,0 +1,6 @@ +KHADAS-EDGE2-RK3588S +M: Jacobe Zang +S: Maintained +F: configs/khadas-edge2-rk3588s_defconfig +F: include/configs/khadas-edge2-rk3588s.h +F: dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts \ No newline at end of file diff --git a/configs/khadas-edge2-rk3588s_defconfig b/configs/khadas-edge2-rk3588s_defconfig new file mode 100644 index 00000000000..208c72ca425 --- /dev/null +++ b/configs/khadas-edge2-rk3588s_defconfig @@ -0,0 +1,215 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-khadas-edge2" +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x80000 +CONFIG_ROCKCHIP_RK3588=y +CONFIG_ROCKCHIP_FIT_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_KHADAS_EDGE2_RK3588=y +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-khadas-edge2.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_MMC_WRITE=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_ATF=y +CONFIG_SPL_AB=y +CONFIG_SYS_PROMPT="kedge2# " +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot\n" +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DTIMG=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_SPI=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_MMC=y +# CONFIG_DM_SPI_FLASH=y +CONFIG_MMC=y +# CONFIG_MMC_SPI=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TFTP_BOOTM=y +CONFIG_CMD_TFTP_FLASH=y +CONFIG_CMD_MTD_BLK=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_DTB_MINIMUM=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_OF_U_BOOT_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_SARADC_ROCKCHIP_V2=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 +CONFIG_FASTBOOT_BUF_ADDR=0xc00800 +CONFIG_FASTBOOT_BUF_SIZE=0x07000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_ROCKCHIP_GPIO=y +CONFIG_ROCKCHIP_GPIO_V2=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_DM_KEY=y +CONFIG_RK8XX_PWRKEY=y +CONFIG_ADC_KEY=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SPL_MISC=y +CONFIG_MISC_DECOMPRESS=y +CONFIG_SPL_MISC_DECOMPRESS=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_SPL_ROCKCHIP_SECURE_OTP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_MTD=y +CONFIG_MTD_BLK=y +CONFIG_MTD_DEVICE=y +# CONFIG_NAND=y +# CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=80000000 +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_FUEL_GAUGE=y +CONFIG_POWER_FG_CW201X=y +CONFIG_POWER_FG_CW221X=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_SPI_RK8XX=y +CONFIG_DM_POWER_DELIVERY=y +CONFIG_TYPEC_TCPM=y +CONFIG_TYPEC_TCPCI=y +CONFIG_TYPEC_HUSB311=y +CONFIG_TYPEC_FUSB302=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK860X=y +CONFIG_REGULATOR_RK806=y +CONFIG_CHARGER_BQ25700=y +CONFIG_CHARGER_BQ25890=y +CONFIG_CHARGER_SC8551=y +CONFIG_CHARGER_SGM41542=y +CONFIG_DM_CHARGE_DISPLAY=y +CONFIG_CHARGE_ANIMATION=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RAMDISK=y +CONFIG_RAMDISK_RO=y +CONFIG_DM_RESET=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_RESET_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x350a +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_DRM_ROCKCHIP=y +CONFIG_DRM_MAXIM_MAX96745=y +CONFIG_DRM_MAXIM_MAX96755F=y +CONFIG_DRM_PANEL_ROHM_BU18RL82=y +CONFIG_DRM_PANEL_MAXIM_MAX96752F=y +CONFIG_DRM_ROHM_BU18XL82=y +CONFIG_DRM_ROCKCHIP_DW_HDMI_QP=y +CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y +CONFIG_DRM_ROCKCHIP_DW_DP=y +CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y +CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y +CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_LIB_RAND=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_N_SIZE=0x200 +CONFIG_RSA_E_SIZE=0x10 +CONFIG_RSA_C_SIZE=0x20 +CONFIG_XBC=y +CONFIG_LZ4=y +CONFIG_LZMA=y +CONFIG_ERRNO_STR=y +CONFIG_AVB_LIBAVB=y +CONFIG_AVB_LIBAVB_AB=y +CONFIG_AVB_LIBAVB_ATX=y +CONFIG_AVB_LIBAVB_USER=y +CONFIG_RK_AVB_LIBAVB_USER=y +CONFIG_OPTEE_CLIENT=y +CONFIG_OPTEE_V2=y +CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 9bab86d2347..ea98b73d33c 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -137,6 +137,7 @@ List of mainline supported Rockchip boards: - Generic RK3588S/RK3588 (generic-rk3588) - Hardkernel ODROID-M2 (odroid-m2-rk3588s) - Indiedroid Nova (nova-rk3588s) + - Khadas Edge2 (khadas-edge2-rk3588s) - Pine64 QuartzPro64 (quartzpro64-rk3588) - Radxa ROCK 5 ITX (rock-5-itx-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) diff --git a/include/configs/khadas-edge2-rk3588s.h b/include/configs/khadas-edge2-rk3588s.h new file mode 100644 index 00000000000..d279cf3826a --- /dev/null +++ b/include/configs/khadas-edge2-rk3588s.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024 Khadas Technology Co., Ltd. + */ + +#ifndef __KHADAS_EDGE2_RK3588_H +#define __KHADAS_EDGE2_RK3588_H + +#include + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#endif /* __KHADAS_EDGE2_RK3588_H */ -- cgit v1.3.1 From d7882f556efb11f00fbb93ce13ef2df297b6b1c7 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Thu, 26 Sep 2024 20:31:08 +0200 Subject: rockchip: rk3399-roc-pc: Hook sysreset gpio to enable full reset The reset mechanism used by Linux to reset the SoC is known to only partially reset the logic. A mechanism is implemented in rk3399_force_power_on_reset to use a GPIO connected to the PMIC's over-temperature (OTP) reset pin, which fully resets all logic. Hook the associated GPIO where the function expects it to enable this reset mechanism and avoid any possible side-effect of partially-reset units. Without this patch, reading from the micro sd slot fails after a reset. With this mechanism, U-Boot is able to boot from it reliably. Signed-off-by: Paul Kocialkowski Reviewed-by: Quentin Schulz --- arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi index aecf7dbe383..883d399a06a 100644 --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi @@ -7,6 +7,10 @@ #include "rk3399-sdram-lpddr4-100.dtsi" / { + config { + sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + }; + vcc_hub_en: vcc_hub_en-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -36,6 +40,10 @@ bootph-pre-ram; }; +&gpio1 { + bootph-pre-ram; +}; + &spi1 { flash@0 { bootph-pre-ram; -- cgit v1.3.1 From 95433be7ac9b22e4704a6e7a18c3b3a5876cc1f2 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Thu, 26 Sep 2024 20:31:09 +0200 Subject: rockchip: rk3399-rockpro64: Hook sysreset gpio to enable full reset The reset mechanism used by Linux to reset the SoC is known to only partially reset the logic. A mechanism is implemented in rk3399_force_power_on_reset to use a GPIO connected to the PMIC's over-temperature (OTP) reset pin, which fully resets all logic. Hook the associated GPIO where the function expects it to enable this reset mechanism and avoid any possible side-effect of partially-reset units. Signed-off-by: Paul Kocialkowski Reviewed-by: Quentin Schulz --- arch/arm/dts/rk3399-rockpro64-u-boot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi index 43b67991fe5..cd84269dab4 100644 --- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi @@ -7,6 +7,10 @@ #include "rk3399-sdram-lpddr4-100.dtsi" / { + config { + sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + }; + smbios { compatible = "u-boot,sysinfo-smbios"; smbios { @@ -32,6 +36,10 @@ bootph-pre-ram; }; +&gpio1 { + bootph-pre-ram; +}; + &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v; -- cgit v1.3.1 From e3c11f96b8e96417b33c06f7703b350eed4af29d Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Thu, 26 Sep 2024 20:31:10 +0200 Subject: rockchip: rk3399-rockpro64: Disable bootstage instrumentation config The boot timing and reporting (bootstage) infrastructure is useful for performance analysis and debug but adds overhead and console noise when using the device normally. Remove it from the device config. Signed-off-by: Paul Kocialkowski Reviewed-by: Peter Robinson Reviewed-by: Simon Glass --- configs/rockpro64-rk3399_defconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 08b7e2784e9..75322073285 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -20,8 +20,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_PCI=y CONFIG_DEBUG_UART=y -CONFIG_BOOTSTAGE=y -CONFIG_BOOTSTAGE_REPORT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 @@ -39,7 +37,6 @@ CONFIG_CMD_POWEROFF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y -CONFIG_CMD_BOOTSTAGE=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y -- cgit v1.3.1 From 1e3e3534a9ac6c10d8a3c6aeee68a85f47e9e86c Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 22:09:34 +0000 Subject: rockchip: rk3288-firefly: Drop unused SPL_LED related code The firefly-rk3288_defconfig build target does not enable the SPL_LED Kconfig option. Drop the unused SPL_LED related code and replace it with a default-state prop to ensure the LED driver enable the LED at U-Boot proper phase. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-firefly-u-boot.dtsi | 17 +--------- arch/arm/mach-rockchip/rk3288/Kconfig | 1 - board/firefly/firefly-rk3288/Makefile | 7 ---- board/firefly/firefly-rk3288/firefly-rk3288.c | 46 --------------------------- 4 files changed, 1 insertion(+), 70 deletions(-) delete mode 100644 board/firefly/firefly-rk3288/Makefile delete mode 100644 board/firefly/firefly-rk3288/firefly-rk3288.c diff --git a/arch/arm/dts/rk3288-firefly-u-boot.dtsi b/arch/arm/dts/rk3288-firefly-u-boot.dtsi index 644198a4a2f..30b471900b3 100644 --- a/arch/arm/dts/rk3288-firefly-u-boot.dtsi +++ b/arch/arm/dts/rk3288-firefly-u-boot.dtsi @@ -6,20 +6,9 @@ #include "rk3288-u-boot.dtsi" / { - config { - bootph-all; - u-boot,boot-led = "firefly:green:power"; - }; - leds { - bootph-all; - - work { - bootph-all; - }; - power { - bootph-all; + default-state = "on"; }; }; }; @@ -56,10 +45,6 @@ bootph-all; }; -&gpio8 { - bootph-all; -}; - &pcfg_pull_up_drv_12ma { bootph-pre-ram; }; diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index ff16d258b4f..9cc97bacc41 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -75,7 +75,6 @@ config TARGET_FENNEC_RK3288 config TARGET_FIREFLY_RK3288 bool "Firefly-RK3288" select BOARD_LATE_INIT - select SPL_BOARD_INIT if SPL select TPL help Firefly is a RK3288-based development board with 2 USB ports, diff --git a/board/firefly/firefly-rk3288/Makefile b/board/firefly/firefly-rk3288/Makefile deleted file mode 100644 index 671684597d2..00000000000 --- a/board/firefly/firefly-rk3288/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# (C) Copyright 2015 Google, Inc -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += firefly-rk3288.o diff --git a/board/firefly/firefly-rk3288/firefly-rk3288.c b/board/firefly/firefly-rk3288/firefly-rk3288.c deleted file mode 100644 index c65ce5890e5..00000000000 --- a/board/firefly/firefly-rk3288/firefly-rk3288.c +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 Google, Inc - */ - -#include -#include -#include -#include -#include - -#ifdef CONFIG_XPL_BUILD -static int setup_led(void) -{ -#ifdef CONFIG_SPL_LED - struct udevice *dev; - char *led_name; - int ret; - - led_name = ofnode_conf_read_str("u-boot,boot-led"); - if (!led_name) - return 0; - ret = led_get_by_label(led_name, &dev); - if (ret) { - debug("%s: get=%d\n", __func__, ret); - return ret; - } - ret = led_set_state(dev, LEDST_ON); - if (ret) - return ret; -#endif - - return 0; -} - -void spl_board_init(void) -{ - int ret; - - ret = setup_led(); - if (ret) { - debug("LED ret=%d\n", ret); - hang(); - } -} -#endif -- cgit v1.3.1 From 20ff82dc5189742cbd28be6e434beae73cb3d2b4 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 22:09:35 +0000 Subject: rockchip: rk3288-firefly: Sort u-boot.dtsi nodes alphabetically Sort the nodes in rk3288-firefly-u-boot.dtsi in alphabetical order. This has no intended change to board DT, this only rearrange nodes in preparation for future changes. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-firefly-u-boot.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/dts/rk3288-firefly-u-boot.dtsi b/arch/arm/dts/rk3288-firefly-u-boot.dtsi index 30b471900b3..8870188e612 100644 --- a/arch/arm/dts/rk3288-firefly-u-boot.dtsi +++ b/arch/arm/dts/rk3288-firefly-u-boot.dtsi @@ -25,30 +25,26 @@ rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; }; -&pinctrl { +&emmc { bootph-all; }; -&uart2 { +&gpio3 { bootph-all; }; -&sdmmc { - bootph-all; +&pcfg_pull_up_drv_12ma { + bootph-pre-ram; }; -&emmc { +&pinctrl { bootph-all; }; -&gpio3 { +&sdmmc { bootph-all; }; -&pcfg_pull_up_drv_12ma { - bootph-pre-ram; -}; - &sdmmc_bus4 { bootph-pre-ram; }; @@ -64,3 +60,7 @@ &sdmmc_pwr { bootph-pre-ram; }; + +&uart2 { + bootph-all; +}; -- cgit v1.3.1 From 35ae87eff6df02ad65f539278ff21dddd9b5d1ad Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 22:09:36 +0000 Subject: rockchip: rk3288-firefly: Set ethaddr env based on cpuid Enable Kconfig options to read cpuid from efuse and set cpuid#, serial# and ethaddr env vars based on the value read from efuse. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- configs/firefly-rk3288_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 00f23174210..eed0806b232 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -29,6 +29,7 @@ CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb" CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_NO_BSS_LIMIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set @@ -50,7 +51,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -63,6 +63,8 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_ETH_DESIGNWARE=y -- cgit v1.3.1 From 14c13f295a2e5d5c8790b52fc7ead1eeeacdd2ee Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 22:09:37 +0000 Subject: rockchip: rk3288-firefly: Use common bss and stack addresses Migrate to use common bss, stack and malloc heap size and addresses to unify memory use in TPL, SPL and pre-reloc. ENV_OFFSET is using the default value of 0x3f8000 and is also dropped. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3288/Kconfig | 1 + configs/firefly-rk3288_defconfig | 10 ---------- 2 files changed, 1 insertion(+), 10 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 9cc97bacc41..e563bf455e6 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -75,6 +75,7 @@ config TARGET_FENNEC_RK3288 config TARGET_FIREFLY_RK3288 bool "Firefly-RK3288" select BOARD_LATE_INIT + select ROCKCHIP_COMMON_STACK_ADDR select TPL help Firefly is a RK3288-based development board with 2 USB ports, diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index eed0806b232..87ed0c0d2ae 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -5,19 +5,11 @@ CONFIG_SYS_ARCH_TIMER=y CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x01000000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly" CONFIG_DM_RESET=y -CONFIG_SYS_MONITOR_LEN=614400 CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_FIREFLY_RK3288=y -CONFIG_SPL_STACK_R_ADDR=0x80000 -CONFIG_SPL_STACK=0xff718000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_SPL_SIZE_LIMIT=0x40000 @@ -31,8 +23,6 @@ CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 -CONFIG_SPL_NO_BSS_LIMIT=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y -- cgit v1.3.1 From 8baa2d89588108db9aeecc4850b106a6248771b8 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 22:09:38 +0000 Subject: rockchip: rk3288-firefly: Include required DT nodes in xPL Add bootph- props to emmc, sdmmc, uart and related pinctrl nodes to ensure devices and pinctrl can be used in xPL and U-Boot pre-reloc. Remove the explicit bootph-all prop from the pinctrl node, any bootph- prop will automatically be propagated to the pinctrl node. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-firefly-u-boot.dtsi | 55 ++++++++++++++++++++++++++++++--- configs/firefly-rk3288_defconfig | 2 +- 2 files changed, 51 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/rk3288-firefly-u-boot.dtsi b/arch/arm/dts/rk3288-firefly-u-boot.dtsi index 8870188e612..435a02acea5 100644 --- a/arch/arm/dts/rk3288-firefly-u-boot.dtsi +++ b/arch/arm/dts/rk3288-firefly-u-boot.dtsi @@ -26,35 +26,75 @@ }; &emmc { - bootph-all; + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_bus8 { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_clk { + bootph-pre-ram; + bootph-some-ram; }; -&gpio3 { +&emmc_cmd { + bootph-pre-ram; + bootph-some-ram; +}; + +&emmc_pwr { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio7 { + /delete-property/ bootph-all; +}; + +&pcfg_pull_none { bootph-all; }; -&pcfg_pull_up_drv_12ma { +&pcfg_pull_none_12ma { bootph-pre-ram; + bootph-some-ram; }; -&pinctrl { +&pcfg_pull_up { bootph-all; }; +&pcfg_pull_up_drv_12ma { + bootph-pre-ram; + bootph-some-ram; +}; + &sdmmc { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; &sdmmc_bus4 { bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_cd { + bootph-pre-ram; + bootph-some-ram; }; &sdmmc_clk { bootph-pre-ram; + bootph-some-ram; }; &sdmmc_cmd { bootph-pre-ram; + bootph-some-ram; }; &sdmmc_pwr { @@ -64,3 +104,8 @@ &uart2 { bootph-all; }; + +&uart2_xfer { + bootph-pre-sram; + bootph-pre-ram; +}; diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 87ed0c0d2ae..862a17c84e0 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -38,7 +38,7 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y -- cgit v1.3.1 From cf84730409c8e2e3e3b9314cbed9fe7f3ebc8462 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 22:09:39 +0000 Subject: rockchip: rk3288-firefly: Include sdmmc regulator in SPL Add bootph props and enable related Kconfig options to include the sdmmc regulator in SPL. Also enable SPL_DM_SEQ_ALIAS to ensure aliases is handled correctly in SPL. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-firefly-u-boot.dtsi | 5 +++++ configs/firefly-rk3288_defconfig | 4 +++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3288-firefly-u-boot.dtsi b/arch/arm/dts/rk3288-firefly-u-boot.dtsi index 435a02acea5..f953f682132 100644 --- a/arch/arm/dts/rk3288-firefly-u-boot.dtsi +++ b/arch/arm/dts/rk3288-firefly-u-boot.dtsi @@ -52,6 +52,7 @@ &gpio7 { /delete-property/ bootph-all; + bootph-pre-ram; }; &pcfg_pull_none { @@ -109,3 +110,7 @@ bootph-pre-sram; bootph-pre-ram; }; + +&vcc_sd { + bootph-pre-ram; +}; diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 862a17c84e0..2160474fe0f 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -4,6 +4,7 @@ CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SYS_ARCH_TIMER=y CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x01000000 +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly" @@ -41,6 +42,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -62,10 +64,10 @@ CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_DM_PMIC=y -# CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_ACT8846=y CONFIG_REGULATOR_ACT8846=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y -- cgit v1.3.1 From c18f00c3310db3b537bdf131543896767edf8a92 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 22:09:40 +0000 Subject: rockchip: rk3288-firefly: Drop use of silent console and late boardinfo Current use of SILENT_CONSOLE hide valuable information when something goes wrong during boot, drop this Kconfig option to allow user to see e.g. from what media U-Boot proper is loaded from. A second Model line is printed on console due to DISPLAY_BOARDINFO_LATE, drop this Kconfig option to remove the second redundant line. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- configs/firefly-rk3288_defconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 2160474fe0f..6e395f5c450 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -20,8 +20,6 @@ CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb" -CONFIG_SILENT_CONSOLE=y -CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_CMD_GPIO=y -- cgit v1.3.1 From 4a18711f54dd5e68742cf3e4c2f3dc9489cd9a07 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 22:09:41 +0000 Subject: rockchip: rk3288-firefly: Drop USE_PREBOOT Kconfig option After the migration to use standard boot, storage media devices should automatically be initialized in the order listed in boot_targets env. Drop USE_PREBOOT to speed up boot when booting from SD-card or eMMC. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- configs/firefly-rk3288_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 6e395f5c450..661ac065ce3 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -18,7 +18,6 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb" CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 -- cgit v1.3.1 From 338cfeac31d23fe6eb73e7f7f9687df46e41d5d7 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 22:09:42 +0000 Subject: rockchip: rk3288-firefly: Migrate to OF_UPSTREAM The device tree for Firefly-RK3288 in dts/upstream can be used as-is by U-Boot, migrate board to use OF_UPSTREAM. Add chosen stdout-path prop to board u-boot.dtsi as it is missing in DT from dts/upstream. Also change to use the upstream power_led symbol. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 - arch/arm/dts/rk3288-firefly-u-boot.dtsi | 10 +- arch/arm/dts/rk3288-firefly.dts | 43 --- arch/arm/dts/rk3288-firefly.dtsi | 491 ------------------------------- board/firefly/firefly-rk3288/MAINTAINERS | 1 + configs/firefly-rk3288_defconfig | 6 +- 6 files changed, 11 insertions(+), 541 deletions(-) delete mode 100644 arch/arm/dts/rk3288-firefly.dts delete mode 100644 arch/arm/dts/rk3288-firefly.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 93656e53610..22d121ae318 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -69,7 +69,6 @@ dtb-$(CONFIG_ROCKCHIP_RK322X) += \ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-evb.dtb \ - rk3288-firefly.dtb \ rk3288-popmetal.dtb \ rk3288-rock2-square.dtb \ rk3288-rock-pi-n8.dtb \ diff --git a/arch/arm/dts/rk3288-firefly-u-boot.dtsi b/arch/arm/dts/rk3288-firefly-u-boot.dtsi index f953f682132..13f5be27a96 100644 --- a/arch/arm/dts/rk3288-firefly-u-boot.dtsi +++ b/arch/arm/dts/rk3288-firefly-u-boot.dtsi @@ -6,10 +6,8 @@ #include "rk3288-u-boot.dtsi" / { - leds { - power { - default-state = "on"; - }; + chosen { + stdout-path = "serial2:115200n8"; }; }; @@ -73,6 +71,10 @@ bootph-some-ram; }; +&power_led { + default-state = "on"; +}; + &sdmmc { bootph-pre-ram; bootph-some-ram; diff --git a/arch/arm/dts/rk3288-firefly.dts b/arch/arm/dts/rk3288-firefly.dts deleted file mode 100644 index 72982efdf6d..00000000000 --- a/arch/arm/dts/rk3288-firefly.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright (c) 2014, 2015 FUKAUMI Naoki - */ - -/dts-v1/; -#include "rk3288-firefly.dtsi" - -/ { - model = "Firefly-RK3288"; - compatible = "firefly,firefly-rk3288", "rockchip,rk3288"; - - chosen { - stdout-path = &uart2; - }; -}; - -&ir { - gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; -}; - -&pinctrl { - act8846 { - pmic_vsel: pmic-vsel { - rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - ir { - ir_int: ir-int { - rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3288-firefly.dtsi b/arch/arm/dts/rk3288-firefly.dtsi deleted file mode 100644 index 0824b19ee64..00000000000 --- a/arch/arm/dts/rk3288-firefly.dtsi +++ /dev/null @@ -1,491 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright (c) 2014, 2015 FUKAUMI Naoki - */ - -#include "rk3288.dtsi" - -/ { - memory { - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ext_gmac: external-gmac-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - }; - - ir: ir-receiver { - compatible = "gpio-ir-receiver"; - pinctrl-names = "default"; - pinctrl-0 = <&ir_int>; - }; - - keys: gpio-keys { - compatible = "gpio-keys"; - - button@0 { - gpio-key,wakeup = <1>; - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = <116>; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - }; - }; - - leds { - compatible = "gpio-leds"; - - work { - gpios = <&gpio8 1 GPIO_ACTIVE_LOW>; - label = "firefly:blue:user"; - linux,default-trigger = "rc-feedback"; - pinctrl-names = "default"; - pinctrl-0 = <&work_led>; - }; - - power { - gpios = <&gpio8 2 GPIO_ACTIVE_LOW>; - label = "firefly:green:power"; - linux,default-trigger = "default-on"; - pinctrl-names = "default"; - pinctrl-0 = <&power_led>; - }; - }; - - vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_flash: flash-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_flash"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_io>; - }; - - vcc_5v: usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_host_5v: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; - - vcc_otg_5v: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc_otg_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vcc_5v>; - }; -}; - -&cpu0 { - cpu0-supply = <&vdd_cpu>; -}; - -&emmc { - broken-cd; - bus-width = <8>; - cap-mmc-highspeed; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; - vmmc-supply = <&vcc_io>; - vqmmc-supply = <&vcc_flash>; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>; - clock_in_out = "input"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; - phy-supply = <&vcc_lan>; - phy-mode = "rgmii"; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - vdd_cpu: syr827@40 { - compatible = "silergy,syr827"; - fcs,suspend-voltage-selector = <1>; - reg = <0x40>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vdd_gpu: syr828@41 { - compatible = "silergy,syr828"; - fcs,suspend-voltage-selector = <1>; - reg = <0x41>; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio7>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; - system-power-controller; - - regulators { - vcc_ddr: REG1 { - regulator-name = "vcc_ddr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vcc_io: REG2 { - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_log: REG3 { - regulator-name = "vdd_log"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - vcc_20: REG4 { - regulator-name = "vcc_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - vccio_sd: REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd10_lcd: REG6 { - regulator-name = "vdd10_lcd"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcca_18: REG7 { - regulator-name = "vcca_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcca_33: REG8 { - regulator-name = "vcca_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_lan: REG9 { - regulator-name = "vcc_lan"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_10: REG10 { - regulator-name = "vdd_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "vcc_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc18_lcd: REG12 { - regulator-name = "vcc18_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&pinctrl { - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - act8846 { - pwr_hold: pwr-hold { - rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - gmac { - phy_int: phy-int { - rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_pmeb: phy-pmeb { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - phy_rst: phy-rst { - rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - keys { - pwr_key: pwr-key { - rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - leds { - power_led: power-led { - rockchip,pins = <8 2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - work_led: work-led { - rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - /* - * Default drive strength isn't enough to achieve even - * high-speed mode on firefly board so bump up to 12ma. - */ - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC1 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC2 1 &pcfg_pull_up_drv_12ma>, - <6 RK_PC3 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_12ma>; - }; - - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usbhub_rst: usbhub-rst { - rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - usb_otg { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_18>; - status = "okay"; -}; - -&sdio0 { - broken-cd; - bus-width = <4>; - disable-wp; - non-removable; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>; - vmmc-supply = <&vcc_18>; - status = "disabled"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - disable-wp; - num-slots = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - vmmc-supply = <&vcc_sd>; - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk>, <&spi0_cs0>, <&spi0_tx>, <&spi0_rx>, <&spi0_cs1>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usb_host1 { - pinctrl-names = "default"; - pinctrl-0 = <&usbhub_rst>; - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&vopl { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/board/firefly/firefly-rk3288/MAINTAINERS b/board/firefly/firefly-rk3288/MAINTAINERS index 42db0bd5e1f..174027e770b 100644 --- a/board/firefly/firefly-rk3288/MAINTAINERS +++ b/board/firefly/firefly-rk3288/MAINTAINERS @@ -1,6 +1,7 @@ FIREFLY M: Simon Glass S: Maintained +F: arch/arm/dts/rk3288-firefly-u-boot.dtsi F: board/firefly/firefly-rk3288 F: include/configs/firefly-rk3288.h F: configs/firefly-rk3288_defconfig diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 661ac065ce3..a79e217c7ad 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -7,7 +7,7 @@ CONFIG_TEXT_BASE=0x01000000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-firefly" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_FIREFLY_RK3288=y @@ -18,7 +18,7 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set -CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-firefly.dtb" CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_CMD_GPIO=y @@ -36,6 +36,8 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -- cgit v1.3.1 From dc691ef150eb0f12072202d6090280c9af8a39a5 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 22:09:43 +0000 Subject: rockchip: rk3288-firefly: Fix slow Ethernet initializion For some reason the Ethernet PHY reset delay is set to 1 second, this cause an unneccecery long boot delay. Firefly-RK3288 use RTL8211 Ethernet PHY, datasheet list an initial 10ms delay and then a 30-76ms delay before accessing registers. Change to use 80ms delay instead of a full second to speed up Ethernet initializion in U-Boot. Also enable PHY_REALTEK, DM_ETH_PHY and PHY_GIGE to improve Ethernet PHY support in U-Boot. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3288-firefly-u-boot.dtsi | 4 ++++ configs/firefly-rk3288_defconfig | 3 +++ 2 files changed, 7 insertions(+) diff --git a/arch/arm/dts/rk3288-firefly-u-boot.dtsi b/arch/arm/dts/rk3288-firefly-u-boot.dtsi index 13f5be27a96..b7d13bcb860 100644 --- a/arch/arm/dts/rk3288-firefly-u-boot.dtsi +++ b/arch/arm/dts/rk3288-firefly-u-boot.dtsi @@ -48,6 +48,10 @@ bootph-some-ram; }; +&gmac { + snps,reset-delays-us = <0 10000 80000>; +}; + &gpio7 { /delete-property/ bootph-all; bootph-pre-ram; diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index a79e217c7ad..95fb20b8b24 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -58,6 +58,9 @@ CONFIG_MISC=y CONFIG_ROCKCHIP_EFUSE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y -- cgit v1.3.1 From 514839d5b1b41b58de721b65673c975818c3cfa0 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 22:09:44 +0000 Subject: rockchip: rk3288-firefly: Change to use FIT Change to use FIT and FIT_SIGNATURE when loading U-Boot proper in SPL to allow checksum validation and fallback loading of FIT from a different mmc device. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- configs/firefly-rk3288_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 95fb20b8b24..d8a671b7a8a 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -18,9 +18,15 @@ CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-firefly.dtb" CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -92,4 +98,5 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_CMD_DHRYSTONE=y +CONFIG_SPL_CRC32=y CONFIG_ERRNO_STR=y -- cgit v1.3.1 From 09ffc136aaf8b8eab12d2058044e8a68b3dd7b52 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Thu, 26 Dec 2024 17:20:37 +0800 Subject: arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps Ethernet ports designed and developed by FriendlyElec for IoT applications. Specification: - Rockchip RK3566 - 2GB LPDDR4X RAM - optional 32GB eMMC module - SD card slot - 2x 1000 Base-T - 3x LEDs (POWER, LAN, WAN) - 2x Buttons (Reset, MaskROM) - 1x USB 3.0 Port - Type-C 5V 2A Power Signed-off-by: Tianling Shen Link: https://lore.kernel.org/r/20241020173946.225960-2-cnsztl@gmail.com Signed-off-by: Heiko Stuebner [ upstream commit: 50decd493c8394c52d04561fe4ede34df27a46ba ] Signed-off-by: Tianling Shen Reviewed-by: Kever Yang --- .../src/arm64/rockchip/rk3566-nanopi-r3s.dts | 554 +++++++++++++++++++++ 1 file changed, 554 insertions(+) create mode 100644 dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts new file mode 100644 index 00000000000..a7a55d68dbb --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2024 Tianling Shen + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include "rk3566.dtsi" + +/ { + model = "FriendlyARM NanoPi R3S"; + compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&reset_button_pin>; + + button-reset { + label = "reset"; + gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <50>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&power_led_pin>, <&lan_led_pin>, <&wan_led_pin>; + + power_led: led-0 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + lan_led: led-1 { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + }; + + wan_led: led-2 { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + }; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vdd_usbc>; + }; + + vcc5v0_usb: regulator-vcc5v0_usb { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_usbc: regulator-vdd-usbc { + compatible = "regulator-fixed"; + regulator-name = "vdd_usbc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2_level3 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk_level2 + &gmac1m0_rgmii_bus_level3>; + snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&gpio4>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_reset_pin>; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pinctrl { + gpio-leds { + lan_led_pin: lan-led-pin { + rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + power_led_pin: power-led-pin { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac { + eth_phy_reset_pin: eth-phy-reset-pin { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie_reset_h: pcie-reset-h { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rockchip-key { + reset_button_pin: reset-button-pin { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rtc { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_usb_host_en: vcc5v0-usb-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-sdio; + no-mmc; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr50; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb>; + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; -- cgit v1.3.1 From 2222224bf9a6a3d7f28001a1ffdbb09ddb7e8808 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Thu, 26 Dec 2024 17:20:38 +0800 Subject: arm64: dts: rockchip: fix model name for FriendlyElec NanoPi R3S Use the marketing name for model name, this matches the dt-binding. Also update the website url in copyright. Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board") Suggested-by: Jonas Karlman Signed-off-by: Tianling Shen Link: https://lore.kernel.org/r/20241022193537.1117919-2-cnsztl@gmail.com Signed-off-by: Heiko Stuebner [ upstream commit: b5bf84206a5c77528f9dd4cbca4e72caa063c102 ] Signed-off-by: Tianling Shen Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts index a7a55d68dbb..6bc17f755b7 100644 --- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts +++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts @@ -3,7 +3,7 @@ * Copyright (c) 2020 Rockchip Electronics Co., Ltd. * * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd. - * (http://www.friendlyarm.com) + * (http://www.friendlyelec.com) * * Copyright (c) 2024 Tianling Shen */ @@ -17,7 +17,7 @@ #include "rk3566.dtsi" / { - model = "FriendlyARM NanoPi R3S"; + model = "FriendlyElec NanoPi R3S"; compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566"; aliases { -- cgit v1.3.1 From b9afcf4062c93d5c1766b33d083a9dff8f2d00d3 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Thu, 26 Dec 2024 17:20:39 +0800 Subject: arm64: dts: rockchip: replace deprecated snps, reset props for NanoPi R3S Replace deprecated snps,reset props and move them to the PHY node. Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board") Suggested-by: Jonas Karlman Signed-off-by: Tianling Shen Link: https://lore.kernel.org/r/20241022193537.1117919-3-cnsztl@gmail.com Signed-off-by: Heiko Stuebner [ upstream commit: 82b2868937883b65732da498b26366d34db61510 ] Signed-off-by: Tianling Shen Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts index 6bc17f755b7..66a00cddda0 100644 --- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts +++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts @@ -149,10 +149,6 @@ &gmac1m0_rx_bus2 &gmac1m0_rgmii_clk_level2 &gmac1m0_rgmii_bus_level3>; - snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; status = "okay"; }; @@ -414,6 +410,9 @@ interrupts = ; pinctrl-names = "default"; pinctrl-0 = <ð_phy_reset_pin>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; }; }; -- cgit v1.3.1 From d3c686212faee17976a87ff41872f895e1b57e43 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Thu, 26 Dec 2024 17:20:40 +0800 Subject: arm64: dts: rockchip: sort props in pmu_io_domains node for NanoPi R3S The status prop is typically the last prop. Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board") Suggested-by: Jonas Karlman Signed-off-by: Tianling Shen Link: https://lore.kernel.org/r/20241022193537.1117919-4-cnsztl@gmail.com Signed-off-by: Heiko Stuebner [ upstream commit: 17e150fdd983c7e59b9240e34a166285f3c3fb39 ] Signed-off-by: Tianling Shen Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts index 66a00cddda0..243574f8da7 100644 --- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts +++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts @@ -476,7 +476,6 @@ }; &pmu_io_domains { - status = "okay"; pmuio1-supply = <&vcc3v3_pmu>; pmuio2-supply = <&vcc3v3_pmu>; vccio1-supply = <&vccio_acodec>; @@ -486,6 +485,7 @@ vccio5-supply = <&vcc_1v8>; vccio6-supply = <&vcc_3v3>; vccio7-supply = <&vcc_3v3>; + status = "okay"; }; &sdhci { -- cgit v1.3.1 From 30db98ed87d261d292684ce3f1da804e9182f983 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Thu, 26 Dec 2024 17:20:41 +0800 Subject: arm64: dts: rockchip: enable eMMC HS200 mode for NanoPi R3S It is required to boot from eMMC without additional patch in u-boot. Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board") Suggested-by: Jonas Karlman Signed-off-by: Tianling Shen Link: https://lore.kernel.org/r/20241022193537.1117919-5-cnsztl@gmail.com Signed-off-by: Heiko Stuebner [ upstream commit: 1b5365034410f1ca21adadadd492b99bdf4f2c55 ] Signed-off-by: Tianling Shen Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts index 243574f8da7..03a2f90f621 100644 --- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts +++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts @@ -491,6 +491,7 @@ &sdhci { bus-width = <8>; max-frequency = <200000000>; + mmc-hs200-1_8v; non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; -- cgit v1.3.1 From c16cd170b903c25056d214df0277e415d1bc9dc7 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Thu, 26 Dec 2024 17:20:42 +0800 Subject: arm64: dts: rockchip: reorder mmc aliases for NanoPi R3S Typically any non-removable storage (emmc) is listed before removable storage (sd-card) options. Also U-Boot will try to override and use mmc0=sdhci and mmc1=sdmmc0 for all rk356x boards. Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board") Suggested-by: Jonas Karlman Signed-off-by: Tianling Shen Link: https://lore.kernel.org/r/20241022193537.1117919-6-cnsztl@gmail.com Signed-off-by: Heiko Stuebner [ upstream commit: b7cd1115456d312f8c5e60c80fdc35fd35ea6eab ] Signed-off-by: Tianling Shen Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts index 03a2f90f621..fb1f65c8688 100644 --- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts +++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts @@ -22,8 +22,8 @@ aliases { ethernet0 = &gmac1; - mmc0 = &sdmmc0; - mmc1 = &sdhci; + mmc0 = &sdhci; + mmc1 = &sdmmc0; }; chosen: chosen { -- cgit v1.3.1 From bf4a33e725ae02cae064a03ea90c45779780f323 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Thu, 26 Dec 2024 17:20:43 +0800 Subject: board: rockchip: add FriendlyElec NanoPi R3S The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps Ethernet ports designed and developed by FriendlyElec for IoT applications. Specification: - Rockchip RK3566 - 2GB LPDDR4X RAM - optional 32GB eMMC module - SD card slot - 2x 1000 Base-T - 3x LEDs (POWER, LAN, WAN) - 2x Buttons (Reset, MaskROM) - 1x USB 3.0 Port - Type-C 5V 2A Power Signed-off-by: Tianling Shen Reviewed-by: Kever Yang Signed-off-by: Kever Yang --- arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi | 8 ++++ board/rockchip/evb_rk3568/MAINTAINERS | 7 +++ configs/nanopi-r3s-rk3566_defconfig | 75 ++++++++++++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + 4 files changed, 91 insertions(+) create mode 100644 arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi create mode 100644 configs/nanopi-r3s-rk3566_defconfig diff --git a/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi b/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi new file mode 100644 index 00000000000..b66e5015d60 --- /dev/null +++ b/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "rk356x-u-boot.dtsi" + +&vcc5v0_usb { + /delete-property/ regulator-always-on; + /delete-property/ regulator-boot-on; +}; diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index 588134ecb27..b2780401a39 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -28,6 +28,13 @@ F: configs/lubancat-2-rk3568_defconfig F: arch/arm/dts/rk3568-lubancat-2.dts F: arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi +NANOPI-R3S +M: Tianling Shen +R: Jonas Karlman +S: Maintained +F: configs/nanopi-r3s-rk3566_defconfig +F: arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi + NANOPI-R5C M: Tianling Shen R: Jonas Karlman diff --git a/configs/nanopi-r3s-rk3566_defconfig b/configs/nanopi-r3s-rk3566_defconfig new file mode 100644 index 00000000000..870613f690a --- /dev/null +++ b/configs/nanopi-r3s-rk3566_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-nanopi-r3s" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_SERIAL=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-nanopi-r3s.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index ea98b73d33c..538b9df69bf 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -99,6 +99,7 @@ List of mainline supported Rockchip boards: * rk3566 - Anbernic RGxx3 (anbernic-rgxx3-rk3566) + - FriendlyElec NanoPi R3S (nanopi-r3s-rk3566) - Hardkernel ODROID-M1S (odroid-m1s-rk3566) - Pine64 PineTab2 (pinetab2-rk3566) - Pine64 Quartz64-A Board (quartz64-a-rk3566) -- cgit v1.3.1 From d113d47976c6428e5afc48445e0561f61f657618 Mon Sep 17 00:00:00 2001 From: Sam Edwards Date: Sat, 4 Jan 2025 01:57:01 +0000 Subject: arm64: dts: rockchip: Split up RK3588's PCIe pinctrls These pinctrls manage the low-speed PCIe signals: - CLKREQ#: An output on the RK3588 (both RC or EP modes), used to request that external clock-generation circuitry provide a clock. - PERST#: An input on the RK3588 in EP mode, used to detect a reset signal from the RC. In RC mode, the hardware does not use this signal: Linux itself generates it by putting the pin in GPIO mode. - WAKE#: In EP mode, this is an output; in RC mode, this is an input. Each of these signals serves a distinct purpose, and more importantly, PERST# should not be muxed when the RK3588 is in the RC role. Bundling them together in pinctrl groups prevents proper use: indeed, almost none of the current board-specific .dts files make any use of them. (Exception: Rock 5A recently had a patch land that misuses _pins; this patch corrects that.) However, on some RK3588 boards, the PCIe 3 controller will indefinitely stall the boot if CLKREQ# is not muxed (details in the next patch). This patch unbundles the signals to allow them to be used. Signed-off-by: Sam Edwards Link: https://lore.kernel.org/r/20240912025034.180233-2-CFSworks@gmail.com Signed-off-by: Heiko Stuebner [ upstream commit: 4294e32111781b3de4d73b944cbd1bc1662a9a7a ] (cherry picked from commit 8713425fa162b61bcf5f7a6dcd171fddfb12be36) Reviewed-by: Kever Yang --- .../src/arm64/rockchip/rk3588-base-pinctrl.dtsi | 271 +++++++++++++++++---- .../src/arm64/rockchip/rk3588s-rock-5a.dts | 6 +- 2 files changed, 228 insertions(+), 49 deletions(-) diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base-pinctrl.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base-pinctrl.dtsi index d1368418502..7f874c77410 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-base-pinctrl.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-base-pinctrl.dtsi @@ -1612,23 +1612,43 @@ pcie20x1 { /omit-if-no-ref/ - pcie20x1m0_pins: pcie20x1m0-pins { + pcie20x1m0_clkreqn: pcie20x1m0-clkreqn { rockchip,pins = /* pcie20x1_2_clkreqn_m0 */ - <3 RK_PC7 4 &pcfg_pull_none>, + <3 RK_PC7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1m0_perstn: pcie20x1m0-perstn { + rockchip,pins = /* pcie20x1_2_perstn_m0 */ - <3 RK_PD1 4 &pcfg_pull_none>, + <3 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1m0_waken: pcie20x1m0-waken { + rockchip,pins = /* pcie20x1_2_waken_m0 */ <3 RK_PD0 4 &pcfg_pull_none>; }; /omit-if-no-ref/ - pcie20x1m1_pins: pcie20x1m1-pins { + pcie20x1m1_clkreqn: pcie20x1m1-clkreqn { rockchip,pins = /* pcie20x1_2_clkreqn_m1 */ - <4 RK_PB7 4 &pcfg_pull_none>, + <4 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1m1_perstn: pcie20x1m1-perstn { + rockchip,pins = /* pcie20x1_2_perstn_m1 */ - <4 RK_PC1 4 &pcfg_pull_none>, + <4 RK_PC1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1m1_waken: pcie20x1m1-waken { + rockchip,pins = /* pcie20x1_2_waken_m1 */ <4 RK_PC0 4 &pcfg_pull_none>; }; @@ -1654,52 +1674,127 @@ pcie30x1 { /omit-if-no-ref/ - pcie30x1m0_pins: pcie30x1m0-pins { + pcie30x1m0_0_clkreqn: pcie30x1m0-0-clkreqn { rockchip,pins = /* pcie30x1_0_clkreqn_m0 */ - <0 RK_PC0 12 &pcfg_pull_none>, + <0 RK_PC0 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m0_0_perstn: pcie30x1m0-0-perstn { + rockchip,pins = /* pcie30x1_0_perstn_m0 */ - <0 RK_PC5 12 &pcfg_pull_none>, + <0 RK_PC5 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m0_0_waken: pcie30x1m0-0-waken { + rockchip,pins = /* pcie30x1_0_waken_m0 */ - <0 RK_PC4 12 &pcfg_pull_none>, + <0 RK_PC4 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m0_1_clkreqn: pcie30x1m0-1-clkreqn { + rockchip,pins = /* pcie30x1_1_clkreqn_m0 */ - <0 RK_PB5 12 &pcfg_pull_none>, + <0 RK_PB5 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m0_1_perstn: pcie30x1m0-1-perstn { + rockchip,pins = /* pcie30x1_1_perstn_m0 */ - <0 RK_PB7 12 &pcfg_pull_none>, + <0 RK_PB7 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m0_1_waken: pcie30x1m0-1-waken { + rockchip,pins = /* pcie30x1_1_waken_m0 */ <0 RK_PB6 12 &pcfg_pull_none>; }; /omit-if-no-ref/ - pcie30x1m1_pins: pcie30x1m1-pins { + pcie30x1m1_0_clkreqn: pcie30x1m1-0-clkreqn { rockchip,pins = /* pcie30x1_0_clkreqn_m1 */ - <4 RK_PA3 4 &pcfg_pull_none>, + <4 RK_PA3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_0_perstn: pcie30x1m1-0-perstn { + rockchip,pins = /* pcie30x1_0_perstn_m1 */ - <4 RK_PA5 4 &pcfg_pull_none>, + <4 RK_PA5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_0_waken: pcie30x1m1-0-waken { + rockchip,pins = /* pcie30x1_0_waken_m1 */ - <4 RK_PA4 4 &pcfg_pull_none>, + <4 RK_PA4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_1_clkreqn: pcie30x1m1-1-clkreqn { + rockchip,pins = /* pcie30x1_1_clkreqn_m1 */ - <4 RK_PA0 4 &pcfg_pull_none>, + <4 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_1_perstn: pcie30x1m1-1-perstn { + rockchip,pins = /* pcie30x1_1_perstn_m1 */ - <4 RK_PA2 4 &pcfg_pull_none>, + <4 RK_PA2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_1_waken: pcie30x1m1-1-waken { + rockchip,pins = /* pcie30x1_1_waken_m1 */ <4 RK_PA1 4 &pcfg_pull_none>; }; /omit-if-no-ref/ - pcie30x1m2_pins: pcie30x1m2-pins { + pcie30x1m2_0_clkreqn: pcie30x1m2-0-clkreqn { rockchip,pins = /* pcie30x1_0_clkreqn_m2 */ - <1 RK_PB5 4 &pcfg_pull_none>, + <1 RK_PB5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_0_perstn: pcie30x1m2-0-perstn { + rockchip,pins = /* pcie30x1_0_perstn_m2 */ - <1 RK_PB4 4 &pcfg_pull_none>, + <1 RK_PB4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_0_waken: pcie30x1m2-0-waken { + rockchip,pins = /* pcie30x1_0_waken_m2 */ - <1 RK_PB3 4 &pcfg_pull_none>, + <1 RK_PB3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_1_clkreqn: pcie30x1m2-1-clkreqn { + rockchip,pins = /* pcie30x1_1_clkreqn_m2 */ - <1 RK_PA0 4 &pcfg_pull_none>, + <1 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_1_perstn: pcie30x1m2-1-perstn { + rockchip,pins = /* pcie30x1_1_perstn_m2 */ - <1 RK_PA7 4 &pcfg_pull_none>, + <1 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_1_waken: pcie30x1m2-1-waken { + rockchip,pins = /* pcie30x1_1_waken_m2 */ <1 RK_PA1 4 &pcfg_pull_none>; }; @@ -1721,45 +1816,85 @@ pcie30x2 { /omit-if-no-ref/ - pcie30x2m0_pins: pcie30x2m0-pins { + pcie30x2m0_clkreqn: pcie30x2m0-clkreqn { rockchip,pins = /* pcie30x2_clkreqn_m0 */ - <0 RK_PD1 12 &pcfg_pull_none>, + <0 RK_PD1 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m0_perstn: pcie30x2m0-perstn { + rockchip,pins = /* pcie30x2_perstn_m0 */ - <0 RK_PD4 12 &pcfg_pull_none>, + <0 RK_PD4 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m0_waken: pcie30x2m0-waken { + rockchip,pins = /* pcie30x2_waken_m0 */ <0 RK_PD2 12 &pcfg_pull_none>; }; /omit-if-no-ref/ - pcie30x2m1_pins: pcie30x2m1-pins { + pcie30x2m1_clkreqn: pcie30x2m1-clkreqn { rockchip,pins = /* pcie30x2_clkreqn_m1 */ - <4 RK_PA6 4 &pcfg_pull_none>, + <4 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m1_perstn: pcie30x2m1-perstn { + rockchip,pins = /* pcie30x2_perstn_m1 */ - <4 RK_PB0 4 &pcfg_pull_none>, + <4 RK_PB0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m1_waken: pcie30x2m1-waken { + rockchip,pins = /* pcie30x2_waken_m1 */ <4 RK_PA7 4 &pcfg_pull_none>; }; /omit-if-no-ref/ - pcie30x2m2_pins: pcie30x2m2-pins { + pcie30x2m2_clkreqn: pcie30x2m2-clkreqn { rockchip,pins = /* pcie30x2_clkreqn_m2 */ - <3 RK_PD2 4 &pcfg_pull_none>, + <3 RK_PD2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m2_perstn: pcie30x2m2-perstn { + rockchip,pins = /* pcie30x2_perstn_m2 */ - <3 RK_PD4 4 &pcfg_pull_none>, + <3 RK_PD4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m2_waken: pcie30x2m2-waken { + rockchip,pins = /* pcie30x2_waken_m2 */ <3 RK_PD3 4 &pcfg_pull_none>; }; /omit-if-no-ref/ - pcie30x2m3_pins: pcie30x2m3-pins { + pcie30x2m3_clkreqn: pcie30x2m3-clkreqn { rockchip,pins = /* pcie30x2_clkreqn_m3 */ - <1 RK_PD7 4 &pcfg_pull_none>, + <1 RK_PD7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m3_perstn: pcie30x2m3-perstn { + rockchip,pins = /* pcie30x2_perstn_m3 */ - <1 RK_PB7 4 &pcfg_pull_none>, + <1 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m3_waken: pcie30x2m3-waken { + rockchip,pins = /* pcie30x2_waken_m3 */ <1 RK_PB6 4 &pcfg_pull_none>; }; @@ -1774,45 +1909,85 @@ pcie30x4 { /omit-if-no-ref/ - pcie30x4m0_pins: pcie30x4m0-pins { + pcie30x4m0_clkreqn: pcie30x4m0-clkreqn { rockchip,pins = /* pcie30x4_clkreqn_m0 */ - <0 RK_PC6 12 &pcfg_pull_none>, + <0 RK_PC6 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m0_perstn: pcie30x4m0-perstn { + rockchip,pins = /* pcie30x4_perstn_m0 */ - <0 RK_PD0 12 &pcfg_pull_none>, + <0 RK_PD0 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m0_waken: pcie30x4m0-waken { + rockchip,pins = /* pcie30x4_waken_m0 */ <0 RK_PC7 12 &pcfg_pull_none>; }; /omit-if-no-ref/ - pcie30x4m1_pins: pcie30x4m1-pins { + pcie30x4m1_clkreqn: pcie30x4m1-clkreqn { rockchip,pins = /* pcie30x4_clkreqn_m1 */ - <4 RK_PB4 4 &pcfg_pull_none>, + <4 RK_PB4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m1_perstn: pcie30x4m1-perstn { + rockchip,pins = /* pcie30x4_perstn_m1 */ - <4 RK_PB6 4 &pcfg_pull_none>, + <4 RK_PB6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m1_waken: pcie30x4m1-waken { + rockchip,pins = /* pcie30x4_waken_m1 */ <4 RK_PB5 4 &pcfg_pull_none>; }; /omit-if-no-ref/ - pcie30x4m2_pins: pcie30x4m2-pins { + pcie30x4m2_clkreqn: pcie30x4m2-clkreqn { rockchip,pins = /* pcie30x4_clkreqn_m2 */ - <3 RK_PC4 4 &pcfg_pull_none>, + <3 RK_PC4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m2_perstn: pcie30x4m2-perstn { + rockchip,pins = /* pcie30x4_perstn_m2 */ - <3 RK_PC6 4 &pcfg_pull_none>, + <3 RK_PC6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m2_waken: pcie30x4m2-waken { + rockchip,pins = /* pcie30x4_waken_m2 */ <3 RK_PC5 4 &pcfg_pull_none>; }; /omit-if-no-ref/ - pcie30x4m3_pins: pcie30x4m3-pins { + pcie30x4m3_clkreqn: pcie30x4m3-clkreqn { rockchip,pins = /* pcie30x4_clkreqn_m3 */ - <1 RK_PB0 4 &pcfg_pull_none>, + <1 RK_PB0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m3_perstn: pcie30x4m3-perstn { + rockchip,pins = /* pcie30x4_perstn_m3 */ - <1 RK_PB2 4 &pcfg_pull_none>, + <1 RK_PB2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m3_waken: pcie30x4m3-waken { + rockchip,pins = /* pcie30x4_waken_m3 */ <1 RK_PB1 4 &pcfg_pull_none>; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts index 294b99dd50d..87fce8d9a96 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts @@ -310,7 +310,7 @@ }; &pcie2x1l2 { - pinctrl-0 = <&pcie20x1m0_pins>; + pinctrl-0 = <&pcie2_reset>, <&pcie20x1m0_clkreqn>, <&pcie20x1m0_waken>; pinctrl-names = "default"; reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_wf>; @@ -328,6 +328,10 @@ pow_en: pow-en { rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; }; + + pcie2_reset: pcie2-reset { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; power { -- cgit v1.3.1 From 2cbffc157930baa773c7acc1c727436ab5e9e728 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Sat, 4 Jan 2025 01:57:02 +0000 Subject: arm64: dts: rockchip: Add HDMI0 node to rk3588 Add support for the HDMI0 output port found on RK3588 SoC. Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20241019-rk3588-hdmi0-dt-v2-1-466cd80e8ff9@collabora.com Signed-off-by: Heiko Stuebner [ upstream commit: d7bb71e69f58c1b3665a9f926bf8d3855111bf8e ] (cherry picked from commit a839348380c2072e00a26bbdb80744982fe04c56) Reviewed-by: Kever Yang --- dts/upstream/src/arm64/rockchip/rk3588-base.dtsi | 41 ++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi index fc67585b64b..a337f3fb837 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi @@ -1370,6 +1370,47 @@ status = "disabled"; }; + hdmi0: hdmi@fde80000 { + compatible = "rockchip,rk3588-dw-hdmi-qp"; + reg = <0x0 0xfde80000 0x0 0x20000>; + clocks = <&cru PCLK_HDMITX0>, + <&cru CLK_HDMITX0_EARC>, + <&cru CLK_HDMITX0_REF>, + <&cru MCLK_I2S5_8CH_TX>, + <&cru CLK_HDMIHDP0>, + <&cru HCLK_VO1>; + clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; + interrupts = , + , + , + , + ; + interrupt-names = "avp", "cec", "earc", "main", "hpd"; + phys = <&hdptxphy_hdmi0>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda>; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; + reset-names = "ref", "hdp"; + rockchip,grf = <&sys_grf>; + rockchip,vo-grf = <&vo1_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi0_in: port@0 { + reg = <0>; + }; + + hdmi0_out: port@1 { + reg = <1>; + }; + }; + }; + qos_gpu_m0: qos@fdf35000 { compatible = "rockchip,rk3588-qos", "syscon"; reg = <0x0 0xfdf35000 0x0 0x20>; -- cgit v1.3.1 From a0dd3480a7dc028b23ab640eacb652c5b0cf2b77 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Sat, 4 Jan 2025 01:57:03 +0000 Subject: arm64: dts: rockchip: add Radxa ROCK 5C Radxa ROCK 5C is a 8K computer for everything[1] using the Rockchip RK3588S2 chip: - Rockchip RK3588S2 - Quad A76 and Quad A55 CPU - 6 TOPS NPU - up to 32GB LPDDR4x RAM - eMMC / SPI flash connector - Micro SD Card slot - Gigabit ethernet port (supports PoE with add-on PoE HAT) - WiFi6 / BT5.4 - 1x USB 3.0 Type-A HOST port - 1x USB 3.0 Type-A OTG port - 2x USB 2.0 Type-A HOST port - 1x USB Type-C 5V power port [1] https://radxa.com/products/rock5/5c Signed-off-by: FUKAUMI Naoki Link: https://lore.kernel.org/r/20241021090548.1052-2-naoki@radxa.com Signed-off-by: Heiko Stuebner [ upstream commit: 3ddf5cdb77e6efd6fe9b70f36dec935e324a3cd2 ] (cherry picked from commit f80689fcef4b9b07a97b629b4075cc1a4c21a68e) Reviewed-by: Kever Yang --- .../src/arm64/rockchip/rk3588s-rock-5c.dts | 920 +++++++++++++++++++++ 1 file changed, 920 insertions(+) create mode 100644 dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts new file mode 100644 index 00000000000..9b14d5383cd --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts @@ -0,0 +1,920 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd. + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "rk3588s.dtsi" + +/ { + model = "Radxa ROCK 5C"; + compatible = "radxa,rock-5c", "rockchip,rk3588s"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + analog-sound { + compatible = "audio-graph-card"; + label = "rk3588-es8316"; + dais = <&i2s0_8ch_p0>; + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + }; + + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led-0 { + color = ; + default-state = "on"; + function = LED_FUNCTION_POWER; + gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + color = ; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <0 64 128 192 255>; + fan-supply = <&vcc_5v0>; + pwms = <&pwm3 0 10000 0>; + }; + + pcie2x1l2_3v3: regulator-pcie2x1l2-3v3 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pow_en>; + regulator-name = "pcie2x1l2_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sysin>; + }; + + vcc5v_dcin: regulator-vcc5v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb_host: regulator-vcc5v0-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren_h>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sysin>; + }; + + vcc5v0_usb_otg0: regulator-vcc5v0-usb-otg0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwren_h>; + regulator-name = "vcc5v0_usb_otg0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sysin>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc_sysin>; + }; + + vcc_3v3_pmu: regulator-vcc-3v3-pmu { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_s0: regulator-vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_1v8_s0>; + }; + + vcc_5v0: regulator-vcc-5v0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_pwren_h>; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sysin>; + }; + + vcc_sysin: regulator-vcc-sysin { + compatible = "regulator-fixed"; + regulator-name = "vcc_sysin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_dcin>; + }; + + vcca: regulator-vcca { + compatible = "regulator-fixed"; + regulator-name = "vcca"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + vin-supply = <&vcc_sysin>; + }; + + vdd_3v3: regulator-vdd-3v3 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_wifi_pwr>; + regulator-name = "vdd_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac1 { + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3_s0>; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus + &gmac1_clkinout>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&hdmi0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec + &hdmim1_tx0_hpd + &hdmim0_tx0_scl + &hdmim0_tx0_sda>; + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sysin>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sysin>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + vcc-supply = <&vcc_3v3_pmu>; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sysin>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m2_xfer>; + status = "okay"; + + rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "rtcic_32kout"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_l>; + }; +}; + +&i2c7 { + status = "okay"; + + audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rstn>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20x1_2_perstn_m0>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&pcie2x1l2_3v3>; + status = "okay"; +}; + +&pinctrl { + leds { + led_pins: led-pins { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mdio { + gmac1_rstn: gmac1-rstn { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie20x1_2_perstn_m0: pcie20x1-2-perstn-m0 { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pow_en: pow-en { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtc { + rtc_int_l: rtc-int-l { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren_h: usb-host-pwren-h { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg_pwren_h: usb-otg-pwren-h { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_wifi_pwr: usb-wifi-pwr { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc_5v0_pwren_h: vcc-5v0-pwren-h { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m1_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspim0_pins>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc_sysin>; + vcc2-supply = <&vcc_sysin>; + vcc3-supply = <&vcc_sysin>; + vcc4-supply = <&vcc_sysin>; + vcc5-supply = <&vcc_sysin>; + vcc6-supply = <&vcc_sysin>; + vcc7-supply = <&vcc_sysin>; + vcc8-supply = <&vcc_sysin>; + vcc9-supply = <&vcc_sysin>; + vcc10-supply = <&vcc_sysin>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc_sysin>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcca>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg3 { + regulator-name = "vdd_logic_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu_ddr_s3: dcdc-reg10 { + regulator-name = "vcc1v8_pmu_ddr_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_1v8_s0: pldo-reg1 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8_s0: pldo-reg2 { + regulator-name = "vcca_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-name = "vdda_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-name = "vcca_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdda_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdda_0v75_s0: nldo-reg3 { + regulator-name = "vdda_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-name = "vdda_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vcc5v0_usb_otg0>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + /* connected to USB hub, which is powered by vcc_5v0 */ + phy-supply = <&vcc_5v0>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host2_xhci { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; -- cgit v1.3.1 From e1661639d976d382fed73323b2c62874a25ab0e6 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Sat, 4 Jan 2025 01:57:04 +0000 Subject: rockchip: Add support for Radxa ROCK 5C Radxa ROCK 5C[1] is a Rockchip RK3588S2 based single board computer. [1] https://radxa.com/products/rock5/5c Signed-off-by: FUKAUMI Naoki Reviewed-by: Kever Yang --- arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi | 11 +++++ arch/arm/mach-rockchip/rk3588/Kconfig | 21 ++++++++ board/radxa/rock-5c-rk3588s/Kconfig | 12 +++++ board/radxa/rock-5c-rk3588s/MAINTAINERS | 7 +++ configs/rock-5c-rk3588s_defconfig | 84 ++++++++++++++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + include/configs/rock-5c-rk3588s.h | 15 ++++++ 7 files changed, 151 insertions(+) create mode 100644 arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi create mode 100644 board/radxa/rock-5c-rk3588s/Kconfig create mode 100644 board/radxa/rock-5c-rk3588s/MAINTAINERS create mode 100644 configs/rock-5c-rk3588s_defconfig create mode 100644 include/configs/rock-5c-rk3588s.h diff --git a/arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi b/arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi new file mode 100644 index 00000000000..1dc574c2f21 --- /dev/null +++ b/arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024-2025 Radxa Computer (Shenzhen) Co., Ltd. + */ + +#include "rk3588s-u-boot.dtsi" + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 7d817e7f1bd..155b8f00ca2 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -282,6 +282,26 @@ config TARGET_ROCK_5_ITX_RK3588 Front-panel connectors for audio and case-power, -leds Powered by either 12V, ATX power-supply or PoE +config TARGET_ROCK_5C_RK3588S + bool "Radxa ROCK 5C RK3588S2 board" + select BOARD_LATE_INIT + help + Radxa ROCK 5C is a Rockchip RK3588S2 based single board computer. + + Specification: + + Quad A76 and Quad A55 CPU + 6 TOPS NPU + up to 32GB LPDDR4x RAM + eMMC / SPI flash connector + Micro SD Card slot + Gigabit ethernet port (supports PoE with add-on PoE HAT) + WiFi6 / BT5.4 + 1x USB 3.0 Type-A HOST port + 1x USB 3.0 Type-A OTG port + 2x USB 2.0 Type-A HOST port + 1x USB Type-C 5V power port + config TARGET_SIGE7_RK3588 bool "ArmSoM Sige7 RK3588 board" select BOARD_LATE_INIT @@ -421,6 +441,7 @@ source "board/turing/turing-rk1-rk3588/Kconfig" source "board/radxa/rock5a-rk3588s/Kconfig" source "board/radxa/rock5b-rk3588/Kconfig" source "board/radxa/rock-5-itx-rk3588/Kconfig" +source "board/radxa/rock-5c-rk3588s/Kconfig" source "board/rockchip/evb_rk3588/Kconfig" source "board/rockchip/toybrick_rk3588/Kconfig" source "board/theobroma-systems/jaguar_rk3588/Kconfig" diff --git a/board/radxa/rock-5c-rk3588s/Kconfig b/board/radxa/rock-5c-rk3588s/Kconfig new file mode 100644 index 00000000000..ec964bdcb93 --- /dev/null +++ b/board/radxa/rock-5c-rk3588s/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ROCK_5C_RK3588S + +config SYS_BOARD + default "rock-5c-rk3588s" + +config SYS_VENDOR + default "radxa" + +config SYS_CONFIG_NAME + default "rock-5c-rk3588s" + +endif diff --git a/board/radxa/rock-5c-rk3588s/MAINTAINERS b/board/radxa/rock-5c-rk3588s/MAINTAINERS new file mode 100644 index 00000000000..17183c739d6 --- /dev/null +++ b/board/radxa/rock-5c-rk3588s/MAINTAINERS @@ -0,0 +1,7 @@ +ROCK-5C-RK3588S +M: FUKAUMI Naoki +S: Maintained +F: arch/arm/dts/rk3588s-rock-5c-u-boot.dtsi +F: board/radxa/rock-5c-rk3588s/ +F: configs/rock-5c-rk3588s_defconfig +F: include/configs/rock-5c-rk3588s.h diff --git a/configs/rock-5c-rk3588s_defconfig b/configs/rock-5c-rk3588s_defconfig new file mode 100644 index 00000000000..59f9f25edcb --- /dev/null +++ b/configs/rock-5c-rk3588s_defconfig @@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-rock-5c" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_ROCK_5C_RK3588S=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5c.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 538b9df69bf..1407080f1f4 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -143,6 +143,7 @@ List of mainline supported Rockchip boards: - Radxa ROCK 5 ITX (rock-5-itx-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) - Radxa ROCK 5B (rock5b-rk3588) + - Radxa ROCK 5C (rock-5c-rk3588s) - Rockchip Toybrick TB-RK3588X (toybrick-rk3588) - Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588) - Theobroma Systems SOM-RK3588-Q7 - Tiger (tiger-rk3588) diff --git a/include/configs/rock-5c-rk3588s.h b/include/configs/rock-5c-rk3588s.h new file mode 100644 index 00000000000..0fd76c96f0c --- /dev/null +++ b/include/configs/rock-5c-rk3588s.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024-2025 Radxa Computer (Shenzhen) Co., Ltd. + */ + +#ifndef __ROCK_5C_RK3588S_H +#define __ROCK_5C_RK3588S_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#endif /* __ROCK_5C_RK3588S_H */ -- cgit v1.3.1 From 43728edfc266bb0a952dce7dde4060cc6cd4786c Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Mon, 16 Dec 2024 13:44:32 +0100 Subject: rockchip: use OF_UPSTREAM for rk3066a/rk3188 The device tree for rk3066a/rk3188 combined is now available in the /dts/upstream directory. Use imply OF_UPSTREAM to migrate all rk3066a/rk3188 boards. Signed-off-by: Johan Jonker Reviewed-by: Sumit Garg Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 6 - arch/arm/dts/rk3066a-mk808.dts | 241 ----------- arch/arm/dts/rk3066a-u-boot.dtsi | 20 - arch/arm/dts/rk3066a.dtsi | 880 -------------------------------------- arch/arm/dts/rk3188-radxarock.dts | 389 ----------------- arch/arm/dts/rk3188-u-boot.dtsi | 17 - arch/arm/dts/rk3188.dtsi | 815 ----------------------------------- arch/arm/dts/rk3xxx.dtsi | 488 --------------------- arch/arm/mach-rockchip/Kconfig | 2 + configs/mk808_defconfig | 4 +- configs/rock_defconfig | 4 +- 11 files changed, 6 insertions(+), 2860 deletions(-) delete mode 100644 arch/arm/dts/rk3066a-mk808.dts delete mode 100644 arch/arm/dts/rk3066a.dtsi delete mode 100644 arch/arm/dts/rk3188-radxarock.dts delete mode 100644 arch/arm/dts/rk3188.dtsi delete mode 100644 arch/arm/dts/rk3xxx.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 22d121ae318..aef0425c967 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -55,15 +55,9 @@ dtb-$(CONFIG_MACH_S700) += \ dtb-$(CONFIG_ROCKCHIP_RK3036) += \ rk3036-sdk.dtb -dtb-$(CONFIG_ROCKCHIP_RK3066) += \ - rk3066a-mk808.dtb - dtb-$(CONFIG_ROCKCHIP_RK3128) += \ rk3128-evb.dtb -dtb-$(CONFIG_ROCKCHIP_RK3188) += \ - rk3188-radxarock.dtb - dtb-$(CONFIG_ROCKCHIP_RK322X) += \ rk3229-evb.dtb diff --git a/arch/arm/dts/rk3066a-mk808.dts b/arch/arm/dts/rk3066a-mk808.dts deleted file mode 100644 index 06790f05b39..00000000000 --- a/arch/arm/dts/rk3066a-mk808.dts +++ /dev/null @@ -1,241 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 PaweÅ‚ Jarosz - */ - -/dts-v1/; -#include -#include "rk3066a.dtsi" - -/ { - model = "Rikomagic MK808"; - compatible = "rikomagic,mk808", "rockchip,rk3066a"; - - aliases { - mmc0 = &mmc0; - mmc1 = &mmc1; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - memory@60000000 { - reg = <0x60000000 0x40000000>; - device_type = "memory"; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <2500000>; - poll-interval = <100>; - - button-recovery { - label = "recovery"; - linux,code = ; - press-threshold-microvolt = <0>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - blue_led: led-0 { - label = "mk808:blue:power"; - gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "default-on"; - }; - }; - - hdmi_con { - compatible = "hdmi-connector"; - type = "c"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - vcc_2v5: vcc-2v5 { - compatible = "regulator-fixed"; - regulator-name = "vcc_2v5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - vcc_io: vcc-io { - compatible = "regulator-fixed"; - regulator-name = "vcc_io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&host_drv>; - pinctrl-names = "default"; - regulator-always-on; - regulator-name = "host-pwr"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_otg: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&otg_drv>; - pinctrl-names = "default"; - regulator-always-on; - regulator-name = "vcc_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_sd: sdmmc-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&sdmmc_pwr>; - pinctrl-names = "default"; - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_wifi: sdio-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&wifi_pwr>; - pinctrl-names = "default"; - regulator-name = "vcc_wifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_in_vop1 { - status = "disabled"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - vmmc-supply = <&vcc_sd>; - status = "okay"; -}; - -&mmc1 { - bus-width = <4>; - non-removable; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; - pinctrl-names = "default"; - vmmc-supply = <&vcc_wifi>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - }; -}; - -&nfc { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - nand@0 { - reg = <0>; - label = "rk-nand"; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-ecc-step-size = <1024>; - nand-ecc-strength = <40>; - nand-is-boot-medium; - rockchip,boot-blks = <8>; - rockchip,boot-ecc-strength = <24>; - }; -}; - -&pinctrl { - usb-host { - host_drv: host-drv { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - usb-otg { - otg_drv: otg-drv { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - sdmmc { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_default>; - }; - }; - - sdio { - wifi_pwr: wifi-pwr { - rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&saradc { - vref-supply = <&vcc_2v5>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&vop0 { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3066a-u-boot.dtsi b/arch/arm/dts/rk3066a-u-boot.dtsi index 06f405ca2c5..d99db7853b5 100644 --- a/arch/arm/dts/rk3066a-u-boot.dtsi +++ b/arch/arm/dts/rk3066a-u-boot.dtsi @@ -3,26 +3,6 @@ #include "rockchip-u-boot.dtsi" #include "rk3xxx-u-boot.dtsi" -&gpio0 { - gpio-ranges = <&pinctrl 0 0 32>; -}; - -&gpio1 { - gpio-ranges = <&pinctrl 0 32 32>; -}; - -&gpio2 { - gpio-ranges = <&pinctrl 0 64 32>; -}; - -&gpio3 { - gpio-ranges = <&pinctrl 0 96 32>; -}; - -&gpio4 { - gpio-ranges = <&pinctrl 0 128 32>; -}; - &gpio6 { status = "disabled"; }; diff --git a/arch/arm/dts/rk3066a.dtsi b/arch/arm/dts/rk3066a.dtsi deleted file mode 100644 index de9915d946f..00000000000 --- a/arch/arm/dts/rk3066a.dtsi +++ /dev/null @@ -1,880 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#include -#include -#include -#include -#include "rk3xxx.dtsi" - -/ { - compatible = "rockchip,rk3066a"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3066-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - operating-points = - /* kHz uV */ - <1416000 1300000>, - <1200000 1175000>, - <1008000 1125000>, - <816000 1125000>, - <600000 1100000>, - <504000 1100000>, - <312000 1075000>; - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x1>; - }; - }; - - display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop0_out>, <&vop1_out>; - }; - - sram: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x10000>; - - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x0 0x50>; - }; - }; - - vop0: vop@1010c000 { - compatible = "rockchip,rk3066-vop"; - reg = <0x1010c000 0x19c>; - interrupts = ; - clocks = <&cru ACLK_LCDC0>, - <&cru DCLK_LCDC0>, - <&cru HCLK_LCDC0>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3066_PD_VIO>; - resets = <&cru SRST_LCDC0_AXI>, - <&cru SRST_LCDC0_AHB>, - <&cru SRST_LCDC0_DCLK>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vop0_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop0_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop0>; - }; - }; - }; - - vop1: vop@1010e000 { - compatible = "rockchip,rk3066-vop"; - reg = <0x1010e000 0x19c>; - interrupts = ; - clocks = <&cru ACLK_LCDC1>, - <&cru DCLK_LCDC1>, - <&cru HCLK_LCDC1>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3066_PD_VIO>; - resets = <&cru SRST_LCDC1_AXI>, - <&cru SRST_LCDC1_AHB>, - <&cru SRST_LCDC1_DCLK>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vop1_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop1_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop1>; - }; - }; - }; - - hdmi: hdmi@10116000 { - compatible = "rockchip,rk3066-hdmi"; - reg = <0x10116000 0x2000>; - interrupts = ; - clocks = <&cru HCLK_HDMI>; - clock-names = "hclk"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; - power-domains = <&power RK3066_PD_VIO>; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in_vop0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vop0_out_hdmi>; - }; - - hdmi_in_vop1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vop1_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - i2s0: i2s@10118000 { - compatible = "rockchip,rk3066-i2s"; - reg = <0x10118000 0x2000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac1_s 4>, <&dmac1_s 5>; - dma-names = "tx", "rx"; - rockchip,playback-channels = <8>; - rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1: i2s@1011a000 { - compatible = "rockchip,rk3066-i2s"; - reg = <0x1011a000 0x2000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac1_s 6>, <&dmac1_s 7>; - dma-names = "tx", "rx"; - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2: i2s@1011c000 { - compatible = "rockchip,rk3066-i2s"; - reg = <0x1011c000 0x2000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_bus>; - clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac1_s 9>, <&dmac1_s 10>; - dma-names = "tx", "rx"; - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3066a-cru"; - reg = <0x20000000 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, - <&cru ACLK_CPU>, <&cru HCLK_CPU>, - <&cru PCLK_CPU>, <&cru ACLK_PERI>, - <&cru HCLK_PERI>, <&cru PCLK_PERI>; - assigned-clock-rates = <400000000>, <594000000>, - <300000000>, <150000000>, - <75000000>, <300000000>, - <150000000>, <75000000>; - }; - - timer2: timer@2000e000 { - compatible = "snps,dw-apb-timer"; - reg = <0x2000e000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; - clock-names = "timer", "pclk"; - }; - - efuse: efuse@20010000 { - compatible = "rockchip,rk3066a-efuse"; - reg = <0x20010000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE>; - clock-names = "pclk_efuse"; - - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - timer0: timer@20038000 { - compatible = "snps,dw-apb-timer"; - reg = <0x20038000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; - clock-names = "timer", "pclk"; - }; - - timer1: timer@2003a000 { - compatible = "snps,dw-apb-timer"; - reg = <0x2003a000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; - clock-names = "timer", "pclk"; - }; - - tsadc: tsadc@20060000 { - compatible = "rockchip,rk3066-tsadc"; - reg = <0x20060000 0x100>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "saradc", "apb_pclk"; - interrupts = ; - #io-channel-cells = <1>; - resets = <&cru SRST_TSADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3066a-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio@20034000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20034000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2003e000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003e000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@20084000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20084000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@2000a000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2000a000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO6>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_default: pcfg-pull-default { - bias-pull-pin-default; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - emac { - emac_xfer: emac-xfer { - rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */ - <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */ - <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */ - <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */ - <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */ - <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */ - <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */ - <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */ - }; - - emac_mdio: emac-mdio { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */ - <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */ - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>; - }; - - emmc_rst: emmc-rst { - rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>; - }; - - /* - * The data pins are shared between nandc and emmc and - * not accessible through pinctrl. Also they should've - * been already set correctly by firmware, as - * flash/emmc is the boot-device. - */ - }; - - hdmi { - hdmi_hpd: hdmi-hpd { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; - }; - - hdmii2c_xfer: hdmii2c-xfer { - rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, - <0 RK_PA2 1 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>, - <2 RK_PD5 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>, - <2 RK_PD7 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>, - <3 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>, - <3 RK_PA3 2 &pcfg_pull_none>; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, - <3 RK_PA5 1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_out: pwm0-out { - rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_out: pwm1-out { - rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_out: pwm2-out { - rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_out: pwm3-out { - rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>; - }; - spi1_cs1: spi1-cs1 { - rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, - <1 RK_PA1 1 &pcfg_pull_default>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>, - <1 RK_PA5 1 &pcfg_pull_default>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, - <1 RK_PB1 1 &pcfg_pull_default>; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>, - <3 RK_PD4 1 &pcfg_pull_default>; - }; - - uart3_cts: uart3-cts { - rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>; - }; - - uart3_rts: uart3-rts { - rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>; - }; - }; - - sd0 { - sd0_clk: sd0-clk { - rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>; - }; - - sd0_cmd: sd0-cmd { - rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>; - }; - - sd0_cd: sd0-cd { - rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>; - }; - - sd0_wp: sd0-wp { - rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>; - }; - - sd0_bus1: sd0-bus-width1 { - rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>; - }; - - sd0_bus4: sd0-bus-width4 { - rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>, - <3 RK_PB3 1 &pcfg_pull_default>, - <3 RK_PB4 1 &pcfg_pull_default>, - <3 RK_PB5 1 &pcfg_pull_default>; - }; - }; - - sd1 { - sd1_clk: sd1-clk { - rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>; - }; - - sd1_cmd: sd1-cmd { - rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>; - }; - - sd1_cd: sd1-cd { - rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>; - }; - - sd1_wp: sd1-wp { - rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>; - }; - - sd1_bus1: sd1-bus-width1 { - rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>; - }; - - sd1_bus4: sd1-bus-width4 { - rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>, - <3 RK_PC2 1 &pcfg_pull_default>, - <3 RK_PC3 1 &pcfg_pull_default>, - <3 RK_PC4 1 &pcfg_pull_default>; - }; - }; - - i2s0 { - i2s0_bus: i2s0-bus { - rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>, - <0 RK_PB0 1 &pcfg_pull_default>, - <0 RK_PB1 1 &pcfg_pull_default>, - <0 RK_PB2 1 &pcfg_pull_default>, - <0 RK_PB3 1 &pcfg_pull_default>, - <0 RK_PB4 1 &pcfg_pull_default>, - <0 RK_PB5 1 &pcfg_pull_default>, - <0 RK_PB6 1 &pcfg_pull_default>, - <0 RK_PB7 1 &pcfg_pull_default>; - }; - }; - - i2s1 { - i2s1_bus: i2s1-bus { - rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, - <0 RK_PC1 1 &pcfg_pull_default>, - <0 RK_PC2 1 &pcfg_pull_default>, - <0 RK_PC3 1 &pcfg_pull_default>, - <0 RK_PC4 1 &pcfg_pull_default>, - <0 RK_PC5 1 &pcfg_pull_default>; - }; - }; - - i2s2 { - i2s2_bus: i2s2-bus { - rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>, - <0 RK_PD1 1 &pcfg_pull_default>, - <0 RK_PD2 1 &pcfg_pull_default>, - <0 RK_PD3 1 &pcfg_pull_default>, - <0 RK_PD4 1 &pcfg_pull_default>, - <0 RK_PD5 1 &pcfg_pull_default>; - }; - }; - }; -}; - -&gpu { - compatible = "rockchip,rk3066-mali", "arm,mali-400"; - interrupts = , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3"; - power-domains = <&power RK3066_PD_GPU>; -}; - -&grf { - compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd"; - - usbphy: usbphy { - compatible = "rockchip,rk3066a-usb-phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@17c { - reg = <0x17c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - #phy-cells = <0>; - }; - - usbphy1: usb-phy@188 { - reg = <0x188>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - #phy-cells = <0>; - }; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; -}; - -&mmc0 { - clock-frequency = <50000000>; - dmas = <&dmac2 1>; - dma-names = "rx-tx"; - max-frequency = <50000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; -}; - -&mmc1 { - dmas = <&dmac2 3>; - dma-names = "rx-tx"; - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; -}; - -&emmc { - dmas = <&dmac2 4>; - dma-names = "rx-tx"; -}; - -&pmu { - power: power-controller { - compatible = "rockchip,rk3066-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3066_PD_VIO { - reg = ; - clocks = <&cru ACLK_LCDC0>, - <&cru ACLK_LCDC1>, - <&cru DCLK_LCDC0>, - <&cru DCLK_LCDC1>, - <&cru HCLK_LCDC0>, - <&cru HCLK_LCDC1>, - <&cru SCLK_CIF1>, - <&cru ACLK_CIF1>, - <&cru HCLK_CIF1>, - <&cru SCLK_CIF0>, - <&cru ACLK_CIF0>, - <&cru HCLK_CIF0>, - <&cru HCLK_HDMI>, - <&cru ACLK_IPP>, - <&cru HCLK_IPP>, - <&cru ACLK_RGA>, - <&cru HCLK_RGA>; - pm_qos = <&qos_lcdc0>, - <&qos_lcdc1>, - <&qos_cif0>, - <&qos_cif1>, - <&qos_ipp>, - <&qos_rga>; - #power-domain-cells = <0>; - }; - - power-domain@RK3066_PD_VIDEO { - reg = ; - clocks = <&cru ACLK_VDPU>, - <&cru ACLK_VEPU>, - <&cru HCLK_VDPU>, - <&cru HCLK_VEPU>; - pm_qos = <&qos_vpu>; - #power-domain-cells = <0>; - }; - - power-domain@RK3066_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - #power-domain-cells = <0>; - }; - }; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_out>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_out>; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_out>; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_out>; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; -}; - -&uart0 { - compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; - dmas = <&dmac1_s 0>, <&dmac1_s 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; -}; - -&uart1 { - compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; - dmas = <&dmac1_s 2>, <&dmac1_s 3>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; -}; - -&uart2 { - compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; - dmas = <&dmac2 6>, <&dmac2 7>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; -}; - -&uart3 { - compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; - dmas = <&dmac2 8>, <&dmac2 9>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; -}; - -&vpu { - power-domains = <&power RK3066_PD_VIDEO>; -}; - -&wdt { - compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; -}; - -&emac { - compatible = "rockchip,rk3066-emac"; -}; diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts deleted file mode 100644 index 118deacd38c..00000000000 --- a/arch/arm/dts/rk3188-radxarock.dts +++ /dev/null @@ -1,389 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2013 Heiko Stuebner - */ - -/dts-v1/; -#include -#include "rk3188.dtsi" - -/ { - model = "Radxa Rock"; - compatible = "radxa,rock", "rockchip,rk3188"; - - aliases { - mmc0 = &mmc0; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - key-power { - gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "GPIO Key Power"; - linux,input-type = <1>; - wakeup-source; - debounce-interval = <100>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - green_led: led-0 { - label = "rock:green:user1"; - gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - blue_led: led-1 { - label = "rock:blue:user2"; - gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - sleep_led: led-2 { - label = "rock:red:power"; - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - - simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ - cpu { sound-dai = <&spdif>; }; - codec { sound-dai = <&spdif_out>; }; - }; - }; - - spdif_out: spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_recv_pin>; - }; - - vcc_otg: usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "otg-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sd0: sdmmc-regulator { - compatible = "regulator-fixed"; - regulator-name = "sdmmc-supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwr>; - startup-delay-us = <100000>; - vin-supply = <&vcc_io>; - }; - - vcc_host: usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "host-pwr"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; -}; - -&emac { - phy = <&phy0>; - phy-supply = <&vcc_rmii>; - pinctrl-names = "default"; - pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio3>; - interrupts = ; - }; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&gpu { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - #clock-cells = <0>; - clock-output-names = "xin32k"; - }; - - act8846: act8846@5a { - compatible = "active-semi,act8846"; - reg = <0x5a>; - status = "okay"; - system-power-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&act8846_dvs0_ctl>; - - vp1-supply = <&vsys>; - vp2-supply = <&vsys>; - vp3-supply = <&vsys>; - vp4-supply = <&vsys>; - inl1-supply = <&vcc_io>; - inl2-supply = <&vsys>; - inl3-supply = <&vsys>; - - regulators { - vcc_ddr: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd_log: REG2 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vdd_arm: REG3 { - regulator-name = "VDD_ARM"; - regulator-min-microvolt = <875000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vcc_io: REG4 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_10: REG5 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vdd_hdmi: REG6 { - regulator-name = "VDD_HDMI"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vcc18: REG7 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcca_33: REG8 { - regulator-name = "VCCA_33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_rmii: REG9 { - regulator-name = "VCC_RMII"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vccio_wl: REG10 { - regulator-name = "VCCIO_WL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vcc_18: REG11 { - regulator-name = "VCC18_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc28: REG12 { - regulator-name = "VCC_28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - }; - }; -}; - -&mmc0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - vmmc-supply = <&vcc_sd0>; - - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm3 { - status = "okay"; -}; - -&pinctrl { - pcfg_output_low: pcfg-output-low { - output-low; - }; - - act8846 { - act8846_dvs0_ctl: act8846-dvs0-ctl { - rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lan8720a { - phy_int: phy-int { - rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - ir-receiver { - ir_recv_pin: ir-recv-pin { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sd0 { - sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&spdif { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; - -&usb_host { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; - -&wdt { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3188-u-boot.dtsi b/arch/arm/dts/rk3188-u-boot.dtsi index 176f9e65c26..8f2849dda24 100644 --- a/arch/arm/dts/rk3188-u-boot.dtsi +++ b/arch/arm/dts/rk3188-u-boot.dtsi @@ -6,25 +6,8 @@ #include "rockchip-u-boot.dtsi" #include "rk3xxx-u-boot.dtsi" -&global_timer { - status = "okay"; -}; - &gpio0 { compatible = "rockchip,gpio-bank"; - gpio-ranges = <&pinctrl 0 0 32>; -}; - -&gpio1 { - gpio-ranges = <&pinctrl 0 32 32>; -}; - -&gpio2 { - gpio-ranges = <&pinctrl 0 64 32>; -}; - -&gpio3 { - gpio-ranges = <&pinctrl 0 96 32>; }; &pmu { diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi deleted file mode 100644 index 44b54af0bbf..00000000000 --- a/arch/arm/dts/rk3188.dtsi +++ /dev/null @@ -1,815 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#include -#include -#include -#include -#include "rk3xxx.dtsi" - -/ { - compatible = "rockchip,rk3188"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3066-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x0>; - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - operating-points-v2 = <&cpu0_opp_table>; - resets = <&cru SRST_CORE0>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x1>; - operating-points-v2 = <&cpu0_opp_table>; - resets = <&cru SRST_CORE1>; - }; - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x2>; - operating-points-v2 = <&cpu0_opp_table>; - resets = <&cru SRST_CORE2>; - }; - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - next-level-cache = <&L2>; - reg = <0x3>; - operating-points-v2 = <&cpu0_opp_table>; - resets = <&cru SRST_CORE3>; - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - opp-microvolt = <875000>; - clock-latency-ns = <40000>; - }; - opp-504000000 { - opp-hz = /bits/ 64 <504000000>; - opp-microvolt = <925000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <950000>; - opp-suspend; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <975000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1075000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1150000>; - }; - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1250000>; - }; - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1350000>; - }; - }; - - display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop0_out>, <&vop1_out>; - }; - - sram: sram@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x8000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x8000>; - - smp-sram@0 { - compatible = "rockchip,rk3066-smp-sram"; - reg = <0x0 0x50>; - }; - }; - - vop0: vop@1010c000 { - compatible = "rockchip,rk3188-vop"; - reg = <0x1010c000 0x1000>; - interrupts = ; - clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3188_PD_VIO>; - resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vop0_out: port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - vop1: vop@1010e000 { - compatible = "rockchip,rk3188-vop"; - reg = <0x1010e000 0x1000>; - interrupts = ; - clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK3188_PD_VIO>; - resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; - reset-names = "axi", "ahb", "dclk"; - status = "disabled"; - - vop1_out: port { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - timer3: timer@2000e000 { - compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; - reg = <0x2000e000 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>; - clock-names = "pclk", "timer"; - }; - - timer6: timer@200380a0 { - compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; - reg = <0x200380a0 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>; - clock-names = "pclk", "timer"; - }; - - i2s0: i2s@1011a000 { - compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; - reg = <0x1011a000 0x2000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac1_s 6>, <&dmac1_s 7>; - dma-names = "tx", "rx"; - rockchip,playback-channels = <2>; - rockchip,capture-channels = <2>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - spdif: sound@1011e000 { - compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; - reg = <0x1011e000 0x2000>; - #sound-dai-cells = <0>; - clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; - clock-names = "mclk", "hclk"; - dmas = <&dmac1_s 8>; - dma-names = "tx"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx>; - status = "disabled"; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - efuse: efuse@20010000 { - compatible = "rockchip,rk3188-efuse"; - reg = <0x20010000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE>; - clock-names = "pclk_efuse"; - - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3188-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio@2000a000 { - compatible = "rockchip,rk3188-gpio-bank0"; - reg = <0x2000a000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2003e000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003e000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>; - }; - - emmc_rst: emmc-rst { - rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>; - }; - - /* - * The data pins are shared between nandc and emmc and - * not accessible through pinctrl. Also they should've - * been already set correctly by firmware, as - * flash/emmc is the boot-device. - */ - }; - - emac { - emac_xfer: emac-xfer { - rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */ - <3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */ - <3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */ - <3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */ - <3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */ - <3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */ - <3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */ - <3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */ - }; - - emac_mdio: emac-mdio { - rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, - <3 RK_PD1 2 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, - <1 RK_PD1 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>, - <1 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>, - <1 RK_PD5 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>, - <3 RK_PB7 2 &pcfg_pull_none>; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>, - <1 RK_PD7 1 &pcfg_pull_none>; - }; - }; - - lcdc1 { - lcdc1_dclk: lcdc1-dclk { - rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>; - }; - - lcdc1_den: lcdc1-den { - rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>; - }; - - lcdc1_hsync: lcdc1-hsync { - rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; - }; - - lcdc1_vsync: lcdc1-vsync { - rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; - }; - - lcdc1_rgb24: lcdc1-rgb24 { - rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, - <2 RK_PA1 1 &pcfg_pull_none>, - <2 RK_PA2 1 &pcfg_pull_none>, - <2 RK_PA3 1 &pcfg_pull_none>, - <2 RK_PA4 1 &pcfg_pull_none>, - <2 RK_PA5 1 &pcfg_pull_none>, - <2 RK_PA6 1 &pcfg_pull_none>, - <2 RK_PA7 1 &pcfg_pull_none>, - <2 RK_PB0 1 &pcfg_pull_none>, - <2 RK_PB1 1 &pcfg_pull_none>, - <2 RK_PB2 1 &pcfg_pull_none>, - <2 RK_PB3 1 &pcfg_pull_none>, - <2 RK_PB4 1 &pcfg_pull_none>, - <2 RK_PB5 1 &pcfg_pull_none>, - <2 RK_PB6 1 &pcfg_pull_none>, - <2 RK_PB7 1 &pcfg_pull_none>, - <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PC1 1 &pcfg_pull_none>, - <2 RK_PC2 1 &pcfg_pull_none>, - <2 RK_PC3 1 &pcfg_pull_none>, - <2 RK_PC4 1 &pcfg_pull_none>, - <2 RK_PC5 1 &pcfg_pull_none>, - <2 RK_PC6 1 &pcfg_pull_none>, - <2 RK_PC7 1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_out: pwm0-out { - rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_out: pwm1-out { - rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_out: pwm2-out { - rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_out: pwm3-out { - rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>; - }; - spi1_cs1: spi1-cs1 { - rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>, - <1 RK_PA1 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>, - <1 RK_PA5 1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>, - <1 RK_PB1 1 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - uart3 { - uart3_xfer: uart3-xfer { - rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>, - <1 RK_PB3 1 &pcfg_pull_none>; - }; - - uart3_cts: uart3-cts { - rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>; - }; - - uart3_rts: uart3-rts { - rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>; - }; - }; - - sd0 { - sd0_clk: sd0-clk { - rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>; - }; - - sd0_cmd: sd0-cmd { - rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; - }; - - sd0_cd: sd0-cd { - rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>; - }; - - sd0_wp: sd0-wp { - rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>; - }; - - sd0_pwr: sd0-pwr { - rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; - }; - - sd0_bus1: sd0-bus-width1 { - rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; - }; - - sd0_bus4: sd0-bus-width4 { - rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, - <3 RK_PA5 1 &pcfg_pull_none>, - <3 RK_PA6 1 &pcfg_pull_none>, - <3 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - sd1 { - sd1_clk: sd1-clk { - rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; - }; - - sd1_cmd: sd1-cmd { - rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>; - }; - - sd1_cd: sd1-cd { - rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>; - }; - - sd1_wp: sd1-wp { - rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>; - }; - - sd1_bus1: sd1-bus-width1 { - rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>; - }; - - sd1_bus4: sd1-bus-width4 { - rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>, - <3 RK_PC2 1 &pcfg_pull_none>, - <3 RK_PC3 1 &pcfg_pull_none>, - <3 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - i2s0 { - i2s0_bus: i2s0-bus { - rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, - <1 RK_PC1 1 &pcfg_pull_none>, - <1 RK_PC2 1 &pcfg_pull_none>, - <1 RK_PC3 1 &pcfg_pull_none>, - <1 RK_PC4 1 &pcfg_pull_none>, - <1 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - spdif { - spdif_tx: spdif-tx { - rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>; - }; - }; - }; -}; - -&emac { - compatible = "rockchip,rk3188-emac"; -}; - -&global_timer { - interrupts = ; -}; - -&local_timer { - interrupts = ; -}; - -&gpu { - compatible = "rockchip,rk3188-mali", "arm,mali-400"; - interrupts = , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3"; - power-domains = <&power RK3188_PD_GPU>; -}; - -&grf { - compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd"; - - io_domains: io-domains { - compatible = "rockchip,rk3188-io-voltage-domain"; - status = "disabled"; - }; - - usbphy: usbphy { - compatible = "rockchip,rk3188-usb-phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@10c { - reg = <0x10c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - #phy-cells = <0>; - }; - - usbphy1: usb-phy@11c { - reg = <0x11c>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - #phy-cells = <0>; - }; - }; -}; - -&i2c0 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; -}; - -&i2c1 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; -}; - -&i2c2 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; -}; - -&i2c3 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; -}; - -&i2c4 { - compatible = "rockchip,rk3188-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; -}; - -&pmu { - power: power-controller { - compatible = "rockchip,rk3188-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3188_PD_VIO { - reg = ; - clocks = <&cru ACLK_LCDC0>, - <&cru ACLK_LCDC1>, - <&cru DCLK_LCDC0>, - <&cru DCLK_LCDC1>, - <&cru HCLK_LCDC0>, - <&cru HCLK_LCDC1>, - <&cru SCLK_CIF0>, - <&cru ACLK_CIF0>, - <&cru HCLK_CIF0>, - <&cru ACLK_IPP>, - <&cru HCLK_IPP>, - <&cru ACLK_RGA>, - <&cru HCLK_RGA>; - pm_qos = <&qos_lcdc0>, - <&qos_lcdc1>, - <&qos_cif0>, - <&qos_ipp>, - <&qos_rga>; - #power-domain-cells = <0>; - }; - - power-domain@RK3188_PD_VIDEO { - reg = ; - clocks = <&cru ACLK_VDPU>, - <&cru ACLK_VEPU>, - <&cru HCLK_VDPU>, - <&cru HCLK_VEPU>; - pm_qos = <&qos_vpu>; - #power-domain-cells = <0>; - }; - - power-domain@RK3188_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - #power-domain-cells = <0>; - }; - }; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_out>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_out>; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_out>; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_out>; -}; - -&spi0 { - compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; -}; - -&spi1 { - compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; -}; - -&uart0 { - compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; -}; - -&uart1 { - compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; -}; - -&uart2 { - compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; -}; - -&uart3 { - compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_xfer>; -}; - -&vpu { - compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu"; - power-domains = <&power RK3188_PD_VIDEO>; -}; - -&wdt { - compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; -}; diff --git a/arch/arm/dts/rk3xxx.dtsi b/arch/arm/dts/rk3xxx.dtsi deleted file mode 100644 index cb4e42ede56..00000000000 --- a/arch/arm/dts/rk3xxx.dtsi +++ /dev/null @@ -1,488 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - aliases { - ethernet0 = &emac; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - spi0 = &spi0; - spi1 = &spi1; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - clock-output-names = "xin24m"; - }; - - gpu: gpu@10090000 { - compatible = "arm,mali-400"; - reg = <0x10090000 0x10000>; - clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; - clock-names = "bus", "core"; - assigned-clocks = <&cru ACLK_GPU>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_GPU>; - status = "disabled"; - }; - - vpu: video-codec@10104000 { - compatible = "rockchip,rk3066-vpu"; - reg = <0x10104000 0x800>; - interrupts = , - ; - interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>, - <&cru ACLK_VEPU>, <&cru HCLK_VEPU>; - clock-names = "aclk_vdpu", "hclk_vdpu", - "aclk_vepu", "hclk_vepu"; - }; - - L2: cache-controller@10138000 { - compatible = "arm,pl310-cache"; - reg = <0x10138000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - scu@1013c000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1013c000 0x100>; - }; - - global_timer: global-timer@1013c200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x1013c200 0x20>; - interrupts = ; - clocks = <&cru CORE_PERI>; - status = "disabled"; - /* The clock source and the sched_clock provided by the arm_global_timer - * on Rockchip rk3066a/rk3188 are quite unstable because their rates - * depend on the CPU frequency. - * Keep the arm_global_timer disabled in order to have the - * DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default. - */ - }; - - local_timer: local-timer@1013c600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1013c600 0x20>; - interrupts = ; - clocks = <&cru CORE_PERI>; - }; - - gic: interrupt-controller@1013d000 { - compatible = "arm,cortex-a9-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x1013d000 0x1000>, - <0x1013c100 0x0100>; - }; - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - status = "disabled"; - }; - - uart1: serial@10126000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10126000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - status = "disabled"; - }; - - qos_gpu: qos@1012d000 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012d000 0x20>; - }; - - qos_vpu: qos@1012e000 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012e000 0x20>; - }; - - qos_lcdc0: qos@1012f000 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f000 0x20>; - }; - - qos_cif0: qos@1012f080 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f080 0x20>; - }; - - qos_ipp: qos@1012f100 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f100 0x20>; - }; - - qos_lcdc1: qos@1012f180 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f180 0x20>; - }; - - qos_cif1: qos@1012f200 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f200 0x20>; - }; - - qos_rga: qos@1012f280 { - compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f280 0x20>; - }; - - usb_otg: usb@10180000 { - compatible = "rockchip,rk3066-usb", "snps,dwc2"; - reg = <0x10180000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG0>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <275>; - g-tx-fifo-size = <256 128 128 64 64 32>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host: usb@101c0000 { - compatible = "snps,dwc2"; - reg = <0x101c0000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG1>; - clock-names = "otg"; - dr_mode = "host"; - phys = <&usbphy1>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - emac: ethernet@10204000 { - compatible = "snps,arc-emac"; - reg = <0x10204000 0x3c>; - interrupts = ; - - rockchip,grf = <&grf>; - - clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; - clock-names = "hclk", "macref"; - max-speed = <100>; - phy-mode = "rmii"; - - status = "disabled"; - }; - - mmc0: mmc@10214000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10214000 0x1000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; - dmas = <&dmac2 1>; - dma-names = "rx-tx"; - fifo-depth = <256>; - resets = <&cru SRST_SDMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - mmc1: mmc@10218000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x10218000 0x1000>; - interrupts = ; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; - clock-names = "biu", "ciu"; - dmas = <&dmac2 3>; - dma-names = "rx-tx"; - fifo-depth = <256>; - resets = <&cru SRST_SDIO>; - reset-names = "reset"; - status = "disabled"; - }; - - emmc: mmc@1021c000 { - compatible = "rockchip,rk2928-dw-mshc"; - reg = <0x1021c000 0x1000>; - interrupts = ; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; - clock-names = "biu", "ciu"; - dmas = <&dmac2 4>; - dma-names = "rx-tx"; - fifo-depth = <256>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - nfc: nand-controller@10500000 { - compatible = "rockchip,rk2928-nfc"; - reg = <0x10500000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_NANDC0>; - clock-names = "ahb"; - status = "disabled"; - }; - - pmu: pmu@20004000 { - compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; - reg = <0x20004000 0x100>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x40>; - mode-normal = ; - mode-recovery = ; - mode-bootloader = ; - mode-loader = ; - }; - }; - - grf: grf@20008000 { - compatible = "syscon", "simple-mfd"; - reg = <0x20008000 0x200>; - }; - - dmac1_s: dma-controller@20018000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20018000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMA1>; - clock-names = "apb_pclk"; - }; - - dmac1_ns: dma-controller@2001c000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x2001c000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMA1>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - i2c0: i2c@2002d000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2002d000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - - status = "disabled"; - }; - - i2c1: i2c@2002f000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2002f000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C1>; - clock-names = "i2c"; - - status = "disabled"; - }; - - pwm0: pwm@20030000 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20030000 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM01>; - status = "disabled"; - }; - - pwm1: pwm@20030010 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20030010 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM01>; - status = "disabled"; - }; - - wdt: watchdog@2004c000 { - compatible = "snps,dw-wdt"; - reg = <0x2004c000 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = ; - status = "disabled"; - }; - - pwm2: pwm@20050020 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050020 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM23>; - status = "disabled"; - }; - - pwm3: pwm@20050030 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050030 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM23>; - status = "disabled"; - }; - - i2c2: i2c@20056000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x20056000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C2>; - clock-names = "i2c"; - - status = "disabled"; - }; - - i2c3: i2c@2005a000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2005a000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C3>; - clock-names = "i2c"; - - status = "disabled"; - }; - - i2c4: i2c@2005e000 { - compatible = "rockchip,rk3066-i2c"; - reg = <0x2005e000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - rockchip,grf = <&grf>; - - clocks = <&cru PCLK_I2C4>; - clock-names = "i2c"; - - status = "disabled"; - }; - - uart2: serial@20064000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20064000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - status = "disabled"; - }; - - uart3: serial@20068000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20068000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - status = "disabled"; - }; - - saradc: saradc@2006c000 { - compatible = "rockchip,saradc"; - reg = <0x2006c000 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - spi0: spi@20070000 { - compatible = "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - reg = <0x20070000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmac2 10>, <&dmac2 11>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi1: spi@20074000 { - compatible = "rockchip,rk3066-spi"; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - interrupts = ; - reg = <0x20074000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmac2 12>, <&dmac2 13>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - dmac2: dma-controller@20078000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20078000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMA2>; - clock-names = "apb_pclk"; - }; -}; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 269c219a6f8..4d3157b2edd 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -48,6 +48,7 @@ config ROCKCHIP_RK3066 select TPL select TPL_ROCKCHIP_BACK_TO_BROM select TPL_ROCKCHIP_EARLYRETURN_TO_BROM + imply OF_UPSTREAM imply ROCKCHIP_COMMON_BOARD imply SPL_ROCKCHIP_COMMON_BOARD imply SPL_SERIAL @@ -84,6 +85,7 @@ config ROCKCHIP_RK3188 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM select SPL_ROCKCHIP_BACK_TO_BROM select BOARD_LATE_INIT + imply OF_UPSTREAM imply ROCKCHIP_COMMON_BOARD imply SPL_ROCKCHIP_COMMON_BOARD help diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig index 12a37054b4d..e47d0b594f3 100644 --- a/configs/mk808_defconfig +++ b/configs/mk808_defconfig @@ -14,7 +14,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x78000000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_SIZE=0x8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3066a-mk808" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3066a-mk808" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3066=y # CONFIG_ROCKCHIP_STIMER is not set @@ -35,7 +35,7 @@ CONFIG_SPL_PAYLOAD="u-boot.bin" CONFIG_DEBUG_UART=y CONFIG_SD_BOOT=y CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3066a-mk808.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3066a-mk808.dtb" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/rock_defconfig b/configs/rock_defconfig index d7f11310cba..9c05bf45146 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -11,7 +11,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3188-radxarock" CONFIG_ROCKCHIP_RK3188=y # CONFIG_ROCKCHIP_STIMER is not set CONFIG_TARGET_ROCK=y @@ -25,7 +25,7 @@ CONFIG_DEBUG_UART_BASE=0x20064000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3188-radxarock.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3188-radxarock.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x7800 -- cgit v1.3.1 From 3681fe06ab8259a50918e11f88d97d5b0a6f3e3a Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sun, 8 Dec 2024 18:46:31 +0100 Subject: rockchip: rk3066a/rk3188: use includes from dts/upstream The clock and power DT includes for rk3066a and rk3188 are now available in the dts/upstream directory, so remove the ones that are now redundant. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- include/dt-bindings/clock/rk3066a-cru.h | 31 --- include/dt-bindings/clock/rk3188-cru-common.h | 261 -------------------------- include/dt-bindings/clock/rk3188-cru.h | 47 ----- include/dt-bindings/power/rk3066-power.h | 22 --- include/dt-bindings/power/rk3188-power.h | 24 --- 5 files changed, 385 deletions(-) delete mode 100644 include/dt-bindings/clock/rk3066a-cru.h delete mode 100644 include/dt-bindings/clock/rk3188-cru-common.h delete mode 100644 include/dt-bindings/clock/rk3188-cru.h delete mode 100644 include/dt-bindings/power/rk3066-power.h delete mode 100644 include/dt-bindings/power/rk3188-power.h diff --git a/include/dt-bindings/clock/rk3066a-cru.h b/include/dt-bindings/clock/rk3066a-cru.h deleted file mode 100644 index 014eec58668..00000000000 --- a/include/dt-bindings/clock/rk3066a-cru.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H - -#include - -/* soft-reset indices */ -#define SRST_SRST1 0 -#define SRST_SRST2 1 - -#define SRST_L2MEM 18 -#define SRST_I2S0 23 -#define SRST_I2S1 24 -#define SRST_I2S2 25 -#define SRST_TIMER2 29 - -#define SRST_GPIO4 36 -#define SRST_GPIO6 38 - -#define SRST_TSADC 92 - -#define SRST_HDMI 96 -#define SRST_HDMI_APB 97 -#define SRST_CIF1 111 - -#endif diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h deleted file mode 100644 index afad90680fc..00000000000 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ /dev/null @@ -1,261 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H - -/* core clocks from */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define CORE_PERI 5 -#define CORE_L2C 6 -#define ARMCLK 7 - -/* sclk gates (special clocks) */ -#define SCLK_UART0 64 -#define SCLK_UART1 65 -#define SCLK_UART2 66 -#define SCLK_UART3 67 -#define SCLK_MAC 68 -#define SCLK_SPI0 69 -#define SCLK_SPI1 70 -#define SCLK_SARADC 71 -#define SCLK_SDMMC 72 -#define SCLK_SDIO 73 -#define SCLK_EMMC 74 -#define SCLK_I2S0 75 -#define SCLK_I2S1 76 -#define SCLK_I2S2 77 -#define SCLK_SPDIF 78 -#define SCLK_CIF0 79 -#define SCLK_CIF1 80 -#define SCLK_OTGPHY0 81 -#define SCLK_OTGPHY1 82 -#define SCLK_HSADC 83 -#define SCLK_TIMER0 84 -#define SCLK_TIMER1 85 -#define SCLK_TIMER2 86 -#define SCLK_TIMER3 87 -#define SCLK_TIMER4 88 -#define SCLK_TIMER5 89 -#define SCLK_TIMER6 90 -#define SCLK_JTAG 91 -#define SCLK_SMC 92 -#define SCLK_TSADC 93 - -#define DCLK_LCDC0 190 -#define DCLK_LCDC1 191 - -/* aclk gates */ -#define ACLK_DMA1 192 -#define ACLK_DMA2 193 -#define ACLK_GPS 194 -#define ACLK_LCDC0 195 -#define ACLK_LCDC1 196 -#define ACLK_GPU 197 -#define ACLK_SMC 198 -#define ACLK_CIF1 199 -#define ACLK_IPP 200 -#define ACLK_RGA 201 -#define ACLK_CIF0 202 -#define ACLK_CPU 203 -#define ACLK_PERI 204 -#define ACLK_VEPU 205 -#define ACLK_VDPU 206 - -/* pclk gates */ -#define PCLK_GRF 320 -#define PCLK_PMU 321 -#define PCLK_TIMER0 322 -#define PCLK_TIMER1 323 -#define PCLK_TIMER2 324 -#define PCLK_TIMER3 325 -#define PCLK_PWM01 326 -#define PCLK_PWM23 327 -#define PCLK_SPI0 328 -#define PCLK_SPI1 329 -#define PCLK_SARADC 330 -#define PCLK_WDT 331 -#define PCLK_UART0 332 -#define PCLK_UART1 333 -#define PCLK_UART2 334 -#define PCLK_UART3 335 -#define PCLK_I2C0 336 -#define PCLK_I2C1 337 -#define PCLK_I2C2 338 -#define PCLK_I2C3 339 -#define PCLK_I2C4 340 -#define PCLK_GPIO0 341 -#define PCLK_GPIO1 342 -#define PCLK_GPIO2 343 -#define PCLK_GPIO3 344 -#define PCLK_GPIO4 345 -#define PCLK_GPIO6 346 -#define PCLK_EFUSE 347 -#define PCLK_TZPC 348 -#define PCLK_TSADC 349 -#define PCLK_CPU 350 -#define PCLK_PERI 351 -#define PCLK_DDRUPCTL 352 -#define PCLK_PUBL 353 - -/* hclk gates */ -#define HCLK_SDMMC 448 -#define HCLK_SDIO 449 -#define HCLK_EMMC 450 -#define HCLK_OTG0 451 -#define HCLK_EMAC 452 -#define HCLK_SPDIF 453 -#define HCLK_I2S0 454 -#define HCLK_I2S1 455 -#define HCLK_I2S2 456 -#define HCLK_OTG1 457 -#define HCLK_HSIC 458 -#define HCLK_HSADC 459 -#define HCLK_PIDF 460 -#define HCLK_LCDC0 461 -#define HCLK_LCDC1 462 -#define HCLK_ROM 463 -#define HCLK_CIF0 464 -#define HCLK_IPP 465 -#define HCLK_RGA 466 -#define HCLK_NANDC0 467 -#define HCLK_CPU 468 -#define HCLK_PERI 469 -#define HCLK_CIF1 470 -#define HCLK_VEPU 471 -#define HCLK_VDPU 472 -#define HCLK_HDMI 473 - -#define CLK_NR_CLKS (HCLK_HDMI + 1) - -/* soft-reset indices */ -#define SRST_MCORE 2 -#define SRST_CORE0 3 -#define SRST_CORE1 4 -#define SRST_MCORE_DBG 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE0_WDT 12 -#define SRST_CORE1_WDT 13 -#define SRST_STRC_SYS 14 -#define SRST_L2C 15 - -#define SRST_CPU_AHB 17 -#define SRST_AHB2APB 19 -#define SRST_DMA1 20 -#define SRST_INTMEM 21 -#define SRST_ROM 22 -#define SRST_SPDIF 26 -#define SRST_TIMER0 27 -#define SRST_TIMER1 28 -#define SRST_EFUSE 30 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 - -#define SRST_UART0 39 -#define SRST_UART1 40 -#define SRST_UART2 41 -#define SRST_UART3 42 -#define SRST_I2C0 43 -#define SRST_I2C1 44 -#define SRST_I2C2 45 -#define SRST_I2C3 46 -#define SRST_I2C4 47 - -#define SRST_PWM0 48 -#define SRST_PWM1 49 -#define SRST_DAP_PO 50 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_TPIU_ATB 53 -#define SRST_PMU_APB 54 -#define SRST_GRF 55 -#define SRST_PMU 56 -#define SRST_PERI_AXI 57 -#define SRST_PERI_AHB 58 -#define SRST_PERI_APB 59 -#define SRST_PERI_NIU 60 -#define SRST_CPU_PERI 61 -#define SRST_EMEM_PERI 62 -#define SRST_USB_PERI 63 - -#define SRST_DMA2 64 -#define SRST_SMC 65 -#define SRST_MAC 66 -#define SRST_NANC0 68 -#define SRST_USBOTG0 69 -#define SRST_USBPHY0 70 -#define SRST_OTGC0 71 -#define SRST_USBOTG1 72 -#define SRST_USBPHY1 73 -#define SRST_OTGC1 74 -#define SRST_HSADC 76 -#define SRST_PIDFILTER 77 -#define SRST_DDR_MSCH 79 - -#define SRST_TZPC 80 -#define SRST_SDMMC 81 -#define SRST_SDIO 82 -#define SRST_EMMC 83 -#define SRST_SPI0 84 -#define SRST_SPI1 85 -#define SRST_WDT 86 -#define SRST_SARADC 87 -#define SRST_DDRPHY 88 -#define SRST_DDRPHY_APB 89 -#define SRST_DDRCTL 90 -#define SRST_DDRCTL_APB 91 -#define SRST_DDRPUB 93 - -#define SRST_VIO0_AXI 98 -#define SRST_VIO0_AHB 99 -#define SRST_LCDC0_AXI 100 -#define SRST_LCDC0_AHB 101 -#define SRST_LCDC0_DCLK 102 -#define SRST_LCDC1_AXI 103 -#define SRST_LCDC1_AHB 104 -#define SRST_LCDC1_DCLK 105 -#define SRST_IPP_AXI 106 -#define SRST_IPP_AHB 107 -#define SRST_RGA_AXI 108 -#define SRST_RGA_AHB 109 -#define SRST_CIF0 110 - -#define SRST_VCODEC_AXI 112 -#define SRST_VCODEC_AHB 113 -#define SRST_VIO1_AXI 114 -#define SRST_VCODEC_CPU 115 -#define SRST_VCODEC_NIU 116 -#define SRST_GPU 120 -#define SRST_GPU_NIU 122 -#define SRST_TFUN_ATB 125 -#define SRST_TFUN_APB 126 -#define SRST_CTI4_APB 127 - -#define SRST_TPIU_APB 128 -#define SRST_TRACE 129 -#define SRST_CORE_DBG 130 -#define SRST_DBG_APB 131 -#define SRST_CTI0 132 -#define SRST_CTI0_APB 133 -#define SRST_CTI1 134 -#define SRST_CTI1_APB 135 -#define SRST_PTM_CORE0 136 -#define SRST_PTM_CORE1 137 -#define SRST_PTM0 138 -#define SRST_PTM0_ATB 139 -#define SRST_PTM1 140 -#define SRST_PTM1_ATB 141 -#define SRST_CTM 142 -#define SRST_TS 143 - -#endif diff --git a/include/dt-bindings/clock/rk3188-cru.h b/include/dt-bindings/clock/rk3188-cru.h deleted file mode 100644 index 1da306e1788..00000000000 --- a/include/dt-bindings/clock/rk3188-cru.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H - -#include - -/* soft-reset indices */ -#define SRST_PTM_CORE2 0 -#define SRST_PTM_CORE3 1 -#define SRST_CORE2 5 -#define SRST_CORE3 6 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 - -#define SRST_TIMER2 16 -#define SRST_TIMER4 23 -#define SRST_I2S0 24 -#define SRST_TIMER5 25 -#define SRST_TIMER3 29 -#define SRST_TIMER6 31 - -#define SRST_PTM3 36 -#define SRST_PTM3_ATB 37 - -#define SRST_GPS 67 -#define SRST_HSICPHY 75 -#define SRST_TIMER 78 - -#define SRST_PTM2 92 -#define SRST_CORE2_WDT 94 -#define SRST_CORE3_WDT 95 - -#define SRST_PTM2_ATB 111 - -#define SRST_HSIC 117 -#define SRST_CTI2 118 -#define SRST_CTI2_APB 119 -#define SRST_GPU_BRIDGE 121 -#define SRST_CTI3 123 -#define SRST_CTI3_APB 124 - -#endif diff --git a/include/dt-bindings/power/rk3066-power.h b/include/dt-bindings/power/rk3066-power.h deleted file mode 100644 index acf9f310ac5..00000000000 --- a/include/dt-bindings/power/rk3066-power.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3066_POWER_H__ -#define __DT_BINDINGS_POWER_RK3066_POWER_H__ - -/* VD_CORE */ -#define RK3066_PD_A9_0 0 -#define RK3066_PD_A9_1 1 -#define RK3066_PD_DBG 4 -#define RK3066_PD_SCU 5 - -/* VD_LOGIC */ -#define RK3066_PD_VIDEO 6 -#define RK3066_PD_VIO 7 -#define RK3066_PD_GPU 8 -#define RK3066_PD_PERI 9 -#define RK3066_PD_CPU 10 -#define RK3066_PD_ALIVE 11 - -/* VD_PMU */ -#define RK3066_PD_RTC 12 - -#endif diff --git a/include/dt-bindings/power/rk3188-power.h b/include/dt-bindings/power/rk3188-power.h deleted file mode 100644 index 93d23dfba33..00000000000 --- a/include/dt-bindings/power/rk3188-power.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3188_POWER_H__ -#define __DT_BINDINGS_POWER_RK3188_POWER_H__ - -/* VD_CORE */ -#define RK3188_PD_A9_0 0 -#define RK3188_PD_A9_1 1 -#define RK3188_PD_A9_2 2 -#define RK3188_PD_A9_3 3 -#define RK3188_PD_DBG 4 -#define RK3188_PD_SCU 5 - -/* VD_LOGIC */ -#define RK3188_PD_VIDEO 6 -#define RK3188_PD_VIO 7 -#define RK3188_PD_GPU 8 -#define RK3188_PD_PERI 9 -#define RK3188_PD_CPU 10 -#define RK3188_PD_ALIVE 11 - -/* VD_PMU */ -#define RK3188_PD_RTC 12 - -#endif -- cgit v1.3.1 From 532e30e709d9608e1ba2ae767cd2833a112165f9 Mon Sep 17 00:00:00 2001 From: Daniel Semkowicz Date: Tue, 26 Nov 2024 09:27:15 +0100 Subject: board: theobroma-systems: Update TF-A setup steps for RK3588 boards ddrbin_tool interface has been changed. Additional chip_name argument is now required to modify ddr binary file. Update documentation to be consistent with the new interface. Update BL31 and ROCKCHIP_TPL file paths to match current version of binaries available in the rkbin repository. Signed-off-by: Daniel Semkowicz Acked-by: Quentin Schulz Reviewed-by: Quentin Schulz --- doc/board/theobroma-systems/jaguar_rk3588.rst | 6 +++--- doc/board/theobroma-systems/tiger_rk3588.rst | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/doc/board/theobroma-systems/jaguar_rk3588.rst b/doc/board/theobroma-systems/jaguar_rk3588.rst index db15f945d3b..cba4fd066ab 100644 --- a/doc/board/theobroma-systems/jaguar_rk3588.rst +++ b/doc/board/theobroma-systems/jaguar_rk3588.rst @@ -40,10 +40,10 @@ Get the TF-A and DDR init (TPL) binaries git clone https://github.com/rockchip-linux/rkbin cd rkbin export RKBIN=$(pwd) - export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.38.elf - export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.11.bin + export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.47.elf + export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt - ./tools/ddrbin_tool tools/ddrbin_param.txt "$ROCKCHIP_TPL" + ./tools/ddrbin_tool rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL" ./tools/boot_merger RKBOOT/RK3588MINIALL.ini export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin diff --git a/doc/board/theobroma-systems/tiger_rk3588.rst b/doc/board/theobroma-systems/tiger_rk3588.rst index 46112544c82..4586b8d8b5a 100644 --- a/doc/board/theobroma-systems/tiger_rk3588.rst +++ b/doc/board/theobroma-systems/tiger_rk3588.rst @@ -47,11 +47,11 @@ Get the TF-A and DDR init (TPL) binaries git clone https://github.com/rockchip-linux/rkbin cd rkbin export RKBIN=$(pwd) - export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.38.elf - export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.11.bin + export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.47.elf + export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt sed -i 's/^uart iomux=.*$/uart iomux=2/' tools/ddrbin_param.txt - ./tools/ddrbin_tool tools/ddrbin_param.txt "$ROCKCHIP_TPL" + ./tools/ddrbin_tool rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL" ./tools/boot_merger RKBOOT/RK3588MINIALL.ini export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin -- cgit v1.3.1 From ddb3d7e635c41bd46dd386efdb0e9c21e94ba99e Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Mon, 2 Dec 2024 23:40:18 +0000 Subject: rockchip: rk3399: expand space for decompressed kernel fix following error by using same ENV_MEM_LAYOUT_SETTINGS with rk35xx: U-Boot 2025.01-rc3-00001-g1527c7dcdb01 (Dec 02 2024 - 22:57:18 +0000) : Retrieving file: /boot/extlinux/../nixos/dhqjsnprmzjxncil3m0g9l09a479crn3-linux-6.12.1-Image Retrieving file: /boot/extlinux/../nixos/6fq8fmmab31yxdwcs7zw44p78fq9fy1s-initrd-linux-6.12.1-initrd append: init=/nix/store/yjbxgzf1vkwbw6ab738bf4kxazhyypa1-nixos-system-rock-5b-25.05.20241201.ac35b10/init console=ttyS2,1500000n8 console=ttyAMA0,115200n8 console=tty0 loglevel=7 Retrieving file: /boot/extlinux/../nixos/dhqjsnprmzjxncil3m0g9l09a479crn3-linux-6.12.1-dtbs/rockchip/rk3399-rock-4se.dtb Moving Image from 0x2080000 to 0x2200000, end=0x60d0000 ERROR: RD image overlaps OS image (OS=2200000..60d0000) Boot failed (err=-14) $ ls -lh boot/nixos/ total 84M -r--r--r-- 1 root root 24M Jan 1 1970 6fq8fmmab31yxdwcs7zw44p78fq9fy1s-initrd-linux-6.12.1-initrd -r--r--r-- 1 root root 62M Jan 1 1970 dhqjsnprmzjxncil3m0g9l09a479crn3-linux-6.12.1-Image dr-xr-xr-x 36 root root 4.0K Jan 1 1970 dhqjsnprmzjxncil3m0g9l09a479crn3-linux-6.12.1-dtbs similar problem was fixed for rk35xx by: commit 69b73877f02c ("rockchip: rk35xx: expand space for decompressed kernel") Signed-off-by: FUKAUMI Naoki Reviewed-by: Kever Yang --- include/configs/rk3399_common.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index c5bcd7dc5e8..76f40e7cd5f 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -20,16 +20,16 @@ #endif #define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x00500000\0" \ + "scriptaddr=0x00c00000\0" \ "script_offset_f=0xffe000\0" \ "script_size_f=0x2000\0" \ - "pxefile_addr_r=0x00600000\0" \ - "fdt_addr_r=0x01e00000\0" \ - "fdtoverlay_addr_r=0x01f00000\0" \ - "kernel_addr_r=0x02080000\0" \ - "ramdisk_addr_r=0x06000000\0" \ - "kernel_comp_addr_r=0x08000000\0" \ - "kernel_comp_size=0x2000000\0" + "pxefile_addr_r=0x00e00000\0" \ + "kernel_addr_r=0x02000000\0" \ + "kernel_comp_addr_r=0x0a000000\0" \ + "fdt_addr_r=0x12000000\0" \ + "fdtoverlay_addr_r=0x12100000\0" \ + "ramdisk_addr_r=0x12180000\0" \ + "kernel_comp_size=0x8000000\0" #define CFG_EXTRA_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ -- cgit v1.3.1 From 4576e65a5d6b10fd207c3a44061676ce0220d794 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 23:57:08 +0000 Subject: rockchip: rk3399: Fix TPL build of bob and kevin Building chromebook_bob/kevin with TPL=y ends with a linking error: arch/arm/mach-rockchip/rk3399/rk3399.o: in function `board_debug_uart_init': arch/arm/mach-rockchip/rk3399/rk3399.c:148:(.text.board_debug_uart_init+0x34): undefined reference to `spl_gpio_output' arch/arm/mach-rockchip/rk3399/rk3399.c:148:(.text.board_debug_uart_init+0x34): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `spl_gpio_output' make[2]: *** [scripts/Makefile.xpl:542: tpl/u-boot-tpl] Error 1 make[1]: *** [Makefile:2134: tpl/u-boot-tpl] Error 2 make: *** [Makefile:568: __build_one_by_one] Error 2 Change to only use spl_gpio functions in SPL to fix this. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 0c28241c603..ba89079b1e7 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -136,7 +136,7 @@ void board_debug_uart_init(void) struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; - if (IS_ENABLED(CONFIG_XPL_BUILD) && + if (IS_ENABLED(CONFIG_SPL_BUILD) && (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) || IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) { rk_setreg(&grf->io_vsel, 1 << 0); -- cgit v1.3.1 From 01048aa9f8d669869a4dff8399e2238dd39b0531 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 23:57:09 +0000 Subject: rockchip: rk3399-gru: Use SYS_SPI_U_BOOT_OFFS value in offset prop Use the offset configured with SYS_SPI_U_BOOT_OFFS Kconfig option instead of a hardcoded 0x40000 for the FIT payload offset. This has no intended impact as SYS_SPI_U_BOOT_OFFS=0x40000. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-gru-u-boot.dtsi | 2 +- arch/arm/dts/rk3399-u-boot.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi index 6bdc892bd91..2505d9b01b8 100644 --- a/arch/arm/dts/rk3399-gru-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -11,7 +11,7 @@ }; config { - u-boot,spl-payload-offset = <0x40000>; + u-boot,spl-payload-offset = ; }; }; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 2bec139d833..81a3c6fc972 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -43,7 +43,7 @@ }; }; u-boot-img { - offset = <0x40000>; + offset = ; }; u-boot { offset = <0x300000>; -- cgit v1.3.1 From afbc34c79ceea585a7c8d97b5011ba377b7b0a63 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 23:57:10 +0000 Subject: rockchip: rk3399-gru: Move SPI flash payload offset for bob and kevin The BootROM on RK3399 only read the first 2 KB of each 4 KB page from SPI flash. With current FIT payload offset of 0x40000 this limits the supported TPL+SPL size to only 128 KB. Change to use 0xE0000 as FIT payload offset, similar to other RK3399 boards, to allow a maximum size for TPL of 192 KB and SPL of 256 KB. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- configs/chromebook_bob_defconfig | 2 +- configs/chromebook_kevin_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index decac2e1935..69a07ef7e01 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -44,7 +44,7 @@ CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 5bbea6c42a8..d689eeaf278 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -45,7 +45,7 @@ CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y -- cgit v1.3.1 From 656892f102b47207e1eef738dbdb55137e8bc856 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 23:57:11 +0000 Subject: rockchip: rk3399-gru: Fix include of TPL in u-boot.rom image The chromebook specific u-boot.rom image does not include TPL when building with TPL=y or ROCKCHIP_EXTERNAL_TPL=y. Fix this by adding rockchip-tpl and u-boot-tpl nodes to the mkimage node for the u-boot.rom binman image. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-u-boot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 81a3c6fc972..bd7527dde22 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -39,6 +39,14 @@ mkimage { args = "-n rk3399 -T rkspi"; + multiple-data-files; +#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL + rockchip-tpl { + }; +#elif defined(CONFIG_TPL) + u-boot-tpl { + }; +#endif u-boot-spl { }; }; -- cgit v1.3.1 From 49f8131e5594ac76e52f4580e4b1858a5c3b2c3e Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 23:57:12 +0000 Subject: rockchip: rk3399-gru: Use TPL with common bss and stack addresses Migrate to use TPL, common bss, stack and malloc heap size and addresses to unify memory use in TPL, SPL and pre-reloc with other RK3399 boards. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang (Disable TPL_BLOBLIST) Signed-off-by: Kever Yang --- configs/chromebook_bob_defconfig | 14 ++------------ configs/chromebook_kevin_defconfig | 14 ++------------ 2 files changed, 4 insertions(+), 24 deletions(-) diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 69a07ef7e01..b16bc3a9100 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -3,26 +3,15 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-gru-bob" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 # CONFIG_SPL_MMC is not set -CONFIG_SPL_STACK=0xff8effff -CONFIG_SPL_TEXT_BASE=0xff8c2000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_SF_DEFAULT_BUS=1 CONFIG_DEBUG_UART_BASE=0xff1a0000 @@ -36,16 +25,17 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y +# CONFIG_TPL_BLOBLIST is not set CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 CONFIG_SPL_MAX_SIZE=0x1e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index d689eeaf278..966422a5d92 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -3,27 +3,16 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_TEXT_BASE=0x00200000 CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-gru-kevin" CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_BOOT_MODE_REG=0 -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 # CONFIG_SPL_MMC is not set CONFIG_TARGET_CHROMEBOOK_KEVIN=y -CONFIG_SPL_STACK=0xff8effff -CONFIG_SPL_TEXT_BASE=0xff8c2000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xff8e0000 -CONFIG_SPL_BSS_MAX_SIZE=0x10000 -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_SF_DEFAULT_BUS=1 CONFIG_DEBUG_UART_BASE=0xff1a0000 @@ -37,16 +26,17 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_R=y CONFIG_BLOBLIST=y +# CONFIG_TPL_BLOBLIST is not set CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 CONFIG_SPL_MAX_SIZE=0x1e000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y -- cgit v1.3.1 From 55c9e3e5b212440178f389c55096000d9469afae Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 23:57:13 +0000 Subject: rockchip: rk3399-gru: Include binman generated FIT in u-boot.rom image The u-boot.rom image contain u-boot.img FIT instead of the FIT generated by binman for the u-boot-rockchip.bin image. Change to include the binman generated FIT for the u-boot.rom image. This change result in TF-A being included and the use sha256 instead of crc32 checksum in the u-boot.rom FIT. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-u-boot.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index bd7527dde22..70f35b6c197 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -50,7 +50,9 @@ u-boot-spl { }; }; - u-boot-img { + fit { + type = "blob"; + filename = "u-boot.itb"; offset = ; }; u-boot { -- cgit v1.3.1 From 51b3e463631346a74fec64ab95f603af984738ac Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 23:57:14 +0000 Subject: rockchip: rk3399: Drop common Kconfig options already implied The last two RK3399 boards, chromebook bob and kevin, have now migraded to use common bss and stack addresses. Cleanup and remove Kconfig options no longer needed in rk3399/Kconfig when all boards now use common bss and stack addresses. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3399/Kconfig | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 04a84e2f6a0..500cfcd87af 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -146,15 +146,6 @@ config SYS_SOC config ROCKCHIP_COMMON_STACK_ADDR default y -config SYS_MALLOC_F_LEN - default 0x4000 if !SPL_SHARES_INIT_SP_ADDR - -config SPL_LIBCOMMON_SUPPORT - default y - -config SPL_LIBGENERIC_SUPPORT - default y - config TPL_LDSCRIPT default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" @@ -164,9 +155,6 @@ config TPL_STACK config TPL_TEXT_BASE default 0xff8c2000 -config SPL_STACK_R_ADDR - default 0x04000000 if !SPL_SHARES_INIT_SP_ADDR - if BOOTCOUNT_LIMIT config BOOTCOUNT_BOOTLIMIT -- cgit v1.3.1 From 1c34c315e7b6fb921a6a63d562ef9cd45aad7d31 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 23:57:15 +0000 Subject: rockchip: rk3399-gru: Remove unused nodes from xPL control FDT The eMMC PHY and SPI flash is not used in all xPL phases. Change to no longer include emmc_phy and spi_flash in all xPL phases. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-gru-u-boot.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi index 2505d9b01b8..5f44327736d 100644 --- a/arch/arm/dts/rk3399-gru-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -29,6 +29,11 @@ rockchip,panel = <&edp_panel>; }; +&emmc_phy { + /delete-property/ bootph-pre-ram; +}; + + &pp1800_audio { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -80,7 +85,8 @@ &spi1 { spi_flash: flash@0 { - bootph-all; + bootph-pre-ram; + bootph-some-ram; }; }; -- cgit v1.3.1 From 0187fcc3c02fe7e8e4511d48d8ad03bdff168b7b Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 23:57:16 +0000 Subject: rockchip: rk3399-gru: Enable dcache and signature validation in SPL With TPL being used to init DRAM, SPL being used to load FIT and the adjusted FIT payload offset it is now possible to increase the size limit of SPL to 256 KB and enable uses of dcache and FIT signature validation. Drop SPL_SYS_DCACHE_OFF=y to enable use of dcache in SPL. Drop SPL_FIT_SIGNATURE=n to enable signature validation of FIT in SPL. Change SPL_MAX_SIZE to 256 KB now that payload offset has moved in SPI and TF-A may be loaded to 0x40000 in DRAM. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- configs/chromebook_bob_defconfig | 4 +--- configs/chromebook_kevin_defconfig | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index b16bc3a9100..03fd1174c74 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y @@ -19,7 +18,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y -# CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -28,7 +26,7 @@ CONFIG_BLOBLIST=y # CONFIG_TPL_BLOBLIST is not set CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 -CONFIG_SPL_MAX_SIZE=0x1e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 966422a5d92..32b0b003420 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -1,6 +1,5 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y @@ -20,7 +19,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_DEBUG_UART=y -# CONFIG_SPL_FIT_SIGNATURE is not set CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -29,7 +27,7 @@ CONFIG_BLOBLIST=y # CONFIG_TPL_BLOBLIST is not set CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_BLOBLIST_SIZE=0x1000 -CONFIG_SPL_MAX_SIZE=0x1e000 +CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_HANDOFF=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -- cgit v1.3.1 From 4636b19afb58f8d139172873a80c189524e717b6 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 23:57:17 +0000 Subject: rockchip: rk3399-gru: Use SDMA mode to read from eMMC Enable use of SDMA mode when reading from eMMC to speed up boot. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- configs/chromebook_bob_defconfig | 1 + configs/chromebook_kevin_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 03fd1174c74..18dc80fd0a1 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -64,6 +64,7 @@ CONFIG_MMC_PWRSEQ=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 32b0b003420..e233670dca0 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -65,6 +65,7 @@ CONFIG_MMC_PWRSEQ=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y -- cgit v1.3.1 From 54fddb9d884a35ca4572dbe13fa167f6436afc6d Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 23:57:18 +0000 Subject: rockchip: rk3399-gru: Include pinctrl and regulators in SPL Add bootph props and enable related Kconfig options to include vital regulators in SPL. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-gru-u-boot.dtsi | 19 +++++++++++++++++++ configs/chromebook_bob_defconfig | 3 ++- configs/chromebook_kevin_defconfig | 3 ++- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi index 5f44327736d..5517176aa4a 100644 --- a/arch/arm/dts/rk3399-gru-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -33,12 +33,31 @@ /delete-property/ bootph-pre-ram; }; +&gpio0 { + bootph-pre-ram; +}; + +&pp1500_ap_io { + bootph-pre-ram; +}; &pp1800_audio { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; +&pp1500_en { + bootph-pre-ram; +}; + +&pp3000 { + bootph-pre-ram; +}; + +&pp3000_en { + bootph-pre-ram; +}; + &ppvar_bigcpu_pwm { regulator-init-microvolt = <900000>; }; diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 18dc80fd0a1..5e67de3bd85 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -48,7 +48,7 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_LOG=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -74,6 +74,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_CROS_EC=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index e233670dca0..0be6e4462dd 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -49,7 +49,7 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_LOG=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ROCKCHIP_GPIO=y @@ -75,6 +75,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_CROS_EC=y -- cgit v1.3.1 From af518a1dfe637cb4dc486d7a832585e4a48bc970 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 12 Dec 2024 23:57:19 +0000 Subject: rockchip: rk3399: Drop unneeded bob and kevin board specific code The IO-domain driver will configure io_vsel and always-on/boot-on regulators will be enabled based on the board device tree now that required nodes and Kconfig options is enabled for SPL. Remove the bob and kevin board specific code from the common rk3399.c, the IO-domain and regulator driver provide similar functionality. Signed-off-by: Jonas Karlman --- arch/arm/mach-rockchip/rk3399/rk3399.c | 23 +---------------------- 1 file changed, 1 insertion(+), 22 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index ba89079b1e7..1ce43c6f0d4 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -16,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -133,27 +133,6 @@ void board_debug_uart_init(void) GRF_GPIO3B7_SEL_MASK, GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT); #else - struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; - struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; - - if (IS_ENABLED(CONFIG_SPL_BUILD) && - (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) || - IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) { - rk_setreg(&grf->io_vsel, 1 << 0); - - /* - * Let's enable these power rails here, we are already running - * the SPI-Flash-based code. - */ - spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */ - spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), - GPIO_PULL_NORMAL); - - spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */ - spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), - GPIO_PULL_NORMAL); - } - /* Enable early UART2 channel C on the RK3399 */ rk_clrsetreg(&grf->gpio4c_iomux, GRF_GPIO4C3_SEL_MASK, -- cgit v1.3.1 From dc53e48d17b842b7340d255da432cea741e77823 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 6 Jan 2025 18:22:29 +0000 Subject: rockchip: rk3588-nanopc-t6-lts: Add missing board -u-boot.dtsi The commit 7cec3e701940 ("rockchip: rk3588-nanopc-t6: Add support for NanoPC-T6 LTS") added support for the LTS variant of NanoPC T6. However, a board specific -u-boot.dtsi file was never added. Due to the missing -u-boot.dtsi file the LTS fdt included in the FIT is never tagged with bootph props. When ENV_IS_IN_SPI_FLASH is enabled, not enabled in defconfig, the env can successfully load from SPI flash on the non-LTS variant, something that does not work on the LTS variant due to missing bootph-some-ram props in the LTS fdt. Fix this by adding a LTS -u-boot.dtsi file that just include the non-LTS -u-boot.dtsi file. Reported-by: Ricardo Pardini Fixes: 7cec3e701940 ("rockchip: rk3588-nanopc-t6: Add support for NanoPC-T6 LTS") Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-nanopc-t6-lts-u-boot.dtsi | 3 +++ board/friendlyelec/nanopc-t6-rk3588/MAINTAINERS | 3 +-- 2 files changed, 4 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/rk3588-nanopc-t6-lts-u-boot.dtsi diff --git a/arch/arm/dts/rk3588-nanopc-t6-lts-u-boot.dtsi b/arch/arm/dts/rk3588-nanopc-t6-lts-u-boot.dtsi new file mode 100644 index 00000000000..b18f958c8a2 --- /dev/null +++ b/arch/arm/dts/rk3588-nanopc-t6-lts-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-nanopc-t6-u-boot.dtsi" diff --git a/board/friendlyelec/nanopc-t6-rk3588/MAINTAINERS b/board/friendlyelec/nanopc-t6-rk3588/MAINTAINERS index 63ff6fafc8d..27853188e59 100644 --- a/board/friendlyelec/nanopc-t6-rk3588/MAINTAINERS +++ b/board/friendlyelec/nanopc-t6-rk3588/MAINTAINERS @@ -5,5 +5,4 @@ S: Maintained F: board/friendlyelec/nanopc-t6-rk3588 F: include/configs/nanopc-t6-rk3588.h F: configs/nanopc-t6-rk3588_defconfig -F: arch/arm/dts/rk3588-nanopc-t6.dts -F: arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi +F: arch/arm/dts/rk3588-nanopc-t6* -- cgit v1.3.1 From 46e371cd31d29561592a8a297f16c858639b99bf Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 20 Nov 2024 11:19:11 +0100 Subject: clk: rockchip: rk3588: fix mask define for aclk_vop_root The mask for aclk_vop_root is 3-bit wide, not 2-bit wide according to the TRM, so set the mask accordingly. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/cru_rk3588.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h index dad484813fa..afce8a44af3 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h @@ -346,7 +346,7 @@ enum { ACLK_VOP_LOW_ROOT_SEL_100M, ACLK_VOP_LOW_ROOT_SEL_24M, ACLK_VOP_ROOT_SEL_SHIFT = 5, - ACLK_VOP_ROOT_SEL_MASK = 3 << ACLK_VOP_ROOT_SEL_SHIFT, + ACLK_VOP_ROOT_SEL_MASK = 7 << ACLK_VOP_ROOT_SEL_SHIFT, ACLK_VOP_ROOT_SEL_GPLL = 0, ACLK_VOP_ROOT_SEL_CPLL, ACLK_VOP_ROOT_SEL_AUPLL, -- cgit v1.3.1 From c72e37dceb3343b9026d363411a828bd6be6f3a7 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 19 Nov 2024 00:12:19 +0000 Subject: rockchip: rk3399-rock-pi-4: Fix Synchronous Abort After the commit 788cf33315c7 ("efi: add a helper to generate dynamic UUIDs") update_info.num_images must match number of valid update images. On Rock Pi 4 following Synchronous Abort can be observed due to fw_name being NULL: Scanning global bootmeth 'efi_mgr': "Synchronous Abort" handler, esr 0x96000010, far 0x0 elr: 0000000000200e28 lr : 000000000028adb8 (reloc) elr: 00000000f3efbe28 lr : 00000000f3f85db8 x0 : 0000000000000000 x1 : ffffffffffffffff x2 : 0000000000000000 x3 : 000000000000000e x4 : 0000000000000000 x5 : 00000000f1ef0d78 x6 : 00000000f3fb3b90 x7 : 0000000000000044 x8 : 0000000000000010 x9 : 0000000000000031 x10: 00000000f0ea3fff x11: 00000000f1f29e00 x12: 0000000000000002 x13: fffffffffffff000 x14: 00000000f1f29e00 x15: 0000000000000018 x16: 00000000f3f44f7c x17: 0000000000000000 x18: 00000000f1ef2de0 x19: 00000000f0ea3040 x20: 00000000f3ff53d8 x21: 00000000f3fd0498 x22: 0000000000000000 x23: 00000000f1edb960 x24: 00000000f1edb95f x25: 00000000f1edb990 x26: 00000000f1edb964 x27: 00000000f1edb998 x28: 00000000f1edc1ec x29: 00000000f1edb820 Code: aa0003e2 d2800000 eb01001f 54000060 (78607843) Resetting CPU ... resetting ... Fix this by setting update_info.num_images to 0 when no valid update images is added to update_info. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Tested-by: FUKAUMI Naoki --- board/radxa/rockpi4-rk3399/rockpi4-rk3399.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/radxa/rockpi4-rk3399/rockpi4-rk3399.c b/board/radxa/rockpi4-rk3399/rockpi4-rk3399.c index fd827467b30..856b434df36 100644 --- a/board/radxa/rockpi4-rk3399/rockpi4-rk3399.c +++ b/board/radxa/rockpi4-rk3399/rockpi4-rk3399.c @@ -52,6 +52,8 @@ void rockchip_capsule_update_board_setup(void) fw_images[0].fw_name = u"ROCKPI4C-IDBLOADER"; fw_images[1].fw_name = u"ROCKPI4C-UBOOT"; + } else { + update_info.num_images = 0; } } #endif /* CONFIG_EFI_HAVE_CAPSULE_SUPPORT && CONFIG_EFI_PARTITION */ -- cgit v1.3.1 From 1a520a9b20f9ca3dda9adbcd1cf5e5723c73eaef Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 10 Nov 2024 00:56:15 +0000 Subject: rockchip: rk356x: Implement checkboard() to print SoC variant Implement checkboard() to print current SoC model used by a board, e.g. one of: SoC: RK3566 SoC: RK3566T SoC: RK3568 SoC: RK3568B2 SoC: RK3568J when U-Boot proper is running. U-Boot 2025.01-rc1 (Nov 10 2024 - 00:39:37 +0000) Model: Generic RK3566/RK3568 SoC: RK3568J DRAM: 8 GiB (effective 7.7 GiB) Information about the SoC model and variant is read from OTP. Also update rk356x-u-boot.dtsi to include OTP in U-Boot pre-reloc phase, where checkboard() is called. Signed-off-by: Jonas Karlman Tested-by: FUKAUMI Naoki Reviewed-by: Kever Yang --- arch/arm/dts/rk356x-u-boot.dtsi | 4 +++ arch/arm/mach-rockchip/rk3568/rk3568.c | 61 ++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index 0a0943b462a..24a976cf7e2 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -87,6 +87,10 @@ bootph-all; }; +&otp { + bootph-some-ram; +}; + &pcfg_pull_none { bootph-all; }; diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index c9a32287e92..c2b96902d2d 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -3,7 +3,10 @@ * (C) Copyright 2021 Rockchip Electronics Co., Ltd */ +#define LOG_CATEGORY LOGC_ARCH + #include +#include #include #include #include @@ -139,3 +142,61 @@ int arch_cpu_init(void) #endif return 0; } + +#define RK3568_OTP_CPU_CODE_OFFSET 0x02 +#define RK3568_OTP_SPECIFICATION_OFFSET 0x07 +#define RK3568_OTP_PERFORMANCE_OFFSET 0x22 + +int checkboard(void) +{ + u8 cpu_code[2], specification, package, performance; + struct udevice *dev; + char suffix[3]; + int ret; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return 0; + } + + /* cpu-code: SoC model, e.g. 0x35 0x66 or 0x35 0x68 */ + ret = misc_read(dev, RK3568_OTP_CPU_CODE_OFFSET, cpu_code, 2); + if (ret < 0) { + log_debug("Could not read cpu-code, ret=%d\n", ret); + return 0; + } + + /* specification: SoC variant, e.g. 0x2 for RK3568B2 and 0xA for RK3568J */ + ret = misc_read(dev, RK3568_OTP_SPECIFICATION_OFFSET, &specification, 1); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + /* package: likely SoC variant revision, 0x2 for RK3568B2 */ + package = specification >> 5; + specification &= 0x1f; + + /* performance: used to identify RK3566T SoC variant */ + ret = misc_read(dev, RK3568_OTP_PERFORMANCE_OFFSET, &performance, 1); + if (ret < 0) { + log_debug("Could not read performance, ret=%d\n", ret); + return 0; + } + if (performance & 0x0f) + specification = 0x14; /* T-variant */ + + /* for RK3568J i.e. '@' + 0xA = 'J' */ + suffix[0] = specification > 1 ? '@' + specification : '\0'; + /* for RK3568B2 i.e. '0' + 0x2 = '2' */ + suffix[1] = package > 1 ? '0' + package : '\0'; + suffix[2] = '\0'; + + printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix); + + return 0; +} -- cgit v1.3.1 From 1c2ffcd5e622031fa1c05335d0db839de14bf0e9 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 10 Nov 2024 00:56:16 +0000 Subject: rockchip: rk3588: Implement checkboard() to print SoC variant Implement checkboard() to print current SoC model used by a board, e.g. one of: SoC: RK3582 SoC: RK3588 SoC: RK3588J SoC: RK3588S SoC: RK3588S2 when U-Boot proper is running. U-Boot 2025.01-rc1 (Nov 10 2024 - 00:31:29 +0000) Model: Generic RK3588S/RK3588 SoC: RK3588S2 DRAM: 8 GiB Information about the SoC model and variant is read from OTP. Also update rk3588s-u-boot.dtsi to include OTP in U-Boot pre-reloc phase, where checkboard() is called. Signed-off-by: Jonas Karlman Tested-by: FUKAUMI Naoki Reviewed-by: Kever Yang --- arch/arm/dts/rk3588s-u-boot.dtsi | 4 +++ arch/arm/mach-rockchip/rk3588/rk3588.c | 52 ++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index 09d8b311cec..8880d162b11 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -69,6 +69,10 @@ bootph-all; }; +&otp { + bootph-some-ram; +}; + &pcfg_pull_down { bootph-all; }; diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index e2dac2a5b80..c1dce3ee370 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -4,6 +4,10 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ +#define LOG_CATEGORY LOGC_ARCH + +#include +#include #include #include #include @@ -178,3 +182,51 @@ int arch_cpu_init(void) return 0; } #endif + +#define RK3588_OTP_CPU_CODE_OFFSET 0x02 +#define RK3588_OTP_SPECIFICATION_OFFSET 0x06 + +int checkboard(void) +{ + u8 cpu_code[2], specification, package; + struct udevice *dev; + char suffix[3]; + int ret; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return 0; + } + + /* cpu-code: SoC model, e.g. 0x35 0x82 or 0x35 0x88 */ + ret = misc_read(dev, RK3588_OTP_CPU_CODE_OFFSET, cpu_code, 2); + if (ret < 0) { + log_debug("Could not read cpu-code, ret=%d\n", ret); + return 0; + } + + /* specification: SoC variant, e.g. 0xA for RK3588J and 0x13 for RK3588S */ + ret = misc_read(dev, RK3588_OTP_SPECIFICATION_OFFSET, &specification, 1); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + /* package: likely SoC variant revision, 0x2 for RK3588S2 */ + package = specification >> 5; + specification &= 0x1f; + + /* for RK3588J i.e. '@' + 0xA = 'J' */ + suffix[0] = specification > 1 ? '@' + specification : '\0'; + /* for RK3588S2 i.e. '0' + 0x2 = '2' */ + suffix[1] = package > 1 ? '0' + package : '\0'; + suffix[2] = '\0'; + + printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix); + + return 0; +} -- cgit v1.3.1 From 39389cfb3dfe10bc549b0719688285629b11c25d Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 10 Nov 2024 00:56:17 +0000 Subject: rockchip: rk3308: Implement checkboard() to print SoC variant Implement checkboard() to print current SoC variant used by a board, e.g. one of: SoC: RK3308 SoC: RK3308B SoC: RK3308B-S when U-Boot proper is running. U-Boot 2025.01-rc1 (Nov 02 2024 - 20:26:25 +0000) Model: Radxa ROCK Pi S SoC: RK3308B DRAM: 512 MiB (effective 510 MiB) Information about the SoC variant is read from GRF. Signed-off-by: Jonas Karlman --- arch/arm/mach-rockchip/rk3308/rk3308.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index c6b1a35f47e..03d97e1d746 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -216,3 +216,19 @@ int arch_cpu_init(void) return 0; } #endif + +#define RK3308_GRF_CHIP_ID 0xFF000800 + +int checkboard(void) +{ + u32 chip_id = readl(RK3308_GRF_CHIP_ID); + + if (chip_id == 0x3308) + printf("SoC: RK3308B\n"); + else if (chip_id == 0x3308c) + printf("SoC: RK3308B-S\n"); + else + printf("SoC: RK3308\n"); + + return 0; +} -- cgit v1.3.1