From d8ee42f113474c81f2d25a98e6cbcd60cf5bdfd5 Mon Sep 17 00:00:00 2001 From: Lukas Schmid Date: Sun, 26 Oct 2025 12:41:17 +0100 Subject: sunxi: extend R528/T113-s3/D1(s) DRAM initialisation The T113-s4 SoC is using the same die as the T113-s3, but comes with 256MiB of co-packaged DRAM. Besides the doubled size, the DRAM chip seems to be connected slightly differently, which requires to use a different pin remapping. Extend the DRAM initialisation code to add support for the T113-S4 aka T113M4020DC0 by checking the SoC's CHIPID, which is stored in the first word of the SID efuses. Signed-off-by: Lukas Schmid Tested-by: John Watts Reviewed-by: John Watts Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- drivers/ram/sunxi/dram_sun20i_d1.c | 10 ++++++++++ drivers/ram/sunxi/dram_sun20i_d1.h | 11 +++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/ram/sunxi/dram_sun20i_d1.c b/drivers/ram/sunxi/dram_sun20i_d1.c index a1794032f3b..79cf0a51e47 100644 --- a/drivers/ram/sunxi/dram_sun20i_d1.c +++ b/drivers/ram/sunxi/dram_sun20i_d1.c @@ -54,6 +54,11 @@ static void sid_read_ldoB_cal(const dram_para_t *para) clrsetbits_le32(0x3000150, 0xff00, reg << 8); } +static uint32_t sid_read_soc_chipid(void) +{ + return readl(SUNXI_SID_BASE + 0x00) & 0xffff; +} + static void dram_voltage_set(const dram_para_t *para) { int vol; @@ -663,6 +668,11 @@ static void mctl_phy_ac_remapping(const dram_para_t *para, fuse = (readl(SUNXI_SID_BASE + 0x28) & 0xf00) >> 8; debug("DDR efuse: 0x%x\n", fuse); + debug("SoC Chip ID: 0x%08x\n", sid_read_soc_chipid()); + + /* No remapping needed on T113-s4 with 256MB co-packaged DRAM */ + if (sid_read_soc_chipid() == SUNXI_CHIPID_T113M4020DC0) + return; if (para->dram_type == SUNXI_DRAM_TYPE_DDR2) { if (fuse == 15) diff --git a/drivers/ram/sunxi/dram_sun20i_d1.h b/drivers/ram/sunxi/dram_sun20i_d1.h index 91383f6cf10..83ae7eb36cd 100644 --- a/drivers/ram/sunxi/dram_sun20i_d1.h +++ b/drivers/ram/sunxi/dram_sun20i_d1.h @@ -19,6 +19,17 @@ enum sunxi_dram_type { SUNXI_DRAM_TYPE_LPDDR3 = 7, }; +/* + * Chip-IDs taken from + * https://github.com/ua1arn/hftrx/blob/25d8cb9e4cfe1d7d0e4a2f641025c88a9ec5e758/inc/clocks.h#L250 + */ +enum sunxi_soc_chipid { + SUNXI_CHIPID_F133A = 0x5C00, + SUNXI_CHIPID_D1S = 0x5E00, + SUNXI_CHIPID_T113S3 = 0x6000, + SUNXI_CHIPID_T113M4020DC0 = 0x7200, +}; + /* * This structure contains a mixture of fixed configuration settings, * variables that are used at runtime to communicate settings between -- cgit v1.3.1 From c47b636737366d9bc017b915ca6fcbcce8706e6e Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 22 Oct 2025 00:53:34 +0100 Subject: sunxi: dram: detect non-power-of-2 sized DRAM chips Some boards feature an "odd" DRAM size, where the total RAM is 1.5GB or 3GB. Our existing DRAM size detection routines can only detect power-of-2 sized configuration, and on those boards the DRAM size is overestimated, so this typically breaks the boot quite early. There doesn't seem to be an easy explicit way to detect those odd-sized chips, but we can test whether the later part of the memory behaves like memory, by verifying that a written pattern can be read back. Experiments show that there is no aliasing effect here, as all locations in the unimplemented range always return some fixed pattern, and cannot be changed. Also so far all those boards use a factor of 3 of some lower power-of-2 number, or 3/4th of some higher number. The size detection routine discovers the higher number, so we can check for some memory cells beyond 75% of the detected size to be legit. Add a routine the inverts all bits at a given location in memory, and reads that back to prove that the new value was stored. Then test the memory cell at exactly 3/4th of the detected size, and cap the size of the memory to 75% when this test fails. For good measure also make sure that memory just below the assumed memory end really works. This enables boards which ship with such odd memory sizes. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- arch/arm/include/asm/arch-sunxi/dram.h | 1 + arch/arm/mach-sunxi/dram_dw_helpers.c | 22 +++++++++++++++++++++- arch/arm/mach-sunxi/dram_helpers.c | 12 ++++++++++++ 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h index 0eccb1e6c28..59e2e980bfa 100644 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -45,5 +45,6 @@ unsigned long sunxi_dram_init(void); void mctl_await_completion(u32 *reg, u32 mask, u32 val); bool mctl_mem_matches(u32 offset); bool mctl_mem_matches_base(u32 offset, ulong base); +bool mctl_check_memory(phys_addr_t addr); #endif /* _SUNXI_DRAM_H */ diff --git a/arch/arm/mach-sunxi/dram_dw_helpers.c b/arch/arm/mach-sunxi/dram_dw_helpers.c index 24767354935..d2af2d57fde 100644 --- a/arch/arm/mach-sunxi/dram_dw_helpers.c +++ b/arch/arm/mach-sunxi/dram_dw_helpers.c @@ -143,8 +143,28 @@ void mctl_auto_detect_dram_size(const struct dram_para *para, unsigned long mctl_calc_size(const struct dram_config *config) { + unsigned long size; u8 width = config->bus_full_width ? 4 : 2; /* 8 banks */ - return (1ULL << (config->cols + config->rows + 3)) * width * config->ranks; + size = (1ULL << (config->cols + config->rows + 3)) * width * + config->ranks; + + /* + * There are boards with non-power-of-2 sized DRAM chips, like 1.5GB + * or 3GB. They are detected as the larger power-of-2 (2GB and 4GB), + * so test the last quarter for being able to store values. + */ + if (!mctl_check_memory(CFG_SYS_SDRAM_BASE + size / 4 * 3)) { + if (mctl_check_memory(CFG_SYS_SDRAM_BASE + size / 4 * 3 - 64)) { + size = (size / 4) * 3; + debug("capping memory at %ld MB\n", size >> 20); + } else { + printf("DRAM test failure at address 0x%lx\n", + CFG_SYS_SDRAM_BASE + size / 4 * 3 - 64); + return 0; + } + } + + return size; } diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c index 83dbe4ca98f..376b7d14f86 100644 --- a/arch/arm/mach-sunxi/dram_helpers.c +++ b/arch/arm/mach-sunxi/dram_helpers.c @@ -62,3 +62,15 @@ bool mctl_mem_matches(u32 offset) return mctl_mem_matches_base(offset, CFG_SYS_SDRAM_BASE); } #endif + +bool mctl_check_memory(phys_addr_t addr) +{ + uint32_t orig, val; + + orig = readl(addr); + writel(~orig, addr); + val = readl(addr); + writel(orig, addr); + + return ~orig == val; +} -- cgit v1.3.1 From eb7390797d262eaab589a4d4e71fbb0c156bd61c Mon Sep 17 00:00:00 2001 From: Bohdan Chubuk Date: Sun, 23 Nov 2025 22:43:46 +0200 Subject: sunxi: avoid double vendor prefix when CONFIG_OF_UPSTREAM is enabled When CONFIG_OF_UPSTREAM is enabled, the device tree name provided by SPL already includes the vendor directory (e.g., "allwinner/board-name"). The existing logic in misc_init_r() unconditionally prepends "allwinner/" for ARM64 builds, resulting in an incorrect path like "allwinner/allwinner/board-name.dtb". This patch modifies the logic to only prepend the vendor prefix if CONFIG_OF_UPSTREAM is NOT enabled. This ensures compatibility with both legacy builds and the new upstream devicetree structure. Signed-off-by: Bohdan Chubuk Reviewed-by: Andre Przywara --- board/sunxi/board.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 2929bc17f08..e9e3fb9a571 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -834,9 +834,12 @@ int misc_init_r(void) /* Set fdtfile to match the FIT configuration chosen in SPL. */ spl_dt_name = get_spl_dt_name(); if (spl_dt_name) { - char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : ""; + const char *prefix = ""; char str[64]; + if (IS_ENABLED(CONFIG_ARM64) && !IS_ENABLED(CONFIG_OF_UPSTREAM)) + prefix = "allwinner/"; + snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name); env_set("fdtfile", str); } -- cgit v1.3.1 From 71f07932756fa9f414146618c02ed299d565f092 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 13 Jan 2026 12:01:55 +0800 Subject: power: regulator: add AXP318W support The PMIC is also known as AXP819 in vendor pmu code For DCDC6, 8, 9, the underlying hardware support more than two levels voltage step tuning, but for now only first two levels are implemented in this driver, hence highest voltage will be limited at seccond level. It actual meets board requirement in current design, and we've verified it in Radxa Cubie A7A board. Following are detail explanation of voltage tuning stpes for those DCDCs: DCDC | voltage range | units | steps | implemented 6 | 0.5 - 1.2 | 10 mV | 71 | Y . | 1.22 - 1.54 | 20 mV | 17 | Y . | 1.8 - 2.4 | 20 mV | 31 | N . | 2.44 - 2.76 | 40 mV | 9 | N -------------------------------------------------- 8/9 | 0.5 - 1.2 | 10 mV | 71 | Y . | 1.22 - 1.84 | 20 mV | 32 | Y . | 1.9 - 3.4 | 100mV | 16 | N Signed-off-by: Yixun Lan Reviewed-by: Andre Przywara --- drivers/power/pmic/axp.c | 1 + drivers/power/regulator/axp_regulator.c | 50 +++++++++++++++++++++++++++++++++ include/axp_pmic.h | 1 + 3 files changed, 52 insertions(+) diff --git a/drivers/power/pmic/axp.c b/drivers/power/pmic/axp.c index 1204ec00f8d..7d8348b0769 100644 --- a/drivers/power/pmic/axp.c +++ b/drivers/power/pmic/axp.c @@ -95,6 +95,7 @@ static const struct udevice_id axp_pmic_ids[] = { { .compatible = "x-powers,axp806", .data = AXP806_ID }, { .compatible = "x-powers,axp809", .data = AXP809_ID }, { .compatible = "x-powers,axp813", .data = AXP813_ID }, + { .compatible = "x-powers,axp318w", .data = AXP318_ID }, { } }; diff --git a/drivers/power/regulator/axp_regulator.c b/drivers/power/regulator/axp_regulator.c index 7794a4f5d92..16d3a8f7f90 100644 --- a/drivers/power/regulator/axp_regulator.c +++ b/drivers/power/regulator/axp_regulator.c @@ -189,6 +189,55 @@ static const struct axp_regulator_plat axp313_regulators[] = { { } }; + /* + * Only two level step tuning is implemented for DCDC6, 8, 9 + * so the voltage below is not support in this driver + * DCDC6: 20 (v1.8 - 2.4v), 40 (2.44v - 2.76v) + * DCDC8,9: 100 (1.9v - 3.4v) + */ +static const struct axp_regulator_plat axp318_regulators[] = { + { "dcdc1", 0x10, BIT(0), 0x12, 0x1f, 1000, 3400, 100, NA }, + { "dcdc2", 0x10, BIT(1), 0x13, 0x7f, 500, 1540, 10, 70 }, + { "dcdc3", 0x10, BIT(2), 0x14, 0x7f, 500, 1540, 10, 70 }, + { "dcdc4", 0x10, BIT(3), 0x15, 0x7f, 500, 1540, 10, 70 }, + { "dcdc5", 0x10, BIT(4), 0x16, 0x7f, 500, 1540, 10, 70 }, + { "dcdc6", 0x10, BIT(5), 0x17, 0x7f, 500, 1540, 10, 70 }, + { "dcdc7", 0x10, BIT(6), 0x18, 0x7f, 500, 1840, 10, 70 }, + { "dcdc8", 0x10, BIT(7), 0x19, 0x7f, 500, 1840, 10, 70 }, + { "dcdc9", 0x11, BIT(0), 0x1a, 0x7f, 500, 1840, 10, 70 }, + { "aldo1", 0x20, BIT(0), 0x24, 0x1f, 500, 3400, 100, NA }, + { "aldo2", 0x20, BIT(1), 0x25, 0x1f, 500, 3400, 100, NA }, + { "aldo3", 0x20, BIT(2), 0x26, 0x1f, 500, 3400, 100, NA }, + { "aldo4", 0x20, BIT(3), 0x27, 0x1f, 500, 3400, 100, NA }, + { "aldo5", 0x20, BIT(4), 0x28, 0x1f, 500, 3400, 100, NA }, + { "aldo6", 0x20, BIT(5), 0x29, 0x1f, 500, 3400, 100, NA }, + { "bldo1", 0x20, BIT(6), 0x2a, 0x1f, 500, 3400, 100, NA }, + { "bldo2", 0x20, BIT(7), 0x2b, 0x1f, 500, 3400, 100, NA }, + { "bldo3", 0x21, BIT(0), 0x2c, 0x1f, 500, 3400, 100, NA }, + { "bldo4", 0x21, BIT(1), 0x2d, 0x1f, 500, 3400, 100, NA }, + { "bldo5", 0x21, BIT(2), 0x2e, 0x1f, 500, 3400, 100, NA }, + { "cldo1", 0x21, BIT(3), 0x2f, 0x1f, 500, 3400, 100, NA }, + { "cldo2", 0x21, BIT(4), 0x30, 0x1f, 500, 3400, 100, NA }, + { "cldo3", 0x21, BIT(5), 0x31, 0x1f, 500, 3400, 100, NA }, + { "cldo4", 0x21, BIT(6), 0x32, 0x1f, 500, 3400, 100, NA }, + { "cldo5", 0x21, BIT(7), 0x33, 0x1f, 500, 3400, 100, NA }, + { "dldo1", 0x22, BIT(0), 0x34, 0x1f, 500, 3400, 100, NA }, + { "dldo2", 0x22, BIT(1), 0x35, 0x1f, 500, 3400, 100, NA }, + { "dldo3", 0x22, BIT(2), 0x36, 0x1f, 500, 3400, 100, NA }, + { "dldo4", 0x22, BIT(3), 0x37, 0x1f, 500, 3400, 100, NA }, + { "dldo5", 0x22, BIT(4), 0x38, 0x1f, 500, 3400, 100, NA }, + { "dldo6", 0x22, BIT(5), 0x39, 0x1f, 500, 3400, 100, NA }, + { "eldo1", 0x22, BIT(6), 0x3a, 0x1f, 500, 1500, 25, NA }, + { "eldo2", 0x22, BIT(7), 0x3b, 0x1f, 500, 1500, 25, NA }, + { "eldo3", 0x23, BIT(0), 0x3c, 0x1f, 500, 1500, 25, NA }, + { "eldo4", 0x23, BIT(1), 0x3d, 0x1f, 500, 1500, 25, NA }, + { "eldo5", 0x23, BIT(2), 0x3e, 0x1f, 500, 1500, 25, NA }, + { "eldo6", 0x23, BIT(3), 0x3f, 0x1f, 500, 1500, 25, NA }, + { "swout1", 0x11, BIT(3), NA, NA, NA, NA, NA, NA }, + { "swout2", 0x11, BIT(4), NA, NA, NA, NA, NA, NA }, + { } +}; + /* * The "dcdc2" regulator has another range, beyond 1.54V up to 3.4V, in * steps of 100mV. We cannot model this easily, but also don't need that, @@ -318,6 +367,7 @@ static const struct axp_regulator_plat *const axp_regulators[] = { [AXP221_ID] = axp22x_regulators, [AXP223_ID] = axp22x_regulators, [AXP313_ID] = axp313_regulators, + [AXP318_ID] = axp318_regulators, [AXP323_ID] = axp313_regulators, [AXP717_ID] = axp717_regulators, [AXP803_ID] = axp803_regulators, diff --git a/include/axp_pmic.h b/include/axp_pmic.h index 1806a7270a0..2f547da74c2 100644 --- a/include/axp_pmic.h +++ b/include/axp_pmic.h @@ -39,6 +39,7 @@ enum { AXP806_ID, AXP809_ID, AXP813_ID, + AXP318_ID, }; int axp_set_dcdc1(unsigned int mvolt); -- cgit v1.3.1 From 61c2f29bde1d11a35664525d37c5806e61ec4304 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 13 Jan 2026 12:01:56 +0800 Subject: power: regulator: enable AWP318W SPL support Add the descriptions for the DC/DC regulators of the AXP318W, and enable it when CONFIG_AXP318W_POWER is enabled. Signed-off-by: Yixun Lan Reviewed-by: Andre Przywara --- drivers/power/Kconfig | 10 ++++++++++ drivers/power/Makefile | 1 + drivers/power/axp_spl.c | 20 ++++++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index d17337c0c3f..1b06d8a66c7 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -58,6 +58,7 @@ choice default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40 default AXP818_POWER if MACH_SUN8I_A83T + default AXP318W_POWER if MACH_SUN60I_A733 default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_V3S config SUNXI_NO_PMIC @@ -140,6 +141,14 @@ config AXP818_POWER Say y here to enable support for the axp818 pmic found on A83T dev board. +config AXP318W_POWER + bool "axp318w pmic support" + select AXP_PMIC_BUS + select CMD_POWEROFF + ---help--- + Select this to enable support for the AXP318W PMIC found on some + A733 boards. + config SY8106A_POWER bool "SY8106A pmic support" depends on MACH_SUNXI_H3_H5 @@ -154,6 +163,7 @@ config AXP_I2C_ADDRESS depends on ARCH_SUNXI && !SUNXI_NO_PMIC default 0x36 if AXP305_POWER default 0x36 if AXP313_POWER + default 0x36 if AXP318W_POWER default 0x30 if AXP152_POWER default 0x34 ---help--- diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 3363191fdc8..1a54898c874 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_AXP152_POWER) += axp152.o obj-$(CONFIG_AXP209_POWER) += axp209.o obj-$(CONFIG_AXP305_POWER) += axp_spl.o obj-$(CONFIG_AXP313_POWER) += axp_spl.o +obj-$(CONFIG_AXP318W_POWER) += axp_spl.o obj-$(CONFIG_AXP717_POWER) += axp_spl.o obj-$(CONFIG_AXP809_POWER) += axp809.o obj-$(CONFIG_AXP818_POWER) += axp818.o diff --git a/drivers/power/axp_spl.c b/drivers/power/axp_spl.c index 7c51a9b3dfb..0162ef5e4cc 100644 --- a/drivers/power/axp_spl.c +++ b/drivers/power/axp_spl.c @@ -67,6 +67,26 @@ static const struct axp_reg_desc_spl axp_spl_dcdc_regulators[] = { #define AXP_SHUTDOWN_REG 0x1a #define AXP_SHUTDOWN_MASK BIT(7) +#elif defined(CONFIG_AXP318W_POWER) /* AXP318W */ + +static const struct axp_reg_desc_spl axp_spl_dcdc_regulators[] = { + { 0x10, BIT(0), 0x12, 0x1f, 1000, 3400, 100, NA }, + { 0x10, BIT(1), 0x13, 0x7f, 500, 1540, 10, 70 }, + { 0x10, BIT(2), 0x14, 0x7f, 500, 1540, 10, 70 }, + { 0x10, BIT(3), 0x15, 0x7f, 500, 1540, 10, 70 }, + { 0x10, BIT(4), 0x16, 0x7f, 500, 1540, 10, 70 }, + { 0x10, BIT(5), 0x17, 0x7f, 500, 1540, 10, 70 }, + { 0x10, BIT(6), 0x18, 0x7f, 500, 1840, 10, 70 }, + { 0x10, BIT(7), 0x19, 0x7f, 500, 1840, 10, 70 }, + { 0x11, BIT(0), 0x1a, 0x7f, 500, 1840, 10, 70 }, +}; + +#define AXP_CHIP_VERSION 0 +#define AXP_CHIP_VERSION_MASK 0 +#define AXP_CHIP_ID 0 +#define AXP_SHUTDOWN_REG 0x55 +#define AXP_SHUTDOWN_MASK BIT(7) + #elif defined(CONFIG_AXP305_POWER) /* AXP305 */ static const struct axp_reg_desc_spl axp_spl_dcdc_regulators[] = { -- cgit v1.3.1 From 8805aa120ca5341ca14d8f7f2311f7a85d57a5f9 Mon Sep 17 00:00:00 2001 From: "J. Neuschäfer" Date: Tue, 20 Jan 2026 16:20:38 +0100 Subject: board: sunxi: Add X96Q support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The X96Q is a set-top box with an H313 SoC, AXP305 PMIC, 1 or 2 GiB RAM, 8 or 16 GiB eMMC flash, 2x USB A, Micro-SD, HDMI, Ethernet, audio/video output, and infrared input. https://x96mini.com/products/x96q-tv-box-android-10-set-top-box This commit adds a defconfig and some documentation. The devicetree is already in dts/upstream. The CONFIG_DRAM_SUNXI_* settings are chosen such that the register values in the DRAM PHY's MMIO space are as close as possible to those observed when booting with the preinstalled vendor U-Boot. The DRAM clock frequency of 600 MHz was reported in the vendor U-Boot's output. Signed-off-by: J. Neuschäfer Reviewed-by: Andre Przywara --- board/sunxi/MAINTAINERS | 5 +++++ configs/x96q_defconfig | 27 +++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 configs/x96q_defconfig diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index c52e8a34c85..775d0f7ae83 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -611,6 +611,11 @@ M: Andre Przywara S: Maintained F: configs/x96_mate_defconfig +X96Q TV BOX +M: J. Neuschäfer +S: Maintained +F: configs/x96q_defconfig + X96Q PRO+ TV BOX M: Andre Przywara S: Maintained diff --git a/configs/x96q_defconfig b/configs/x96q_defconfig new file mode 100644 index 00000000000..59f01aae4eb --- /dev/null +++ b/configs/x96q_defconfig @@ -0,0 +1,27 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h313-x96q" +CONFIG_DRAM_CLK=600 +CONFIG_SPL=y +CONFIG_DRAM_SUNXI_DX_ODT=0x03030303 +CONFIG_DRAM_SUNXI_DX_DRI=0x0e0e0e0e +CONFIG_DRAM_SUNXI_CA_DRI=0x1f12 +CONFIG_DRAM_SUNXI_TPR0=0xc0001002 +CONFIG_DRAM_SUNXI_TPR2=0x00000100 +CONFIG_DRAM_SUNXI_TPR10=0x002f0107 +CONFIG_DRAM_SUNXI_TPR11=0xddddcccc +CONFIG_DRAM_SUNXI_TPR12=0xeddc7665 +CONFIG_MACH_SUN50I_H616=y +CONFIG_SUNXI_DRAM_H616_DDR3_1333=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_R_I2C_ENABLE=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SPEED=400000 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SUN8I_EMAC=y +CONFIG_AXP305_POWER=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y -- cgit v1.3.1