From 424b324165ea0343598c5a8b52591ea504dcde52 Mon Sep 17 00:00:00 2001 From: Mateus Lima Alves Date: Mon, 26 Jan 2026 13:05:19 -0300 Subject: armv7: Add CPLD support via IFC to the ls1021a-iot board. This patch adds CPLD support via IFC to the ls1021a-iot board. Signed-off-by: Mateus Lima Alves --- board/freescale/ls1021aiot/ls1021aiot.c | 5 +++++ configs/ls1021aiot_sdcard_defconfig | 1 + drivers/misc/Kconfig | 7 ++++++- include/configs/ls1021aiot.h | 34 +++++++++++++++++++++++++++++++++ 4 files changed, 46 insertions(+), 1 deletion(-) diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c index 4eff0a3fee0..52a3c3abdb4 100644 --- a/board/freescale/ls1021aiot/ls1021aiot.c +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -120,6 +121,10 @@ int board_early_init_f(void) #endif +#ifdef CONFIG_FSL_IFC + init_early_memctl_regs(); +#endif + arch_soc_init(); return 0; diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index 6b32150e408..78b81c1895e 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -106,3 +106,4 @@ CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_FSL_IFC=y diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index dde773ab6b1..be7fdab56d1 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -694,7 +694,12 @@ config ESM_PMIC typically to reboot the board in error condition. config FSL_IFC - bool + bool "Freescale Integrated Flash Controller" + depends on ARM + help + This driver is for the Integrated Flash Controller(IFC) module + available in Freescale SoCs. This controller allows to handle + devices such as NOR, NAND, FPGA and ASIC etc. config SL28CPLD bool "Enable Kontron sl28cpld multi-function driver" diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 971a393817a..59acf00b8e5 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -44,6 +44,40 @@ #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +/* CPLD */ + +#define CFG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE + +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) + +/* CPLD Timing parameters for IFC GPCM */ +#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ + FTIM0_GPCM_TEADC(0xf) | \ + FTIM0_GPCM_TEAHC(0xf)) +#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ + FTIM2_GPCM_TCH(0xf) | \ + FTIM2_GPCM_TWP(0xff)) +#define CFG_SYS_FPGA_FTIM3 0x0 +#define CFG_SYS_CSPR0_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_FPGA_FTIM3 + /* * Serial Port */ -- cgit v1.2.3 From add12cb688d5a05858beb82a9a3c272767468262 Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Fri, 23 Jan 2026 15:54:06 +0800 Subject: board: nxp: Rename board directory from board/freescale to board/nxp This patch renames the board directory from board/freescale to board/nxp because NXP now provides Board Support Packages (BSPs) and tools for the former Freescale i.MX and other i.MX products. All relevant references have been updated accordingly. This change does not affect functionality. Signed-off-by: Alice Guo Reviewed-by: Fabio Estevam --- MAINTAINERS | 4 +- arch/arm/Kconfig | 34 +- arch/arm/cpu/armv7/vf610/Kconfig | 2 +- arch/arm/mach-imx/imx8/Kconfig | 4 +- arch/arm/mach-imx/imx8m/Kconfig | 8 +- arch/arm/mach-imx/imx8ulp/Kconfig | 2 +- arch/arm/mach-imx/imx9/Kconfig | 14 +- arch/arm/mach-imx/imxrt/Kconfig | 6 +- arch/arm/mach-imx/mx5/Kconfig | 4 +- arch/arm/mach-imx/mx6/Kconfig | 18 +- arch/arm/mach-imx/mx7/Kconfig | 2 +- arch/arm/mach-imx/mx7ulp/Kconfig | 2 +- arch/arm/mach-imx/mxs/Kconfig | 4 +- arch/m68k/Kconfig | 20 +- arch/powerpc/cpu/mpc83xx/Kconfig | 2 +- arch/powerpc/cpu/mpc85xx/Kconfig | 18 +- board/CZ.NIC/turris_1x/MAINTAINERS | 4 +- board/CZ.NIC/turris_1x/Makefile | 4 +- board/CZ.NIC/turris_1x/turris_1x.c | 2 +- board/beacon/imx8mm/Makefile | 2 +- board/beacon/imx8mn/Makefile | 2 +- board/beacon/imx8mp/Kconfig | 2 +- board/beacon/imx8mp/Makefile | 2 +- board/beckhoff/mx53cx9020/imximage.cfg | 2 +- board/beckhoff/mx53cx9020/mx53cx9020.c | 2 +- board/beckhoff/mx53cx9020/mx53cx9020_video.c | 2 +- board/boundary/nitrogen6x/README | 2 +- board/ea/mx7ulp_com/imximage.cfg | 2 +- board/freescale/common/Makefile | 83 - board/freescale/common/arm_sleep.c | 130 -- board/freescale/common/cadmus.c | 74 - board/freescale/common/cadmus.h | 33 - board/freescale/common/cds_pci_ft.c | 17 - board/freescale/common/cds_via.c | 95 - board/freescale/common/cmd_esbc_validate.c | 86 - board/freescale/common/eeprom.h | 30 - board/freescale/common/emc2305.c | 61 - board/freescale/common/emc2305.h | 22 - board/freescale/common/fman.c | 88 - board/freescale/common/fman.h | 14 - board/freescale/common/fsl_chain_of_trust.c | 160 -- board/freescale/common/fsl_validate.c | 973 ---------- board/freescale/common/i2c_common.c | 34 - board/freescale/common/i2c_common.h | 30 - board/freescale/common/i2c_mux.c | 41 - board/freescale/common/i2c_mux.h | 15 - board/freescale/common/ics307_clk.c | 149 -- board/freescale/common/ics307_clk.h | 14 - board/freescale/common/ls102xa_stream_id.c | 35 - board/freescale/common/mc34vr500.c | 94 - board/freescale/common/mmc.c | 49 - board/freescale/common/mpc85xx_sleep.c | 97 - board/freescale/common/ngpixis.c | 247 --- board/freescale/common/ngpixis.h | 60 - board/freescale/common/ns_access.c | 241 --- board/freescale/common/p_corenet/Makefile | 7 - board/freescale/common/p_corenet/law.c | 36 - board/freescale/common/p_corenet/tlb.c | 161 -- board/freescale/common/pfuze.c | 172 -- board/freescale/common/pfuze.h | 17 - board/freescale/common/qixis.c | 389 ---- board/freescale/common/qixis.h | 190 -- board/freescale/common/sdhc_boot.c | 78 - board/freescale/common/sgmii_riser.h | 16 - board/freescale/common/sleep.h | 20 - board/freescale/common/spl.h | 12 - board/freescale/common/sys_eeprom.c | 648 ------- board/freescale/common/via.h | 18 - board/freescale/common/vid.c | 797 -------- board/freescale/common/vid.h | 75 - board/freescale/common/vsc3316_3308.h | 23 - board/freescale/imx8mm_evk/Kconfig | 15 - board/freescale/imx8mm_evk/MAINTAINERS | 7 - board/freescale/imx8mm_evk/Makefile | 12 - board/freescale/imx8mm_evk/imx8mm_evk.c | 93 - board/freescale/imx8mm_evk/imx8mm_evk.env | 67 - .../imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg | 7 - board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg | 8 - board/freescale/imx8mm_evk/lpddr4_timing.c | 1848 ------------------ board/freescale/imx8mm_evk/spl.c | 143 -- board/freescale/imx8mn_evk/Kconfig | 18 - board/freescale/imx8mn_evk/MAINTAINERS | 7 - board/freescale/imx8mn_evk/Makefile | 18 - board/freescale/imx8mn_evk/ddr4_timing.c | 1053 ---------- board/freescale/imx8mn_evk/ddr4_timing_ld.c | 1054 ---------- board/freescale/imx8mn_evk/imx8mn_evk.c | 65 - board/freescale/imx8mn_evk/imx8mn_evk.env | 67 - board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg | 9 - board/freescale/imx8mn_evk/lpddr4_timing.c | 1587 --------------- board/freescale/imx8mn_evk/lpddr4_timing_ld.c | 1440 -------------- board/freescale/imx8mn_evk/spl.c | 137 -- board/freescale/imx8mp_evk/Kconfig | 15 - board/freescale/imx8mp_evk/MAINTAINERS | 7 - board/freescale/imx8mp_evk/Makefile | 12 - board/freescale/imx8mp_evk/imx8mp_evk.c | 43 - board/freescale/imx8mp_evk/imx8mp_evk.env | 58 - board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg | 9 - board/freescale/imx8mp_evk/lpddr4_timing.c | 2048 -------------------- board/freescale/imx8mp_evk/spl.c | 145 -- board/freescale/imx8mq_evk/Kconfig | 15 - board/freescale/imx8mq_evk/MAINTAINERS | 7 - board/freescale/imx8mq_evk/Makefile | 12 - board/freescale/imx8mq_evk/imx8mq_evk.c | 84 - board/freescale/imx8mq_evk/imx8mq_evk.env | 60 - board/freescale/imx8mq_evk/lpddr4_timing.c | 1323 ------------- board/freescale/imx8mq_evk/lpddr4_timing_b0.c | 1190 ------------ board/freescale/imx8mq_evk/spl.c | 256 --- board/freescale/imx8qm_mek/Kconfig | 15 - board/freescale/imx8qm_mek/MAINTAINERS | 6 - board/freescale/imx8qm_mek/Makefile | 8 - board/freescale/imx8qm_mek/README | 54 - board/freescale/imx8qm_mek/imx8qm_mek.c | 137 -- board/freescale/imx8qm_mek/imximage.cfg | 18 - board/freescale/imx8qm_mek/spl.c | 71 - board/freescale/imx8qm_mek/uboot-container.cfg | 12 - board/freescale/imx8qxp_mek/Kconfig | 15 - board/freescale/imx8qxp_mek/MAINTAINERS | 7 - board/freescale/imx8qxp_mek/Makefile | 8 - board/freescale/imx8qxp_mek/imx8qxp_mek.c | 161 -- board/freescale/imx8qxp_mek/imximage.cfg | 20 - board/freescale/imx8qxp_mek/spl.c | 89 - board/freescale/imx8qxp_mek/uboot-container.cfg | 12 - board/freescale/imx8ulp_evk/Kconfig | 12 - board/freescale/imx8ulp_evk/MAINTAINERS | 6 - board/freescale/imx8ulp_evk/Makefile | 12 - board/freescale/imx8ulp_evk/imx8ulp_evk.c | 136 -- board/freescale/imx8ulp_evk/imx8ulp_evk.env | 97 - board/freescale/imx8ulp_evk/lpddr4_timing.c | 1158 ----------- board/freescale/imx8ulp_evk/lpddr4_timing_266.c | 1109 ----------- board/freescale/imx8ulp_evk/spl.c | 148 -- board/freescale/imx91_evk/Kconfig | 19 - board/freescale/imx91_evk/MAINTAINERS | 7 - board/freescale/imx91_evk/Makefile | 16 - board/freescale/imx91_evk/imx91_evk.c | 26 - board/freescale/imx91_evk/imx91_evk.env | 88 - board/freescale/imx91_evk/lpddr4_timing_1600mts.c | 1995 ------------------- .../imx91_evk/lpddr4_timing_1600mts_ecc.c | 1995 ------------------- board/freescale/imx91_evk/lpddr4_timing_2400mts.c | 1995 ------------------- .../imx91_evk/lpddr4_timing_2400mts_ecc.c | 1995 ------------------- board/freescale/imx91_evk/spl.c | 151 -- board/freescale/imx91_frdm/Kconfig | 12 - board/freescale/imx91_frdm/MAINTAINERS | 7 - board/freescale/imx91_frdm/Makefile | 16 - board/freescale/imx91_frdm/imx91_frdm.c | 84 - board/freescale/imx91_frdm/imx91_frdm.env | 89 - .../imx91_frdm/lpddr4_2400mts_1gb_timing.c | 1996 ------------------- .../imx91_frdm/lpddr4_2400mts_2gb_timing.c | 1996 ------------------- .../imx91_frdm/lpddr4_2400mts_ecc_1gb_timing.c | 1996 ------------------- .../imx91_frdm/lpddr4_2400mts_ecc_2gb_timing.c | 1996 ------------------- board/freescale/imx91_frdm/lpddr4_timing.h | 12 - board/freescale/imx91_frdm/spl.c | 193 -- board/freescale/imx93_evk/Kconfig | 19 - board/freescale/imx93_evk/MAINTAINERS | 7 - board/freescale/imx93_evk/Makefile | 12 - board/freescale/imx93_evk/imx93_evk.c | 42 - board/freescale/imx93_evk/imx93_evk.env | 89 - board/freescale/imx93_evk/lpddr4x_timing.c | 1994 ------------------- board/freescale/imx93_evk/lpddr4x_timing_1866mts.c | 1995 ------------------- board/freescale/imx93_evk/spl.c | 157 -- board/freescale/imx93_frdm/Kconfig | 12 - board/freescale/imx93_frdm/MAINTAINERS | 6 - board/freescale/imx93_frdm/Makefile | 11 - board/freescale/imx93_frdm/imx93_frdm.c | 124 -- board/freescale/imx93_frdm/imx93_frdm.env | 39 - board/freescale/imx93_frdm/lpddr4_timing.h | 12 - board/freescale/imx93_frdm/lpddr4x_1gb_timing.c | 1996 ------------------- board/freescale/imx93_frdm/lpddr4x_2gb_timing.c | 1995 ------------------- board/freescale/imx93_frdm/spl.c | 195 -- board/freescale/imx93_qsb/Kconfig | 12 - board/freescale/imx93_qsb/MAINTAINERS | 7 - board/freescale/imx93_qsb/Makefile | 16 - board/freescale/imx93_qsb/imx93_qsb.c | 26 - board/freescale/imx93_qsb/imx93_qsb.env | 88 - board/freescale/imx93_qsb/lpddr4_timing.c | 1995 ------------------- board/freescale/imx93_qsb/lpddr4_timing_ecc.c | 1995 ------------------- board/freescale/imx93_qsb/spl.c | 159 -- board/freescale/imx94_evk/Kconfig | 12 - board/freescale/imx94_evk/MAINTAINERS | 6 - board/freescale/imx94_evk/Makefile | 11 - board/freescale/imx94_evk/imx94_evk.c | 41 - board/freescale/imx94_evk/imx94_evk.env | 100 - board/freescale/imx94_evk/spl.c | 82 - board/freescale/imx95_evk/Kconfig | 12 - board/freescale/imx95_evk/MAINTAINERS | 8 - board/freescale/imx95_evk/Makefile | 11 - board/freescale/imx95_evk/imx95_evk.c | 31 - board/freescale/imx95_evk/imx95_evk.env | 91 - board/freescale/imx95_evk/spl.c | 80 - board/freescale/imxrt1020-evk/Kconfig | 18 - board/freescale/imxrt1020-evk/MAINTAINERS | 6 - board/freescale/imxrt1020-evk/Makefile | 6 - board/freescale/imxrt1020-evk/imximage.cfg | 35 - board/freescale/imxrt1020-evk/imxrt1020-evk.c | 79 - board/freescale/imxrt1050-evk/Kconfig | 18 - board/freescale/imxrt1050-evk/MAINTAINERS | 7 - board/freescale/imxrt1050-evk/Makefile | 6 - board/freescale/imxrt1050-evk/imximage-nor.cfg | 41 - board/freescale/imxrt1050-evk/imximage.cfg | 41 - .../freescale/imxrt1050-evk/imxrt1050-evk-nor.env | 13 - board/freescale/imxrt1050-evk/imxrt1050-evk.c | 84 - board/freescale/imxrt1050-evk/imxrt1050-evk.env | 13 - board/freescale/imxrt1170-evk/Kconfig | 18 - board/freescale/imxrt1170-evk/MAINTAINERS | 7 - board/freescale/imxrt1170-evk/Makefile | 6 - board/freescale/imxrt1170-evk/imximage.cfg | 31 - board/freescale/imxrt1170-evk/imxrt1170-evk.c | 79 - board/freescale/ls1012afrdm/Kconfig | 80 - board/freescale/ls1012afrdm/MAINTAINERS | 17 - board/freescale/ls1012afrdm/Makefile | 8 - board/freescale/ls1012afrdm/README | 58 - board/freescale/ls1012afrdm/eth.c | 124 -- board/freescale/ls1012afrdm/ls1012afrdm.c | 188 -- board/freescale/ls1012aqds/Kconfig | 72 - board/freescale/ls1012aqds/MAINTAINERS | 8 - board/freescale/ls1012aqds/Makefile | 8 - board/freescale/ls1012aqds/README | 59 - board/freescale/ls1012aqds/eth.c | 309 --- board/freescale/ls1012aqds/ls1012aqds.c | 287 --- board/freescale/ls1012aqds/ls1012aqds_pfe.h | 44 - board/freescale/ls1012aqds/ls1012aqds_qixis.h | 34 - board/freescale/ls1012ardb/Kconfig | 108 -- board/freescale/ls1012ardb/MAINTAINERS | 17 - board/freescale/ls1012ardb/Makefile | 8 - board/freescale/ls1012ardb/README | 97 - board/freescale/ls1012ardb/eth.c | 171 -- board/freescale/ls1012ardb/ls1012ardb.c | 411 ---- board/freescale/ls1021aiot/Kconfig | 15 - board/freescale/ls1021aiot/MAINTAINERS | 7 - board/freescale/ls1021aiot/Makefile | 6 - board/freescale/ls1021aiot/README | 58 - board/freescale/ls1021aiot/ls1021aiot.c | 207 -- board/freescale/ls1021aiot/ls102xa_pbi.cfg | 14 - board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg | 27 - board/freescale/ls1021aiot/psci.S | 27 - board/freescale/ls1021aqds/Kconfig | 15 - board/freescale/ls1021aqds/MAINTAINERS | 14 - board/freescale/ls1021aqds/Makefile | 9 - board/freescale/ls1021aqds/README | 117 -- board/freescale/ls1021aqds/ddr.c | 199 -- board/freescale/ls1021aqds/ddr.h | 61 - board/freescale/ls1021aqds/ls1021aqds.c | 456 ----- board/freescale/ls1021aqds/ls1021aqds_qixis.h | 36 - board/freescale/ls1021aqds/ls102xa_pbi.cfg | 12 - board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg | 7 - board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg | 14 - board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg | 14 - board/freescale/ls1021aqds/psci.S | 32 - board/freescale/ls1021atsn/Kconfig | 16 - board/freescale/ls1021atsn/MAINTAINERS | 8 - board/freescale/ls1021atsn/Makefile | 3 - board/freescale/ls1021atsn/README.rst | 97 - board/freescale/ls1021atsn/ls1021atsn.c | 264 --- board/freescale/ls1021atsn/ls102xa_pbi.cfg | 15 - board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg | 8 - board/freescale/ls1021atwr/Kconfig | 15 - board/freescale/ls1021atwr/MAINTAINERS | 12 - board/freescale/ls1021atwr/Makefile | 8 - board/freescale/ls1021atwr/README | 114 -- board/freescale/ls1021atwr/ls1021atwr.c | 753 ------- board/freescale/ls1021atwr/ls102xa_pbi.cfg | 12 - board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg | 8 - board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg | 8 - board/freescale/ls1021atwr/psci.S | 24 - board/freescale/ls1028a/Kconfig | 47 - board/freescale/ls1028a/MAINTAINERS | 26 - board/freescale/ls1028a/Makefile | 8 - board/freescale/ls1028a/README | 164 -- board/freescale/ls1028a/ddr.c | 20 - board/freescale/ls1028a/ls1028a.c | 329 ---- board/freescale/ls1043aqds/Kconfig | 15 - board/freescale/ls1043aqds/MAINTAINERS | 14 - board/freescale/ls1043aqds/Makefile | 11 - board/freescale/ls1043aqds/README | 64 - board/freescale/ls1043aqds/ddr.c | 145 -- board/freescale/ls1043aqds/ddr.h | 61 - board/freescale/ls1043aqds/eth.c | 501 ----- board/freescale/ls1043aqds/ls1043aqds.c | 595 ------ board/freescale/ls1043aqds/ls1043aqds_pbi.cfg | 14 - board/freescale/ls1043aqds/ls1043aqds_qixis.h | 38 - board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg | 7 - .../freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg | 8 - .../ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg | 8 - board/freescale/ls1043ardb/Kconfig | 16 - board/freescale/ls1043ardb/MAINTAINERS | 13 - board/freescale/ls1043ardb/Makefile | 10 - board/freescale/ls1043ardb/README | 54 - board/freescale/ls1043ardb/cpld.c | 178 -- board/freescale/ls1043ardb/cpld.h | 46 - board/freescale/ls1043ardb/ddr.c | 254 --- board/freescale/ls1043ardb/ddr.h | 116 -- board/freescale/ls1043ardb/eth.c | 77 - board/freescale/ls1043ardb/ls1043ardb.c | 415 ---- board/freescale/ls1043ardb/ls1043ardb_pbi.cfg | 14 - board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg | 7 - board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg | 7 - board/freescale/ls1046afrwy/Kconfig | 16 - board/freescale/ls1046afrwy/MAINTAINERS | 8 - board/freescale/ls1046afrwy/Makefile | 7 - board/freescale/ls1046afrwy/README | 76 - board/freescale/ls1046afrwy/ddr.c | 19 - board/freescale/ls1046afrwy/eth.c | 118 -- board/freescale/ls1046afrwy/ls1046afrwy.c | 218 --- board/freescale/ls1046aqds/Kconfig | 15 - board/freescale/ls1046aqds/MAINTAINERS | 14 - board/freescale/ls1046aqds/Makefile | 11 - board/freescale/ls1046aqds/README | 70 - board/freescale/ls1046aqds/ddr.c | 130 -- board/freescale/ls1046aqds/ddr.h | 43 - board/freescale/ls1046aqds/eth.c | 431 ---- board/freescale/ls1046aqds/ls1046aqds.c | 479 ----- board/freescale/ls1046aqds/ls1046aqds_pbi.cfg | 17 - board/freescale/ls1046aqds/ls1046aqds_qixis.h | 38 - board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg | 7 - .../freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg | 8 - .../ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg | 8 - board/freescale/ls1046ardb/Kconfig | 16 - board/freescale/ls1046ardb/MAINTAINERS | 16 - board/freescale/ls1046ardb/Makefile | 10 - board/freescale/ls1046ardb/cpld.c | 167 -- board/freescale/ls1046ardb/cpld.h | 49 - board/freescale/ls1046ardb/ddr.c | 132 -- board/freescale/ls1046ardb/ddr.h | 62 - board/freescale/ls1046ardb/eth.c | 129 -- board/freescale/ls1046ardb/ls1046ardb.c | 192 -- board/freescale/ls1046ardb/ls1046ardb_pbi.cfg | 22 - board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg | 26 - board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg | 7 - board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg | 7 - board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg | 7 - board/freescale/ls1088a/Kconfig | 31 - board/freescale/ls1088a/MAINTAINERS | 35 - board/freescale/ls1088a/Makefile | 10 - board/freescale/ls1088a/README | 145 -- board/freescale/ls1088a/ddr.c | 134 -- board/freescale/ls1088a/ddr.h | 48 - board/freescale/ls1088a/eth_ls1088aqds.c | 105 - board/freescale/ls1088a/eth_ls1088ardb.c | 13 - board/freescale/ls1088a/ls1088a.c | 1041 ---------- board/freescale/ls1088a/ls1088a_qixis.h | 55 - board/freescale/ls2080aqds/Kconfig | 16 - board/freescale/ls2080aqds/MAINTAINERS | 13 - board/freescale/ls2080aqds/Makefile | 7 - board/freescale/ls2080aqds/README | 215 -- board/freescale/ls2080aqds/ddr.c | 181 -- board/freescale/ls2080aqds/ddr.h | 90 - board/freescale/ls2080aqds/eth.c | 117 -- board/freescale/ls2080aqds/ls2080aqds.c | 349 ---- board/freescale/ls2080aqds/ls2080aqds_qixis.h | 29 - board/freescale/ls2080ardb/Kconfig | 15 - board/freescale/ls2080ardb/MAINTAINERS | 32 - board/freescale/ls2080ardb/Makefile | 6 - board/freescale/ls2080ardb/README | 134 -- board/freescale/ls2080ardb/ddr.c | 186 -- board/freescale/ls2080ardb/ddr.h | 75 - board/freescale/ls2080ardb/eth_ls2080rdb.c | 36 - board/freescale/ls2080ardb/ls2080ardb.c | 571 ------ board/freescale/ls2080ardb/ls2080ardb_qixis.h | 19 - board/freescale/lx2160a/Kconfig | 47 - board/freescale/lx2160a/MAINTAINERS | 55 - board/freescale/lx2160a/Makefile | 11 - board/freescale/lx2160a/README | 329 ---- board/freescale/lx2160a/ddr.c | 20 - board/freescale/lx2160a/eth_lx2160aqds.c | 148 -- board/freescale/lx2160a/eth_lx2160ardb.c | 144 -- board/freescale/lx2160a/eth_lx2162aqds.c | 143 -- board/freescale/lx2160a/lx2160a.c | 864 --------- board/freescale/lx2160a/lx2160a.h | 76 - board/freescale/m5208evbe/Kconfig | 15 - board/freescale/m5208evbe/MAINTAINERS | 6 - board/freescale/m5208evbe/Makefile | 6 - board/freescale/m5208evbe/m5208evbe.c | 83 - board/freescale/m5235evb/Kconfig | 18 - board/freescale/m5235evb/MAINTAINERS | 7 - board/freescale/m5235evb/Makefile | 6 - board/freescale/m5235evb/m5235evb.c | 111 -- board/freescale/m5249evb/Kconfig | 15 - board/freescale/m5249evb/MAINTAINERS | 6 - board/freescale/m5249evb/Makefile | 6 - board/freescale/m5249evb/m5249evb.c | 99 - board/freescale/m5253demo/Kconfig | 19 - board/freescale/m5253demo/MAINTAINERS | 6 - board/freescale/m5253demo/Makefile | 6 - board/freescale/m5253demo/flash.c | 440 ----- board/freescale/m5253demo/m5253demo.c | 142 -- board/freescale/m5272c3/Kconfig | 15 - board/freescale/m5272c3/MAINTAINERS | 6 - board/freescale/m5272c3/Makefile | 6 - board/freescale/m5272c3/m5272c3.c | 44 - board/freescale/m5275evb/Kconfig | 15 - board/freescale/m5275evb/MAINTAINERS | 6 - board/freescale/m5275evb/Makefile | 6 - board/freescale/m5275evb/m5275evb.c | 104 - board/freescale/m5282evb/Kconfig | 15 - board/freescale/m5282evb/MAINTAINERS | 6 - board/freescale/m5282evb/Makefile | 6 - board/freescale/m5282evb/m5282evb.c | 87 - board/freescale/m53017evb/Kconfig | 15 - board/freescale/m53017evb/MAINTAINERS | 6 - board/freescale/m53017evb/Makefile | 6 - board/freescale/m53017evb/README | 178 -- board/freescale/m53017evb/m53017evb.c | 83 - board/freescale/m5329evb/Kconfig | 15 - board/freescale/m5329evb/MAINTAINERS | 7 - board/freescale/m5329evb/Makefile | 6 - board/freescale/m5329evb/m5329evb.c | 77 - board/freescale/m5329evb/nand.c | 70 - board/freescale/m5373evb/Kconfig | 15 - board/freescale/m5373evb/MAINTAINERS | 6 - board/freescale/m5373evb/Makefile | 6 - board/freescale/m5373evb/README | 324 ---- board/freescale/m5373evb/m5373evb.c | 77 - board/freescale/m5373evb/nand.c | 74 - board/freescale/mpc837xerdb/Kconfig | 15 - board/freescale/mpc837xerdb/MAINTAINERS | 7 - board/freescale/mpc837xerdb/Makefile | 6 - board/freescale/mpc837xerdb/README | 97 - board/freescale/mpc837xerdb/mpc837xerdb.c | 242 --- board/freescale/mpc8548cds/Kconfig | 24 - board/freescale/mpc8548cds/MAINTAINERS | 8 - board/freescale/mpc8548cds/Makefile | 10 - board/freescale/mpc8548cds/ddr.c | 51 - board/freescale/mpc8548cds/law.c | 18 - board/freescale/mpc8548cds/mpc8548cds.c | 170 -- board/freescale/mpc8548cds/tlb.c | 87 - board/freescale/mx23evk/Kconfig | 15 - board/freescale/mx23evk/MAINTAINERS | 8 - board/freescale/mx23evk/Makefile | 10 - board/freescale/mx23evk/mx23evk.c | 55 - board/freescale/mx23evk/spl_boot.c | 133 -- board/freescale/mx28evk/Kconfig | 15 - board/freescale/mx28evk/MAINTAINERS | 7 - board/freescale/mx28evk/Makefile | 10 - board/freescale/mx28evk/README | 62 - board/freescale/mx28evk/iomux.c | 204 -- board/freescale/mx28evk/mx28evk.c | 73 - board/freescale/mx51evk/Kconfig | 18 - board/freescale/mx51evk/MAINTAINERS | 6 - board/freescale/mx51evk/Makefile | 7 - board/freescale/mx51evk/imximage.cfg | 108 -- board/freescale/mx51evk/mx51evk.c | 220 --- board/freescale/mx53loco/Kconfig | 21 - board/freescale/mx53loco/MAINTAINERS | 7 - board/freescale/mx53loco/Makefile | 6 - board/freescale/mx53loco/imximage.cfg | 83 - board/freescale/mx53loco/mx53loco.c | 246 --- board/freescale/mx6memcal/Kconfig | 230 --- board/freescale/mx6memcal/MAINTAINERS | 7 - board/freescale/mx6memcal/Makefile | 11 - board/freescale/mx6memcal/README | 49 - board/freescale/mx6memcal/mx6memcal.c | 26 - board/freescale/mx6memcal/spl.c | 457 ----- board/freescale/mx6sabreauto/Kconfig | 12 - board/freescale/mx6sabreauto/MAINTAINERS | 7 - board/freescale/mx6sabreauto/Makefile | 7 - board/freescale/mx6sabreauto/mx6sabreauto.c | 931 --------- board/freescale/mx6sabresd/Kconfig | 12 - board/freescale/mx6sabresd/MAINTAINERS | 6 - board/freescale/mx6sabresd/Makefile | 7 - board/freescale/mx6sabresd/mx6sabresd.c | 868 --------- board/freescale/mx6slevk/Kconfig | 15 - board/freescale/mx6slevk/MAINTAINERS | 9 - board/freescale/mx6slevk/Makefile | 4 - board/freescale/mx6slevk/imximage.cfg | 122 -- board/freescale/mx6slevk/mx6slevk.c | 390 ---- board/freescale/mx6sllevk/Kconfig | 15 - board/freescale/mx6sllevk/MAINTAINERS | 7 - board/freescale/mx6sllevk/Makefile | 4 - board/freescale/mx6sllevk/imximage.cfg | 125 -- board/freescale/mx6sllevk/mx6sllevk.c | 114 -- board/freescale/mx6sllevk/plugin.S | 154 -- board/freescale/mx6sxsabreauto/Kconfig | 15 - board/freescale/mx6sxsabreauto/MAINTAINERS | 6 - board/freescale/mx6sxsabreauto/Makefile | 4 - board/freescale/mx6sxsabreauto/imximage.cfg | 134 -- board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 324 ---- board/freescale/mx6sxsabresd/Kconfig | 15 - board/freescale/mx6sxsabresd/MAINTAINERS | 6 - board/freescale/mx6sxsabresd/Makefile | 4 - board/freescale/mx6sxsabresd/imximage.cfg | 137 -- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 328 ---- board/freescale/mx6ul_14x14_evk/Kconfig | 12 - board/freescale/mx6ul_14x14_evk/MAINTAINERS | 7 - board/freescale/mx6ul_14x14_evk/Makefile | 4 - board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 471 ----- board/freescale/mx6ullevk/Kconfig | 15 - board/freescale/mx6ullevk/MAINTAINERS | 8 - board/freescale/mx6ullevk/Makefile | 4 - board/freescale/mx6ullevk/imximage.cfg | 114 -- board/freescale/mx6ullevk/mx6ullevk.c | 138 -- board/freescale/mx6ullevk/plugin.S | 138 -- board/freescale/mx7dsabresd/Kconfig | 15 - board/freescale/mx7dsabresd/MAINTAINERS | 8 - board/freescale/mx7dsabresd/Makefile | 4 - board/freescale/mx7dsabresd/imximage.cfg | 99 - board/freescale/mx7dsabresd/mx7dsabresd.c | 327 ---- board/freescale/mx7ulp_evk/Kconfig | 15 - board/freescale/mx7ulp_evk/MAINTAINERS | 7 - board/freescale/mx7ulp_evk/Makefile | 4 - board/freescale/mx7ulp_evk/imximage.cfg | 130 -- board/freescale/mx7ulp_evk/mx7ulp_evk.c | 95 - board/freescale/mx7ulp_evk/plugin.S | 216 --- board/freescale/p1010rdb/Kconfig | 12 - board/freescale/p1010rdb/MAINTAINERS | 21 - board/freescale/p1010rdb/Makefile | 26 - board/freescale/p1010rdb/README.P1010RDB-PA | 207 -- board/freescale/p1010rdb/README.P1010RDB-PB | 187 -- board/freescale/p1010rdb/ddr.c | 97 - board/freescale/p1010rdb/law.c | 16 - board/freescale/p1010rdb/p1010rdb.c | 679 ------- board/freescale/p1010rdb/spl.c | 113 -- board/freescale/p1010rdb/spl_minimal.c | 66 - board/freescale/p1010rdb/tlb.c | 90 - board/freescale/p1_p2_rdb_pc/Kconfig | 14 - board/freescale/p1_p2_rdb_pc/MAINTAINERS | 25 - board/freescale/p1_p2_rdb_pc/Makefile | 26 - board/freescale/p1_p2_rdb_pc/README | 64 - board/freescale/p1_p2_rdb_pc/ddr.c | 290 --- board/freescale/p1_p2_rdb_pc/law.c | 21 - board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 481 ----- board/freescale/p1_p2_rdb_pc/spl.c | 132 -- board/freescale/p1_p2_rdb_pc/spl_minimal.c | 64 - board/freescale/p1_p2_rdb_pc/tlb.c | 107 - board/freescale/p2041rdb/Kconfig | 12 - board/freescale/p2041rdb/MAINTAINERS | 11 - board/freescale/p2041rdb/Makefile | 10 - board/freescale/p2041rdb/README | 138 -- board/freescale/p2041rdb/cpld.c | 157 -- board/freescale/p2041rdb/cpld.h | 54 - board/freescale/p2041rdb/ddr.c | 143 -- board/freescale/p2041rdb/eth.c | 210 -- board/freescale/p2041rdb/p2041rdb.c | 248 --- board/freescale/p2041rdb/pbi.cfg | 33 - board/freescale/p2041rdb/rcw_p2041rdb.cfg | 11 - board/freescale/t102xrdb/Kconfig | 12 - board/freescale/t102xrdb/MAINTAINERS | 9 - board/freescale/t102xrdb/Makefile | 16 - board/freescale/t102xrdb/README | 340 ---- board/freescale/t102xrdb/cpld.c | 103 - board/freescale/t102xrdb/cpld.h | 47 - board/freescale/t102xrdb/ddr.c | 258 --- board/freescale/t102xrdb/eth_t102xrdb.c | 149 -- board/freescale/t102xrdb/law.c | 31 - board/freescale/t102xrdb/spl.c | 132 -- board/freescale/t102xrdb/t1023_nand_rcw.cfg | 8 - board/freescale/t102xrdb/t1023_sd_rcw.cfg | 8 - board/freescale/t102xrdb/t1023_spi_rcw.cfg | 8 - board/freescale/t102xrdb/t1024_nand_rcw.cfg | 8 - board/freescale/t102xrdb/t1024_pbi.cfg | 26 - board/freescale/t102xrdb/t1024_sd_rcw.cfg | 8 - board/freescale/t102xrdb/t1024_spi_rcw.cfg | 8 - board/freescale/t102xrdb/t102xrdb.c | 397 ---- board/freescale/t102xrdb/t102xrdb.h | 15 - board/freescale/t102xrdb/tlb.c | 117 -- board/freescale/t104xrdb/Kconfig | 12 - board/freescale/t104xrdb/MAINTAINERS | 26 - board/freescale/t104xrdb/Makefile | 14 - board/freescale/t104xrdb/README | 386 ---- board/freescale/t104xrdb/cpld.c | 116 -- board/freescale/t104xrdb/cpld.h | 45 - board/freescale/t104xrdb/ddr.c | 148 -- board/freescale/t104xrdb/ddr.h | 56 - board/freescale/t104xrdb/eth.c | 91 - board/freescale/t104xrdb/law.c | 31 - board/freescale/t104xrdb/spl.c | 131 -- board/freescale/t104xrdb/t1040_nand_rcw.cfg | 7 - board/freescale/t104xrdb/t1040_sd_rcw.cfg | 7 - board/freescale/t104xrdb/t1040_spi_rcw.cfg | 7 - board/freescale/t104xrdb/t1040d4_nand_rcw.cfg | 7 - board/freescale/t104xrdb/t1040d4_sd_rcw.cfg | 7 - board/freescale/t104xrdb/t1040d4_spi_rcw.cfg | 7 - board/freescale/t104xrdb/t1042_nand_rcw.cfg | 7 - board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg | 7 - board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg | 7 - board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg | 7 - board/freescale/t104xrdb/t1042_sd_rcw.cfg | 7 - board/freescale/t104xrdb/t1042_spi_rcw.cfg | 7 - board/freescale/t104xrdb/t1042d4_nand_rcw.cfg | 7 - board/freescale/t104xrdb/t1042d4_sd_rcw.cfg | 7 - board/freescale/t104xrdb/t1042d4_spi_rcw.cfg | 7 - board/freescale/t104xrdb/t104x_pbi.cfg | 36 - board/freescale/t104xrdb/t104x_pbi_sb.cfg | 38 - board/freescale/t104xrdb/t104xrdb.c | 159 -- board/freescale/t104xrdb/t104xrdb.h | 12 - board/freescale/t104xrdb/tlb.c | 132 -- board/freescale/t208xqds/Kconfig | 15 - board/freescale/t208xqds/MAINTAINERS | 20 - board/freescale/t208xqds/Makefile | 15 - board/freescale/t208xqds/README | 292 --- board/freescale/t208xqds/ddr.c | 125 -- board/freescale/t208xqds/ddr.h | 70 - board/freescale/t208xqds/eth_t208xqds.c | 723 ------- board/freescale/t208xqds/law.c | 33 - board/freescale/t208xqds/spl.c | 141 -- board/freescale/t208xqds/t2080_nand_rcw.cfg | 16 - board/freescale/t208xqds/t2080_sd_rcw.cfg | 16 - board/freescale/t208xqds/t2080_spi_rcw.cfg | 16 - board/freescale/t208xqds/t2081_nand_rcw.cfg | 8 - board/freescale/t208xqds/t2081_sd_rcw.cfg | 8 - board/freescale/t208xqds/t2081_spi_rcw.cfg | 8 - board/freescale/t208xqds/t208x_pbi.cfg | 40 - board/freescale/t208xqds/t208xqds.c | 426 ---- board/freescale/t208xqds/t208xqds.h | 12 - board/freescale/t208xqds/t208xqds_qixis.h | 47 - board/freescale/t208xqds/tlb.c | 152 -- board/freescale/t208xrdb/Kconfig | 15 - board/freescale/t208xrdb/MAINTAINERS | 14 - board/freescale/t208xrdb/Makefile | 15 - board/freescale/t208xrdb/README | 288 --- board/freescale/t208xrdb/cpld.c | 72 - board/freescale/t208xrdb/cpld.h | 48 - board/freescale/t208xrdb/ddr.c | 118 -- board/freescale/t208xrdb/ddr.h | 46 - board/freescale/t208xrdb/eth_t208xrdb.c | 100 - board/freescale/t208xrdb/law.c | 33 - board/freescale/t208xrdb/spl.c | 101 - board/freescale/t208xrdb/t2080_nand_rcw.cfg | 19 - board/freescale/t208xrdb/t2080_pbi.cfg | 40 - board/freescale/t208xrdb/t2080_sd_rcw.cfg | 19 - board/freescale/t208xrdb/t2080_spi_rcw.cfg | 19 - board/freescale/t208xrdb/t208xrdb.c | 188 -- board/freescale/t208xrdb/t208xrdb.h | 18 - board/freescale/t208xrdb/tlb.c | 152 -- board/freescale/t4rdb/Kconfig | 12 - board/freescale/t4rdb/MAINTAINERS | 7 - board/freescale/t4rdb/Makefile | 17 - board/freescale/t4rdb/cpld.c | 130 -- board/freescale/t4rdb/cpld.h | 47 - board/freescale/t4rdb/ddr.c | 126 -- board/freescale/t4rdb/ddr.h | 76 - board/freescale/t4rdb/eth.c | 152 -- board/freescale/t4rdb/law.c | 30 - board/freescale/t4rdb/spl.c | 88 - board/freescale/t4rdb/t4240rdb.c | 183 -- board/freescale/t4rdb/t4_pbi.cfg | 27 - board/freescale/t4rdb/t4_sd_rcw.cfg | 7 - board/freescale/t4rdb/t4rdb.h | 20 - board/freescale/t4rdb/tlb.c | 124 -- board/freescale/vf610twr/Kconfig | 15 - board/freescale/vf610twr/MAINTAINERS | 7 - board/freescale/vf610twr/Makefile | 5 - board/freescale/vf610twr/imximage.cfg | 16 - board/freescale/vf610twr/vf610twr.c | 386 ---- board/ge/mx53ppd/Makefile | 2 +- board/ge/mx53ppd/imximage.cfg | 2 +- board/ge/mx53ppd/mx53ppd.c | 2 +- board/ge/mx53ppd/mx53ppd_video.c | 2 +- board/k+p/kp_imx53/Kconfig | 2 +- board/keymile/pg-wcom-ls102xa/Makefile | 6 +- board/nxp/common/Makefile | 83 + board/nxp/common/arm_sleep.c | 130 ++ board/nxp/common/cadmus.c | 74 + board/nxp/common/cadmus.h | 33 + board/nxp/common/cds_pci_ft.c | 17 + board/nxp/common/cds_via.c | 95 + board/nxp/common/cmd_esbc_validate.c | 86 + board/nxp/common/eeprom.h | 30 + board/nxp/common/emc2305.c | 61 + board/nxp/common/emc2305.h | 22 + board/nxp/common/fman.c | 88 + board/nxp/common/fman.h | 14 + board/nxp/common/fsl_chain_of_trust.c | 160 ++ board/nxp/common/fsl_validate.c | 973 ++++++++++ board/nxp/common/i2c_common.c | 34 + board/nxp/common/i2c_common.h | 30 + board/nxp/common/i2c_mux.c | 41 + board/nxp/common/i2c_mux.h | 15 + board/nxp/common/ics307_clk.c | 149 ++ board/nxp/common/ics307_clk.h | 14 + board/nxp/common/ls102xa_stream_id.c | 35 + board/nxp/common/mc34vr500.c | 94 + board/nxp/common/mmc.c | 49 + board/nxp/common/mpc85xx_sleep.c | 97 + board/nxp/common/ngpixis.c | 247 +++ board/nxp/common/ngpixis.h | 60 + board/nxp/common/ns_access.c | 241 +++ board/nxp/common/p_corenet/Makefile | 7 + board/nxp/common/p_corenet/law.c | 36 + board/nxp/common/p_corenet/tlb.c | 161 ++ board/nxp/common/pfuze.c | 172 ++ board/nxp/common/pfuze.h | 17 + board/nxp/common/qixis.c | 389 ++++ board/nxp/common/qixis.h | 190 ++ board/nxp/common/sdhc_boot.c | 78 + board/nxp/common/sgmii_riser.h | 16 + board/nxp/common/sleep.h | 20 + board/nxp/common/spl.h | 12 + board/nxp/common/sys_eeprom.c | 648 +++++++ board/nxp/common/via.h | 18 + board/nxp/common/vid.c | 797 ++++++++ board/nxp/common/vid.h | 75 + board/nxp/common/vsc3316_3308.h | 23 + board/nxp/imx8mm_evk/Kconfig | 15 + board/nxp/imx8mm_evk/MAINTAINERS | 7 + board/nxp/imx8mm_evk/Makefile | 12 + board/nxp/imx8mm_evk/imx8mm_evk.c | 93 + board/nxp/imx8mm_evk/imx8mm_evk.env | 67 + board/nxp/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg | 7 + board/nxp/imx8mm_evk/imximage-8mm-lpddr4.cfg | 8 + board/nxp/imx8mm_evk/lpddr4_timing.c | 1848 ++++++++++++++++++ board/nxp/imx8mm_evk/spl.c | 143 ++ board/nxp/imx8mn_evk/Kconfig | 18 + board/nxp/imx8mn_evk/MAINTAINERS | 7 + board/nxp/imx8mn_evk/Makefile | 18 + board/nxp/imx8mn_evk/ddr4_timing.c | 1053 ++++++++++ board/nxp/imx8mn_evk/ddr4_timing_ld.c | 1054 ++++++++++ board/nxp/imx8mn_evk/imx8mn_evk.c | 65 + board/nxp/imx8mn_evk/imx8mn_evk.env | 67 + board/nxp/imx8mn_evk/imximage-8mn-ddr4.cfg | 9 + board/nxp/imx8mn_evk/lpddr4_timing.c | 1587 +++++++++++++++ board/nxp/imx8mn_evk/lpddr4_timing_ld.c | 1440 ++++++++++++++ board/nxp/imx8mn_evk/spl.c | 137 ++ board/nxp/imx8mp_evk/Kconfig | 15 + board/nxp/imx8mp_evk/MAINTAINERS | 7 + board/nxp/imx8mp_evk/Makefile | 12 + board/nxp/imx8mp_evk/imx8mp_evk.c | 43 + board/nxp/imx8mp_evk/imx8mp_evk.env | 58 + board/nxp/imx8mp_evk/imximage-8mp-lpddr4.cfg | 9 + board/nxp/imx8mp_evk/lpddr4_timing.c | 2048 ++++++++++++++++++++ board/nxp/imx8mp_evk/spl.c | 145 ++ board/nxp/imx8mq_evk/Kconfig | 15 + board/nxp/imx8mq_evk/MAINTAINERS | 7 + board/nxp/imx8mq_evk/Makefile | 12 + board/nxp/imx8mq_evk/imx8mq_evk.c | 84 + board/nxp/imx8mq_evk/imx8mq_evk.env | 60 + board/nxp/imx8mq_evk/lpddr4_timing.c | 1323 +++++++++++++ board/nxp/imx8mq_evk/lpddr4_timing_b0.c | 1190 ++++++++++++ board/nxp/imx8mq_evk/spl.c | 256 +++ board/nxp/imx8qm_mek/Kconfig | 15 + board/nxp/imx8qm_mek/MAINTAINERS | 6 + board/nxp/imx8qm_mek/Makefile | 8 + board/nxp/imx8qm_mek/README | 54 + board/nxp/imx8qm_mek/imx8qm_mek.c | 137 ++ board/nxp/imx8qm_mek/imximage.cfg | 18 + board/nxp/imx8qm_mek/spl.c | 71 + board/nxp/imx8qm_mek/uboot-container.cfg | 12 + board/nxp/imx8qxp_mek/Kconfig | 15 + board/nxp/imx8qxp_mek/MAINTAINERS | 7 + board/nxp/imx8qxp_mek/Makefile | 8 + board/nxp/imx8qxp_mek/imx8qxp_mek.c | 161 ++ board/nxp/imx8qxp_mek/imximage.cfg | 20 + board/nxp/imx8qxp_mek/spl.c | 89 + board/nxp/imx8qxp_mek/uboot-container.cfg | 12 + board/nxp/imx8ulp_evk/Kconfig | 12 + board/nxp/imx8ulp_evk/MAINTAINERS | 6 + board/nxp/imx8ulp_evk/Makefile | 12 + board/nxp/imx8ulp_evk/imx8ulp_evk.c | 136 ++ board/nxp/imx8ulp_evk/imx8ulp_evk.env | 97 + board/nxp/imx8ulp_evk/lpddr4_timing.c | 1158 +++++++++++ board/nxp/imx8ulp_evk/lpddr4_timing_266.c | 1109 +++++++++++ board/nxp/imx8ulp_evk/spl.c | 148 ++ board/nxp/imx91_evk/Kconfig | 19 + board/nxp/imx91_evk/MAINTAINERS | 7 + board/nxp/imx91_evk/Makefile | 16 + board/nxp/imx91_evk/imx91_evk.c | 26 + board/nxp/imx91_evk/imx91_evk.env | 88 + board/nxp/imx91_evk/lpddr4_timing_1600mts.c | 1995 +++++++++++++++++++ board/nxp/imx91_evk/lpddr4_timing_1600mts_ecc.c | 1995 +++++++++++++++++++ board/nxp/imx91_evk/lpddr4_timing_2400mts.c | 1995 +++++++++++++++++++ board/nxp/imx91_evk/lpddr4_timing_2400mts_ecc.c | 1995 +++++++++++++++++++ board/nxp/imx91_evk/spl.c | 151 ++ board/nxp/imx91_frdm/Kconfig | 12 + board/nxp/imx91_frdm/MAINTAINERS | 7 + board/nxp/imx91_frdm/Makefile | 16 + board/nxp/imx91_frdm/imx91_frdm.c | 84 + board/nxp/imx91_frdm/imx91_frdm.env | 89 + board/nxp/imx91_frdm/lpddr4_2400mts_1gb_timing.c | 1996 +++++++++++++++++++ board/nxp/imx91_frdm/lpddr4_2400mts_2gb_timing.c | 1996 +++++++++++++++++++ .../nxp/imx91_frdm/lpddr4_2400mts_ecc_1gb_timing.c | 1996 +++++++++++++++++++ .../nxp/imx91_frdm/lpddr4_2400mts_ecc_2gb_timing.c | 1996 +++++++++++++++++++ board/nxp/imx91_frdm/lpddr4_timing.h | 12 + board/nxp/imx91_frdm/spl.c | 193 ++ board/nxp/imx93_evk/Kconfig | 19 + board/nxp/imx93_evk/MAINTAINERS | 7 + board/nxp/imx93_evk/Makefile | 12 + board/nxp/imx93_evk/imx93_evk.c | 42 + board/nxp/imx93_evk/imx93_evk.env | 89 + board/nxp/imx93_evk/lpddr4x_timing.c | 1994 +++++++++++++++++++ board/nxp/imx93_evk/lpddr4x_timing_1866mts.c | 1995 +++++++++++++++++++ board/nxp/imx93_evk/spl.c | 157 ++ board/nxp/imx93_frdm/Kconfig | 12 + board/nxp/imx93_frdm/MAINTAINERS | 6 + board/nxp/imx93_frdm/Makefile | 11 + board/nxp/imx93_frdm/imx93_frdm.c | 124 ++ board/nxp/imx93_frdm/imx93_frdm.env | 39 + board/nxp/imx93_frdm/lpddr4_timing.h | 12 + board/nxp/imx93_frdm/lpddr4x_1gb_timing.c | 1996 +++++++++++++++++++ board/nxp/imx93_frdm/lpddr4x_2gb_timing.c | 1995 +++++++++++++++++++ board/nxp/imx93_frdm/spl.c | 195 ++ board/nxp/imx93_qsb/Kconfig | 12 + board/nxp/imx93_qsb/MAINTAINERS | 7 + board/nxp/imx93_qsb/Makefile | 16 + board/nxp/imx93_qsb/imx93_qsb.c | 26 + board/nxp/imx93_qsb/imx93_qsb.env | 88 + board/nxp/imx93_qsb/lpddr4_timing.c | 1995 +++++++++++++++++++ board/nxp/imx93_qsb/lpddr4_timing_ecc.c | 1995 +++++++++++++++++++ board/nxp/imx93_qsb/spl.c | 159 ++ board/nxp/imx94_evk/Kconfig | 12 + board/nxp/imx94_evk/MAINTAINERS | 6 + board/nxp/imx94_evk/Makefile | 11 + board/nxp/imx94_evk/imx94_evk.c | 41 + board/nxp/imx94_evk/imx94_evk.env | 100 + board/nxp/imx94_evk/spl.c | 82 + board/nxp/imx95_evk/Kconfig | 12 + board/nxp/imx95_evk/MAINTAINERS | 8 + board/nxp/imx95_evk/Makefile | 11 + board/nxp/imx95_evk/imx95_evk.c | 31 + board/nxp/imx95_evk/imx95_evk.env | 91 + board/nxp/imx95_evk/spl.c | 80 + board/nxp/imxrt1020-evk/Kconfig | 18 + board/nxp/imxrt1020-evk/MAINTAINERS | 6 + board/nxp/imxrt1020-evk/Makefile | 6 + board/nxp/imxrt1020-evk/imximage.cfg | 35 + board/nxp/imxrt1020-evk/imxrt1020-evk.c | 79 + board/nxp/imxrt1050-evk/Kconfig | 18 + board/nxp/imxrt1050-evk/MAINTAINERS | 7 + board/nxp/imxrt1050-evk/Makefile | 6 + board/nxp/imxrt1050-evk/imximage-nor.cfg | 41 + board/nxp/imxrt1050-evk/imximage.cfg | 41 + board/nxp/imxrt1050-evk/imxrt1050-evk-nor.env | 13 + board/nxp/imxrt1050-evk/imxrt1050-evk.c | 84 + board/nxp/imxrt1050-evk/imxrt1050-evk.env | 13 + board/nxp/imxrt1170-evk/Kconfig | 18 + board/nxp/imxrt1170-evk/MAINTAINERS | 7 + board/nxp/imxrt1170-evk/Makefile | 6 + board/nxp/imxrt1170-evk/imximage.cfg | 31 + board/nxp/imxrt1170-evk/imxrt1170-evk.c | 79 + board/nxp/ls1012afrdm/Kconfig | 80 + board/nxp/ls1012afrdm/MAINTAINERS | 17 + board/nxp/ls1012afrdm/Makefile | 8 + board/nxp/ls1012afrdm/README | 58 + board/nxp/ls1012afrdm/eth.c | 124 ++ board/nxp/ls1012afrdm/ls1012afrdm.c | 188 ++ board/nxp/ls1012aqds/Kconfig | 72 + board/nxp/ls1012aqds/MAINTAINERS | 8 + board/nxp/ls1012aqds/Makefile | 8 + board/nxp/ls1012aqds/README | 59 + board/nxp/ls1012aqds/eth.c | 309 +++ board/nxp/ls1012aqds/ls1012aqds.c | 287 +++ board/nxp/ls1012aqds/ls1012aqds_pfe.h | 44 + board/nxp/ls1012aqds/ls1012aqds_qixis.h | 34 + board/nxp/ls1012ardb/Kconfig | 108 ++ board/nxp/ls1012ardb/MAINTAINERS | 17 + board/nxp/ls1012ardb/Makefile | 8 + board/nxp/ls1012ardb/README | 97 + board/nxp/ls1012ardb/eth.c | 171 ++ board/nxp/ls1012ardb/ls1012ardb.c | 411 ++++ board/nxp/ls1021aiot/Kconfig | 15 + board/nxp/ls1021aiot/MAINTAINERS | 7 + board/nxp/ls1021aiot/Makefile | 6 + board/nxp/ls1021aiot/README | 58 + board/nxp/ls1021aiot/ls1021aiot.c | 207 ++ board/nxp/ls1021aiot/ls102xa_pbi.cfg | 14 + board/nxp/ls1021aiot/ls102xa_rcw_sd.cfg | 27 + board/nxp/ls1021aiot/psci.S | 27 + board/nxp/ls1021aqds/Kconfig | 15 + board/nxp/ls1021aqds/MAINTAINERS | 14 + board/nxp/ls1021aqds/Makefile | 9 + board/nxp/ls1021aqds/README | 117 ++ board/nxp/ls1021aqds/ddr.c | 199 ++ board/nxp/ls1021aqds/ddr.h | 61 + board/nxp/ls1021aqds/ls1021aqds.c | 456 +++++ board/nxp/ls1021aqds/ls1021aqds_qixis.h | 36 + board/nxp/ls1021aqds/ls102xa_pbi.cfg | 12 + board/nxp/ls1021aqds/ls102xa_rcw_nand.cfg | 7 + board/nxp/ls1021aqds/ls102xa_rcw_sd_ifc.cfg | 14 + board/nxp/ls1021aqds/ls102xa_rcw_sd_qspi.cfg | 14 + board/nxp/ls1021aqds/psci.S | 32 + board/nxp/ls1021atsn/Kconfig | 16 + board/nxp/ls1021atsn/MAINTAINERS | 8 + board/nxp/ls1021atsn/Makefile | 3 + board/nxp/ls1021atsn/README.rst | 97 + board/nxp/ls1021atsn/ls1021atsn.c | 264 +++ board/nxp/ls1021atsn/ls102xa_pbi.cfg | 15 + board/nxp/ls1021atsn/ls102xa_rcw_sd.cfg | 8 + board/nxp/ls1021atwr/Kconfig | 15 + board/nxp/ls1021atwr/MAINTAINERS | 12 + board/nxp/ls1021atwr/Makefile | 8 + board/nxp/ls1021atwr/README | 114 ++ board/nxp/ls1021atwr/ls1021atwr.c | 753 +++++++ board/nxp/ls1021atwr/ls102xa_pbi.cfg | 12 + board/nxp/ls1021atwr/ls102xa_rcw_sd_ifc.cfg | 8 + board/nxp/ls1021atwr/ls102xa_rcw_sd_qspi.cfg | 8 + board/nxp/ls1021atwr/psci.S | 24 + board/nxp/ls1028a/Kconfig | 47 + board/nxp/ls1028a/MAINTAINERS | 26 + board/nxp/ls1028a/Makefile | 8 + board/nxp/ls1028a/README | 164 ++ board/nxp/ls1028a/ddr.c | 20 + board/nxp/ls1028a/ls1028a.c | 329 ++++ board/nxp/ls1043aqds/Kconfig | 15 + board/nxp/ls1043aqds/MAINTAINERS | 14 + board/nxp/ls1043aqds/Makefile | 11 + board/nxp/ls1043aqds/README | 64 + board/nxp/ls1043aqds/ddr.c | 145 ++ board/nxp/ls1043aqds/ddr.h | 61 + board/nxp/ls1043aqds/eth.c | 501 +++++ board/nxp/ls1043aqds/ls1043aqds.c | 595 ++++++ board/nxp/ls1043aqds/ls1043aqds_pbi.cfg | 14 + board/nxp/ls1043aqds/ls1043aqds_qixis.h | 38 + board/nxp/ls1043aqds/ls1043aqds_rcw_nand.cfg | 7 + board/nxp/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg | 8 + board/nxp/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg | 8 + board/nxp/ls1043ardb/Kconfig | 16 + board/nxp/ls1043ardb/MAINTAINERS | 13 + board/nxp/ls1043ardb/Makefile | 10 + board/nxp/ls1043ardb/README | 54 + board/nxp/ls1043ardb/cpld.c | 178 ++ board/nxp/ls1043ardb/cpld.h | 46 + board/nxp/ls1043ardb/ddr.c | 254 +++ board/nxp/ls1043ardb/ddr.h | 116 ++ board/nxp/ls1043ardb/eth.c | 77 + board/nxp/ls1043ardb/ls1043ardb.c | 415 ++++ board/nxp/ls1043ardb/ls1043ardb_pbi.cfg | 14 + board/nxp/ls1043ardb/ls1043ardb_rcw_nand.cfg | 7 + board/nxp/ls1043ardb/ls1043ardb_rcw_sd.cfg | 7 + board/nxp/ls1046afrwy/Kconfig | 16 + board/nxp/ls1046afrwy/MAINTAINERS | 8 + board/nxp/ls1046afrwy/Makefile | 7 + board/nxp/ls1046afrwy/README | 76 + board/nxp/ls1046afrwy/ddr.c | 19 + board/nxp/ls1046afrwy/eth.c | 118 ++ board/nxp/ls1046afrwy/ls1046afrwy.c | 218 +++ board/nxp/ls1046aqds/Kconfig | 15 + board/nxp/ls1046aqds/MAINTAINERS | 14 + board/nxp/ls1046aqds/Makefile | 11 + board/nxp/ls1046aqds/README | 70 + board/nxp/ls1046aqds/ddr.c | 130 ++ board/nxp/ls1046aqds/ddr.h | 43 + board/nxp/ls1046aqds/eth.c | 431 ++++ board/nxp/ls1046aqds/ls1046aqds.c | 479 +++++ board/nxp/ls1046aqds/ls1046aqds_pbi.cfg | 17 + board/nxp/ls1046aqds/ls1046aqds_qixis.h | 38 + board/nxp/ls1046aqds/ls1046aqds_rcw_nand.cfg | 7 + board/nxp/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg | 8 + board/nxp/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg | 8 + board/nxp/ls1046ardb/Kconfig | 16 + board/nxp/ls1046ardb/MAINTAINERS | 16 + board/nxp/ls1046ardb/Makefile | 10 + board/nxp/ls1046ardb/cpld.c | 167 ++ board/nxp/ls1046ardb/cpld.h | 49 + board/nxp/ls1046ardb/ddr.c | 132 ++ board/nxp/ls1046ardb/ddr.h | 62 + board/nxp/ls1046ardb/eth.c | 129 ++ board/nxp/ls1046ardb/ls1046ardb.c | 192 ++ board/nxp/ls1046ardb/ls1046ardb_pbi.cfg | 22 + board/nxp/ls1046ardb/ls1046ardb_qspi_pbi.cfg | 26 + board/nxp/ls1046ardb/ls1046ardb_rcw_emmc.cfg | 7 + board/nxp/ls1046ardb/ls1046ardb_rcw_qspi.cfg | 7 + board/nxp/ls1046ardb/ls1046ardb_rcw_sd.cfg | 7 + board/nxp/ls1088a/Kconfig | 31 + board/nxp/ls1088a/MAINTAINERS | 35 + board/nxp/ls1088a/Makefile | 10 + board/nxp/ls1088a/README | 145 ++ board/nxp/ls1088a/ddr.c | 134 ++ board/nxp/ls1088a/ddr.h | 48 + board/nxp/ls1088a/eth_ls1088aqds.c | 105 + board/nxp/ls1088a/eth_ls1088ardb.c | 13 + board/nxp/ls1088a/ls1088a.c | 1041 ++++++++++ board/nxp/ls1088a/ls1088a_qixis.h | 55 + board/nxp/ls2080aqds/Kconfig | 16 + board/nxp/ls2080aqds/MAINTAINERS | 13 + board/nxp/ls2080aqds/Makefile | 7 + board/nxp/ls2080aqds/README | 215 ++ board/nxp/ls2080aqds/ddr.c | 181 ++ board/nxp/ls2080aqds/ddr.h | 90 + board/nxp/ls2080aqds/eth.c | 117 ++ board/nxp/ls2080aqds/ls2080aqds.c | 349 ++++ board/nxp/ls2080aqds/ls2080aqds_qixis.h | 29 + board/nxp/ls2080ardb/Kconfig | 15 + board/nxp/ls2080ardb/MAINTAINERS | 32 + board/nxp/ls2080ardb/Makefile | 6 + board/nxp/ls2080ardb/README | 134 ++ board/nxp/ls2080ardb/ddr.c | 186 ++ board/nxp/ls2080ardb/ddr.h | 75 + board/nxp/ls2080ardb/eth_ls2080rdb.c | 36 + board/nxp/ls2080ardb/ls2080ardb.c | 571 ++++++ board/nxp/ls2080ardb/ls2080ardb_qixis.h | 19 + board/nxp/lx2160a/Kconfig | 47 + board/nxp/lx2160a/MAINTAINERS | 55 + board/nxp/lx2160a/Makefile | 11 + board/nxp/lx2160a/README | 329 ++++ board/nxp/lx2160a/ddr.c | 20 + board/nxp/lx2160a/eth_lx2160aqds.c | 148 ++ board/nxp/lx2160a/eth_lx2160ardb.c | 144 ++ board/nxp/lx2160a/eth_lx2162aqds.c | 143 ++ board/nxp/lx2160a/lx2160a.c | 864 +++++++++ board/nxp/lx2160a/lx2160a.h | 76 + board/nxp/m5208evbe/Kconfig | 15 + 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create mode 100644 board/nxp/p1010rdb/README.P1010RDB-PB create mode 100644 board/nxp/p1010rdb/ddr.c create mode 100644 board/nxp/p1010rdb/law.c create mode 100644 board/nxp/p1010rdb/p1010rdb.c create mode 100644 board/nxp/p1010rdb/spl.c create mode 100644 board/nxp/p1010rdb/spl_minimal.c create mode 100644 board/nxp/p1010rdb/tlb.c create mode 100644 board/nxp/p1_p2_rdb_pc/Kconfig create mode 100644 board/nxp/p1_p2_rdb_pc/MAINTAINERS create mode 100644 board/nxp/p1_p2_rdb_pc/Makefile create mode 100644 board/nxp/p1_p2_rdb_pc/README create mode 100644 board/nxp/p1_p2_rdb_pc/ddr.c create mode 100644 board/nxp/p1_p2_rdb_pc/law.c create mode 100644 board/nxp/p1_p2_rdb_pc/p1_p2_rdb_pc.c create mode 100644 board/nxp/p1_p2_rdb_pc/spl.c create mode 100644 board/nxp/p1_p2_rdb_pc/spl_minimal.c create mode 100644 board/nxp/p1_p2_rdb_pc/tlb.c create mode 100644 board/nxp/p2041rdb/Kconfig create mode 100644 board/nxp/p2041rdb/MAINTAINERS create mode 100644 board/nxp/p2041rdb/Makefile create mode 100644 board/nxp/p2041rdb/README create mode 100644 board/nxp/p2041rdb/cpld.c create mode 100644 board/nxp/p2041rdb/cpld.h create mode 100644 board/nxp/p2041rdb/ddr.c create mode 100644 board/nxp/p2041rdb/eth.c create mode 100644 board/nxp/p2041rdb/p2041rdb.c create mode 100644 board/nxp/p2041rdb/pbi.cfg create mode 100644 board/nxp/p2041rdb/rcw_p2041rdb.cfg create mode 100644 board/nxp/t102xrdb/Kconfig create mode 100644 board/nxp/t102xrdb/MAINTAINERS create mode 100644 board/nxp/t102xrdb/Makefile create mode 100644 board/nxp/t102xrdb/README create mode 100644 board/nxp/t102xrdb/cpld.c create mode 100644 board/nxp/t102xrdb/cpld.h create mode 100644 board/nxp/t102xrdb/ddr.c create mode 100644 board/nxp/t102xrdb/eth_t102xrdb.c create mode 100644 board/nxp/t102xrdb/law.c create mode 100644 board/nxp/t102xrdb/spl.c create mode 100644 board/nxp/t102xrdb/t1023_nand_rcw.cfg create mode 100644 board/nxp/t102xrdb/t1023_sd_rcw.cfg create mode 100644 board/nxp/t102xrdb/t1023_spi_rcw.cfg create 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board/nxp/t104xrdb/t1040_spi_rcw.cfg create mode 100644 board/nxp/t104xrdb/t1040d4_nand_rcw.cfg create mode 100644 board/nxp/t104xrdb/t1040d4_sd_rcw.cfg create mode 100644 board/nxp/t104xrdb/t1040d4_spi_rcw.cfg create mode 100644 board/nxp/t104xrdb/t1042_nand_rcw.cfg create mode 100644 board/nxp/t104xrdb/t1042_pi_nand_rcw.cfg create mode 100644 board/nxp/t104xrdb/t1042_pi_sd_rcw.cfg create mode 100644 board/nxp/t104xrdb/t1042_pi_spi_rcw.cfg create mode 100644 board/nxp/t104xrdb/t1042_sd_rcw.cfg create mode 100644 board/nxp/t104xrdb/t1042_spi_rcw.cfg create mode 100644 board/nxp/t104xrdb/t1042d4_nand_rcw.cfg create mode 100644 board/nxp/t104xrdb/t1042d4_sd_rcw.cfg create mode 100644 board/nxp/t104xrdb/t1042d4_spi_rcw.cfg create mode 100644 board/nxp/t104xrdb/t104x_pbi.cfg create mode 100644 board/nxp/t104xrdb/t104x_pbi_sb.cfg create mode 100644 board/nxp/t104xrdb/t104xrdb.c create mode 100644 board/nxp/t104xrdb/t104xrdb.h create mode 100644 board/nxp/t104xrdb/tlb.c create mode 100644 board/nxp/t208xqds/Kconfig create mode 100644 board/nxp/t208xqds/MAINTAINERS create mode 100644 board/nxp/t208xqds/Makefile create mode 100644 board/nxp/t208xqds/README create mode 100644 board/nxp/t208xqds/ddr.c create mode 100644 board/nxp/t208xqds/ddr.h create mode 100644 board/nxp/t208xqds/eth_t208xqds.c create mode 100644 board/nxp/t208xqds/law.c create mode 100644 board/nxp/t208xqds/spl.c create mode 100644 board/nxp/t208xqds/t2080_nand_rcw.cfg create mode 100644 board/nxp/t208xqds/t2080_sd_rcw.cfg create mode 100644 board/nxp/t208xqds/t2080_spi_rcw.cfg create mode 100644 board/nxp/t208xqds/t2081_nand_rcw.cfg create mode 100644 board/nxp/t208xqds/t2081_sd_rcw.cfg create mode 100644 board/nxp/t208xqds/t2081_spi_rcw.cfg create mode 100644 board/nxp/t208xqds/t208x_pbi.cfg create mode 100644 board/nxp/t208xqds/t208xqds.c create mode 100644 board/nxp/t208xqds/t208xqds.h create mode 100644 board/nxp/t208xqds/t208xqds_qixis.h create mode 100644 board/nxp/t208xqds/tlb.c create mode 100644 board/nxp/t208xrdb/Kconfig create mode 100644 board/nxp/t208xrdb/MAINTAINERS create mode 100644 board/nxp/t208xrdb/Makefile create mode 100644 board/nxp/t208xrdb/README create mode 100644 board/nxp/t208xrdb/cpld.c create mode 100644 board/nxp/t208xrdb/cpld.h create mode 100644 board/nxp/t208xrdb/ddr.c create mode 100644 board/nxp/t208xrdb/ddr.h create mode 100644 board/nxp/t208xrdb/eth_t208xrdb.c create mode 100644 board/nxp/t208xrdb/law.c create mode 100644 board/nxp/t208xrdb/spl.c create mode 100644 board/nxp/t208xrdb/t2080_nand_rcw.cfg create mode 100644 board/nxp/t208xrdb/t2080_pbi.cfg create mode 100644 board/nxp/t208xrdb/t2080_sd_rcw.cfg create mode 100644 board/nxp/t208xrdb/t2080_spi_rcw.cfg create mode 100644 board/nxp/t208xrdb/t208xrdb.c create mode 100644 board/nxp/t208xrdb/t208xrdb.h create mode 100644 board/nxp/t208xrdb/tlb.c create mode 100644 board/nxp/t4rdb/Kconfig create mode 100644 board/nxp/t4rdb/MAINTAINERS create mode 100644 board/nxp/t4rdb/Makefile create mode 100644 board/nxp/t4rdb/cpld.c create mode 100644 board/nxp/t4rdb/cpld.h create mode 100644 board/nxp/t4rdb/ddr.c create mode 100644 board/nxp/t4rdb/ddr.h create mode 100644 board/nxp/t4rdb/eth.c create mode 100644 board/nxp/t4rdb/law.c create mode 100644 board/nxp/t4rdb/spl.c create mode 100644 board/nxp/t4rdb/t4240rdb.c create mode 100644 board/nxp/t4rdb/t4_pbi.cfg create mode 100644 board/nxp/t4rdb/t4_sd_rcw.cfg create mode 100644 board/nxp/t4rdb/t4rdb.h create mode 100644 board/nxp/t4rdb/tlb.c create mode 100644 board/nxp/vf610twr/Kconfig create mode 100644 board/nxp/vf610twr/MAINTAINERS create mode 100644 board/nxp/vf610twr/Makefile create mode 100644 board/nxp/vf610twr/imximage.cfg create mode 100644 board/nxp/vf610twr/vf610twr.c diff --git a/MAINTAINERS b/MAINTAINERS index 218b1fa5ff4..a0f87da67e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -315,8 +315,8 @@ F: arch/arm/include/asm/arch-imx*/ F: arch/arm/include/asm/arch-mx*/ F: arch/arm/include/asm/arch-vf610/ F: arch/arm/include/asm/mach-imx/ -F: board/freescale/*mx*/ -F: board/freescale/common/ +F: board/nxp/*mx*/ +F: board/nxp/common/ F: common/spl/spl_imx_container.c F: doc/board/nxp/ F: doc/imx/ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ea1a9b4e8c6..e9e9f236b0a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2414,23 +2414,23 @@ source "board/cavium/thunderx/Kconfig" source "board/eets/pdu001/Kconfig" source "board/emulation/qemu-arm/Kconfig" source "board/emulation/qemu-sbsa/Kconfig" -source "board/freescale/ls2080aqds/Kconfig" -source "board/freescale/ls2080ardb/Kconfig" -source "board/freescale/ls1088a/Kconfig" -source "board/freescale/ls1028a/Kconfig" -source "board/freescale/ls1021aqds/Kconfig" -source "board/freescale/ls1043aqds/Kconfig" -source "board/freescale/ls1021atwr/Kconfig" -source "board/freescale/ls1021atsn/Kconfig" -source "board/freescale/ls1021aiot/Kconfig" -source "board/freescale/ls1046aqds/Kconfig" -source "board/freescale/ls1043ardb/Kconfig" -source "board/freescale/ls1046ardb/Kconfig" -source "board/freescale/ls1046afrwy/Kconfig" -source "board/freescale/ls1012aqds/Kconfig" -source "board/freescale/ls1012ardb/Kconfig" -source "board/freescale/ls1012afrdm/Kconfig" -source "board/freescale/lx2160a/Kconfig" +source "board/nxp/ls2080aqds/Kconfig" +source "board/nxp/ls2080ardb/Kconfig" +source "board/nxp/ls1088a/Kconfig" +source "board/nxp/ls1028a/Kconfig" +source "board/nxp/ls1021aqds/Kconfig" +source "board/nxp/ls1043aqds/Kconfig" +source "board/nxp/ls1021atwr/Kconfig" +source "board/nxp/ls1021atsn/Kconfig" +source "board/nxp/ls1021aiot/Kconfig" +source "board/nxp/ls1046aqds/Kconfig" +source "board/nxp/ls1043ardb/Kconfig" +source "board/nxp/ls1046ardb/Kconfig" +source "board/nxp/ls1046afrwy/Kconfig" +source "board/nxp/ls1012aqds/Kconfig" +source "board/nxp/ls1012ardb/Kconfig" +source "board/nxp/ls1012afrdm/Kconfig" +source "board/nxp/lx2160a/Kconfig" source "board/grinn/chiliboard/Kconfig" source "board/hisilicon/hikey/Kconfig" source "board/hisilicon/hikey960/Kconfig" diff --git a/arch/arm/cpu/armv7/vf610/Kconfig b/arch/arm/cpu/armv7/vf610/Kconfig index 5d485a3ce24..6689494b488 100644 --- a/arch/arm/cpu/armv7/vf610/Kconfig +++ b/arch/arm/cpu/armv7/vf610/Kconfig @@ -30,7 +30,7 @@ endchoice config SYS_SOC default "vf610" -source "board/freescale/vf610twr/Kconfig" +source "board/nxp/vf610twr/Kconfig" source "board/phytec/pcm052/Kconfig" source "board/toradex/colibri_vf/Kconfig" diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 257c14e61b6..2ca0d7465f4 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -104,8 +104,8 @@ config TARGET_IMX8QXP_MEK endchoice -source "board/freescale/imx8qm_mek/Kconfig" -source "board/freescale/imx8qxp_mek/Kconfig" +source "board/nxp/imx8qm_mek/Kconfig" +source "board/nxp/imx8qxp_mek/Kconfig" source "board/congatec/cgtqmx8/Kconfig" source "board/advantech/imx8qm_dmsse20_a1/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 1dea8a466a6..d25e0910328 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -441,10 +441,10 @@ source "board/dhelectronics/dh_imx8mp/Kconfig" source "board/emcraft/imx8mp_navqp/Kconfig" source "board/engicam/imx8mm/Kconfig" source "board/engicam/imx8mp/Kconfig" -source "board/freescale/imx8mq_evk/Kconfig" -source "board/freescale/imx8mm_evk/Kconfig" -source "board/freescale/imx8mn_evk/Kconfig" -source "board/freescale/imx8mp_evk/Kconfig" +source "board/nxp/imx8mq_evk/Kconfig" +source "board/nxp/imx8mm_evk/Kconfig" +source "board/nxp/imx8mn_evk/Kconfig" +source "board/nxp/imx8mp_evk/Kconfig" source "board/gateworks/venice/Kconfig" source "board/google/imx8mq_phanbell/Kconfig" source "board/kontron/osm-s-mx8mp/Kconfig" diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-imx/imx8ulp/Kconfig index 37a8cefd6cc..aec13d49037 100644 --- a/arch/arm/mach-imx/imx8ulp/Kconfig +++ b/arch/arm/mach-imx/imx8ulp/Kconfig @@ -31,6 +31,6 @@ config TARGET_IMX8ULP_EVK endchoice -source "board/freescale/imx8ulp_evk/Kconfig" +source "board/nxp/imx8ulp_evk/Kconfig" endif diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 65d3ca72e1f..d9f97e4328c 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -155,16 +155,16 @@ config TARGET_TORADEX_SMARC_IMX95 endchoice -source "board/freescale/imx91_evk/Kconfig" -source "board/freescale/imx91_frdm/Kconfig" -source "board/freescale/imx93_evk/Kconfig" -source "board/freescale/imx93_frdm/Kconfig" -source "board/freescale/imx93_qsb/Kconfig" +source "board/nxp/imx91_evk/Kconfig" +source "board/nxp/imx91_frdm/Kconfig" +source "board/nxp/imx93_evk/Kconfig" +source "board/nxp/imx93_frdm/Kconfig" +source "board/nxp/imx93_qsb/Kconfig" source "board/kontron/osm-s-mx93/Kconfig" source "board/phytec/phycore_imx93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" -source "board/freescale/imx94_evk/Kconfig" -source "board/freescale/imx95_evk/Kconfig" +source "board/nxp/imx94_evk/Kconfig" +source "board/nxp/imx95_evk/Kconfig" source "board/toradex/smarc-imx95/Kconfig" endif diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig index ccccf702f67..6bc0de54e8b 100644 --- a/arch/arm/mach-imx/imxrt/Kconfig +++ b/arch/arm/mach-imx/imxrt/Kconfig @@ -38,8 +38,8 @@ config TARGET_IMXRT1170_EVK endchoice -source "board/freescale/imxrt1020-evk/Kconfig" -source "board/freescale/imxrt1050-evk/Kconfig" -source "board/freescale/imxrt1170-evk/Kconfig" +source "board/nxp/imxrt1020-evk/Kconfig" +source "board/nxp/imxrt1050-evk/Kconfig" +source "board/nxp/imxrt1170-evk/Kconfig" endif diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig index 0dfd6849687..6ce27257708 100644 --- a/arch/arm/mach-imx/mx5/Kconfig +++ b/arch/arm/mach-imx/mx5/Kconfig @@ -71,8 +71,8 @@ config SYS_SOC default "mx5" source "board/beckhoff/mx53cx9020/Kconfig" -source "board/freescale/mx51evk/Kconfig" -source "board/freescale/mx53loco/Kconfig" +source "board/nxp/mx51evk/Kconfig" +source "board/nxp/mx53loco/Kconfig" source "board/ge/mx53ppd/Kconfig" source "board/inversepath/usbarmory/Kconfig" source "board/k+p/kp_imx53/Kconfig" diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 3f5e91da204..f64bebfc14b 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -713,15 +713,15 @@ source "board/dhelectronics/dh_imx6/Kconfig" source "board/embest/mx6boards/Kconfig" source "board/engicam/imx6q/Kconfig" source "board/engicam/imx6ul/Kconfig" -source "board/freescale/mx6memcal/Kconfig" -source "board/freescale/mx6sabreauto/Kconfig" -source "board/freescale/mx6sabresd/Kconfig" -source "board/freescale/mx6slevk/Kconfig" -source "board/freescale/mx6sllevk/Kconfig" -source "board/freescale/mx6sxsabresd/Kconfig" -source "board/freescale/mx6sxsabreauto/Kconfig" -source "board/freescale/mx6ul_14x14_evk/Kconfig" -source "board/freescale/mx6ullevk/Kconfig" +source "board/nxp/mx6memcal/Kconfig" +source "board/nxp/mx6sabreauto/Kconfig" +source "board/nxp/mx6sabresd/Kconfig" +source "board/nxp/mx6slevk/Kconfig" +source "board/nxp/mx6sllevk/Kconfig" +source "board/nxp/mx6sxsabresd/Kconfig" +source "board/nxp/mx6sxsabreauto/Kconfig" +source "board/nxp/mx6ul_14x14_evk/Kconfig" +source "board/nxp/mx6ullevk/Kconfig" source "board/bosch/acc/Kconfig" source "board/grinn/liteboard/Kconfig" source "board/phytec/pcm058/Kconfig" diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 4e0e8ed0582..f576ee650f0 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -97,7 +97,7 @@ config SYS_SOC source "board/compulab/cl-som-imx7/Kconfig" source "board/ronetix/imx7-cm/Kconfig" -source "board/freescale/mx7dsabresd/Kconfig" +source "board/nxp/mx7dsabresd/Kconfig" source "board/novtech/meerkat96/Kconfig" source "board/storopack/smegw01/Kconfig" source "board/technexion/pico-imx7d/Kconfig" diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig index 632c4bf6fa5..e8cb58bc89f 100644 --- a/arch/arm/mach-imx/mx7ulp/Kconfig +++ b/arch/arm/mach-imx/mx7ulp/Kconfig @@ -46,6 +46,6 @@ config TARGET_MX7ULP_EVK endchoice source "board/ea/mx7ulp_com/Kconfig" -source "board/freescale/mx7ulp_evk/Kconfig" +source "board/nxp/mx7ulp_evk/Kconfig" endif diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index b134d04b210..204252ed3c6 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -24,7 +24,7 @@ config SYS_SOC default "mxs" source "board/olimex/mx23_olinuxino/Kconfig" -source "board/freescale/mx23evk/Kconfig" +source "board/nxp/mx23evk/Kconfig" endif @@ -74,7 +74,7 @@ config SPL_MXS_PMU_ENABLE_4P2_LINEAR_REGULATOR This option enables the 4P2 linear regulator (derived from VDD5V) - so the VDD4P2 power source is operational. -source "board/freescale/mx28evk/Kconfig" +source "board/nxp/mx28evk/Kconfig" source "board/liebherr/btt/Kconfig" source "board/liebherr/xea/Kconfig" diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 8ade6f7b9d1..f5d495f9935 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -180,16 +180,16 @@ endchoice source "board/BuS/eb_cpu5282/Kconfig" source "board/cobra5272/Kconfig" -source "board/freescale/m5208evbe/Kconfig" -source "board/freescale/m5235evb/Kconfig" -source "board/freescale/m5249evb/Kconfig" -source "board/freescale/m5253demo/Kconfig" -source "board/freescale/m5272c3/Kconfig" -source "board/freescale/m5275evb/Kconfig" -source "board/freescale/m5282evb/Kconfig" -source "board/freescale/m53017evb/Kconfig" -source "board/freescale/m5329evb/Kconfig" -source "board/freescale/m5373evb/Kconfig" +source "board/nxp/m5208evbe/Kconfig" +source "board/nxp/m5235evb/Kconfig" +source "board/nxp/m5249evb/Kconfig" +source "board/nxp/m5253demo/Kconfig" +source "board/nxp/m5272c3/Kconfig" +source "board/nxp/m5275evb/Kconfig" +source "board/nxp/m5282evb/Kconfig" +source "board/nxp/m53017evb/Kconfig" +source "board/nxp/m5329evb/Kconfig" +source "board/nxp/m5373evb/Kconfig" source "board/sysam/amcore/Kconfig" source "board/sysam/stmark2/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 582e1412211..8ac83420ee2 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -207,7 +207,7 @@ config FSL_SERDES config NEVER_ASSERT_ODT_TO_CPU bool "Never assert ODT to internal IOs" -source "board/freescale/mpc837xerdb/Kconfig" +source "board/nxp/mpc837xerdb/Kconfig" source "board/gdsys/mpc8308/Kconfig" source "board/cssi/cmpcpro/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index fd0ef3633b7..c5c2220593f 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1542,15 +1542,15 @@ config FSL_VIA source "board/CZ.NIC/turris_1x/Kconfig" source "board/emulation/qemu-ppce500/Kconfig" -source "board/freescale/mpc8548cds/Kconfig" -source "board/freescale/p1010rdb/Kconfig" -source "board/freescale/p1_p2_rdb_pc/Kconfig" -source "board/freescale/p2041rdb/Kconfig" -source "board/freescale/t102xrdb/Kconfig" -source "board/freescale/t104xrdb/Kconfig" -source "board/freescale/t208xqds/Kconfig" -source "board/freescale/t208xrdb/Kconfig" -source "board/freescale/t4rdb/Kconfig" +source "board/nxp/mpc8548cds/Kconfig" +source "board/nxp/p1010rdb/Kconfig" +source "board/nxp/p1_p2_rdb_pc/Kconfig" +source "board/nxp/p2041rdb/Kconfig" +source "board/nxp/t102xrdb/Kconfig" +source "board/nxp/t104xrdb/Kconfig" +source "board/nxp/t208xqds/Kconfig" +source "board/nxp/t208xrdb/Kconfig" +source "board/nxp/t4rdb/Kconfig" source "board/socrates/Kconfig" endmenu diff --git a/board/CZ.NIC/turris_1x/MAINTAINERS b/board/CZ.NIC/turris_1x/MAINTAINERS index e858c97b962..36e27a57221 100644 --- a/board/CZ.NIC/turris_1x/MAINTAINERS +++ b/board/CZ.NIC/turris_1x/MAINTAINERS @@ -6,8 +6,8 @@ F: arch/powerpc/dts/turris1x.dts F: board/CZ.NIC/turris_1x/ F: board/CZ.NIC/turris_atsha_otp.c F: board/CZ.NIC/turris_atsha_otp.h -F: board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c -F: board/freescale/p1_p2_rdb_pc/spl.c +F: board/nxp/p1_p2_rdb_pc/p1_p2_rdb_pc.c +F: board/nxp/p1_p2_rdb_pc/spl.c F: configs/turris_1x_nor_defconfig F: configs/turris_1x_sdcard_defconfig F: include/configs/turris_1x.h diff --git a/board/CZ.NIC/turris_1x/Makefile b/board/CZ.NIC/turris_1x/Makefile index 1bf370122d9..c5c47adac0a 100644 --- a/board/CZ.NIC/turris_1x/Makefile +++ b/board/CZ.NIC/turris_1x/Makefile @@ -2,10 +2,10 @@ # (C) 2022 Pali Rohár ifdef CONFIG_XPL_BUILD -obj-y += ../../freescale/p1_p2_rdb_pc/spl.o +obj-y += ../../nxp/p1_p2_rdb_pc/spl.o endif -obj-y += ../../freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.o +obj-y += ../../nxp/p1_p2_rdb_pc/p1_p2_rdb_pc.o obj-y += ../turris_atsha_otp.o obj-y += ../turris_common.o diff --git a/board/CZ.NIC/turris_1x/turris_1x.c b/board/CZ.NIC/turris_1x/turris_1x.c index 7a0b68caaef..2f9557a4170 100644 --- a/board/CZ.NIC/turris_1x/turris_1x.c +++ b/board/CZ.NIC/turris_1x/turris_1x.c @@ -315,7 +315,7 @@ int misc_init_r(void) return 0; } -/* This comes from ../../freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c */ +/* This comes from ../../nxp/p1_p2_rdb_pc/p1_p2_rdb_pc.c */ extern int checkboard_p1_p2(void); int checkboard(void) diff --git a/board/beacon/imx8mm/Makefile b/board/beacon/imx8mm/Makefile index b33dc8b05b9..8484b85ae12 100644 --- a/board/beacon/imx8mm/Makefile +++ b/board/beacon/imx8mm/Makefile @@ -5,7 +5,7 @@ # obj-y += imx8mm_beacon.o -obj-y += ../../freescale/common/ +obj-y += ../../nxp/common/ ifdef CONFIG_XPL_BUILD obj-y += spl.o diff --git a/board/beacon/imx8mn/Makefile b/board/beacon/imx8mn/Makefile index 48b7b0952cc..54735792b93 100644 --- a/board/beacon/imx8mn/Makefile +++ b/board/beacon/imx8mn/Makefile @@ -5,7 +5,7 @@ # obj-y += imx8mn_beacon.o -obj-y += ../../freescale/common/ +obj-y += ../../nxp/common/ ifdef CONFIG_XPL_BUILD obj-y += spl.o ifdef CONFIG_IMX8MN_BEACON_2GB_LPDDR diff --git a/board/beacon/imx8mp/Kconfig b/board/beacon/imx8mp/Kconfig index 3c0fca9be8d..b0dd98cf9fd 100644 --- a/board/beacon/imx8mp/Kconfig +++ b/board/beacon/imx8mp/Kconfig @@ -10,7 +10,7 @@ config SYS_CONFIG_NAME default "imx8mp_beacon" config IMX_CONFIG - default "board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg" + default "board/nxp/imx8mp_evk/imximage-8mp-lpddr4.cfg" endif diff --git a/board/beacon/imx8mp/Makefile b/board/beacon/imx8mp/Makefile index 7b994d2c8a1..669b54d63e7 100644 --- a/board/beacon/imx8mp/Makefile +++ b/board/beacon/imx8mp/Makefile @@ -5,7 +5,7 @@ # obj-y += imx8mp_beacon.o -obj-y += ../../freescale/common/ +obj-y += ../../nxp/common/ ifdef CONFIG_XPL_BUILD obj-y += spl.o diff --git a/board/beckhoff/mx53cx9020/imximage.cfg b/board/beckhoff/mx53cx9020/imximage.cfg index 159f50e2a5f..be2ec43d346 100644 --- a/board/beckhoff/mx53cx9020/imximage.cfg +++ b/board/beckhoff/mx53cx9020/imximage.cfg @@ -3,7 +3,7 @@ * Copyright (C) 2015 Beckhoff Automation GmbH * Patrick Bruenn * - * Based on /board/freescale/mx53loco/imximage.cfg + * Based on /board/nxp/mx53loco/imximage.cfg * Copyright (C) 2011 Freescale Semiconductor, Inc. */ diff --git a/board/beckhoff/mx53cx9020/mx53cx9020.c b/board/beckhoff/mx53cx9020/mx53cx9020.c index 3a766728a6f..ffbd639921d 100644 --- a/board/beckhoff/mx53cx9020/mx53cx9020.c +++ b/board/beckhoff/mx53cx9020/mx53cx9020.c @@ -3,7 +3,7 @@ * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG * Patrick Bruenn * - * Based on /board/freescale/mx53loco/mx53loco.c + * Based on /board/nxp/mx53loco/mx53loco.c * Copyright (C) 2011 Freescale Semiconductor, Inc. */ diff --git a/board/beckhoff/mx53cx9020/mx53cx9020_video.c b/board/beckhoff/mx53cx9020/mx53cx9020_video.c index fd28a70f4d7..e3eaf0393ba 100644 --- a/board/beckhoff/mx53cx9020/mx53cx9020_video.c +++ b/board/beckhoff/mx53cx9020/mx53cx9020_video.c @@ -3,7 +3,7 @@ * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG * Patrick Bruenn * - * Based on /board/freescale/mx53loco/mx53loco_video.c + * Based on /board/nxp/mx53loco/mx53loco_video.c * Copyright (C) 2012 Freescale Semiconductor, Inc. */ diff --git a/board/boundary/nitrogen6x/README b/board/boundary/nitrogen6x/README index 973b18fa93f..0b59289e7f0 100644 --- a/board/boundary/nitrogen6x/README +++ b/board/boundary/nitrogen6x/README @@ -10,7 +10,7 @@ Freescale i.MX6Q SabreLite boards. The configuration in this directory supports both the Nitrogen6X and Freescale SabreLite board, but in a different fashion from Freescale's implementation in -board/freescale/mx6qsabrelite. +board/nxp/mx6qsabrelite. In particular, this image supports booting from SPI NOR and saving the environment to SPI NOR. diff --git a/board/ea/mx7ulp_com/imximage.cfg b/board/ea/mx7ulp_com/imximage.cfg index 1731da814d0..c77a9966076 100644 --- a/board/ea/mx7ulp_com/imximage.cfg +++ b/board/ea/mx7ulp_com/imximage.cfg @@ -24,7 +24,7 @@ BOOT_FROM sd #ifdef CONFIG_USE_IMXIMG_PLUGIN /*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ -PLUGIN board/freescale/mx7ulp_evk/plugin.bin 0x2F020000 +PLUGIN board/nxp/mx7ulp_evk/plugin.bin 0x2F020000 #else #ifdef CONFIG_IMX_HAB diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile deleted file mode 100644 index ed102ae7bf7..00000000000 --- a/board/freescale/common/Makefile +++ /dev/null @@ -1,83 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -MINIMAL= - -ifdef CONFIG_XPL_BUILD -ifndef CONFIG_TPL_BUILD -ifdef CONFIG_SPL_INIT_MINIMAL -MINIMAL=y -endif -endif -endif - -ifdef MINIMAL -# necessary to create built-in.a -obj- := __dummy__.a -else -# include i2c_common.o once if either VID or FSL_USE_PCA9547_MUX -I2C_COMMON= -ifdef CONFIG_VID -I2C_COMMON=y -endif -ifdef CONFIG_FSL_USE_PCA9547_MUX -I2C_COMMON=y -endif - -obj-$(CONFIG_FSL_CADMUS) += cadmus.o -obj-$(CONFIG_FSL_VIA) += cds_via.o -obj-$(CONFIG_FMAN_ENET) += fman.o -ifndef CONFIG_XPL_BUILD -obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o -endif -obj-$(I2C_COMMON) += i2c_common.o -obj-$(CONFIG_FSL_USE_PCA9547_MUX) += i2c_mux.o -obj-$(CONFIG_$(PHASE_)VID) += vid.o -obj-$(CONFIG_FSL_QIXIS) += qixis.o -ifndef CONFIG_XPL_BUILD -obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o -endif -ifndef CONFIG_RAMBOOT_PBL -obj-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o -endif - -ifdef CONFIG_ARM -obj-$(CONFIG_DEEP_SLEEP) += arm_sleep.o -else -obj-$(CONFIG_DEEP_SLEEP) += mpc85xx_sleep.o -endif - -obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o - -obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o -obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o -obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o -ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y) -obj-$(CONFIG_POWER_PFUZE100) += pfuze.o -endif -obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o -obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o -ifneq (,$(filter $(SOC), imx8m imx8ulp imx9)) -obj-y += mmc.o -endif - -obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o - -obj-$(CONFIG_EMC2305) += emc2305.o - -# deal with common files for P-series corenet based devices -obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/ -obj-$(CONFIG_TARGET_P3041DS) += p_corenet/ -obj-$(CONFIG_TARGET_P4080DS) += p_corenet/ -obj-$(CONFIG_TARGET_P5040DS) += p_corenet/ - -obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o - -ifdef CONFIG_NXP_ESBC -obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o -endif -obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o - -endif diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c deleted file mode 100644 index 228f07502f7..00000000000 --- a/board/freescale/common/arm_sleep.c +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#ifndef CONFIG_ARMV7_NONSEC -#error " Deep sleep needs non-secure mode support. " -#else -#include -#endif -#include - -#if defined(CONFIG_ARCH_LS1021A) -#include -#endif - -#include "sleep.h" -#ifdef CONFIG_U_QE -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -void __weak board_mem_sleep_setup(void) -{ -} - -void __weak board_sleep_prepare(void) -{ -} - -bool is_warm_boot(void) -{ - struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; - - if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) - return 1; - - return 0; -} - -void fsl_dp_disable_console(void) -{ - gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; -} - -/* - * When wakeup from deep sleep, the first 128 bytes space - * will be used to do DDR training which corrupts the data - * in there. This function will restore them. - */ -static void dp_ddr_restore(void) -{ - u64 *src, *dst; - int i; - struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; - - /* get the address of ddr date from SPARECR3 */ - src = (u64 *)in_le32(&scfg->sparecr[2]); - dst = (u64 *)CFG_SYS_SDRAM_BASE; - - for (i = 0; i < DDR_BUFF_LEN / 8; i++) - *dst++ = *src++; -} - -#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A) -void ls1_psci_resume_fixup(void) -{ - u32 tmp; - struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; - -#ifdef QIXIS_BASE - void *qixis_base = (void *)QIXIS_BASE; - - /* Pull on PCIe RST# */ - out_8(qixis_base + QIXIS_RST_FORCE_3, 0); - - /* disable deep sleep signals in FPGA */ - tmp = in_8(qixis_base + QIXIS_PWR_CTL2); - tmp &= ~QIXIS_PWR_CTL2_PCTL; - out_8(qixis_base + QIXIS_PWR_CTL2, tmp); -#endif - - /* Disable wakeup interrupt during deep sleep */ - out_be32(&scfg->pmcintecr, 0); - /* Clear PMC interrupt status */ - out_be32(&scfg->pmcintsr, 0xffffffff); - - /* Disable Warm Device Reset */ - tmp = in_be32(&scfg->dpslpcr); - tmp &= ~SCFG_DPSLPCR_WDRR_EN; - out_be32(&scfg->dpslpcr, tmp); -} -#endif - -static void dp_resume_prepare(void) -{ - dp_ddr_restore(); - board_sleep_prepare(); - armv7_init_nonsec(); -#ifdef CONFIG_U_QE - u_qe_resume(); -#endif -#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A) - ls1_psci_resume_fixup(); -#endif -} - -int fsl_dp_resume(void) -{ - u32 start_addr; - void (*kernel_resume)(void); - struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; - - if (!is_warm_boot()) - return 0; - - dp_resume_prepare(); - - /* Get the entry address and jump to kernel */ - start_addr = in_le32(&scfg->sparecr[3]); - debug("Entry address is 0x%08x\n", start_addr); - kernel_resume = (void (*)(void))start_addr; - secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0); - - return 0; -} diff --git a/board/freescale/common/cadmus.c b/board/freescale/common/cadmus.c deleted file mode 100644 index e5ecd0e19c6..00000000000 --- a/board/freescale/common/cadmus.c +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2004, 2011 Freescale Semiconductor. - */ - -#include -#include -#include - -/* - * CADMUS Board System Registers - */ -#ifndef CFG_SYS_CADMUS_BASE_REG -#define CFG_SYS_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000) -#endif - -typedef struct cadmus_reg { - u_char cm_ver; /* Board version */ - u_char cm_csr; /* General control/status */ - u_char cm_rst; /* Reset control */ - u_char cm_hsclk; /* High speed clock */ - u_char cm_hsxclk; /* High speed clock extended */ - u_char cm_led; /* LED data */ - u_char cm_pci; /* PCI control/status */ - u_char cm_dma; /* DMA control */ - u_char cm_reserved[248]; /* Total 256 bytes */ -} cadmus_reg_t; - -unsigned int -get_board_version(void) -{ - volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG; - - return cadmus->cm_ver; -} - -unsigned long -get_board_sys_clk(void) -{ - volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG; - - uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */ - - if (pci1_speed == 0) { - return 33333333; - } else if (pci1_speed == 1) { - return 66666666; - } else { - /* Really, unknown. Be safe? */ - return 33333333; - } -} - -unsigned int -get_pci_slot(void) -{ - volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG; - - /* - * PCI slot in USER bits CSR[6:7] by convention. - */ - return ((cadmus->cm_csr >> 6) & 0x3) + 1; -} - -unsigned int -get_pci_dual(void) -{ - volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG; - - /* - * PCI DUAL in CM_PCI[3] - */ - return cadmus->cm_pci & 0x10; -} diff --git a/board/freescale/common/cadmus.h b/board/freescale/common/cadmus.h deleted file mode 100644 index 93cea120845..00000000000 --- a/board/freescale/common/cadmus.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2004 Freescale Semiconductor. - */ - -#ifndef __CADMUS_H_ -#define __CADMUS_H_ - -/* - * CADMUS Board System Register interface. - */ - -/* - * Returns board version register. - */ -extern unsigned int get_board_version(void); - -/* - * Returns either 33000000 or 66000000 as the SYS_CLK_FREQ. - */ -extern unsigned long get_board_sys_clk(void); - -/* - * Returns 1 - 4, as found in the USER CSR[6:7] bits. - */ -extern unsigned int get_pci_slot(void); - -/* - * Returns PCI DUAL as found in CM_PCI[3]. - */ -extern unsigned int get_pci_dual(void); - -#endif /* __CADMUS_H_ */ diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c deleted file mode 100644 index 56b01e3f51f..00000000000 --- a/board/freescale/common/cds_pci_ft.c +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2004 Freescale Semiconductor. - */ - -#include -#include -#include "cadmus.h" - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif diff --git a/board/freescale/common/cds_via.c b/board/freescale/common/cds_via.c deleted file mode 100644 index 6fc3a21780f..00000000000 --- a/board/freescale/common/cds_via.c +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2006 Freescale Semiconductor. - */ - -#include - -/* Config the VIA chip */ -void mpc85xx_config_via(struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *tab) -{ - pci_dev_t bridge; - unsigned int cmdstat; - - /* Enable USB and IDE functions */ - pci_hose_write_config_byte(hose, dev, 0x48, 0x08); - - pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); - cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER; - pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - - /* - * Force the backplane P2P bridge to have a window - * open from 0x00000000-0x00001fff in PCI I/O space. - * This allows legacy I/O (i8259, etc) on the VIA - * southbridge to be accessed. - */ -#ifdef CONFIG_TARGET_MPC8548CDS_LEGACY - bridge = PCI_BDF(0, 17, 0); -#else - bridge = PCI_BDF(0, 28, 0); -#endif - pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0); - pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0); - pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10); - pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0); -} - -/* Function 1, IDE */ -void mpc85xx_config_via_usbide(struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *tab) -{ - pciauto_config_device(hose, dev); - /* - * Since the P2P window was forced to cover the fixed - * legacy I/O addresses, it is necessary to manually - * place the base addresses for the IDE and USB functions - * within this window. - */ - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8); - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4); - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8); - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4); - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0); -} - -/* Function 2, USB ports 0-1 */ -void mpc85xx_config_via_usb(struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *tab) -{ - pciauto_config_device(hose, dev); - - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0); -} - -/* Function 3, USB ports 2-3 */ -void mpc85xx_config_via_usb2(struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *tab) -{ - pciauto_config_device(hose, dev); - - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80); -} - -/* Function 5, Power Management */ -void mpc85xx_config_via_power(struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *tab) -{ - pciauto_config_device(hose, dev); - - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00); - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc); - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8); -} - -/* Function 6, AC97 Interface */ -void mpc85xx_config_via_ac97(struct pci_controller *hose, - pci_dev_t dev, struct pci_config_table *tab) -{ - pciauto_config_device(hose, dev); - - pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00); -} diff --git a/board/freescale/common/cmd_esbc_validate.c b/board/freescale/common/cmd_esbc_validate.c deleted file mode 100644 index 7629d7091e9..00000000000 --- a/board/freescale/common/cmd_esbc_validate.c +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include - -int do_esbc_halt(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - if (fsl_check_boot_mode_secure() == 0) { - printf("Boot Mode is Non-Secure. Not entering spin loop.\n"); - return 0; - } - - printf("Core is entering spin loop.\n"); -loop: - goto loop; - - return 0; -} - -#ifndef CONFIG_XPL_BUILD -static int do_esbc_validate(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - char *hash_str = NULL; - uintptr_t haddr; - int ret; - uintptr_t img_addr = 0; - char buf[20]; - - if (argc < 2) - return cmd_usage(cmdtp); - else if (argc > 2) - /* Second arg - Optional - Hash Str*/ - hash_str = argv[2]; - - /* First argument - header address -32/64bit */ - haddr = (uintptr_t)hextoul(argv[1], NULL); - - /* With esbc_validate command, Image address must be - * part of header. So, the function is called - * by passing this argument as 0. - */ - ret = fsl_secboot_validate(haddr, hash_str, &img_addr); - - /* Need to set "img_addr" even if validation failure. - * Required when SB_EN in RCW set and non-fatal error - * to continue U-Boot - */ - sprintf(buf, "%lx", img_addr); - env_set("img_addr", buf); - - if (ret) - return 1; - - printf("esbc_validate command successful\n"); - return 0; -} - -/***************************************************/ -U_BOOT_LONGHELP(esbc_validate, - "esbc_validate hdr_addr - Validates signature using\n" - " RSA verification\n" - " $hdr_addr Address of header of the image\n" - " to be validated.\n" - " $hash_val -Optional\n" - " It provides Hash of public/srk key to be\n" - " used to verify signature.\n"); - -U_BOOT_CMD( - esbc_validate, 3, 0, do_esbc_validate, - "Validates signature on a given image using RSA verification", - esbc_validate_help_text -); - -U_BOOT_CMD( - esbc_halt, 1, 0, do_esbc_halt, - "Put the core in spin loop (Secure Boot Only)", - "" -); -#endif diff --git a/board/freescale/common/eeprom.h b/board/freescale/common/eeprom.h deleted file mode 100644 index 1d0685fde67..00000000000 --- a/board/freescale/common/eeprom.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2004 Freescale Semiconductor. - */ - -#ifndef __EEPROM_H_ -#define __EEPROM_H_ - -/* - * EEPROM Board System Register interface. - */ - -/* - * CPU Board Revision - */ -#define MPC85XX_CPU_BOARD_REV(maj, min) ((((maj)&0xff) << 8) | ((min) & 0xff)) -#define MPC85XX_CPU_BOARD_MAJOR(rev) (((rev) >> 8) & 0xff) -#define MPC85XX_CPU_BOARD_MINOR(rev) ((rev) & 0xff) - -#define MPC85XX_CPU_BOARD_REV_UNKNOWN MPC85XX_CPU_BOARD_REV(0,0) -#define MPC85XX_CPU_BOARD_REV_1_0 MPC85XX_CPU_BOARD_REV(1,0) -#define MPC85XX_CPU_BOARD_REV_1_1 MPC85XX_CPU_BOARD_REV(1,1) - -/* - * Returns CPU board revision register as a 16-bit value with - * the Major in the high byte, and Minor in the low byte. - */ -extern unsigned int get_cpu_board_revision(void); - -#endif /* __CADMUS_H_ */ diff --git a/board/freescale/common/emc2305.c b/board/freescale/common/emc2305.c deleted file mode 100644 index 50252bb5007..00000000000 --- a/board/freescale/common/emc2305.c +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018-2020 NXP. - * - */ - -#include -#include -#include -#include - -#include "emc2305.h" - -DECLARE_GLOBAL_DATA_PTR; - -void set_fan_speed(u8 data, int chip_addr) -{ - u8 index; - u8 Fan[NUM_OF_FANS] = {I2C_EMC2305_FAN1, - I2C_EMC2305_FAN2, - I2C_EMC2305_FAN3, - I2C_EMC2305_FAN4, - I2C_EMC2305_FAN5}; - - for (index = 0; index < NUM_OF_FANS; index++) { -#if !CONFIG_IS_ENABLED(DM_I2C) - if (i2c_write(chip_addr, Fan[index], 1, &data, 1) != 0) { - printf("Error: failed to change fan speed @%x\n", - Fan[index]); - } -#else - struct udevice *dev; - - if (i2c_get_chip_for_busnum(0, chip_addr, 1, &dev)) - continue; - - if (dm_i2c_write(dev, Fan[index], &data, 1) != 0) { - printf("Error: failed to change fan speed @%x\n", - Fan[index]); - } -#endif - } -} - -void emc2305_init(int chip_addr) -{ - u8 data; - - data = I2C_EMC2305_CMD; -#if !CONFIG_IS_ENABLED(DM_I2C) - if (i2c_write(chip_addr, I2C_EMC2305_CONF, 1, &data, 1) != 0) - printf("Error: failed to configure EMC2305\n"); -#else - struct udevice *dev; - - if (!i2c_get_chip_for_busnum(0, chip_addr, 1, &dev)) - if (dm_i2c_write(dev, I2C_EMC2305_CONF, &data, 1)) - printf("Error: failed to configure EMC2305\n"); -#endif - -} diff --git a/board/freescale/common/emc2305.h b/board/freescale/common/emc2305.h deleted file mode 100644 index 24c5410d120..00000000000 --- a/board/freescale/common/emc2305.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018-2020 NXP - * - */ - -#ifndef __EMC2305_H_ -#define __EMC2305_H_ - -#define I2C_EMC2305_CONF 0x20 -#define I2C_EMC2305_FAN1 0x30 -#define I2C_EMC2305_FAN2 0x40 -#define I2C_EMC2305_FAN3 0x50 -#define I2C_EMC2305_FAN4 0x60 -#define I2C_EMC2305_FAN5 0x70 - -#define NUM_OF_FANS 5 - -void emc2305_init(int chip_addr); -void set_fan_speed(u8 data, int chip_addr); - -#endif /* __EMC2305_H_ */ diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c deleted file mode 100644 index 650ecc7b440..00000000000 --- a/board/freescale/common/fman.c +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011-2015 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -#include -#ifdef CONFIG_FSL_LAYERSCAPE -#include -#else -#include -#endif - -/* - * Given the following ... - * - * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' - * compatible string and 'addr' physical address) - * - * 2) The name of an alias that points to the ethernet-phy node (usually inside - * a virtual MDIO node) - * - * ... update that Ethernet node's phy-handle property to point to the - * ethernet-phy node. This is how we link an Ethernet node to its PHY, so each - * PHY in a virtual MDIO node must have an alias. - * - * Returns 0 on success, or a negative FDT error code on error. - */ -int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr, - const char *alias) -{ - int offset; - unsigned int ph; - const char *path; - - /* Get a path to the node that 'alias' points to */ - path = fdt_get_alias(fdt, alias); - if (!path) - return -FDT_ERR_BADPATH; - - /* Get the offset of that node */ - offset = fdt_path_offset(fdt, path); - if (offset < 0) - return offset; - - ph = fdt_create_phandle(fdt, offset); - if (!ph) - return -FDT_ERR_BADPHANDLE; - - ph = cpu_to_fdt32(ph); - - offset = fdt_node_offset_by_compat_reg(fdt, compat, addr); - if (offset < 0) - return offset; - - return fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph)); -} - -/* - * Return the SerDes device enum for a given Fman port - * - * This function just maps the fm_port namespace to the srds_prtcl namespace. - */ -enum srds_prtcl serdes_device_from_fm_port(enum fm_port port) -{ - static const enum srds_prtcl srds_table[] = { - [FM1_DTSEC1] = SGMII_FM1_DTSEC1, - [FM1_DTSEC2] = SGMII_FM1_DTSEC2, - [FM1_DTSEC3] = SGMII_FM1_DTSEC3, - [FM1_DTSEC4] = SGMII_FM1_DTSEC4, - [FM1_DTSEC5] = SGMII_FM1_DTSEC5, - [FM1_10GEC1] = XAUI_FM1, - [FM2_DTSEC1] = SGMII_FM2_DTSEC1, - [FM2_DTSEC2] = SGMII_FM2_DTSEC2, - [FM2_DTSEC3] = SGMII_FM2_DTSEC3, - [FM2_DTSEC4] = SGMII_FM2_DTSEC4, - [FM2_DTSEC5] = SGMII_FM2_DTSEC5, - [FM2_10GEC1] = XAUI_FM2, - }; - - if ((port < FM1_DTSEC1) || (port > FM2_10GEC1)) - return NONE; - else - return srds_table[port]; -} diff --git a/board/freescale/common/fman.h b/board/freescale/common/fman.h deleted file mode 100644 index 16afc34b03e..00000000000 --- a/board/freescale/common/fman.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - */ - -#ifndef __FMAN_BOARD_HELPER__ -#define __FMAN_BOARD_HELPER__ - -int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr, - const char *alias); - -enum srds_prtcl serdes_device_from_fm_port(enum fm_port port); - -#endif diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c deleted file mode 100644 index 3d44357caf7..00000000000 --- a/board/freescale/common/fsl_chain_of_trust.c +++ /dev/null @@ -1,160 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * Copyright 2022 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK) -#include -#endif - -#ifdef CONFIG_FSL_CORENET -#include -#endif - -#ifdef CONFIG_ARCH_LS1021A -#include -#endif - -#if defined(CONFIG_MPC85xx) -#define CFG_DCFG_ADDR CFG_SYS_MPC85xx_GUTS_ADDR -#else -#define CFG_DCFG_ADDR CFG_SYS_FSL_GUTS_ADDR -#endif - -#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE -#define gur_in32(a) in_le32(a) -#else -#define gur_in32(a) in_be32(a) -#endif - -/* Check the Boot Mode. If Secure, return 1 else return 0 */ -int fsl_check_boot_mode_secure(void) -{ - uint32_t val; - struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); - struct ccsr_gur __iomem *gur = (void *)(CFG_DCFG_ADDR); - - val = sfp_in32(&sfp_regs->ospr) & ITS_MASK; - if (val == ITS_MASK) - return 1; - -#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx) - /* For PBL based platforms check the SB_EN bit in RCWSR */ - val = gur_in32(&gur->rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK; - if (val == RCW_SB_EN_MASK) - return 1; -#endif - -#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET) - /* For Non-PBL Platforms, check the Device Status register 2*/ - val = gur_in32(&gur->pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK; - if (val != MPC85xx_PORDEVSR2_SBC_MASK) - return 1; - -#endif - return 0; -} - -#ifndef CONFIG_XPL_BUILD -int fsl_setenv_chain_of_trust(void) -{ - /* Check Boot Mode - * If Boot Mode is Non-Secure, no changes are required - */ - if (fsl_check_boot_mode_secure() == 0) - return 0; - - /* If Boot mode is Secure, set the environment variables - * bootdelay = 0 (To disable Boot Prompt) - * bootcmd = CHAIN_BOOT_CMD (Validate and execute Boot script) - */ - env_set("bootdelay", "-2"); - -#ifdef CONFIG_ARM - env_set("secureboot", "y"); -#else - env_set("bootcmd", CHAIN_BOOT_CMD); -#endif - - return 0; -} -#endif - -#ifdef CONFIG_XPL_BUILD -void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr) -{ - int res; - - /* - * Check Boot Mode - * If Boot Mode is Non-Secure, skip validation - */ - if (fsl_check_boot_mode_secure() == 0) - return; - - printf("SPL: Validating U-Boot image\n"); - -#ifdef CONFIG_ADDR_MAP - init_addr_map(); -#endif - -#ifdef CONFIG_FSL_CORENET - if (pamu_init() < 0) - fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); -#endif - -/* - * dm_init_and_scan() is called as part of common SPL framework, so no - * need to call it again but in case of powerpc platforms which currently - * do not use common SPL framework, so need to call this function here. - */ -#if defined(CONFIG_SPL_DM) && (!defined(CONFIG_SPL_FRAMEWORK)) - dm_init_and_scan(true); -#endif - res = fsl_secboot_validate(hdr_addr, CONFIG_SPL_UBOOT_KEY_HASH, - &img_addr); - - if (res == 0) - printf("SPL: Validation of U-Boot successful\n"); -} - -#ifdef CONFIG_SPL_FRAMEWORK -/* Override weak funtion defined in SPL framework to enable validation - * of main u-boot image before jumping to u-boot image. - */ -void __noreturn jump_to_image(struct spl_image_info *spl_image) -{ - typedef void __noreturn (*image_entry_noargs_t)(void); - uint32_t hdr_addr; - - image_entry_noargs_t image_entry = - (image_entry_noargs_t)(unsigned long)spl_image->entry_point; - - hdr_addr = (spl_image->entry_point + spl_image->size - - FSL_U_BOOT_HDR_SIZE); - spl_validate_uboot(hdr_addr, (uintptr_t)spl_image->entry_point); - /* - * In case of failure in validation, spl_validate_uboot would - * not return back in case of Production environment with ITS=1. - * Thus U-Boot will not start. - * In Development environment (ITS=0 and SB_EN=1), the function - * may return back in case of non-fatal failures. - */ - - debug("image entry point: 0x%lX\n", spl_image->entry_point); - image_entry(); -} -#endif /* ifdef CONFIG_SPL_FRAMEWORK */ -#endif /* ifdef CONFIG_XPL_BUILD */ diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c deleted file mode 100644 index df0c1a1f406..00000000000 --- a/board/freescale/common/fsl_validate.c +++ /dev/null @@ -1,973 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * Copyright 2021-2022 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_ARCH_LS1021A -#include -#endif -#include - -#define SHA256_BITS 256 -#define SHA256_BYTES (256/8) -#define SHA256_NIBBLES (256/4) -#define NUM_HEX_CHARS (sizeof(ulong) * 2) - -#define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \ - ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \ - ((key_len) == 2 * KEY_SIZE_BYTES)) -#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) -/* Global data structure */ -static struct fsl_secboot_glb glb; -#endif - -/* This array contains DER value for SHA-256 */ -static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, - 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, - 0x04, 0x20 - }; - -static u8 hash_val[SHA256_BYTES]; - -#ifdef CONFIG_ESBC_HDR_LS -/* New Barker Code for LS ESBC Header */ -static const u8 barker_code[ESBC_BARKER_LEN] = { 0x12, 0x19, 0x20, 0x01 }; -#else -static const u8 barker_code[ESBC_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 }; -#endif - -void branch_to_self(void) __attribute__ ((noreturn)); - -/* - * This function will put core in infinite loop. - * This will be called when the ESBC can not proceed further due - * to some unknown errors. - */ -void branch_to_self(void) -{ - printf("Core is in infinite loop due to errors.\n"); -self: - goto self; -} - -#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) -static u32 check_ie(struct fsl_secboot_img_priv *img) -{ - if (img->hdr.ie_flag & IE_FLAG_MASK) - return 1; - - return 0; -} - -/* This function returns the CSF Header Address of uboot - * For MPC85xx based platforms, the LAW mapping for NOR - * flash changes in uboot code. Hence the offset needs - * to be calculated and added to the new NOR flash base - * address - */ -#if defined(CONFIG_MPC85xx) -#include - -int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) -{ - struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); - u32 csf_flash_offset = csf_hdr_addr & ~(CFG_SYS_PBI_FLASH_BASE); - u32 flash_addr, addr; - int found = 0; - int i = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - flash_addr = flash_info[i].start[0]; - addr = flash_info[i].start[0] + csf_flash_offset; - if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) { - debug("Barker found on addr %x\n", addr); - found = 1; - break; - } - } - - if (!found) - return -1; - - *csf_addr = addr; - *flash_base_addr = flash_addr; - - return 0; -} -#else -/* For platforms like LS1020, correct flash address is present in - * the header. So the function reqturns flash base address as 0 - */ -int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) -{ - struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); - - if (memcmp((u8 *)(uintptr_t)csf_hdr_addr, - barker_code, ESBC_BARKER_LEN)) - return -1; - - *csf_addr = csf_hdr_addr; - *flash_base_addr = 0; - return 0; -} -#endif - -#if defined(CONFIG_ESBC_HDR_LS) -static int get_ie_info_addr(uintptr_t *ie_addr) -{ - struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - /* For LS-CH3, the address of IE Table is - * stated in Scratch13 and scratch14 of DCFG. - * Bootrom validates this table while validating uboot. - * DCFG is LE*/ - *ie_addr = in_le32(&gur->scratchrw[SCRATCH_IE_HIGH_ADR - 1]); - *ie_addr = *ie_addr << 32; - *ie_addr |= in_le32(&gur->scratchrw[SCRATCH_IE_LOW_ADR - 1]); - return 0; -} -#else /* CONFIG_ESBC_HDR_LS */ -static int get_ie_info_addr(uintptr_t *ie_addr) -{ - struct fsl_secboot_img_hdr *hdr; - struct fsl_secboot_sg_table *sg_tbl; - u32 flash_base_addr, csf_addr; - - if (get_csf_base_addr(&csf_addr, &flash_base_addr)) - return -1; - - hdr = (struct fsl_secboot_img_hdr *)(uintptr_t)csf_addr; - - /* For SoC's with Trust Architecture v1 with corenet bus - * the sg table field in CSF header has absolute address - * for sg table in memory. In other Trust Architecture, - * this field specifies the offset of sg table from the - * base address of CSF Header - */ -#if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET) - sg_tbl = (struct fsl_secboot_sg_table *) - (((u32)hdr->psgtable & ~(CFG_SYS_PBI_FLASH_BASE)) + - flash_base_addr); -#else - sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr + - (u32)hdr->psgtable); -#endif - - /* IE Key Table is the first entry in the SG Table */ -#if defined(CONFIG_MPC85xx) - *ie_addr = (uintptr_t)((sg_tbl->src_addr & - ~(CFG_SYS_PBI_FLASH_BASE)) + - flash_base_addr); -#else - *ie_addr = (uintptr_t)sg_tbl->src_addr; -#endif - - debug("IE Table address is %lx\n", *ie_addr); - return 0; -} -#endif /* CONFIG_ESBC_HDR_LS */ -#endif - -#ifdef CONFIG_KEY_REVOCATION -/* This function checks srk_table_flag in header and set/reset srk_flag.*/ -static u32 check_srk(struct fsl_secboot_img_priv *img) -{ -#ifdef CONFIG_ESBC_HDR_LS - /* In LS, No SRK Flag as SRK is always present if IE not present*/ -#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) - return !check_ie(img); -#endif - return 1; -#else - if (img->hdr.len_kr.srk_table_flag & SRK_FLAG) - return 1; - - return 0; -#endif -} - -/* This function returns ospr's key_revoc values.*/ -static u32 get_key_revoc(void) -{ - struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); - return (sfp_in32(&sfp_regs->ospr) & OSPR_KEY_REVOC_MASK) >> - OSPR_KEY_REVOC_SHIFT; -} - -/* This function checks if selected key is revoked or not.*/ -static u32 is_key_revoked(u32 keynum, u32 rev_flag) -{ - if (keynum == UNREVOCABLE_KEY) - return 0; - - if ((u32)(1 << (ALIGN_REVOC_KEY - keynum)) & rev_flag) - return 1; - - return 0; -} - -/* It read validates srk_table key lengths.*/ -static u32 read_validate_srk_tbl(struct fsl_secboot_img_priv *img) -{ - int i = 0; - u32 ret, key_num, key_revoc_flag, size; - struct fsl_secboot_img_hdr *hdr = &img->hdr; - void *esbc = (u8 *)(uintptr_t)img->ehdrloc; - - if ((hdr->len_kr.num_srk == 0) || - (hdr->len_kr.num_srk > MAX_KEY_ENTRIES)) - return ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY; - - key_num = hdr->len_kr.srk_sel; - if (key_num == 0 || key_num > hdr->len_kr.num_srk) - return ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM; - - /* Get revoc key from sfp */ - key_revoc_flag = get_key_revoc(); - ret = is_key_revoked(key_num, key_revoc_flag); - if (ret) - return ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED; - - size = hdr->len_kr.num_srk * sizeof(struct srk_table); - - memcpy(&img->srk_tbl, esbc + hdr->srk_tbl_off, size); - - for (i = 0; i < hdr->len_kr.num_srk; i++) { - if (!CHECK_KEY_LEN(img->srk_tbl[i].key_len)) - return ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN; - } - - img->key_len = img->srk_tbl[key_num - 1].key_len; - - memcpy(&img->img_key, &(img->srk_tbl[key_num - 1].pkey), - img->key_len); - - return 0; -} -#endif - -#ifndef CONFIG_ESBC_HDR_LS -static u32 read_validate_single_key(struct fsl_secboot_img_priv *img) -{ - struct fsl_secboot_img_hdr *hdr = &img->hdr; - void *esbc = (u8 *)(uintptr_t)img->ehdrloc; - - /* check key length */ - if (!CHECK_KEY_LEN(hdr->key_len)) - return ERROR_ESBC_CLIENT_HEADER_KEY_LEN; - - memcpy(&img->img_key, esbc + hdr->pkey, hdr->key_len); - - img->key_len = hdr->key_len; - - return 0; -} -#endif /* CONFIG_ESBC_HDR_LS */ - -#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) - -static void install_ie_tbl(uintptr_t ie_tbl_addr, - struct fsl_secboot_img_priv *img) -{ - /* Copy IE tbl to Global Data */ - memcpy(&glb.ie_tbl, (u8 *)ie_tbl_addr, sizeof(struct ie_key_info)); - img->ie_addr = (uintptr_t)&glb.ie_tbl; - glb.ie_addr = img->ie_addr; -} - -static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img) -{ - struct fsl_secboot_img_hdr *hdr = &img->hdr; - u32 ie_key_len, ie_revoc_flag, ie_num; - struct ie_key_info *ie_info; - - if (!img->ie_addr) { - if (get_ie_info_addr(&img->ie_addr)) - return ERROR_IE_TABLE_NOT_FOUND; - else - install_ie_tbl(img->ie_addr, img); - } - - ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr; - if (ie_info->num_keys == 0 || ie_info->num_keys > 32) - return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY; - - ie_num = hdr->ie_key_sel; - if (ie_num == 0 || ie_num > ie_info->num_keys) - return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM; - - ie_revoc_flag = ie_info->key_revok; - if ((u32)(1 << (ie_num - 1)) & ie_revoc_flag) - return ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED; - - ie_key_len = ie_info->ie_key_tbl[ie_num - 1].key_len; - - if (!CHECK_KEY_LEN(ie_key_len)) - return ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN; - - memcpy(&img->img_key, &(ie_info->ie_key_tbl[ie_num - 1].pkey), - ie_key_len); - - img->key_len = ie_key_len; - return 0; -} -#endif - -/* This function return length of public key.*/ -static inline u32 get_key_len(struct fsl_secboot_img_priv *img) -{ - return img->key_len; -} - -/* - * Handles the ESBC uboot client header verification failure. - * This function handles all the errors which might occur in the - * parsing and checking of ESBC uboot client header. It will also - * set the error bits in the SEC_MON. - */ -static void fsl_secboot_header_verification_failure(void) -{ - struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); - - /* 29th bit of OSPR is ITS */ - u32 its = sfp_in32(&sfp_regs->ospr) >> 2; - - if (its == 1) - set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL); - else - set_sec_mon_state(HPSR_SSM_ST_NON_SECURE); - - printf("Generating reset request\n"); - do_reset(NULL, 0, 0, NULL); - /* If reset doesn't coocur, halt execution */ - do_esbc_halt(NULL, 0, 0, NULL); -} - -/* - * Handles the ESBC uboot client image verification failure. - * This function handles all the errors which might occur in the - * public key hash comparison and signature verification of - * ESBC uboot client image. It will also - * set the error bits in the SEC_MON. - */ -static void fsl_secboot_image_verification_failure(void) -{ - struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); - - u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT; - - if (its == 1) { - set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL); - - printf("Generating reset request\n"); - do_reset(NULL, 0, 0, NULL); - /* If reset doesn't coocur, halt execution */ - do_esbc_halt(NULL, 0, 0, NULL); - - } else { - set_sec_mon_state(HPSR_SSM_ST_NON_SECURE); - } -} - -static void fsl_secboot_bootscript_parse_failure(void) -{ - fsl_secboot_header_verification_failure(); -} - -/* - * Handles the errors in esbc boot. - * This function handles all the errors which might occur in the - * esbc boot phase. It will call the appropriate api to log the - * errors and set the error bits in the SEC_MON. - */ -void fsl_secboot_handle_error(int error) -{ -#ifndef CONFIG_XPL_BUILD - const struct fsl_secboot_errcode *e; - - for (e = fsl_secboot_errcodes; e->errcode != ERROR_ESBC_CLIENT_MAX; - e++) { - if (e->errcode == error) - printf("ERROR :: %x :: %s\n", error, e->name); - } -#else - printf("ERROR :: %x\n", error); -#endif - - /* If Boot Mode is secure, transition the SNVS state and issue - * reset based on type of failure and ITS setting. - * If Boot mode is non-secure, return from this function. - */ - if (fsl_check_boot_mode_secure() == 0) - return; - - switch (error) { - case ERROR_ESBC_CLIENT_HEADER_BARKER: - case ERROR_ESBC_CLIENT_HEADER_IMG_SIZE: - case ERROR_ESBC_CLIENT_HEADER_KEY_LEN: - case ERROR_ESBC_CLIENT_HEADER_SIG_LEN: - case ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN: - case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1: - case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2: - case ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD: - case ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP: - case ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD: - case ERROR_KEY_TABLE_NOT_FOUND: -#ifdef CONFIG_KEY_REVOCATION - case ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED: - case ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY: - case ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM: - case ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN: -#endif -#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) - /*@fallthrough@*/ - case ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED: - case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY: - case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM: - case ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN: - case ERROR_IE_TABLE_NOT_FOUND: -#endif - fsl_secboot_header_verification_failure(); - break; - case ERROR_ESBC_SEC_RESET: - case ERROR_ESBC_SEC_DEQ: - case ERROR_ESBC_SEC_ENQ: - case ERROR_ESBC_SEC_DEQ_TO: - case ERROR_ESBC_SEC_JOBQ_STATUS: - case ERROR_ESBC_CLIENT_HASH_COMPARE_KEY: - case ERROR_ESBC_CLIENT_HASH_COMPARE_EM: - fsl_secboot_image_verification_failure(); - break; - case ERROR_ESBC_MISSING_BOOTM: - fsl_secboot_bootscript_parse_failure(); - break; - case ERROR_ESBC_WRONG_CMD: - default: - branch_to_self(); - break; - } -} - -static void fsl_secblk_handle_error(int error) -{ - switch (error) { - case ERROR_ESBC_SEC_ENQ: - fsl_secboot_handle_error(ERROR_ESBC_SEC_ENQ); - break; - case ERROR_ESBC_SEC_DEQ: - fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ); - break; - case ERROR_ESBC_SEC_DEQ_TO: - fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ_TO); - break; - default: - printf("Job Queue Output status %x\n", error); - fsl_secboot_handle_error(ERROR_ESBC_SEC_JOBQ_STATUS); - break; - } -} - -/* - * Calculate hash of key obtained via offset present in ESBC uboot - * client hdr. This function calculates the hash of key which is obtained - * through offset present in ESBC uboot client header. - */ -static int calc_img_key_hash(struct fsl_secboot_img_priv *img) -{ - struct hash_algo *algo; - void *ctx; - int i, srk = 0; - int ret = 0; - const char *algo_name = "sha256"; - - /* Calculate hash of the esbc key */ - ret = hash_progressive_lookup_algo(algo_name, &algo); - if (ret) - return ret; - - ret = algo->hash_init(algo, &ctx); - if (ret) - return ret; - /* Update hash for ESBC key */ -#ifdef CONFIG_KEY_REVOCATION - if (check_srk(img)) { - ret = algo->hash_update(algo, ctx, - (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off), - img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1); - srk = 1; - } -#endif - if (!srk) - ret = algo->hash_update(algo, ctx, - img->img_key, img->key_len, 1); - if (ret) - return ret; - /* Copy hash at destination buffer */ - ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size); - if (ret) { - free(ctx); - return ret; - } - for (i = 0; i < SHA256_BYTES; i++) - img->img_key_hash[i] = hash_val[i]; - - return 0; -} - -/* - * Calculate hash of ESBC hdr and ESBC. This function calculates the - * single hash of ESBC header and ESBC image. If SG flag is on, all - * SG entries are also hashed alongwith the complete SG table. - */ -static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) -{ - struct hash_algo *algo; - void *ctx; - int ret = 0; - int key_hash = 0; - const char *algo_name = "sha256"; - - /* Calculate the hash of the ESBC */ - ret = hash_progressive_lookup_algo(algo_name, &algo); - if (ret) - return ret; - - ret = algo->hash_init(algo, &ctx); - /* Copy hash at destination buffer */ - if (ret) - return ret; - - /* Update hash for CSF Header */ - ret = algo->hash_update(algo, ctx, - (u8 *)&img->hdr, sizeof(struct fsl_secboot_img_hdr), 0); - if (ret) - return ret; - - /* Update the hash with that of srk table if srk flag is 1 - * If IE Table is selected, key is not added in the hash - * If neither srk table nor IE key table available, add key - * from header in the hash calculation - */ -#ifdef CONFIG_KEY_REVOCATION - if (check_srk(img)) { - ret = algo->hash_update(algo, ctx, - (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off), - img->hdr.len_kr.num_srk * sizeof(struct srk_table), 0); - key_hash = 1; - } -#endif -#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) - if (!key_hash && check_ie(img)) - key_hash = 1; -#endif -#ifndef CONFIG_ESBC_HDR_LS -/* No single key support in LS ESBC header */ - if (!key_hash) { - ret = algo->hash_update(algo, ctx, - img->img_key, img->hdr.key_len, 0); - key_hash = 1; - } -#endif - if (ret) - return ret; - if (!key_hash) { - free(ctx); - return ERROR_KEY_TABLE_NOT_FOUND; - } - /* Update hash for actual Image */ - ret = algo->hash_update(algo, ctx, - (u8 *)(*(img->img_addr_ptr)), img->img_size, 1); - if (ret) - return ret; - - /* Copy hash at destination buffer */ - ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size); - if (ret) { - free(ctx); - return ret; - } - return 0; -} - -/* - * Construct encoded hash EM' wrt PKCSv1.5. This function calculates the - * pointers for padding, DER value and hash. And finally, constructs EM' - * which includes hash of complete CSF header and ESBC image. If SG flag - * is on, hash of SG table and entries is also included. - */ -static void construct_img_encoded_hash_second(struct fsl_secboot_img_priv *img) -{ - /* - * RSA PKCSv1.5 encoding format for encoded message is below - * EM = 0x0 || 0x1 || PS || 0x0 || DER || Hash - * PS is Padding String - * DER is DER value for SHA-256 - * Hash is SHA-256 hash - * ********************************************************* - * representative points to first byte of EM initially and is - * filled with 0x0 - * representative is incremented by 1 and second byte is filled - * with 0x1 - * padding points to third byte of EM - * digest points to full length of EM - 32 bytes - * hash_id (DER value) points to 19 bytes before pDigest - * separator is one byte which separates padding and DER - */ - - size_t len; - u8 *representative; - u8 *padding, *digest; - u8 *hash_id, *separator; - int i; - - len = (get_key_len(img) / 2) - 1; - representative = img->img_encoded_hash_second; - representative[0] = 0; - representative[1] = 1; /* block type 1 */ - - padding = &representative[2]; - digest = &representative[1] + len - 32; - hash_id = digest - sizeof(hash_identifier); - separator = hash_id - 1; - - /* fill padding area pointed by padding with 0xff */ - memset(padding, 0xff, separator - padding); - - /* fill byte pointed by separator */ - *separator = 0; - - /* fill SHA-256 DER value pointed by HashId */ - memcpy(hash_id, hash_identifier, sizeof(hash_identifier)); - - /* fill hash pointed by Digest */ - for (i = 0; i < SHA256_BYTES; i++) - digest[i] = hash_val[i]; -} - -/* - * Reads and validates the ESBC client header. - * This function reads key and signature from the ESBC client header. - * If Scatter/Gather flag is on, lengths and offsets of images - * present as SG entries are also read. This function also checks - * whether the header is valid or not. - */ -static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) -{ - struct fsl_secboot_img_hdr *hdr = &img->hdr; - void *esbc = (u8 *)(uintptr_t)img->ehdrloc; - u8 *k, *s; - u32 ret = 0; - - int key_found = 0; - - /* check barker code */ - if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN)) - return ERROR_ESBC_CLIENT_HEADER_BARKER; - - /* If Image Address is not passed as argument to function, - * then Address and Size must be read from the Header. - */ - if (*(img->img_addr_ptr) == 0) { - #ifdef CONFIG_ESBC_ADDR_64BIT - *(img->img_addr_ptr) = hdr->pimg64; - #else - *(img->img_addr_ptr) = hdr->pimg; - #endif - } - - if (!hdr->img_size) - return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE; - - img->img_size = hdr->img_size; - - /* Key checking*/ -#ifdef CONFIG_KEY_REVOCATION - if (check_srk(img)) { - ret = read_validate_srk_tbl(img); - if (ret != 0) - return ret; - key_found = 1; - } -#endif - -#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) - if (!key_found && check_ie(img)) { - ret = read_validate_ie_tbl(img); - if (ret != 0) - return ret; - key_found = 1; - } -#endif -#ifndef CONFIG_ESBC_HDR_LS -/* Single Key Feature not available in LS ESBC Header */ - if (key_found == 0) { - ret = read_validate_single_key(img); - if (ret != 0) - return ret; - key_found = 1; - } -#endif - if (!key_found) - return ERROR_KEY_TABLE_NOT_FOUND; - - /* check signaure */ - if (get_key_len(img) == 2 * hdr->sign_len) { - /* check signature length */ - if (!((hdr->sign_len == KEY_SIZE_BYTES / 4) || - (hdr->sign_len == KEY_SIZE_BYTES / 2) || - (hdr->sign_len == KEY_SIZE_BYTES))) - return ERROR_ESBC_CLIENT_HEADER_SIG_LEN; - } else { - return ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN; - } - - memcpy(&img->img_sign, esbc + hdr->psign, hdr->sign_len); -/* No SG support in LS-CH3 */ -#ifndef CONFIG_ESBC_HDR_LS - /* No SG support */ - if (hdr->sg_flag) - return ERROR_ESBC_CLIENT_HEADER_SG; -#endif - - /* modulus most significant bit should be set */ - k = (u8 *)&img->img_key; - - if ((k[0] & 0x80) == 0) - return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1; - - /* modulus value should be odd */ - if ((k[get_key_len(img) / 2 - 1] & 0x1) == 0) - return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2; - - /* Check signature value < modulus value */ - s = (u8 *)&img->img_sign; - - if (!(memcmp(s, k, hdr->sign_len) < 0)) - return ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD; - - return ESBC_VALID_HDR; -} - -static inline int str2longbe(const char *p, ulong *num) -{ - char *endptr; - ulong tmp; - - if (!p) { - return 0; - } else { - tmp = hextoul(p, &endptr); - if (sizeof(ulong) == 4) - *num = cpu_to_be32(tmp); - else - *num = cpu_to_be64(tmp); - } - - return *p != '\0' && *endptr == '\0'; -} -/* Function to calculate the ESBC Image Hash - * and hash from Digital signature. - * The Two hash's are compared to yield the - * result of signature validation. - */ -static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img) -{ - int ret; - uint32_t key_len; - struct key_prop prop; -#if !defined(USE_HOSTCC) - struct udevice *mod_exp_dev; -#endif - ret = calc_esbchdr_esbc_hash(img); - if (ret) - return ret; - - /* Construct encoded hash EM' wrt PKCSv1.5 */ - construct_img_encoded_hash_second(img); - - /* Fill prop structure for public key */ - memset(&prop, 0, sizeof(struct key_prop)); - key_len = get_key_len(img) / 2; - prop.modulus = img->img_key; - prop.public_exponent = img->img_key + key_len; - prop.num_bits = key_len * 8; - prop.exp_len = key_len; - -#if defined(CONFIG_XPL_BUILD) - ret = device_bind_driver(NULL, "fsl_rsa_mod_exp", "fsl_rsa_mod_exp", NULL); - if (ret) { - printf("Couldn't bind fsl_rsa_mod_exp driver (%d)\n", ret); - return -EINVAL; - } -#endif - ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev); - if (ret) { - printf("RSA: Can't find Modular Exp implementation\n"); - return -EINVAL; - } - - ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len, - &prop, img->img_encoded_hash); - if (ret) - return ret; - - /* - * compare the encoded messages EM' and EM wrt RSA PKCSv1.5 - * memcmp returns zero on success - * memcmp returns non-zero on failure - */ - ret = memcmp(&img->img_encoded_hash_second, &img->img_encoded_hash, - img->hdr.sign_len); - - if (ret) - return ERROR_ESBC_CLIENT_HASH_COMPARE_EM; - - return 0; -} -/* Function to initialize img priv and global data structure - */ -static int secboot_init(struct fsl_secboot_img_priv **img_ptr) -{ - *img_ptr = malloc(sizeof(struct fsl_secboot_img_priv)); - - struct fsl_secboot_img_priv *img = *img_ptr; - - if (!img) - return -ENOMEM; - memset(img, 0, sizeof(struct fsl_secboot_img_priv)); - -#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) - if (glb.ie_addr) - img->ie_addr = glb.ie_addr; -#endif - return 0; -} - -/* haddr - Address of the header of image to be validated. - * arg_hash_str - Option hash string. If provided, this - * overrides the key hash in the SFP fuses. - * img_addr_ptr - Optional pointer to address of image to be validated. - * If non zero addr, this overrides the addr of image in header, - * otherwise updated to image addr in header. - * Acts as both input and output of function. - * This pointer shouldn't be NULL. - */ -int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, - uintptr_t *img_addr_ptr) -{ - struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); - ulong hash[SHA256_BYTES/sizeof(ulong)]; - char hash_str[NUM_HEX_CHARS + 1]; - struct fsl_secboot_img_priv *img; - struct fsl_secboot_img_hdr *hdr; - void *esbc; - int ret, i, hash_cmd = 0; - u32 srk_hash[8]; - - if (strlen(arg_hash_str) != 0) { - const char *cp = arg_hash_str; - int i = 0; - - if (*cp == '0' && *(cp + 1) == 'x') - cp += 2; - - /* The input string expected is in hex, where - * each 4 bits would be represented by a hex - * sha256 hash is 256 bits long, which would mean - * num of characters = 256 / 4 - */ - if (strlen(cp) != SHA256_NIBBLES) { - printf("%s is not a 256 bits hex string as expected\n", - arg_hash_str); - return -1; - } - - for (i = 0; i < sizeof(hash)/sizeof(ulong); i++) { - strncpy(hash_str, cp + (i * NUM_HEX_CHARS), - NUM_HEX_CHARS); - hash_str[NUM_HEX_CHARS] = '\0'; - if (!str2longbe(hash_str, &hash[i])) { - printf("%s is not a 256 bits hex string ", - arg_hash_str); - return -1; - } - } - - hash_cmd = 1; - } - - ret = secboot_init(&img); - if (ret) - goto exit; - - /* Update the information in Private Struct */ - hdr = &img->hdr; - img->ehdrloc = haddr; - img->img_addr_ptr = img_addr_ptr; - esbc = (u8 *)img->ehdrloc; - - memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr)); - - /* read and validate esbc header */ - ret = read_validate_esbc_client_header(img); - - if (ret != ESBC_VALID_HDR) { - fsl_secboot_handle_error(ret); - goto exit; - } - - /* SRKH present in SFP */ - for (i = 0; i < NUM_SRKH_REGS; i++) - srk_hash[i] = srk_in32(&sfp_regs->srk_hash[i]); - - /* - * Calculate hash of key obtained via offset present in - * ESBC uboot client hdr - */ - ret = calc_img_key_hash(img); - if (ret) { - fsl_secblk_handle_error(ret); - goto exit; - } - - /* Compare hash obtained above with SRK hash present in SFP */ - if (hash_cmd) - ret = memcmp(&hash, &img->img_key_hash, SHA256_BYTES); - else - ret = memcmp(srk_hash, img->img_key_hash, SHA256_BYTES); - -#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) - if (!hash_cmd && check_ie(img)) - ret = 0; -#endif - - if (ret != 0) { - fsl_secboot_handle_error(ERROR_ESBC_CLIENT_HASH_COMPARE_KEY); - goto exit; - } - - ret = calculate_cmp_img_sig(img); - if (ret) { - fsl_secboot_handle_error(ret); - goto exit; - } - -exit: - /* Free Img as it was malloc'ed*/ - free(img); - return ret; -} diff --git a/board/freescale/common/i2c_common.c b/board/freescale/common/i2c_common.c deleted file mode 100644 index 20705ecc8e4..00000000000 --- a/board/freescale/common/i2c_common.c +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2020-21 NXP - * Copyright 2021 Microsoft Corporation - */ - -#include -#include -#include "i2c_common.h" - -#if CONFIG_IS_ENABLED(DM_I2C) - -/* If DM is in use, retrieve the chip for the specified bus number */ -int fsl_i2c_get_device(int address, int bus, DEVICE_HANDLE_T *dev) -{ - int ret = i2c_get_chip_for_busnum(bus, address, 1, dev); - - if (ret) - printf("I2C: Bus %d has no device with address 0x%02X\n", - bus, address); - return ret; -} - -#else - -/* Handle is passed directly */ -int fsl_i2c_get_device(int address, int bus, DEVICE_HANDLE_T *dev) -{ - *dev = address; - return 0; -} - -#endif diff --git a/board/freescale/common/i2c_common.h b/board/freescale/common/i2c_common.h deleted file mode 100644 index 77a7b6aedd7..00000000000 --- a/board/freescale/common/i2c_common.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2020-21 NXP - * Copyright 2021 Microsoft Corporation - */ - -#ifndef __NXP_I2C_COMMON_H__ -#define __NXP_I2C_COMMON_H__ - -/* Common functionality shared by the I2C drivers for VID and the mux. */ -#if CONFIG_IS_ENABLED(DM_I2C) -#define DEVICE_HANDLE_T struct udevice * - -#define I2C_READ(dev, register, data, length) \ - dm_i2c_read(dev, register, data, length) -#define I2C_WRITE(dev, register, data, length) \ - dm_i2c_write(dev, register, data, length) -#else -#define DEVICE_HANDLE_T int - -#define I2C_READ(dev, register, data, length) \ - i2c_read(dev, register, 1, data, length) -#define I2C_WRITE(dev, register, data, length) \ - i2c_write(dev, register, 1, data, length) -#endif - -int fsl_i2c_get_device(int address, int bus, DEVICE_HANDLE_T *dev); - -#endif diff --git a/board/freescale/common/i2c_mux.c b/board/freescale/common/i2c_mux.c deleted file mode 100644 index 89151ccaf06..00000000000 --- a/board/freescale/common/i2c_mux.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2020-21 NXP - * Copyright 2021 Microsoft Corporation - */ - -#include -#include -#include -#include "i2c_common.h" -#include "i2c_mux.h" - -/* - * A new Kconfig option for something that used to always be built should be - * "default y". - */ -#ifdef CONFIG_FSL_USE_PCA9547_MUX - -int select_i2c_ch_pca9547(u8 ch, int bus) -{ - int ret; - DEVICE_HANDLE_T dev; - - /* Open device handle */ - ret = fsl_i2c_get_device(I2C_MUX_PCA_ADDR_PRI, bus, &dev); - if (ret) { - printf("PCA: No PCA9547 device found\n"); - return ret; - } - - ret = I2C_WRITE(dev, 0, &ch, sizeof(ch)); - if (ret) { - printf("PCA: Unable to select channel %d (%d)\n", (int)ch, ret); - return ret; - } - - return 0; -} - -#endif diff --git a/board/freescale/common/i2c_mux.h b/board/freescale/common/i2c_mux.h deleted file mode 100644 index 0870c1918e6..00000000000 --- a/board/freescale/common/i2c_mux.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2020-21 NXP - * Copyright 2021 Microsoft Corporation - */ - -#ifndef __NXP_I2C_MUX_H__ -#define __NXP_I2C_MUX_H__ - -#ifdef CONFIG_FSL_USE_PCA9547_MUX -int select_i2c_ch_pca9547(u8 ch, int bus); -#endif - -#endif diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c deleted file mode 100644 index af30faa0c5f..00000000000 --- a/board/freescale/common/ics307_clk.c +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include - -#include "ics307_clk.h" - -#if defined(CONFIG_FSL_NGPIXIS) -#include "ngpixis.h" -#define fpga_reg pixis -#elif defined(CONFIG_FSL_QIXIS) -#include "qixis.h" -#define fpga_reg ((struct qixis *)QIXIS_BASE) -#else -#include "pixis.h" -#define fpga_reg pixis -#endif - -/* define for SYS CLK or CLK1Frequency */ -#define TTL 1 -#define CLK2 0 -#define CRYSTAL 0 -#define MAX_VDW (511 + 8) -#define MAX_RDW (127 + 2) -#define MIN_VDW (4 + 8) -#define MIN_RDW (1 + 2) -#define NUM_OD_SETTING 8 -/* - * These defines cover the industrial temperature range part, - * for commercial, change below to 400000 and 55000, respectively - */ -#define MAX_VCO 360000 -#define MIN_VCO 60000 - -/* decode S[0-2] to Output Divider (OD) */ -static u8 ics307_s_to_od[] = { - 10, 2, 8, 4, 5, 7, 3, 6 -}; - -/* - * Find one solution to generate required frequency for SYSCLK - * out_freq: KHz, required frequency to the SYSCLK - * the result will be retuned with component RDW, VDW, OD, TTL, - * CLK2 and crystal - */ -unsigned long ics307_sysclk_calculator(unsigned long out_freq) -{ - const unsigned long input_freq = CFG_ICS307_REFCLK_HZ; - unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od; - unsigned long tmp_out, diff, result = 0; - int found = 0; - - for (odp = 0; odp < NUM_OD_SETTING; odp++) { - od = ics307_s_to_od[odp]; - if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO) - continue; - for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) { - /* Calculate the VDW */ - vdw = out_freq * 1000 * od * rdw / (input_freq * 2); - if (vdw > MAX_VDW) - vdw = MAX_VDW; - if (vdw < MIN_VDW) - continue; - /* Calculate the temp out frequency */ - tmp_out = input_freq * 2 * vdw / (rdw * od * 1000); - diff = max(out_freq, tmp_out) - min(out_freq, tmp_out); - /* - * calculate the percent, the precision is 1/1000 - * If greater than 1/1000, continue - * otherwise, we think the solution is we required - */ - if (diff * 1000 / out_freq > 1) - continue; - else { - s_vdw = vdw; - s_rdw = rdw; - s_odp = odp; - found = 1; - break; - } - } - } - - if (found) - result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 | - CLK2 << 19 | TTL << 21 | CRYSTAL << 22; - - debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8, - ics307_s_to_od[s_odp]); - return result; -} - -/* - * Calculate frequency being generated by ICS307-02 clock chip based upon - * the control bytes being programmed into it. - */ -static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2) -{ - const unsigned long input_freq = CFG_ICS307_REFCLK_HZ; - unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); - unsigned long rdw = cw2 & 0x7F; - unsigned long od = ics307_s_to_od[cw0 & 0x7]; - unsigned long freq; - - /* - * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD) - * - * cw0: C1 C0 TTL F1 F0 S2 S1 S0 - * cw1: V8 V7 V6 V5 V4 V3 V2 V1 - * cw2: V0 R6 R5 R4 R3 R2 R1 R0 - * - * R6:R0 = Reference Divider Word (RDW) - * V8:V0 = VCO Divider Word (VDW) - * S2:S0 = Output Divider Select (OD) - * F1:F0 = Function of CLK2 Output - * TTL = duty cycle - * C1:C0 = internal load capacitance for cyrstal - * - */ - - freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od); - - debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2, - freq); - return freq; -} - -unsigned long get_board_sys_clk(void) -{ - return ics307_clk_freq( - in_8(&fpga_reg->sclk[0]), - in_8(&fpga_reg->sclk[1]), - in_8(&fpga_reg->sclk[2])); -} - -#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ -unsigned long get_board_ddr_clk(void) -{ - return ics307_clk_freq( - in_8(&fpga_reg->dclk[0]), - in_8(&fpga_reg->dclk[1]), - in_8(&fpga_reg->dclk[2])); -} -#endif diff --git a/board/freescale/common/ics307_clk.h b/board/freescale/common/ics307_clk.h deleted file mode 100644 index 163496930c8..00000000000 --- a/board/freescale/common/ics307_clk.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ -#ifndef __ICS_CLK_H_ -#define __ICS_CLK_H_ 1 - -#ifndef __ASSEMBLY__ - -extern unsigned long get_board_sys_clk(void); -extern unsigned long ics307_sysclk_calculator(unsigned long out_freq); -#endif - -#endif /* __ICS_CLK_H_ */ diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c deleted file mode 100644 index bf76274c43c..00000000000 --- a/board/freescale/common/ls102xa_stream_id.c +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor - */ - -#include -#include -#include - -void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num) -{ - void *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; - int i; - u32 icid; - - for (i = 0; i < num; i++) { - icid = (id[i].stream_id & 0xff) << 24; - out_be32((u32 *)(scfg + id[i].offset), icid); - } -} - -void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size) -{ - int i; - u32 liodn; - - for (i = 0; i < size; i++) { - if (tbl[i].num_ids == 2) - liodn = (tbl[i].id[0] << 16) | tbl[i].id[1]; - else - liodn = tbl[i].id[0]; - - out_le32((u32 *)(tbl[i].reg_offset), liodn); - } -} diff --git a/board/freescale/common/mc34vr500.c b/board/freescale/common/mc34vr500.c deleted file mode 100644 index cf14b29a3ec..00000000000 --- a/board/freescale/common/mc34vr500.c +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Hou Zhiqiang - */ - -#include -#include -#include -#include -#include - -static uint8_t swxvolt_addr[4] = { MC34VR500_SW1VOLT, - MC34VR500_SW2VOLT, - MC34VR500_SW3VOLT, - MC34VR500_SW4VOLT }; - -static uint8_t swx_set_point_base[4] = { 13, 9, 9, 9 }; - -int mc34vr500_get_sw_volt(uint8_t sw) -{ - struct pmic *p; - u32 swxvolt; - uint8_t spb; - int sw_volt; - int ret; - - debug("%s: Get SW%u volt from swxvolt_addr = 0x%x\n", - __func__, sw + 1, swxvolt_addr[sw]); - if (sw > SW4) { - printf("%s: Unsupported SW(sw%d)\n", __func__, sw + 1); - return -EINVAL; - } - - p = pmic_get("MC34VR500"); - if (!p) { - printf("%s: Did NOT find PMIC MC34VR500\n", __func__); - return -ENODEV; - } - - ret = pmic_probe(p); - if (ret) - return ret; - - ret = pmic_reg_read(p, swxvolt_addr[sw], &swxvolt); - if (ret) { - printf("%s: Failed to get SW%u volt\n", __func__, sw + 1); - return ret; - } - - debug("%s: SW%d step point swxvolt = %u\n", __func__, sw + 1, swxvolt); - spb = swx_set_point_base[sw]; - /* The base of SW volt is 625mV and increase by step 25mV */ - sw_volt = 625 + (swxvolt - spb) * 25; - - debug("%s: SW%u volt = %dmV\n", __func__, sw + 1, sw_volt); - return sw_volt; -} - -int mc34vr500_set_sw_volt(uint8_t sw, int sw_volt) -{ - struct pmic *p; - u32 swxvolt; - uint8_t spb; - int ret; - - debug("%s: Set SW%u volt to %dmV\n", __func__, sw + 1, sw_volt); - /* The least SW volt is 625mV, and only 4 SW outputs */ - if (sw > SW4 || sw_volt < 625) - return -EINVAL; - - p = pmic_get("MC34VR500"); - if (!p) { - printf("%s: Did NOT find PMIC MC34VR500\n", __func__); - return -ENODEV; - } - - ret = pmic_probe(p); - if (ret) - return ret; - - spb = swx_set_point_base[sw]; - /* The base of SW volt is 625mV and increase by step 25mV */ - swxvolt = (sw_volt - 625) / 25 + spb; - debug("%s: SW%d step point swxvolt = %u\n", __func__, sw + 1, swxvolt); - if (swxvolt > 63) - return -EINVAL; - - ret = pmic_reg_write(p, swxvolt_addr[sw], swxvolt); - if (ret) - return ret; - - return 0; -} diff --git a/board/freescale/common/mmc.c b/board/freescale/common/mmc.c deleted file mode 100644 index 00e4f3675fe..00000000000 --- a/board/freescale/common/mmc.c +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2018-2022 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -static int check_mmc_autodetect(void) -{ - char *autodetect_str = env_get("mmcautodetect"); - - if (autodetect_str && !strcmp(autodetect_str, "yes")) - return 1; - - return 0; -} - -/* This should be defined for each board */ -__weak int mmc_map_to_kernel_blk(int dev_no) -{ - return dev_no; -} - -void board_late_mmc_env_init(void) -{ - char cmd[32]; - char mmcblk[32]; - u32 dev_no = mmc_get_env_dev(); - - if (!check_mmc_autodetect()) - return; - - env_set_ulong("mmcdev", dev_no); - - /* Set mmcblk env */ - sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", mmc_map_to_kernel_blk(dev_no)); - env_set("mmcroot", mmcblk); - - sprintf(cmd, "mmc dev %d", dev_no); - run_command(cmd, 0); -} diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c deleted file mode 100644 index d4ca278e883..00000000000 --- a/board/freescale/common/mpc85xx_sleep.c +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include "sleep.h" -#ifdef CONFIG_U_QE -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -void __weak board_mem_sleep_setup(void) -{ -} - -void __weak board_sleep_prepare(void) -{ -} - -bool is_warm_boot(void) -{ - struct ccsr_gur __iomem *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; - - if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR) - return 1; - - return 0; -} - -void fsl_dp_disable_console(void) -{ - gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; -} - -/* - * When wakeup from deep sleep, the first 128 bytes space - * will be used to do DDR training which corrupts the data - * in there. This function will restore them. - */ -static void dp_ddr_restore(void) -{ - u64 *src, *dst; - int i; - struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85xx_SCFG; - - /* get the address of ddr date from SPARECR3 */ - src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8); - dst = (u64 *)(CFG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8); - - for (i = 0; i < DDR_BUFF_LEN / 8; i++) - *dst-- = *src--; - - flush_dcache(); -} - -static void dp_resume_prepare(void) -{ - dp_ddr_restore(); - - board_sleep_prepare(); - - l2cache_init(); -#if defined(CONFIG_RAMBOOT_PBL) - disable_cpc_sram(); -#endif - enable_cpc(); - -#ifdef CONFIG_U_QE - u_qe_resume(); -#endif - -} - -int fsl_dp_resume(void) -{ - u32 start_addr; - void (*kernel_resume)(void); - struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85xx_SCFG; - - if (!is_warm_boot()) - return 0; - - dp_resume_prepare(); - - /* Get the entry address and jump to kernel */ - start_addr = in_be32(&scfg->sparecr[1]); - debug("Entry address is 0x%08x\n", start_addr); - kernel_resume = (void (*)(void))start_addr; - kernel_resume(); - - return 0; -} diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c deleted file mode 100644 index 74c345807e6..00000000000 --- a/board/freescale/common/ngpixis.c +++ /dev/null @@ -1,247 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/** - * Copyright 2010-2011 Freescale Semiconductor - * Author: Timur Tabi - * - * This file provides support for the ngPIXIS, a board-specific FPGA used on - * some Freescale reference boards. - * - * A "switch" is black rectangular block on the motherboard. It contains - * eight "bits". The ngPIXIS has a set of memory-mapped registers (SWx) that - * shadow the actual physical switches. There is also another set of - * registers (ENx) that tell the ngPIXIS which bits of SWx should actually be - * used to override the values of the bits in the physical switches. - * - * The following macros need to be defined: - * - * PIXIS_BASE - The virtual address of the base of the PIXIS register map - * - * PIXIS_LBMAP_SWITCH - The switch number (i.e. the "x" in "SWx"). This value - * is used in the PIXIS_SW() macro to determine which offset in - * the PIXIS register map corresponds to the physical switch that controls - * the boot bank. - * - * PIXIS_LBMAP_MASK - A bit mask the defines which bits in SWx to use. - * - * PIXIS_LBMAP_SHIFT - The shift value that corresponds to PIXIS_LBMAP_MASK. - * - * PIXIS_LBMAP_ALTBANK - The value to program into SWx to tell the ngPIXIS to - * boot from the alternate bank. - */ - -#include -#include - -#include "ngpixis.h" - -static u8 __pixis_read(unsigned int reg) -{ - void *p = (void *)PIXIS_BASE; - - return in_8(p + reg); -} -u8 pixis_read(unsigned int reg) __attribute__((weak, alias("__pixis_read"))); - -static void __pixis_write(unsigned int reg, u8 value) -{ - void *p = (void *)PIXIS_BASE; - - out_8(p + reg, value); -} -void pixis_write(unsigned int reg, u8 value) - __attribute__((weak, alias("__pixis_write"))); - -/* - * Reset the board. This ignores the ENx registers. - */ -void __pixis_reset(void) -{ - PIXIS_WRITE(rst, 0); - - while (1); -} -void pixis_reset(void) __attribute__((weak, alias("__pixis_reset"))); - -/* - * Reset the board. Like pixis_reset(), but it honors the ENx registers. - */ -void __pixis_bank_reset(void) -{ - PIXIS_WRITE(vctl, 0); - PIXIS_WRITE(vctl, 1); - - while (1); -} -void pixis_bank_reset(void) __attribute__((weak, alias("__pixis_bank_reset"))); - -/** - * Set the boot bank to the power-on default bank - */ -void __clear_altbank(void) -{ - u8 reg; - - /* Tell the ngPIXIS to use this the bits in the physical switch for the - * boot bank value, instead of the SWx register. We need to be careful - * only to set the bits in SWx that correspond to the boot bank. - */ - reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].en); - reg &= ~PIXIS_LBMAP_MASK; - PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].en, reg); -} -void clear_altbank(void) __attribute__((weak, alias("__clear_altbank"))); - -/** - * Set the boot bank to the alternate bank - */ -void __set_altbank(void) -{ - u8 reg; - - /* Program the alternate bank number into the SWx register. - */ - reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].sw); - reg = (reg & ~PIXIS_LBMAP_MASK) | PIXIS_LBMAP_ALTBANK; - PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].sw, reg); - - /* Tell the ngPIXIS to use this the bits in the SWx register for the - * boot bank value, instead of the physical switch. We need to be - * careful only to set the bits in SWx that correspond to the boot bank. - */ - reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].en); - reg |= PIXIS_LBMAP_MASK; - PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].en, reg); -} -void set_altbank(void) __attribute__((weak, alias("__set_altbank"))); - -#ifdef DEBUG -static void pixis_dump_regs(void) -{ - unsigned int i; - - printf("id=%02x\n", PIXIS_READ(id)); - printf("arch=%02x\n", PIXIS_READ(arch)); - printf("scver=%02x\n", PIXIS_READ(scver)); - printf("csr=%02x\n", PIXIS_READ(csr)); - printf("rst=%02x\n", PIXIS_READ(rst)); - printf("aux=%02x\n", PIXIS_READ(aux)); - printf("spd=%02x\n", PIXIS_READ(spd)); - printf("brdcfg0=%02x\n", PIXIS_READ(brdcfg0)); - printf("brdcfg1=%02x\n", PIXIS_READ(brdcfg1)); - printf("addr=%02x\n", PIXIS_READ(addr)); - printf("data=%02x\n", PIXIS_READ(data)); - printf("led=%02x\n", PIXIS_READ(led)); - printf("vctl=%02x\n", PIXIS_READ(vctl)); - printf("vstat=%02x\n", PIXIS_READ(vstat)); - printf("vcfgen0=%02x\n", PIXIS_READ(vcfgen0)); - printf("ocmcsr=%02x\n", PIXIS_READ(ocmcsr)); - printf("ocmmsg=%02x\n", PIXIS_READ(ocmmsg)); - printf("gmdbg=%02x\n", PIXIS_READ(gmdbg)); - printf("sclk=%02x%02x%02x\n", - PIXIS_READ(sclk[0]), PIXIS_READ(sclk[1]), PIXIS_READ(sclk[2])); - printf("dclk=%02x%02x%02x\n", - PIXIS_READ(dclk[0]), PIXIS_READ(dclk[1]), PIXIS_READ(dclk[2])); - printf("watch=%02x\n", PIXIS_READ(watch)); - - for (i = 0; i < 8; i++) { - printf("SW%u=%02x/%02x ", i + 1, - PIXIS_READ(s[i].sw), PIXIS_READ(s[i].en)); - } - putc('\n'); -} -#endif - -void pixis_sysclk_set(unsigned long sysclk) -{ - unsigned long freq_word; - u8 sclk0, sclk1, sclk2; - - freq_word = ics307_sysclk_calculator(sysclk); - sclk2 = freq_word & 0xff; - sclk1 = (freq_word >> 8) & 0xff; - sclk0 = (freq_word >> 16) & 0xff; - - /* set SYSCLK enable bit */ - PIXIS_WRITE(vcfgen0, 0x01); - - /* SYSCLK to required frequency */ - PIXIS_WRITE(sclk[0], sclk0); - PIXIS_WRITE(sclk[1], sclk1); - PIXIS_WRITE(sclk[2], sclk2); -} - -int pixis_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - unsigned int i; - unsigned long sysclk; - char *p_altbank = NULL; -#ifdef DEBUG - char *p_dump = NULL; -#endif - char *unknown_param = NULL; - - /* No args is a simple reset request. - */ - if (argc <= 1) - pixis_reset(); - - for (i = 1; i < argc; i++) { - if (strcmp(argv[i], "altbank") == 0) { - p_altbank = argv[i]; - continue; - } - -#ifdef DEBUG - if (strcmp(argv[i], "dump") == 0) { - p_dump = argv[i]; - continue; - } -#endif - if (strcmp(argv[i], "sysclk") == 0) { - sysclk = simple_strtoul(argv[i + 1], NULL, 0); - i += 1; - pixis_sysclk_set(sysclk); - continue; - } - - unknown_param = argv[i]; - } - - if (unknown_param) { - printf("Invalid option: %s\n", unknown_param); - return 1; - } - -#ifdef DEBUG - if (p_dump) { - pixis_dump_regs(); - - /* 'dump' ignores other commands */ - return 0; - } -#endif - - if (p_altbank) - set_altbank(); - else - clear_altbank(); - - pixis_bank_reset(); - - /* Shouldn't be reached. */ - return 0; -} - -U_BOOT_LONGHELP(pixis, - "- hard reset to default bank\n" - "pixis_reset altbank - reset to alternate bank\n" -#ifdef DEBUG - "pixis_reset dump - display the PIXIS registers\n" -#endif - "pixis_reset sysclk - reset with SYSCLK frequency(KHz)\n"); - -U_BOOT_CMD( - pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd, - "Reset the board using the FPGA sequencer", pixis_help_text - ); diff --git a/board/freescale/common/ngpixis.h b/board/freescale/common/ngpixis.h deleted file mode 100644 index 7a20ee015fa..00000000000 --- a/board/freescale/common/ngpixis.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/** - * Copyright 2010-2011 Freescale Semiconductor - * Author: Timur Tabi - * - * This file provides support for the ngPIXIS, a board-specific FPGA used on - * some Freescale reference boards. - */ - -/* ngPIXIS register set. Hopefully, this won't change too much over time. - * Feel free to add board-specific #ifdefs where necessary. - */ -typedef struct ngpixis { - u8 id; - u8 arch; - u8 scver; - u8 csr; - u8 rst; - u8 serclk; - u8 aux; - u8 spd; - u8 brdcfg0; - u8 brdcfg1; /* On some boards, this register is called 'dma' */ - u8 addr; - u8 brdcfg2; - u8 gpiodir; - u8 data; - u8 led; - u8 tag; - u8 vctl; - u8 vstat; - u8 vcfgen0; - u8 res4; - u8 ocmcsr; - u8 ocmmsg; - u8 gmdbg; - u8 res5[2]; - u8 sclk[3]; - u8 dclk[3]; - u8 watch; - struct { - u8 sw; - u8 en; - } s[9]; /* s[0]..s[7] is SW1..SW8, and s[8] is SW11 */ -} __attribute__ ((packed)) ngpixis_t; - -/* Pointer to the PIXIS register set */ -#define pixis ((ngpixis_t *)PIXIS_BASE) - -/* The PIXIS SW register that corresponds to board switch X, where x >= 1 */ -#define PIXIS_SW(x) (pixis->s[(x) - 1].sw) - -/* The PIXIS EN register that corresponds to board switch X, where x >= 1 */ -#define PIXIS_EN(x) (pixis->s[(x) - 1].en) - -u8 pixis_read(unsigned int reg); -void pixis_write(unsigned int reg, u8 value); - -#define PIXIS_READ(reg) pixis_read(offsetof(ngpixis_t, reg)) -#define PIXIS_WRITE(reg, value) pixis_write(offsetof(ngpixis_t, reg), value) diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c deleted file mode 100644 index c46e87f4cce..00000000000 --- a/board/freescale/common/ns_access.c +++ /dev/null @@ -1,241 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor - */ - -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_ARCH_LS1021A -static struct csu_ns_dev ns_dev[] = { - { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, - { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, - { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, - { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, - { CSU_CSLX_OCRAM, CSU_ALL_RW }, - { CSU_CSLX_GIC, CSU_ALL_RW }, - { CSU_CSLX_PCIE1, CSU_ALL_RW }, - { CSU_CSLX_OCRAM2, CSU_ALL_RW }, - { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, - { CSU_CSLX_PCIE2, CSU_ALL_RW }, - { CSU_CSLX_SATA, CSU_ALL_RW }, - { CSU_CSLX_USB3, CSU_ALL_RW }, - { CSU_CSLX_SERDES, CSU_ALL_RW }, - { CSU_CSLX_QDMA, CSU_ALL_RW }, - { CSU_CSLX_LPUART2, CSU_ALL_RW }, - { CSU_CSLX_LPUART1, CSU_ALL_RW }, - { CSU_CSLX_LPUART4, CSU_ALL_RW }, - { CSU_CSLX_LPUART3, CSU_ALL_RW }, - { CSU_CSLX_LPUART6, CSU_ALL_RW }, - { CSU_CSLX_LPUART5, CSU_ALL_RW }, - { CSU_CSLX_DSPI2, CSU_ALL_RW }, - { CSU_CSLX_DSPI1, CSU_ALL_RW }, - { CSU_CSLX_QSPI, CSU_ALL_RW }, - { CSU_CSLX_ESDHC, CSU_ALL_RW }, - { CSU_CSLX_2D_ACE, CSU_ALL_RW }, - { CSU_CSLX_IFC, CSU_ALL_RW }, - { CSU_CSLX_I2C1, CSU_ALL_RW }, - { CSU_CSLX_USB2, CSU_ALL_RW }, - { CSU_CSLX_I2C3, CSU_ALL_RW }, - { CSU_CSLX_I2C2, CSU_ALL_RW }, - { CSU_CSLX_DUART2, CSU_ALL_RW }, - { CSU_CSLX_DUART1, CSU_ALL_RW }, - { CSU_CSLX_WDT2, CSU_ALL_RW }, - { CSU_CSLX_WDT1, CSU_ALL_RW }, - { CSU_CSLX_EDMA, CSU_ALL_RW }, - { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, - { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, - { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, - { CSU_CSLX_DDR, CSU_ALL_RW }, - { CSU_CSLX_QUICC, CSU_ALL_RW }, - { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, - { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, - { CSU_CSLX_SFP, CSU_ALL_RW }, - { CSU_CSLX_TMU, CSU_ALL_RW }, - { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, - { CSU_CSLX_RESERVED0, CSU_ALL_RW }, - { CSU_CSLX_ETSEC1, CSU_ALL_RW }, - { CSU_CSLX_SEC5_5, CSU_ALL_RW }, - { CSU_CSLX_ETSEC3, CSU_ALL_RW }, - { CSU_CSLX_ETSEC2, CSU_ALL_RW }, - { CSU_CSLX_GPIO2, CSU_ALL_RW }, - { CSU_CSLX_GPIO1, CSU_ALL_RW }, - { CSU_CSLX_GPIO4, CSU_ALL_RW }, - { CSU_CSLX_GPIO3, CSU_ALL_RW }, - { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, - { CSU_CSLX_CSU, CSU_ALL_RW }, - { CSU_CSLX_ASRC, CSU_ALL_RW }, - { CSU_CSLX_SPDIF, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, - { CSU_CSLX_SAI2, CSU_ALL_RW }, - { CSU_CSLX_SAI1, CSU_ALL_RW }, - { CSU_CSLX_SAI4, CSU_ALL_RW }, - { CSU_CSLX_SAI3, CSU_ALL_RW }, - { CSU_CSLX_FTM2, CSU_ALL_RW }, - { CSU_CSLX_FTM1, CSU_ALL_RW }, - { CSU_CSLX_FTM4, CSU_ALL_RW }, - { CSU_CSLX_FTM3, CSU_ALL_RW }, - { CSU_CSLX_FTM6, CSU_ALL_RW }, - { CSU_CSLX_FTM5, CSU_ALL_RW }, - { CSU_CSLX_FTM8, CSU_ALL_RW }, - { CSU_CSLX_FTM7, CSU_ALL_RW }, - { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, - { CSU_CSLX_EPU, CSU_ALL_RW }, - { CSU_CSLX_GDI, CSU_ALL_RW }, - { CSU_CSLX_DDI, CSU_ALL_RW }, - { CSU_CSLX_RESERVED1, CSU_ALL_RW }, - { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, - { CSU_CSLX_RESERVED2, CSU_ALL_RW }, -}; - -#else -static struct csu_ns_dev ns_dev[] = { - {CSU_CSLX_PCIE2_IO, CSU_ALL_RW}, - {CSU_CSLX_PCIE1_IO, CSU_ALL_RW}, - {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW}, - {CSU_CSLX_IFC_MEM, CSU_ALL_RW}, - {CSU_CSLX_OCRAM, CSU_ALL_RW}, - {CSU_CSLX_GIC, CSU_ALL_RW}, - {CSU_CSLX_PCIE1, CSU_ALL_RW}, - {CSU_CSLX_OCRAM2, CSU_ALL_RW}, - {CSU_CSLX_QSPI_MEM, CSU_ALL_RW}, - {CSU_CSLX_PCIE2, CSU_ALL_RW}, - {CSU_CSLX_SATA, CSU_ALL_RW}, - {CSU_CSLX_USB1, CSU_ALL_RW}, - {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW}, - {CSU_CSLX_PCIE3, CSU_ALL_RW}, - {CSU_CSLX_PCIE3_IO, CSU_ALL_RW}, - {CSU_CSLX_USB3, CSU_ALL_RW}, - {CSU_CSLX_USB2, CSU_ALL_RW}, - {CSU_CSLX_PFE, CSU_ALL_RW}, - {CSU_CSLX_SERDES, CSU_ALL_RW}, - {CSU_CSLX_QDMA, CSU_ALL_RW}, - {CSU_CSLX_LPUART2, CSU_ALL_RW}, - {CSU_CSLX_LPUART1, CSU_ALL_RW}, - {CSU_CSLX_LPUART4, CSU_ALL_RW}, - {CSU_CSLX_LPUART3, CSU_ALL_RW}, - {CSU_CSLX_LPUART6, CSU_ALL_RW}, - {CSU_CSLX_LPUART5, CSU_ALL_RW}, - {CSU_CSLX_DSPI1, CSU_ALL_RW}, - {CSU_CSLX_QSPI, CSU_ALL_RW}, - {CSU_CSLX_ESDHC, CSU_ALL_RW}, - {CSU_CSLX_IFC, CSU_ALL_RW}, - {CSU_CSLX_I2C1, CSU_ALL_RW}, - {CSU_CSLX_I2C3, CSU_ALL_RW}, - {CSU_CSLX_I2C2, CSU_ALL_RW}, - {CSU_CSLX_DUART2, CSU_ALL_RW}, - {CSU_CSLX_DUART1, CSU_ALL_RW}, - {CSU_CSLX_WDT2, CSU_ALL_RW}, - {CSU_CSLX_WDT1, CSU_ALL_RW}, - {CSU_CSLX_EDMA, CSU_ALL_RW}, - {CSU_CSLX_SYS_CNT, CSU_ALL_RW}, - {CSU_CSLX_DMA_MUX2, CSU_ALL_RW}, - {CSU_CSLX_DMA_MUX1, CSU_ALL_RW}, - {CSU_CSLX_DDR, CSU_ALL_RW}, - {CSU_CSLX_QUICC, CSU_ALL_RW}, - {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW}, - {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW}, - {CSU_CSLX_SFP, CSU_ALL_RW}, - {CSU_CSLX_TMU, CSU_ALL_RW}, - {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW}, - {CSU_CSLX_SCFG, CSU_ALL_RW}, - {CSU_CSLX_FM, CSU_ALL_RW}, - {CSU_CSLX_SEC5_5, CSU_ALL_RW}, - {CSU_CSLX_BM, CSU_ALL_RW}, - {CSU_CSLX_QM, CSU_ALL_RW}, - {CSU_CSLX_GPIO2, CSU_ALL_RW}, - {CSU_CSLX_GPIO1, CSU_ALL_RW}, - {CSU_CSLX_GPIO4, CSU_ALL_RW}, - {CSU_CSLX_GPIO3, CSU_ALL_RW}, - {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW}, - {CSU_CSLX_CSU, CSU_ALL_RW}, - {CSU_CSLX_IIC4, CSU_ALL_RW}, - {CSU_CSLX_WDT4, CSU_ALL_RW}, - {CSU_CSLX_WDT3, CSU_ALL_RW}, - {CSU_CSLX_ESDHC2, CSU_ALL_RW}, - {CSU_CSLX_WDT5, CSU_ALL_RW}, - {CSU_CSLX_SAI2, CSU_ALL_RW}, - {CSU_CSLX_SAI1, CSU_ALL_RW}, - {CSU_CSLX_SAI4, CSU_ALL_RW}, - {CSU_CSLX_SAI3, CSU_ALL_RW}, - {CSU_CSLX_FTM2, CSU_ALL_RW}, - {CSU_CSLX_FTM1, CSU_ALL_RW}, - {CSU_CSLX_FTM4, CSU_ALL_RW}, - {CSU_CSLX_FTM3, CSU_ALL_RW}, - {CSU_CSLX_FTM6, CSU_ALL_RW}, - {CSU_CSLX_FTM5, CSU_ALL_RW}, - {CSU_CSLX_FTM8, CSU_ALL_RW}, - {CSU_CSLX_FTM7, CSU_ALL_RW}, - {CSU_CSLX_DSCR, CSU_ALL_RW}, -}; -#endif - -void set_devices_ns_access(unsigned long index, u16 val) -{ - u32 *base = (u32 *)CFG_SYS_FSL_CSU_ADDR; - u32 *reg; - uint32_t tmp; - - reg = base + index / 2; - tmp = in_be32(reg); - if (index % 2 == 0) { - tmp &= 0x0000ffff; - tmp |= val << 16; - } else { - tmp &= 0xffff0000; - tmp |= val; - } - - out_be32(reg, tmp); -} - -static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) -{ - int i; - - for (i = 0; i < num; i++) - set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val); -} - -void enable_layerscape_ns_access(void) -{ -#ifdef CONFIG_ARM64 - if (current_el() == 3) -#endif - enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); -} - -void set_pcie_ns_access(int pcie, u16 val) -{ - switch (pcie) { -#ifdef CONFIG_PCIE1 - case PCIE1: - set_devices_ns_access(CSU_CSLX_PCIE1, val); - set_devices_ns_access(CSU_CSLX_PCIE1_IO, val); - return; -#endif -#ifdef CONFIG_PCIE2 - case PCIE2: - set_devices_ns_access(CSU_CSLX_PCIE2, val); - set_devices_ns_access(CSU_CSLX_PCIE2_IO, val); - return; -#endif -#ifdef CONFIG_PCIE3 - case PCIE3: - set_devices_ns_access(CSU_CSLX_PCIE3, val); - set_devices_ns_access(CSU_CSLX_PCIE3_IO, val); - return; -#endif - default: - debug("The PCIE%d doesn't exist!\n", pcie); - return; - } -} diff --git a/board/freescale/common/p_corenet/Makefile b/board/freescale/common/p_corenet/Makefile deleted file mode 100644 index ce156018a06..00000000000 --- a/board/freescale/common/p_corenet/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c deleted file mode 100644 index 83818d6d847..00000000000 --- a/board/freescale/common/p_corenet/law.c +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008-2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -#ifdef CFG_SYS_BMAN_MEM_PHYS - SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), -#endif -#ifdef CFG_SYS_QMAN_MEM_PHYS - SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), -#endif -#ifdef PIXIS_BASE_PHYS - SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), -#endif -#ifdef CPLD_BASE_PHYS - SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), -#endif -#ifdef CFG_SYS_DCSRBAR_PHYS - /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), -#endif -#ifdef CFG_SYS_NAND_BASE_PHYS - SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c deleted file mode 100644 index cebdedfa4a7..00000000000 --- a/board/freescale/common/p_corenet/tlb.c +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008-2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, - CFG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, - CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, - CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, - CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), -#ifdef CPLD_BASE - SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 0), -#endif - -#ifdef PIXIS_BASE - SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 0), -#endif - - /* TLB 1 */ - /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) - -#if !defined(CONFIG_NXP_ESBC) - /* - * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the - * SRAM is at 0xfff00000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), -#else - /* - * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot - * the physical address of the SRAM is at CFG_SYS_INIT_L3_ADDR, - * and virtual address is CONFIG_SYS_MONITOR_BASE - */ - - SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000, - CFG_SYS_INIT_L3_ADDR & 0xfff00000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), -#endif - -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) - /* - * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the - * space is at 0xfff00000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, - CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), -#else - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), - - /* *I*G* - Flash, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x40000000, - CFG_SYS_PCIE1_MEM_PHYS + 0x40000000, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x50000000, - CFG_SYS_PCIE1_MEM_PHYS + 0x50000000, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), - - /* Bman/Qman */ -#ifdef CFG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, - MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x00100000, - CFG_SYS_BMAN_MEM_PHYS + 0x00100000, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_1M, 1), -#endif -#ifdef CFG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, - MAS3_SW|MAS3_SR, 0, - 0, 11, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x00100000, - CFG_SYS_QMAN_MEM_PHYS + 0x00100000, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 12, BOOKE_PAGESZ_1M, 1), -#endif -#ifdef CFG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 13, BOOKE_PAGESZ_4M, 1), -#endif -#ifdef CFG_SYS_NAND_BASE - /* - * *I*G - NAND - * entry 14 and 15 has been used hard coded, they will be disabled - * in cpu_init_f, so we use entry 16 for nand. - */ - SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 16, BOOKE_PAGESZ_1M, 1), -#endif -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE - /* - * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for - * fetching ucode and ENV from master - */ - SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, - CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, - 0, 17, BOOKE_PAGESZ_1M, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c deleted file mode 100644 index 0d7a94fd232..00000000000 --- a/board/freescale/common/pfuze.c +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -#ifndef CONFIG_DM_PMIC_PFUZE100 -int pfuze_mode_init(struct pmic *p, u32 mode) -{ - unsigned char offset, i, switch_num; - u32 id; - int ret; - - pmic_reg_read(p, PFUZE100_DEVICEID, &id); - id = id & 0xf; - - if (id == 0) { - switch_num = 6; - offset = PFUZE100_SW1CMODE; - } else if (id == 1) { - switch_num = 4; - offset = PFUZE100_SW2MODE; - } else { - printf("Not supported, id=%d\n", id); - return -EINVAL; - } - - ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); - if (ret < 0) { - printf("Set SW1AB mode error!\n"); - return ret; - } - - for (i = 0; i < switch_num - 1; i++) { - ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); - if (ret < 0) { - printf("Set switch 0x%x mode error!\n", - offset + i * SWITCH_SIZE); - return ret; - } - } - - return ret; -} - -struct pmic *pfuze_common_init(unsigned char i2cbus) -{ - struct pmic *p; - int ret; - unsigned int reg; - - ret = power_pfuze100_init(i2cbus); - if (ret) - return NULL; - - p = pmic_get("PFUZE100"); - ret = pmic_probe(p); - if (ret) - return NULL; - - pmic_reg_read(p, PFUZE100_DEVICEID, ®); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); - - /* Set SW1AB stanby volage to 0.975V */ - pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); - reg &= ~SW1x_STBY_MASK; - reg |= SW1x_0_975V; - pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); - - /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE100_SW1ABCONF, ®); - reg &= ~SW1xCONF_DVSSPEED_MASK; - reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); - - /* Set SW1C standby voltage to 0.975V */ - pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); - reg &= ~SW1x_STBY_MASK; - reg |= SW1x_0_975V; - pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); - - /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE100_SW1CCONF, ®); - reg &= ~SW1xCONF_DVSSPEED_MASK; - reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(p, PFUZE100_SW1CCONF, reg); - - return p; -} -#elif defined(CONFIG_DM_PMIC) -int pfuze_mode_init(struct udevice *dev, u32 mode) -{ - unsigned char offset, i, switch_num; - u32 id; - int ret; - - id = pmic_reg_read(dev, PFUZE100_DEVICEID); - id = id & 0xf; - - if (id == 0) { - switch_num = 6; - offset = PFUZE100_SW1CMODE; - } else if (id == 1) { - switch_num = 4; - offset = PFUZE100_SW2MODE; - } else { - printf("Not supported, id=%d\n", id); - return -EINVAL; - } - - ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode); - if (ret < 0) { - printf("Set SW1AB mode error!\n"); - return ret; - } - - for (i = 0; i < switch_num - 1; i++) { - ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode); - if (ret < 0) { - printf("Set switch 0x%x mode error!\n", - offset + i * SWITCH_SIZE); - return ret; - } - } - - return ret; -} - -struct udevice *pfuze_common_init(void) -{ - struct udevice *dev; - int ret; - unsigned int reg, dev_id, rev_id; - - ret = pmic_get("pfuze100@8", &dev); - if (ret == -ENODEV) - return NULL; - - dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); - rev_id = pmic_reg_read(dev, PFUZE100_REVID); - printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); - - /* Set SW1AB stanby volage to 0.975V */ - reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); - reg &= ~SW1x_STBY_MASK; - reg |= SW1x_0_975V; - pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); - - /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); - reg &= ~SW1xCONF_DVSSPEED_MASK; - reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); - - /* Set SW1C standby voltage to 0.975V */ - reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); - reg &= ~SW1x_STBY_MASK; - reg |= SW1x_0_975V; - pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); - - /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ - reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); - reg &= ~SW1xCONF_DVSSPEED_MASK; - reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); - - return dev; -} -#endif diff --git a/board/freescale/common/pfuze.h b/board/freescale/common/pfuze.h deleted file mode 100644 index 45b49afaeb7..00000000000 --- a/board/freescale/common/pfuze.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __PFUZE_BOARD_HELPER__ -#define __PFUZE_BOARD_HELPER__ - -#ifdef CONFIG_DM_PMIC_PFUZE100 -struct udevice *pfuze_common_init(void); -int pfuze_mode_init(struct udevice *dev, u32 mode); -#else -struct pmic *pfuze_common_init(unsigned char i2cbus); -int pfuze_mode_init(struct pmic *p, u32 mode); -#endif - -#endif diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c deleted file mode 100644 index 04cad48f033..00000000000 --- a/board/freescale/common/qixis.c +++ /dev/null @@ -1,389 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011 Freescale Semiconductor - * Copyright 2020 NXP - * Author: Shengzhou Liu - * - * This file provides support for the QIXIS of some Freescale reference boards. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "qixis.h" - -#ifndef QIXIS_LBMAP_BRDCFG_REG -/* - * For consistency with existing platforms - */ -#define QIXIS_LBMAP_BRDCFG_REG 0x00 -#endif - -#ifndef QIXIS_RCFG_CTL_RECONFIG_IDLE -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#endif -#ifndef QIXIS_RCFG_CTL_RECONFIG_START -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#endif - -#ifdef CFG_SYS_I2C_FPGA_ADDR -u8 qixis_read_i2c(unsigned int reg) -{ -#if !CONFIG_IS_ENABLED(DM_I2C) - return i2c_reg_read(CFG_SYS_I2C_FPGA_ADDR, reg); -#else - struct udevice *dev; - - if (i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev)) - return 0xff; - - return dm_i2c_reg_read(dev, reg); -#endif -} - -void qixis_write_i2c(unsigned int reg, u8 value) -{ - u8 val = value; -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_reg_write(CFG_SYS_I2C_FPGA_ADDR, reg, val); -#else - struct udevice *dev; - - if (!i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev)) - dm_i2c_reg_write(dev, reg, val); -#endif - -} -#endif - -#ifdef QIXIS_BASE -u8 qixis_read(unsigned int reg) -{ - void *p = (void *)QIXIS_BASE; - - return in_8(p + reg); -} - -void qixis_write(unsigned int reg, u8 value) -{ - void *p = (void *)QIXIS_BASE; - - out_8(p + reg, value); -} -#endif - -u16 qixis_read_minor(void) -{ - u16 minor; - - /* this data is in little endian */ - QIXIS_WRITE(tagdata, 5); - minor = QIXIS_READ(tagdata); - QIXIS_WRITE(tagdata, 6); - minor += QIXIS_READ(tagdata) << 8; - - return minor; -} - -char *qixis_read_time(char *result) -{ - time_t time = 0; - int i; - - /* timestamp is in 32-bit big endian */ - for (i = 8; i <= 11; i++) { - QIXIS_WRITE(tagdata, i); - time = (time << 8) + QIXIS_READ(tagdata); - } - - return ctime_r(&time, result); -} - -char *qixis_read_tag(char *buf) -{ - int i; - char tag, *ptr = buf; - - for (i = 16; i <= 63; i++) { - QIXIS_WRITE(tagdata, i); - tag = QIXIS_READ(tagdata); - *(ptr++) = tag; - if (!tag) - break; - } - if (i > 63) - *ptr = '\0'; - - return buf; -} - -/* - * return the string of binary of u8 in the format of - * 1010 10_0. The masked bit is filled as underscore. - */ -const char *byte_to_binary_mask(u8 val, u8 mask, char *buf) -{ - char *ptr; - int i; - - ptr = buf; - for (i = 0x80; i > 0x08 ; i >>= 1, ptr++) - *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0'); - *(ptr++) = ' '; - for (i = 0x08; i > 0 ; i >>= 1, ptr++) - *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0'); - - *ptr = '\0'; - - return buf; -} - -#ifdef QIXIS_RST_FORCE_MEM -void board_assert_mem_reset(void) -{ - u8 rst; - - rst = QIXIS_READ(rst_frc[0]); - if (!(rst & QIXIS_RST_FORCE_MEM)) - QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM); -} - -void board_deassert_mem_reset(void) -{ - u8 rst; - - rst = QIXIS_READ(rst_frc[0]); - if (rst & QIXIS_RST_FORCE_MEM) - QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM); -} -#endif - -#ifndef CONFIG_XPL_BUILD -static void qixis_reset(void) -{ - QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET); -} - -#ifdef QIXIS_LBMAP_ALTBANK -static void qixis_bank_reset(void) -{ - QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); - QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); -} -#endif - -static void __maybe_unused set_lbmap(int lbmap) -{ - u8 reg; - - reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); - reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap; - QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg); -} - -static void __maybe_unused set_rcw_src(int rcw_src) -{ -#ifdef CONFIG_NXP_LSCH3_2 - QIXIS_WRITE(dutcfg[0], (rcw_src & 0xff)); -#else - u8 reg; - - reg = QIXIS_READ(dutcfg[1]); - reg = (reg & ~1) | (rcw_src & 1); - QIXIS_WRITE(dutcfg[1], reg); - QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff); -#endif -} - -static void qixis_dump_regs(void) -{ - int i; - - printf("id = %02x\n", QIXIS_READ(id)); - printf("arch = %02x\n", QIXIS_READ(arch)); - printf("scver = %02x\n", QIXIS_READ(scver)); - printf("model = %02x\n", QIXIS_READ(model)); - printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl)); - printf("aux = %02x\n", QIXIS_READ(aux)); - for (i = 0; i < 16; i++) - printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i])); - for (i = 0; i < 16; i++) - printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i])); - printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]), - QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2])); - printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]), - QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2])); - printf("aux = %02x\n", QIXIS_READ(aux)); - printf("watch = %02x\n", QIXIS_READ(watch)); - printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys)); - printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl)); - printf("present = %02x\n", QIXIS_READ(present)); - printf("present2 = %02x\n", QIXIS_READ(present2)); - printf("clk_spd = %02x\n", QIXIS_READ(clk_spd)); - printf("stat_dut = %02x\n", QIXIS_READ(stat_dut)); - printf("stat_sys = %02x\n", QIXIS_READ(stat_sys)); - printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm)); -} - -void __weak qixis_dump_switch(void) -{ - puts("Reverse engineering switch is not implemented for this board\n"); -} - -static int qixis_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - int i; - - if (argc <= 1) { - set_lbmap(QIXIS_LBMAP_DFLTBANK); - qixis_reset(); - } else if (strcmp(argv[1], "altbank") == 0) { -#ifdef QIXIS_LBMAP_ALTBANK - set_lbmap(QIXIS_LBMAP_ALTBANK); - qixis_bank_reset(); -#else - printf("No Altbank!\n"); -#endif - } else if (strcmp(argv[1], "nand") == 0) { -#ifdef QIXIS_LBMAP_NAND - QIXIS_WRITE(rst_ctl, 0x30); - QIXIS_WRITE(rcfg_ctl, 0); - set_lbmap(QIXIS_LBMAP_NAND); - set_rcw_src(QIXIS_RCW_SRC_NAND); - QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); - QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); -#else - printf("Not implemented\n"); -#endif - } else if (strcmp(argv[1], "sd") == 0) { -#ifdef QIXIS_LBMAP_SD - QIXIS_WRITE(rst_ctl, 0x30); - QIXIS_WRITE(rcfg_ctl, 0); -#ifdef NON_EXTENDED_DUTCFG - QIXIS_WRITE(dutcfg[0], QIXIS_RCW_SRC_SD); -#else - set_lbmap(QIXIS_LBMAP_SD); - set_rcw_src(QIXIS_RCW_SRC_SD); -#endif - QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); - QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); -#else - printf("Not implemented\n"); -#endif - } else if (strcmp(argv[1], "ifc") == 0) { -#ifdef QIXIS_LBMAP_IFC - QIXIS_WRITE(rst_ctl, 0x30); - QIXIS_WRITE(rcfg_ctl, 0); - set_lbmap(QIXIS_LBMAP_IFC); - set_rcw_src(QIXIS_RCW_SRC_IFC); - QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); - QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); -#else - printf("Not implemented\n"); -#endif - } else if (strcmp(argv[1], "emmc") == 0) { -#ifdef QIXIS_LBMAP_EMMC - QIXIS_WRITE(rst_ctl, 0x30); - QIXIS_WRITE(rcfg_ctl, 0); -#ifndef NON_EXTENDED_DUTCFG - set_lbmap(QIXIS_LBMAP_EMMC); -#endif - set_rcw_src(QIXIS_RCW_SRC_EMMC); - QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); - QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); -#else - printf("Not implemented\n"); -#endif - } else if (strcmp(argv[1], "sd_qspi") == 0) { -#ifdef QIXIS_LBMAP_SD_QSPI - QIXIS_WRITE(rst_ctl, 0x30); - QIXIS_WRITE(rcfg_ctl, 0); - set_lbmap(QIXIS_LBMAP_SD_QSPI); - set_rcw_src(QIXIS_RCW_SRC_SD); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), - QIXIS_RCFG_CTL_RECONFIG_IDLE); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), - QIXIS_RCFG_CTL_RECONFIG_START); -#else - printf("Not implemented\n"); -#endif - } else if (strcmp(argv[1], "qspi") == 0) { -#ifdef QIXIS_LBMAP_QSPI - QIXIS_WRITE(rst_ctl, 0x30); - QIXIS_WRITE(rcfg_ctl, 0); - set_lbmap(QIXIS_LBMAP_QSPI); - set_rcw_src(QIXIS_RCW_SRC_QSPI); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), - QIXIS_RCFG_CTL_RECONFIG_IDLE); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), - QIXIS_RCFG_CTL_RECONFIG_START); -#else - printf("Not implemented\n"); -#endif - } else if (strcmp(argv[1], "xspi") == 0) { -#ifdef QIXIS_LBMAP_XSPI - QIXIS_WRITE(rst_ctl, 0x30); - QIXIS_WRITE(rcfg_ctl, 0); - set_lbmap(QIXIS_LBMAP_XSPI); - set_rcw_src(QIXIS_RCW_SRC_XSPI); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), - QIXIS_RCFG_CTL_RECONFIG_IDLE); - qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), - QIXIS_RCFG_CTL_RECONFIG_START); -#else - printf("Not implemented\n"); -#endif - } else if (strcmp(argv[1], "watchdog") == 0) { - static char *period[9] = {"2s", "4s", "8s", "16s", "32s", - "1min", "2min", "4min", "8min"}; - u8 rcfg = QIXIS_READ(rcfg_ctl); - - if (argv[2] == NULL) { - printf("qixis watchdog \n"); - return 0; - } - for (i = 0; i < ARRAY_SIZE(period); i++) { - if (strcmp(argv[2], period[i]) == 0) { - /* disable watchdog */ - QIXIS_WRITE(rcfg_ctl, - rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE); - QIXIS_WRITE(watch, ((i<<2) - 1)); - QIXIS_WRITE(rcfg_ctl, rcfg); - return 0; - } - } - } else if (strcmp(argv[1], "dump") == 0) { - qixis_dump_regs(); - return 0; - } else if (strcmp(argv[1], "switch") == 0) { - qixis_dump_switch(); - return 0; - } else { - printf("Invalid option: %s\n", argv[1]); - return 1; - } - - return 0; -} - -U_BOOT_CMD( - qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd, - "Reset the board using the FPGA sequencer", - "- hard reset to default bank\n" - "qixis_reset altbank - reset to alternate bank\n" - "qixis_reset nand - reset to nand\n" - "qixis_reset sd - reset to sd\n" - "qixis_reset sd_qspi - reset to sd with qspi support\n" - "qixis_reset qspi - reset to qspi\n" - "qixis watchdog - set the watchdog period\n" - " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n" - "qixis_reset dump - display the QIXIS registers\n" - "qixis_reset emmc - reset to emmc\n" - "qixis_reset switch - display switch\n" - ); -#endif diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h deleted file mode 100644 index 0a0df6f34f8..00000000000 --- a/board/freescale/common/qixis.h +++ /dev/null @@ -1,190 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011 Freescale Semiconductor - * Copyright 2020 NXP - * Author: Shengzhou Liu - * - * This file provides support for the QIXIS of some Freescale reference boards. - */ - -#ifndef __QIXIS_H_ -#define __QIXIS_H_ - -struct qixis { - u8 id; /* ID value uniquely identifying each QDS board type */ - u8 arch; /* Board version information */ - u8 scver; /* QIXIS Version Register */ - u8 model; /* Information of software programming model version */ - u8 tagdata; - u8 ctl_sys; - u8 aux; /* Auxiliary Register,0x06 */ - u8 clk_spd; - u8 stat_dut; - u8 stat_sys; - u8 stat_alrm; - u8 present; - u8 present2; /* Presence Status Register 2,0x0c */ - u8 rcw_ctl; - u8 ctl_led; - u8 i2cblk; - u8 rcfg_ctl; /* Reconfig Control Register,0x10 */ - u8 rcfg_st; - u8 dcm_ad; - u8 dcm_da; - u8 dcmd; - u8 dmsg; - u8 gdc; - u8 gdd; /* DCM Debug Data Register,0x17 */ - u8 dmack; - u8 res1; - u8 sdhc1; - u8 sdhc2; - u8 stat_pres3; - u8 los_stat; - u8 usb_ctl; - u8 watch; /* Watchdog Register,0x1F */ - u8 pwr_ctl[2]; /* Power Control Register,0x20 */ - u8 res2[2]; - u8 pwr_stat[4]; /* Power Status Register,0x24 */ - u8 res3[8]; - u8 clk_spd2[2]; /* SYSCLK clock Speed Register,0x30 */ - u8 res4[2]; - u8 sclk[3]; /* Clock Configuration Registers,0x34 */ - u8 res5; - u8 dclk[3]; - u8 res6; - u8 clk_dspd[3]; - u8 res7; - u8 rst_ctl; /* Reset Control Register,0x40 */ - u8 rst_stat; /* Reset Status Register */ - u8 rst_rsn; /* Reset Reason Register */ - u8 rst_frc[2]; /* Reset Force Registers,0x43 */ - u8 res8[11]; - u8 brdcfg[16]; /* Board Configuration Register,0x50 */ - u8 dutcfg[16]; - u8 rcw_ad[2]; /* RCW SRAM Address Registers,0x70 */ - u8 rcw_data; - u8 res9[5]; - u8 post_ctl; - u8 post_stat; - u8 post_dat[2]; - u8 pi_d[4]; - u8 gpio_io[4]; - u8 gpio_dir[4]; - u8 res10[20]; - u8 rjtag_ctl; - u8 rjtag_dat; - u8 res11[2]; - u8 trig_src[4]; - u8 trig_dst[4]; - u8 trig_stat; - u8 res12[3]; - u8 trig_ctr[4]; - u8 res13[16]; - u8 clk_freq[6]; /* Clock Measurement Registers */ - u8 res_c6[8]; - u8 clk_base[2]; /* Clock Frequency Base Reg */ - u8 res_d0[8]; - u8 cms[2]; /* Core Management Space Address Register, 0xD8 */ - u8 res_c0[6]; - u8 aux2[4]; /* Auxiliary Registers,0xE0 */ - u8 res14[10]; - u8 aux_ad; - u8 aux_da; - u8 res15[16]; -}; - -u8 qixis_read(unsigned int reg); -void qixis_write(unsigned int reg, u8 value); -u16 qixis_read_minor(void); -char *qixis_read_time(char *result); -char *qixis_read_tag(char *buf); -const char *byte_to_binary_mask(u8 val, u8 mask, char *buf); -#ifdef CFG_SYS_I2C_FPGA_ADDR -u8 qixis_read_i2c(unsigned int reg); -void qixis_write_i2c(unsigned int reg, u8 value); -#endif - -#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CFG_SYS_I2C_FPGA_ADDR) -#define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg)) -#define QIXIS_WRITE(reg, value) \ - qixis_write_i2c(offsetof(struct qixis, reg), value) -#else -#define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg)) -#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value) -#endif - -#ifdef CFG_SYS_I2C_FPGA_ADDR -#define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg)) -#define QIXIS_WRITE_I2C(reg, value) \ - qixis_write_i2c(offsetof(struct qixis, reg), value) -#endif - -/* Use for SDHC adapter card type identification and operation */ -#define QIXIS_SDID_MASK 0x07 - -#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC45 0x1 /* eMMC Card Rev4.5 */ -#define QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY 0x2 /* SD/MMC Legacy Card */ -#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC44 0x3 /* eMMC Card Rev4.4 */ -#define QIXIS_ESDHC_ADAPTER_TYPE_RSV 0x4 /* Reserved */ -#define QIXIS_ESDHC_ADAPTER_TYPE_MMC 0x5 /* MMC Card */ -#define QIXIS_ESDHC_ADAPTER_TYPE_SD 0x6 /* SD Card Rev2.0 3.0 */ -#define QIXIS_ESDHC_NO_ADAPTER 0x7 /* No Card is Present*/ - -#define QIXIS_SDHC1_S1V3 0x80 /* SDHC1: SDHC1 3.3V power control */ -#define QIXIS_SDHC1_VS 0x30 /* BRDCFG11: route to SDHC1_VS */ - -#define QIXIS_SDCLKIN 0x08 -#define QIXIS_SDCLKOUT 0x02 -#define QIXIS_DAT5_6_7 0x02 -#define QIXIS_DAT4 0x01 - -#define QIXIS_EVDD_BY_SDHC_VS 0x0c - -#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \ -defined(CONFIG_TARGET_LX2160ARDB) -#define QIXIS_XMAP_MASK 0x07 -#define QIXIS_RST_CTL_RESET_EN 0x30 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x20 -#define QIXIS_LBMAP_QSPI 0x00 -#define QIXIS_RCW_SRC_QSPI 0xff -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SD -#define QIXIS_LBMAP_EMMC -#define QIXIS_RCW_SRC_SD 0x08 -#define QIXIS_RCW_SRC_EMMC 0x09 -#define NON_EXTENDED_DUTCFG -#endif - -#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) -#define QIXIS_SDID_MASK 0x07 -#define QIXIS_ESDHC_NO_ADAPTER 0x7 -#endif - -/* - * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro. - */ -static inline u8 qixis_esdhc_detect_quirk(void) -{ - /* - * SDHC1 Card ID: - * Specifies the type of card installed in the SDHC1 adapter slot. - * 000= (reserved) - * 001= eMMC V4.5 adapter is installed. - * 010= SD/MMC 3.3V adapter is installed. - * 011= eMMC V4.4 adapter is installed. - * 100= eMMC V5.0 adapter is installed. - * 101= MMC card/Legacy (3.3V) adapter is installed. - * 110= SDCard V2/V3 adapter installed. - * 111= no adapter is installed. - */ - return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) != - QIXIS_ESDHC_NO_ADAPTER); -} - -#endif diff --git a/board/freescale/common/sdhc_boot.c b/board/freescale/common/sdhc_boot.c deleted file mode 100644 index 5ee730cefd0..00000000000 --- a/board/freescale/common/sdhc_boot.c +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - */ - -#include -#include - -/* - * The environment variables are written to just after the u-boot image - * on SDCard, so we must read the MBR to get the start address and code - * length of the u-boot image, then calculate the address of the env. - */ -#define ESDHC_BOOT_IMAGE_SIZE 0x48 -#define ESDHC_BOOT_IMAGE_ADDR 0x50 - -#define ESDHC_DEFAULT_ENVADDR 0x400 - -int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) -{ - u8 *tmp_buf; - u32 blklen, code_offset, code_len, n; - - blklen = mmc->read_bl_len; - tmp_buf = malloc(blklen); - if (!tmp_buf) - return 1; - - /* read out the first block, get the config data information */ -#ifdef CONFIG_BLK - n = blk_dread(mmc_get_blk_desc(mmc), 0, 1, tmp_buf); -#else - n = mmc->block_dev.block_read(&mmc->block_dev, 0, 1, tmp_buf); -#endif - if (!n) { - free(tmp_buf); - return 1; - } - - /* Get the Source Address, from offset 0x50 */ - code_offset = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_ADDR); - - /* Get the code size from offset 0x48 */ - code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE); - -#ifdef CONFIG_ESDHC_HC_BLK_ADDR - /* - * On soc BSC9131, BSC9132: - * In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and - * code length of these soc specify the memory address in block address - * format. Block length is fixed to 512 bytes as per the SD High - * Capacity specification. - */ - u64 tmp; - - if (mmc->high_capacity) { - tmp = (u64)code_offset * blklen; - tmp += code_len * blklen; - } else - tmp = code_offset + code_len; - - if ((tmp + CONFIG_ENV_SIZE > mmc->capacity) || - (tmp > 0xFFFFFFFFU)) - *env_addr = ESDHC_DEFAULT_ENVADDR; - else - *env_addr = tmp; - - free(tmp_buf); - - return 0; -#endif - - *env_addr = code_offset + code_len; - - free(tmp_buf); - - return 0; -} diff --git a/board/freescale/common/sgmii_riser.h b/board/freescale/common/sgmii_riser.h deleted file mode 100644 index e1fcc858f3f..00000000000 --- a/board/freescale/common/sgmii_riser.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Freescale SGMII Riser Card - * - * This driver supports the SGMII Riser card found on the - * "DS" style of development board from Freescale. - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * Copyright 2008 Freescale Semiconductor, Inc. - * - */ - -void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num); -void fsl_sgmii_riser_fdt_fixup(void *fdt); diff --git a/board/freescale/common/sleep.h b/board/freescale/common/sleep.h deleted file mode 100644 index 1450baa0725..00000000000 --- a/board/freescale/common/sleep.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __SLEEP_H -#define __SLEEP_H - -#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) -#define DDR_BUFF_LEN 128 - -/* determine if it is a wakeup from deep sleep */ -bool is_warm_boot(void); - -/* disable console output */ -void fsl_dp_disable_console(void); - -/* clean up everything and jump to kernel */ -int fsl_dp_resume(void); -#endif diff --git a/board/freescale/common/spl.h b/board/freescale/common/spl.h deleted file mode 100644 index d4689d3d726..00000000000 --- a/board/freescale/common/spl.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Google, Inc - */ - -#ifndef __FREESCALE_BOARD_SPL_H -#define __FREESCALE_BOARD_SPL_H - -void fsl_spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst); -void fsl_spi_boot(void) __noreturn; - -#endif diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c deleted file mode 100644 index ec3c9e37222..00000000000 --- a/board/freescale/common/sys_eeprom.c +++ /dev/null @@ -1,648 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor - * York Sun (yorksun@freescale.com) - * Haiying Wang (haiying.wang@freescale.com) - * Timur Tabi (timur@freescale.com) - */ - -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_SYS_I2C_EEPROM_CCID -#include "../common/eeprom.h" -#define MAX_NUM_PORTS 8 -#endif - -#ifdef CONFIG_SYS_I2C_EEPROM_NXID -/* some boards with non-256-bytes EEPROM have special define */ -/* for MAX_NUM_PORTS in board-specific file */ -#ifndef MAX_NUM_PORTS -#define MAX_NUM_PORTS 16 -#endif -#define NXID_VERSION 1 -#endif - -/** - * static eeprom: EEPROM layout for CCID or NXID formats - * - * See application note AN3638 for details. - */ -static struct __attribute__ ((__packed__)) eeprom { -#ifdef CONFIG_SYS_I2C_EEPROM_CCID - u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'CCID' */ - u8 major; /* 0x04 Board revision, major */ - u8 minor; /* 0x05 Board revision, minor */ - u8 sn[10]; /* 0x06 - 0x0F Serial Number*/ - u8 errata[2]; /* 0x10 - 0x11 Errata Level */ - u8 date[6]; /* 0x12 - 0x17 Build Date */ - u8 res_0[40]; /* 0x18 - 0x3f Reserved */ - u8 mac_count; /* 0x40 Number of MAC addresses */ - u8 mac_flag; /* 0x41 MAC table flags */ - u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */ - u32 crc; /* 0x72 CRC32 checksum */ -#endif -#ifdef CONFIG_SYS_I2C_EEPROM_NXID - u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'NXID' */ - u8 sn[12]; /* 0x04 - 0x0F Serial Number */ - u8 errata[5]; /* 0x10 - 0x14 Errata Level */ - u8 date[6]; /* 0x15 - 0x1a Build Date */ - u8 res_0; /* 0x1b Reserved */ - u32 version; /* 0x1c - 0x1f NXID Version */ - u8 tempcal[8]; /* 0x20 - 0x27 Temperature Calibration Factors */ - u8 tempcalsys[2]; /* 0x28 - 0x29 System Temperature Calibration Factors */ - u8 tempcalflags; /* 0x2a Temperature Calibration Flags */ - u8 res_1[21]; /* 0x2b - 0x3f Reserved */ - u8 mac_count; /* 0x40 Number of MAC addresses */ - u8 mac_flag; /* 0x41 MAC table flags */ - u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0xa1 MAC addresses */ - u8 res_2[90]; /* 0xa2 - 0xfb Reserved */ - u32 crc; /* 0xfc - 0xff CRC32 checksum */ -#endif -} e; - -/* Set to 1 if we've read EEPROM into memory */ -static int has_been_read = 0; - -#ifdef CONFIG_SYS_I2C_EEPROM_NXID -/* Is this a valid NXID EEPROM? */ -#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \ - (e.id[2] == 'I') || (e.id[3] == 'D')) -#endif - -#ifdef CONFIG_SYS_I2C_EEPROM_CCID -/* Is this a valid CCID EEPROM? */ -#define is_valid ((e.id[0] == 'C') || (e.id[1] == 'C') || \ - (e.id[2] == 'I') || (e.id[3] == 'D')) -#endif - -/** - * show_eeprom - display the contents of the EEPROM - */ -static void show_eeprom(void) -{ - int i; - unsigned int crc; - - /* EEPROM tag ID, either CCID or NXID */ -#ifdef CONFIG_SYS_I2C_EEPROM_NXID - printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], - be32_to_cpu(e.version)); -#else - printf("ID: %c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]); -#endif - - /* Serial number */ - printf("SN: %s\n", e.sn); - - /* Errata level. */ -#ifdef CONFIG_SYS_I2C_EEPROM_NXID - printf("Errata: %s\n", e.errata); -#else - printf("Errata: %c%c\n", - e.errata[0] ? e.errata[0] : '.', - e.errata[1] ? e.errata[1] : '.'); -#endif - - /* Build date, BCD date values, as YYMMDDhhmmss */ - printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n", - e.date[0], e.date[1], e.date[2], - e.date[3] & 0x7F, e.date[4], e.date[5], - e.date[3] & 0x80 ? "PM" : ""); - - /* Show MAC addresses */ - for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) { - - u8 *p = e.mac[i]; - - printf("Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n", i, - p[0], p[1], p[2], p[3], p[4], p[5]); - } - - crc = crc32(0, (void *)&e, sizeof(e) - 4); - - if (crc == be32_to_cpu(e.crc)) - printf("CRC: %08x\n", be32_to_cpu(e.crc)); - else - printf("CRC: %08x (should be %08x)\n", - be32_to_cpu(e.crc), crc); - -#ifdef DEBUG - printf("EEPROM dump: (0x%x bytes)\n", sizeof(e)); - for (i = 0; i < sizeof(e); i++) { - if ((i % 16) == 0) - printf("%02X: ", i); - printf("%02X ", ((u8 *)&e)[i]); - if (((i % 16) == 15) || (i == sizeof(e) - 1)) - printf("\n"); - } -#endif -} - -/** - * read_eeprom - read the EEPROM into memory - */ -static int read_eeprom(void) -{ - int ret; -#ifdef CONFIG_SYS_EEPROM_BUS_NUM -#if !CONFIG_IS_ENABLED(DM_I2C) - unsigned int bus; -#endif -#endif - - if (has_been_read) - return 0; - -#ifdef CONFIG_SYS_EEPROM_BUS_NUM -#if !CONFIG_IS_ENABLED(DM_I2C) - bus = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); -#endif -#endif - -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - (void *)&e, sizeof(e)); -#else - struct udevice *dev; -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, - CONFIG_SYS_I2C_EEPROM_ADDR, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev); -#else - ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev); -#endif - if (!ret) - ret = dm_i2c_read(dev, 0, (void *)&e, sizeof(e)); -#endif - -#ifdef CONFIG_SYS_EEPROM_BUS_NUM -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_set_bus_num(bus); -#endif -#endif - -#ifdef DEBUG - show_eeprom(); -#endif - - has_been_read = (ret == 0) ? 1 : 0; - - return ret; -} - -/** - * update_crc - update the CRC - * - * This function should be called after each update to the EEPROM structure, - * to make sure the CRC is always correct. - */ -static void update_crc(void) -{ - u32 crc; - - crc = crc32(0, (void *)&e, sizeof(e) - 4); - e.crc = cpu_to_be32(crc); -} - -/** - * prog_eeprom - write the EEPROM from memory - */ -static int prog_eeprom(void) -{ - int ret = 0; - int i; - void *p; -#ifdef CONFIG_SYS_EEPROM_BUS_NUM -#if !CONFIG_IS_ENABLED(DM_I2C) - unsigned int bus; -#endif -#endif - - /* Set the reserved values to 0xFF */ -#ifdef CONFIG_SYS_I2C_EEPROM_NXID - e.res_0 = 0xFF; - memset(e.res_1, 0xFF, sizeof(e.res_1)); -#else - memset(e.res_0, 0xFF, sizeof(e.res_0)); -#endif - update_crc(); - -#if !CONFIG_IS_ENABLED(DM_I2C) -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - bus = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); -#endif -#endif - - /* - * The AT24C02 datasheet says that data can only be written in page - * mode, which means 8 bytes at a time, and it takes up to 5ms to - * complete a given write. - */ - for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) { -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - p, min((int)(sizeof(e) - i), 8)); -#else - struct udevice *dev; -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, - CONFIG_SYS_I2C_EEPROM_ADDR, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - &dev); -#else - ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - &dev); -#endif - if (!ret) - ret = dm_i2c_write(dev, i, p, min((int)(sizeof(e) - i), - 8)); -#endif - if (ret) - break; - udelay(5000); /* 5ms write cycle timing */ - } - - if (!ret) { - /* Verify the write by reading back the EEPROM and comparing */ - struct eeprom e2; - -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - (void *)&e2, sizeof(e2)); -#else - struct udevice *dev; -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, - CONFIG_SYS_I2C_EEPROM_ADDR, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - &dev); -#else - ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - &dev); -#endif - if (!ret) - ret = dm_i2c_read(dev, 0, (void *)&e2, sizeof(e2)); -#endif - if (!ret && memcmp(&e, &e2, sizeof(e))) - ret = -1; - } - -#if !CONFIG_IS_ENABLED(DM_I2C) -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - i2c_set_bus_num(bus); -#endif -#endif - - if (ret) { - printf("Programming failed.\n"); - has_been_read = 0; - return -1; - } - - printf("Programming passed.\n"); - return 0; -} - -/** - * h2i - converts hex character into a number - * - * This function takes a hexadecimal character (e.g. '7' or 'C') and returns - * the integer equivalent. - */ -static inline u8 h2i(char p) -{ - if ((p >= '0') && (p <= '9')) - return p - '0'; - - if ((p >= 'A') && (p <= 'F')) - return (p - 'A') + 10; - - if ((p >= 'a') && (p <= 'f')) - return (p - 'a') + 10; - - return 0; -} - -/** - * set_date - stores the build date into the EEPROM - * - * This function takes a pointer to a string in the format "YYMMDDhhmmss" - * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string, - * and stores it in the build date field of the EEPROM local copy. - */ -static void set_date(const char *string) -{ - unsigned int i; - - if (strlen(string) != 12) { - printf("Usage: mac date YYMMDDhhmmss\n"); - return; - } - - for (i = 0; i < 6; i++) - e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]); - - update_crc(); -} - -/** - * set_mac_address - stores a MAC address into the EEPROM - * - * This function takes a pointer to MAC address string - * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and - * stores it in one of the MAC address fields of the EEPROM local copy. - */ -static void set_mac_address(unsigned int index, const char *string) -{ - char *p = (char *) string; - unsigned int i; - - if ((index >= MAX_NUM_PORTS) || !string) { - printf("Usage: mac XX:XX:XX:XX:XX:XX\n"); - return; - } - - for (i = 0; *p && (i < 6); i++) { - e.mac[index][i] = hextoul(p, &p); - if (*p == ':') - p++; - } - - update_crc(); -} - -int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - char cmd; - - if (argc == 1) { - show_eeprom(); - return 0; - } - - cmd = argv[1][0]; - - if (cmd == 'r') { - read_eeprom(); - return 0; - } - - if (cmd == 'i') { -#ifdef CONFIG_SYS_I2C_EEPROM_NXID - memcpy(e.id, "NXID", sizeof(e.id)); - e.version = cpu_to_be32(NXID_VERSION); -#else - memcpy(e.id, "CCID", sizeof(e.id)); -#endif - update_crc(); - return 0; - } - - if (!is_valid) { - printf("Please read the EEPROM ('r') and/or set the ID ('i') first.\n"); - return 0; - } - - if (argc == 2) { - switch (cmd) { - case 's': /* save */ - prog_eeprom(); - break; - default: - return CMD_RET_USAGE; - } - - return 0; - } - - /* We know we have at least one parameter */ - - switch (cmd) { - case 'n': /* serial number */ - memset(e.sn, 0, sizeof(e.sn)); - strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1); - update_crc(); - break; - case 'e': /* errata */ -#ifdef CONFIG_SYS_I2C_EEPROM_NXID - memset(e.errata, 0, 5); - strncpy((char *)e.errata, argv[2], 4); -#else - e.errata[0] = argv[2][0]; - e.errata[1] = argv[2][1]; -#endif - update_crc(); - break; - case 'd': /* date BCD format YYMMDDhhmmss */ - set_date(argv[2]); - break; - case 'p': /* MAC table size */ - e.mac_count = hextoul(argv[2], NULL); - update_crc(); - break; - case '0' ... '9': /* "mac 0" through "mac 22" */ - set_mac_address(dectoul(argv[1], NULL), argv[2]); - break; - case 'h': /* help */ - default: - return cmd_usage(cmdtp); - } - - return 0; -} - -/** - * mac_read_from_eeprom - read the MAC addresses from EEPROM - * - * This function reads the MAC addresses from EEPROM and sets the - * appropriate environment variables for each one read. - * - * The environment variables are only set if they haven't been set already. - * This ensures that any user-saved variables are never overwritten. - * - * This function must be called after relocation. - * - * For NXID v1 EEPROMs, we support loading and up-converting the older NXID v0 - * format. In a v0 EEPROM, there are only eight MAC addresses and the CRC is - * located at a different offset. - */ -int mac_read_from_eeprom(void) -{ - unsigned int i; - u32 crc, crc_offset = offsetof(struct eeprom, crc); - u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */ - - puts("EEPROM: "); - - if (read_eeprom()) { - printf("Read failed.\n"); - return 0; - } - - if (!is_valid) { - printf("Invalid ID (%02x %02x %02x %02x)\n", - e.id[0], e.id[1], e.id[2], e.id[3]); - return 0; - } - -#ifdef CONFIG_SYS_I2C_EEPROM_NXID - /* - * If we've read an NXID v0 EEPROM, then we need to set the CRC offset - * to where it is in v0. - */ - if (e.version == 0) - crc_offset = 0x72; -#endif - - crc = crc32(0, (void *)&e, crc_offset); - crcp = (void *)&e + crc_offset; - if (crc != be32_to_cpu(*crcp)) { - printf("CRC mismatch (%08x != %08x)\n", crc, be32_to_cpu(e.crc)); - return 0; - } - -#ifdef CONFIG_SYS_I2C_EEPROM_NXID - /* - * MAC address #9 in v1 occupies the same position as the CRC in v0. - * Erase it so that it's not mistaken for a MAC address. We'll - * update the CRC later. - */ - if (e.version == 0) - memset(e.mac[8], 0xff, 6); -#endif - - for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) { - if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) && - memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) { - char ethaddr[18]; - char enetvar[9]; - - sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", - e.mac[i][0], - e.mac[i][1], - e.mac[i][2], - e.mac[i][3], - e.mac[i][4], - e.mac[i][5]); - sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i); - /* Only initialize environment variables that are blank - * (i.e. have not yet been set) - */ - if (!env_get(enetvar)) - env_set(enetvar, ethaddr); - } - } - -#ifdef CONFIG_SYS_I2C_EEPROM_NXID - printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], - be32_to_cpu(e.version)); -#else - printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]); -#endif - -#ifdef CONFIG_SYS_I2C_EEPROM_NXID - /* - * Now we need to upconvert the data into v1 format. We do this last so - * that at boot time, U-Boot will still say "NXID v0". - */ - if (e.version == 0) { - e.version = cpu_to_be32(NXID_VERSION); - update_crc(); - } -#endif - - return 0; -} - -#ifdef CONFIG_SYS_I2C_EEPROM_CCID - -/** - * get_cpu_board_revision - get the CPU board revision on 85xx boards - * - * Read the EEPROM to determine the board revision. - * - * This function is called before relocation, so we need to read a private - * copy of the EEPROM into a local variable on the stack. - * - * Also, we assume that CONFIG_SYS_EEPROM_BUS_NUM == CONFIG_SYS_SPD_BUS_NUM. The global - * variable i2c_bus_num must be compile-time initialized to CONFIG_SYS_SPD_BUS_NUM, - * so that the SPD code will work. This means that all pre-relocation I2C - * operations can only occur on the CONFIG_SYS_SPD_BUS_NUM bus. So if - * CONFIG_SYS_EEPROM_BUS_NUM != CONFIG_SYS_SPD_BUS_NUM, then we can't read the EEPROM when - * this function is called. Oh well. - */ -unsigned int get_cpu_board_revision(void) -{ - struct board_eeprom { - u32 id; /* 0x00 - 0x03 EEPROM Tag 'CCID' */ - u8 major; /* 0x04 Board revision, major */ - u8 minor; /* 0x05 Board revision, minor */ - } be; - -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - (void *)&be, sizeof(be)); -#else - struct udevice *dev; - int ret; -#ifdef CONFIG_SYS_EEPROM_BUS_NUM - ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, - CONFIG_SYS_I2C_EEPROM_ADDR, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - &dev); -#else - ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - &dev); -#endif - if (!ret) - dm_i2c_read(dev, 0, (void *)&be, sizeof(be)); -#endif - - if (be.id != (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D')) - return MPC85XX_CPU_BOARD_REV(0, 0); - - if ((be.major == 0xff) && (be.minor == 0xff)) - return MPC85XX_CPU_BOARD_REV(0, 0); - - return MPC85XX_CPU_BOARD_REV(be.major, be.minor); -} -#endif - -U_BOOT_LONGHELP(mac, - "[read|save|id|num|errata|date|ports|port_number]\n" - "mac read\n" - " - read EEPROM content into memory data structure\n" - "mac save\n" - " - save memory data structure to the EEPROM\n" - "mac id\n" - " - program system id per hard coded value\n" - "mac num string\n" - " - program system serial number to value string\n" - "mac errata string\n" - " - program errata data to value string\n" - "mac date YYMMDDhhmmss\n" - " - program date to string value YYMMDDhhmmss\n" - "mac ports N\n" - " - program the number of network ports to integer N\n" - "mac X string\n" - " - program MAC addr for port X [X=0,1..] to colon separated string"); - -U_BOOT_CMD( - mac, 3, 1, do_mac, - "display and program the system ID and MAC addresses in EEPROM", - mac_help_text); diff --git a/board/freescale/common/via.h b/board/freescale/common/via.h deleted file mode 100644 index 77cfacc5261..00000000000 --- a/board/freescale/common/via.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef _MPC85xx_VIA_H -void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); - -/* Function 1, IDE */ -void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); - -/* Function 2, USB ports 0-1 */ -void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); - -/* Function 3, USB ports 2-3 */ -void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); - -/* Function 5, Power Management */ -void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); - -/* Function 6, AC97 Interface */ -void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); -#endif /* _MPC85xx_VIA_H */ diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c deleted file mode 100644 index 84cb43fad56..00000000000 --- a/board/freescale/common/vid.c +++ /dev/null @@ -1,797 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2020-21 NXP - * Copyright 2020 Stephen Carlson - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_FSL_LSCH2 -#include -#elif defined(CONFIG_FSL_LSCH3) -#include -#else -#include -#endif -#include -#include "i2c_common.h" -#include "vid.h" - -#ifndef I2C_VOL_MONITOR_BUS -#define I2C_VOL_MONITOR_BUS 0 -#endif - -/* Voltages are generally handled in mV to keep them as integers */ -#define MV_PER_V 1000 - -/* - * Select the channel on the I2C mux (on some NXP boards) that contains - * the voltage regulator to use for VID. Return 0 for success or nonzero - * for failure. - */ -int __weak i2c_multiplexer_select_vid_channel(u8 channel) -{ - return 0; -} - -/* - * Compensate for a board specific voltage drop between regulator and SoC. - * Returns the voltage offset in mV. - */ -int __weak board_vdd_drop_compensation(void) -{ - return 0; -} - -/* - * Performs any board specific adjustments after the VID voltage has been - * set. Return 0 for success or nonzero for failure. - */ -int __weak board_adjust_vdd(int vdd) -{ - return 0; -} - -/* - * Processor specific method of converting the fuse value read from VID - * registers into the core voltage to supply. Return the voltage in mV. - */ -u16 __weak soc_get_fuse_vid(int vid_index) -{ - /* Default VDD for Layerscape Chassis 1 devices */ - static const u16 vdd[32] = { - 0, /* unused */ - 9875, /* 0.9875V */ - 9750, - 9625, - 9500, - 9375, - 9250, - 9125, - 9000, - 8875, - 8750, - 8625, - 8500, - 8375, - 8250, - 8125, - 10000, /* 1.0000V */ - 10125, - 10250, - 10375, - 10500, - 10625, - 10750, - 10875, - 11000, - 0, /* reserved */ - }; - return vdd[vid_index]; -} - -#ifndef I2C_VOL_MONITOR_ADDR -#define I2C_VOL_MONITOR_ADDR 0 -#endif - -#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ - defined(CONFIG_VOL_MONITOR_IR36021_READ) -/* - * Get the i2c address configuration for the IR regulator chip - * - * There are some variance in the RDB HW regarding the I2C address configuration - * for the IR regulator chip, which is likely a problem of external resistor - * accuracy. So we just check each address in a hopefully non-intrusive mode - * and use the first one that seems to work - * - * The IR chip can show up under the following addresses: - * 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA) - * 0x09 (Verified on T1040RDB-PA) - * 0x38 (Verified on T2080QDS, T2081QDS, T4240RDB) - */ -static int find_ir_chip_on_i2c(void) -{ - int i2caddress, ret, i; - u8 mfrID; - const int ir_i2c_addr[] = {0x38, 0x08, 0x09}; - DEVICE_HANDLE_T dev; - - /* Check all the address */ - for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) { - i2caddress = ir_i2c_addr[i]; - ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); - if (!ret) { - ret = I2C_READ(dev, IR36021_MFR_ID_OFFSET, - (void *)&mfrID, sizeof(mfrID)); - /* If manufacturer ID matches the IR36021 */ - if (!ret && mfrID == IR36021_MFR_ID) - return i2caddress; - } - } - return -1; -} -#endif - -/* Maximum loop count waiting for new voltage to take effect */ -#define MAX_LOOP_WAIT_NEW_VOL 100 -/* Maximum loop count waiting for the voltage to be stable */ -#define MAX_LOOP_WAIT_VOL_STABLE 100 -/* - * read_voltage from sensor on I2C bus - * We use average of 4 readings, waiting for WAIT_FOR_ADC before - * another reading - */ -#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */ - -/* If an INA220 chip is available, we can use it to read back the voltage - * as it may have a higher accuracy than the IR chip for the same purpose - */ -#ifdef CONFIG_VOL_MONITOR_INA220 -#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */ -#define ADC_MIN_ACCURACY 4 -#else -#define WAIT_FOR_ADC 138 /* wait for 138 microseconds for ADC */ -#define ADC_MIN_ACCURACY 4 -#endif - -#ifdef CONFIG_VOL_MONITOR_INA220 -static int read_voltage_from_INA220(int i2caddress) -{ - int i, ret, voltage_read = 0; - u16 vol_mon; - u8 buf[2]; - DEVICE_HANDLE_T dev; - - /* Open device handle */ - ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); - if (ret) - return ret; - - for (i = 0; i < NUM_READINGS; i++) { - ret = I2C_READ(dev, I2C_VOL_MONITOR_BUS_V_OFFSET, - (void *)&buf[0], sizeof(buf)); - if (ret) { - printf("VID: failed to read core voltage\n"); - return ret; - } - - vol_mon = (buf[0] << 8) | buf[1]; - if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { - printf("VID: Core voltage sensor error\n"); - return -1; - } - - debug("VID: bus voltage reads 0x%04x\n", vol_mon); - /* LSB = 4mv */ - voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; - udelay(WAIT_FOR_ADC); - } - - /* calculate the average */ - voltage_read /= NUM_READINGS; - - return voltage_read; -} -#endif - -#ifdef CONFIG_VOL_MONITOR_IR36021_READ -/* read voltage from IR */ -static int read_voltage_from_IR(int i2caddress) -{ - int i, ret, voltage_read = 0; - u16 vol_mon; - u8 buf; - DEVICE_HANDLE_T dev; - - /* Open device handle */ - ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); - if (ret) - return ret; - - for (i = 0; i < NUM_READINGS; i++) { - ret = I2C_READ(dev, IR36021_LOOP1_VOUT_OFFSET, (void *)&buf, - sizeof(buf)); - if (ret) { - printf("VID: failed to read core voltage\n"); - return ret; - } - vol_mon = buf; - if (!vol_mon) { - printf("VID: Core voltage sensor error\n"); - return -1; - } - debug("VID: bus voltage reads 0x%02x\n", vol_mon); - /* Resolution is 1/128V. We scale up here to get 1/128mV - * and divide at the end - */ - voltage_read += vol_mon * MV_PER_V; - udelay(WAIT_FOR_ADC); - } - /* Scale down to the real mV as IR resolution is 1/128V, rounding up */ - voltage_read = DIV_ROUND_UP(voltage_read, 128); - - /* calculate the average */ - voltage_read /= NUM_READINGS; - - /* Compensate for a board specific voltage drop between regulator and - * SoC before converting into an IR VID value - */ - voltage_read -= board_vdd_drop_compensation(); - - return voltage_read; -} -#endif - -#if defined(CONFIG_VOL_MONITOR_ISL68233_READ) || \ - defined(CONFIG_VOL_MONITOR_LTC3882_READ) || \ - defined(CONFIG_VOL_MONITOR_ISL68233_SET) || \ - defined(CONFIG_VOL_MONITOR_LTC3882_SET) - -/* - * The message displayed if the VOUT exponent causes a resolution - * worse than 1.0 V (if exponent is >= 0). - */ -#define VOUT_WARNING "VID: VOUT_MODE exponent has resolution worse than 1 V!\n" - -/* Checks the PMBus voltage monitor for the format used for voltage values */ -static int get_pmbus_multiplier(DEVICE_HANDLE_T dev) -{ - u8 mode; - int exponent, multiplier, ret; - - ret = I2C_READ(dev, PMBUS_CMD_VOUT_MODE, &mode, sizeof(mode)); - if (ret) { - printf("VID: unable to determine voltage multiplier\n"); - return 1; - } - - /* Upper 3 bits is mode, lower 5 bits is exponent */ - exponent = (int)mode & 0x1F; - mode >>= 5; - switch (mode) { - case 0: - /* Linear, 5 bit twos component exponent */ - if (exponent & 0x10) { - multiplier = 1 << (16 - (exponent & 0xF)); - } else { - /* If exponent is >= 0, then resolution is 1 V! */ - printf(VOUT_WARNING); - multiplier = 1; - } - break; - case 1: - /* VID code identifier */ - printf("VID: custom VID codes are not supported\n"); - multiplier = MV_PER_V; - break; - default: - /* Direct, in mV */ - multiplier = MV_PER_V; - break; - } - - debug("VID: calculated multiplier is %d\n", multiplier); - return multiplier; -} -#endif - -#if defined(CONFIG_VOL_MONITOR_ISL68233_READ) || \ - defined(CONFIG_VOL_MONITOR_LTC3882_READ) -static int read_voltage_from_pmbus(int i2caddress) -{ - int ret, multiplier, vout; - u8 channel = PWM_CHANNEL0; - u16 vcode; - DEVICE_HANDLE_T dev; - - /* Open device handle */ - ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); - if (ret) - return ret; - - /* Select the right page */ - ret = I2C_WRITE(dev, PMBUS_CMD_PAGE, &channel, sizeof(channel)); - if (ret) { - printf("VID: failed to select VDD page %d\n", channel); - return ret; - } - - /* VOUT is little endian */ - ret = I2C_READ(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, sizeof(vcode)); - if (ret) { - printf("VID: failed to read core voltage\n"); - return ret; - } - - /* Scale down to the real mV */ - multiplier = get_pmbus_multiplier(dev); - vout = (int)vcode; - /* Multiplier 1000 (direct mode) requires no change to convert */ - if (multiplier != MV_PER_V) - vout = DIV_ROUND_UP(vout * MV_PER_V, multiplier); - return vout - board_vdd_drop_compensation(); -} -#endif - -static int read_voltage(int i2caddress) -{ - int voltage_read; -#ifdef CONFIG_VOL_MONITOR_INA220 - voltage_read = read_voltage_from_INA220(I2C_VOL_MONITOR_ADDR); -#elif defined CONFIG_VOL_MONITOR_IR36021_READ - voltage_read = read_voltage_from_IR(i2caddress); -#elif defined(CONFIG_VOL_MONITOR_ISL68233_READ) || \ - defined(CONFIG_VOL_MONITOR_LTC3882_READ) - voltage_read = read_voltage_from_pmbus(i2caddress); -#else - voltage_read = -1; -#endif - return voltage_read; -} - -#ifdef CONFIG_VOL_MONITOR_IR36021_SET -/* - * We need to calculate how long before the voltage stops to drop - * or increase. It returns with the loop count. Each loop takes - * several readings (WAIT_FOR_ADC) - */ -static int wait_for_new_voltage(int vdd, int i2caddress) -{ - int timeout, vdd_current; - - vdd_current = read_voltage(i2caddress); - /* wait until voltage starts to reach the target. Voltage slew - * rates by typical regulators will always lead to stable readings - * within each fairly long ADC interval in comparison to the - * intended voltage delta change until the target voltage is - * reached. The fairly small voltage delta change to any target - * VID voltage also means that this function will always complete - * within few iterations. If the timeout was ever reached, it would - * point to a serious failure in the regulator system. - */ - for (timeout = 0; - abs(vdd - vdd_current) > (IR_VDD_STEP_UP + IR_VDD_STEP_DOWN) && - timeout < MAX_LOOP_WAIT_NEW_VOL; timeout++) { - vdd_current = read_voltage(i2caddress); - } - if (timeout >= MAX_LOOP_WAIT_NEW_VOL) { - printf("VID: Voltage adjustment timeout\n"); - return -1; - } - return timeout; -} - -/* - * Blocks and reads the VID voltage until it stabilizes, or the - * timeout expires - */ -static int wait_for_voltage_stable(int i2caddress) -{ - int timeout, vdd_current, vdd; - - vdd = read_voltage(i2caddress); - udelay(NUM_READINGS * WAIT_FOR_ADC); - - vdd_current = read_voltage(i2caddress); - /* - * The maximum timeout is - * MAX_LOOP_WAIT_VOL_STABLE * NUM_READINGS * WAIT_FOR_ADC - */ - for (timeout = MAX_LOOP_WAIT_VOL_STABLE; - abs(vdd - vdd_current) > ADC_MIN_ACCURACY && - timeout > 0; timeout--) { - vdd = vdd_current; - udelay(NUM_READINGS * WAIT_FOR_ADC); - vdd_current = read_voltage(i2caddress); - } - if (timeout == 0) - return -1; - return vdd_current; -} - -/* Sets the VID voltage using the IR36021 */ -static int set_voltage_to_IR(int i2caddress, int vdd) -{ - int wait, vdd_last; - int ret; - u8 vid; - DEVICE_HANDLE_T dev; - - /* Open device handle */ - ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); - if (ret) - return ret; - - /* Compensate for a board specific voltage drop between regulator and - * SoC before converting into an IR VID value - */ - vdd += board_vdd_drop_compensation(); -#ifdef CONFIG_FSL_LSCH2 - vid = DIV_ROUND_UP(vdd - 265, 5); -#else - vid = DIV_ROUND_UP(vdd - 245, 5); -#endif - - ret = I2C_WRITE(dev, IR36021_LOOP1_MANUAL_ID_OFFSET, (void *)&vid, - sizeof(vid)); - if (ret) { - printf("VID: failed to write new voltage\n"); - return -1; - } - wait = wait_for_new_voltage(vdd, i2caddress); - if (wait < 0) - return -1; - debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC); - - vdd_last = wait_for_voltage_stable(i2caddress); - if (vdd_last < 0) - return -1; - debug("VID: Current voltage is %d mV\n", vdd_last); - return vdd_last; -} -#endif - -#if defined(CONFIG_VOL_MONITOR_ISL68233_SET) || \ - defined(CONFIG_VOL_MONITOR_LTC3882_SET) -static int set_voltage_to_pmbus(int i2caddress, int vdd) -{ - int ret, vdd_last, vdd_target = vdd; - int count = MAX_LOOP_WAIT_NEW_VOL, temp = 0, multiplier; - unsigned char value; - - /* The data to be sent with the PMBus command PAGE_PLUS_WRITE */ - u8 buffer[5] = { 0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, 0, 0 }; - DEVICE_HANDLE_T dev; - - /* Open device handle */ - ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); - if (ret) - return ret; - - /* Scale up to the proper value for the VOUT command, little endian */ - multiplier = get_pmbus_multiplier(dev); - vdd += board_vdd_drop_compensation(); - if (multiplier != MV_PER_V) - vdd = DIV_ROUND_UP(vdd * multiplier, MV_PER_V); - buffer[3] = vdd & 0xFF; - buffer[4] = (vdd & 0xFF00) >> 8; - - /* Check write protect state */ - ret = I2C_READ(dev, PMBUS_CMD_WRITE_PROTECT, (void *)&value, - sizeof(value)); - if (ret) - goto exit; - - if (value != EN_WRITE_ALL_CMD) { - value = EN_WRITE_ALL_CMD; - ret = I2C_WRITE(dev, PMBUS_CMD_WRITE_PROTECT, - (void *)&value, sizeof(value)); - if (ret) - goto exit; - } - - /* Write the desired voltage code to the regulator */ - ret = I2C_WRITE(dev, PMBUS_CMD_PAGE_PLUS_WRITE, (void *)&buffer[0], - sizeof(buffer)); - if (ret) { - printf("VID: I2C failed to write to the voltage regulator\n"); - return -1; - } - -exit: - /* Wait for the voltage to get to the desired value */ - do { - vdd_last = read_voltage_from_pmbus(i2caddress); - if (vdd_last < 0) { - printf("VID: Couldn't read sensor abort VID adjust\n"); - return -1; - } - count--; - temp = vdd_last - vdd_target; - } while ((abs(temp) > 2) && (count > 0)); - - return vdd_last; -} -#endif - -static int set_voltage(int i2caddress, int vdd) -{ - int vdd_last = -1; - -#ifdef CONFIG_VOL_MONITOR_IR36021_SET - vdd_last = set_voltage_to_IR(i2caddress, vdd); -#elif defined(CONFIG_VOL_MONITOR_ISL68233_SET) || \ - defined(CONFIG_VOL_MONITOR_LTC3882_SET) - vdd_last = set_voltage_to_pmbus(i2caddress, vdd); -#else - #error Specific voltage monitor must be defined -#endif - return vdd_last; -} - -int adjust_vdd(ulong vdd_override) -{ - int re_enable = disable_interrupts(); -#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); -#else - ccsr_gur_t __iomem *gur = - (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); -#endif - u8 vid; - u32 fusesr; - int vdd_current, vdd_last, vdd_target; - int ret, i2caddress = I2C_VOL_MONITOR_ADDR; - unsigned long vdd_string_override; - char *vdd_string; - -#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ - defined(CONFIG_VOL_MONITOR_IR36021_READ) - u8 buf; - DEVICE_HANDLE_T dev; -#endif - - /* - * VID is used according to the table below - * --------------------------------------- - * | DA_V | - * |-------------------------------------| - * | 5b00000 | 5b00001-5b11110 | 5b11111 | - * ---------------+---------+-----------------+---------| - * | D | 5b00000 | NO VID | VID = DA_V | NO VID | - * | A |----------+---------+-----------------+---------| - * | _ | 5b00001 |VID = | VID = |VID = | - * | V | ~ | DA_V_ALT| DA_V_ALT | DA_A_VLT| - * | _ | 5b11110 | | | | - * | A |----------+---------+-----------------+---------| - * | L | 5b11111 | No VID | VID = DA_V | NO VID | - * | T | | | | | - * ------------------------------------------------------ - */ -#if defined(CONFIG_FSL_LSCH3) - fusesr = in_le32(&gur->dcfg_fusesr); - vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & - FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; - if (vid == 0 || vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK) { - vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & - FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; - } -#elif defined(CONFIG_FSL_LSCH2) - fusesr = in_be32(&gur->dcfg_fusesr); - vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & - FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK; - if (vid == 0 || vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK) { - vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & - FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; - } -#else - fusesr = in_be32(&gur->dcfg_fusesr); - vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & - FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; - if (vid == 0 || vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK) { - vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & - FSL_CORENET_DCFG_FUSESR_VID_MASK; - } -#endif - vdd_target = soc_get_fuse_vid((int)vid); - - ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); - if (ret) { - debug("VID: I2C failed to switch channel\n"); - ret = -1; - goto exit; - } - -#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ - defined(CONFIG_VOL_MONITOR_IR36021_READ) - ret = find_ir_chip_on_i2c(); - if (ret < 0) { - printf("VID: Could not find voltage regulator on I2C.\n"); - ret = -1; - goto exit; - } else { - i2caddress = ret; - debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); - } - - ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); - if (ret) - return ret; - - /* check IR chip work on Intel mode */ - ret = I2C_READ(dev, IR36021_INTEL_MODE_OFFSET, (void *)&buf, - sizeof(buf)); - if (ret) { - printf("VID: failed to read IR chip mode.\n"); - ret = -1; - goto exit; - } - if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) { - printf("VID: IR Chip is not used in Intel mode.\n"); - ret = -1; - goto exit; - } -#endif - - /* check override variable for overriding VDD */ - vdd_string = env_get(CONFIG_VID_FLS_ENV); - debug("VID: Initial VDD value is %d mV\n", - DIV_ROUND_UP(vdd_target, 10)); - if (vdd_override == 0 && vdd_string && - !strict_strtoul(vdd_string, 10, &vdd_string_override)) - vdd_override = vdd_string_override; - if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) { - vdd_target = vdd_override * 10; /* convert to 1/10 mV */ - debug("VID: VDD override is %lu\n", vdd_override); - } else if (vdd_override != 0) { - printf("VID: Invalid VDD value.\n"); - } - if (vdd_target == 0) { - debug("VID: VID not used\n"); - ret = 0; - goto exit; - } else { - /* divide and round up by 10 to get a value in mV */ - vdd_target = DIV_ROUND_UP(vdd_target, 10); - debug("VID: vid = %d mV\n", vdd_target); - } - - /* - * Read voltage monitor to check real voltage. - */ - vdd_last = read_voltage(i2caddress); - if (vdd_last < 0) { - printf("VID: Couldn't read sensor abort VID adjustment\n"); - ret = -1; - goto exit; - } - vdd_current = vdd_last; - debug("VID: Core voltage is currently at %d mV\n", vdd_last); - -#if defined(CONFIG_VOL_MONITOR_LTC3882_SET) || \ - defined(CONFIG_VOL_MONITOR_ISL68233_SET) - /* Set the target voltage */ - vdd_current = set_voltage(i2caddress, vdd_target); - vdd_last = vdd_current; -#else - /* - * Adjust voltage to at or one step above target. - * As measurements are less precise than setting the values - * we may run through dummy steps that cancel each other - * when stepping up and then down. - */ - while (vdd_last > 0 && - vdd_last < vdd_target) { - vdd_current += IR_VDD_STEP_UP; - vdd_last = set_voltage(i2caddress, vdd_current); - } - while (vdd_last > 0 && - vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) { - vdd_current -= IR_VDD_STEP_DOWN; - vdd_last = set_voltage(i2caddress, vdd_current); - } -#endif - - /* Board specific adjustments */ - if (board_adjust_vdd(vdd_target) < 0) { - ret = -1; - goto exit; - } - - if (vdd_last > 0) - printf("VID: Core voltage after adjustment is at %d mV\n", - vdd_last); - else - ret = -1; -exit: - if (re_enable) - enable_interrupts(); - - i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); - - return ret; -} - -static int print_vdd(void) -{ - int vdd_last, ret, i2caddress = I2C_VOL_MONITOR_ADDR; - - ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); - if (ret) { - debug("VID : I2c failed to switch channel\n"); - return -1; - } -#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ - defined(CONFIG_VOL_MONITOR_IR36021_READ) - ret = find_ir_chip_on_i2c(); - if (ret < 0) { - printf("VID: Could not find voltage regulator on I2C.\n"); - goto exit; - } else { - i2caddress = ret; - debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); - } -#endif - - /* - * Read voltage monitor to check real voltage. - */ - vdd_last = read_voltage(i2caddress); - if (vdd_last < 0) { - printf("VID: Couldn't read sensor abort VID adjustment\n"); - goto exit; - } - printf("VID: Core voltage is at %d mV\n", vdd_last); -exit: - i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); - - return ret < 0 ? -1 : 0; -} - -static int do_vdd_override(struct cmd_tbl *cmdtp, - int flag, int argc, - char *const argv[]) -{ - ulong override; - int ret = 0; - - if (argc < 2) - return CMD_RET_USAGE; - - if (!strict_strtoul(argv[1], 10, &override)) { - ret = adjust_vdd(override); - if (ret < 0) - return CMD_RET_FAILURE; - } else - return CMD_RET_USAGE; - return 0; -} - -static int do_vdd_read(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - if (argc < 1) - return CMD_RET_USAGE; - print_vdd(); - - return 0; -} - -U_BOOT_CMD( - vdd_override, 2, 0, do_vdd_override, - "override VDD", - " - override with the voltage specified in mV, eg. 1050" -); - -U_BOOT_CMD( - vdd_read, 1, 0, do_vdd_read, - "read VDD", - " - Read the voltage specified in mV" -); diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h deleted file mode 100644 index b34c080b4ba..00000000000 --- a/board/freescale/common/vid.h +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - */ - -#ifndef __VID_H_ -#define __VID_H_ - -/* IR36021 command codes */ -#define IR36021_LOOP1_MANUAL_ID_OFFSET 0x6A -#define IR36021_LOOP1_VOUT_OFFSET 0x9A -#define IR36021_MFR_ID_OFFSET 0x92 -#define IR36021_MFR_ID 0x43 -#define IR36021_INTEL_MODE_OFFSET 0x14 -#define IR36021_MODE_MASK 0x20 -#define IR36021_INTEL_MODE 0x00 -#define IR36021_AMD_MODE 0x20 - -/* Step the IR regulator in 5mV increments */ -#define IR_VDD_STEP_DOWN 5 -#define IR_VDD_STEP_UP 5 - -/* LTC3882 */ -#define PMBUS_CMD_WRITE_PROTECT 0x10 -/* - * WRITE_PROTECT command supported values - * 0x80: Disable all writes except WRITE_PROTECT, PAGE, - * STORE_USER_ALL and MFR_EE_UNLOCK commands. - * 0x40: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ALL, - * MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS and CLEAR_FAULTS commands. - * Individual faults can also be cleared by writing a 1 to the - * respective status bit. - * 0x20: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ ALL, - * MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS, CLEAR_FAULTS, ON_OFF_CONFIG - * and VOUT_COMMAND commands. Individual faults can be cleared by - * writing a 1 to the respective status bit. - * 0x00: Enables write to all commands - */ -#define EN_WRITE_ALL_CMD (0) - -#ifdef CONFIG_TARGET_LX2160ARDB -/* The lowest and highest voltage allowed*/ -#define VDD_MV_MIN 775 -#define VDD_MV_MAX 855 -#endif - -#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) -/* The lowest and highest voltage allowed*/ -#define VDD_MV_MIN 775 -#define VDD_MV_MAX 925 -#endif - -/* PM Bus commands code for LTC3882*/ -#define PWM_CHANNEL0 0x0 -#define PMBUS_CMD_PAGE 0x0 -#define PMBUS_CMD_READ_VOUT 0x8B -#define PMBUS_CMD_VOUT_MODE 0x20 -#define PMBUS_CMD_VOUT_COMMAND 0x21 -#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 - -#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \ -defined(CONFIG_TARGET_LX2160ARDB) -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 -#define I2C_VOL_MONITOR_ADDR 0x63 -#define I2C_MUX_CH_VOL_MONITOR 0xA -#endif - -int adjust_vdd(ulong vdd_override); -u16 soc_get_fuse_vid(int vid_index); - -#endif /* __VID_H_ */ diff --git a/board/freescale/common/vsc3316_3308.h b/board/freescale/common/vsc3316_3308.h deleted file mode 100644 index 9725d6d9e39..00000000000 --- a/board/freescale/common/vsc3316_3308.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - */ - -#ifndef __VSC_CROSSBAR_H_ -#define __VSC_CROSSBAR_H_ - -#include -#include - -int vsc_if_enable(unsigned int vsc_addr); -int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2], - unsigned int num_con); -#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR -int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2], - unsigned int num_con); -#endif -int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2], - unsigned int num_con); -void vsc_wp_config(unsigned int vsc_addr); - -#endif /* __VSC_CROSSBAR_H_ */ diff --git a/board/freescale/imx8mm_evk/Kconfig b/board/freescale/imx8mm_evk/Kconfig deleted file mode 100644 index 24cc526b0ab..00000000000 --- a/board/freescale/imx8mm_evk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_IMX8MM_EVK - -config SYS_BOARD - default "imx8mm_evk" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "imx8mm_evk" - -config IMX_CONFIG - default "board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg" - -endif diff --git a/board/freescale/imx8mm_evk/MAINTAINERS b/board/freescale/imx8mm_evk/MAINTAINERS deleted file mode 100644 index 875adf58ee2..00000000000 --- a/board/freescale/imx8mm_evk/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -i.MX8MM EVK BOARD -M: Peng Fan -S: Maintained -F: board/freescale/imx8mm_evk/ -F: include/configs/imx8mm_evk.h -F: configs/imx8mm_evk_defconfig -F: configs/imx8mm_evk_fspi_defconfig diff --git a/board/freescale/imx8mm_evk/Makefile b/board/freescale/imx8mm_evk/Makefile deleted file mode 100644 index 9fecd8dd8cb..00000000000 --- a/board/freescale/imx8mm_evk/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright 2018 NXP -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += imx8mm_evk.o - -ifdef CONFIG_XPL_BUILD -obj-y += spl.o -obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o -endif diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c deleted file mode 100644 index ecc20768cb5..00000000000 --- a/board/freescale/imx8mm_evk/imx8mm_evk.c +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 NXP - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) -#define IMX_BOOT_IMAGE_GUID \ - EFI_GUID(0xead2005e, 0x7780, 0x400b, 0x93, 0x48, \ - 0xa2, 0x82, 0xeb, 0x85, 0x8b, 0x6b) - -struct efi_fw_image fw_images[] = { - { - .image_type_id = IMX_BOOT_IMAGE_GUID, - .fw_name = u"IMX8MM-EVK-RAW", - .image_index = 1, - }, -}; - -struct efi_capsule_update_info update_info = { - .dfu_string = "mmc 2=flash-bin raw 0x42 0x2000 mmcpart 1", - .num_images = ARRAY_SIZE(fw_images), - .images = fw_images, -}; -#endif /* EFI_HAVE_CAPSULE_SUPPORT */ - -#if IS_ENABLED(CONFIG_FEC_MXC) -static int setup_fec(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - /* Use 125M anatop REF_CLK1 for ENET1, not from external */ - clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - /* enable rgmii rxc skew and phy mode select to RGMII copper */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); - - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); - - if (phydev->drv->config) - phydev->drv->config(phydev); - return 0; -} -#endif - -int board_init(void) -{ - if (IS_ENABLED(CONFIG_FEC_MXC)) - setup_fec(); - - return 0; -} - -int board_mmc_get_env_dev(int devno) -{ - return devno; -} - -int board_late_init(void) -{ - if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) - board_late_mmc_env_init(); - - if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { - env_set("board_name", "EVK"); - env_set("board_rev", "iMX8MM"); - } - - return 0; -} diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.env b/board/freescale/imx8mm_evk/imx8mm_evk.env deleted file mode 100644 index 299b8472c74..00000000000 --- a/board/freescale/imx8mm_evk/imx8mm_evk.env +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ - -boot_fdt=try -boot_fit=no -boot_targets=mmc1 mmc2 dhcp -bootm_size=0x10000000 -console=ttymxc1,115200 -fdt_addr_r=0x48000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE -fdtoverlay_addr_r=0x49000000 -initrd_addr=0x48080000 -image=Image -ip_dyn=yes -kernel_addr_r=0x42000000 -loadaddr=CONFIG_SYS_LOAD_ADDR -mmcautodetect=yes -mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX -mmcpart=1 -mmcroot=/dev/mmcblk1p2 rootwait rw -prepare_mcore=setenv mcore_clk clk-imx8mm.mcore_booted; -pxefile_addr_r=0x40100000 -ramdisk_addr_r=0x48080000 -scriptaddr=0x40000000 - -mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} -prepare_mcore=setenv mcore_clk clk-imx8mn.mcore_booted -loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} -loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -mmcboot=echo Booting from mmc ...; - run mmcargs; - if test ${boot_fit} = yes || test ${boot_fit} = try; then - bootm ${loadaddr}; - else - if run loadfdt; then - booti ${loadaddr} - ${fdt_addr_r}; - else - echo WARN: Cannot load the DT; - fi; - fi -netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs - ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp -netboot=echo Booting from net ...; - run netargs; - if test ${ip_dyn} = yes; then - setenv get_cmd dhcp; - else - setenv get_cmd tftp; - fi; - ${get_cmd} ${loadaddr} ${image}; - if test ${boot_fit} = yes || test ${boot_fit} = try; then - bootm ${loadaddr}; - else - if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then - booti ${loadaddr} - ${fdt_addr_r}; - else - echo WARN: Cannot load the DT; - fi; - fi; -bsp_bootcmd=echo Running BSP bootcmd ...; - mmc dev ${mmcdev}; - if mmc rescan; then - if run loadimage; then - run mmcboot; - else - run netboot; - fi; - fi; diff --git a/board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg b/board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg deleted file mode 100644 index fcace8a93a0..00000000000 --- a/board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2021 NXP - */ - -BOOT_FROM fspi -LOADER u-boot-spl-ddr.bin 0x7E2000 diff --git a/board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg b/board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg deleted file mode 100644 index 20061521f22..00000000000 --- a/board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2021 NXP - */ - - -BOOT_FROM sd -LOADER u-boot-spl-ddr.bin 0x7E1000 diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c b/board/freescale/imx8mm_evk/lpddr4_timing.c deleted file mode 100644 index 4373ca624e4..00000000000 --- a/board/freescale/imx8mm_evk/lpddr4_timing.c +++ /dev/null @@ -1,1848 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018-2019 NXP - * - * Generated code from MX8M_DDR_tool - */ - -#include -#include - -struct dram_cfg_param ddr_ddrc_cfg[] = { - /* Initialize DDRC registers */ - { 0x3d400304, 0x1 }, - { 0x3d400030, 0x1 }, - { 0x3d400000, 0xa1080020 }, - { 0x3d400020, 0x223 }, - { 0x3d400024, 0x16e3600 }, - { 0x3d400064, 0x5b00d2 }, - { 0x3d4000d0, 0xc00305ba }, - { 0x3d4000d4, 0x940000 }, - { 0x3d4000dc, 0xd4002d }, - { 0x3d4000e0, 0x310000 }, - { 0x3d4000e8, 0x66004d }, - { 0x3d4000ec, 0x16004d }, - { 0x3d400100, 0x191e1920 }, - { 0x3d400104, 0x60630 }, - { 0x3d40010c, 0xb0b000 }, - { 0x3d400110, 0xe04080e }, - { 0x3d400114, 0x2040c0c }, - { 0x3d400118, 0x1010007 }, - { 0x3d40011c, 0x401 }, - { 0x3d400130, 0x20600 }, - { 0x3d400134, 0xc100002 }, - { 0x3d400138, 0xd8 }, - { 0x3d400144, 0x96004b }, - { 0x3d400180, 0x2ee0017 }, - { 0x3d400184, 0x2605b8e }, - { 0x3d400188, 0x0 }, - { 0x3d400190, 0x497820a }, - { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x170a }, - { 0x3d4001a0, 0xe0400018 }, - { 0x3d4001a4, 0xdf00e4 }, - { 0x3d4001a8, 0x80000000 }, - { 0x3d4001b0, 0x11 }, - { 0x3d4001c0, 0x1 }, - { 0x3d4001c4, 0x0 }, - { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x70e1617 }, - { 0x3d400200, 0x1f }, - { 0x3d40020c, 0x0 }, - { 0x3d400210, 0x1f1f }, - { 0x3d400204, 0x80808 }, - { 0x3d400214, 0x7070707 }, - { 0x3d400218, 0x7070707 }, - - /* performance setting */ - { 0x3d400250, 0x29001701 }, - { 0x3d400254, 0x2c }, - { 0x3d40025c, 0x4000030 }, - { 0x3d400264, 0x900093e7 }, - { 0x3d40026c, 0x2005574 }, - { 0x3d400400, 0x111 }, - { 0x3d400408, 0x72ff }, - { 0x3d400494, 0x2100e07 }, - { 0x3d400498, 0x620096 }, - { 0x3d40049c, 0x1100e07 }, - { 0x3d4004a0, 0xc8012c }, - - /* P1: 400mts */ - { 0x3d402020, 0x21 }, - { 0x3d402024, 0x30d400 }, - { 0x3d402050, 0x20d040 }, - { 0x3d402064, 0xc001c }, - { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0x310000 }, - { 0x3d4020e8, 0x66004d }, - { 0x3d4020ec, 0x16004d }, - { 0x3d402100, 0xa040305 }, - { 0x3d402104, 0x30407 }, - { 0x3d402108, 0x203060b }, - { 0x3d40210c, 0x505000 }, - { 0x3d402110, 0x2040202 }, - { 0x3d402114, 0x2030202 }, - { 0x3d402118, 0x1010004 }, - { 0x3d40211c, 0x301 }, - { 0x3d402130, 0x20300 }, - { 0x3d402134, 0xa100002 }, - { 0x3d402138, 0x1d }, - { 0x3d402144, 0x14000a }, - { 0x3d402180, 0x640004 }, - { 0x3d402190, 0x3818200 }, - { 0x3d402194, 0x80303 }, - { 0x3d4021b4, 0x100 }, - - /* p2: 100mts */ - { 0x3d403020, 0x21 }, - { 0x3d403024, 0xc3500 }, - { 0x3d403050, 0x20d040 }, - { 0x3d403064, 0x30007 }, - { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0x310000 }, - { 0x3d4030e8, 0x66004d }, - { 0x3d4030ec, 0x16004d }, - { 0x3d403100, 0xa010102 }, - { 0x3d403104, 0x30404 }, - { 0x3d403108, 0x203060b }, - { 0x3d40310c, 0x505000 }, - { 0x3d403110, 0x2040202 }, - { 0x3d403114, 0x2030202 }, - { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x301 }, - { 0x3d403130, 0x20300 }, - { 0x3d403134, 0xa100002 }, - { 0x3d403138, 0x8 }, - { 0x3d403144, 0x50003 }, - { 0x3d403180, 0x190004 }, - { 0x3d403190, 0x3818200 }, - { 0x3d403194, 0x80303 }, - { 0x3d4031b4, 0x100 }, - - /* default boot point */ - { 0x3d400028, 0x0 }, -}; - -/* PHY Initialize Configuration */ -struct dram_cfg_param ddr_ddrphy_cfg[] = { - { 0x100a0, 0x0 }, - { 0x100a1, 0x1 }, - { 0x100a2, 0x2 }, - { 0x100a3, 0x3 }, - { 0x100a4, 0x4 }, - { 0x100a5, 0x5 }, - { 0x100a6, 0x6 }, - { 0x100a7, 0x7 }, - { 0x110a0, 0x0 }, - { 0x110a1, 0x1 }, - { 0x110a2, 0x3 }, - { 0x110a3, 0x4 }, - { 0x110a4, 0x5 }, - { 0x110a5, 0x2 }, - { 0x110a6, 0x7 }, - { 0x110a7, 0x6 }, - { 0x120a0, 0x0 }, - { 0x120a1, 0x1 }, - { 0x120a2, 0x3 }, - { 0x120a3, 0x2 }, - { 0x120a4, 0x5 }, - { 0x120a5, 0x4 }, - { 0x120a6, 0x7 }, - { 0x120a7, 0x6 }, - { 0x130a0, 0x0 }, - { 0x130a1, 0x1 }, - { 0x130a2, 0x2 }, - { 0x130a3, 0x3 }, - { 0x130a4, 0x4 }, - { 0x130a5, 0x5 }, - { 0x130a6, 0x6 }, - { 0x130a7, 0x7 }, - { 0x1005f, 0x1ff }, - { 0x1015f, 0x1ff }, - { 0x1105f, 0x1ff }, - { 0x1115f, 0x1ff }, - { 0x1205f, 0x1ff }, - { 0x1215f, 0x1ff }, - { 0x1305f, 0x1ff }, - { 0x1315f, 0x1ff }, - { 0x11005f, 0x1ff }, - { 0x11015f, 0x1ff }, - { 0x11105f, 0x1ff }, - { 0x11115f, 0x1ff }, - { 0x11205f, 0x1ff }, - { 0x11215f, 0x1ff }, - { 0x11305f, 0x1ff }, - { 0x11315f, 0x1ff }, - { 0x21005f, 0x1ff }, - { 0x21015f, 0x1ff }, - { 0x21105f, 0x1ff }, - { 0x21115f, 0x1ff }, - { 0x21205f, 0x1ff }, - { 0x21215f, 0x1ff }, - { 0x21305f, 0x1ff }, - { 0x21315f, 0x1ff }, - { 0x55, 0x1ff }, - { 0x1055, 0x1ff }, - { 0x2055, 0x1ff }, - { 0x3055, 0x1ff }, - { 0x4055, 0x1ff }, - { 0x5055, 0x1ff }, - { 0x6055, 0x1ff }, - { 0x7055, 0x1ff }, - { 0x8055, 0x1ff }, - { 0x9055, 0x1ff }, - { 0x200c5, 0x19 }, - { 0x1200c5, 0x7 }, - { 0x2200c5, 0x7 }, - { 0x2002e, 0x2 }, - { 0x12002e, 0x2 }, - { 0x22002e, 0x2 }, - { 0x90204, 0x0 }, - { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - { 0x20024, 0x1ab }, - { 0x2003a, 0x0 }, - { 0x120024, 0x1ab }, - { 0x2003a, 0x0 }, - { 0x220024, 0x1ab }, - { 0x2003a, 0x0 }, - { 0x20056, 0x3 }, - { 0x120056, 0xa }, - { 0x220056, 0xa }, - { 0x1004d, 0xe00 }, - { 0x1014d, 0xe00 }, - { 0x1104d, 0xe00 }, - { 0x1114d, 0xe00 }, - { 0x1204d, 0xe00 }, - { 0x1214d, 0xe00 }, - { 0x1304d, 0xe00 }, - { 0x1314d, 0xe00 }, - { 0x11004d, 0xe00 }, - { 0x11014d, 0xe00 }, - { 0x11104d, 0xe00 }, - { 0x11114d, 0xe00 }, - { 0x11204d, 0xe00 }, - { 0x11214d, 0xe00 }, - { 0x11304d, 0xe00 }, - { 0x11314d, 0xe00 }, - { 0x21004d, 0xe00 }, - { 0x21014d, 0xe00 }, - { 0x21104d, 0xe00 }, - { 0x21114d, 0xe00 }, - { 0x21204d, 0xe00 }, - { 0x21214d, 0xe00 }, - { 0x21304d, 0xe00 }, - { 0x21314d, 0xe00 }, - { 0x10049, 0xeba }, - { 0x10149, 0xeba }, - { 0x11049, 0xeba }, - { 0x11149, 0xeba }, - { 0x12049, 0xeba }, - { 0x12149, 0xeba }, - { 0x13049, 0xeba }, - { 0x13149, 0xeba }, - { 0x110049, 0xeba }, - { 0x110149, 0xeba }, - { 0x111049, 0xeba }, - { 0x111149, 0xeba }, - { 0x112049, 0xeba }, - { 0x112149, 0xeba }, - { 0x113049, 0xeba }, - { 0x113149, 0xeba }, - { 0x210049, 0xeba }, - { 0x210149, 0xeba }, - { 0x211049, 0xeba }, - { 0x211149, 0xeba }, - { 0x212049, 0xeba }, - { 0x212149, 0xeba }, - { 0x213049, 0xeba }, - { 0x213149, 0xeba }, - { 0x43, 0x63 }, - { 0x1043, 0x63 }, - { 0x2043, 0x63 }, - { 0x3043, 0x63 }, - { 0x4043, 0x63 }, - { 0x5043, 0x63 }, - { 0x6043, 0x63 }, - { 0x7043, 0x63 }, - { 0x8043, 0x63 }, - { 0x9043, 0x63 }, - { 0x20018, 0x3 }, - { 0x20075, 0x4 }, - { 0x20050, 0x0 }, - { 0x20008, 0x2ee }, - { 0x120008, 0x64 }, - { 0x220008, 0x19 }, - { 0x20088, 0x9 }, - { 0x200b2, 0xdc }, - { 0x10043, 0x5a1 }, - { 0x10143, 0x5a1 }, - { 0x11043, 0x5a1 }, - { 0x11143, 0x5a1 }, - { 0x12043, 0x5a1 }, - { 0x12143, 0x5a1 }, - { 0x13043, 0x5a1 }, - { 0x13143, 0x5a1 }, - { 0x1200b2, 0xdc }, - { 0x110043, 0x5a1 }, - { 0x110143, 0x5a1 }, - { 0x111043, 0x5a1 }, - { 0x111143, 0x5a1 }, - { 0x112043, 0x5a1 }, - { 0x112143, 0x5a1 }, - { 0x113043, 0x5a1 }, - { 0x113143, 0x5a1 }, - { 0x2200b2, 0xdc }, - { 0x210043, 0x5a1 }, - { 0x210143, 0x5a1 }, - { 0x211043, 0x5a1 }, - { 0x211143, 0x5a1 }, - { 0x212043, 0x5a1 }, - { 0x212143, 0x5a1 }, - { 0x213043, 0x5a1 }, - { 0x213143, 0x5a1 }, - { 0x200fa, 0x1 }, - { 0x1200fa, 0x1 }, - { 0x2200fa, 0x1 }, - { 0x20019, 0x1 }, - { 0x120019, 0x1 }, - { 0x220019, 0x1 }, - { 0x200f0, 0x660 }, - { 0x200f1, 0x0 }, - { 0x200f2, 0x4444 }, - { 0x200f3, 0x8888 }, - { 0x200f4, 0x5665 }, - { 0x200f5, 0x0 }, - { 0x200f6, 0x0 }, - { 0x200f7, 0xf000 }, - { 0x20025, 0x0 }, - { 0x2002d, 0x0 }, - { 0x12002d, 0x0 }, - { 0x22002d, 0x0 }, - { 0x200c7, 0x21 }, - { 0x1200c7, 0x21 }, - { 0x2200c7, 0x21 }, - { 0x200ca, 0x24 }, - { 0x1200ca, 0x24 }, - { 0x2200ca, 0x24 }, -}; - -/* ddr phy trained csr */ -struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - { 0x200b2, 0x0 }, - { 0x1200b2, 0x0 }, - { 0x2200b2, 0x0 }, - { 0x200cb, 0x0 }, - { 0x10043, 0x0 }, - { 0x110043, 0x0 }, - { 0x210043, 0x0 }, - { 0x10143, 0x0 }, - { 0x110143, 0x0 }, - { 0x210143, 0x0 }, - { 0x11043, 0x0 }, - { 0x111043, 0x0 }, - { 0x211043, 0x0 }, - { 0x11143, 0x0 }, - { 0x111143, 0x0 }, - { 0x211143, 0x0 }, - { 0x12043, 0x0 }, - { 0x112043, 0x0 }, - { 0x212043, 0x0 }, - { 0x12143, 0x0 }, - { 0x112143, 0x0 }, - { 0x212143, 0x0 }, - { 0x13043, 0x0 }, - { 0x113043, 0x0 }, - { 0x213043, 0x0 }, - { 0x13143, 0x0 }, - { 0x113143, 0x0 }, - { 0x213143, 0x0 }, - { 0x80, 0x0 }, - { 0x100080, 0x0 }, - { 0x200080, 0x0 }, - { 0x1080, 0x0 }, - { 0x101080, 0x0 }, - { 0x201080, 0x0 }, - { 0x2080, 0x0 }, - { 0x102080, 0x0 }, - { 0x202080, 0x0 }, - { 0x3080, 0x0 }, - { 0x103080, 0x0 }, - { 0x203080, 0x0 }, - { 0x4080, 0x0 }, - { 0x104080, 0x0 }, - { 0x204080, 0x0 }, - { 0x5080, 0x0 }, - { 0x105080, 0x0 }, - { 0x205080, 0x0 }, - { 0x6080, 0x0 }, - { 0x106080, 0x0 }, - { 0x206080, 0x0 }, - { 0x7080, 0x0 }, - { 0x107080, 0x0 }, - { 0x207080, 0x0 }, - { 0x8080, 0x0 }, - { 0x108080, 0x0 }, - { 0x208080, 0x0 }, - { 0x9080, 0x0 }, - { 0x109080, 0x0 }, - { 0x209080, 0x0 }, - { 0x10080, 0x0 }, - { 0x110080, 0x0 }, - { 0x210080, 0x0 }, - { 0x10180, 0x0 }, - { 0x110180, 0x0 }, - { 0x210180, 0x0 }, - { 0x11080, 0x0 }, - { 0x111080, 0x0 }, - { 0x211080, 0x0 }, - { 0x11180, 0x0 }, - { 0x111180, 0x0 }, - { 0x211180, 0x0 }, - { 0x12080, 0x0 }, - { 0x112080, 0x0 }, - { 0x212080, 0x0 }, - { 0x12180, 0x0 }, - { 0x112180, 0x0 }, - { 0x212180, 0x0 }, - { 0x13080, 0x0 }, - { 0x113080, 0x0 }, - { 0x213080, 0x0 }, - { 0x13180, 0x0 }, - { 0x113180, 0x0 }, - { 0x213180, 0x0 }, - { 0x10081, 0x0 }, - { 0x110081, 0x0 }, - { 0x210081, 0x0 }, - { 0x10181, 0x0 }, - { 0x110181, 0x0 }, - { 0x210181, 0x0 }, - { 0x11081, 0x0 }, - { 0x111081, 0x0 }, - { 0x211081, 0x0 }, - { 0x11181, 0x0 }, - { 0x111181, 0x0 }, - { 0x211181, 0x0 }, - { 0x12081, 0x0 }, - { 0x112081, 0x0 }, - { 0x212081, 0x0 }, - { 0x12181, 0x0 }, - { 0x112181, 0x0 }, - { 0x212181, 0x0 }, - { 0x13081, 0x0 }, - { 0x113081, 0x0 }, - { 0x213081, 0x0 }, - { 0x13181, 0x0 }, - { 0x113181, 0x0 }, - { 0x213181, 0x0 }, - { 0x100d0, 0x0 }, - { 0x1100d0, 0x0 }, - { 0x2100d0, 0x0 }, - { 0x101d0, 0x0 }, - { 0x1101d0, 0x0 }, - { 0x2101d0, 0x0 }, - { 0x110d0, 0x0 }, - { 0x1110d0, 0x0 }, - { 0x2110d0, 0x0 }, - { 0x111d0, 0x0 }, - { 0x1111d0, 0x0 }, - { 0x2111d0, 0x0 }, - { 0x120d0, 0x0 }, - { 0x1120d0, 0x0 }, - { 0x2120d0, 0x0 }, - { 0x121d0, 0x0 }, - { 0x1121d0, 0x0 }, - { 0x2121d0, 0x0 }, - { 0x130d0, 0x0 }, - { 0x1130d0, 0x0 }, - { 0x2130d0, 0x0 }, - { 0x131d0, 0x0 }, - { 0x1131d0, 0x0 }, - { 0x2131d0, 0x0 }, - { 0x100d1, 0x0 }, - { 0x1100d1, 0x0 }, - { 0x2100d1, 0x0 }, - { 0x101d1, 0x0 }, - { 0x1101d1, 0x0 }, - { 0x2101d1, 0x0 }, - { 0x110d1, 0x0 }, - { 0x1110d1, 0x0 }, - { 0x2110d1, 0x0 }, - { 0x111d1, 0x0 }, - { 0x1111d1, 0x0 }, - { 0x2111d1, 0x0 }, - { 0x120d1, 0x0 }, - { 0x1120d1, 0x0 }, - { 0x2120d1, 0x0 }, - { 0x121d1, 0x0 }, - { 0x1121d1, 0x0 }, - { 0x2121d1, 0x0 }, - { 0x130d1, 0x0 }, - { 0x1130d1, 0x0 }, - { 0x2130d1, 0x0 }, - { 0x131d1, 0x0 }, - { 0x1131d1, 0x0 }, - { 0x2131d1, 0x0 }, - { 0x10068, 0x0 }, - { 0x10168, 0x0 }, - { 0x10268, 0x0 }, - { 0x10368, 0x0 }, - { 0x10468, 0x0 }, - { 0x10568, 0x0 }, - { 0x10668, 0x0 }, - { 0x10768, 0x0 }, - { 0x10868, 0x0 }, - { 0x11068, 0x0 }, - { 0x11168, 0x0 }, - { 0x11268, 0x0 }, - { 0x11368, 0x0 }, - { 0x11468, 0x0 }, - { 0x11568, 0x0 }, - { 0x11668, 0x0 }, - { 0x11768, 0x0 }, - { 0x11868, 0x0 }, - { 0x12068, 0x0 }, - { 0x12168, 0x0 }, - { 0x12268, 0x0 }, - { 0x12368, 0x0 }, - { 0x12468, 0x0 }, - { 0x12568, 0x0 }, - { 0x12668, 0x0 }, - { 0x12768, 0x0 }, - { 0x12868, 0x0 }, - { 0x13068, 0x0 }, - { 0x13168, 0x0 }, - { 0x13268, 0x0 }, - { 0x13368, 0x0 }, - { 0x13468, 0x0 }, - { 0x13568, 0x0 }, - { 0x13668, 0x0 }, - { 0x13768, 0x0 }, - { 0x13868, 0x0 }, - { 0x10069, 0x0 }, - { 0x10169, 0x0 }, - { 0x10269, 0x0 }, - { 0x10369, 0x0 }, - { 0x10469, 0x0 }, - { 0x10569, 0x0 }, - { 0x10669, 0x0 }, - { 0x10769, 0x0 }, - { 0x10869, 0x0 }, - { 0x11069, 0x0 }, - { 0x11169, 0x0 }, - { 0x11269, 0x0 }, - { 0x11369, 0x0 }, - { 0x11469, 0x0 }, - { 0x11569, 0x0 }, - { 0x11669, 0x0 }, - { 0x11769, 0x0 }, - { 0x11869, 0x0 }, - { 0x12069, 0x0 }, - { 0x12169, 0x0 }, - { 0x12269, 0x0 }, - { 0x12369, 0x0 }, - { 0x12469, 0x0 }, - { 0x12569, 0x0 }, - { 0x12669, 0x0 }, - { 0x12769, 0x0 }, - { 0x12869, 0x0 }, - { 0x13069, 0x0 }, - { 0x13169, 0x0 }, - { 0x13269, 0x0 }, - { 0x13369, 0x0 }, - { 0x13469, 0x0 }, - { 0x13569, 0x0 }, - { 0x13669, 0x0 }, - { 0x13769, 0x0 }, - { 0x13869, 0x0 }, - { 0x1008c, 0x0 }, - { 0x11008c, 0x0 }, - { 0x21008c, 0x0 }, - { 0x1018c, 0x0 }, - { 0x11018c, 0x0 }, - { 0x21018c, 0x0 }, - { 0x1108c, 0x0 }, - { 0x11108c, 0x0 }, - { 0x21108c, 0x0 }, - { 0x1118c, 0x0 }, - { 0x11118c, 0x0 }, - { 0x21118c, 0x0 }, - { 0x1208c, 0x0 }, - { 0x11208c, 0x0 }, - { 0x21208c, 0x0 }, - { 0x1218c, 0x0 }, - { 0x11218c, 0x0 }, - { 0x21218c, 0x0 }, - { 0x1308c, 0x0 }, - { 0x11308c, 0x0 }, - { 0x21308c, 0x0 }, - { 0x1318c, 0x0 }, - { 0x11318c, 0x0 }, - { 0x21318c, 0x0 }, - { 0x1008d, 0x0 }, - { 0x11008d, 0x0 }, - { 0x21008d, 0x0 }, - { 0x1018d, 0x0 }, - { 0x11018d, 0x0 }, - { 0x21018d, 0x0 }, - { 0x1108d, 0x0 }, - { 0x11108d, 0x0 }, - { 0x21108d, 0x0 }, - { 0x1118d, 0x0 }, - { 0x11118d, 0x0 }, - { 0x21118d, 0x0 }, - { 0x1208d, 0x0 }, - { 0x11208d, 0x0 }, - { 0x21208d, 0x0 }, - { 0x1218d, 0x0 }, - { 0x11218d, 0x0 }, - { 0x21218d, 0x0 }, - { 0x1308d, 0x0 }, - { 0x11308d, 0x0 }, - { 0x21308d, 0x0 }, - { 0x1318d, 0x0 }, - { 0x11318d, 0x0 }, - { 0x21318d, 0x0 }, - { 0x100c0, 0x0 }, - { 0x1100c0, 0x0 }, - { 0x2100c0, 0x0 }, - { 0x101c0, 0x0 }, - { 0x1101c0, 0x0 }, - { 0x2101c0, 0x0 }, - { 0x102c0, 0x0 }, - { 0x1102c0, 0x0 }, - { 0x2102c0, 0x0 }, - { 0x103c0, 0x0 }, - { 0x1103c0, 0x0 }, - { 0x2103c0, 0x0 }, - { 0x104c0, 0x0 }, - { 0x1104c0, 0x0 }, - { 0x2104c0, 0x0 }, - { 0x105c0, 0x0 }, - { 0x1105c0, 0x0 }, - { 0x2105c0, 0x0 }, - { 0x106c0, 0x0 }, - { 0x1106c0, 0x0 }, - { 0x2106c0, 0x0 }, - { 0x107c0, 0x0 }, - { 0x1107c0, 0x0 }, - { 0x2107c0, 0x0 }, - { 0x108c0, 0x0 }, - { 0x1108c0, 0x0 }, - { 0x2108c0, 0x0 }, - { 0x110c0, 0x0 }, - { 0x1110c0, 0x0 }, - { 0x2110c0, 0x0 }, - { 0x111c0, 0x0 }, - { 0x1111c0, 0x0 }, - { 0x2111c0, 0x0 }, - { 0x112c0, 0x0 }, - { 0x1112c0, 0x0 }, - { 0x2112c0, 0x0 }, - { 0x113c0, 0x0 }, - { 0x1113c0, 0x0 }, - { 0x2113c0, 0x0 }, - { 0x114c0, 0x0 }, - { 0x1114c0, 0x0 }, - { 0x2114c0, 0x0 }, - { 0x115c0, 0x0 }, - { 0x1115c0, 0x0 }, - { 0x2115c0, 0x0 }, - { 0x116c0, 0x0 }, - { 0x1116c0, 0x0 }, - { 0x2116c0, 0x0 }, - { 0x117c0, 0x0 }, - { 0x1117c0, 0x0 }, - { 0x2117c0, 0x0 }, - { 0x118c0, 0x0 }, - { 0x1118c0, 0x0 }, - { 0x2118c0, 0x0 }, - { 0x120c0, 0x0 }, - { 0x1120c0, 0x0 }, - { 0x2120c0, 0x0 }, - { 0x121c0, 0x0 }, - { 0x1121c0, 0x0 }, - { 0x2121c0, 0x0 }, - { 0x122c0, 0x0 }, - { 0x1122c0, 0x0 }, - { 0x2122c0, 0x0 }, - { 0x123c0, 0x0 }, - { 0x1123c0, 0x0 }, - { 0x2123c0, 0x0 }, - { 0x124c0, 0x0 }, - { 0x1124c0, 0x0 }, - { 0x2124c0, 0x0 }, - { 0x125c0, 0x0 }, - { 0x1125c0, 0x0 }, - { 0x2125c0, 0x0 }, - { 0x126c0, 0x0 }, - { 0x1126c0, 0x0 }, - { 0x2126c0, 0x0 }, - { 0x127c0, 0x0 }, - { 0x1127c0, 0x0 }, - { 0x2127c0, 0x0 }, - { 0x128c0, 0x0 }, - { 0x1128c0, 0x0 }, - { 0x2128c0, 0x0 }, - { 0x130c0, 0x0 }, - { 0x1130c0, 0x0 }, - { 0x2130c0, 0x0 }, - { 0x131c0, 0x0 }, - { 0x1131c0, 0x0 }, - { 0x2131c0, 0x0 }, - { 0x132c0, 0x0 }, - { 0x1132c0, 0x0 }, - { 0x2132c0, 0x0 }, - { 0x133c0, 0x0 }, - { 0x1133c0, 0x0 }, - { 0x2133c0, 0x0 }, - { 0x134c0, 0x0 }, - { 0x1134c0, 0x0 }, - { 0x2134c0, 0x0 }, - { 0x135c0, 0x0 }, - { 0x1135c0, 0x0 }, - { 0x2135c0, 0x0 }, - { 0x136c0, 0x0 }, - { 0x1136c0, 0x0 }, - { 0x2136c0, 0x0 }, - { 0x137c0, 0x0 }, - { 0x1137c0, 0x0 }, - { 0x2137c0, 0x0 }, - { 0x138c0, 0x0 }, - { 0x1138c0, 0x0 }, - { 0x2138c0, 0x0 }, - { 0x100c1, 0x0 }, - { 0x1100c1, 0x0 }, - { 0x2100c1, 0x0 }, - { 0x101c1, 0x0 }, - { 0x1101c1, 0x0 }, - { 0x2101c1, 0x0 }, - { 0x102c1, 0x0 }, - { 0x1102c1, 0x0 }, - { 0x2102c1, 0x0 }, - { 0x103c1, 0x0 }, - { 0x1103c1, 0x0 }, - { 0x2103c1, 0x0 }, - { 0x104c1, 0x0 }, - { 0x1104c1, 0x0 }, - { 0x2104c1, 0x0 }, - { 0x105c1, 0x0 }, - { 0x1105c1, 0x0 }, - { 0x2105c1, 0x0 }, - { 0x106c1, 0x0 }, - { 0x1106c1, 0x0 }, - { 0x2106c1, 0x0 }, - { 0x107c1, 0x0 }, - { 0x1107c1, 0x0 }, - { 0x2107c1, 0x0 }, - { 0x108c1, 0x0 }, - { 0x1108c1, 0x0 }, - { 0x2108c1, 0x0 }, - { 0x110c1, 0x0 }, - { 0x1110c1, 0x0 }, - { 0x2110c1, 0x0 }, - { 0x111c1, 0x0 }, - { 0x1111c1, 0x0 }, - { 0x2111c1, 0x0 }, - { 0x112c1, 0x0 }, - { 0x1112c1, 0x0 }, - { 0x2112c1, 0x0 }, - { 0x113c1, 0x0 }, - { 0x1113c1, 0x0 }, - { 0x2113c1, 0x0 }, - { 0x114c1, 0x0 }, - { 0x1114c1, 0x0 }, - { 0x2114c1, 0x0 }, - { 0x115c1, 0x0 }, - { 0x1115c1, 0x0 }, - { 0x2115c1, 0x0 }, - { 0x116c1, 0x0 }, - { 0x1116c1, 0x0 }, - { 0x2116c1, 0x0 }, - { 0x117c1, 0x0 }, - { 0x1117c1, 0x0 }, - { 0x2117c1, 0x0 }, - { 0x118c1, 0x0 }, - { 0x1118c1, 0x0 }, - { 0x2118c1, 0x0 }, - { 0x120c1, 0x0 }, - { 0x1120c1, 0x0 }, - { 0x2120c1, 0x0 }, - { 0x121c1, 0x0 }, - { 0x1121c1, 0x0 }, - { 0x2121c1, 0x0 }, - { 0x122c1, 0x0 }, - { 0x1122c1, 0x0 }, - { 0x2122c1, 0x0 }, - { 0x123c1, 0x0 }, - { 0x1123c1, 0x0 }, - { 0x2123c1, 0x0 }, - { 0x124c1, 0x0 }, - { 0x1124c1, 0x0 }, - { 0x2124c1, 0x0 }, - { 0x125c1, 0x0 }, - { 0x1125c1, 0x0 }, - { 0x2125c1, 0x0 }, - { 0x126c1, 0x0 }, - { 0x1126c1, 0x0 }, - { 0x2126c1, 0x0 }, - { 0x127c1, 0x0 }, - { 0x1127c1, 0x0 }, - { 0x2127c1, 0x0 }, - { 0x128c1, 0x0 }, - { 0x1128c1, 0x0 }, - { 0x2128c1, 0x0 }, - { 0x130c1, 0x0 }, - { 0x1130c1, 0x0 }, - { 0x2130c1, 0x0 }, - { 0x131c1, 0x0 }, - { 0x1131c1, 0x0 }, - { 0x2131c1, 0x0 }, - { 0x132c1, 0x0 }, - { 0x1132c1, 0x0 }, - { 0x2132c1, 0x0 }, - { 0x133c1, 0x0 }, - { 0x1133c1, 0x0 }, - { 0x2133c1, 0x0 }, - { 0x134c1, 0x0 }, - { 0x1134c1, 0x0 }, - { 0x2134c1, 0x0 }, - { 0x135c1, 0x0 }, - { 0x1135c1, 0x0 }, - { 0x2135c1, 0x0 }, - { 0x136c1, 0x0 }, - { 0x1136c1, 0x0 }, - { 0x2136c1, 0x0 }, - { 0x137c1, 0x0 }, - { 0x1137c1, 0x0 }, - { 0x2137c1, 0x0 }, - { 0x138c1, 0x0 }, - { 0x1138c1, 0x0 }, - { 0x2138c1, 0x0 }, - { 0x10020, 0x0 }, - { 0x110020, 0x0 }, - { 0x210020, 0x0 }, - { 0x11020, 0x0 }, - { 0x111020, 0x0 }, - { 0x211020, 0x0 }, - { 0x12020, 0x0 }, - { 0x112020, 0x0 }, - { 0x212020, 0x0 }, - { 0x13020, 0x0 }, - { 0x113020, 0x0 }, - { 0x213020, 0x0 }, - { 0x20072, 0x0 }, - { 0x20073, 0x0 }, - { 0x20074, 0x0 }, - { 0x100aa, 0x0 }, - { 0x110aa, 0x0 }, - { 0x120aa, 0x0 }, - { 0x130aa, 0x0 }, - { 0x20010, 0x0 }, - { 0x120010, 0x0 }, - { 0x220010, 0x0 }, - { 0x20011, 0x0 }, - { 0x120011, 0x0 }, - { 0x220011, 0x0 }, - { 0x100ae, 0x0 }, - { 0x1100ae, 0x0 }, - { 0x2100ae, 0x0 }, - { 0x100af, 0x0 }, - { 0x1100af, 0x0 }, - { 0x2100af, 0x0 }, - { 0x110ae, 0x0 }, - { 0x1110ae, 0x0 }, - { 0x2110ae, 0x0 }, - { 0x110af, 0x0 }, - { 0x1110af, 0x0 }, - { 0x2110af, 0x0 }, - { 0x120ae, 0x0 }, - { 0x1120ae, 0x0 }, - { 0x2120ae, 0x0 }, - { 0x120af, 0x0 }, - { 0x1120af, 0x0 }, - { 0x2120af, 0x0 }, - { 0x130ae, 0x0 }, - { 0x1130ae, 0x0 }, - { 0x2130ae, 0x0 }, - { 0x130af, 0x0 }, - { 0x1130af, 0x0 }, - { 0x2130af, 0x0 }, - { 0x20020, 0x0 }, - { 0x120020, 0x0 }, - { 0x220020, 0x0 }, - { 0x100a0, 0x0 }, - { 0x100a1, 0x0 }, - { 0x100a2, 0x0 }, - { 0x100a3, 0x0 }, - { 0x100a4, 0x0 }, - { 0x100a5, 0x0 }, - { 0x100a6, 0x0 }, - { 0x100a7, 0x0 }, - { 0x110a0, 0x0 }, - { 0x110a1, 0x0 }, - { 0x110a2, 0x0 }, - { 0x110a3, 0x0 }, - { 0x110a4, 0x0 }, - { 0x110a5, 0x0 }, - { 0x110a6, 0x0 }, - { 0x110a7, 0x0 }, - { 0x120a0, 0x0 }, - { 0x120a1, 0x0 }, - { 0x120a2, 0x0 }, - { 0x120a3, 0x0 }, - { 0x120a4, 0x0 }, - { 0x120a5, 0x0 }, - { 0x120a6, 0x0 }, - { 0x120a7, 0x0 }, - { 0x130a0, 0x0 }, - { 0x130a1, 0x0 }, - { 0x130a2, 0x0 }, - { 0x130a3, 0x0 }, - { 0x130a4, 0x0 }, - { 0x130a5, 0x0 }, - { 0x130a6, 0x0 }, - { 0x130a7, 0x0 }, - { 0x2007c, 0x0 }, - { 0x12007c, 0x0 }, - { 0x22007c, 0x0 }, - { 0x2007d, 0x0 }, - { 0x12007d, 0x0 }, - { 0x22007d, 0x0 }, - { 0x400fd, 0x0 }, - { 0x400c0, 0x0 }, - { 0x90201, 0x0 }, - { 0x190201, 0x0 }, - { 0x290201, 0x0 }, - { 0x90202, 0x0 }, - { 0x190202, 0x0 }, - { 0x290202, 0x0 }, - { 0x90203, 0x0 }, - { 0x190203, 0x0 }, - { 0x290203, 0x0 }, - { 0x90204, 0x0 }, - { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - { 0x90205, 0x0 }, - { 0x190205, 0x0 }, - { 0x290205, 0x0 }, - { 0x90206, 0x0 }, - { 0x190206, 0x0 }, - { 0x290206, 0x0 }, - { 0x90207, 0x0 }, - { 0x190207, 0x0 }, - { 0x290207, 0x0 }, - { 0x90208, 0x0 }, - { 0x190208, 0x0 }, - { 0x290208, 0x0 }, - { 0x10062, 0x0 }, - { 0x10162, 0x0 }, - { 0x10262, 0x0 }, - { 0x10362, 0x0 }, - { 0x10462, 0x0 }, - { 0x10562, 0x0 }, - { 0x10662, 0x0 }, - { 0x10762, 0x0 }, - { 0x10862, 0x0 }, - { 0x11062, 0x0 }, - { 0x11162, 0x0 }, - { 0x11262, 0x0 }, - { 0x11362, 0x0 }, - { 0x11462, 0x0 }, - { 0x11562, 0x0 }, - { 0x11662, 0x0 }, - { 0x11762, 0x0 }, - { 0x11862, 0x0 }, - { 0x12062, 0x0 }, - { 0x12162, 0x0 }, - { 0x12262, 0x0 }, - { 0x12362, 0x0 }, - { 0x12462, 0x0 }, - { 0x12562, 0x0 }, - { 0x12662, 0x0 }, - { 0x12762, 0x0 }, - { 0x12862, 0x0 }, - { 0x13062, 0x0 }, - { 0x13162, 0x0 }, - { 0x13262, 0x0 }, - { 0x13362, 0x0 }, - { 0x13462, 0x0 }, - { 0x13562, 0x0 }, - { 0x13662, 0x0 }, - { 0x13762, 0x0 }, - { 0x13862, 0x0 }, - { 0x20077, 0x0 }, - { 0x10001, 0x0 }, - { 0x11001, 0x0 }, - { 0x12001, 0x0 }, - { 0x13001, 0x0 }, - { 0x10040, 0x0 }, - { 0x10140, 0x0 }, - { 0x10240, 0x0 }, - { 0x10340, 0x0 }, - { 0x10440, 0x0 }, - { 0x10540, 0x0 }, - { 0x10640, 0x0 }, - { 0x10740, 0x0 }, - { 0x10840, 0x0 }, - { 0x10030, 0x0 }, - { 0x10130, 0x0 }, - { 0x10230, 0x0 }, - { 0x10330, 0x0 }, - { 0x10430, 0x0 }, - { 0x10530, 0x0 }, - { 0x10630, 0x0 }, - { 0x10730, 0x0 }, - { 0x10830, 0x0 }, - { 0x11040, 0x0 }, - { 0x11140, 0x0 }, - { 0x11240, 0x0 }, - { 0x11340, 0x0 }, - { 0x11440, 0x0 }, - { 0x11540, 0x0 }, - { 0x11640, 0x0 }, - { 0x11740, 0x0 }, - { 0x11840, 0x0 }, - { 0x11030, 0x0 }, - { 0x11130, 0x0 }, - { 0x11230, 0x0 }, - { 0x11330, 0x0 }, - { 0x11430, 0x0 }, - { 0x11530, 0x0 }, - { 0x11630, 0x0 }, - { 0x11730, 0x0 }, - { 0x11830, 0x0 }, - { 0x12040, 0x0 }, - { 0x12140, 0x0 }, - { 0x12240, 0x0 }, - { 0x12340, 0x0 }, - { 0x12440, 0x0 }, - { 0x12540, 0x0 }, - { 0x12640, 0x0 }, - { 0x12740, 0x0 }, - { 0x12840, 0x0 }, - { 0x12030, 0x0 }, - { 0x12130, 0x0 }, - { 0x12230, 0x0 }, - { 0x12330, 0x0 }, - { 0x12430, 0x0 }, - { 0x12530, 0x0 }, - { 0x12630, 0x0 }, - { 0x12730, 0x0 }, - { 0x12830, 0x0 }, - { 0x13040, 0x0 }, - { 0x13140, 0x0 }, - { 0x13240, 0x0 }, - { 0x13340, 0x0 }, - { 0x13440, 0x0 }, - { 0x13540, 0x0 }, - { 0x13640, 0x0 }, - { 0x13740, 0x0 }, - { 0x13840, 0x0 }, - { 0x13030, 0x0 }, - { 0x13130, 0x0 }, - { 0x13230, 0x0 }, - { 0x13330, 0x0 }, - { 0x13430, 0x0 }, - { 0x13530, 0x0 }, - { 0x13630, 0x0 }, - { 0x13730, 0x0 }, - { 0x13830, 0x0 }, -}; -/* P0 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp0_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, - { 0x54008, 0x131f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x54012, 0x110 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, - { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P1 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp1_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x101 }, - { 0x54003, 0x190 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x54012, 0x110 }, - { 0x54019, 0x84 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0x8400 }, - { 0x54033, 0x3100 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0x3100 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P2 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp2_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x102 }, - { 0x54003, 0x64 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x54012, 0x110 }, - { 0x54019, 0x84 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0x8400 }, - { 0x54033, 0x3100 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0x3100 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P0 2D message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0xbb8 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, - { 0x54008, 0x61 }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54010, 0x1f7f }, - { 0x54012, 0x110 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x1 }, - { 0x54032, 0xd400 }, - { 0x54033, 0x312d }, - { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, - { 0x54038, 0xd400 }, - { 0x54039, 0x312d }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* DRAM PHY init engine image */ -struct dram_cfg_param ddr_phy_pie[] = { - { 0xd0000, 0x0 }, - { 0x90000, 0x10 }, - { 0x90001, 0x400 }, - { 0x90002, 0x10e }, - { 0x90003, 0x0 }, - { 0x90004, 0x0 }, - { 0x90005, 0x8 }, - { 0x90029, 0xb }, - { 0x9002a, 0x480 }, - { 0x9002b, 0x109 }, - { 0x9002c, 0x8 }, - { 0x9002d, 0x448 }, - { 0x9002e, 0x139 }, - { 0x9002f, 0x8 }, - { 0x90030, 0x478 }, - { 0x90031, 0x109 }, - { 0x90032, 0x0 }, - { 0x90033, 0xe8 }, - { 0x90034, 0x109 }, - { 0x90035, 0x2 }, - { 0x90036, 0x10 }, - { 0x90037, 0x139 }, - { 0x90038, 0xf }, - { 0x90039, 0x7c0 }, - { 0x9003a, 0x139 }, - { 0x9003b, 0x44 }, - { 0x9003c, 0x630 }, - { 0x9003d, 0x159 }, - { 0x9003e, 0x14f }, - { 0x9003f, 0x630 }, - { 0x90040, 0x159 }, - { 0x90041, 0x47 }, - { 0x90042, 0x630 }, - { 0x90043, 0x149 }, - { 0x90044, 0x4f }, - { 0x90045, 0x630 }, - { 0x90046, 0x179 }, - { 0x90047, 0x8 }, - { 0x90048, 0xe0 }, - { 0x90049, 0x109 }, - { 0x9004a, 0x0 }, - { 0x9004b, 0x7c8 }, - { 0x9004c, 0x109 }, - { 0x9004d, 0x0 }, - { 0x9004e, 0x1 }, - { 0x9004f, 0x8 }, - { 0x90050, 0x0 }, - { 0x90051, 0x45a }, - { 0x90052, 0x9 }, - { 0x90053, 0x0 }, - { 0x90054, 0x448 }, - { 0x90055, 0x109 }, - { 0x90056, 0x40 }, - { 0x90057, 0x630 }, - { 0x90058, 0x179 }, - { 0x90059, 0x1 }, - { 0x9005a, 0x618 }, - { 0x9005b, 0x109 }, - { 0x9005c, 0x40c0 }, - { 0x9005d, 0x630 }, - { 0x9005e, 0x149 }, - { 0x9005f, 0x8 }, - { 0x90060, 0x4 }, - { 0x90061, 0x48 }, - { 0x90062, 0x4040 }, - { 0x90063, 0x630 }, - { 0x90064, 0x149 }, - { 0x90065, 0x0 }, - { 0x90066, 0x4 }, - { 0x90067, 0x48 }, - { 0x90068, 0x40 }, - { 0x90069, 0x630 }, - { 0x9006a, 0x149 }, - { 0x9006b, 0x10 }, - { 0x9006c, 0x4 }, - { 0x9006d, 0x18 }, - { 0x9006e, 0x0 }, - { 0x9006f, 0x4 }, - { 0x90070, 0x78 }, - { 0x90071, 0x549 }, - { 0x90072, 0x630 }, - { 0x90073, 0x159 }, - { 0x90074, 0xd49 }, - { 0x90075, 0x630 }, - { 0x90076, 0x159 }, - { 0x90077, 0x94a }, - { 0x90078, 0x630 }, - { 0x90079, 0x159 }, - { 0x9007a, 0x441 }, - { 0x9007b, 0x630 }, - { 0x9007c, 0x149 }, - { 0x9007d, 0x42 }, - { 0x9007e, 0x630 }, - { 0x9007f, 0x149 }, - { 0x90080, 0x1 }, - { 0x90081, 0x630 }, - { 0x90082, 0x149 }, - { 0x90083, 0x0 }, - { 0x90084, 0xe0 }, - { 0x90085, 0x109 }, - { 0x90086, 0xa }, - { 0x90087, 0x10 }, - { 0x90088, 0x109 }, - { 0x90089, 0x9 }, - { 0x9008a, 0x3c0 }, - { 0x9008b, 0x149 }, - { 0x9008c, 0x9 }, - { 0x9008d, 0x3c0 }, - { 0x9008e, 0x159 }, - { 0x9008f, 0x18 }, - { 0x90090, 0x10 }, - { 0x90091, 0x109 }, - { 0x90092, 0x0 }, - { 0x90093, 0x3c0 }, - { 0x90094, 0x109 }, - { 0x90095, 0x18 }, - { 0x90096, 0x4 }, - { 0x90097, 0x48 }, - { 0x90098, 0x18 }, - { 0x90099, 0x4 }, - { 0x9009a, 0x58 }, - { 0x9009b, 0xa }, - { 0x9009c, 0x10 }, - { 0x9009d, 0x109 }, - { 0x9009e, 0x2 }, - { 0x9009f, 0x10 }, - { 0x900a0, 0x109 }, - { 0x900a1, 0x5 }, - { 0x900a2, 0x7c0 }, - { 0x900a3, 0x109 }, - { 0x900a4, 0x10 }, - { 0x900a5, 0x10 }, - { 0x900a6, 0x109 }, - { 0x40000, 0x811 }, - { 0x40020, 0x880 }, - { 0x40040, 0x0 }, - { 0x40060, 0x0 }, - { 0x40001, 0x4008 }, - { 0x40021, 0x83 }, - { 0x40041, 0x4f }, - { 0x40061, 0x0 }, - { 0x40002, 0x4040 }, - { 0x40022, 0x83 }, - { 0x40042, 0x51 }, - { 0x40062, 0x0 }, - { 0x40003, 0x811 }, - { 0x40023, 0x880 }, - { 0x40043, 0x0 }, - { 0x40063, 0x0 }, - { 0x40004, 0x720 }, - { 0x40024, 0xf }, - { 0x40044, 0x1740 }, - { 0x40064, 0x0 }, - { 0x40005, 0x16 }, - { 0x40025, 0x83 }, - { 0x40045, 0x4b }, - { 0x40065, 0x0 }, - { 0x40006, 0x716 }, - { 0x40026, 0xf }, - { 0x40046, 0x2001 }, - { 0x40066, 0x0 }, - { 0x40007, 0x716 }, - { 0x40027, 0xf }, - { 0x40047, 0x2800 }, - { 0x40067, 0x0 }, - { 0x40008, 0x716 }, - { 0x40028, 0xf }, - { 0x40048, 0xf00 }, - { 0x40068, 0x0 }, - { 0x40009, 0x720 }, - { 0x40029, 0xf }, - { 0x40049, 0x1400 }, - { 0x40069, 0x0 }, - { 0x4000a, 0xe08 }, - { 0x4002a, 0xc15 }, - { 0x4004a, 0x0 }, - { 0x4006a, 0x0 }, - { 0x4000b, 0x623 }, - { 0x4002b, 0x15 }, - { 0x4004b, 0x0 }, - { 0x4006b, 0x0 }, - { 0x4000c, 0x4028 }, - { 0x4002c, 0x80 }, - { 0x4004c, 0x0 }, - { 0x4006c, 0x0 }, - { 0x4000d, 0xe08 }, - { 0x4002d, 0xc1a }, - { 0x4004d, 0x0 }, - { 0x4006d, 0x0 }, - { 0x4000e, 0x623 }, - { 0x4002e, 0x1a }, - { 0x4004e, 0x0 }, - { 0x4006e, 0x0 }, - { 0x4000f, 0x4040 }, - { 0x4002f, 0x80 }, - { 0x4004f, 0x0 }, - { 0x4006f, 0x0 }, - { 0x40010, 0x2604 }, - { 0x40030, 0x15 }, - { 0x40050, 0x0 }, - { 0x40070, 0x0 }, - { 0x40011, 0x708 }, - { 0x40031, 0x5 }, - { 0x40051, 0x0 }, - { 0x40071, 0x2002 }, - { 0x40012, 0x8 }, - { 0x40032, 0x80 }, - { 0x40052, 0x0 }, - { 0x40072, 0x0 }, - { 0x40013, 0x2604 }, - { 0x40033, 0x1a }, - { 0x40053, 0x0 }, - { 0x40073, 0x0 }, - { 0x40014, 0x708 }, - { 0x40034, 0xa }, - { 0x40054, 0x0 }, - { 0x40074, 0x2002 }, - { 0x40015, 0x4040 }, - { 0x40035, 0x80 }, - { 0x40055, 0x0 }, - { 0x40075, 0x0 }, - { 0x40016, 0x60a }, - { 0x40036, 0x15 }, - { 0x40056, 0x1200 }, - { 0x40076, 0x0 }, - { 0x40017, 0x61a }, - { 0x40037, 0x15 }, - { 0x40057, 0x1300 }, - { 0x40077, 0x0 }, - { 0x40018, 0x60a }, - { 0x40038, 0x1a }, - { 0x40058, 0x1200 }, - { 0x40078, 0x0 }, - { 0x40019, 0x642 }, - { 0x40039, 0x1a }, - { 0x40059, 0x1300 }, - { 0x40079, 0x0 }, - { 0x4001a, 0x4808 }, - { 0x4003a, 0x880 }, - { 0x4005a, 0x0 }, - { 0x4007a, 0x0 }, - { 0x900a7, 0x0 }, - { 0x900a8, 0x790 }, - { 0x900a9, 0x11a }, - { 0x900aa, 0x8 }, - { 0x900ab, 0x7aa }, - { 0x900ac, 0x2a }, - { 0x900ad, 0x10 }, - { 0x900ae, 0x7b2 }, - { 0x900af, 0x2a }, - { 0x900b0, 0x0 }, - { 0x900b1, 0x7c8 }, - { 0x900b2, 0x109 }, - { 0x900b3, 0x10 }, - { 0x900b4, 0x2a8 }, - { 0x900b5, 0x129 }, - { 0x900b6, 0x8 }, - { 0x900b7, 0x370 }, - { 0x900b8, 0x129 }, - { 0x900b9, 0xa }, - { 0x900ba, 0x3c8 }, - { 0x900bb, 0x1a9 }, - { 0x900bc, 0xc }, - { 0x900bd, 0x408 }, - { 0x900be, 0x199 }, - { 0x900bf, 0x14 }, - { 0x900c0, 0x790 }, - { 0x900c1, 0x11a }, - { 0x900c2, 0x8 }, - { 0x900c3, 0x4 }, - { 0x900c4, 0x18 }, - { 0x900c5, 0xe }, - { 0x900c6, 0x408 }, - { 0x900c7, 0x199 }, - { 0x900c8, 0x8 }, - { 0x900c9, 0x8568 }, - { 0x900ca, 0x108 }, - { 0x900cb, 0x18 }, - { 0x900cc, 0x790 }, - { 0x900cd, 0x16a }, - { 0x900ce, 0x8 }, - { 0x900cf, 0x1d8 }, - { 0x900d0, 0x169 }, - { 0x900d1, 0x10 }, - { 0x900d2, 0x8558 }, - { 0x900d3, 0x168 }, - { 0x900d4, 0x70 }, - { 0x900d5, 0x788 }, - { 0x900d6, 0x16a }, - { 0x900d7, 0x1ff8 }, - { 0x900d8, 0x85a8 }, - { 0x900d9, 0x1e8 }, - { 0x900da, 0x50 }, - { 0x900db, 0x798 }, - { 0x900dc, 0x16a }, - { 0x900dd, 0x60 }, - { 0x900de, 0x7a0 }, - { 0x900df, 0x16a }, - { 0x900e0, 0x8 }, - { 0x900e1, 0x8310 }, - { 0x900e2, 0x168 }, - { 0x900e3, 0x8 }, - { 0x900e4, 0xa310 }, - { 0x900e5, 0x168 }, - { 0x900e6, 0xa }, - { 0x900e7, 0x408 }, - { 0x900e8, 0x169 }, - { 0x900e9, 0x6e }, - { 0x900ea, 0x0 }, - { 0x900eb, 0x68 }, - { 0x900ec, 0x0 }, - { 0x900ed, 0x408 }, - { 0x900ee, 0x169 }, - { 0x900ef, 0x0 }, - { 0x900f0, 0x8310 }, - { 0x900f1, 0x168 }, - { 0x900f2, 0x0 }, - { 0x900f3, 0xa310 }, - { 0x900f4, 0x168 }, - { 0x900f5, 0x1ff8 }, - { 0x900f6, 0x85a8 }, - { 0x900f7, 0x1e8 }, - { 0x900f8, 0x68 }, - { 0x900f9, 0x798 }, - { 0x900fa, 0x16a }, - { 0x900fb, 0x78 }, - { 0x900fc, 0x7a0 }, - { 0x900fd, 0x16a }, - { 0x900fe, 0x68 }, - { 0x900ff, 0x790 }, - { 0x90100, 0x16a }, - { 0x90101, 0x8 }, - { 0x90102, 0x8b10 }, - { 0x90103, 0x168 }, - { 0x90104, 0x8 }, - { 0x90105, 0xab10 }, - { 0x90106, 0x168 }, - { 0x90107, 0xa }, - { 0x90108, 0x408 }, - { 0x90109, 0x169 }, - { 0x9010a, 0x58 }, - { 0x9010b, 0x0 }, - { 0x9010c, 0x68 }, - { 0x9010d, 0x0 }, - { 0x9010e, 0x408 }, - { 0x9010f, 0x169 }, - { 0x90110, 0x0 }, - { 0x90111, 0x8b10 }, - { 0x90112, 0x168 }, - { 0x90113, 0x0 }, - { 0x90114, 0xab10 }, - { 0x90115, 0x168 }, - { 0x90116, 0x0 }, - { 0x90117, 0x1d8 }, - { 0x90118, 0x169 }, - { 0x90119, 0x80 }, - { 0x9011a, 0x790 }, - { 0x9011b, 0x16a }, - { 0x9011c, 0x18 }, - { 0x9011d, 0x7aa }, - { 0x9011e, 0x6a }, - { 0x9011f, 0xa }, - { 0x90120, 0x0 }, - { 0x90121, 0x1e9 }, - { 0x90122, 0x8 }, - { 0x90123, 0x8080 }, - { 0x90124, 0x108 }, - { 0x90125, 0xf }, - { 0x90126, 0x408 }, - { 0x90127, 0x169 }, - { 0x90128, 0xc }, - { 0x90129, 0x0 }, - { 0x9012a, 0x68 }, - { 0x9012b, 0x9 }, - { 0x9012c, 0x0 }, - { 0x9012d, 0x1a9 }, - { 0x9012e, 0x0 }, - { 0x9012f, 0x408 }, - { 0x90130, 0x169 }, - { 0x90131, 0x0 }, - { 0x90132, 0x8080 }, - { 0x90133, 0x108 }, - { 0x90134, 0x8 }, - { 0x90135, 0x7aa }, - { 0x90136, 0x6a }, - { 0x90137, 0x0 }, - { 0x90138, 0x8568 }, - { 0x90139, 0x108 }, - { 0x9013a, 0xb7 }, - { 0x9013b, 0x790 }, - { 0x9013c, 0x16a }, - { 0x9013d, 0x1f }, - { 0x9013e, 0x0 }, - { 0x9013f, 0x68 }, - { 0x90140, 0x8 }, - { 0x90141, 0x8558 }, - { 0x90142, 0x168 }, - { 0x90143, 0xf }, - { 0x90144, 0x408 }, - { 0x90145, 0x169 }, - { 0x90146, 0xc }, - { 0x90147, 0x0 }, - { 0x90148, 0x68 }, - { 0x90149, 0x0 }, - { 0x9014a, 0x408 }, - { 0x9014b, 0x169 }, - { 0x9014c, 0x0 }, - { 0x9014d, 0x8558 }, - { 0x9014e, 0x168 }, - { 0x9014f, 0x8 }, - { 0x90150, 0x3c8 }, - { 0x90151, 0x1a9 }, - { 0x90152, 0x3 }, - { 0x90153, 0x370 }, - { 0x90154, 0x129 }, - { 0x90155, 0x20 }, - { 0x90156, 0x2aa }, - { 0x90157, 0x9 }, - { 0x90158, 0x0 }, - { 0x90159, 0x400 }, - { 0x9015a, 0x10e }, - { 0x9015b, 0x8 }, - { 0x9015c, 0xe8 }, - { 0x9015d, 0x109 }, - { 0x9015e, 0x0 }, - { 0x9015f, 0x8140 }, - { 0x90160, 0x10c }, - { 0x90161, 0x10 }, - { 0x90162, 0x8138 }, - { 0x90163, 0x10c }, - { 0x90164, 0x8 }, - { 0x90165, 0x7c8 }, - { 0x90166, 0x101 }, - { 0x90167, 0x8 }, - { 0x90168, 0x0 }, - { 0x90169, 0x8 }, - { 0x9016a, 0x8 }, - { 0x9016b, 0x448 }, - { 0x9016c, 0x109 }, - { 0x9016d, 0xf }, - { 0x9016e, 0x7c0 }, - { 0x9016f, 0x109 }, - { 0x90170, 0x0 }, - { 0x90171, 0xe8 }, - { 0x90172, 0x109 }, - { 0x90173, 0x47 }, - { 0x90174, 0x630 }, - { 0x90175, 0x109 }, - { 0x90176, 0x8 }, - { 0x90177, 0x618 }, - { 0x90178, 0x109 }, - { 0x90179, 0x8 }, - { 0x9017a, 0xe0 }, - { 0x9017b, 0x109 }, - { 0x9017c, 0x0 }, - { 0x9017d, 0x7c8 }, - { 0x9017e, 0x109 }, - { 0x9017f, 0x8 }, - { 0x90180, 0x8140 }, - { 0x90181, 0x10c }, - { 0x90182, 0x0 }, - { 0x90183, 0x1 }, - { 0x90184, 0x8 }, - { 0x90185, 0x8 }, - { 0x90186, 0x4 }, - { 0x90187, 0x8 }, - { 0x90188, 0x8 }, - { 0x90189, 0x7c8 }, - { 0x9018a, 0x101 }, - { 0x90006, 0x0 }, - { 0x90007, 0x0 }, - { 0x90008, 0x8 }, - { 0x90009, 0x0 }, - { 0x9000a, 0x0 }, - { 0x9000b, 0x0 }, - { 0xd00e7, 0x400 }, - { 0x90017, 0x0 }, - { 0x9001f, 0x2a }, - { 0x90026, 0x6a }, - { 0x400d0, 0x0 }, - { 0x400d1, 0x101 }, - { 0x400d2, 0x105 }, - { 0x400d3, 0x107 }, - { 0x400d4, 0x10f }, - { 0x400d5, 0x202 }, - { 0x400d6, 0x20a }, - { 0x400d7, 0x20b }, - { 0x2003a, 0x2 }, - { 0x2000b, 0x5d }, - { 0x2000c, 0xbb }, - { 0x2000d, 0x753 }, - { 0x2000e, 0x2c }, - { 0x12000b, 0xc }, - { 0x12000c, 0x19 }, - { 0x12000d, 0xfa }, - { 0x12000e, 0x10 }, - { 0x22000b, 0x3 }, - { 0x22000c, 0x6 }, - { 0x22000d, 0x3e }, - { 0x22000e, 0x10 }, - { 0x9000c, 0x0 }, - { 0x9000d, 0x173 }, - { 0x9000e, 0x60 }, - { 0x9000f, 0x6110 }, - { 0x90010, 0x2152 }, - { 0x90011, 0xdfbd }, - { 0x90012, 0x60 }, - { 0x90013, 0x6152 }, - { 0x20010, 0x5a }, - { 0x20011, 0x3 }, - { 0x120010, 0x5a }, - { 0x120011, 0x3 }, - { 0x220010, 0x5a }, - { 0x220011, 0x3 }, - { 0x40080, 0xe0 }, - { 0x40081, 0x12 }, - { 0x40082, 0xe0 }, - { 0x40083, 0x12 }, - { 0x40084, 0xe0 }, - { 0x40085, 0x12 }, - { 0x140080, 0xe0 }, - { 0x140081, 0x12 }, - { 0x140082, 0xe0 }, - { 0x140083, 0x12 }, - { 0x140084, 0xe0 }, - { 0x140085, 0x12 }, - { 0x240080, 0xe0 }, - { 0x240081, 0x12 }, - { 0x240082, 0xe0 }, - { 0x240083, 0x12 }, - { 0x240084, 0xe0 }, - { 0x240085, 0x12 }, - { 0x400fd, 0xf }, - { 0x10011, 0x1 }, - { 0x10012, 0x1 }, - { 0x10013, 0x180 }, - { 0x10018, 0x1 }, - { 0x10002, 0x6209 }, - { 0x100b2, 0x1 }, - { 0x101b4, 0x1 }, - { 0x102b4, 0x1 }, - { 0x103b4, 0x1 }, - { 0x104b4, 0x1 }, - { 0x105b4, 0x1 }, - { 0x106b4, 0x1 }, - { 0x107b4, 0x1 }, - { 0x108b4, 0x1 }, - { 0x11011, 0x1 }, - { 0x11012, 0x1 }, - { 0x11013, 0x180 }, - { 0x11018, 0x1 }, - { 0x11002, 0x6209 }, - { 0x110b2, 0x1 }, - { 0x111b4, 0x1 }, - { 0x112b4, 0x1 }, - { 0x113b4, 0x1 }, - { 0x114b4, 0x1 }, - { 0x115b4, 0x1 }, - { 0x116b4, 0x1 }, - { 0x117b4, 0x1 }, - { 0x118b4, 0x1 }, - { 0x12011, 0x1 }, - { 0x12012, 0x1 }, - { 0x12013, 0x180 }, - { 0x12018, 0x1 }, - { 0x12002, 0x6209 }, - { 0x120b2, 0x1 }, - { 0x121b4, 0x1 }, - { 0x122b4, 0x1 }, - { 0x123b4, 0x1 }, - { 0x124b4, 0x1 }, - { 0x125b4, 0x1 }, - { 0x126b4, 0x1 }, - { 0x127b4, 0x1 }, - { 0x128b4, 0x1 }, - { 0x13011, 0x1 }, - { 0x13012, 0x1 }, - { 0x13013, 0x180 }, - { 0x13018, 0x1 }, - { 0x13002, 0x6209 }, - { 0x130b2, 0x1 }, - { 0x131b4, 0x1 }, - { 0x132b4, 0x1 }, - { 0x133b4, 0x1 }, - { 0x134b4, 0x1 }, - { 0x135b4, 0x1 }, - { 0x136b4, 0x1 }, - { 0x137b4, 0x1 }, - { 0x138b4, 0x1 }, - { 0x2003a, 0x2 }, - { 0xc0080, 0x2 }, - { 0xd0000, 0x1 } -}; - -struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 3000mts 1D */ - .drate = 3000, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 400mts 1D */ - .drate = 400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 100mts 1D */ - .drate = 100, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 3000mts 2D */ - .drate = 3000, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3000, 400, 100, }, -}; diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c deleted file mode 100644 index cd251d274ff..00000000000 --- a/board/freescale/imx8mm_evk/spl.c +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019, 2021 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int spl_board_boot_device(enum boot_device boot_dev_spl) -{ - switch (boot_dev_spl) { - case USB_BOOT: - return BOOT_DEVICE_BOARD; - case SD2_BOOT: - case MMC2_BOOT: - return BOOT_DEVICE_MMC1; - case SD3_BOOT: - case MMC3_BOOT: - return BOOT_DEVICE_MMC2; - case QSPI_BOOT: - return BOOT_DEVICE_NOR; - default: - return BOOT_DEVICE_NONE; - } -} - -static void spl_dram_init(void) -{ - ddr_init(&dram_timing); -} - -void spl_board_init(void) -{ - arch_misc_init(); -} - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif - -static int power_init_board(void) -{ - struct udevice *dev; - int ret; - - ret = pmic_get("pca9450@25", &dev); - if (ret == -ENODEV) { - puts("No pmic\n"); - return 0; - } - if (ret != 0) - return ret; - - /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); - - /* Buck 1 DVS control through PMIC_STBY_REQ */ - pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); - - /* Set DVS1 to 0.8v for suspend */ - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10); - - /* increase VDD_DRAM to 0.95v for 3Ghz DDR */ - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C); - - /* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */ - pmic_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a); - - /* set VDD_SNVS_0V8 from default 0.85V */ - pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); - - return 0; -} - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - - arch_cpu_init(); - - init_uart_clk(1); - - timer_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - ret = uclass_get_device_by_name(UCLASS_CLK, - "clock-controller@30380000", - &dev); - if (ret < 0) { - printf("Failed to find clock node. Check device tree\n"); - hang(); - } - - preloader_console_init(); - - enable_tzc380(); - - power_init_board(); - - /* DDR initialization */ - spl_dram_init(); - - board_init_r(NULL, 0); -} diff --git a/board/freescale/imx8mn_evk/Kconfig b/board/freescale/imx8mn_evk/Kconfig deleted file mode 100644 index a148a9b998c..00000000000 --- a/board/freescale/imx8mn_evk/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -if TARGET_IMX8MN_EVK || TARGET_IMX8MN_DDR4_EVK - -config SYS_BOARD - default "imx8mn_evk" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "imx8mn_evk" - -config IMX8MN_LOW_DRIVE_MODE - bool "Enable the low drive mode of iMX8MN on EVK board" - -config IMX_CONFIG - default "board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg" - -endif diff --git a/board/freescale/imx8mn_evk/MAINTAINERS b/board/freescale/imx8mn_evk/MAINTAINERS deleted file mode 100644 index 6d110ccf22b..00000000000 --- a/board/freescale/imx8mn_evk/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -i.MX8MN EVK BOARD -M: Peng Fan -S: Maintained -F: board/freescale/imx8mn_evk/ -F: include/configs/imx8mn_evk.h -F: configs/imx8mn_ddr4_evk_defconfig -F: configs/imx8mn_evk_defconfig diff --git a/board/freescale/imx8mn_evk/Makefile b/board/freescale/imx8mn_evk/Makefile deleted file mode 100644 index 5ef666a36dd..00000000000 --- a/board/freescale/imx8mn_evk/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright 2018 NXP -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += imx8mn_evk.o - -ifdef CONFIG_XPL_BUILD -obj-y += spl.o -ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE -obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_ld.o -obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing_ld.o -else -obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o -obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o -endif -endif diff --git a/board/freescale/imx8mn_evk/ddr4_timing.c b/board/freescale/imx8mn_evk/ddr4_timing.c deleted file mode 100644 index ce39c9e2bcf..00000000000 --- a/board/freescale/imx8mn_evk/ddr4_timing.c +++ /dev/null @@ -1,1053 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 NXP - * - * Generated code from MX8M_DDR_tool - * Align with uboot version: - * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga - */ - -#include -#include - -struct dram_cfg_param ddr_ddrc_cfg[] = { - /** Initialize DDRC registers **/ - { 0x3d400000, 0x81040010 }, - { 0x3d400030, 0x20 }, - { 0x3d400034, 0x221306 }, - { 0x3d400050, 0x210070 }, - { 0x3d400054, 0x10008 }, - { 0x3d400060, 0x0 }, - { 0x3d400064, 0x92014a }, - { 0x3d4000c0, 0x0 }, - { 0x3d4000c4, 0x1000 }, - { 0x3d4000d0, 0xc0030126 }, - { 0x3d4000d4, 0x770000 }, - { 0x3d4000dc, 0x8340105 }, - { 0x3d4000e0, 0x180200 }, - { 0x3d4000e4, 0x110000 }, - { 0x3d4000e8, 0x2000600 }, - { 0x3d4000ec, 0x810 }, - { 0x3d4000f0, 0x20 }, - { 0x3d4000f4, 0xec7 }, - { 0x3d400100, 0x11122914 }, - { 0x3d400104, 0x4051c }, - { 0x3d400108, 0x608050d }, - { 0x3d40010c, 0x400c }, - { 0x3d400110, 0x8030409 }, - { 0x3d400114, 0x6060403 }, - { 0x3d40011c, 0x606 }, - { 0x3d400120, 0x7070d0c }, - { 0x3d400124, 0x2040a }, - { 0x3d40012c, 0x1809010e }, - { 0x3d400130, 0x8 }, - { 0x3d40013c, 0x0 }, - { 0x3d400180, 0x1000040 }, - { 0x3d400184, 0x493e }, - { 0x3d400190, 0x38b8207 }, - { 0x3d400194, 0x2020303 }, - { 0x3d400198, 0x7f04011 }, - { 0x3d40019c, 0xb0 }, - { 0x3d4001a0, 0xe0400018 }, - { 0x3d4001a4, 0x48005a }, - { 0x3d4001a8, 0x80000000 }, - { 0x3d4001b0, 0x1 }, - { 0x3d4001b4, 0xb07 }, - { 0x3d4001b8, 0x4 }, - { 0x3d4001c0, 0x1 }, - { 0x3d4001c4, 0x0 }, - { 0x3d400200, 0x3f1f }, - { 0x3d400204, 0x3f0909 }, - { 0x3d400208, 0x700 }, - { 0x3d40020c, 0x0 }, - { 0x3d400210, 0x1f1f }, - { 0x3d400214, 0x7070707 }, - { 0x3d400218, 0x7070707 }, - { 0x3d40021c, 0xf07 }, - { 0x3d400220, 0x3f01 }, - { 0x3d400240, 0x6000610 }, - { 0x3d400244, 0x1323 }, - { 0x3d400400, 0x100 }, - - /* performance setting */ - { 0x3d400250, 0x00001f05 }, - { 0x3d400254, 0x1f }, - { 0x3d400264, 0x900003ff }, - { 0x3d40026c, 0x200003ff }, - { 0x3d400494, 0x01000e00 }, - { 0x3d400498, 0x03ff0000 }, - { 0x3d40049c, 0x01000e00 }, - { 0x3d4004a0, 0x03ff0000 }, - - { 0x3d402050, 0x210070 }, - { 0x3d402064, 0x400093 }, - { 0x3d4020dc, 0x105 }, - { 0x3d4020e0, 0x0 }, - { 0x3d4020e8, 0x2000600 }, - { 0x3d4020ec, 0x10 }, - { 0x3d402100, 0xb081209 }, - { 0x3d402104, 0x2020d }, - { 0x3d402108, 0x5050309 }, - { 0x3d40210c, 0x400c }, - { 0x3d402110, 0x5030206 }, - { 0x3d402114, 0x3030202 }, - { 0x3d40211c, 0x303 }, - { 0x3d402120, 0x4040d06 }, - { 0x3d402124, 0x20208 }, - { 0x3d40212c, 0x1205010e }, - { 0x3d402130, 0x8 }, - { 0x3d40213c, 0x0 }, - { 0x3d402180, 0x1000040 }, - { 0x3d402190, 0x3848204 }, - { 0x3d402194, 0x2020303 }, - { 0x3d4021b4, 0x404 }, - { 0x3d4021b8, 0x4 }, - { 0x3d402240, 0x6000600 }, - { 0x3d4020f4, 0xec7 }, -}; - -/* PHY Initialize Configuration */ -struct dram_cfg_param ddr_ddrphy_cfg[] = { - { 0x1005f, 0x2fd }, - { 0x1015f, 0x2fd }, - { 0x1105f, 0x2fd }, - { 0x1115f, 0x2fd }, - { 0x11005f, 0x2fd }, - { 0x11015f, 0x2fd }, - { 0x11105f, 0x2fd }, - { 0x11115f, 0x2fd }, - { 0x55, 0x355 }, - { 0x1055, 0x355 }, - { 0x2055, 0x355 }, - { 0x3055, 0x355 }, - { 0x4055, 0x55 }, - { 0x5055, 0x55 }, - { 0x6055, 0x355 }, - { 0x7055, 0x355 }, - { 0x8055, 0x355 }, - { 0x9055, 0x355 }, - { 0x200c5, 0xa }, - { 0x1200c5, 0x6 }, - { 0x2002e, 0x2 }, - { 0x12002e, 0x1 }, - { 0x20024, 0x8 }, - { 0x2003a, 0x2 }, - { 0x120024, 0x8 }, - { 0x2003a, 0x2 }, - { 0x20056, 0x6 }, - { 0x120056, 0xa }, - { 0x1004d, 0x1a }, - { 0x1014d, 0x1a }, - { 0x1104d, 0x1a }, - { 0x1114d, 0x1a }, - { 0x11004d, 0x1a }, - { 0x11014d, 0x1a }, - { 0x11104d, 0x1a }, - { 0x11114d, 0x1a }, - { 0x10049, 0xe38 }, - { 0x10149, 0xe38 }, - { 0x11049, 0xe38 }, - { 0x11149, 0xe38 }, - { 0x110049, 0xe38 }, - { 0x110149, 0xe38 }, - { 0x111049, 0xe38 }, - { 0x111149, 0xe38 }, - { 0x43, 0x63 }, - { 0x1043, 0x63 }, - { 0x2043, 0x63 }, - { 0x3043, 0x63 }, - { 0x4043, 0x63 }, - { 0x5043, 0x63 }, - { 0x6043, 0x63 }, - { 0x7043, 0x63 }, - { 0x8043, 0x63 }, - { 0x9043, 0x63 }, - { 0x20018, 0x1 }, - { 0x20075, 0x2 }, - { 0x20050, 0x0 }, - { 0x20008, 0x258 }, - { 0x120008, 0x10a }, - { 0x20088, 0x9 }, - { 0x200b2, 0x268 }, - { 0x10043, 0x5b1 }, - { 0x10143, 0x5b1 }, - { 0x11043, 0x5b1 }, - { 0x11143, 0x5b1 }, - { 0x1200b2, 0x268 }, - { 0x110043, 0x5b1 }, - { 0x110143, 0x5b1 }, - { 0x111043, 0x5b1 }, - { 0x111143, 0x5b1 }, - { 0x200fa, 0x1 }, - { 0x1200fa, 0x1 }, - { 0x20019, 0x5 }, - { 0x120019, 0x5 }, - { 0x200f0, 0x5555 }, - { 0x200f1, 0x5555 }, - { 0x200f2, 0x5555 }, - { 0x200f3, 0x5555 }, - { 0x200f4, 0x5555 }, - { 0x200f5, 0x5555 }, - { 0x200f6, 0x5555 }, - { 0x200f7, 0xf000 }, - { 0x20025, 0x0 }, - { 0x2002d, 0x0 }, - { 0x12002d, 0x0 }, - { 0x2005b, 0x7529 }, - { 0x2005c, 0x0 }, - { 0x200c7, 0x21 }, - { 0x200ca, 0x24 }, - { 0x200cc, 0x1f7 }, - { 0x1200c7, 0x21 }, - { 0x1200ca, 0x24 }, - { 0x1200cc, 0x1f7 }, - { 0x2007d, 0x212 }, - { 0x12007d, 0x212 }, - { 0x2007c, 0x61 }, - { 0x12007c, 0x61 }, - { 0x1004a, 0x500 }, - { 0x1104a, 0x500 }, - { 0x2002c, 0x0 }, -}; - -/* ddr phy trained csr */ -struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - {0x0200b2, 0x0}, - {0x1200b2, 0x0}, - {0x2200b2, 0x0}, - {0x0200cb, 0x0}, - {0x010043, 0x0}, - {0x110043, 0x0}, - {0x210043, 0x0}, - {0x010143, 0x0}, - {0x110143, 0x0}, - {0x210143, 0x0}, - {0x011043, 0x0}, - {0x111043, 0x0}, - {0x211043, 0x0}, - {0x011143, 0x0}, - {0x111143, 0x0}, - {0x211143, 0x0}, - {0x000080, 0x0}, - {0x100080, 0x0}, - {0x200080, 0x0}, - {0x001080, 0x0}, - {0x101080, 0x0}, - {0x201080, 0x0}, - {0x002080, 0x0}, - {0x102080, 0x0}, - {0x202080, 0x0}, - {0x003080, 0x0}, - {0x103080, 0x0}, - {0x203080, 0x0}, - {0x004080, 0x0}, - {0x104080, 0x0}, - {0x204080, 0x0}, - {0x005080, 0x0}, - {0x105080, 0x0}, - {0x205080, 0x0}, - {0x006080, 0x0}, - {0x106080, 0x0}, - {0x206080, 0x0}, - {0x007080, 0x0}, - {0x107080, 0x0}, - {0x207080, 0x0}, - {0x008080, 0x0}, - {0x108080, 0x0}, - {0x208080, 0x0}, - {0x009080, 0x0}, - {0x109080, 0x0}, - {0x209080, 0x0}, - {0x010080, 0x0}, - {0x110080, 0x0}, - {0x210080, 0x0}, - {0x010180, 0x0}, - {0x110180, 0x0}, - {0x210180, 0x0}, - {0x010081, 0x0}, - {0x110081, 0x0}, - {0x210081, 0x0}, - {0x010181, 0x0}, - {0x110181, 0x0}, - {0x210181, 0x0}, - {0x010082, 0x0}, - {0x110082, 0x0}, - {0x210082, 0x0}, - {0x010182, 0x0}, - {0x110182, 0x0}, - {0x210182, 0x0}, - {0x010083, 0x0}, - {0x110083, 0x0}, - {0x210083, 0x0}, - {0x010183, 0x0}, - {0x110183, 0x0}, - {0x210183, 0x0}, - {0x011080, 0x0}, - {0x111080, 0x0}, - {0x211080, 0x0}, - {0x011180, 0x0}, - {0x111180, 0x0}, - {0x211180, 0x0}, - {0x011081, 0x0}, - {0x111081, 0x0}, - {0x211081, 0x0}, - {0x011181, 0x0}, - {0x111181, 0x0}, - {0x211181, 0x0}, - {0x011082, 0x0}, - {0x111082, 0x0}, - {0x211082, 0x0}, - {0x011182, 0x0}, - {0x111182, 0x0}, - {0x211182, 0x0}, - {0x011083, 0x0}, - {0x111083, 0x0}, - {0x211083, 0x0}, - {0x011183, 0x0}, - {0x111183, 0x0}, - {0x211183, 0x0}, - {0x0100d0, 0x0}, - {0x1100d0, 0x0}, - {0x2100d0, 0x0}, - {0x0101d0, 0x0}, - {0x1101d0, 0x0}, - {0x2101d0, 0x0}, - {0x0100d1, 0x0}, - {0x1100d1, 0x0}, - {0x2100d1, 0x0}, - {0x0101d1, 0x0}, - {0x1101d1, 0x0}, - {0x2101d1, 0x0}, - {0x0100d2, 0x0}, - {0x1100d2, 0x0}, - {0x2100d2, 0x0}, - {0x0101d2, 0x0}, - {0x1101d2, 0x0}, - {0x2101d2, 0x0}, - {0x0100d3, 0x0}, - {0x1100d3, 0x0}, - {0x2100d3, 0x0}, - {0x0101d3, 0x0}, - {0x1101d3, 0x0}, - {0x2101d3, 0x0}, - {0x0110d0, 0x0}, - {0x1110d0, 0x0}, - {0x2110d0, 0x0}, - {0x0111d0, 0x0}, - {0x1111d0, 0x0}, - {0x2111d0, 0x0}, - {0x0110d1, 0x0}, - {0x1110d1, 0x0}, - {0x2110d1, 0x0}, - {0x0111d1, 0x0}, - {0x1111d1, 0x0}, - {0x2111d1, 0x0}, - {0x0110d2, 0x0}, - {0x1110d2, 0x0}, - {0x2110d2, 0x0}, - {0x0111d2, 0x0}, - {0x1111d2, 0x0}, - {0x2111d2, 0x0}, - {0x0110d3, 0x0}, - {0x1110d3, 0x0}, - {0x2110d3, 0x0}, - {0x0111d3, 0x0}, - {0x1111d3, 0x0}, - {0x2111d3, 0x0}, - {0x010068, 0x0}, - {0x010168, 0x0}, - {0x010268, 0x0}, - {0x010368, 0x0}, - {0x010468, 0x0}, - {0x010568, 0x0}, - {0x010668, 0x0}, - {0x010768, 0x0}, - {0x010868, 0x0}, - {0x010069, 0x0}, - {0x010169, 0x0}, - {0x010269, 0x0}, - {0x010369, 0x0}, - {0x010469, 0x0}, - {0x010569, 0x0}, - {0x010669, 0x0}, - {0x010769, 0x0}, - {0x010869, 0x0}, - {0x01006a, 0x0}, - {0x01016a, 0x0}, - {0x01026a, 0x0}, - {0x01036a, 0x0}, - {0x01046a, 0x0}, - {0x01056a, 0x0}, - {0x01066a, 0x0}, - {0x01076a, 0x0}, - {0x01086a, 0x0}, - {0x01006b, 0x0}, - {0x01016b, 0x0}, - {0x01026b, 0x0}, - {0x01036b, 0x0}, - {0x01046b, 0x0}, - {0x01056b, 0x0}, - {0x01066b, 0x0}, - {0x01076b, 0x0}, - {0x01086b, 0x0}, - {0x011068, 0x0}, - {0x011168, 0x0}, - {0x011268, 0x0}, - {0x011368, 0x0}, - {0x011468, 0x0}, - {0x011568, 0x0}, - {0x011668, 0x0}, - {0x011768, 0x0}, - {0x011868, 0x0}, - {0x011069, 0x0}, - {0x011169, 0x0}, - {0x011269, 0x0}, - {0x011369, 0x0}, - {0x011469, 0x0}, - {0x011569, 0x0}, - {0x011669, 0x0}, - {0x011769, 0x0}, - {0x011869, 0x0}, - {0x01106a, 0x0}, - {0x01116a, 0x0}, - {0x01126a, 0x0}, - {0x01136a, 0x0}, - {0x01146a, 0x0}, - {0x01156a, 0x0}, - {0x01166a, 0x0}, - {0x01176a, 0x0}, - {0x01186a, 0x0}, - {0x01106b, 0x0}, - {0x01116b, 0x0}, - {0x01126b, 0x0}, - {0x01136b, 0x0}, - {0x01146b, 0x0}, - {0x01156b, 0x0}, - {0x01166b, 0x0}, - {0x01176b, 0x0}, - {0x01186b, 0x0}, - {0x01008c, 0x0}, - {0x11008c, 0x0}, - {0x21008c, 0x0}, - {0x01018c, 0x0}, - {0x11018c, 0x0}, - {0x21018c, 0x0}, - {0x01008d, 0x0}, - {0x11008d, 0x0}, - {0x21008d, 0x0}, - {0x01018d, 0x0}, - {0x11018d, 0x0}, - {0x21018d, 0x0}, - {0x01008e, 0x0}, - {0x11008e, 0x0}, - {0x21008e, 0x0}, - {0x01018e, 0x0}, - {0x11018e, 0x0}, - {0x21018e, 0x0}, - {0x01008f, 0x0}, - {0x11008f, 0x0}, - {0x21008f, 0x0}, - {0x01018f, 0x0}, - {0x11018f, 0x0}, - {0x21018f, 0x0}, - {0x01108c, 0x0}, - {0x11108c, 0x0}, - {0x21108c, 0x0}, - {0x01118c, 0x0}, - {0x11118c, 0x0}, - {0x21118c, 0x0}, - {0x01108d, 0x0}, - {0x11108d, 0x0}, - {0x21108d, 0x0}, - {0x01118d, 0x0}, - {0x11118d, 0x0}, - {0x21118d, 0x0}, - {0x01108e, 0x0}, - {0x11108e, 0x0}, - {0x21108e, 0x0}, - {0x01118e, 0x0}, - {0x11118e, 0x0}, - {0x21118e, 0x0}, - {0x01108f, 0x0}, - {0x11108f, 0x0}, - {0x21108f, 0x0}, - {0x01118f, 0x0}, - {0x11118f, 0x0}, - {0x21118f, 0x0}, - {0x0100c0, 0x0}, - {0x1100c0, 0x0}, - {0x2100c0, 0x0}, - {0x0101c0, 0x0}, - {0x1101c0, 0x0}, - {0x2101c0, 0x0}, - {0x0102c0, 0x0}, - {0x1102c0, 0x0}, - {0x2102c0, 0x0}, - {0x0103c0, 0x0}, - {0x1103c0, 0x0}, - {0x2103c0, 0x0}, - {0x0104c0, 0x0}, - {0x1104c0, 0x0}, - {0x2104c0, 0x0}, - {0x0105c0, 0x0}, - {0x1105c0, 0x0}, - {0x2105c0, 0x0}, - {0x0106c0, 0x0}, - {0x1106c0, 0x0}, - {0x2106c0, 0x0}, - {0x0107c0, 0x0}, - {0x1107c0, 0x0}, - {0x2107c0, 0x0}, - {0x0108c0, 0x0}, - {0x1108c0, 0x0}, - {0x2108c0, 0x0}, - {0x0100c1, 0x0}, - {0x1100c1, 0x0}, - {0x2100c1, 0x0}, - {0x0101c1, 0x0}, - {0x1101c1, 0x0}, - {0x2101c1, 0x0}, - {0x0102c1, 0x0}, - {0x1102c1, 0x0}, - {0x2102c1, 0x0}, - {0x0103c1, 0x0}, - {0x1103c1, 0x0}, - {0x2103c1, 0x0}, - {0x0104c1, 0x0}, - {0x1104c1, 0x0}, - {0x2104c1, 0x0}, - {0x0105c1, 0x0}, - {0x1105c1, 0x0}, - {0x2105c1, 0x0}, - {0x0106c1, 0x0}, - {0x1106c1, 0x0}, - {0x2106c1, 0x0}, - {0x0107c1, 0x0}, - {0x1107c1, 0x0}, - {0x2107c1, 0x0}, - {0x0108c1, 0x0}, - {0x1108c1, 0x0}, - {0x2108c1, 0x0}, - {0x0100c2, 0x0}, - {0x1100c2, 0x0}, - {0x2100c2, 0x0}, - {0x0101c2, 0x0}, - {0x1101c2, 0x0}, - {0x2101c2, 0x0}, - {0x0102c2, 0x0}, - {0x1102c2, 0x0}, - {0x2102c2, 0x0}, - {0x0103c2, 0x0}, - {0x1103c2, 0x0}, - {0x2103c2, 0x0}, - {0x0104c2, 0x0}, - {0x1104c2, 0x0}, - {0x2104c2, 0x0}, - {0x0105c2, 0x0}, - {0x1105c2, 0x0}, - {0x2105c2, 0x0}, - {0x0106c2, 0x0}, - {0x1106c2, 0x0}, - {0x2106c2, 0x0}, - {0x0107c2, 0x0}, - {0x1107c2, 0x0}, - {0x2107c2, 0x0}, - {0x0108c2, 0x0}, - {0x1108c2, 0x0}, - {0x2108c2, 0x0}, - {0x0100c3, 0x0}, - {0x1100c3, 0x0}, - {0x2100c3, 0x0}, - {0x0101c3, 0x0}, - {0x1101c3, 0x0}, - {0x2101c3, 0x0}, - {0x0102c3, 0x0}, - {0x1102c3, 0x0}, - {0x2102c3, 0x0}, - {0x0103c3, 0x0}, - {0x1103c3, 0x0}, - {0x2103c3, 0x0}, - {0x0104c3, 0x0}, - {0x1104c3, 0x0}, - {0x2104c3, 0x0}, - {0x0105c3, 0x0}, - {0x1105c3, 0x0}, - {0x2105c3, 0x0}, - {0x0106c3, 0x0}, - {0x1106c3, 0x0}, - {0x2106c3, 0x0}, - {0x0107c3, 0x0}, - {0x1107c3, 0x0}, - {0x2107c3, 0x0}, - {0x0108c3, 0x0}, - {0x1108c3, 0x0}, - {0x2108c3, 0x0}, - {0x0110c0, 0x0}, - {0x1110c0, 0x0}, - {0x2110c0, 0x0}, - {0x0111c0, 0x0}, - {0x1111c0, 0x0}, - {0x2111c0, 0x0}, - {0x0112c0, 0x0}, - {0x1112c0, 0x0}, - {0x2112c0, 0x0}, - {0x0113c0, 0x0}, - {0x1113c0, 0x0}, - {0x2113c0, 0x0}, - {0x0114c0, 0x0}, - {0x1114c0, 0x0}, - {0x2114c0, 0x0}, - {0x0115c0, 0x0}, - {0x1115c0, 0x0}, - {0x2115c0, 0x0}, - {0x0116c0, 0x0}, - {0x1116c0, 0x0}, - {0x2116c0, 0x0}, - {0x0117c0, 0x0}, - {0x1117c0, 0x0}, - {0x2117c0, 0x0}, - {0x0118c0, 0x0}, - {0x1118c0, 0x0}, - {0x2118c0, 0x0}, - {0x0110c1, 0x0}, - {0x1110c1, 0x0}, - {0x2110c1, 0x0}, - {0x0111c1, 0x0}, - {0x1111c1, 0x0}, - {0x2111c1, 0x0}, - {0x0112c1, 0x0}, - {0x1112c1, 0x0}, - {0x2112c1, 0x0}, - {0x0113c1, 0x0}, - {0x1113c1, 0x0}, - {0x2113c1, 0x0}, - {0x0114c1, 0x0}, - {0x1114c1, 0x0}, - {0x2114c1, 0x0}, - {0x0115c1, 0x0}, - {0x1115c1, 0x0}, - {0x2115c1, 0x0}, - {0x0116c1, 0x0}, - {0x1116c1, 0x0}, - {0x2116c1, 0x0}, - {0x0117c1, 0x0}, - {0x1117c1, 0x0}, - {0x2117c1, 0x0}, - {0x0118c1, 0x0}, - {0x1118c1, 0x0}, - {0x2118c1, 0x0}, - {0x0110c2, 0x0}, - {0x1110c2, 0x0}, - {0x2110c2, 0x0}, - {0x0111c2, 0x0}, - {0x1111c2, 0x0}, - {0x2111c2, 0x0}, - {0x0112c2, 0x0}, - {0x1112c2, 0x0}, - {0x2112c2, 0x0}, - {0x0113c2, 0x0}, - {0x1113c2, 0x0}, - {0x2113c2, 0x0}, - {0x0114c2, 0x0}, - {0x1114c2, 0x0}, - {0x2114c2, 0x0}, - {0x0115c2, 0x0}, - {0x1115c2, 0x0}, - {0x2115c2, 0x0}, - {0x0116c2, 0x0}, - {0x1116c2, 0x0}, - {0x2116c2, 0x0}, - {0x0117c2, 0x0}, - {0x1117c2, 0x0}, - {0x2117c2, 0x0}, - {0x0118c2, 0x0}, - {0x1118c2, 0x0}, - {0x2118c2, 0x0}, - {0x0110c3, 0x0}, - {0x1110c3, 0x0}, - {0x2110c3, 0x0}, - {0x0111c3, 0x0}, - {0x1111c3, 0x0}, - {0x2111c3, 0x0}, - {0x0112c3, 0x0}, - {0x1112c3, 0x0}, - {0x2112c3, 0x0}, - {0x0113c3, 0x0}, - {0x1113c3, 0x0}, - {0x2113c3, 0x0}, - {0x0114c3, 0x0}, - {0x1114c3, 0x0}, - {0x2114c3, 0x0}, - {0x0115c3, 0x0}, - {0x1115c3, 0x0}, - {0x2115c3, 0x0}, - {0x0116c3, 0x0}, - {0x1116c3, 0x0}, - {0x2116c3, 0x0}, - {0x0117c3, 0x0}, - {0x1117c3, 0x0}, - {0x2117c3, 0x0}, - {0x0118c3, 0x0}, - {0x1118c3, 0x0}, - {0x2118c3, 0x0}, - {0x010020, 0x0}, - {0x110020, 0x0}, - {0x210020, 0x0}, - {0x011020, 0x0}, - {0x111020, 0x0}, - {0x211020, 0x0}, - {0x02007d, 0x0}, - {0x12007d, 0x0}, - {0x22007d, 0x0}, - {0x010040, 0x0}, - {0x010140, 0x0}, - {0x010240, 0x0}, - {0x010340, 0x0}, - {0x010440, 0x0}, - {0x010540, 0x0}, - {0x010640, 0x0}, - {0x010740, 0x0}, - {0x010840, 0x0}, - {0x010030, 0x0}, - {0x010130, 0x0}, - {0x010230, 0x0}, - {0x010330, 0x0}, - {0x010430, 0x0}, - {0x010530, 0x0}, - {0x010630, 0x0}, - {0x010730, 0x0}, - {0x010830, 0x0}, - {0x011040, 0x0}, - {0x011140, 0x0}, - {0x011240, 0x0}, - {0x011340, 0x0}, - {0x011440, 0x0}, - {0x011540, 0x0}, - {0x011640, 0x0}, - {0x011740, 0x0}, - {0x011840, 0x0}, - {0x011030, 0x0}, - {0x011130, 0x0}, - {0x011230, 0x0}, - {0x011330, 0x0}, - {0x011430, 0x0}, - {0x011530, 0x0}, - {0x011630, 0x0}, - {0x011730, 0x0}, - {0x011830, 0x0}, -}; - -/* P0 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp0_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0x960 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2830 }, - { 0x54006, 0x25e }, - { 0x54007, 0x1000 }, - { 0x54008, 0x101 }, - { 0x5400b, 0x31f }, - { 0x5400c, 0xc8 }, - { 0x5400d, 0x100 }, - { 0x54012, 0x1 }, - { 0x5402f, 0x834 }, - { 0x54030, 0x105 }, - { 0x54031, 0x18 }, - { 0x54032, 0x200 }, - { 0x54033, 0x200 }, - { 0x54034, 0x600 }, - { 0x54035, 0x810 }, - { 0x54036, 0x101 }, - { 0x5403f, 0x1221 }, - { 0x541fc, 0x100 }, - { 0xd0000, 0x1 }, -}; - -/* P1 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp1_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x1 }, - { 0x54003, 0x42a }, - { 0x54004, 0x2 }, - { 0x54005, 0x2830 }, - { 0x54006, 0x25e }, - { 0x54007, 0x1000 }, - { 0x54008, 0x101 }, - { 0x5400b, 0x21f }, - { 0x5400c, 0xc8 }, - { 0x5400d, 0x100 }, - { 0x54012, 0x1 }, - { 0x54030, 0x105 }, - { 0x54033, 0x200 }, - { 0x54034, 0x600 }, - { 0x54035, 0x10 }, - { 0x54036, 0x101 }, - { 0x5403f, 0x1221 }, - { 0x541fc, 0x100 }, - { 0xd0000, 0x1 }, -}; - -/* P0 2D message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0x960 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2830 }, - { 0x54006, 0x25e }, - { 0x54007, 0x1000 }, - { 0x54008, 0x101 }, - { 0x5400b, 0x61 }, - { 0x5400c, 0xc8 }, - { 0x5400d, 0x100 }, - { 0x5400e, 0x1f7f }, - { 0x54012, 0x1 }, - { 0x5402f, 0x834 }, - { 0x54030, 0x105 }, - { 0x54031, 0x18 }, - { 0x54032, 0x200 }, - { 0x54033, 0x200 }, - { 0x54034, 0x600 }, - { 0x54035, 0x810 }, - { 0x54036, 0x101 }, - { 0x5403f, 0x1221 }, - { 0x541fc, 0x100 }, - { 0xd0000, 0x1 }, -}; - -/* DRAM PHY init engine image */ -struct dram_cfg_param ddr_phy_pie[] = { - { 0xd0000, 0x0 }, - { 0x90000, 0x10 }, - { 0x90001, 0x400 }, - { 0x90002, 0x10e }, - { 0x90003, 0x0 }, - { 0x90004, 0x0 }, - { 0x90005, 0x8 }, - { 0x90029, 0xb }, - { 0x9002a, 0x480 }, - { 0x9002b, 0x109 }, - { 0x9002c, 0x8 }, - { 0x9002d, 0x448 }, - { 0x9002e, 0x139 }, - { 0x9002f, 0x8 }, - { 0x90030, 0x478 }, - { 0x90031, 0x109 }, - { 0x90032, 0x2 }, - { 0x90033, 0x10 }, - { 0x90034, 0x139 }, - { 0x90035, 0xb }, - { 0x90036, 0x7c0 }, - { 0x90037, 0x139 }, - { 0x90038, 0x44 }, - { 0x90039, 0x633 }, - { 0x9003a, 0x159 }, - { 0x9003b, 0x14f }, - { 0x9003c, 0x630 }, - { 0x9003d, 0x159 }, - { 0x9003e, 0x47 }, - { 0x9003f, 0x633 }, - { 0x90040, 0x149 }, - { 0x90041, 0x4f }, - { 0x90042, 0x633 }, - { 0x90043, 0x179 }, - { 0x90044, 0x8 }, - { 0x90045, 0xe0 }, - { 0x90046, 0x109 }, - { 0x90047, 0x0 }, - { 0x90048, 0x7c8 }, - { 0x90049, 0x109 }, - { 0x9004a, 0x0 }, - { 0x9004b, 0x1 }, - { 0x9004c, 0x8 }, - { 0x9004d, 0x0 }, - { 0x9004e, 0x45a }, - { 0x9004f, 0x9 }, - { 0x90050, 0x0 }, - { 0x90051, 0x448 }, - { 0x90052, 0x109 }, - { 0x90053, 0x40 }, - { 0x90054, 0x633 }, - { 0x90055, 0x179 }, - { 0x90056, 0x1 }, - { 0x90057, 0x618 }, - { 0x90058, 0x109 }, - { 0x90059, 0x40c0 }, - { 0x9005a, 0x633 }, - { 0x9005b, 0x149 }, - { 0x9005c, 0x8 }, - { 0x9005d, 0x4 }, - { 0x9005e, 0x48 }, - { 0x9005f, 0x4040 }, - { 0x90060, 0x633 }, - { 0x90061, 0x149 }, - { 0x90062, 0x0 }, - { 0x90063, 0x4 }, - { 0x90064, 0x48 }, - { 0x90065, 0x40 }, - { 0x90066, 0x633 }, - { 0x90067, 0x149 }, - { 0x90068, 0x10 }, - { 0x90069, 0x4 }, - { 0x9006a, 0x18 }, - { 0x9006b, 0x0 }, - { 0x9006c, 0x4 }, - { 0x9006d, 0x78 }, - { 0x9006e, 0x549 }, - { 0x9006f, 0x633 }, - { 0x90070, 0x159 }, - { 0x90071, 0xd49 }, - { 0x90072, 0x633 }, - { 0x90073, 0x159 }, - { 0x90074, 0x94a }, - { 0x90075, 0x633 }, - { 0x90076, 0x159 }, - { 0x90077, 0x441 }, - { 0x90078, 0x633 }, - { 0x90079, 0x149 }, - { 0x9007a, 0x42 }, - { 0x9007b, 0x633 }, - { 0x9007c, 0x149 }, - { 0x9007d, 0x1 }, - { 0x9007e, 0x633 }, - { 0x9007f, 0x149 }, - { 0x90080, 0x0 }, - { 0x90081, 0xe0 }, - { 0x90082, 0x109 }, - { 0x90083, 0xa }, - { 0x90084, 0x10 }, - { 0x90085, 0x109 }, - { 0x90086, 0x9 }, - { 0x90087, 0x3c0 }, - { 0x90088, 0x149 }, - { 0x90089, 0x9 }, - { 0x9008a, 0x3c0 }, - { 0x9008b, 0x159 }, - { 0x9008c, 0x18 }, - { 0x9008d, 0x10 }, - { 0x9008e, 0x109 }, - { 0x9008f, 0x0 }, - { 0x90090, 0x3c0 }, - { 0x90091, 0x109 }, - { 0x90092, 0x18 }, - { 0x90093, 0x4 }, - { 0x90094, 0x48 }, - { 0x90095, 0x18 }, - { 0x90096, 0x4 }, - { 0x90097, 0x58 }, - { 0x90098, 0xb }, - { 0x90099, 0x10 }, - { 0x9009a, 0x109 }, - { 0x9009b, 0x1 }, - { 0x9009c, 0x10 }, - { 0x9009d, 0x109 }, - { 0x9009e, 0x5 }, - { 0x9009f, 0x7c0 }, - { 0x900a0, 0x109 }, - { 0x900a1, 0x0 }, - { 0x900a2, 0x8140 }, - { 0x900a3, 0x10c }, - { 0x900a4, 0x10 }, - { 0x900a5, 0x8138 }, - { 0x900a6, 0x10c }, - { 0x900a7, 0x8 }, - { 0x900a8, 0x7c8 }, - { 0x900a9, 0x101 }, - { 0x900aa, 0x8 }, - { 0x900ab, 0x448 }, - { 0x900ac, 0x109 }, - { 0x900ad, 0xf }, - { 0x900ae, 0x7c0 }, - { 0x900af, 0x109 }, - { 0x900b0, 0x47 }, - { 0x900b1, 0x630 }, - { 0x900b2, 0x109 }, - { 0x900b3, 0x8 }, - { 0x900b4, 0x618 }, - { 0x900b5, 0x109 }, - { 0x900b6, 0x8 }, - { 0x900b7, 0xe0 }, - { 0x900b8, 0x109 }, - { 0x900b9, 0x0 }, - { 0x900ba, 0x7c8 }, - { 0x900bb, 0x109 }, - { 0x900bc, 0x8 }, - { 0x900bd, 0x8140 }, - { 0x900be, 0x10c }, - { 0x900bf, 0x0 }, - { 0x900c0, 0x1 }, - { 0x900c1, 0x8 }, - { 0x900c2, 0x8 }, - { 0x900c3, 0x4 }, - { 0x900c4, 0x8 }, - { 0x900c5, 0x8 }, - { 0x900c6, 0x7c8 }, - { 0x900c7, 0x101 }, - { 0x90006, 0x0 }, - { 0x90007, 0x0 }, - { 0x90008, 0x8 }, - { 0x90009, 0x0 }, - { 0x9000a, 0x0 }, - { 0x9000b, 0x0 }, - { 0xd00e7, 0x400 }, - { 0x90017, 0x0 }, - { 0x90026, 0x2b }, - { 0x2000b, 0x4b }, - { 0x2000c, 0x96 }, - { 0x2000d, 0x5dc }, - { 0x2000e, 0x2c }, - { 0x12000b, 0x21 }, - { 0x12000c, 0x42 }, - { 0x12000d, 0x29a }, - { 0x12000e, 0x21 }, - { 0x9000c, 0x0 }, - { 0x9000d, 0x173 }, - { 0x9000e, 0x60 }, - { 0x9000f, 0x6110 }, - { 0x90010, 0x2152 }, - { 0x90011, 0xdfbd }, - { 0x90012, 0xffff }, - { 0x90013, 0x6152 }, - { 0x20089, 0x1 }, - { 0x20088, 0x19 }, - { 0xc0080, 0x0 }, - { 0xd0000, 0x1 } -}; - -struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 2400mts 1D */ - .drate = 2400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 1066mts 1D */ - .drate = 1066, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P0 2400mts 2D */ - .drate = 2400, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 2400, 1066, }, -}; diff --git a/board/freescale/imx8mn_evk/ddr4_timing_ld.c b/board/freescale/imx8mn_evk/ddr4_timing_ld.c deleted file mode 100644 index d719b5916f5..00000000000 --- a/board/freescale/imx8mn_evk/ddr4_timing_ld.c +++ /dev/null @@ -1,1054 +0,0 @@ -/* - * Copyright 2019 NXP - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Generated code from MX8M_DDR_tool - * Align with uboot version: - * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga - */ - -#include -#include - -struct dram_cfg_param ddr_ddrc_cfg[] = { - /** Initialize DDRC registers **/ - { 0x3d400000, 0x81040010 }, - { 0x3d400030, 0x20 }, - { 0x3d400034, 0x221306 }, - { 0x3d400050, 0x210070 }, - { 0x3d400054, 0x10008 }, - { 0x3d400060, 0x0 }, - { 0x3d400064, 0x6100dc }, - { 0x3d4000c0, 0x0 }, - { 0x3d4000c4, 0x1000 }, - { 0x3d4000d0, 0xc00200c5 }, - { 0x3d4000d4, 0x500000 }, - { 0x3d4000dc, 0x2340105 }, - { 0x3d4000e0, 0x0 }, - { 0x3d4000e4, 0x110000 }, - { 0x3d4000e8, 0x2000600 }, - { 0x3d4000ec, 0x410 }, - { 0x3d4000f0, 0x20 }, - { 0x3d4000f4, 0xec7 }, - { 0x3d400100, 0xd0c1b0d }, - { 0x3d400104, 0x30313 }, - { 0x3d400108, 0x508060a }, - { 0x3d40010c, 0x400c }, - { 0x3d400110, 0x6030306 }, - { 0x3d400114, 0x4040302 }, - { 0x3d40011c, 0x404 }, - { 0x3d400120, 0x5050d08 }, - { 0x3d400124, 0x20308 }, - { 0x3d40012c, 0x1406010e }, - { 0x3d400130, 0x8 }, - { 0x3d40013c, 0x0 }, - { 0x3d400180, 0x1000040 }, - { 0x3d400184, 0x30d4 }, - { 0x3d400190, 0x38b8204 }, - { 0x3d400194, 0x2020303 }, - { 0x3d400198, 0x7f04011 }, - { 0x3d40019c, 0xb0 }, - { 0x3d4001a0, 0xe0400018 }, - { 0x3d4001a4, 0x48005a }, - { 0x3d4001a8, 0x80000000 }, - { 0x3d4001b0, 0x1 }, - { 0x3d4001b4, 0xb04 }, - { 0x3d4001b8, 0x4 }, - { 0x3d4001c0, 0x1 }, - { 0x3d4001c4, 0x0 }, - { 0x3d400200, 0x3f1f }, - { 0x3d400204, 0x3f0909 }, - { 0x3d400208, 0x700 }, - { 0x3d40020c, 0x0 }, - { 0x3d400210, 0x1f1f }, - { 0x3d400214, 0x7070707 }, - { 0x3d400218, 0x7070707 }, - { 0x3d40021c, 0xf07 }, - { 0x3d400220, 0x3f01 }, - { 0x3d400240, 0x600061c }, - { 0x3d400244, 0x1323 }, - { 0x3d400400, 0x100 }, - { 0x3d400250, 0x317d1a07 }, - { 0x3d400254, 0xf }, - { 0x3d40025c, 0x2a001b76 }, - { 0x3d400264, 0x7300b473 }, - { 0x3d40026c, 0x30000e06 }, - { 0x3d400300, 0x14 }, - { 0x3d40036c, 0x10 }, - { 0x3d400404, 0x13193 }, - { 0x3d400408, 0x6096 }, - { 0x3d400490, 0x1 }, - { 0x3d400494, 0x2000c00 }, - { 0x3d400498, 0x3c00db }, - { 0x3d40049c, 0x100009 }, - { 0x3d4004a0, 0x2 }, - { 0x3d402050, 0x210070 }, - { 0x3d402064, 0x400093 }, - { 0x3d4020dc, 0x40105 }, - { 0x3d4020e0, 0x0 }, - { 0x3d4020e8, 0x2000600 }, - { 0x3d4020ec, 0x10 }, - { 0x3d402100, 0xb081209 }, - { 0x3d402104, 0x2020d }, - { 0x3d402108, 0x5050309 }, - { 0x3d40210c, 0x400c }, - { 0x3d402110, 0x5030206 }, - { 0x3d402114, 0x3030202 }, - { 0x3d40211c, 0x303 }, - { 0x3d402120, 0x4040d06 }, - { 0x3d402124, 0x20208 }, - { 0x3d40212c, 0x1205010e }, - { 0x3d402130, 0x8 }, - { 0x3d40213c, 0x0 }, - { 0x3d402180, 0x1000040 }, - { 0x3d402190, 0x3858204 }, - { 0x3d402194, 0x2020303 }, - { 0x3d4021b4, 0x504 }, - { 0x3d4021b8, 0x4 }, - { 0x3d402240, 0x6000604 }, - { 0x3d4020f4, 0xec7 }, -}; - -/* PHY Initialize Configuration */ -struct dram_cfg_param ddr_ddrphy_cfg[] = { - { 0x1005f, 0x2fd }, - { 0x1015f, 0x2fd }, - { 0x1105f, 0x2fd }, - { 0x1115f, 0x2fd }, - { 0x11005f, 0x2fd }, - { 0x11015f, 0x2fd }, - { 0x11105f, 0x2fd }, - { 0x11115f, 0x2fd }, - { 0x55, 0x355 }, - { 0x1055, 0x355 }, - { 0x2055, 0x355 }, - { 0x3055, 0x355 }, - { 0x4055, 0x55 }, - { 0x5055, 0x55 }, - { 0x6055, 0x355 }, - { 0x7055, 0x355 }, - { 0x8055, 0x355 }, - { 0x9055, 0x355 }, - { 0x200c5, 0xb }, - { 0x1200c5, 0x6 }, - { 0x2002e, 0x1 }, - { 0x12002e, 0x1 }, - { 0x20024, 0x8 }, - { 0x2003a, 0x2 }, - { 0x120024, 0x8 }, - { 0x2003a, 0x2 }, - { 0x20056, 0xa }, - { 0x120056, 0xa }, - { 0x1004d, 0x1a }, - { 0x1014d, 0x1a }, - { 0x1104d, 0x1a }, - { 0x1114d, 0x1a }, - { 0x11004d, 0x1a }, - { 0x11014d, 0x1a }, - { 0x11104d, 0x1a }, - { 0x11114d, 0x1a }, - { 0x10049, 0xe38 }, - { 0x10149, 0xe38 }, - { 0x11049, 0xe38 }, - { 0x11149, 0xe38 }, - { 0x110049, 0xe38 }, - { 0x110149, 0xe38 }, - { 0x111049, 0xe38 }, - { 0x111149, 0xe38 }, - { 0x43, 0x63 }, - { 0x1043, 0x63 }, - { 0x2043, 0x63 }, - { 0x3043, 0x63 }, - { 0x4043, 0x63 }, - { 0x5043, 0x63 }, - { 0x6043, 0x63 }, - { 0x7043, 0x63 }, - { 0x8043, 0x63 }, - { 0x9043, 0x63 }, - { 0x20018, 0x1 }, - { 0x20075, 0x2 }, - { 0x20050, 0x0 }, - { 0x20008, 0x190 }, - { 0x120008, 0x10a }, - { 0x20088, 0x9 }, - { 0x200b2, 0x268 }, - { 0x10043, 0x5b1 }, - { 0x10143, 0x5b1 }, - { 0x11043, 0x5b1 }, - { 0x11143, 0x5b1 }, - { 0x1200b2, 0x268 }, - { 0x110043, 0x5b1 }, - { 0x110143, 0x5b1 }, - { 0x111043, 0x5b1 }, - { 0x111143, 0x5b1 }, - { 0x200fa, 0x1 }, - { 0x1200fa, 0x1 }, - { 0x20019, 0x5 }, - { 0x120019, 0x5 }, - { 0x200f0, 0x5555 }, - { 0x200f1, 0x5555 }, - { 0x200f2, 0x5555 }, - { 0x200f3, 0x5555 }, - { 0x200f4, 0x5555 }, - { 0x200f5, 0x5555 }, - { 0x200f6, 0x5555 }, - { 0x200f7, 0xf000 }, - { 0x20025, 0x0 }, - { 0x2002d, 0x0 }, - { 0x12002d, 0x0 }, - { 0x2005b, 0x7529 }, - { 0x2005c, 0x0 }, - { 0x200c7, 0x21 }, - { 0x200ca, 0x24 }, - { 0x200cc, 0x1f7 }, - { 0x1200c7, 0x21 }, - { 0x1200ca, 0x24 }, - { 0x1200cc, 0x1f7 }, - { 0x2007d, 0x212 }, - { 0x12007d, 0x212 }, - { 0x2007c, 0x61 }, - { 0x12007c, 0x61 }, - { 0x1004a, 0x500 }, - { 0x1104a, 0x500 }, - { 0x2002c, 0x0 }, -}; - -/* ddr phy trained csr */ -struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - {0x0200b2, 0x0}, - {0x1200b2, 0x0}, - {0x2200b2, 0x0}, - {0x0200cb, 0x0}, - {0x010043, 0x0}, - {0x110043, 0x0}, - {0x210043, 0x0}, - {0x010143, 0x0}, - {0x110143, 0x0}, - {0x210143, 0x0}, - {0x011043, 0x0}, - {0x111043, 0x0}, - {0x211043, 0x0}, - {0x011143, 0x0}, - {0x111143, 0x0}, - {0x211143, 0x0}, - {0x000080, 0x0}, - {0x100080, 0x0}, - {0x200080, 0x0}, - {0x001080, 0x0}, - {0x101080, 0x0}, - {0x201080, 0x0}, - {0x002080, 0x0}, - {0x102080, 0x0}, - {0x202080, 0x0}, - {0x003080, 0x0}, - {0x103080, 0x0}, - {0x203080, 0x0}, - {0x004080, 0x0}, - {0x104080, 0x0}, - {0x204080, 0x0}, - {0x005080, 0x0}, - {0x105080, 0x0}, - {0x205080, 0x0}, - {0x006080, 0x0}, - {0x106080, 0x0}, - {0x206080, 0x0}, - {0x007080, 0x0}, - {0x107080, 0x0}, - {0x207080, 0x0}, - {0x008080, 0x0}, - {0x108080, 0x0}, - {0x208080, 0x0}, - {0x009080, 0x0}, - {0x109080, 0x0}, - {0x209080, 0x0}, - {0x010080, 0x0}, - {0x110080, 0x0}, - {0x210080, 0x0}, - {0x010180, 0x0}, - {0x110180, 0x0}, - {0x210180, 0x0}, - {0x010081, 0x0}, - {0x110081, 0x0}, - {0x210081, 0x0}, - {0x010181, 0x0}, - {0x110181, 0x0}, - {0x210181, 0x0}, - {0x010082, 0x0}, - {0x110082, 0x0}, - {0x210082, 0x0}, - {0x010182, 0x0}, - {0x110182, 0x0}, - {0x210182, 0x0}, - {0x010083, 0x0}, - {0x110083, 0x0}, - {0x210083, 0x0}, - {0x010183, 0x0}, - {0x110183, 0x0}, - {0x210183, 0x0}, - {0x011080, 0x0}, - {0x111080, 0x0}, - {0x211080, 0x0}, - {0x011180, 0x0}, - {0x111180, 0x0}, - {0x211180, 0x0}, - {0x011081, 0x0}, - {0x111081, 0x0}, - {0x211081, 0x0}, - {0x011181, 0x0}, - {0x111181, 0x0}, - {0x211181, 0x0}, - {0x011082, 0x0}, - {0x111082, 0x0}, - {0x211082, 0x0}, - {0x011182, 0x0}, - {0x111182, 0x0}, - {0x211182, 0x0}, - {0x011083, 0x0}, - {0x111083, 0x0}, - {0x211083, 0x0}, - {0x011183, 0x0}, - {0x111183, 0x0}, - {0x211183, 0x0}, - {0x0100d0, 0x0}, - {0x1100d0, 0x0}, - {0x2100d0, 0x0}, - {0x0101d0, 0x0}, - {0x1101d0, 0x0}, - {0x2101d0, 0x0}, - {0x0100d1, 0x0}, - {0x1100d1, 0x0}, - {0x2100d1, 0x0}, - {0x0101d1, 0x0}, - {0x1101d1, 0x0}, - {0x2101d1, 0x0}, - {0x0100d2, 0x0}, - {0x1100d2, 0x0}, - {0x2100d2, 0x0}, - {0x0101d2, 0x0}, - {0x1101d2, 0x0}, - {0x2101d2, 0x0}, - {0x0100d3, 0x0}, - {0x1100d3, 0x0}, - {0x2100d3, 0x0}, - {0x0101d3, 0x0}, - {0x1101d3, 0x0}, - {0x2101d3, 0x0}, - {0x0110d0, 0x0}, - {0x1110d0, 0x0}, - {0x2110d0, 0x0}, - {0x0111d0, 0x0}, - {0x1111d0, 0x0}, - {0x2111d0, 0x0}, - {0x0110d1, 0x0}, - {0x1110d1, 0x0}, - {0x2110d1, 0x0}, - {0x0111d1, 0x0}, - {0x1111d1, 0x0}, - {0x2111d1, 0x0}, - {0x0110d2, 0x0}, - {0x1110d2, 0x0}, - {0x2110d2, 0x0}, - {0x0111d2, 0x0}, - {0x1111d2, 0x0}, - {0x2111d2, 0x0}, - {0x0110d3, 0x0}, - {0x1110d3, 0x0}, - {0x2110d3, 0x0}, - {0x0111d3, 0x0}, - {0x1111d3, 0x0}, - {0x2111d3, 0x0}, - {0x010068, 0x0}, - {0x010168, 0x0}, - {0x010268, 0x0}, - {0x010368, 0x0}, - {0x010468, 0x0}, - {0x010568, 0x0}, - {0x010668, 0x0}, - {0x010768, 0x0}, - {0x010868, 0x0}, - {0x010069, 0x0}, - {0x010169, 0x0}, - {0x010269, 0x0}, - {0x010369, 0x0}, - {0x010469, 0x0}, - {0x010569, 0x0}, - {0x010669, 0x0}, - {0x010769, 0x0}, - {0x010869, 0x0}, - {0x01006a, 0x0}, - {0x01016a, 0x0}, - {0x01026a, 0x0}, - {0x01036a, 0x0}, - {0x01046a, 0x0}, - {0x01056a, 0x0}, - {0x01066a, 0x0}, - {0x01076a, 0x0}, - {0x01086a, 0x0}, - {0x01006b, 0x0}, - {0x01016b, 0x0}, - {0x01026b, 0x0}, - {0x01036b, 0x0}, - {0x01046b, 0x0}, - {0x01056b, 0x0}, - {0x01066b, 0x0}, - {0x01076b, 0x0}, - {0x01086b, 0x0}, - {0x011068, 0x0}, - {0x011168, 0x0}, - {0x011268, 0x0}, - {0x011368, 0x0}, - {0x011468, 0x0}, - {0x011568, 0x0}, - {0x011668, 0x0}, - {0x011768, 0x0}, - {0x011868, 0x0}, - {0x011069, 0x0}, - {0x011169, 0x0}, - {0x011269, 0x0}, - {0x011369, 0x0}, - {0x011469, 0x0}, - {0x011569, 0x0}, - {0x011669, 0x0}, - {0x011769, 0x0}, - {0x011869, 0x0}, - {0x01106a, 0x0}, - {0x01116a, 0x0}, - {0x01126a, 0x0}, - {0x01136a, 0x0}, - {0x01146a, 0x0}, - {0x01156a, 0x0}, - {0x01166a, 0x0}, - {0x01176a, 0x0}, - {0x01186a, 0x0}, - {0x01106b, 0x0}, - {0x01116b, 0x0}, - {0x01126b, 0x0}, - {0x01136b, 0x0}, - {0x01146b, 0x0}, - {0x01156b, 0x0}, - {0x01166b, 0x0}, - {0x01176b, 0x0}, - {0x01186b, 0x0}, - {0x01008c, 0x0}, - {0x11008c, 0x0}, - {0x21008c, 0x0}, - {0x01018c, 0x0}, - {0x11018c, 0x0}, - {0x21018c, 0x0}, - {0x01008d, 0x0}, - {0x11008d, 0x0}, - {0x21008d, 0x0}, - {0x01018d, 0x0}, - {0x11018d, 0x0}, - {0x21018d, 0x0}, - {0x01008e, 0x0}, - {0x11008e, 0x0}, - {0x21008e, 0x0}, - {0x01018e, 0x0}, - {0x11018e, 0x0}, - {0x21018e, 0x0}, - {0x01008f, 0x0}, - {0x11008f, 0x0}, - {0x21008f, 0x0}, - {0x01018f, 0x0}, - {0x11018f, 0x0}, - {0x21018f, 0x0}, - {0x01108c, 0x0}, - {0x11108c, 0x0}, - {0x21108c, 0x0}, - {0x01118c, 0x0}, - {0x11118c, 0x0}, - {0x21118c, 0x0}, - {0x01108d, 0x0}, - {0x11108d, 0x0}, - {0x21108d, 0x0}, - {0x01118d, 0x0}, - {0x11118d, 0x0}, - {0x21118d, 0x0}, - {0x01108e, 0x0}, - {0x11108e, 0x0}, - {0x21108e, 0x0}, - {0x01118e, 0x0}, - {0x11118e, 0x0}, - {0x21118e, 0x0}, - {0x01108f, 0x0}, - {0x11108f, 0x0}, - {0x21108f, 0x0}, - {0x01118f, 0x0}, - {0x11118f, 0x0}, - {0x21118f, 0x0}, - {0x0100c0, 0x0}, - {0x1100c0, 0x0}, - {0x2100c0, 0x0}, - {0x0101c0, 0x0}, - {0x1101c0, 0x0}, - {0x2101c0, 0x0}, - {0x0102c0, 0x0}, - {0x1102c0, 0x0}, - {0x2102c0, 0x0}, - {0x0103c0, 0x0}, - {0x1103c0, 0x0}, - {0x2103c0, 0x0}, - {0x0104c0, 0x0}, - {0x1104c0, 0x0}, - {0x2104c0, 0x0}, - {0x0105c0, 0x0}, - {0x1105c0, 0x0}, - {0x2105c0, 0x0}, - {0x0106c0, 0x0}, - {0x1106c0, 0x0}, - {0x2106c0, 0x0}, - {0x0107c0, 0x0}, - {0x1107c0, 0x0}, - {0x2107c0, 0x0}, - {0x0108c0, 0x0}, - {0x1108c0, 0x0}, - {0x2108c0, 0x0}, - {0x0100c1, 0x0}, - {0x1100c1, 0x0}, - {0x2100c1, 0x0}, - {0x0101c1, 0x0}, - {0x1101c1, 0x0}, - {0x2101c1, 0x0}, - {0x0102c1, 0x0}, - {0x1102c1, 0x0}, - {0x2102c1, 0x0}, - {0x0103c1, 0x0}, - {0x1103c1, 0x0}, - {0x2103c1, 0x0}, - {0x0104c1, 0x0}, - {0x1104c1, 0x0}, - {0x2104c1, 0x0}, - {0x0105c1, 0x0}, - {0x1105c1, 0x0}, - {0x2105c1, 0x0}, - {0x0106c1, 0x0}, - {0x1106c1, 0x0}, - {0x2106c1, 0x0}, - {0x0107c1, 0x0}, - {0x1107c1, 0x0}, - {0x2107c1, 0x0}, - {0x0108c1, 0x0}, - {0x1108c1, 0x0}, - {0x2108c1, 0x0}, - {0x0100c2, 0x0}, - {0x1100c2, 0x0}, - {0x2100c2, 0x0}, - {0x0101c2, 0x0}, - {0x1101c2, 0x0}, - {0x2101c2, 0x0}, - {0x0102c2, 0x0}, - {0x1102c2, 0x0}, - {0x2102c2, 0x0}, - {0x0103c2, 0x0}, - {0x1103c2, 0x0}, - {0x2103c2, 0x0}, - {0x0104c2, 0x0}, - {0x1104c2, 0x0}, - {0x2104c2, 0x0}, - {0x0105c2, 0x0}, - {0x1105c2, 0x0}, - {0x2105c2, 0x0}, - {0x0106c2, 0x0}, - {0x1106c2, 0x0}, - {0x2106c2, 0x0}, - {0x0107c2, 0x0}, - {0x1107c2, 0x0}, - {0x2107c2, 0x0}, - {0x0108c2, 0x0}, - {0x1108c2, 0x0}, - {0x2108c2, 0x0}, - {0x0100c3, 0x0}, - {0x1100c3, 0x0}, - {0x2100c3, 0x0}, - {0x0101c3, 0x0}, - {0x1101c3, 0x0}, - {0x2101c3, 0x0}, - {0x0102c3, 0x0}, - {0x1102c3, 0x0}, - {0x2102c3, 0x0}, - {0x0103c3, 0x0}, - {0x1103c3, 0x0}, - {0x2103c3, 0x0}, - {0x0104c3, 0x0}, - {0x1104c3, 0x0}, - {0x2104c3, 0x0}, - {0x0105c3, 0x0}, - {0x1105c3, 0x0}, - {0x2105c3, 0x0}, - {0x0106c3, 0x0}, - {0x1106c3, 0x0}, - {0x2106c3, 0x0}, - {0x0107c3, 0x0}, - {0x1107c3, 0x0}, - {0x2107c3, 0x0}, - {0x0108c3, 0x0}, - {0x1108c3, 0x0}, - {0x2108c3, 0x0}, - {0x0110c0, 0x0}, - {0x1110c0, 0x0}, - {0x2110c0, 0x0}, - {0x0111c0, 0x0}, - {0x1111c0, 0x0}, - {0x2111c0, 0x0}, - {0x0112c0, 0x0}, - {0x1112c0, 0x0}, - {0x2112c0, 0x0}, - {0x0113c0, 0x0}, - {0x1113c0, 0x0}, - {0x2113c0, 0x0}, - {0x0114c0, 0x0}, - {0x1114c0, 0x0}, - {0x2114c0, 0x0}, - {0x0115c0, 0x0}, - {0x1115c0, 0x0}, - {0x2115c0, 0x0}, - {0x0116c0, 0x0}, - {0x1116c0, 0x0}, - {0x2116c0, 0x0}, - {0x0117c0, 0x0}, - {0x1117c0, 0x0}, - {0x2117c0, 0x0}, - {0x0118c0, 0x0}, - {0x1118c0, 0x0}, - {0x2118c0, 0x0}, - {0x0110c1, 0x0}, - {0x1110c1, 0x0}, - {0x2110c1, 0x0}, - {0x0111c1, 0x0}, - {0x1111c1, 0x0}, - {0x2111c1, 0x0}, - {0x0112c1, 0x0}, - {0x1112c1, 0x0}, - {0x2112c1, 0x0}, - {0x0113c1, 0x0}, - {0x1113c1, 0x0}, - {0x2113c1, 0x0}, - {0x0114c1, 0x0}, - {0x1114c1, 0x0}, - {0x2114c1, 0x0}, - {0x0115c1, 0x0}, - {0x1115c1, 0x0}, - {0x2115c1, 0x0}, - {0x0116c1, 0x0}, - {0x1116c1, 0x0}, - {0x2116c1, 0x0}, - {0x0117c1, 0x0}, - {0x1117c1, 0x0}, - {0x2117c1, 0x0}, - {0x0118c1, 0x0}, - {0x1118c1, 0x0}, - {0x2118c1, 0x0}, - {0x0110c2, 0x0}, - {0x1110c2, 0x0}, - {0x2110c2, 0x0}, - {0x0111c2, 0x0}, - {0x1111c2, 0x0}, - {0x2111c2, 0x0}, - {0x0112c2, 0x0}, - {0x1112c2, 0x0}, - {0x2112c2, 0x0}, - {0x0113c2, 0x0}, - {0x1113c2, 0x0}, - {0x2113c2, 0x0}, - {0x0114c2, 0x0}, - {0x1114c2, 0x0}, - {0x2114c2, 0x0}, - {0x0115c2, 0x0}, - {0x1115c2, 0x0}, - {0x2115c2, 0x0}, - {0x0116c2, 0x0}, - {0x1116c2, 0x0}, - {0x2116c2, 0x0}, - {0x0117c2, 0x0}, - {0x1117c2, 0x0}, - {0x2117c2, 0x0}, - {0x0118c2, 0x0}, - {0x1118c2, 0x0}, - {0x2118c2, 0x0}, - {0x0110c3, 0x0}, - {0x1110c3, 0x0}, - {0x2110c3, 0x0}, - {0x0111c3, 0x0}, - {0x1111c3, 0x0}, - {0x2111c3, 0x0}, - {0x0112c3, 0x0}, - {0x1112c3, 0x0}, - {0x2112c3, 0x0}, - {0x0113c3, 0x0}, - {0x1113c3, 0x0}, - {0x2113c3, 0x0}, - {0x0114c3, 0x0}, - {0x1114c3, 0x0}, - {0x2114c3, 0x0}, - {0x0115c3, 0x0}, - {0x1115c3, 0x0}, - {0x2115c3, 0x0}, - {0x0116c3, 0x0}, - {0x1116c3, 0x0}, - {0x2116c3, 0x0}, - {0x0117c3, 0x0}, - {0x1117c3, 0x0}, - {0x2117c3, 0x0}, - {0x0118c3, 0x0}, - {0x1118c3, 0x0}, - {0x2118c3, 0x0}, - {0x010020, 0x0}, - {0x110020, 0x0}, - {0x210020, 0x0}, - {0x011020, 0x0}, - {0x111020, 0x0}, - {0x211020, 0x0}, - {0x02007d, 0x0}, - {0x12007d, 0x0}, - {0x22007d, 0x0}, - {0x010040, 0x0}, - {0x010140, 0x0}, - {0x010240, 0x0}, - {0x010340, 0x0}, - {0x010440, 0x0}, - {0x010540, 0x0}, - {0x010640, 0x0}, - {0x010740, 0x0}, - {0x010840, 0x0}, - {0x010030, 0x0}, - {0x010130, 0x0}, - {0x010230, 0x0}, - {0x010330, 0x0}, - {0x010430, 0x0}, - {0x010530, 0x0}, - {0x010630, 0x0}, - {0x010730, 0x0}, - {0x010830, 0x0}, - {0x011040, 0x0}, - {0x011140, 0x0}, - {0x011240, 0x0}, - {0x011340, 0x0}, - {0x011440, 0x0}, - {0x011540, 0x0}, - {0x011640, 0x0}, - {0x011740, 0x0}, - {0x011840, 0x0}, - {0x011030, 0x0}, - {0x011130, 0x0}, - {0x011230, 0x0}, - {0x011330, 0x0}, - {0x011430, 0x0}, - {0x011530, 0x0}, - {0x011630, 0x0}, - {0x011730, 0x0}, - {0x011830, 0x0}, -}; - -/* P0 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp0_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0x640 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2830 }, - { 0x54006, 0x25e }, - { 0x54007, 0x1000 }, - { 0x54008, 0x101 }, - { 0x5400b, 0x31f }, - { 0x5400c, 0xc8 }, - { 0x5400d, 0x100 }, - { 0x54012, 0x1 }, - { 0x5402f, 0x234 }, - { 0x54030, 0x105 }, - { 0x54033, 0x200 }, - { 0x54034, 0x600 }, - { 0x54035, 0x410 }, - { 0x54036, 0x101 }, - { 0x5403f, 0x1221 }, - { 0x541fc, 0x100 }, - { 0xd0000, 0x1 }, -}; - -/* P1 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp1_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x1 }, - { 0x54003, 0x42a }, - { 0x54004, 0x2 }, - { 0x54005, 0x2830 }, - { 0x54006, 0x25e }, - { 0x54007, 0x1000 }, - { 0x54008, 0x101 }, - { 0x5400b, 0x21f }, - { 0x5400c, 0xc8 }, - { 0x5400d, 0x100 }, - { 0x54012, 0x1 }, - { 0x5402f, 0x4 }, - { 0x54030, 0x105 }, - { 0x54033, 0x200 }, - { 0x54034, 0x600 }, - { 0x54035, 0x10 }, - { 0x54036, 0x101 }, - { 0x5403f, 0x1221 }, - { 0x541fc, 0x100 }, - { 0xd0000, 0x1 }, -}; - -/* P0 2D message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0x640 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2830 }, - { 0x54006, 0x25e }, - { 0x54007, 0x1000 }, - { 0x54008, 0x101 }, - { 0x5400b, 0x61 }, - { 0x5400c, 0xc8 }, - { 0x5400d, 0x100 }, - { 0x5400e, 0x1f7f }, - { 0x54012, 0x1 }, - { 0x5402f, 0x234 }, - { 0x54030, 0x105 }, - { 0x54033, 0x200 }, - { 0x54034, 0x600 }, - { 0x54035, 0x410 }, - { 0x54036, 0x101 }, - { 0x5403f, 0x1221 }, - { 0x541fc, 0x100 }, - { 0xd0000, 0x1 }, -}; - -/* DRAM PHY init engine image */ -struct dram_cfg_param ddr_phy_pie[] = { - { 0xd0000, 0x0 }, - { 0x90000, 0x10 }, - { 0x90001, 0x400 }, - { 0x90002, 0x10e }, - { 0x90003, 0x0 }, - { 0x90004, 0x0 }, - { 0x90005, 0x8 }, - { 0x90029, 0xb }, - { 0x9002a, 0x480 }, - { 0x9002b, 0x109 }, - { 0x9002c, 0x8 }, - { 0x9002d, 0x448 }, - { 0x9002e, 0x139 }, - { 0x9002f, 0x8 }, - { 0x90030, 0x478 }, - { 0x90031, 0x109 }, - { 0x90032, 0x2 }, - { 0x90033, 0x10 }, - { 0x90034, 0x139 }, - { 0x90035, 0xb }, - { 0x90036, 0x7c0 }, - { 0x90037, 0x139 }, - { 0x90038, 0x44 }, - { 0x90039, 0x633 }, - { 0x9003a, 0x159 }, - { 0x9003b, 0x14f }, - { 0x9003c, 0x630 }, - { 0x9003d, 0x159 }, - { 0x9003e, 0x47 }, - { 0x9003f, 0x633 }, - { 0x90040, 0x149 }, - { 0x90041, 0x4f }, - { 0x90042, 0x633 }, - { 0x90043, 0x179 }, - { 0x90044, 0x8 }, - { 0x90045, 0xe0 }, - { 0x90046, 0x109 }, - { 0x90047, 0x0 }, - { 0x90048, 0x7c8 }, - { 0x90049, 0x109 }, - { 0x9004a, 0x0 }, - { 0x9004b, 0x1 }, - { 0x9004c, 0x8 }, - { 0x9004d, 0x0 }, - { 0x9004e, 0x45a }, - { 0x9004f, 0x9 }, - { 0x90050, 0x0 }, - { 0x90051, 0x448 }, - { 0x90052, 0x109 }, - { 0x90053, 0x40 }, - { 0x90054, 0x633 }, - { 0x90055, 0x179 }, - { 0x90056, 0x1 }, - { 0x90057, 0x618 }, - { 0x90058, 0x109 }, - { 0x90059, 0x40c0 }, - { 0x9005a, 0x633 }, - { 0x9005b, 0x149 }, - { 0x9005c, 0x8 }, - { 0x9005d, 0x4 }, - { 0x9005e, 0x48 }, - { 0x9005f, 0x4040 }, - { 0x90060, 0x633 }, - { 0x90061, 0x149 }, - { 0x90062, 0x0 }, - { 0x90063, 0x4 }, - { 0x90064, 0x48 }, - { 0x90065, 0x40 }, - { 0x90066, 0x633 }, - { 0x90067, 0x149 }, - { 0x90068, 0x10 }, - { 0x90069, 0x4 }, - { 0x9006a, 0x18 }, - { 0x9006b, 0x0 }, - { 0x9006c, 0x4 }, - { 0x9006d, 0x78 }, - { 0x9006e, 0x549 }, - { 0x9006f, 0x633 }, - { 0x90070, 0x159 }, - { 0x90071, 0xd49 }, - { 0x90072, 0x633 }, - { 0x90073, 0x159 }, - { 0x90074, 0x94a }, - { 0x90075, 0x633 }, - { 0x90076, 0x159 }, - { 0x90077, 0x441 }, - { 0x90078, 0x633 }, - { 0x90079, 0x149 }, - { 0x9007a, 0x42 }, - { 0x9007b, 0x633 }, - { 0x9007c, 0x149 }, - { 0x9007d, 0x1 }, - { 0x9007e, 0x633 }, - { 0x9007f, 0x149 }, - { 0x90080, 0x0 }, - { 0x90081, 0xe0 }, - { 0x90082, 0x109 }, - { 0x90083, 0xa }, - { 0x90084, 0x10 }, - { 0x90085, 0x109 }, - { 0x90086, 0x9 }, - { 0x90087, 0x3c0 }, - { 0x90088, 0x149 }, - { 0x90089, 0x9 }, - { 0x9008a, 0x3c0 }, - { 0x9008b, 0x159 }, - { 0x9008c, 0x18 }, - { 0x9008d, 0x10 }, - { 0x9008e, 0x109 }, - { 0x9008f, 0x0 }, - { 0x90090, 0x3c0 }, - { 0x90091, 0x109 }, - { 0x90092, 0x18 }, - { 0x90093, 0x4 }, - { 0x90094, 0x48 }, - { 0x90095, 0x18 }, - { 0x90096, 0x4 }, - { 0x90097, 0x58 }, - { 0x90098, 0xb }, - { 0x90099, 0x10 }, - { 0x9009a, 0x109 }, - { 0x9009b, 0x1 }, - { 0x9009c, 0x10 }, - { 0x9009d, 0x109 }, - { 0x9009e, 0x5 }, - { 0x9009f, 0x7c0 }, - { 0x900a0, 0x109 }, - { 0x900a1, 0x0 }, - { 0x900a2, 0x8140 }, - { 0x900a3, 0x10c }, - { 0x900a4, 0x10 }, - { 0x900a5, 0x8138 }, - { 0x900a6, 0x10c }, - { 0x900a7, 0x8 }, - { 0x900a8, 0x7c8 }, - { 0x900a9, 0x101 }, - { 0x900aa, 0x8 }, - { 0x900ab, 0x448 }, - { 0x900ac, 0x109 }, - { 0x900ad, 0xf }, - { 0x900ae, 0x7c0 }, - { 0x900af, 0x109 }, - { 0x900b0, 0x47 }, - { 0x900b1, 0x630 }, - { 0x900b2, 0x109 }, - { 0x900b3, 0x8 }, - { 0x900b4, 0x618 }, - { 0x900b5, 0x109 }, - { 0x900b6, 0x8 }, - { 0x900b7, 0xe0 }, - { 0x900b8, 0x109 }, - { 0x900b9, 0x0 }, - { 0x900ba, 0x7c8 }, - { 0x900bb, 0x109 }, - { 0x900bc, 0x8 }, - { 0x900bd, 0x8140 }, - { 0x900be, 0x10c }, - { 0x900bf, 0x0 }, - { 0x900c0, 0x1 }, - { 0x900c1, 0x8 }, - { 0x900c2, 0x8 }, - { 0x900c3, 0x4 }, - { 0x900c4, 0x8 }, - { 0x900c5, 0x8 }, - { 0x900c6, 0x7c8 }, - { 0x900c7, 0x101 }, - { 0x90006, 0x0 }, - { 0x90007, 0x0 }, - { 0x90008, 0x8 }, - { 0x90009, 0x0 }, - { 0x9000a, 0x0 }, - { 0x9000b, 0x0 }, - { 0xd00e7, 0x400 }, - { 0x90017, 0x0 }, - { 0x90026, 0x2b }, - { 0x2000b, 0x32 }, - { 0x2000c, 0x64 }, - { 0x2000d, 0x3e8 }, - { 0x2000e, 0x2c }, - { 0x12000b, 0x21 }, - { 0x12000c, 0x42 }, - { 0x12000d, 0x29a }, - { 0x12000e, 0x21 }, - { 0x9000c, 0x0 }, - { 0x9000d, 0x173 }, - { 0x9000e, 0x60 }, - { 0x9000f, 0x6110 }, - { 0x90010, 0x2152 }, - { 0x90011, 0xdfbd }, - { 0x90012, 0xffff }, - { 0x90013, 0x6152 }, - { 0x20089, 0x1 }, - { 0x20088, 0x19 }, - { 0xc0080, 0x0 }, - { 0xd0000, 0x1 } -}; - -struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 1600mts 1D */ - .drate = 1600, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 1066mts 1D */ - .drate = 1066, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P0 1600mts 2D */ - .drate = 1600, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 1600, 1066, }, -}; diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c b/board/freescale/imx8mn_evk/imx8mn_evk.c deleted file mode 100644 index 9d3f29f2253..00000000000 --- a/board/freescale/imx8mn_evk/imx8mn_evk.c +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 NXP - */ - -#include -#include -#include -#include -#include -#include - -#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) -#define IMX_BOOT_IMAGE_GUID \ - EFI_GUID(0xcbabf44d, 0x12cc, 0x45dd, 0xb0, 0xc5, \ - 0x29, 0xc5, 0xb7, 0x42, 0x2d, 0x34) - -struct efi_fw_image fw_images[] = { - { - .image_type_id = IMX_BOOT_IMAGE_GUID, - .fw_name = u"IMX8MN-EVK-RAW", - .image_index = 1, - }, -}; - -struct efi_capsule_update_info update_info = { - .dfu_string = "mmc 2=flash-bin raw 0 0x2000 mmcpart 1", - .num_images = ARRAY_SIZE(fw_images), - .images = fw_images, -}; -#endif /* EFI_HAVE_CAPSULE_SUPPORT */ - -int board_mmc_get_env_dev(int devno) -{ - return devno; -} - -static void setup_fec(void) -{ - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - - /* Use 125M anatop REF_CLK1 for ENET1, not from external */ - clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); -} - -int board_init(void) -{ - setup_fec(); - - return 0; -} - -int board_late_init(void) -{ -#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) - board_late_mmc_env_init(); -#endif - -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - env_set("board_name", "DDR4 EVK"); - env_set("board_rev", "iMX8MN"); -#endif - return 0; -} diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.env b/board/freescale/imx8mn_evk/imx8mn_evk.env deleted file mode 100644 index 487893f9287..00000000000 --- a/board/freescale/imx8mn_evk/imx8mn_evk.env +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ - -boot_fdt=try -boot_fit=no -boot_targets=mmc1 mmc2 dhcp -bootm_size=0x10000000 -console=ttymxc1,115200 -fdt_addr_r=0x48000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE -fdtoverlay_addr_r=0x49000000 -initrd_addr=0x48080000 -image=Image -ip_dyn=yes -kernel_addr_r=0x42000000 -loadaddr=CONFIG_SYS_LOAD_ADDR -mmcautodetect=yes -mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX -mmcpart=1 -mmcroot=/dev/mmcblk1p2 rootwait rw -prepare_mcore=setenv mcore_clk clk-imx8mn.mcore_booted; -pxefile_addr_r=0x40100000 -ramdisk_addr_r=0x48080000 -scriptaddr=0x40000000 - -mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} -prepare_mcore=setenv mcore_clk clk-imx8mn.mcore_booted -loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} -loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -mmcboot=echo Booting from mmc ...; - run mmcargs; - if test ${boot_fit} = yes || test ${boot_fit} = try; then - bootm ${loadaddr}; - else - if run loadfdt; then - booti ${loadaddr} - ${fdt_addr_r}; - else - echo WARN: Cannot load the DT; - fi; - fi -netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs - ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp -netboot=echo Booting from net ...; - run netargs; - if test ${ip_dyn} = yes; then - setenv get_cmd dhcp; - else - setenv get_cmd tftp; - fi; - ${get_cmd} ${loadaddr} ${image}; - if test ${boot_fit} = yes || test ${boot_fit} = try; then - bootm ${loadaddr}; - else - if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then - booti ${loadaddr} - ${fdt_addr_r}; - else - echo WARN: Cannot load the DT; - fi; - fi; -bsp_bootcmd=echo Running BSP bootcmd ...; - mmc dev ${mmcdev}; - if mmc rescan; then - if run loadimage; then - run mmcboot; - else - run netboot; - fi; - fi; diff --git a/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg b/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg deleted file mode 100644 index 0edda9c5e06..00000000000 --- a/board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2021 NXP - */ - - -ROM_VERSION v2 -BOOT_FROM sd -LOADER u-boot-spl-ddr.bin 0x912000 diff --git a/board/freescale/imx8mn_evk/lpddr4_timing.c b/board/freescale/imx8mn_evk/lpddr4_timing.c deleted file mode 100644 index 671e924132a..00000000000 --- a/board/freescale/imx8mn_evk/lpddr4_timing.c +++ /dev/null @@ -1,1587 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 NXP - * - * Generated code from MX8M_DDR_tool - * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga - */ - -#include -#include - -struct dram_cfg_param ddr_ddrc_cfg[] = { - {0x3d400020, 0x00000213}, - {0x3d400024, 0x0003e800}, - {0x3d400030, 0x00000120}, - {0x3d400000, 0xa3080020}, - {0x3d400064, 0x006100e0}, - {0x3d4000d0, 0xc003061c}, - {0x3d4000d4, 0x009e0000}, - {0x3d4000dc, 0x00d4002d}, - {0x3d4000e0, 0x00310000}, - {0x3d4000e8, 0x0066004d}, - {0x3d4000ec, 0x0016004a}, - {0x3d400100, 0x1a201b22}, - {0x3d400104, 0x00060633}, - {0x3d40010c, 0x00c0c000}, - {0x3d400110, 0x0f04080f}, - {0x3d400114, 0x02040c0c}, - {0x3d400118, 0x01010007}, - {0x3d40011c, 0x00000401}, - {0x3d400130, 0x00020600}, - {0x3d400134, 0x0c100002}, - {0x3d400138, 0x000000e6}, - {0x3d400144, 0x00a00050}, - {0x3d400180, 0x03200018}, - {0x3d400184, 0x028061a8}, - {0x3d400188, 0x00000000}, - {0x3d400190, 0x0497820a}, - {0x3d4001b4, 0x0000170a}, - {0x3d400108, 0x070e1617}, - {0x3d4001c0, 0x00000001}, - {0x3d400194, 0x00080303}, - {0x3d4001a0, 0xe0400018}, - {0x3d4001a4, 0x00df00e4}, - {0x3d4001a8, 0x80000000}, - {0x3d4001b0, 0x00000011}, - {0x3d4001c4, 0x00000001}, - {0x3d4000f4, 0x00000c99}, - {0x3d400200, 0x00000017}, - {0x3d400204, 0x00080808}, - {0x3d400208, 0x00000000}, - {0x3d40020c, 0x00000000}, - {0x3d400210, 0x00001f1f}, - {0x3d400214, 0x07070707}, - {0x3d400218, 0x07070707}, - {0x3d40021c, 0x00000f0f}, - {0x3d400250, 0x29001701}, - {0x3d400254, 0x0000002c}, - {0x3d40025c, 0x04000030}, - {0x3d400264, 0x900093e7}, - {0x3d40026c, 0x20005574}, - {0x3d400400, 0x00000111}, - {0x3d400408, 0x000072ff}, - {0x3d400494, 0x02100e07}, - {0x3d400498, 0x00620096}, - {0x3d40049c, 0x01100e07}, - {0x3d4004a0, 0x00c8012c}, - {0x3d402020, 0x00000011}, - {0x3d402024, 0x00007d00}, - {0x3d402050, 0x0020d040}, - {0x3d402064, 0x000c001d}, - {0x3d4020f4, 0x00000c99}, - {0x3d402100, 0x0a040305}, - {0x3d402104, 0x00030407}, - {0x3d402108, 0x0203060b}, - {0x3d40210c, 0x00505000}, - {0x3d402110, 0x02040202}, - {0x3d402114, 0x02030202}, - {0x3d402118, 0x01010004}, - {0x3d40211c, 0x00000301}, - {0x3d402130, 0x00020300}, - {0x3d402134, 0x0a100002}, - {0x3d402138, 0x0000001d}, - {0x3d402144, 0x0014000a}, - {0x3d402180, 0x00650004}, - {0x3d402190, 0x03818200}, - {0x3d402194, 0x00080303}, - {0x3d4021b4, 0x00000100}, - {0x3d4020dc, 0x00840000}, - {0x3d4020e0, 0x00310000}, - {0x3d4020e8, 0x0066004d}, - {0x3d4020ec, 0x0016004a}, - {0x3d403020, 0x00000011}, - {0x3d403024, 0x00001f40}, - {0x3d403050, 0x0020d040}, - {0x3d403064, 0x00030007}, - {0x3d4030f4, 0x00000c99}, - {0x3d403100, 0x0a010102}, - {0x3d403104, 0x00030404}, - {0x3d403108, 0x0203060b}, - {0x3d40310c, 0x00505000}, - {0x3d403110, 0x02040202}, - {0x3d403114, 0x02030202}, - {0x3d403118, 0x01010004}, - {0x3d40311c, 0x00000301}, - {0x3d403130, 0x00020300}, - {0x3d403134, 0x0a100002}, - {0x3d403138, 0x00000008}, - {0x3d403144, 0x00050003}, - {0x3d403180, 0x00190004}, - {0x3d403190, 0x03818200}, - {0x3d403194, 0x00080303}, - {0x3d4031b4, 0x00000100}, - {0x3d4030dc, 0x00840000}, - {0x3d4030e0, 0x00310000}, - {0x3d4030e8, 0x0066004d}, - {0x3d4030ec, 0x0016004a}, - - /* default boot point */ - { 0x3d400028, 0x0 }, -}; - -/* PHY Initialize Configuration */ -struct dram_cfg_param ddr_ddrphy_cfg[] = { - {0x000d0000, 0x00000000}, - {0x000100a0, 0x00000000}, - {0x000100a1, 0x00000001}, - {0x000100a2, 0x00000002}, - {0x000100a3, 0x00000003}, - {0x000100a4, 0x00000004}, - {0x000100a5, 0x00000005}, - {0x000100a6, 0x00000006}, - {0x000100a7, 0x00000007}, - {0x000110a0, 0x00000000}, - {0x000110a1, 0x00000001}, - {0x000110a2, 0x00000003}, - {0x000110a3, 0x00000004}, - {0x000110a4, 0x00000005}, - {0x000110a5, 0x00000002}, - {0x000110a6, 0x00000007}, - {0x000110a7, 0x00000006}, - {0x0001005f, 0x0000015f}, - {0x0001015f, 0x0000015f}, - {0x0001105f, 0x0000015f}, - {0x0001115f, 0x0000015f}, - {0x0011005f, 0x0000015f}, - {0x0011015f, 0x0000015f}, - {0x0011105f, 0x0000015f}, - {0x0011115f, 0x0000015f}, - {0x0021005f, 0x0000015f}, - {0x0021015f, 0x0000015f}, - {0x0021105f, 0x0000015f}, - {0x0021115f, 0x0000015f}, - {0x00000055, 0x0000016f}, - {0x00001055, 0x0000016f}, - {0x00002055, 0x0000016f}, - {0x00003055, 0x0000016f}, - {0x00004055, 0x0000016f}, - {0x00005055, 0x0000016f}, - {0x00006055, 0x0000016f}, - {0x00007055, 0x0000016f}, - {0x00008055, 0x0000016f}, - {0x00009055, 0x0000016f}, - {0x000200c5, 0x00000019}, - {0x001200c5, 0x00000007}, - {0x002200c5, 0x00000007}, - {0x0002002e, 0x00000002}, - {0x0012002e, 0x00000002}, - {0x0022002e, 0x00000002}, - {0x00090204, 0x00000000}, - {0x00190204, 0x00000000}, - {0x00290204, 0x00000000}, - {0x00020024, 0x000001a3}, - {0x0002003a, 0x00000002}, - {0x0002007d, 0x00000212}, - {0x0002007c, 0x00000061}, - {0x00120024, 0x000001a3}, - {0x0002003a, 0x00000002}, - {0x0012007d, 0x00000212}, - {0x0012007c, 0x00000061}, - {0x00220024, 0x000001a3}, - {0x0002003a, 0x00000002}, - {0x0022007d, 0x00000212}, - {0x0022007c, 0x00000061}, - {0x00020056, 0x00000003}, - {0x00120056, 0x00000003}, - {0x00220056, 0x00000003}, - {0x0001004d, 0x00000f80}, - {0x0001014d, 0x00000f80}, - {0x0001104d, 0x00000f80}, - {0x0001114d, 0x00000f80}, - {0x0011004d, 0x00000f80}, - {0x0011014d, 0x00000f80}, - {0x0011104d, 0x00000f80}, - {0x0011114d, 0x00000f80}, - {0x0021004d, 0x00000f80}, - {0x0021014d, 0x00000f80}, - {0x0021104d, 0x00000f80}, - {0x0021114d, 0x00000f80}, - {0x00010049, 0x00000fbe}, - {0x00010149, 0x00000fbe}, - {0x00011049, 0x00000fbe}, - {0x00011149, 0x00000fbe}, - {0x00110049, 0x00000fbe}, - {0x00110149, 0x00000fbe}, - {0x00111049, 0x00000fbe}, - {0x00111149, 0x00000fbe}, - {0x00210049, 0x00000fbe}, - {0x00210149, 0x00000fbe}, - {0x00211049, 0x00000fbe}, - {0x00211149, 0x00000fbe}, - {0x00000043, 0x00000063}, - {0x00001043, 0x00000063}, - {0x00002043, 0x00000063}, - {0x00003043, 0x00000063}, - {0x00004043, 0x00000063}, - {0x00005043, 0x00000063}, - {0x00006043, 0x00000063}, - {0x00007043, 0x00000063}, - {0x00008043, 0x00000063}, - {0x00009043, 0x00000063}, - {0x00020018, 0x00000001}, - {0x00020075, 0x00000004}, - {0x00020050, 0x00000000}, - {0x00020008, 0x00000320}, - {0x00120008, 0x00000064}, - {0x00220008, 0x00000019}, - {0x00020088, 0x00000009}, - {0x000200b2, 0x000000dc}, - {0x00010043, 0x000005a1}, - {0x00010143, 0x000005a1}, - {0x00011043, 0x000005a1}, - {0x00011143, 0x000005a1}, - {0x001200b2, 0x000000dc}, - {0x00110043, 0x000005a1}, - {0x00110143, 0x000005a1}, - {0x00111043, 0x000005a1}, - {0x00111143, 0x000005a1}, - {0x002200b2, 0x000000dc}, - {0x00210043, 0x000005a1}, - {0x00210143, 0x000005a1}, - {0x00211043, 0x000005a1}, - {0x00211143, 0x000005a1}, - {0x000200fa, 0x00000001}, - {0x001200fa, 0x00000001}, - {0x002200fa, 0x00000001}, - {0x00020019, 0x00000001}, - {0x00120019, 0x00000001}, - {0x00220019, 0x00000001}, - {0x000200f0, 0x00000660}, - {0x000200f1, 0x00000000}, - {0x000200f2, 0x00004444}, - {0x000200f3, 0x00008888}, - {0x000200f4, 0x00005665}, - {0x000200f5, 0x00000000}, - {0x000200f6, 0x00000000}, - {0x000200f7, 0x0000f000}, - {0x0001004a, 0x00000500}, - {0x0001104a, 0x00000500}, - {0x00020025, 0x00000000}, - {0x0002002d, 0x00000000}, - {0x0012002d, 0x00000000}, - {0x0022002d, 0x00000000}, - {0x0002002c, 0x00000000}, - {0x000200c7, 0x00000021}, - {0x000200ca, 0x00000024}, - {0x000200cc, 0x000001f7}, - {0x001200c7, 0x00000021}, - {0x001200ca, 0x00000024}, - {0x001200cc, 0x000001f7}, - {0x002200c7, 0x00000021}, - {0x002200ca, 0x00000024}, - {0x002200cc, 0x000001f7}, - {0x00020060, 0x00000002}, - {0x000d0000, 0x00000001}, -}; - -/* ddr phy trained csr */ -struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - {0x0200b2, 0x0}, - {0x1200b2, 0x0}, - {0x2200b2, 0x0}, - {0x0200cb, 0x0}, - {0x010043, 0x0}, - {0x110043, 0x0}, - {0x210043, 0x0}, - {0x010143, 0x0}, - {0x110143, 0x0}, - {0x210143, 0x0}, - {0x011043, 0x0}, - {0x111043, 0x0}, - {0x211043, 0x0}, - {0x011143, 0x0}, - {0x111143, 0x0}, - {0x211143, 0x0}, - {0x000080, 0x0}, - {0x100080, 0x0}, - {0x200080, 0x0}, - {0x001080, 0x0}, - {0x101080, 0x0}, - {0x201080, 0x0}, - {0x002080, 0x0}, - {0x102080, 0x0}, - {0x202080, 0x0}, - {0x003080, 0x0}, - {0x103080, 0x0}, - {0x203080, 0x0}, - {0x004080, 0x0}, - {0x104080, 0x0}, - {0x204080, 0x0}, - {0x005080, 0x0}, - {0x105080, 0x0}, - {0x205080, 0x0}, - {0x006080, 0x0}, - {0x106080, 0x0}, - {0x206080, 0x0}, - {0x007080, 0x0}, - {0x107080, 0x0}, - {0x207080, 0x0}, - {0x008080, 0x0}, - {0x108080, 0x0}, - {0x208080, 0x0}, - {0x009080, 0x0}, - {0x109080, 0x0}, - {0x209080, 0x0}, - {0x010080, 0x0}, - {0x110080, 0x0}, - {0x210080, 0x0}, - {0x010180, 0x0}, - {0x110180, 0x0}, - {0x210180, 0x0}, - {0x011080, 0x0}, - {0x111080, 0x0}, - {0x211080, 0x0}, - {0x011180, 0x0}, - {0x111180, 0x0}, - {0x211180, 0x0}, - {0x010081, 0x0}, - {0x110081, 0x0}, - {0x210081, 0x0}, - {0x010181, 0x0}, - {0x110181, 0x0}, - {0x210181, 0x0}, - {0x011081, 0x0}, - {0x111081, 0x0}, - {0x211081, 0x0}, - {0x011181, 0x0}, - {0x111181, 0x0}, - {0x211181, 0x0}, - {0x0100d0, 0x0}, - {0x1100d0, 0x0}, - {0x2100d0, 0x0}, - {0x0101d0, 0x0}, - {0x1101d0, 0x0}, - {0x2101d0, 0x0}, - {0x0110d0, 0x0}, - {0x1110d0, 0x0}, - {0x2110d0, 0x0}, - {0x0111d0, 0x0}, - {0x1111d0, 0x0}, - {0x2111d0, 0x0}, - {0x0100d1, 0x0}, - {0x1100d1, 0x0}, - {0x2100d1, 0x0}, - {0x0101d1, 0x0}, - {0x1101d1, 0x0}, - {0x2101d1, 0x0}, - {0x0110d1, 0x0}, - {0x1110d1, 0x0}, - {0x2110d1, 0x0}, - {0x0111d1, 0x0}, - {0x1111d1, 0x0}, - {0x2111d1, 0x0}, - {0x010068, 0x0}, - {0x010168, 0x0}, - {0x010268, 0x0}, - {0x010368, 0x0}, - {0x010468, 0x0}, - {0x010568, 0x0}, - {0x010668, 0x0}, - {0x010768, 0x0}, - {0x010868, 0x0}, - {0x011068, 0x0}, - {0x011168, 0x0}, - {0x011268, 0x0}, - {0x011368, 0x0}, - {0x011468, 0x0}, - {0x011568, 0x0}, - {0x011668, 0x0}, - {0x011768, 0x0}, - {0x011868, 0x0}, - {0x010069, 0x0}, - {0x010169, 0x0}, - {0x010269, 0x0}, - {0x010369, 0x0}, - {0x010469, 0x0}, - {0x010569, 0x0}, - {0x010669, 0x0}, - {0x010769, 0x0}, - {0x010869, 0x0}, - {0x011069, 0x0}, - {0x011169, 0x0}, - {0x011269, 0x0}, - {0x011369, 0x0}, - {0x011469, 0x0}, - {0x011569, 0x0}, - {0x011669, 0x0}, - {0x011769, 0x0}, - {0x011869, 0x0}, - {0x01008c, 0x0}, - {0x11008c, 0x0}, - {0x21008c, 0x0}, - {0x01018c, 0x0}, - {0x11018c, 0x0}, - {0x21018c, 0x0}, - {0x01108c, 0x0}, - {0x11108c, 0x0}, - {0x21108c, 0x0}, - {0x01118c, 0x0}, - {0x11118c, 0x0}, - {0x21118c, 0x0}, - {0x01008d, 0x0}, - {0x11008d, 0x0}, - {0x21008d, 0x0}, - {0x01018d, 0x0}, - {0x11018d, 0x0}, - {0x21018d, 0x0}, - {0x01108d, 0x0}, - {0x11108d, 0x0}, - {0x21108d, 0x0}, - {0x01118d, 0x0}, - {0x11118d, 0x0}, - {0x21118d, 0x0}, - {0x0100c0, 0x0}, - {0x1100c0, 0x0}, - {0x2100c0, 0x0}, - {0x0101c0, 0x0}, - {0x1101c0, 0x0}, - {0x2101c0, 0x0}, - {0x0102c0, 0x0}, - {0x1102c0, 0x0}, - {0x2102c0, 0x0}, - {0x0103c0, 0x0}, - {0x1103c0, 0x0}, - {0x2103c0, 0x0}, - {0x0104c0, 0x0}, - {0x1104c0, 0x0}, - {0x2104c0, 0x0}, - {0x0105c0, 0x0}, - {0x1105c0, 0x0}, - {0x2105c0, 0x0}, - {0x0106c0, 0x0}, - {0x1106c0, 0x0}, - {0x2106c0, 0x0}, - {0x0107c0, 0x0}, - {0x1107c0, 0x0}, - {0x2107c0, 0x0}, - {0x0108c0, 0x0}, - {0x1108c0, 0x0}, - {0x2108c0, 0x0}, - {0x0110c0, 0x0}, - {0x1110c0, 0x0}, - {0x2110c0, 0x0}, - {0x0111c0, 0x0}, - {0x1111c0, 0x0}, - {0x2111c0, 0x0}, - {0x0112c0, 0x0}, - {0x1112c0, 0x0}, - {0x2112c0, 0x0}, - {0x0113c0, 0x0}, - {0x1113c0, 0x0}, - {0x2113c0, 0x0}, - {0x0114c0, 0x0}, - {0x1114c0, 0x0}, - {0x2114c0, 0x0}, - {0x0115c0, 0x0}, - {0x1115c0, 0x0}, - {0x2115c0, 0x0}, - {0x0116c0, 0x0}, - {0x1116c0, 0x0}, - {0x2116c0, 0x0}, - {0x0117c0, 0x0}, - {0x1117c0, 0x0}, - {0x2117c0, 0x0}, - {0x0118c0, 0x0}, - {0x1118c0, 0x0}, - {0x2118c0, 0x0}, - {0x0100c1, 0x0}, - {0x1100c1, 0x0}, - {0x2100c1, 0x0}, - {0x0101c1, 0x0}, - {0x1101c1, 0x0}, - {0x2101c1, 0x0}, - {0x0102c1, 0x0}, - {0x1102c1, 0x0}, - {0x2102c1, 0x0}, - {0x0103c1, 0x0}, - {0x1103c1, 0x0}, - {0x2103c1, 0x0}, - {0x0104c1, 0x0}, - {0x1104c1, 0x0}, - {0x2104c1, 0x0}, - {0x0105c1, 0x0}, - {0x1105c1, 0x0}, - {0x2105c1, 0x0}, - {0x0106c1, 0x0}, - {0x1106c1, 0x0}, - {0x2106c1, 0x0}, - {0x0107c1, 0x0}, - {0x1107c1, 0x0}, - {0x2107c1, 0x0}, - {0x0108c1, 0x0}, - {0x1108c1, 0x0}, - {0x2108c1, 0x0}, - {0x0110c1, 0x0}, - {0x1110c1, 0x0}, - {0x2110c1, 0x0}, - {0x0111c1, 0x0}, - {0x1111c1, 0x0}, - {0x2111c1, 0x0}, - {0x0112c1, 0x0}, - {0x1112c1, 0x0}, - {0x2112c1, 0x0}, - {0x0113c1, 0x0}, - {0x1113c1, 0x0}, - {0x2113c1, 0x0}, - {0x0114c1, 0x0}, - {0x1114c1, 0x0}, - {0x2114c1, 0x0}, - {0x0115c1, 0x0}, - {0x1115c1, 0x0}, - {0x2115c1, 0x0}, - {0x0116c1, 0x0}, - {0x1116c1, 0x0}, - {0x2116c1, 0x0}, - {0x0117c1, 0x0}, - {0x1117c1, 0x0}, - {0x2117c1, 0x0}, - {0x0118c1, 0x0}, - {0x1118c1, 0x0}, - {0x2118c1, 0x0}, - {0x010020, 0x0}, - {0x110020, 0x0}, - {0x210020, 0x0}, - {0x011020, 0x0}, - {0x111020, 0x0}, - {0x211020, 0x0}, - {0x020072, 0x0}, - {0x020073, 0x0}, - {0x020074, 0x0}, - {0x0100aa, 0x0}, - {0x0110aa, 0x0}, - {0x020010, 0x0}, - {0x120010, 0x0}, - {0x220010, 0x0}, - {0x020011, 0x0}, - {0x120011, 0x0}, - {0x220011, 0x0}, - {0x0100ae, 0x0}, - {0x1100ae, 0x0}, - {0x2100ae, 0x0}, - {0x0100af, 0x0}, - {0x1100af, 0x0}, - {0x2100af, 0x0}, - {0x0110ae, 0x0}, - {0x1110ae, 0x0}, - {0x2110ae, 0x0}, - {0x0110af, 0x0}, - {0x1110af, 0x0}, - {0x2110af, 0x0}, - {0x020020, 0x0}, - {0x120020, 0x0}, - {0x220020, 0x0}, - {0x0100a0, 0x0}, - {0x0100a1, 0x0}, - {0x0100a2, 0x0}, - {0x0100a3, 0x0}, - {0x0100a4, 0x0}, - {0x0100a5, 0x0}, - {0x0100a6, 0x0}, - {0x0100a7, 0x0}, - {0x0110a0, 0x0}, - {0x0110a1, 0x0}, - {0x0110a2, 0x0}, - {0x0110a3, 0x0}, - {0x0110a4, 0x0}, - {0x0110a5, 0x0}, - {0x0110a6, 0x0}, - {0x0110a7, 0x0}, - {0x02007c, 0x0}, - {0x12007c, 0x0}, - {0x22007c, 0x0}, - {0x02007d, 0x0}, - {0x12007d, 0x0}, - {0x22007d, 0x0}, - {0x0400fd, 0x0}, - {0x0400c0, 0x0}, - {0x090201, 0x0}, - {0x190201, 0x0}, - {0x290201, 0x0}, - {0x090202, 0x0}, - {0x190202, 0x0}, - {0x290202, 0x0}, - {0x090203, 0x0}, - {0x190203, 0x0}, - {0x290203, 0x0}, - {0x090204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x090205, 0x0}, - {0x190205, 0x0}, - {0x290205, 0x0}, - {0x090206, 0x0}, - {0x190206, 0x0}, - {0x290206, 0x0}, - {0x090207, 0x0}, - {0x190207, 0x0}, - {0x290207, 0x0}, - {0x090208, 0x0}, - {0x190208, 0x0}, - {0x290208, 0x0}, - {0x010062, 0x0}, - {0x010162, 0x0}, - {0x010262, 0x0}, - {0x010362, 0x0}, - {0x010462, 0x0}, - {0x010562, 0x0}, - {0x010662, 0x0}, - {0x010762, 0x0}, - {0x010862, 0x0}, - {0x011062, 0x0}, - {0x011162, 0x0}, - {0x011262, 0x0}, - {0x011362, 0x0}, - {0x011462, 0x0}, - {0x011562, 0x0}, - {0x011662, 0x0}, - {0x011762, 0x0}, - {0x011862, 0x0}, - {0x020077, 0x0}, - {0x010001, 0x0}, - {0x011001, 0x0}, - {0x010040, 0x0}, - {0x010140, 0x0}, - {0x010240, 0x0}, - {0x010340, 0x0}, - {0x010440, 0x0}, - {0x010540, 0x0}, - {0x010640, 0x0}, - {0x010740, 0x0}, - {0x010840, 0x0}, - {0x010030, 0x0}, - {0x010130, 0x0}, - {0x010230, 0x0}, - {0x010330, 0x0}, - {0x010430, 0x0}, - {0x010530, 0x0}, - {0x010630, 0x0}, - {0x010730, 0x0}, - {0x010830, 0x0}, - {0x011040, 0x0}, - {0x011140, 0x0}, - {0x011240, 0x0}, - {0x011340, 0x0}, - {0x011440, 0x0}, - {0x011540, 0x0}, - {0x011640, 0x0}, - {0x011740, 0x0}, - {0x011840, 0x0}, - {0x011030, 0x0}, - {0x011130, 0x0}, - {0x011230, 0x0}, - {0x011330, 0x0}, - {0x011430, 0x0}, - {0x011530, 0x0}, - {0x011630, 0x0}, - {0x011730, 0x0}, - {0x011830, 0x0}, -}; - -/* P0 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp0_cfg[] = { - {0x000d0000, 0x00000000}, - {0x00054000, 0x00000000}, - {0x00054001, 0x00000000}, - {0x00054002, 0x00000000}, - {0x00054003, 0x00000c80}, - {0x00054004, 0x00000002}, - {0x00054005, 0x00000000}, - {0x00054006, 0x00000011}, - {0x00054007, 0x00000000}, - {0x00054008, 0x0000131f}, - {0x00054009, 0x000000c8}, - {0x0005400a, 0x00000000}, - {0x0005400b, 0x00000002}, - {0x0005400c, 0x00000000}, - {0x0005400d, 0x00000000}, - {0x0005400e, 0x00000000}, - {0x0005400f, 0x00000100}, - {0x00054010, 0x00000000}, - {0x00054011, 0x00000000}, - {0x00054012, 0x00000310}, - {0x00054013, 0x00000000}, - {0x00054014, 0x00000000}, - {0x00054015, 0x00000000}, - {0x00054016, 0x00000000}, - {0x00054017, 0x00000000}, - {0x00054018, 0x00000000}, - {0x00054019, 0x00002dd4}, - {0x0005401a, 0x00000031}, - {0x0005401b, 0x00004d66}, - {0x0005401c, 0x00004a00}, - {0x0005401d, 0x00000000}, - {0x0005401e, 0x00000016}, - {0x0005401f, 0x00002dd4}, - {0x00054020, 0x00000031}, - {0x00054021, 0x00004d66}, - {0x00054022, 0x00004a00}, - {0x00054023, 0x00000000}, - {0x00054024, 0x0000002e}, - {0x00054025, 0x00000000}, - {0x00054026, 0x00000000}, - {0x00054027, 0x00000000}, - {0x00054028, 0x00000000}, - {0x00054029, 0x00000000}, - {0x0005402a, 0x00000000}, - {0x0005402b, 0x00000000}, - {0x0005402c, 0x00000000}, - {0x0005402d, 0x00000000}, - {0x0005402e, 0x00000000}, - {0x0005402f, 0x00000000}, - {0x00054030, 0x00000000}, - {0x00054031, 0x00000000}, - {0x00054032, 0x0000d400}, - {0x00054033, 0x0000312d}, - {0x00054034, 0x00006600}, - {0x00054035, 0x0000004d}, - {0x00054036, 0x0000004a}, - {0x00054037, 0x00001600}, - {0x00054038, 0x0000d400}, - {0x00054039, 0x0000312d}, - {0x0005403a, 0x00006600}, - {0x0005403b, 0x0000004d}, - {0x0005403c, 0x0000004a}, - {0x0005403d, 0x00002e00}, - {0x0005403e, 0x00000000}, - {0x0005403f, 0x00000000}, - {0x00054040, 0x00000000}, - {0x00054041, 0x00000000}, - {0x00054042, 0x00000000}, - {0x00054043, 0x00000000}, - {0x00054044, 0x00000000}, - {0x000d0000, 0x00000001}, -}; - -/* P1 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp1_cfg[] = { - {0x000d0000, 0x00000000}, - {0x00054000, 0x00000000}, - {0x00054001, 0x00000000}, - {0x00054002, 0x00000101}, - {0x00054003, 0x00000190}, - {0x00054004, 0x00000002}, - {0x00054005, 0x00000000}, - {0x00054006, 0x00000011}, - {0x00054007, 0x00000000}, - {0x00054008, 0x0000121f}, - {0x00054009, 0x000000c8}, - {0x0005400a, 0x00000000}, - {0x0005400b, 0x00000002}, - {0x0005400c, 0x00000000}, - {0x0005400d, 0x00000000}, - {0x0005400e, 0x00000000}, - {0x0005400f, 0x00000100}, - {0x00054010, 0x00000000}, - {0x00054011, 0x00000000}, - {0x00054012, 0x00000310}, - {0x00054013, 0x00000000}, - {0x00054014, 0x00000000}, - {0x00054015, 0x00000000}, - {0x00054016, 0x00000000}, - {0x00054017, 0x00000000}, - {0x00054018, 0x00000000}, - {0x00054019, 0x00000084}, - {0x0005401a, 0x00000031}, - {0x0005401b, 0x00004d66}, - {0x0005401c, 0x00004a00}, - {0x0005401d, 0x00000000}, - {0x0005401e, 0x00000016}, - {0x0005401f, 0x00000084}, - {0x00054020, 0x00000031}, - {0x00054021, 0x00004d66}, - {0x00054022, 0x00004a00}, - {0x00054023, 0x00000000}, - {0x00054024, 0x0000002e}, - {0x00054025, 0x00000000}, - {0x00054026, 0x00000000}, - {0x00054027, 0x00000000}, - {0x00054028, 0x00000000}, - {0x00054029, 0x00000000}, - {0x0005402a, 0x00000000}, - {0x0005402b, 0x00000000}, - {0x0005402c, 0x00000000}, - {0x0005402d, 0x00000000}, - {0x0005402e, 0x00000000}, - {0x0005402f, 0x00000000}, - {0x00054030, 0x00000000}, - {0x00054031, 0x00000000}, - {0x00054032, 0x00008400}, - {0x00054033, 0x00003100}, - {0x00054034, 0x00006600}, - {0x00054035, 0x0000004d}, - {0x00054036, 0x0000004a}, - {0x00054037, 0x00001600}, - {0x00054038, 0x00008400}, - {0x00054039, 0x00003100}, - {0x0005403a, 0x00006600}, - {0x0005403b, 0x0000004d}, - {0x0005403c, 0x0000004a}, - {0x0005403d, 0x00002e00}, - {0x0005403e, 0x00000000}, - {0x0005403f, 0x00000000}, - {0x00054040, 0x00000000}, - {0x00054041, 0x00000000}, - {0x00054042, 0x00000000}, - {0x00054043, 0x00000000}, - {0x00054044, 0x00000000}, - {0x000d0000, 0x00000001}, -}; - -/* P2 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp2_cfg[] = { - {0x000d0000, 0x00000000}, - {0x00054000, 0x00000000}, - {0x00054001, 0x00000000}, - {0x00054002, 0x00000102}, - {0x00054003, 0x00000064}, - {0x00054004, 0x00000002}, - {0x00054005, 0x00000000}, - {0x00054006, 0x00000011}, - {0x00054007, 0x00000000}, - {0x00054008, 0x0000121f}, - {0x00054009, 0x000000c8}, - {0x0005400a, 0x00000000}, - {0x0005400b, 0x00000002}, - {0x0005400c, 0x00000000}, - {0x0005400d, 0x00000000}, - {0x0005400e, 0x00000000}, - {0x0005400f, 0x00000100}, - {0x00054010, 0x00000000}, - {0x00054011, 0x00000000}, - {0x00054012, 0x00000310}, - {0x00054013, 0x00000000}, - {0x00054014, 0x00000000}, - {0x00054015, 0x00000000}, - {0x00054016, 0x00000000}, - {0x00054017, 0x00000000}, - {0x00054018, 0x00000000}, - {0x00054019, 0x00000084}, - {0x0005401a, 0x00000031}, - {0x0005401b, 0x00004d66}, - {0x0005401c, 0x00004a00}, - {0x0005401d, 0x00000000}, - {0x0005401e, 0x00000016}, - {0x0005401f, 0x00000084}, - {0x00054020, 0x00000031}, - {0x00054021, 0x00004d66}, - {0x00054022, 0x00004a00}, - {0x00054023, 0x00000000}, - {0x00054024, 0x0000002e}, - {0x00054025, 0x00000000}, - {0x00054026, 0x00000000}, - {0x00054027, 0x00000000}, - {0x00054028, 0x00000000}, - {0x00054029, 0x00000000}, - {0x0005402a, 0x00000000}, - {0x0005402b, 0x00000000}, - {0x0005402c, 0x00000000}, - {0x0005402d, 0x00000000}, - {0x0005402e, 0x00000000}, - {0x0005402f, 0x00000000}, - {0x00054030, 0x00000000}, - {0x00054031, 0x00000000}, - {0x00054032, 0x00008400}, - {0x00054033, 0x00003100}, - {0x00054034, 0x00006600}, - {0x00054035, 0x0000004d}, - {0x00054036, 0x0000004a}, - {0x00054037, 0x00001600}, - {0x00054038, 0x00008400}, - {0x00054039, 0x00003100}, - {0x0005403a, 0x00006600}, - {0x0005403b, 0x0000004d}, - {0x0005403c, 0x0000004a}, - {0x0005403d, 0x00002e00}, - {0x0005403e, 0x00000000}, - {0x0005403f, 0x00000000}, - {0x00054040, 0x00000000}, - {0x00054041, 0x00000000}, - {0x00054042, 0x00000000}, - {0x00054043, 0x00000000}, - {0x00054044, 0x00000000}, - {0x000d0000, 0x00000001}, -}; - -/* P0 2D message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - {0x000d0000, 0x00000000}, - {0x00054000, 0x00000000}, - {0x00054001, 0x00000000}, - {0x00054002, 0x00000000}, - {0x00054003, 0x00000c80}, - {0x00054004, 0x00000002}, - {0x00054005, 0x00000000}, - {0x00054006, 0x00000011}, - {0x00054007, 0x00000000}, - {0x00054008, 0x00000061}, - {0x00054009, 0x000000c8}, - {0x0005400a, 0x00000000}, - {0x0005400b, 0x00000002}, - {0x0005400c, 0x00000000}, - {0x0005400d, 0x00000000}, - {0x0005400e, 0x00000000}, - {0x0005400f, 0x00000100}, - {0x00054010, 0x00001f7f}, - {0x00054011, 0x00000000}, - {0x00054012, 0x00000310}, - {0x00054013, 0x00000000}, - {0x00054014, 0x00000000}, - {0x00054015, 0x00000000}, - {0x00054016, 0x00000000}, - {0x00054017, 0x00000000}, - {0x00054018, 0x00000000}, - {0x00054019, 0x00002dd4}, - {0x0005401a, 0x00000031}, - {0x0005401b, 0x00004d66}, - {0x0005401c, 0x00004a00}, - {0x0005401d, 0x00000000}, - {0x0005401e, 0x00000016}, - {0x0005401f, 0x00002dd4}, - {0x00054020, 0x00000031}, - {0x00054021, 0x00004d66}, - {0x00054022, 0x00004a00}, - {0x00054023, 0x00000000}, - {0x00054024, 0x0000002e}, - {0x00054025, 0x00000000}, - {0x00054026, 0x00000000}, - {0x00054027, 0x00000000}, - {0x00054028, 0x00000000}, - {0x00054029, 0x00000000}, - {0x0005402a, 0x00000000}, - {0x0005402b, 0x00000000}, - {0x0005402c, 0x00000000}, - {0x0005402d, 0x00000000}, - {0x0005402e, 0x00000000}, - {0x0005402f, 0x00000000}, - {0x00054030, 0x00000000}, - {0x00054031, 0x00000000}, - {0x00054032, 0x0000d400}, - {0x00054033, 0x0000312d}, - {0x00054034, 0x00006600}, - {0x00054035, 0x0000004d}, - {0x00054036, 0x0000004a}, - {0x00054037, 0x00001600}, - {0x00054038, 0x0000d400}, - {0x00054039, 0x0000312d}, - {0x0005403a, 0x00006600}, - {0x0005403b, 0x0000004d}, - {0x0005403c, 0x0000004a}, - {0x0005403d, 0x00002e00}, - {0x0005403e, 0x00000000}, - {0x0005403f, 0x00000000}, - {0x00054040, 0x00000000}, - {0x00054041, 0x00000000}, - {0x00054042, 0x00000000}, - {0x00054043, 0x00000000}, - {0x00054044, 0x00000000}, - {0x000d0000, 0x00000001}, -}; - -/* DRAM PHY init engine image */ -struct dram_cfg_param ddr_phy_pie[] = { - {0xd0000, 0x0}, - {0x90000, 0x10}, - {0x90001, 0x400}, - {0x90002, 0x10e}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x8}, - {0x90029, 0xb}, - {0x9002a, 0x480}, - {0x9002b, 0x109}, - {0x9002c, 0x8}, - {0x9002d, 0x448}, - {0x9002e, 0x139}, - {0x9002f, 0x8}, - {0x90030, 0x478}, - {0x90031, 0x109}, - {0x90032, 0x0}, - {0x90033, 0xe8}, - {0x90034, 0x109}, - {0x90035, 0x2}, - {0x90036, 0x10}, - {0x90037, 0x139}, - {0x90038, 0xb}, - {0x90039, 0x7c0}, - {0x9003a, 0x139}, - {0x9003b, 0x44}, - {0x9003c, 0x633}, - {0x9003d, 0x159}, - {0x9003e, 0x14f}, - {0x9003f, 0x630}, - {0x90040, 0x159}, - {0x90041, 0x47}, - {0x90042, 0x633}, - {0x90043, 0x149}, - {0x90044, 0x4f}, - {0x90045, 0x633}, - {0x90046, 0x179}, - {0x90047, 0x8}, - {0x90048, 0xe0}, - {0x90049, 0x109}, - {0x9004a, 0x0}, - {0x9004b, 0x7c8}, - {0x9004c, 0x109}, - {0x9004d, 0x0}, - {0x9004e, 0x1}, - {0x9004f, 0x8}, - {0x90050, 0x0}, - {0x90051, 0x45a}, - {0x90052, 0x9}, - {0x90053, 0x0}, - {0x90054, 0x448}, - {0x90055, 0x109}, - {0x90056, 0x40}, - {0x90057, 0x633}, - {0x90058, 0x179}, - {0x90059, 0x1}, - {0x9005a, 0x618}, - {0x9005b, 0x109}, - {0x9005c, 0x40c0}, - {0x9005d, 0x633}, - {0x9005e, 0x149}, - {0x9005f, 0x8}, - {0x90060, 0x4}, - {0x90061, 0x48}, - {0x90062, 0x4040}, - {0x90063, 0x633}, - {0x90064, 0x149}, - {0x90065, 0x0}, - {0x90066, 0x4}, - {0x90067, 0x48}, - {0x90068, 0x40}, - {0x90069, 0x633}, - {0x9006a, 0x149}, - {0x9006b, 0x10}, - {0x9006c, 0x4}, - {0x9006d, 0x18}, - {0x9006e, 0x0}, - {0x9006f, 0x4}, - {0x90070, 0x78}, - {0x90071, 0x549}, - {0x90072, 0x633}, - {0x90073, 0x159}, - {0x90074, 0xd49}, - {0x90075, 0x633}, - {0x90076, 0x159}, - {0x90077, 0x94a}, - {0x90078, 0x633}, - {0x90079, 0x159}, - {0x9007a, 0x441}, - {0x9007b, 0x633}, - {0x9007c, 0x149}, - {0x9007d, 0x42}, - {0x9007e, 0x633}, - {0x9007f, 0x149}, - {0x90080, 0x1}, - {0x90081, 0x633}, - {0x90082, 0x149}, - {0x90083, 0x0}, - {0x90084, 0xe0}, - {0x90085, 0x109}, - {0x90086, 0xa}, - {0x90087, 0x10}, - {0x90088, 0x109}, - {0x90089, 0x9}, - {0x9008a, 0x3c0}, - {0x9008b, 0x149}, - {0x9008c, 0x9}, - {0x9008d, 0x3c0}, - {0x9008e, 0x159}, - {0x9008f, 0x18}, - {0x90090, 0x10}, - {0x90091, 0x109}, - {0x90092, 0x0}, - {0x90093, 0x3c0}, - {0x90094, 0x109}, - {0x90095, 0x18}, - {0x90096, 0x4}, - {0x90097, 0x48}, - {0x90098, 0x18}, - {0x90099, 0x4}, - {0x9009a, 0x58}, - {0x9009b, 0xb}, - {0x9009c, 0x10}, - {0x9009d, 0x109}, - {0x9009e, 0x1}, - {0x9009f, 0x10}, - {0x900a0, 0x109}, - {0x900a1, 0x5}, - {0x900a2, 0x7c0}, - {0x900a3, 0x109}, - {0x40000, 0x811}, - {0x40020, 0x880}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x4008}, - {0x40021, 0x83}, - {0x40041, 0x4f}, - {0x40061, 0x0}, - {0x40002, 0x4040}, - {0x40022, 0x83}, - {0x40042, 0x51}, - {0x40062, 0x0}, - {0x40003, 0x811}, - {0x40023, 0x880}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x720}, - {0x40024, 0xf}, - {0x40044, 0x1740}, - {0x40064, 0x0}, - {0x40005, 0x16}, - {0x40025, 0x83}, - {0x40045, 0x4b}, - {0x40065, 0x0}, - {0x40006, 0x716}, - {0x40026, 0xf}, - {0x40046, 0x2001}, - {0x40066, 0x0}, - {0x40007, 0x716}, - {0x40027, 0xf}, - {0x40047, 0x2800}, - {0x40067, 0x0}, - {0x40008, 0x716}, - {0x40028, 0xf}, - {0x40048, 0xf00}, - {0x40068, 0x0}, - {0x40009, 0x720}, - {0x40029, 0xf}, - {0x40049, 0x1400}, - {0x40069, 0x0}, - {0x4000a, 0xe08}, - {0x4002a, 0xc15}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x625}, - {0x4002b, 0x15}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x4028}, - {0x4002c, 0x80}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0xe08}, - {0x4002d, 0xc1a}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x625}, - {0x4002e, 0x1a}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x4040}, - {0x4002f, 0x80}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x2604}, - {0x40030, 0x15}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x708}, - {0x40031, 0x5}, - {0x40051, 0x0}, - {0x40071, 0x2002}, - {0x40012, 0x8}, - {0x40032, 0x80}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x2604}, - {0x40033, 0x1a}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x708}, - {0x40034, 0xa}, - {0x40054, 0x0}, - {0x40074, 0x2002}, - {0x40015, 0x4040}, - {0x40035, 0x80}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x60a}, - {0x40036, 0x15}, - {0x40056, 0x1200}, - {0x40076, 0x0}, - {0x40017, 0x61a}, - {0x40037, 0x15}, - {0x40057, 0x1300}, - {0x40077, 0x0}, - {0x40018, 0x60a}, - {0x40038, 0x1a}, - {0x40058, 0x1200}, - {0x40078, 0x0}, - {0x40019, 0x642}, - {0x40039, 0x1a}, - {0x40059, 0x1300}, - {0x40079, 0x0}, - {0x4001a, 0x4808}, - {0x4003a, 0x880}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900a4, 0x0}, - {0x900a5, 0x790}, - {0x900a6, 0x11a}, - {0x900a7, 0x8}, - {0x900a8, 0x7aa}, - {0x900a9, 0x2a}, - {0x900aa, 0x10}, - {0x900ab, 0x7b2}, - {0x900ac, 0x2a}, - {0x900ad, 0x0}, - {0x900ae, 0x7c8}, - {0x900af, 0x109}, - {0x900b0, 0x10}, - {0x900b1, 0x10}, - {0x900b2, 0x109}, - {0x900b3, 0x10}, - {0x900b4, 0x2a8}, - {0x900b5, 0x129}, - {0x900b6, 0x8}, - {0x900b7, 0x370}, - {0x900b8, 0x129}, - {0x900b9, 0xa}, - {0x900ba, 0x3c8}, - {0x900bb, 0x1a9}, - {0x900bc, 0xc}, - {0x900bd, 0x408}, - {0x900be, 0x199}, - {0x900bf, 0x14}, - {0x900c0, 0x790}, - {0x900c1, 0x11a}, - {0x900c2, 0x8}, - {0x900c3, 0x4}, - {0x900c4, 0x18}, - {0x900c5, 0xe}, - {0x900c6, 0x408}, - {0x900c7, 0x199}, - {0x900c8, 0x8}, - {0x900c9, 0x8568}, - {0x900ca, 0x108}, - {0x900cb, 0x18}, - {0x900cc, 0x790}, - {0x900cd, 0x16a}, - {0x900ce, 0x8}, - {0x900cf, 0x1d8}, - {0x900d0, 0x169}, - {0x900d1, 0x10}, - {0x900d2, 0x8558}, - {0x900d3, 0x168}, - {0x900d4, 0x70}, - {0x900d5, 0x788}, - {0x900d6, 0x16a}, - {0x900d7, 0x1ff8}, - {0x900d8, 0x85a8}, - {0x900d9, 0x1e8}, - {0x900da, 0x50}, - {0x900db, 0x798}, - {0x900dc, 0x16a}, - {0x900dd, 0x60}, - {0x900de, 0x7a0}, - {0x900df, 0x16a}, - {0x900e0, 0x8}, - {0x900e1, 0x8310}, - {0x900e2, 0x168}, - {0x900e3, 0x8}, - {0x900e4, 0xa310}, - {0x900e5, 0x168}, - {0x900e6, 0xa}, - {0x900e7, 0x408}, - {0x900e8, 0x169}, - {0x900e9, 0x6e}, - {0x900ea, 0x0}, - {0x900eb, 0x68}, - {0x900ec, 0x0}, - {0x900ed, 0x408}, - {0x900ee, 0x169}, - {0x900ef, 0x0}, - {0x900f0, 0x8310}, - {0x900f1, 0x168}, - {0x900f2, 0x0}, - {0x900f3, 0xa310}, - {0x900f4, 0x168}, - {0x900f5, 0x1ff8}, - {0x900f6, 0x85a8}, - {0x900f7, 0x1e8}, - {0x900f8, 0x68}, - {0x900f9, 0x798}, - {0x900fa, 0x16a}, - {0x900fb, 0x78}, - {0x900fc, 0x7a0}, - {0x900fd, 0x16a}, - {0x900fe, 0x68}, - {0x900ff, 0x790}, - {0x90100, 0x16a}, - {0x90101, 0x8}, - {0x90102, 0x8b10}, - {0x90103, 0x168}, - {0x90104, 0x8}, - {0x90105, 0xab10}, - {0x90106, 0x168}, - {0x90107, 0xa}, - {0x90108, 0x408}, - {0x90109, 0x169}, - {0x9010a, 0x58}, - {0x9010b, 0x0}, - {0x9010c, 0x68}, - {0x9010d, 0x0}, - {0x9010e, 0x408}, - {0x9010f, 0x169}, - {0x90110, 0x0}, - {0x90111, 0x8b10}, - {0x90112, 0x168}, - {0x90113, 0x1}, - {0x90114, 0xab10}, - {0x90115, 0x168}, - {0x90116, 0x0}, - {0x90117, 0x1d8}, - {0x90118, 0x169}, - {0x90119, 0x80}, - {0x9011a, 0x790}, - {0x9011b, 0x16a}, - {0x9011c, 0x18}, - {0x9011d, 0x7aa}, - {0x9011e, 0x6a}, - {0x9011f, 0xa}, - {0x90120, 0x0}, - {0x90121, 0x1e9}, - {0x90122, 0x8}, - {0x90123, 0x8080}, - {0x90124, 0x108}, - {0x90125, 0xf}, - {0x90126, 0x408}, - {0x90127, 0x169}, - {0x90128, 0xc}, - {0x90129, 0x0}, - {0x9012a, 0x68}, - {0x9012b, 0x9}, - {0x9012c, 0x0}, - {0x9012d, 0x1a9}, - {0x9012e, 0x0}, - {0x9012f, 0x408}, - {0x90130, 0x169}, - {0x90131, 0x0}, - {0x90132, 0x8080}, - {0x90133, 0x108}, - {0x90134, 0x8}, - {0x90135, 0x7aa}, - {0x90136, 0x6a}, - {0x90137, 0x0}, - {0x90138, 0x8568}, - {0x90139, 0x108}, - {0x9013a, 0xb7}, - {0x9013b, 0x790}, - {0x9013c, 0x16a}, - {0x9013d, 0x1f}, - {0x9013e, 0x0}, - {0x9013f, 0x68}, - {0x90140, 0x8}, - {0x90141, 0x8558}, - {0x90142, 0x168}, - {0x90143, 0xf}, - {0x90144, 0x408}, - {0x90145, 0x169}, - {0x90146, 0xd}, - {0x90147, 0x0}, - {0x90148, 0x68}, - {0x90149, 0x0}, - {0x9014a, 0x408}, - {0x9014b, 0x169}, - {0x9014c, 0x0}, - {0x9014d, 0x8558}, - {0x9014e, 0x168}, - {0x9014f, 0x8}, - {0x90150, 0x3c8}, - {0x90151, 0x1a9}, - {0x90152, 0x3}, - {0x90153, 0x370}, - {0x90154, 0x129}, - {0x90155, 0x20}, - {0x90156, 0x2aa}, - {0x90157, 0x9}, - {0x90158, 0x0}, - {0x90159, 0x400}, - {0x9015a, 0x10e}, - {0x9015b, 0x8}, - {0x9015c, 0xe8}, - {0x9015d, 0x109}, - {0x9015e, 0x0}, - {0x9015f, 0x8140}, - {0x90160, 0x10c}, - {0x90161, 0x10}, - {0x90162, 0x8138}, - {0x90163, 0x10c}, - {0x90164, 0x8}, - {0x90165, 0x7c8}, - {0x90166, 0x101}, - {0x90167, 0x8}, - {0x90168, 0x448}, - {0x90169, 0x109}, - {0x9016a, 0xf}, - {0x9016b, 0x7c0}, - {0x9016c, 0x109}, - {0x9016d, 0x0}, - {0x9016e, 0xe8}, - {0x9016f, 0x109}, - {0x90170, 0x47}, - {0x90171, 0x630}, - {0x90172, 0x109}, - {0x90173, 0x8}, - {0x90174, 0x618}, - {0x90175, 0x109}, - {0x90176, 0x8}, - {0x90177, 0xe0}, - {0x90178, 0x109}, - {0x90179, 0x0}, - {0x9017a, 0x7c8}, - {0x9017b, 0x109}, - {0x9017c, 0x8}, - {0x9017d, 0x8140}, - {0x9017e, 0x10c}, - {0x9017f, 0x0}, - {0x90180, 0x1}, - {0x90181, 0x8}, - {0x90182, 0x8}, - {0x90183, 0x4}, - {0x90184, 0x8}, - {0x90185, 0x8}, - {0x90186, 0x7c8}, - {0x90187, 0x101}, - {0x90006, 0x0}, - {0x90007, 0x0}, - {0x90008, 0x8}, - {0x90009, 0x0}, - {0x9000a, 0x0}, - {0x9000b, 0x0}, - {0xd00e7, 0x400}, - {0x90017, 0x0}, - {0x9001f, 0x29}, - {0x90026, 0x6a}, - {0x400d0, 0x0}, - {0x400d1, 0x101}, - {0x400d2, 0x105}, - {0x400d3, 0x107}, - {0x400d4, 0x10f}, - {0x400d5, 0x202}, - {0x400d6, 0x20a}, - {0x400d7, 0x20b}, - {0x2003a, 0x2}, - {0x2000b, 0x64}, - {0x2000c, 0xc8}, - {0x2000d, 0x7d0}, - {0x2000e, 0x2c}, - {0x12000b, 0xc}, - {0x12000c, 0x19}, - {0x12000d, 0xfa}, - {0x12000e, 0x10}, - {0x22000b, 0x3}, - {0x22000c, 0x6}, - {0x22000d, 0x3e}, - {0x22000e, 0x10}, - {0x9000c, 0x0}, - {0x9000d, 0x173}, - {0x9000e, 0x60}, - {0x9000f, 0x6110}, - {0x90010, 0x2152}, - {0x90011, 0xdfbd}, - {0x90012, 0x2060}, - {0x90013, 0x6152}, - {0x20010, 0x5a}, - {0x20011, 0x3}, - {0x40080, 0xe0}, - {0x40081, 0x12}, - {0x40082, 0xe0}, - {0x40083, 0x12}, - {0x40084, 0xe0}, - {0x40085, 0x12}, - {0x140080, 0xe0}, - {0x140081, 0x12}, - {0x140082, 0xe0}, - {0x140083, 0x12}, - {0x140084, 0xe0}, - {0x140085, 0x12}, - {0x240080, 0xe0}, - {0x240081, 0x12}, - {0x240082, 0xe0}, - {0x240083, 0x12}, - {0x240084, 0xe0}, - {0x240085, 0x12}, - {0x400fd, 0xf}, - {0x10011, 0x1}, - {0x10012, 0x1}, - {0x10013, 0x180}, - {0x10018, 0x1}, - {0x10002, 0x6209}, - {0x100b2, 0x1}, - {0x101b4, 0x1}, - {0x102b4, 0x1}, - {0x103b4, 0x1}, - {0x104b4, 0x1}, - {0x105b4, 0x1}, - {0x106b4, 0x1}, - {0x107b4, 0x1}, - {0x108b4, 0x1}, - {0x11011, 0x1}, - {0x11012, 0x1}, - {0x11013, 0x180}, - {0x11018, 0x1}, - {0x11002, 0x6209}, - {0x110b2, 0x1}, - {0x111b4, 0x1}, - {0x112b4, 0x1}, - {0x113b4, 0x1}, - {0x114b4, 0x1}, - {0x115b4, 0x1}, - {0x116b4, 0x1}, - {0x117b4, 0x1}, - {0x118b4, 0x1}, - {0x20089, 0x1}, - {0x20088, 0x19}, - {0xc0080, 0x2}, - {0xd0000, 0x1}, -}; - -struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 3200mts 1D */ - .drate = 3200, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 400mts 1D */ - .drate = 400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 100mts 1D */ - .drate = 100, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 3200mts 2D */ - .drate = 3200, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3200, 400, 100, }, -}; diff --git a/board/freescale/imx8mn_evk/lpddr4_timing_ld.c b/board/freescale/imx8mn_evk/lpddr4_timing_ld.c deleted file mode 100644 index aa23c350945..00000000000 --- a/board/freescale/imx8mn_evk/lpddr4_timing_ld.c +++ /dev/null @@ -1,1440 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 NXP - * - * Generated code from MX8M_DDR_tool - * Align with uboot version: - * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga - */ - -#include -#include - -struct dram_cfg_param ddr_ddrc_cfg[] = { - /** Initialize DDRC registers **/ - { 0x3d400304, 0x1 }, - { 0x3d400030, 0x1 }, - { 0x3d400000, 0xa3080020 }, - { 0x3d400020, 0x111 }, - { 0x3d400024, 0x1f400 }, - { 0x3d400064, 0x300070 }, - { 0x3d4000d0, 0xc002030f }, - { 0x3d4000d4, 0x500000 }, - { 0x3d4000dc, 0xa40012 }, - { 0x3d4000e0, 0x310000 }, - { 0x3d4000e8, 0x66004d }, - { 0x3d4000ec, 0x16004d }, - { 0x3d400100, 0x10100d11 }, - { 0x3d400104, 0x3041a }, - { 0x3d40010c, 0x606000 }, - { 0x3d400110, 0x8040408 }, - { 0x3d400114, 0x2030606 }, - { 0x3d400118, 0x1010004 }, - { 0x3d40011c, 0x301 }, - { 0x3d400130, 0x20300 }, - { 0x3d400134, 0xa100002 }, - { 0x3d400138, 0x73 }, - { 0x3d400144, 0x500028 }, - { 0x3d400180, 0x190000c }, - { 0x3d400184, 0x14030d4 }, - { 0x3d400188, 0x0 }, - { 0x3d400190, 0x4898204 }, - { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x904 }, - { 0x3d4001a0, 0xe0400018 }, - { 0x3d4001a4, 0xdf00e4 }, - { 0x3d4001a8, 0x80000000 }, - { 0x3d4001b0, 0x11 }, - { 0x3d4001c0, 0x1 }, - { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x4070f0f }, - { 0x3d400200, 0x17 }, - { 0x3d40020c, 0x0 }, - { 0x3d400210, 0x1f1f }, - { 0x3d400204, 0x80808 }, - { 0x3d400214, 0x7070707 }, - { 0x3d400218, 0x7070707 }, - { 0x3d400250, 0x29001701 }, - { 0x3d400254, 0x2c }, - { 0x3d40025c, 0x4000030 }, - { 0x3d400264, 0x900093e7 }, - { 0x3d40026c, 0x2005574 }, - { 0x3d400400, 0x111 }, - { 0x3d400408, 0x72ff }, - { 0x3d400494, 0x2100e07 }, - { 0x3d400498, 0x620096 }, - { 0x3d40049c, 0x1100e07 }, - { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x11 }, - { 0x3d402024, 0x7d00 }, - { 0x3d402050, 0x20d040 }, - { 0x3d402064, 0xc001c }, - { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0x310000 }, - { 0x3d4020e8, 0x66004d }, - { 0x3d4020ec, 0x16004d }, - { 0x3d402100, 0xa040305 }, - { 0x3d402104, 0x30407 }, - { 0x3d402108, 0x203060b }, - { 0x3d40210c, 0x505000 }, - { 0x3d402110, 0x2040202 }, - { 0x3d402114, 0x2030202 }, - { 0x3d402118, 0x1010004 }, - { 0x3d40211c, 0x301 }, - { 0x3d402130, 0x20300 }, - { 0x3d402134, 0xa100002 }, - { 0x3d402138, 0x1d }, - { 0x3d402144, 0x14000a }, - { 0x3d402180, 0x640004 }, - { 0x3d402190, 0x3818200 }, - { 0x3d402194, 0x80303 }, - { 0x3d4021b4, 0x100 }, - { 0x3d4020f4, 0xc99 }, - { 0x3d403020, 0x11 }, - { 0x3d403024, 0x1f40 }, - { 0x3d403050, 0x20d040 }, - { 0x3d403064, 0x30007 }, - { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0x310000 }, - { 0x3d4030e8, 0x66004d }, - { 0x3d4030ec, 0x16004d }, - { 0x3d403100, 0xa010102 }, - { 0x3d403104, 0x30404 }, - { 0x3d403108, 0x203060b }, - { 0x3d40310c, 0x505000 }, - { 0x3d403110, 0x2040202 }, - { 0x3d403114, 0x2030202 }, - { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x301 }, - { 0x3d403130, 0x20300 }, - { 0x3d403134, 0xa100002 }, - { 0x3d403138, 0x8 }, - { 0x3d403144, 0x50003 }, - { 0x3d403180, 0x190004 }, - { 0x3d403190, 0x3818200 }, - { 0x3d403194, 0x80303 }, - { 0x3d4031b4, 0x100 }, - { 0x3d4030f4, 0xc99 }, - { 0x3d400028, 0x0 }, -}; - -/* PHY Initialize Configuration */ -struct dram_cfg_param ddr_ddrphy_cfg[] = { - { 0x100a0, 0x0 }, - { 0x100a1, 0x1 }, - { 0x100a2, 0x2 }, - { 0x100a3, 0x3 }, - { 0x100a4, 0x4 }, - { 0x100a5, 0x5 }, - { 0x100a6, 0x6 }, - { 0x100a7, 0x7 }, - { 0x110a0, 0x0 }, - { 0x110a1, 0x1 }, - { 0x110a2, 0x3 }, - { 0x110a3, 0x4 }, - { 0x110a4, 0x5 }, - { 0x110a5, 0x2 }, - { 0x110a6, 0x7 }, - { 0x110a7, 0x6 }, - { 0x1005f, 0x1ff }, - { 0x1015f, 0x1ff }, - { 0x1105f, 0x1ff }, - { 0x1115f, 0x1ff }, - { 0x11005f, 0x1ff }, - { 0x11015f, 0x1ff }, - { 0x11105f, 0x1ff }, - { 0x11115f, 0x1ff }, - { 0x21005f, 0x1ff }, - { 0x21015f, 0x1ff }, - { 0x21105f, 0x1ff }, - { 0x21115f, 0x1ff }, - { 0x55, 0x1ff }, - { 0x1055, 0x1ff }, - { 0x2055, 0x1ff }, - { 0x3055, 0x1ff }, - { 0x4055, 0x1ff }, - { 0x5055, 0x1ff }, - { 0x6055, 0x1ff }, - { 0x7055, 0x1ff }, - { 0x8055, 0x1ff }, - { 0x9055, 0x1ff }, - { 0x200c5, 0xb }, - { 0x1200c5, 0x7 }, - { 0x2200c5, 0x7 }, - { 0x2002e, 0x1 }, - { 0x12002e, 0x2 }, - { 0x22002e, 0x2 }, - { 0x90204, 0x0 }, - { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - { 0x20024, 0x1a3 }, - { 0x2003a, 0x2 }, - { 0x120024, 0x1a3 }, - { 0x2003a, 0x2 }, - { 0x220024, 0x1a3 }, - { 0x2003a, 0x2 }, - { 0x20056, 0x3 }, - { 0x120056, 0x3 }, - { 0x220056, 0x3 }, - { 0x1004d, 0xe00 }, - { 0x1014d, 0xe00 }, - { 0x1104d, 0xe00 }, - { 0x1114d, 0xe00 }, - { 0x11004d, 0xe00 }, - { 0x11014d, 0xe00 }, - { 0x11104d, 0xe00 }, - { 0x11114d, 0xe00 }, - { 0x21004d, 0xe00 }, - { 0x21014d, 0xe00 }, - { 0x21104d, 0xe00 }, - { 0x21114d, 0xe00 }, - { 0x10049, 0xeba }, - { 0x10149, 0xeba }, - { 0x11049, 0xeba }, - { 0x11149, 0xeba }, - { 0x110049, 0xeba }, - { 0x110149, 0xeba }, - { 0x111049, 0xeba }, - { 0x111149, 0xeba }, - { 0x210049, 0xeba }, - { 0x210149, 0xeba }, - { 0x211049, 0xeba }, - { 0x211149, 0xeba }, - { 0x43, 0x63 }, - { 0x1043, 0x63 }, - { 0x2043, 0x63 }, - { 0x3043, 0x63 }, - { 0x4043, 0x63 }, - { 0x5043, 0x63 }, - { 0x6043, 0x63 }, - { 0x7043, 0x63 }, - { 0x8043, 0x63 }, - { 0x9043, 0x63 }, - { 0x20018, 0x1 }, - { 0x20075, 0x4 }, - { 0x20050, 0x0 }, - { 0x20008, 0x190 }, - { 0x120008, 0x64 }, - { 0x220008, 0x19 }, - { 0x20088, 0x9 }, - { 0x200b2, 0xdc }, - { 0x10043, 0x5a1 }, - { 0x10143, 0x5a1 }, - { 0x11043, 0x5a1 }, - { 0x11143, 0x5a1 }, - { 0x1200b2, 0xdc }, - { 0x110043, 0x5a1 }, - { 0x110143, 0x5a1 }, - { 0x111043, 0x5a1 }, - { 0x111143, 0x5a1 }, - { 0x2200b2, 0xdc }, - { 0x210043, 0x5a1 }, - { 0x210143, 0x5a1 }, - { 0x211043, 0x5a1 }, - { 0x211143, 0x5a1 }, - { 0x200fa, 0x1 }, - { 0x1200fa, 0x1 }, - { 0x2200fa, 0x1 }, - { 0x20019, 0x1 }, - { 0x120019, 0x1 }, - { 0x220019, 0x1 }, - { 0x200f0, 0x660 }, - { 0x200f1, 0x0 }, - { 0x200f2, 0x4444 }, - { 0x200f3, 0x8888 }, - { 0x200f4, 0x5665 }, - { 0x200f5, 0x0 }, - { 0x200f6, 0x0 }, - { 0x200f7, 0xf000 }, - { 0x20025, 0x0 }, - { 0x2002d, 0x0 }, - { 0x12002d, 0x0 }, - { 0x22002d, 0x0 }, - { 0x2005b, 0x7529 }, - { 0x2005c, 0x0 }, - { 0x200c7, 0x21 }, - { 0x200ca, 0x24 }, - { 0x200cc, 0x1f7 }, - { 0x1200c7, 0x21 }, - { 0x1200ca, 0x24 }, - { 0x1200cc, 0x1f7 }, - { 0x2200c7, 0x21 }, - { 0x2200ca, 0x24 }, - { 0x2200cc, 0x1f7 }, - { 0x2007d, 0x212 }, - { 0x12007d, 0x212 }, - { 0x22007d, 0x212 }, - { 0x2007c, 0x61 }, - { 0x12007c, 0x61 }, - { 0x22007c, 0x61 }, - { 0x1004a, 0x500 }, - { 0x1104a, 0x500 }, - { 0x2002c, 0x0 }, -}; - -/* ddr phy trained csr */ -struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - {0x0200b2, 0x0}, - {0x1200b2, 0x0}, - {0x2200b2, 0x0}, - {0x0200cb, 0x0}, - {0x010043, 0x0}, - {0x110043, 0x0}, - {0x210043, 0x0}, - {0x010143, 0x0}, - {0x110143, 0x0}, - {0x210143, 0x0}, - {0x011043, 0x0}, - {0x111043, 0x0}, - {0x211043, 0x0}, - {0x011143, 0x0}, - {0x111143, 0x0}, - {0x211143, 0x0}, - {0x000080, 0x0}, - {0x100080, 0x0}, - {0x200080, 0x0}, - {0x001080, 0x0}, - {0x101080, 0x0}, - {0x201080, 0x0}, - {0x002080, 0x0}, - {0x102080, 0x0}, - {0x202080, 0x0}, - {0x003080, 0x0}, - {0x103080, 0x0}, - {0x203080, 0x0}, - {0x004080, 0x0}, - {0x104080, 0x0}, - {0x204080, 0x0}, - {0x005080, 0x0}, - {0x105080, 0x0}, - {0x205080, 0x0}, - {0x006080, 0x0}, - {0x106080, 0x0}, - {0x206080, 0x0}, - {0x007080, 0x0}, - {0x107080, 0x0}, - {0x207080, 0x0}, - {0x008080, 0x0}, - {0x108080, 0x0}, - {0x208080, 0x0}, - {0x009080, 0x0}, - {0x109080, 0x0}, - {0x209080, 0x0}, - {0x010080, 0x0}, - {0x110080, 0x0}, - {0x210080, 0x0}, - {0x010180, 0x0}, - {0x110180, 0x0}, - {0x210180, 0x0}, - {0x011080, 0x0}, - {0x111080, 0x0}, - {0x211080, 0x0}, - {0x011180, 0x0}, - {0x111180, 0x0}, - {0x211180, 0x0}, - {0x010081, 0x0}, - {0x110081, 0x0}, - {0x210081, 0x0}, - {0x010181, 0x0}, - {0x110181, 0x0}, - {0x210181, 0x0}, - {0x011081, 0x0}, - {0x111081, 0x0}, - {0x211081, 0x0}, - {0x011181, 0x0}, - {0x111181, 0x0}, - {0x211181, 0x0}, - {0x0100d0, 0x0}, - {0x1100d0, 0x0}, - {0x2100d0, 0x0}, - {0x0101d0, 0x0}, - {0x1101d0, 0x0}, - {0x2101d0, 0x0}, - {0x0110d0, 0x0}, - {0x1110d0, 0x0}, - {0x2110d0, 0x0}, - {0x0111d0, 0x0}, - {0x1111d0, 0x0}, - {0x2111d0, 0x0}, - {0x0100d1, 0x0}, - {0x1100d1, 0x0}, - {0x2100d1, 0x0}, - {0x0101d1, 0x0}, - {0x1101d1, 0x0}, - {0x2101d1, 0x0}, - {0x0110d1, 0x0}, - {0x1110d1, 0x0}, - {0x2110d1, 0x0}, - {0x0111d1, 0x0}, - {0x1111d1, 0x0}, - {0x2111d1, 0x0}, - {0x010068, 0x0}, - {0x010168, 0x0}, - {0x010268, 0x0}, - {0x010368, 0x0}, - {0x010468, 0x0}, - {0x010568, 0x0}, - {0x010668, 0x0}, - {0x010768, 0x0}, - {0x010868, 0x0}, - {0x011068, 0x0}, - {0x011168, 0x0}, - {0x011268, 0x0}, - {0x011368, 0x0}, - {0x011468, 0x0}, - {0x011568, 0x0}, - {0x011668, 0x0}, - {0x011768, 0x0}, - {0x011868, 0x0}, - {0x010069, 0x0}, - {0x010169, 0x0}, - {0x010269, 0x0}, - {0x010369, 0x0}, - {0x010469, 0x0}, - {0x010569, 0x0}, - {0x010669, 0x0}, - {0x010769, 0x0}, - {0x010869, 0x0}, - {0x011069, 0x0}, - {0x011169, 0x0}, - {0x011269, 0x0}, - {0x011369, 0x0}, - {0x011469, 0x0}, - {0x011569, 0x0}, - {0x011669, 0x0}, - {0x011769, 0x0}, - {0x011869, 0x0}, - {0x01008c, 0x0}, - {0x11008c, 0x0}, - {0x21008c, 0x0}, - {0x01018c, 0x0}, - {0x11018c, 0x0}, - {0x21018c, 0x0}, - {0x01108c, 0x0}, - {0x11108c, 0x0}, - {0x21108c, 0x0}, - {0x01118c, 0x0}, - {0x11118c, 0x0}, - {0x21118c, 0x0}, - {0x01008d, 0x0}, - {0x11008d, 0x0}, - {0x21008d, 0x0}, - {0x01018d, 0x0}, - {0x11018d, 0x0}, - {0x21018d, 0x0}, - {0x01108d, 0x0}, - {0x11108d, 0x0}, - {0x21108d, 0x0}, - {0x01118d, 0x0}, - {0x11118d, 0x0}, - {0x21118d, 0x0}, - {0x0100c0, 0x0}, - {0x1100c0, 0x0}, - {0x2100c0, 0x0}, - {0x0101c0, 0x0}, - {0x1101c0, 0x0}, - {0x2101c0, 0x0}, - {0x0102c0, 0x0}, - {0x1102c0, 0x0}, - {0x2102c0, 0x0}, - {0x0103c0, 0x0}, - {0x1103c0, 0x0}, - {0x2103c0, 0x0}, - {0x0104c0, 0x0}, - {0x1104c0, 0x0}, - {0x2104c0, 0x0}, - {0x0105c0, 0x0}, - {0x1105c0, 0x0}, - {0x2105c0, 0x0}, - {0x0106c0, 0x0}, - {0x1106c0, 0x0}, - {0x2106c0, 0x0}, - {0x0107c0, 0x0}, - {0x1107c0, 0x0}, - {0x2107c0, 0x0}, - {0x0108c0, 0x0}, - {0x1108c0, 0x0}, - {0x2108c0, 0x0}, - {0x0110c0, 0x0}, - {0x1110c0, 0x0}, - {0x2110c0, 0x0}, - {0x0111c0, 0x0}, - {0x1111c0, 0x0}, - {0x2111c0, 0x0}, - {0x0112c0, 0x0}, - {0x1112c0, 0x0}, - {0x2112c0, 0x0}, - {0x0113c0, 0x0}, - {0x1113c0, 0x0}, - {0x2113c0, 0x0}, - {0x0114c0, 0x0}, - {0x1114c0, 0x0}, - {0x2114c0, 0x0}, - {0x0115c0, 0x0}, - {0x1115c0, 0x0}, - {0x2115c0, 0x0}, - {0x0116c0, 0x0}, - {0x1116c0, 0x0}, - {0x2116c0, 0x0}, - {0x0117c0, 0x0}, - {0x1117c0, 0x0}, - {0x2117c0, 0x0}, - {0x0118c0, 0x0}, - {0x1118c0, 0x0}, - {0x2118c0, 0x0}, - {0x0100c1, 0x0}, - {0x1100c1, 0x0}, - {0x2100c1, 0x0}, - {0x0101c1, 0x0}, - {0x1101c1, 0x0}, - {0x2101c1, 0x0}, - {0x0102c1, 0x0}, - {0x1102c1, 0x0}, - {0x2102c1, 0x0}, - {0x0103c1, 0x0}, - {0x1103c1, 0x0}, - {0x2103c1, 0x0}, - {0x0104c1, 0x0}, - {0x1104c1, 0x0}, - {0x2104c1, 0x0}, - {0x0105c1, 0x0}, - {0x1105c1, 0x0}, - {0x2105c1, 0x0}, - {0x0106c1, 0x0}, - {0x1106c1, 0x0}, - {0x2106c1, 0x0}, - {0x0107c1, 0x0}, - {0x1107c1, 0x0}, - {0x2107c1, 0x0}, - {0x0108c1, 0x0}, - {0x1108c1, 0x0}, - {0x2108c1, 0x0}, - {0x0110c1, 0x0}, - {0x1110c1, 0x0}, - {0x2110c1, 0x0}, - {0x0111c1, 0x0}, - {0x1111c1, 0x0}, - {0x2111c1, 0x0}, - {0x0112c1, 0x0}, - {0x1112c1, 0x0}, - {0x2112c1, 0x0}, - {0x0113c1, 0x0}, - {0x1113c1, 0x0}, - {0x2113c1, 0x0}, - {0x0114c1, 0x0}, - {0x1114c1, 0x0}, - {0x2114c1, 0x0}, - {0x0115c1, 0x0}, - {0x1115c1, 0x0}, - {0x2115c1, 0x0}, - {0x0116c1, 0x0}, - {0x1116c1, 0x0}, - {0x2116c1, 0x0}, - {0x0117c1, 0x0}, - {0x1117c1, 0x0}, - {0x2117c1, 0x0}, - {0x0118c1, 0x0}, - {0x1118c1, 0x0}, - {0x2118c1, 0x0}, - {0x010020, 0x0}, - {0x110020, 0x0}, - {0x210020, 0x0}, - {0x011020, 0x0}, - {0x111020, 0x0}, - {0x211020, 0x0}, - {0x020072, 0x0}, - {0x020073, 0x0}, - {0x020074, 0x0}, - {0x0100aa, 0x0}, - {0x0110aa, 0x0}, - {0x020010, 0x0}, - {0x120010, 0x0}, - {0x220010, 0x0}, - {0x020011, 0x0}, - {0x120011, 0x0}, - {0x220011, 0x0}, - {0x0100ae, 0x0}, - {0x1100ae, 0x0}, - {0x2100ae, 0x0}, - {0x0100af, 0x0}, - {0x1100af, 0x0}, - {0x2100af, 0x0}, - {0x0110ae, 0x0}, - {0x1110ae, 0x0}, - {0x2110ae, 0x0}, - {0x0110af, 0x0}, - {0x1110af, 0x0}, - {0x2110af, 0x0}, - {0x020020, 0x0}, - {0x120020, 0x0}, - {0x220020, 0x0}, - {0x0100a0, 0x0}, - {0x0100a1, 0x0}, - {0x0100a2, 0x0}, - {0x0100a3, 0x0}, - {0x0100a4, 0x0}, - {0x0100a5, 0x0}, - {0x0100a6, 0x0}, - {0x0100a7, 0x0}, - {0x0110a0, 0x0}, - {0x0110a1, 0x0}, - {0x0110a2, 0x0}, - {0x0110a3, 0x0}, - {0x0110a4, 0x0}, - {0x0110a5, 0x0}, - {0x0110a6, 0x0}, - {0x0110a7, 0x0}, - {0x02007c, 0x0}, - {0x12007c, 0x0}, - {0x22007c, 0x0}, - {0x02007d, 0x0}, - {0x12007d, 0x0}, - {0x22007d, 0x0}, - {0x0400fd, 0x0}, - {0x0400c0, 0x0}, - {0x090201, 0x0}, - {0x190201, 0x0}, - {0x290201, 0x0}, - {0x090202, 0x0}, - {0x190202, 0x0}, - {0x290202, 0x0}, - {0x090203, 0x0}, - {0x190203, 0x0}, - {0x290203, 0x0}, - {0x090204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x090205, 0x0}, - {0x190205, 0x0}, - {0x290205, 0x0}, - {0x090206, 0x0}, - {0x190206, 0x0}, - {0x290206, 0x0}, - {0x090207, 0x0}, - {0x190207, 0x0}, - {0x290207, 0x0}, - {0x090208, 0x0}, - {0x190208, 0x0}, - {0x290208, 0x0}, - {0x010062, 0x0}, - {0x010162, 0x0}, - {0x010262, 0x0}, - {0x010362, 0x0}, - {0x010462, 0x0}, - {0x010562, 0x0}, - {0x010662, 0x0}, - {0x010762, 0x0}, - {0x010862, 0x0}, - {0x011062, 0x0}, - {0x011162, 0x0}, - {0x011262, 0x0}, - {0x011362, 0x0}, - {0x011462, 0x0}, - {0x011562, 0x0}, - {0x011662, 0x0}, - {0x011762, 0x0}, - {0x011862, 0x0}, - {0x020077, 0x0}, - {0x010001, 0x0}, - {0x011001, 0x0}, - {0x010040, 0x0}, - {0x010140, 0x0}, - {0x010240, 0x0}, - {0x010340, 0x0}, - {0x010440, 0x0}, - {0x010540, 0x0}, - {0x010640, 0x0}, - {0x010740, 0x0}, - {0x010840, 0x0}, - {0x010030, 0x0}, - {0x010130, 0x0}, - {0x010230, 0x0}, - {0x010330, 0x0}, - {0x010430, 0x0}, - {0x010530, 0x0}, - {0x010630, 0x0}, - {0x010730, 0x0}, - {0x010830, 0x0}, - {0x011040, 0x0}, - {0x011140, 0x0}, - {0x011240, 0x0}, - {0x011340, 0x0}, - {0x011440, 0x0}, - {0x011540, 0x0}, - {0x011640, 0x0}, - {0x011740, 0x0}, - {0x011840, 0x0}, - {0x011030, 0x0}, - {0x011130, 0x0}, - {0x011230, 0x0}, - {0x011330, 0x0}, - {0x011430, 0x0}, - {0x011530, 0x0}, - {0x011630, 0x0}, - {0x011730, 0x0}, - {0x011830, 0x0}, -}; - -/* P0 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp0_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0x640 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, - { 0x54008, 0x131f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x310 }, - { 0x54019, 0x12a4 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x12a4 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, - { 0x54032, 0xa400 }, - { 0x54033, 0x3112 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, - { 0x54038, 0xa400 }, - { 0x54039, 0x3112 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P1 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp1_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x101 }, - { 0x54003, 0x190 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x310 }, - { 0x54019, 0x84 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, - { 0x54032, 0x8400 }, - { 0x54033, 0x3100 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0x3100 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P2 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp2_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x102 }, - { 0x54003, 0x64 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x310 }, - { 0x54019, 0x84 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, - { 0x54032, 0x8400 }, - { 0x54033, 0x3100 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0x3100 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P0 2D message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0x640 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, - { 0x54008, 0x61 }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54010, 0x1f7f }, - { 0x54012, 0x310 }, - { 0x54019, 0x12a4 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x12a4 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, - { 0x54032, 0xa400 }, - { 0x54033, 0x3112 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, - { 0x54038, 0xa400 }, - { 0x54039, 0x3112 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* DRAM PHY init engine image */ -struct dram_cfg_param ddr_phy_pie[] = { - { 0xd0000, 0x0 }, - { 0x90000, 0x10 }, - { 0x90001, 0x400 }, - { 0x90002, 0x10e }, - { 0x90003, 0x0 }, - { 0x90004, 0x0 }, - { 0x90005, 0x8 }, - { 0x90029, 0xb }, - { 0x9002a, 0x480 }, - { 0x9002b, 0x109 }, - { 0x9002c, 0x8 }, - { 0x9002d, 0x448 }, - { 0x9002e, 0x139 }, - { 0x9002f, 0x8 }, - { 0x90030, 0x478 }, - { 0x90031, 0x109 }, - { 0x90032, 0x0 }, - { 0x90033, 0xe8 }, - { 0x90034, 0x109 }, - { 0x90035, 0x2 }, - { 0x90036, 0x10 }, - { 0x90037, 0x139 }, - { 0x90038, 0xb }, - { 0x90039, 0x7c0 }, - { 0x9003a, 0x139 }, - { 0x9003b, 0x44 }, - { 0x9003c, 0x633 }, - { 0x9003d, 0x159 }, - { 0x9003e, 0x14f }, - { 0x9003f, 0x630 }, - { 0x90040, 0x159 }, - { 0x90041, 0x47 }, - { 0x90042, 0x633 }, - { 0x90043, 0x149 }, - { 0x90044, 0x4f }, - { 0x90045, 0x633 }, - { 0x90046, 0x179 }, - { 0x90047, 0x8 }, - { 0x90048, 0xe0 }, - { 0x90049, 0x109 }, - { 0x9004a, 0x0 }, - { 0x9004b, 0x7c8 }, - { 0x9004c, 0x109 }, - { 0x9004d, 0x0 }, - { 0x9004e, 0x1 }, - { 0x9004f, 0x8 }, - { 0x90050, 0x0 }, - { 0x90051, 0x45a }, - { 0x90052, 0x9 }, - { 0x90053, 0x0 }, - { 0x90054, 0x448 }, - { 0x90055, 0x109 }, - { 0x90056, 0x40 }, - { 0x90057, 0x633 }, - { 0x90058, 0x179 }, - { 0x90059, 0x1 }, - { 0x9005a, 0x618 }, - { 0x9005b, 0x109 }, - { 0x9005c, 0x40c0 }, - { 0x9005d, 0x633 }, - { 0x9005e, 0x149 }, - { 0x9005f, 0x8 }, - { 0x90060, 0x4 }, - { 0x90061, 0x48 }, - { 0x90062, 0x4040 }, - { 0x90063, 0x633 }, - { 0x90064, 0x149 }, - { 0x90065, 0x0 }, - { 0x90066, 0x4 }, - { 0x90067, 0x48 }, - { 0x90068, 0x40 }, - { 0x90069, 0x633 }, - { 0x9006a, 0x149 }, - { 0x9006b, 0x10 }, - { 0x9006c, 0x4 }, - { 0x9006d, 0x18 }, - { 0x9006e, 0x0 }, - { 0x9006f, 0x4 }, - { 0x90070, 0x78 }, - { 0x90071, 0x549 }, - { 0x90072, 0x633 }, - { 0x90073, 0x159 }, - { 0x90074, 0xd49 }, - { 0x90075, 0x633 }, - { 0x90076, 0x159 }, - { 0x90077, 0x94a }, - { 0x90078, 0x633 }, - { 0x90079, 0x159 }, - { 0x9007a, 0x441 }, - { 0x9007b, 0x633 }, - { 0x9007c, 0x149 }, - { 0x9007d, 0x42 }, - { 0x9007e, 0x633 }, - { 0x9007f, 0x149 }, - { 0x90080, 0x1 }, - { 0x90081, 0x633 }, - { 0x90082, 0x149 }, - { 0x90083, 0x0 }, - { 0x90084, 0xe0 }, - { 0x90085, 0x109 }, - { 0x90086, 0xa }, - { 0x90087, 0x10 }, - { 0x90088, 0x109 }, - { 0x90089, 0x9 }, - { 0x9008a, 0x3c0 }, - { 0x9008b, 0x149 }, - { 0x9008c, 0x9 }, - { 0x9008d, 0x3c0 }, - { 0x9008e, 0x159 }, - { 0x9008f, 0x18 }, - { 0x90090, 0x10 }, - { 0x90091, 0x109 }, - { 0x90092, 0x0 }, - { 0x90093, 0x3c0 }, - { 0x90094, 0x109 }, - { 0x90095, 0x18 }, - { 0x90096, 0x4 }, - { 0x90097, 0x48 }, - { 0x90098, 0x18 }, - { 0x90099, 0x4 }, - { 0x9009a, 0x58 }, - { 0x9009b, 0xb }, - { 0x9009c, 0x10 }, - { 0x9009d, 0x109 }, - { 0x9009e, 0x1 }, - { 0x9009f, 0x10 }, - { 0x900a0, 0x109 }, - { 0x900a1, 0x5 }, - { 0x900a2, 0x7c0 }, - { 0x900a3, 0x109 }, - { 0x40000, 0x811 }, - { 0x40020, 0x880 }, - { 0x40040, 0x0 }, - { 0x40060, 0x0 }, - { 0x40001, 0x4008 }, - { 0x40021, 0x83 }, - { 0x40041, 0x4f }, - { 0x40061, 0x0 }, - { 0x40002, 0x4040 }, - { 0x40022, 0x83 }, - { 0x40042, 0x51 }, - { 0x40062, 0x0 }, - { 0x40003, 0x811 }, - { 0x40023, 0x880 }, - { 0x40043, 0x0 }, - { 0x40063, 0x0 }, - { 0x40004, 0x720 }, - { 0x40024, 0xf }, - { 0x40044, 0x1740 }, - { 0x40064, 0x0 }, - { 0x40005, 0x16 }, - { 0x40025, 0x83 }, - { 0x40045, 0x4b }, - { 0x40065, 0x0 }, - { 0x40006, 0x716 }, - { 0x40026, 0xf }, - { 0x40046, 0x2001 }, - { 0x40066, 0x0 }, - { 0x40007, 0x716 }, - { 0x40027, 0xf }, - { 0x40047, 0x2800 }, - { 0x40067, 0x0 }, - { 0x40008, 0x716 }, - { 0x40028, 0xf }, - { 0x40048, 0xf00 }, - { 0x40068, 0x0 }, - { 0x40009, 0x720 }, - { 0x40029, 0xf }, - { 0x40049, 0x1400 }, - { 0x40069, 0x0 }, - { 0x4000a, 0xe08 }, - { 0x4002a, 0xc15 }, - { 0x4004a, 0x0 }, - { 0x4006a, 0x0 }, - { 0x4000b, 0x625 }, - { 0x4002b, 0x15 }, - { 0x4004b, 0x0 }, - { 0x4006b, 0x0 }, - { 0x4000c, 0x4028 }, - { 0x4002c, 0x80 }, - { 0x4004c, 0x0 }, - { 0x4006c, 0x0 }, - { 0x4000d, 0xe08 }, - { 0x4002d, 0xc1a }, - { 0x4004d, 0x0 }, - { 0x4006d, 0x0 }, - { 0x4000e, 0x625 }, - { 0x4002e, 0x1a }, - { 0x4004e, 0x0 }, - { 0x4006e, 0x0 }, - { 0x4000f, 0x4040 }, - { 0x4002f, 0x80 }, - { 0x4004f, 0x0 }, - { 0x4006f, 0x0 }, - { 0x40010, 0x2604 }, - { 0x40030, 0x15 }, - { 0x40050, 0x0 }, - { 0x40070, 0x0 }, - { 0x40011, 0x708 }, - { 0x40031, 0x5 }, - { 0x40051, 0x0 }, - { 0x40071, 0x2002 }, - { 0x40012, 0x8 }, - { 0x40032, 0x80 }, - { 0x40052, 0x0 }, - { 0x40072, 0x0 }, - { 0x40013, 0x2604 }, - { 0x40033, 0x1a }, - { 0x40053, 0x0 }, - { 0x40073, 0x0 }, - { 0x40014, 0x708 }, - { 0x40034, 0xa }, - { 0x40054, 0x0 }, - { 0x40074, 0x2002 }, - { 0x40015, 0x4040 }, - { 0x40035, 0x80 }, - { 0x40055, 0x0 }, - { 0x40075, 0x0 }, - { 0x40016, 0x60a }, - { 0x40036, 0x15 }, - { 0x40056, 0x1200 }, - { 0x40076, 0x0 }, - { 0x40017, 0x61a }, - { 0x40037, 0x15 }, - { 0x40057, 0x1300 }, - { 0x40077, 0x0 }, - { 0x40018, 0x60a }, - { 0x40038, 0x1a }, - { 0x40058, 0x1200 }, - { 0x40078, 0x0 }, - { 0x40019, 0x642 }, - { 0x40039, 0x1a }, - { 0x40059, 0x1300 }, - { 0x40079, 0x0 }, - { 0x4001a, 0x4808 }, - { 0x4003a, 0x880 }, - { 0x4005a, 0x0 }, - { 0x4007a, 0x0 }, - { 0x900a4, 0x0 }, - { 0x900a5, 0x790 }, - { 0x900a6, 0x11a }, - { 0x900a7, 0x8 }, - { 0x900a8, 0x7aa }, - { 0x900a9, 0x2a }, - { 0x900aa, 0x10 }, - { 0x900ab, 0x7b2 }, - { 0x900ac, 0x2a }, - { 0x900ad, 0x0 }, - { 0x900ae, 0x7c8 }, - { 0x900af, 0x109 }, - { 0x900b0, 0x10 }, - { 0x900b1, 0x10 }, - { 0x900b2, 0x109 }, - { 0x900b3, 0x10 }, - { 0x900b4, 0x2a8 }, - { 0x900b5, 0x129 }, - { 0x900b6, 0x8 }, - { 0x900b7, 0x370 }, - { 0x900b8, 0x129 }, - { 0x900b9, 0xa }, - { 0x900ba, 0x3c8 }, - { 0x900bb, 0x1a9 }, - { 0x900bc, 0xc }, - { 0x900bd, 0x408 }, - { 0x900be, 0x199 }, - { 0x900bf, 0x14 }, - { 0x900c0, 0x790 }, - { 0x900c1, 0x11a }, - { 0x900c2, 0x8 }, - { 0x900c3, 0x4 }, - { 0x900c4, 0x18 }, - { 0x900c5, 0xe }, - { 0x900c6, 0x408 }, - { 0x900c7, 0x199 }, - { 0x900c8, 0x8 }, - { 0x900c9, 0x8568 }, - { 0x900ca, 0x108 }, - { 0x900cb, 0x18 }, - { 0x900cc, 0x790 }, - { 0x900cd, 0x16a }, - { 0x900ce, 0x8 }, - { 0x900cf, 0x1d8 }, - { 0x900d0, 0x169 }, - { 0x900d1, 0x10 }, - { 0x900d2, 0x8558 }, - { 0x900d3, 0x168 }, - { 0x900d4, 0x70 }, - { 0x900d5, 0x788 }, - { 0x900d6, 0x16a }, - { 0x900d7, 0x1ff8 }, - { 0x900d8, 0x85a8 }, - { 0x900d9, 0x1e8 }, - { 0x900da, 0x50 }, - { 0x900db, 0x798 }, - { 0x900dc, 0x16a }, - { 0x900dd, 0x60 }, - { 0x900de, 0x7a0 }, - { 0x900df, 0x16a }, - { 0x900e0, 0x8 }, - { 0x900e1, 0x8310 }, - { 0x900e2, 0x168 }, - { 0x900e3, 0x8 }, - { 0x900e4, 0xa310 }, - { 0x900e5, 0x168 }, - { 0x900e6, 0xa }, - { 0x900e7, 0x408 }, - { 0x900e8, 0x169 }, - { 0x900e9, 0x6e }, - { 0x900ea, 0x0 }, - { 0x900eb, 0x68 }, - { 0x900ec, 0x0 }, - { 0x900ed, 0x408 }, - { 0x900ee, 0x169 }, - { 0x900ef, 0x0 }, - { 0x900f0, 0x8310 }, - { 0x900f1, 0x168 }, - { 0x900f2, 0x0 }, - { 0x900f3, 0xa310 }, - { 0x900f4, 0x168 }, - { 0x900f5, 0x1ff8 }, - { 0x900f6, 0x85a8 }, - { 0x900f7, 0x1e8 }, - { 0x900f8, 0x68 }, - { 0x900f9, 0x798 }, - { 0x900fa, 0x16a }, - { 0x900fb, 0x78 }, - { 0x900fc, 0x7a0 }, - { 0x900fd, 0x16a }, - { 0x900fe, 0x68 }, - { 0x900ff, 0x790 }, - { 0x90100, 0x16a }, - { 0x90101, 0x8 }, - { 0x90102, 0x8b10 }, - { 0x90103, 0x168 }, - { 0x90104, 0x8 }, - { 0x90105, 0xab10 }, - { 0x90106, 0x168 }, - { 0x90107, 0xa }, - { 0x90108, 0x408 }, - { 0x90109, 0x169 }, - { 0x9010a, 0x58 }, - { 0x9010b, 0x0 }, - { 0x9010c, 0x68 }, - { 0x9010d, 0x0 }, - { 0x9010e, 0x408 }, - { 0x9010f, 0x169 }, - { 0x90110, 0x0 }, - { 0x90111, 0x8b10 }, - { 0x90112, 0x168 }, - { 0x90113, 0x0 }, - { 0x90114, 0xab10 }, - { 0x90115, 0x168 }, - { 0x90116, 0x0 }, - { 0x90117, 0x1d8 }, - { 0x90118, 0x169 }, - { 0x90119, 0x80 }, - { 0x9011a, 0x790 }, - { 0x9011b, 0x16a }, - { 0x9011c, 0x18 }, - { 0x9011d, 0x7aa }, - { 0x9011e, 0x6a }, - { 0x9011f, 0xa }, - { 0x90120, 0x0 }, - { 0x90121, 0x1e9 }, - { 0x90122, 0x8 }, - { 0x90123, 0x8080 }, - { 0x90124, 0x108 }, - { 0x90125, 0xf }, - { 0x90126, 0x408 }, - { 0x90127, 0x169 }, - { 0x90128, 0xc }, - { 0x90129, 0x0 }, - { 0x9012a, 0x68 }, - { 0x9012b, 0x9 }, - { 0x9012c, 0x0 }, - { 0x9012d, 0x1a9 }, - { 0x9012e, 0x0 }, - { 0x9012f, 0x408 }, - { 0x90130, 0x169 }, - { 0x90131, 0x0 }, - { 0x90132, 0x8080 }, - { 0x90133, 0x108 }, - { 0x90134, 0x8 }, - { 0x90135, 0x7aa }, - { 0x90136, 0x6a }, - { 0x90137, 0x0 }, - { 0x90138, 0x8568 }, - { 0x90139, 0x108 }, - { 0x9013a, 0xb7 }, - { 0x9013b, 0x790 }, - { 0x9013c, 0x16a }, - { 0x9013d, 0x1f }, - { 0x9013e, 0x0 }, - { 0x9013f, 0x68 }, - { 0x90140, 0x8 }, - { 0x90141, 0x8558 }, - { 0x90142, 0x168 }, - { 0x90143, 0xf }, - { 0x90144, 0x408 }, - { 0x90145, 0x169 }, - { 0x90146, 0xd }, - { 0x90147, 0x0 }, - { 0x90148, 0x68 }, - { 0x90149, 0x0 }, - { 0x9014a, 0x408 }, - { 0x9014b, 0x169 }, - { 0x9014c, 0x0 }, - { 0x9014d, 0x8558 }, - { 0x9014e, 0x168 }, - { 0x9014f, 0x8 }, - { 0x90150, 0x3c8 }, - { 0x90151, 0x1a9 }, - { 0x90152, 0x3 }, - { 0x90153, 0x370 }, - { 0x90154, 0x129 }, - { 0x90155, 0x20 }, - { 0x90156, 0x2aa }, - { 0x90157, 0x9 }, - { 0x90158, 0x0 }, - { 0x90159, 0x400 }, - { 0x9015a, 0x10e }, - { 0x9015b, 0x8 }, - { 0x9015c, 0xe8 }, - { 0x9015d, 0x109 }, - { 0x9015e, 0x0 }, - { 0x9015f, 0x8140 }, - { 0x90160, 0x10c }, - { 0x90161, 0x10 }, - { 0x90162, 0x8138 }, - { 0x90163, 0x10c }, - { 0x90164, 0x8 }, - { 0x90165, 0x7c8 }, - { 0x90166, 0x101 }, - { 0x90167, 0x8 }, - { 0x90168, 0x448 }, - { 0x90169, 0x109 }, - { 0x9016a, 0xf }, - { 0x9016b, 0x7c0 }, - { 0x9016c, 0x109 }, - { 0x9016d, 0x0 }, - { 0x9016e, 0xe8 }, - { 0x9016f, 0x109 }, - { 0x90170, 0x47 }, - { 0x90171, 0x630 }, - { 0x90172, 0x109 }, - { 0x90173, 0x8 }, - { 0x90174, 0x618 }, - { 0x90175, 0x109 }, - { 0x90176, 0x8 }, - { 0x90177, 0xe0 }, - { 0x90178, 0x109 }, - { 0x90179, 0x0 }, - { 0x9017a, 0x7c8 }, - { 0x9017b, 0x109 }, - { 0x9017c, 0x8 }, - { 0x9017d, 0x8140 }, - { 0x9017e, 0x10c }, - { 0x9017f, 0x0 }, - { 0x90180, 0x1 }, - { 0x90181, 0x8 }, - { 0x90182, 0x8 }, - { 0x90183, 0x4 }, - { 0x90184, 0x8 }, - { 0x90185, 0x8 }, - { 0x90186, 0x7c8 }, - { 0x90187, 0x101 }, - { 0x90006, 0x0 }, - { 0x90007, 0x0 }, - { 0x90008, 0x8 }, - { 0x90009, 0x0 }, - { 0x9000a, 0x0 }, - { 0x9000b, 0x0 }, - { 0xd00e7, 0x400 }, - { 0x90017, 0x0 }, - { 0x9001f, 0x29 }, - { 0x90026, 0x6a }, - { 0x400d0, 0x0 }, - { 0x400d1, 0x101 }, - { 0x400d2, 0x105 }, - { 0x400d3, 0x107 }, - { 0x400d4, 0x10f }, - { 0x400d5, 0x202 }, - { 0x400d6, 0x20a }, - { 0x400d7, 0x20b }, - { 0x2003a, 0x2 }, - { 0x2000b, 0x32 }, - { 0x2000c, 0x64 }, - { 0x2000d, 0x3e8 }, - { 0x2000e, 0x2c }, - { 0x12000b, 0xc }, - { 0x12000c, 0x19 }, - { 0x12000d, 0xfa }, - { 0x12000e, 0x10 }, - { 0x22000b, 0x3 }, - { 0x22000c, 0x6 }, - { 0x22000d, 0x3e }, - { 0x22000e, 0x10 }, - { 0x9000c, 0x0 }, - { 0x9000d, 0x173 }, - { 0x9000e, 0x60 }, - { 0x9000f, 0x6110 }, - { 0x90010, 0x2152 }, - { 0x90011, 0xdfbd }, - { 0x90012, 0x2060 }, - { 0x90013, 0x6152 }, - { 0x20010, 0x5a }, - { 0x20011, 0x3 }, - { 0x120010, 0x5a }, - { 0x120011, 0x3 }, - { 0x220010, 0x5a }, - { 0x220011, 0x3 }, - { 0x40080, 0xe0 }, - { 0x40081, 0x12 }, - { 0x40082, 0xe0 }, - { 0x40083, 0x12 }, - { 0x40084, 0xe0 }, - { 0x40085, 0x12 }, - { 0x140080, 0xe0 }, - { 0x140081, 0x12 }, - { 0x140082, 0xe0 }, - { 0x140083, 0x12 }, - { 0x140084, 0xe0 }, - { 0x140085, 0x12 }, - { 0x240080, 0xe0 }, - { 0x240081, 0x12 }, - { 0x240082, 0xe0 }, - { 0x240083, 0x12 }, - { 0x240084, 0xe0 }, - { 0x240085, 0x12 }, - { 0x400fd, 0xf }, - { 0x10011, 0x1 }, - { 0x10012, 0x1 }, - { 0x10013, 0x180 }, - { 0x10018, 0x1 }, - { 0x10002, 0x6209 }, - { 0x100b2, 0x1 }, - { 0x101b4, 0x1 }, - { 0x102b4, 0x1 }, - { 0x103b4, 0x1 }, - { 0x104b4, 0x1 }, - { 0x105b4, 0x1 }, - { 0x106b4, 0x1 }, - { 0x107b4, 0x1 }, - { 0x108b4, 0x1 }, - { 0x11011, 0x1 }, - { 0x11012, 0x1 }, - { 0x11013, 0x180 }, - { 0x11018, 0x1 }, - { 0x11002, 0x6209 }, - { 0x110b2, 0x1 }, - { 0x111b4, 0x1 }, - { 0x112b4, 0x1 }, - { 0x113b4, 0x1 }, - { 0x114b4, 0x1 }, - { 0x115b4, 0x1 }, - { 0x116b4, 0x1 }, - { 0x117b4, 0x1 }, - { 0x118b4, 0x1 }, - { 0x20089, 0x1 }, - { 0x20088, 0x19 }, - { 0xc0080, 0x2 }, - { 0xd0000, 0x1 } -}; - -struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 1600mts 1D */ - .drate = 1600, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 400mts 1D */ - .drate = 400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 100mts 1D */ - .drate = 100, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 1600mts 2D */ - .drate = 1600, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 1600, 400, 100, }, -}; diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c deleted file mode 100644 index f96f5c45789..00000000000 --- a/board/freescale/imx8mn_evk/spl.c +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2018-2019, 2021 NXP - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int spl_board_boot_device(enum boot_device boot_dev_spl) -{ - return BOOT_DEVICE_BOOTROM; -} - -void spl_dram_init(void) -{ - ddr_init(&dram_timing); -} - -void spl_board_init(void) -{ - struct udevice *dev; - int ret; - - arch_misc_init(); - - puts("Normal Boot\n"); - - ret = uclass_get_device_by_name(UCLASS_CLK, - "clock-controller@30380000", - &dev); - if (ret < 0) - printf("Failed to find clock node. Check device tree\n"); -} - -#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) -int power_init_board(void) -{ - struct udevice *dev; - int ret; - - ret = pmic_get("pmic@25", &dev); - if (ret == -ENODEV) { - puts("No pca9450@25\n"); - return 0; - } - if (ret != 0) - return ret; - - /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); - -#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE - /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); -#else - /* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */ - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); -#endif - /* Set DVS1 to 0.85v for suspend */ - /* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */ - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); - pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); - - /* set VDD_SNVS_0V8 from default 0.85V */ - pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); - - /* enable LDO4 to 1.2v */ - pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x44); - - return 0; -} -#endif - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif - -void board_init_f(ulong dummy) -{ - int ret; - - arch_cpu_init(); - - timer_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - ret = spl_init(); - if (ret) { - debug("spl_init() failed: %d\n", ret); - hang(); - } - - preloader_console_init(); - - enable_tzc380(); - - /* DDR initialization */ - spl_dram_init(); - - board_init_r(NULL, 0); -} diff --git a/board/freescale/imx8mp_evk/Kconfig b/board/freescale/imx8mp_evk/Kconfig deleted file mode 100644 index cafa6329a40..00000000000 --- a/board/freescale/imx8mp_evk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_IMX8MP_EVK - -config SYS_BOARD - default "imx8mp_evk" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "imx8mp_evk" - -config IMX_CONFIG - default "board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg" - -endif diff --git a/board/freescale/imx8mp_evk/MAINTAINERS b/board/freescale/imx8mp_evk/MAINTAINERS deleted file mode 100644 index 4419527b8bc..00000000000 --- a/board/freescale/imx8mp_evk/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -i.MX8MP EVK BOARD -M: Fabio Estevam -M: Peng Fan -S: Maintained -F: board/freescale/imx8mp_evk/ -F: include/configs/imx8mp_evk.h -F: configs/imx8mp_evk_defconfig diff --git a/board/freescale/imx8mp_evk/Makefile b/board/freescale/imx8mp_evk/Makefile deleted file mode 100644 index 3c154d7f7f5..00000000000 --- a/board/freescale/imx8mp_evk/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright 2019 NXP -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += imx8mp_evk.o - -ifdef CONFIG_XPL_BUILD -obj-y += spl.o -obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o -endif diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c deleted file mode 100644 index 732c0fa561d..00000000000 --- a/board/freescale/imx8mp_evk/imx8mp_evk.c +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 NXP - */ - -#include -#include -#include -#include - -#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) -#define IMX_BOOT_IMAGE_GUID \ - EFI_GUID(0x928b33bc, 0xe58b, 0x4247, 0x9f, 0x1d, \ - 0x3b, 0xf1, 0xee, 0x1c, 0xda, 0xff) - -struct efi_fw_image fw_images[] = { - { - .image_type_id = IMX_BOOT_IMAGE_GUID, - .fw_name = u"IMX8MP-EVK-RAW", - .image_index = 1, - }, -}; - -struct efi_capsule_update_info update_info = { - .dfu_string = "mmc 2=flash-bin raw 0 0x2000 mmcpart 1", - .num_images = ARRAY_SIZE(fw_images), - .images = fw_images, -}; -#endif /* EFI_HAVE_CAPSULE_SUPPORT */ - -int board_late_init(void) -{ -#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) - board_late_mmc_env_init(); -#endif - -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - env_set("board_name", "EVK"); - env_set("board_rev", "iMX8MP"); -#endif - - return 0; -} diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.env b/board/freescale/imx8mp_evk/imx8mp_evk.env deleted file mode 100644 index 18cdf3da056..00000000000 --- a/board/freescale/imx8mp_evk/imx8mp_evk.env +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ - -boot_fdt=try -boot_fit=no -boot_targets=mmc1 mmc2 -bootm_size=0x10000000 -console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 -fdt_addr_r=0x43000000 -fdt_addr=0x43000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE -image=Image -ip_dyn=yes -mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX -mmcpart=1 -mmcroot=/dev/mmcblk1p2 rootwait rw -mmcautodetect=yes -mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} -prepare_mcore=setenv mcore_clk clk-imx8mp.mcore_booted -kernel_addr_r=CONFIG_SYS_LOAD_ADDR -loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} -loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -mmcboot=echo Booting from mmc ...; - run mmcargs; - if test ${boot_fit} = yes || test ${boot_fit} = try; then - bootm ${loadaddr}; - else - if run loadfdt; then - booti ${loadaddr} - ${fdt_addr_r}; - else - echo WARN: Cannot load the DT; - fi; - fi; -netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs - ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp -netboot=echo Booting from net ...; - run netargs; - if test ${ip_dyn} = yes; then - setenv get_cmd dhcp; - else - setenv get_cmd tftp; - fi; - ${get_cmd} ${loadaddr} ${image}; - if test ${boot_fit} = yes || test ${boot_fit} = try; then - bootm ${loadaddr}; - else - if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then - booti ${loadaddr} - ${fdt_addr_r}; - else - echo WARN: Cannot load the DT; - fi; - fi; -bsp_bootcmd=echo Running BSP bootcmd ...; - mmc dev ${mmcdev}; - if run loadimage; then - run mmcboot; - else - run netboot; - fi; diff --git a/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg b/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg deleted file mode 100644 index 6dedf1724ab..00000000000 --- a/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2021 NXP - */ - - -ROM_VERSION v2 -BOOT_FROM sd -LOADER u-boot-spl-ddr.bin 0x920000 diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c deleted file mode 100644 index 8c5306d5d20..00000000000 --- a/board/freescale/imx8mp_evk/lpddr4_timing.c +++ /dev/null @@ -1,2048 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 NXP - */ - -#include -#include - -struct dram_cfg_param ddr_ddrc_cfg[] = { - /** Initialize DDRC registers **/ - { 0x3d400304, 0x1 }, - { 0x3d400030, 0x1 }, - { 0x3d400000, 0xa3080020 }, -#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS - { 0x3d400020, 0x223 }, - { 0x3d400024, 0x124f800 }, - { 0x3d400064, 0x4900a8 }, - { 0x3d400070, 0x1027f90 }, - { 0x3d400074, 0x790 }, - { 0x3d4000d0, 0xc0030495 }, - { 0x3d4000d4, 0x770000 }, - { 0x3d4000dc, 0xc40024 }, -#else - { 0x3d400020, 0x1323 }, - { 0x3d400024, 0x1e84800 }, - { 0x3d400064, 0x7a017c }, -#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC - { 0x3d400070, 0x1027f54 }, -#else - { 0x3d400070, 0x1027f10 }, -#endif - { 0x3d400074, 0x7b0 }, - { 0x3d4000d0, 0xc00307a3 }, - { 0x3d4000d4, 0xc50000 }, - { 0x3d4000dc, 0xf4003f }, -#endif - { 0x3d4000e0, 0x330000 }, - { 0x3d4000e8, 0x660048 }, - { 0x3d4000ec, 0x160048 }, -#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS - { 0x3d400100, 0x1618141a }, - { 0x3d400104, 0x504a6 }, - { 0x3d40010c, 0x909000 }, - { 0x3d400110, 0xb04060b }, - { 0x3d400114, 0x2030909 }, - { 0x3d400118, 0x1010006 }, - { 0x3d40011c, 0x301 }, - { 0x3d400130, 0x20500 }, - { 0x3d400134, 0xb100002 }, - { 0x3d400138, 0xad }, - { 0x3d400144, 0x78003c }, - { 0x3d400180, 0x2580012 }, - { 0x3d400184, 0x1e0493e }, - { 0x3d400188, 0x0 }, - { 0x3d400190, 0x4938208 }, - { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x1308 }, -#else - { 0x3d400100, 0x2028222a }, - { 0x3d400104, 0x807bf }, - { 0x3d40010c, 0xe0e000 }, - { 0x3d400110, 0x12040a12 }, - { 0x3d400114, 0x2050f0f }, - { 0x3d400118, 0x1010009 }, - { 0x3d40011c, 0x501 }, - { 0x3d400130, 0x20800 }, - { 0x3d400134, 0xe100002 }, - { 0x3d400138, 0x184 }, - { 0x3d400144, 0xc80064 }, - { 0x3d400180, 0x3e8001e }, - { 0x3d400184, 0x3207a12 }, - { 0x3d400188, 0x0 }, - { 0x3d400190, 0x49f820e }, - { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x1f0e }, -#endif - { 0x3d4001a0, 0xe0400018 }, - { 0x3d4001a4, 0xdf00e4 }, - { 0x3d4001a8, 0x80000000 }, - { 0x3d4001b0, 0x11 }, - { 0x3d4001c0, 0x1 }, - { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0xc99 }, -#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS - { 0x3d400108, 0x60c1514 }, - { 0x3d400200, 0x16 }, - { 0x3d40020c, 0x0 }, - { 0x3d400210, 0x1f1f }, - { 0x3d400204, 0x80808 }, - { 0x3d400214, 0x7070707 }, - { 0x3d400218, 0x68070707 }, - { 0x3d40021c, 0xf08 }, - { 0x3d400250, 0x1f05 }, - { 0x3d400254, 0x1f }, - { 0x3d400264, 0x90003ff }, - { 0x3d40026c, 0x20003ff }, - { 0x3d400400, 0x111 }, - { 0x3d400408, 0x72ff }, - { 0x3d400494, 0x1000e00 }, - { 0x3d400498, 0x3ff0000 }, - { 0x3d40049c, 0x1000e00 }, - { 0x3d4004a0, 0x3ff0000 }, - { 0x3d402020, 0x21 }, - { 0x3d402024, 0x30d400 }, - { 0x3d402050, 0x20d000 }, - { 0x3d402064, 0xc001c }, -#else - { 0x3d400108, 0x9121c1c }, -#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC - { 0x3d400200, 0x13 }, - { 0x3d40020c, 0x13131300 }, - { 0x3d400210, 0x1f1f }, - { 0x3d400204, 0x50505 }, - { 0x3d400214, 0x4040404 }, - { 0x3d400218, 0x68040404 }, -#else - { 0x3d400200, 0x16 }, - { 0x3d40020c, 0x0 }, - { 0x3d400210, 0x1f1f }, - { 0x3d400204, 0x80808 }, - { 0x3d400214, 0x7070707 }, - { 0x3d400218, 0x68070707 }, -#endif - { 0x3d40021c, 0xf08 }, - { 0x3d400250, 0x1705 }, - { 0x3d400254, 0x2c }, - { 0x3d40025c, 0x4000030 }, - { 0x3d400264, 0x900093e7 }, - { 0x3d40026c, 0x2005574 }, - { 0x3d400400, 0x111 }, - { 0x3d400404, 0x72ff }, - { 0x3d400408, 0x72ff }, - { 0x3d400494, 0x2100e07 }, - { 0x3d400498, 0x620096 }, - { 0x3d40049c, 0x1100e07 }, - { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x1021 }, - { 0x3d402024, 0x30d400 }, - { 0x3d402050, 0x20d000 }, - { 0x3d402064, 0xc0026 }, -#endif - { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0x330000 }, - { 0x3d4020e8, 0x660048 }, - { 0x3d4020ec, 0x160048 }, - { 0x3d402100, 0xa040305 }, - { 0x3d402104, 0x30407 }, - { 0x3d402108, 0x203060b }, - { 0x3d40210c, 0x505000 }, - { 0x3d402110, 0x2040202 }, - { 0x3d402114, 0x2030202 }, - { 0x3d402118, 0x1010004 }, - { 0x3d40211c, 0x301 }, - { 0x3d402130, 0x20300 }, - { 0x3d402134, 0xa100002 }, - { 0x3d402138, 0x27 }, - { 0x3d402144, 0x14000a }, - { 0x3d402180, 0x640004 }, - { 0x3d402190, 0x3818200 }, - { 0x3d402194, 0x80303 }, - { 0x3d4021b4, 0x100 }, - { 0x3d4020f4, 0xc99 }, -#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS - { 0x3d403020, 0x21 }, - { 0x3d403024, 0xc3500 }, - { 0x3d403050, 0x20d000 }, - { 0x3d403064, 0x30007 }, -#else - { 0x3d403020, 0x1021 }, - { 0x3d403024, 0xc3500 }, - { 0x3d403050, 0x20d000 }, - { 0x3d403064, 0x3000a }, -#endif - { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0x330000 }, - { 0x3d4030e8, 0x660048 }, - { 0x3d4030ec, 0x160048 }, - { 0x3d403100, 0xa010102 }, - { 0x3d403104, 0x30404 }, - { 0x3d403108, 0x203060b }, - { 0x3d40310c, 0x505000 }, - { 0x3d403110, 0x2040202 }, - { 0x3d403114, 0x2030202 }, - { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x301 }, - { 0x3d403130, 0x20300 }, - { 0x3d403134, 0xa100002 }, - { 0x3d403138, 0xa }, - { 0x3d403144, 0x50003 }, - { 0x3d403180, 0x190004 }, - { 0x3d403190, 0x3818200 }, - { 0x3d403194, 0x80303 }, - { 0x3d4031b4, 0x100 }, - { 0x3d4030f4, 0xc99 }, - { 0x3d400028, 0x0 }, -}; - -/* PHY Initialize Configuration */ -struct dram_cfg_param ddr_ddrphy_cfg[] = { - { 0x100a0, 0x0 }, - { 0x100a1, 0x1 }, - { 0x100a2, 0x2 }, - { 0x100a3, 0x3 }, - { 0x100a4, 0x4 }, - { 0x100a5, 0x5 }, - { 0x100a6, 0x6 }, - { 0x100a7, 0x7 }, - { 0x110a0, 0x0 }, - { 0x110a1, 0x1 }, - { 0x110a2, 0x3 }, - { 0x110a3, 0x4 }, - { 0x110a4, 0x5 }, - { 0x110a5, 0x2 }, - { 0x110a6, 0x7 }, - { 0x110a7, 0x6 }, - { 0x120a0, 0x0 }, - { 0x120a1, 0x1 }, - { 0x120a2, 0x3 }, - { 0x120a3, 0x2 }, - { 0x120a4, 0x5 }, - { 0x120a5, 0x4 }, - { 0x120a6, 0x7 }, - { 0x120a7, 0x6 }, - { 0x130a0, 0x0 }, - { 0x130a1, 0x1 }, - { 0x130a2, 0x2 }, - { 0x130a3, 0x3 }, - { 0x130a4, 0x4 }, - { 0x130a5, 0x5 }, - { 0x130a6, 0x6 }, - { 0x130a7, 0x7 }, - { 0x1005f, 0x1ff }, - { 0x1015f, 0x1ff }, - { 0x1105f, 0x1ff }, - { 0x1115f, 0x1ff }, - { 0x1205f, 0x1ff }, - { 0x1215f, 0x1ff }, - { 0x1305f, 0x1ff }, - { 0x1315f, 0x1ff }, - { 0x11005f, 0x1ff }, - { 0x11015f, 0x1ff }, - { 0x11105f, 0x1ff }, - { 0x11115f, 0x1ff }, - { 0x11205f, 0x1ff }, - { 0x11215f, 0x1ff }, - { 0x11305f, 0x1ff }, - { 0x11315f, 0x1ff }, - { 0x21005f, 0x1ff }, - { 0x21015f, 0x1ff }, - { 0x21105f, 0x1ff }, - { 0x21115f, 0x1ff }, - { 0x21205f, 0x1ff }, - { 0x21215f, 0x1ff }, - { 0x21305f, 0x1ff }, - { 0x21315f, 0x1ff }, - { 0x55, 0x1ff }, - { 0x1055, 0x1ff }, - { 0x2055, 0x1ff }, - { 0x3055, 0x1ff }, - { 0x4055, 0x1ff }, - { 0x5055, 0x1ff }, - { 0x6055, 0x1ff }, - { 0x7055, 0x1ff }, - { 0x8055, 0x1ff }, - { 0x9055, 0x1ff }, -#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS - { 0x200c5, 0xa }, -#else - { 0x200c5, 0x18 }, -#endif - { 0x1200c5, 0x7 }, - { 0x2200c5, 0x7 }, - { 0x2002e, 0x2 }, - { 0x12002e, 0x2 }, - { 0x22002e, 0x2 }, - { 0x90204, 0x0 }, - { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - { 0x20024, 0x1e3 }, - { 0x2003a, 0x2 }, - { 0x120024, 0x1e3 }, - { 0x2003a, 0x2 }, - { 0x220024, 0x1e3 }, - { 0x2003a, 0x2 }, - { 0x20056, 0x3 }, - { 0x120056, 0x3 }, - { 0x220056, 0x3 }, - { 0x1004d, 0xe00 }, - { 0x1014d, 0xe00 }, - { 0x1104d, 0xe00 }, - { 0x1114d, 0xe00 }, - { 0x1204d, 0xe00 }, - { 0x1214d, 0xe00 }, - { 0x1304d, 0xe00 }, - { 0x1314d, 0xe00 }, - { 0x11004d, 0xe00 }, - { 0x11014d, 0xe00 }, - { 0x11104d, 0xe00 }, - { 0x11114d, 0xe00 }, - { 0x11204d, 0xe00 }, - { 0x11214d, 0xe00 }, - { 0x11304d, 0xe00 }, - { 0x11314d, 0xe00 }, - { 0x21004d, 0xe00 }, - { 0x21014d, 0xe00 }, - { 0x21104d, 0xe00 }, - { 0x21114d, 0xe00 }, - { 0x21204d, 0xe00 }, - { 0x21214d, 0xe00 }, - { 0x21304d, 0xe00 }, - { 0x21314d, 0xe00 }, - { 0x10049, 0xeba }, - { 0x10149, 0xeba }, - { 0x11049, 0xeba }, - { 0x11149, 0xeba }, - { 0x12049, 0xeba }, - { 0x12149, 0xeba }, - { 0x13049, 0xeba }, - { 0x13149, 0xeba }, - { 0x110049, 0xeba }, - { 0x110149, 0xeba }, - { 0x111049, 0xeba }, - { 0x111149, 0xeba }, - { 0x112049, 0xeba }, - { 0x112149, 0xeba }, - { 0x113049, 0xeba }, - { 0x113149, 0xeba }, - { 0x210049, 0xeba }, - { 0x210149, 0xeba }, - { 0x211049, 0xeba }, - { 0x211149, 0xeba }, - { 0x212049, 0xeba }, - { 0x212149, 0xeba }, - { 0x213049, 0xeba }, - { 0x213149, 0xeba }, - { 0x43, 0x63 }, - { 0x1043, 0x63 }, - { 0x2043, 0x63 }, - { 0x3043, 0x63 }, - { 0x4043, 0x63 }, - { 0x5043, 0x63 }, - { 0x6043, 0x63 }, - { 0x7043, 0x63 }, - { 0x8043, 0x63 }, - { 0x9043, 0x63 }, - { 0x20018, 0x3 }, - { 0x20075, 0x4 }, - { 0x20050, 0x0 }, -#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS - { 0x20008, 0x258 }, -#else - { 0x20008, 0x3e8 }, -#endif - { 0x120008, 0x64 }, - { 0x220008, 0x19 }, - { 0x20088, 0x9 }, - { 0x200b2, 0x104 }, - { 0x10043, 0x5a1 }, - { 0x10143, 0x5a1 }, - { 0x11043, 0x5a1 }, - { 0x11143, 0x5a1 }, - { 0x12043, 0x5a1 }, - { 0x12143, 0x5a1 }, - { 0x13043, 0x5a1 }, - { 0x13143, 0x5a1 }, - { 0x1200b2, 0x104 }, - { 0x110043, 0x5a1 }, - { 0x110143, 0x5a1 }, - { 0x111043, 0x5a1 }, - { 0x111143, 0x5a1 }, - { 0x112043, 0x5a1 }, - { 0x112143, 0x5a1 }, - { 0x113043, 0x5a1 }, - { 0x113143, 0x5a1 }, - { 0x2200b2, 0x104 }, - { 0x210043, 0x5a1 }, - { 0x210143, 0x5a1 }, - { 0x211043, 0x5a1 }, - { 0x211143, 0x5a1 }, - { 0x212043, 0x5a1 }, - { 0x212143, 0x5a1 }, - { 0x213043, 0x5a1 }, - { 0x213143, 0x5a1 }, - { 0x200fa, 0x1 }, - { 0x1200fa, 0x1 }, - { 0x2200fa, 0x1 }, - { 0x20019, 0x1 }, - { 0x120019, 0x1 }, - { 0x220019, 0x1 }, - { 0x200f0, 0x660 }, - { 0x200f1, 0x0 }, - { 0x200f2, 0x4444 }, - { 0x200f3, 0x8888 }, - { 0x200f4, 0x5665 }, - { 0x200f5, 0x0 }, - { 0x200f6, 0x0 }, - { 0x200f7, 0xf000 }, - { 0x20025, 0x0 }, - { 0x2002d, 0x0 }, - { 0x12002d, 0x0 }, - { 0x22002d, 0x0 }, - { 0x2007d, 0x212 }, - { 0x12007d, 0x212 }, - { 0x22007d, 0x212 }, - { 0x2007c, 0x61 }, - { 0x12007c, 0x61 }, - { 0x22007c, 0x61 }, - { 0x1004a, 0x500 }, - { 0x1104a, 0x500 }, - { 0x1204a, 0x500 }, - { 0x1304a, 0x500 }, - { 0x2002c, 0x0 }, -}; - -/* ddr phy trained csr */ -struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - { 0x200b2, 0x0 }, - { 0x1200b2, 0x0 }, - { 0x2200b2, 0x0 }, - { 0x200cb, 0x0 }, - { 0x10043, 0x0 }, - { 0x110043, 0x0 }, - { 0x210043, 0x0 }, - { 0x10143, 0x0 }, - { 0x110143, 0x0 }, - { 0x210143, 0x0 }, - { 0x11043, 0x0 }, - { 0x111043, 0x0 }, - { 0x211043, 0x0 }, - { 0x11143, 0x0 }, - { 0x111143, 0x0 }, - { 0x211143, 0x0 }, - { 0x12043, 0x0 }, - { 0x112043, 0x0 }, - { 0x212043, 0x0 }, - { 0x12143, 0x0 }, - { 0x112143, 0x0 }, - { 0x212143, 0x0 }, - { 0x13043, 0x0 }, - { 0x113043, 0x0 }, - { 0x213043, 0x0 }, - { 0x13143, 0x0 }, - { 0x113143, 0x0 }, - { 0x213143, 0x0 }, - { 0x80, 0x0 }, - { 0x100080, 0x0 }, - { 0x200080, 0x0 }, - { 0x1080, 0x0 }, - { 0x101080, 0x0 }, - { 0x201080, 0x0 }, - { 0x2080, 0x0 }, - { 0x102080, 0x0 }, - { 0x202080, 0x0 }, - { 0x3080, 0x0 }, - { 0x103080, 0x0 }, - { 0x203080, 0x0 }, - { 0x4080, 0x0 }, - { 0x104080, 0x0 }, - { 0x204080, 0x0 }, - { 0x5080, 0x0 }, - { 0x105080, 0x0 }, - { 0x205080, 0x0 }, - { 0x6080, 0x0 }, - { 0x106080, 0x0 }, - { 0x206080, 0x0 }, - { 0x7080, 0x0 }, - { 0x107080, 0x0 }, - { 0x207080, 0x0 }, - { 0x8080, 0x0 }, - { 0x108080, 0x0 }, - { 0x208080, 0x0 }, - { 0x9080, 0x0 }, - { 0x109080, 0x0 }, - { 0x209080, 0x0 }, - { 0x10080, 0x0 }, - { 0x110080, 0x0 }, - { 0x210080, 0x0 }, - { 0x10180, 0x0 }, - { 0x110180, 0x0 }, - { 0x210180, 0x0 }, - { 0x11080, 0x0 }, - { 0x111080, 0x0 }, - { 0x211080, 0x0 }, - { 0x11180, 0x0 }, - { 0x111180, 0x0 }, - { 0x211180, 0x0 }, - { 0x12080, 0x0 }, - { 0x112080, 0x0 }, - { 0x212080, 0x0 }, - { 0x12180, 0x0 }, - { 0x112180, 0x0 }, - { 0x212180, 0x0 }, - { 0x13080, 0x0 }, - { 0x113080, 0x0 }, - { 0x213080, 0x0 }, - { 0x13180, 0x0 }, - { 0x113180, 0x0 }, - { 0x213180, 0x0 }, - { 0x10081, 0x0 }, - { 0x110081, 0x0 }, - { 0x210081, 0x0 }, - { 0x10181, 0x0 }, - { 0x110181, 0x0 }, - { 0x210181, 0x0 }, - { 0x11081, 0x0 }, - { 0x111081, 0x0 }, - { 0x211081, 0x0 }, - { 0x11181, 0x0 }, - { 0x111181, 0x0 }, - { 0x211181, 0x0 }, - { 0x12081, 0x0 }, - { 0x112081, 0x0 }, - { 0x212081, 0x0 }, - { 0x12181, 0x0 }, - { 0x112181, 0x0 }, - { 0x212181, 0x0 }, - { 0x13081, 0x0 }, - { 0x113081, 0x0 }, - { 0x213081, 0x0 }, - { 0x13181, 0x0 }, - { 0x113181, 0x0 }, - { 0x213181, 0x0 }, - { 0x100d0, 0x0 }, - { 0x1100d0, 0x0 }, - { 0x2100d0, 0x0 }, - { 0x101d0, 0x0 }, - { 0x1101d0, 0x0 }, - { 0x2101d0, 0x0 }, - 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{ 0x190208, 0x0 }, - { 0x290208, 0x0 }, - { 0x10062, 0x0 }, - { 0x10162, 0x0 }, - { 0x10262, 0x0 }, - { 0x10362, 0x0 }, - { 0x10462, 0x0 }, - { 0x10562, 0x0 }, - { 0x10662, 0x0 }, - { 0x10762, 0x0 }, - { 0x10862, 0x0 }, - { 0x11062, 0x0 }, - { 0x11162, 0x0 }, - { 0x11262, 0x0 }, - { 0x11362, 0x0 }, - { 0x11462, 0x0 }, - { 0x11562, 0x0 }, - { 0x11662, 0x0 }, - { 0x11762, 0x0 }, - { 0x11862, 0x0 }, - { 0x12062, 0x0 }, - { 0x12162, 0x0 }, - { 0x12262, 0x0 }, - { 0x12362, 0x0 }, - { 0x12462, 0x0 }, - { 0x12562, 0x0 }, - { 0x12662, 0x0 }, - { 0x12762, 0x0 }, - { 0x12862, 0x0 }, - { 0x13062, 0x0 }, - { 0x13162, 0x0 }, - { 0x13262, 0x0 }, - { 0x13362, 0x0 }, - { 0x13462, 0x0 }, - { 0x13562, 0x0 }, - { 0x13662, 0x0 }, - { 0x13762, 0x0 }, - { 0x13862, 0x0 }, - { 0x20077, 0x0 }, - { 0x10001, 0x0 }, - { 0x11001, 0x0 }, - { 0x12001, 0x0 }, - { 0x13001, 0x0 }, - { 0x10040, 0x0 }, - { 0x10140, 0x0 }, - { 0x10240, 0x0 }, - { 0x10340, 0x0 }, - { 0x10440, 0x0 }, - { 0x10540, 0x0 }, - { 0x10640, 0x0 }, - { 0x10740, 0x0 }, - { 0x10840, 0x0 }, - { 0x10030, 0x0 }, - { 0x10130, 0x0 }, - { 0x10230, 0x0 }, - { 0x10330, 0x0 }, - { 0x10430, 0x0 }, - { 0x10530, 0x0 }, - { 0x10630, 0x0 }, - { 0x10730, 0x0 }, - { 0x10830, 0x0 }, - { 0x11040, 0x0 }, - { 0x11140, 0x0 }, - { 0x11240, 0x0 }, - { 0x11340, 0x0 }, - { 0x11440, 0x0 }, - { 0x11540, 0x0 }, - { 0x11640, 0x0 }, - { 0x11740, 0x0 }, - { 0x11840, 0x0 }, - { 0x11030, 0x0 }, - { 0x11130, 0x0 }, - { 0x11230, 0x0 }, - { 0x11330, 0x0 }, - { 0x11430, 0x0 }, - { 0x11530, 0x0 }, - { 0x11630, 0x0 }, - { 0x11730, 0x0 }, - { 0x11830, 0x0 }, - { 0x12040, 0x0 }, - { 0x12140, 0x0 }, - { 0x12240, 0x0 }, - { 0x12340, 0x0 }, - { 0x12440, 0x0 }, - { 0x12540, 0x0 }, - { 0x12640, 0x0 }, - { 0x12740, 0x0 }, - { 0x12840, 0x0 }, - { 0x12030, 0x0 }, - { 0x12130, 0x0 }, - { 0x12230, 0x0 }, - { 0x12330, 0x0 }, - { 0x12430, 0x0 }, - { 0x12530, 0x0 }, - { 0x12630, 0x0 }, - { 0x12730, 0x0 }, - { 0x12830, 0x0 }, - { 0x13040, 0x0 }, - { 0x13140, 0x0 }, - { 0x13240, 0x0 }, - { 0x13340, 0x0 }, - { 0x13440, 0x0 }, - { 0x13540, 0x0 }, - { 0x13640, 0x0 }, - { 0x13740, 0x0 }, - { 0x13840, 0x0 }, - { 0x13030, 0x0 }, - { 0x13130, 0x0 }, - { 0x13230, 0x0 }, - { 0x13330, 0x0 }, - { 0x13430, 0x0 }, - { 0x13530, 0x0 }, - { 0x13630, 0x0 }, - { 0x13730, 0x0 }, - { 0x13830, 0x0 }, -}; - -/* P0 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp0_cfg[] = { -#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS - { 0xd0000, 0x0 }, - { 0x54003, 0x960 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x131f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x310 }, - { 0x54019, 0x24c4 }, - { 0x5401a, 0x33 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x24c4 }, - { 0x54020, 0x33 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0xc400 }, - { 0x54033, 0x3324 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0xc400 }, - { 0x54039, 0x3324 }, -#else - { 0xd0000, 0x0 }, - { 0x54003, 0xfa0 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x131f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x310 }, - { 0x54019, 0x3ff4 }, - { 0x5401a, 0x33 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x3ff4 }, - { 0x54020, 0x33 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0xf400 }, - { 0x54033, 0x333f }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0xf400 }, - { 0x54039, 0x333f }, -#endif - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P1 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp1_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x101 }, - { 0x54003, 0x190 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x310 }, - { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P2 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp2_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x102 }, - { 0x54003, 0x64 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x310 }, - { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P0 2D message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - { 0xd0000, 0x0 }, -#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS - { 0x54003, 0x960 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x61 }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54010, 0x1f7f }, - { 0x54012, 0x310 }, - { 0x54019, 0x24c4 }, - { 0x5401a, 0x33 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x24c4 }, - { 0x54020, 0x33 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0xc400 }, - { 0x54033, 0x3324 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0xc400 }, - { 0x54039, 0x3324 }, -#else - { 0x54003, 0xfa0 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x61 }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54010, 0x1f7f }, - { 0x54012, 0x310 }, - { 0x54019, 0x3ff4 }, - { 0x5401a, 0x33 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x3ff4 }, - { 0x54020, 0x33 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0xf400 }, - { 0x54033, 0x333f }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0xf400 }, - { 0x54039, 0x333f }, -#endif - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* DRAM PHY init engine image */ -struct dram_cfg_param ddr_phy_pie[] = { - { 0xd0000, 0x0 }, - { 0x90000, 0x10 }, - { 0x90001, 0x400 }, - { 0x90002, 0x10e }, - { 0x90003, 0x0 }, - { 0x90004, 0x0 }, - { 0x90005, 0x8 }, - { 0x90029, 0xb }, - { 0x9002a, 0x480 }, - { 0x9002b, 0x109 }, - { 0x9002c, 0x8 }, - { 0x9002d, 0x448 }, - { 0x9002e, 0x139 }, - { 0x9002f, 0x8 }, - { 0x90030, 0x478 }, - { 0x90031, 0x109 }, - { 0x90032, 0x0 }, - { 0x90033, 0xe8 }, - { 0x90034, 0x109 }, - { 0x90035, 0x2 }, - { 0x90036, 0x10 }, - { 0x90037, 0x139 }, - { 0x90038, 0xb }, - { 0x90039, 0x7c0 }, - { 0x9003a, 0x139 }, - { 0x9003b, 0x44 }, - { 0x9003c, 0x633 }, - { 0x9003d, 0x159 }, - { 0x9003e, 0x14f }, - { 0x9003f, 0x630 }, - { 0x90040, 0x159 }, - { 0x90041, 0x47 }, - { 0x90042, 0x633 }, - { 0x90043, 0x149 }, - { 0x90044, 0x4f }, - { 0x90045, 0x633 }, - { 0x90046, 0x179 }, - { 0x90047, 0x8 }, - { 0x90048, 0xe0 }, - { 0x90049, 0x109 }, - { 0x9004a, 0x0 }, - { 0x9004b, 0x7c8 }, - { 0x9004c, 0x109 }, - { 0x9004d, 0x0 }, - { 0x9004e, 0x1 }, - { 0x9004f, 0x8 }, - { 0x90050, 0x0 }, - { 0x90051, 0x45a }, - { 0x90052, 0x9 }, - { 0x90053, 0x0 }, - { 0x90054, 0x448 }, - { 0x90055, 0x109 }, - { 0x90056, 0x40 }, - { 0x90057, 0x633 }, - { 0x90058, 0x179 }, - { 0x90059, 0x1 }, - { 0x9005a, 0x618 }, - { 0x9005b, 0x109 }, - { 0x9005c, 0x40c0 }, - { 0x9005d, 0x633 }, - { 0x9005e, 0x149 }, - { 0x9005f, 0x8 }, - { 0x90060, 0x4 }, - { 0x90061, 0x48 }, - { 0x90062, 0x4040 }, - { 0x90063, 0x633 }, - { 0x90064, 0x149 }, - { 0x90065, 0x0 }, - { 0x90066, 0x4 }, - { 0x90067, 0x48 }, - { 0x90068, 0x40 }, - { 0x90069, 0x633 }, - { 0x9006a, 0x149 }, - { 0x9006b, 0x10 }, - { 0x9006c, 0x4 }, - { 0x9006d, 0x18 }, - { 0x9006e, 0x0 }, - { 0x9006f, 0x4 }, - { 0x90070, 0x78 }, - { 0x90071, 0x549 }, - { 0x90072, 0x633 }, - { 0x90073, 0x159 }, - { 0x90074, 0xd49 }, - { 0x90075, 0x633 }, - { 0x90076, 0x159 }, - { 0x90077, 0x94a }, - { 0x90078, 0x633 }, - { 0x90079, 0x159 }, - { 0x9007a, 0x441 }, - { 0x9007b, 0x633 }, - { 0x9007c, 0x149 }, - { 0x9007d, 0x42 }, - { 0x9007e, 0x633 }, - { 0x9007f, 0x149 }, - { 0x90080, 0x1 }, - { 0x90081, 0x633 }, - { 0x90082, 0x149 }, - { 0x90083, 0x0 }, - { 0x90084, 0xe0 }, - { 0x90085, 0x109 }, - { 0x90086, 0xa }, - { 0x90087, 0x10 }, - { 0x90088, 0x109 }, - { 0x90089, 0x9 }, - { 0x9008a, 0x3c0 }, - { 0x9008b, 0x149 }, - { 0x9008c, 0x9 }, - { 0x9008d, 0x3c0 }, - { 0x9008e, 0x159 }, - { 0x9008f, 0x18 }, - { 0x90090, 0x10 }, - { 0x90091, 0x109 }, - { 0x90092, 0x0 }, - { 0x90093, 0x3c0 }, - { 0x90094, 0x109 }, - { 0x90095, 0x18 }, - { 0x90096, 0x4 }, - { 0x90097, 0x48 }, - { 0x90098, 0x18 }, - { 0x90099, 0x4 }, - { 0x9009a, 0x58 }, - { 0x9009b, 0xb }, - { 0x9009c, 0x10 }, - { 0x9009d, 0x109 }, - { 0x9009e, 0x1 }, - { 0x9009f, 0x10 }, - { 0x900a0, 0x109 }, - { 0x900a1, 0x5 }, - { 0x900a2, 0x7c0 }, - { 0x900a3, 0x109 }, - { 0x40000, 0x811 }, - { 0x40020, 0x880 }, - { 0x40040, 0x0 }, - { 0x40060, 0x0 }, - { 0x40001, 0x4008 }, - { 0x40021, 0x83 }, - { 0x40041, 0x4f }, - { 0x40061, 0x0 }, - { 0x40002, 0x4040 }, - { 0x40022, 0x83 }, - { 0x40042, 0x51 }, - { 0x40062, 0x0 }, - { 0x40003, 0x811 }, - { 0x40023, 0x880 }, - { 0x40043, 0x0 }, - { 0x40063, 0x0 }, - { 0x40004, 0x720 }, - { 0x40024, 0xf }, - { 0x40044, 0x1740 }, - { 0x40064, 0x0 }, - { 0x40005, 0x16 }, - { 0x40025, 0x83 }, - { 0x40045, 0x4b }, - { 0x40065, 0x0 }, - { 0x40006, 0x716 }, - { 0x40026, 0xf }, - { 0x40046, 0x2001 }, - { 0x40066, 0x0 }, - { 0x40007, 0x716 }, - { 0x40027, 0xf }, - { 0x40047, 0x2800 }, - { 0x40067, 0x0 }, - { 0x40008, 0x716 }, - { 0x40028, 0xf }, - { 0x40048, 0xf00 }, - { 0x40068, 0x0 }, - { 0x40009, 0x720 }, - { 0x40029, 0xf }, - { 0x40049, 0x1400 }, - { 0x40069, 0x0 }, - { 0x4000a, 0xe08 }, - { 0x4002a, 0xc15 }, - { 0x4004a, 0x0 }, - { 0x4006a, 0x0 }, - { 0x4000b, 0x625 }, - { 0x4002b, 0x15 }, - { 0x4004b, 0x0 }, - { 0x4006b, 0x0 }, - { 0x4000c, 0x4028 }, - { 0x4002c, 0x80 }, - { 0x4004c, 0x0 }, - { 0x4006c, 0x0 }, - { 0x4000d, 0xe08 }, - { 0x4002d, 0xc1a }, - { 0x4004d, 0x0 }, - { 0x4006d, 0x0 }, - { 0x4000e, 0x625 }, - { 0x4002e, 0x1a }, - { 0x4004e, 0x0 }, - { 0x4006e, 0x0 }, - { 0x4000f, 0x4040 }, - { 0x4002f, 0x80 }, - { 0x4004f, 0x0 }, - { 0x4006f, 0x0 }, - { 0x40010, 0x2604 }, - { 0x40030, 0x15 }, - { 0x40050, 0x0 }, - { 0x40070, 0x0 }, - { 0x40011, 0x708 }, - { 0x40031, 0x5 }, - { 0x40051, 0x0 }, - { 0x40071, 0x2002 }, - { 0x40012, 0x8 }, - { 0x40032, 0x80 }, - { 0x40052, 0x0 }, - { 0x40072, 0x0 }, - { 0x40013, 0x2604 }, - { 0x40033, 0x1a }, - { 0x40053, 0x0 }, - { 0x40073, 0x0 }, - { 0x40014, 0x708 }, - { 0x40034, 0xa }, - { 0x40054, 0x0 }, - { 0x40074, 0x2002 }, - { 0x40015, 0x4040 }, - { 0x40035, 0x80 }, - { 0x40055, 0x0 }, - { 0x40075, 0x0 }, - { 0x40016, 0x60a }, - { 0x40036, 0x15 }, - { 0x40056, 0x1200 }, - { 0x40076, 0x0 }, - { 0x40017, 0x61a }, - { 0x40037, 0x15 }, - { 0x40057, 0x1300 }, - { 0x40077, 0x0 }, - { 0x40018, 0x60a }, - { 0x40038, 0x1a }, - { 0x40058, 0x1200 }, - { 0x40078, 0x0 }, - { 0x40019, 0x642 }, - { 0x40039, 0x1a }, - { 0x40059, 0x1300 }, - { 0x40079, 0x0 }, - { 0x4001a, 0x4808 }, - { 0x4003a, 0x880 }, - { 0x4005a, 0x0 }, - { 0x4007a, 0x0 }, - { 0x900a4, 0x0 }, - { 0x900a5, 0x790 }, - { 0x900a6, 0x11a }, - { 0x900a7, 0x8 }, - { 0x900a8, 0x7aa }, - { 0x900a9, 0x2a }, - { 0x900aa, 0x10 }, - { 0x900ab, 0x7b2 }, - { 0x900ac, 0x2a }, - { 0x900ad, 0x0 }, - { 0x900ae, 0x7c8 }, - { 0x900af, 0x109 }, - { 0x900b0, 0x10 }, - { 0x900b1, 0x10 }, - { 0x900b2, 0x109 }, - { 0x900b3, 0x10 }, - { 0x900b4, 0x2a8 }, - { 0x900b5, 0x129 }, - { 0x900b6, 0x8 }, - { 0x900b7, 0x370 }, - { 0x900b8, 0x129 }, - { 0x900b9, 0xa }, - { 0x900ba, 0x3c8 }, - { 0x900bb, 0x1a9 }, - { 0x900bc, 0xc }, - { 0x900bd, 0x408 }, - { 0x900be, 0x199 }, - { 0x900bf, 0x14 }, - { 0x900c0, 0x790 }, - { 0x900c1, 0x11a }, - { 0x900c2, 0x8 }, - { 0x900c3, 0x4 }, - { 0x900c4, 0x18 }, - { 0x900c5, 0xe }, - { 0x900c6, 0x408 }, - { 0x900c7, 0x199 }, - { 0x900c8, 0x8 }, - { 0x900c9, 0x8568 }, - { 0x900ca, 0x108 }, - { 0x900cb, 0x18 }, - { 0x900cc, 0x790 }, - { 0x900cd, 0x16a }, - { 0x900ce, 0x8 }, - { 0x900cf, 0x1d8 }, - { 0x900d0, 0x169 }, - { 0x900d1, 0x10 }, - { 0x900d2, 0x8558 }, - { 0x900d3, 0x168 }, - { 0x900d4, 0x70 }, - { 0x900d5, 0x788 }, - { 0x900d6, 0x16a }, - { 0x900d7, 0x1ff8 }, - { 0x900d8, 0x85a8 }, - { 0x900d9, 0x1e8 }, - { 0x900da, 0x50 }, - { 0x900db, 0x798 }, - { 0x900dc, 0x16a }, - { 0x900dd, 0x60 }, - { 0x900de, 0x7a0 }, - { 0x900df, 0x16a }, - { 0x900e0, 0x8 }, - { 0x900e1, 0x8310 }, - { 0x900e2, 0x168 }, - { 0x900e3, 0x8 }, - { 0x900e4, 0xa310 }, - { 0x900e5, 0x168 }, - { 0x900e6, 0xa }, - { 0x900e7, 0x408 }, - { 0x900e8, 0x169 }, - { 0x900e9, 0x6e }, - { 0x900ea, 0x0 }, - { 0x900eb, 0x68 }, - { 0x900ec, 0x0 }, - { 0x900ed, 0x408 }, - { 0x900ee, 0x169 }, - { 0x900ef, 0x0 }, - { 0x900f0, 0x8310 }, - { 0x900f1, 0x168 }, - { 0x900f2, 0x0 }, - { 0x900f3, 0xa310 }, - { 0x900f4, 0x168 }, - { 0x900f5, 0x1ff8 }, - { 0x900f6, 0x85a8 }, - { 0x900f7, 0x1e8 }, - { 0x900f8, 0x68 }, - { 0x900f9, 0x798 }, - { 0x900fa, 0x16a }, - { 0x900fb, 0x78 }, - { 0x900fc, 0x7a0 }, - { 0x900fd, 0x16a }, - { 0x900fe, 0x68 }, - { 0x900ff, 0x790 }, - { 0x90100, 0x16a }, - { 0x90101, 0x8 }, - { 0x90102, 0x8b10 }, - { 0x90103, 0x168 }, - { 0x90104, 0x8 }, - { 0x90105, 0xab10 }, - { 0x90106, 0x168 }, - { 0x90107, 0xa }, - { 0x90108, 0x408 }, - { 0x90109, 0x169 }, - { 0x9010a, 0x58 }, - { 0x9010b, 0x0 }, - { 0x9010c, 0x68 }, - { 0x9010d, 0x0 }, - { 0x9010e, 0x408 }, - { 0x9010f, 0x169 }, - { 0x90110, 0x0 }, - { 0x90111, 0x8b10 }, - { 0x90112, 0x168 }, - { 0x90113, 0x1 }, - { 0x90114, 0xab10 }, - { 0x90115, 0x168 }, - { 0x90116, 0x0 }, - { 0x90117, 0x1d8 }, - { 0x90118, 0x169 }, - { 0x90119, 0x80 }, - { 0x9011a, 0x790 }, - { 0x9011b, 0x16a }, - { 0x9011c, 0x18 }, - { 0x9011d, 0x7aa }, - { 0x9011e, 0x6a }, - { 0x9011f, 0xa }, - { 0x90120, 0x0 }, - { 0x90121, 0x1e9 }, - { 0x90122, 0x8 }, - { 0x90123, 0x8080 }, - { 0x90124, 0x108 }, - { 0x90125, 0xf }, - { 0x90126, 0x408 }, - { 0x90127, 0x169 }, - { 0x90128, 0xc }, - { 0x90129, 0x0 }, - { 0x9012a, 0x68 }, - { 0x9012b, 0x9 }, - { 0x9012c, 0x0 }, - { 0x9012d, 0x1a9 }, - { 0x9012e, 0x0 }, - { 0x9012f, 0x408 }, - { 0x90130, 0x169 }, - { 0x90131, 0x0 }, - { 0x90132, 0x8080 }, - { 0x90133, 0x108 }, - { 0x90134, 0x8 }, - { 0x90135, 0x7aa }, - { 0x90136, 0x6a }, - { 0x90137, 0x0 }, - { 0x90138, 0x8568 }, - { 0x90139, 0x108 }, - { 0x9013a, 0xb7 }, - { 0x9013b, 0x790 }, - { 0x9013c, 0x16a }, - { 0x9013d, 0x1f }, - { 0x9013e, 0x0 }, - { 0x9013f, 0x68 }, - { 0x90140, 0x8 }, - { 0x90141, 0x8558 }, - { 0x90142, 0x168 }, - { 0x90143, 0xf }, - { 0x90144, 0x408 }, - { 0x90145, 0x169 }, - { 0x90146, 0xd }, - { 0x90147, 0x0 }, - { 0x90148, 0x68 }, - { 0x90149, 0x0 }, - { 0x9014a, 0x408 }, - { 0x9014b, 0x169 }, - { 0x9014c, 0x0 }, - { 0x9014d, 0x8558 }, - { 0x9014e, 0x168 }, - { 0x9014f, 0x8 }, - { 0x90150, 0x3c8 }, - { 0x90151, 0x1a9 }, - { 0x90152, 0x3 }, - { 0x90153, 0x370 }, - { 0x90154, 0x129 }, - { 0x90155, 0x20 }, - { 0x90156, 0x2aa }, - { 0x90157, 0x9 }, - { 0x90158, 0x8 }, - { 0x90159, 0xe8 }, - { 0x9015a, 0x109 }, - { 0x9015b, 0x0 }, - { 0x9015c, 0x8140 }, - { 0x9015d, 0x10c }, - { 0x9015e, 0x10 }, - { 0x9015f, 0x8138 }, - { 0x90160, 0x104 }, - { 0x90161, 0x8 }, - { 0x90162, 0x448 }, - { 0x90163, 0x109 }, - { 0x90164, 0xf }, - { 0x90165, 0x7c0 }, - { 0x90166, 0x109 }, - { 0x90167, 0x0 }, - { 0x90168, 0xe8 }, - { 0x90169, 0x109 }, - { 0x9016a, 0x47 }, - { 0x9016b, 0x630 }, - { 0x9016c, 0x109 }, - { 0x9016d, 0x8 }, - { 0x9016e, 0x618 }, - { 0x9016f, 0x109 }, - { 0x90170, 0x8 }, - { 0x90171, 0xe0 }, - { 0x90172, 0x109 }, - { 0x90173, 0x0 }, - { 0x90174, 0x7c8 }, - { 0x90175, 0x109 }, - { 0x90176, 0x8 }, - { 0x90177, 0x8140 }, - { 0x90178, 0x10c }, - { 0x90179, 0x0 }, - { 0x9017a, 0x478 }, - { 0x9017b, 0x109 }, - { 0x9017c, 0x0 }, - { 0x9017d, 0x1 }, - { 0x9017e, 0x8 }, - { 0x9017f, 0x8 }, - { 0x90180, 0x4 }, - { 0x90181, 0x0 }, - { 0x90006, 0x8 }, - { 0x90007, 0x7c8 }, - { 0x90008, 0x109 }, - { 0x90009, 0x0 }, - { 0x9000a, 0x400 }, - { 0x9000b, 0x106 }, - { 0xd00e7, 0x400 }, - { 0x90017, 0x0 }, - { 0x9001f, 0x29 }, - { 0x90026, 0x68 }, - { 0x400d0, 0x0 }, - { 0x400d1, 0x101 }, - { 0x400d2, 0x105 }, - { 0x400d3, 0x107 }, - { 0x400d4, 0x10f }, - { 0x400d5, 0x202 }, - { 0x400d6, 0x20a }, - { 0x400d7, 0x20b }, - { 0x2003a, 0x2 }, -#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS - { 0x2000b, 0x4b }, - { 0x2000c, 0x96 }, - { 0x2000d, 0x5dc }, -#else - { 0x200be, 0x3 }, - { 0x2000b, 0x7d }, - { 0x2000c, 0xfa }, - { 0x2000d, 0x9c4 }, -#endif - { 0x2000e, 0x2c }, - { 0x12000b, 0xc }, - { 0x12000c, 0x19 }, - { 0x12000d, 0xfa }, - { 0x12000e, 0x10 }, - { 0x22000b, 0x3 }, - { 0x22000c, 0x6 }, - { 0x22000d, 0x3e }, - { 0x22000e, 0x10 }, - { 0x9000c, 0x0 }, - { 0x9000d, 0x173 }, - { 0x9000e, 0x60 }, - { 0x9000f, 0x6110 }, - { 0x90010, 0x2152 }, - { 0x90011, 0xdfbd }, - { 0x90012, 0x2060 }, - { 0x90013, 0x6152 }, - { 0x20010, 0x5a }, - { 0x20011, 0x3 }, -#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS - { 0x120010, 0x5a }, - { 0x120011, 0x3 }, - { 0x220010, 0x5a }, - { 0x220011, 0x3 }, -#endif - { 0x40080, 0xe0 }, - { 0x40081, 0x12 }, - { 0x40082, 0xe0 }, - { 0x40083, 0x12 }, - { 0x40084, 0xe0 }, - { 0x40085, 0x12 }, - { 0x140080, 0xe0 }, - { 0x140081, 0x12 }, - { 0x140082, 0xe0 }, - { 0x140083, 0x12 }, - { 0x140084, 0xe0 }, - { 0x140085, 0x12 }, - { 0x240080, 0xe0 }, - { 0x240081, 0x12 }, - { 0x240082, 0xe0 }, - { 0x240083, 0x12 }, - { 0x240084, 0xe0 }, - { 0x240085, 0x12 }, - { 0x400fd, 0xf }, - { 0x10011, 0x1 }, - { 0x10012, 0x1 }, - { 0x10013, 0x180 }, - { 0x10018, 0x1 }, - { 0x10002, 0x6209 }, - { 0x100b2, 0x1 }, - { 0x101b4, 0x1 }, - { 0x102b4, 0x1 }, - { 0x103b4, 0x1 }, - { 0x104b4, 0x1 }, - { 0x105b4, 0x1 }, - { 0x106b4, 0x1 }, - { 0x107b4, 0x1 }, - { 0x108b4, 0x1 }, - { 0x11011, 0x1 }, - { 0x11012, 0x1 }, - { 0x11013, 0x180 }, - { 0x11018, 0x1 }, - { 0x11002, 0x6209 }, - { 0x110b2, 0x1 }, - { 0x111b4, 0x1 }, - { 0x112b4, 0x1 }, - { 0x113b4, 0x1 }, - { 0x114b4, 0x1 }, - { 0x115b4, 0x1 }, - { 0x116b4, 0x1 }, - { 0x117b4, 0x1 }, - { 0x118b4, 0x1 }, - { 0x12011, 0x1 }, - { 0x12012, 0x1 }, - { 0x12013, 0x180 }, - { 0x12018, 0x1 }, - { 0x12002, 0x6209 }, - { 0x120b2, 0x1 }, - { 0x121b4, 0x1 }, - { 0x122b4, 0x1 }, - { 0x123b4, 0x1 }, - { 0x124b4, 0x1 }, - { 0x125b4, 0x1 }, - { 0x126b4, 0x1 }, - { 0x127b4, 0x1 }, - { 0x128b4, 0x1 }, - { 0x13011, 0x1 }, - { 0x13012, 0x1 }, - { 0x13013, 0x180 }, - { 0x13018, 0x1 }, - { 0x13002, 0x6209 }, - { 0x130b2, 0x1 }, - { 0x131b4, 0x1 }, - { 0x132b4, 0x1 }, - { 0x133b4, 0x1 }, - { 0x134b4, 0x1 }, - { 0x135b4, 0x1 }, - { 0x136b4, 0x1 }, - { 0x137b4, 0x1 }, - { 0x138b4, 0x1 }, - { 0x20089, 0x1 }, - { 0x20088, 0x19 }, - { 0xc0080, 0x2 }, - { 0xd0000, 0x1 } -}; - -struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { -#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS - /* P0 2400mts 1D */ - .drate = 2400, -#else - /* P0 4000mts 1D */ - .drate = 4000, -#endif - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 400mts 1D */ - .drate = 400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 100mts 1D */ - .drate = 100, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { -#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS - /* P0 2400mts 2D */ - .drate = 2400, -#else - /* P0 4000mts 2D */ - .drate = 4000, -#endif - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), -#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS - .fsp_table = { 2400, 400, 100, }, -#else - .fsp_table = { 4000, 400, 100, }, -#endif -}; - -#ifndef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS -#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC -void board_dram_ecc_scrub(void) -{ - ddrc_inline_ecc_scrub(0x0, 0x3ffffff); - ddrc_inline_ecc_scrub(0x20000000, 0x23ffffff); - ddrc_inline_ecc_scrub(0x40000000, 0x43ffffff); - ddrc_inline_ecc_scrub(0x4000000, 0x7ffffff); - ddrc_inline_ecc_scrub(0x24000000, 0x27ffffff); - ddrc_inline_ecc_scrub(0x44000000, 0x47ffffff); - ddrc_inline_ecc_scrub(0x8000000, 0xbffffff); - ddrc_inline_ecc_scrub(0x28000000, 0x2bffffff); - ddrc_inline_ecc_scrub(0x48000000, 0x4bffffff); - ddrc_inline_ecc_scrub(0xc000000, 0xfffffff); - ddrc_inline_ecc_scrub(0x2c000000, 0x2fffffff); - ddrc_inline_ecc_scrub(0x4c000000, 0x4fffffff); - ddrc_inline_ecc_scrub(0x10000000, 0x13ffffff); - ddrc_inline_ecc_scrub(0x30000000, 0x33ffffff); - ddrc_inline_ecc_scrub(0x50000000, 0x53ffffff); - ddrc_inline_ecc_scrub(0x14000000, 0x17ffffff); - ddrc_inline_ecc_scrub(0x34000000, 0x37ffffff); - ddrc_inline_ecc_scrub(0x54000000, 0x57ffffff); - ddrc_inline_ecc_scrub(0x18000000, 0x1bffffff); - ddrc_inline_ecc_scrub(0x38000000, 0x3bffffff); - ddrc_inline_ecc_scrub(0x58000000, 0x5bffffff); - ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff); -} -#endif -#endif diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c deleted file mode 100644 index 12da1b2abfb..00000000000 --- a/board/freescale/imx8mp_evk/spl.c +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2018-2019, 2021 NXP - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int spl_board_boot_device(enum boot_device boot_dev_spl) -{ - return BOOT_DEVICE_BOOTROM; -} - -void spl_dram_init(void) -{ - ddr_init(&dram_timing); -} - -void spl_board_init(void) -{ - arch_misc_init(); - - /* - * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does - * not allow to change it. Should set the clock after PMIC - * setting done. Default is 400Mhz (system_pll1_800m with div = 2) - * set by ROM for ND VDD_SOC - */ - clock_enable(CCGR_GIC, 0); - clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); - clock_enable(CCGR_GIC, 1); - - puts("Normal Boot\n"); -} - -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - -#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) -int power_init_board(void) -{ - struct udevice *dev; - int ret; - - ret = pmic_get("pmic@25", &dev); - if (ret == -ENODEV) { - puts("No pmic@25\n"); - return 0; - } - if (ret < 0) - return ret; - - /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); - - /* - * Increase VDD_SOC to typical value 0.95V before first - * DRAM access, set DVS1 to 0.85V for suspend. - * Enable DVS control through PMIC_STBY_REQ and - * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) - */ - if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV)) - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); - else - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); - - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); - pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); - - /* - * Kernel uses OD/OD freq for SOC. - * To avoid timing risk from SOC to ARM,increase VDD_ARM to OD - * voltage 0.95V. - */ - - pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); - - return 0; -} -#endif - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif - -/* Do not use BSS area in this phase */ -void board_init_f(ulong dummy) -{ - int ret; - - arch_cpu_init(); - - init_uart_clk(1); - - ret = spl_early_init(); - if (ret) { - debug("spl_init() failed: %d\n", ret); - hang(); - } - - preloader_console_init(); - - enable_tzc380(); - - power_init_board(); - - /* DDR initialization */ - spl_dram_init(); -} diff --git a/board/freescale/imx8mq_evk/Kconfig b/board/freescale/imx8mq_evk/Kconfig deleted file mode 100644 index c4d20ad7c7d..00000000000 --- a/board/freescale/imx8mq_evk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_IMX8MQ_EVK - -config SYS_BOARD - default "imx8mq_evk" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "imx8mq_evk" - -config IMX_CONFIG - default "arch/arm/mach-imx/imx8m/imximage.cfg" - -endif diff --git a/board/freescale/imx8mq_evk/MAINTAINERS b/board/freescale/imx8mq_evk/MAINTAINERS deleted file mode 100644 index a00bb4ef786..00000000000 --- a/board/freescale/imx8mq_evk/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -i.MX8MQ EVK BOARD -M: Peng Fan -M: Fabio Estevam -S: Maintained -F: board/freescale/imx8mq_evk/ -F: include/configs/imx8mq_evk.h -F: configs/imx8mq_evk_defconfig diff --git a/board/freescale/imx8mq_evk/Makefile b/board/freescale/imx8mq_evk/Makefile deleted file mode 100644 index ca449e6f369..00000000000 --- a/board/freescale/imx8mq_evk/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright 2017 NXP -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += imx8mq_evk.o - -ifdef CONFIG_XPL_BUILD -obj-y += spl.o -obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o -endif diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c deleted file mode 100644 index e90c56c33ff..00000000000 --- a/board/freescale/imx8mq_evk/imx8mq_evk.c +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 NXP - */ - -#include -#include -#include -#include -#include -#include - -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) - -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) - -static iomux_v3_cfg_t const wdog_pads[] = { - IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; - -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) -#define IMX_BOOT_IMAGE_GUID \ - EFI_GUID(0x296119cf, 0xdd70, 0x43de, 0x8a, 0xc8, \ - 0xa7, 0x05, 0x1f, 0x31, 0x25, 0x77) - -struct efi_fw_image fw_images[] = { - { - .image_type_id = IMX_BOOT_IMAGE_GUID, - .fw_name = u"IMX8MQ-EVK-RAW", - .image_index = 1, - }, -}; - -struct efi_capsule_update_info update_info = { - .dfu_string = "mmc 0=flash-bin raw 0x42 0x2000 mmcpart 1", - .num_images = ARRAY_SIZE(fw_images), - .images = fw_images, -}; -#endif /* EFI_HAVE_CAPSULE_SUPPORT */ - -int board_early_init_f(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - set_wdog_reset(wdog); - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - - return 0; -} - -int board_init(void) -{ -#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3) - init_usb_clk(); -#endif - - return 0; -} - -int board_mmc_get_env_dev(int devno) -{ - return devno; -} - -int board_late_init(void) -{ -#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) - board_late_mmc_env_init(); -#endif - -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - env_set("board_name", "EVK"); - env_set("board_rev", "iMX8MQ"); -#endif - - return 0; -} diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.env b/board/freescale/imx8mq_evk/imx8mq_evk.env deleted file mode 100644 index cab8c6b70bf..00000000000 --- a/board/freescale/imx8mq_evk/imx8mq_evk.env +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ - -boot_fdt=try -boot_targets=mmc1 mmc2 dhcp -bootm_size=0x10000000 -console=ttymxc0,115200 -fdt_addr_r=0x43000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE -initrd_addr=0x43800000 -image=Image -ip_dyn=yes -kernel_addr_r=CONFIG_SYS_LOAD_ADDR -loadaddr=CONFIG_SYS_LOAD_ADDR -mmcautodetect=yes -mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX -mmcpart=1 -mmcroot=/dev/mmcblk1p2 rootwait rw -prepare_mcore=setenv mcore_clk clk-imx8mq.mcore_booted; -scriptaddr=CONFIG_SYS_LOAD_ADDR - -mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} -loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} -loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -mmcboot=echo Booting from mmc ...; - run mmcargs; - if test ${boot_fdt} = yes || test ${boot_fdt} = try; then - if run loadfdt; then - booti ${loadaddr} - ${fdt_addr_r}; - else - echo WARN: Cannot load the DT; - fi; - else - echo wait for boot; - fi; -netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs - ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp -netboot=echo Booting from net ...; - run netargs; - if test ${ip_dyn} = yes; then - setenv get_cmd dhcp; - else - setenv get_cmd tftp; - fi; - ${get_cmd} ${loadaddr} ${image}; - if test ${boot_fdt} = yes || test ${boot_fit} = try; then - if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then - booti ${loadaddr} - ${fdt_addr_r}; - else - echo WARN: Cannot load the DT; - fi; - fi; -bsp_bootcmd=echo Running BSP bootcmd ...; - mmc dev ${mmcdev}; - if mmc rescan; then - if run loadimage; then - run mmcboot; - else - run netboot; - fi; - fi; diff --git a/board/freescale/imx8mq_evk/lpddr4_timing.c b/board/freescale/imx8mq_evk/lpddr4_timing.c deleted file mode 100644 index e9559e3d843..00000000000 --- a/board/freescale/imx8mq_evk/lpddr4_timing.c +++ /dev/null @@ -1,1323 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 NXP - */ - -#include -#include -#include - -#define WR_POST_EXT_3200 /* recommened to define */ - -struct dram_cfg_param lpddr4_ddrc_cfg[] = { - /* Start to config, default 3200mbps */ - { DDRC_DBG1(0), 0x00000001 }, - { DDRC_PWRCTL(0), 0x00000001 }, - { DDRC_MSTR(0), 0xa3080020 }, - { DDRC_MSTR2(0), 0x00000000 }, - { DDRC_RFSHTMG(0), 0x006100E0 }, - { DDRC_INIT0(0), 0xC003061B }, - { DDRC_INIT1(0), 0x009D0000 }, - { DDRC_INIT3(0), 0x00D4002D }, -#ifdef WR_POST_EXT_3200 - { DDRC_INIT4(0), 0x00330008 }, -#else - { DDRC_INIT4(0), 0x00310008 }, -#endif - { DDRC_INIT6(0), 0x0066004a }, - { DDRC_INIT7(0), 0x0006004a }, - - { DDRC_DRAMTMG0(0), 0x1A201B22 }, - { DDRC_DRAMTMG1(0), 0x00060633 }, - { DDRC_DRAMTMG3(0), 0x00C0C000 }, - { DDRC_DRAMTMG4(0), 0x0F04080F }, - { DDRC_DRAMTMG5(0), 0x02040C0C }, - { DDRC_DRAMTMG6(0), 0x01010007 }, - { DDRC_DRAMTMG7(0), 0x00000401 }, - { DDRC_DRAMTMG12(0), 0x00020600 }, - { DDRC_DRAMTMG13(0), 0x0C100002 }, - { DDRC_DRAMTMG14(0), 0x000000E6 }, - { DDRC_DRAMTMG17(0), 0x00A00050 }, - - { DDRC_ZQCTL0(0), 0x03200018 }, - { DDRC_ZQCTL1(0), 0x028061A8 }, - { DDRC_ZQCTL2(0), 0x00000000 }, - - { DDRC_DFITMG0(0), 0x0497820A }, - { DDRC_DFITMG1(0), 0x00080303 }, - { DDRC_DFIUPD0(0), 0xE0400018 }, - { DDRC_DFIUPD1(0), 0x00DF00E4 }, - { DDRC_DFIUPD2(0), 0x80000000 }, - { DDRC_DFIMISC(0), 0x00000011 }, - { DDRC_DFITMG2(0), 0x0000170A }, - - { DDRC_DBICTL(0), 0x00000001 }, - { DDRC_DFIPHYMSTR(0), 0x00000001 }, - { DDRC_RANKCTL(0), 0x00000c99 }, - { DDRC_DRAMTMG2(0), 0x070E171a }, - - /* address mapping */ - { DDRC_ADDRMAP0(0), 0x00000015 }, - { DDRC_ADDRMAP3(0), 0x00000000 }, - { DDRC_ADDRMAP4(0), 0x00001F1F }, - /* bank interleave */ - { DDRC_ADDRMAP1(0), 0x00080808 }, - { DDRC_ADDRMAP5(0), 0x07070707 }, - { DDRC_ADDRMAP6(0), 0x08080707 }, - - /* performance setting */ - { DDRC_ODTCFG(0), 0x0b060908 }, - { DDRC_ODTMAP(0), 0x00000000 }, - { DDRC_SCHED(0), 0x29511505 }, - { DDRC_SCHED1(0), 0x0000002c }, - { DDRC_PERFHPR1(0), 0x5900575b }, - /* 150T starve and 0x90 max tran len */ - { DDRC_PERFLPR1(0), 0x90000096 }, - /* 300T starve and 0x10 max tran len */ - { DDRC_PERFWR1(0), 0x1000012c }, - { DDRC_DBG0(0), 0x00000016 }, - { DDRC_DBG1(0), 0x00000000 }, - { DDRC_DBGCMD(0), 0x00000000 }, - { DDRC_SWCTL(0), 0x00000001 }, - { DDRC_POISONCFG(0), 0x00000011 }, - { DDRC_PCCFG(0), 0x00000111 }, - { DDRC_PCFGR_0(0), 0x000010f3 }, - { DDRC_PCFGW_0(0), 0x000072ff }, - { DDRC_PCTRL_0(0), 0x00000001 }, - /* disable Read Qos*/ - { DDRC_PCFGQOS0_0(0), 0x00000e00 }, - { DDRC_PCFGQOS1_0(0), 0x0062ffff }, - /* disable Write Qos*/ - { DDRC_PCFGWQOS0_0(0), 0x00000e00 }, - { DDRC_PCFGWQOS1_0(0), 0x0000ffff }, - - /* Frequency 1: 400mbps */ - { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c }, - { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 }, - { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c }, - { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 }, - { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 }, - { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 }, - { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 }, - { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e }, - { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 }, - { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, - { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b }, - { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 }, - { DDRC_FREQ1_DFITMG0(0), 0x03818200 }, - { DDRC_FREQ1_DFITMG2(0), 0x00000000 }, - { DDRC_FREQ1_RFSHTMG(0), 0x000C001c }, - { DDRC_FREQ1_INIT3(0), 0x00840000 }, - { DDRC_FREQ1_INIT4(0), 0x00310008 }, - { DDRC_FREQ1_INIT6(0), 0x0066004a }, - { DDRC_FREQ1_INIT7(0), 0x0006004a }, - - /* Frequency 2: 100mbps */ - { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c }, - { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 }, - { DDRC_FREQ2_DRAMTMG2(0), 0x0305090c }, - { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 }, - { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 }, - { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 }, - { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 }, - { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e }, - { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 }, - { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b }, - { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 }, - { DDRC_FREQ2_DFITMG0(0), 0x03818200 }, - { DDRC_FREQ2_DFITMG2(0), 0x00000000 }, - { DDRC_FREQ2_RFSHTMG(0), 0x00030007 }, - { DDRC_FREQ2_INIT3(0), 0x00840000 }, - { DDRC_FREQ2_INIT4(0), 0x00310008 }, - { DDRC_FREQ2_INIT6(0), 0x0066004a }, - { DDRC_FREQ2_INIT7(0), 0x0006004a }, -}; - -/* PHY Initialize Configuration */ -struct dram_cfg_param lpddr4_ddrphy_cfg[] = { - { 0x20110, 0x02 }, - { 0x20111, 0x03 }, - { 0x20112, 0x04 }, - { 0x20113, 0x05 }, - { 0x20114, 0x00 }, - { 0x20115, 0x01 }, - - { 0x1005f, 0x1ff }, - { 0x1015f, 0x1ff }, - { 0x1105f, 0x1ff }, - { 0x1115f, 0x1ff }, - { 0x1205f, 0x1ff }, - { 0x1215f, 0x1ff }, - { 0x1305f, 0x1ff }, - { 0x1315f, 0x1ff }, - - { 0x11005f, 0x1ff }, - { 0x11015f, 0x1ff }, - { 0x11105f, 0x1ff }, - { 0x11115f, 0x1ff }, - { 0x11205f, 0x1ff }, - { 0x11215f, 0x1ff }, - { 0x11305f, 0x1ff }, - { 0x11315f, 0x1ff }, - - { 0x21005f, 0x1ff }, - { 0x21015f, 0x1ff }, - { 0x21105f, 0x1ff }, - { 0x21115f, 0x1ff }, - { 0x21205f, 0x1ff }, - { 0x21215f, 0x1ff }, - { 0x21305f, 0x1ff }, - { 0x21315f, 0x1ff }, - - { 0x55, 0x1ff }, - { 0x1055, 0x1ff }, - { 0x2055, 0x1ff }, - { 0x3055, 0x1ff }, - { 0x4055, 0x1ff }, - { 0x5055, 0x1ff }, - { 0x6055, 0x1ff }, - { 0x7055, 0x1ff }, - { 0x8055, 0x1ff }, - { 0x9055, 0x1ff }, - - { 0x200c5, 0x19 }, - { 0x1200c5, 0x7 }, - { 0x2200c5, 0x7 }, - - { 0x2002e, 0x2 }, - { 0x12002e, 0x2 }, - { 0x22002e, 0x2 }, - - { 0x90204, 0x0 }, - { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - -#ifdef WR_POST_EXT_3200 - { 0x20024, 0xeb }, -#else - { 0x20024, 0xab }, -#endif - { 0x2003a, 0x0 }, - { 0x120024, 0xab }, - { 0x2003a, 0x0 }, - { 0x220024, 0xab }, - { 0x2003a, 0x0 }, - { 0x20056, 0x3 }, - { 0x120056, 0xa }, - { 0x220056, 0xa }, - { 0x1004d, 0xe00 }, - { 0x1014d, 0xe00 }, - { 0x1104d, 0xe00 }, - { 0x1114d, 0xe00 }, - { 0x1204d, 0xe00 }, - { 0x1214d, 0xe00 }, - { 0x1304d, 0xe00 }, - { 0x1314d, 0xe00 }, - { 0x11004d, 0xe00 }, - { 0x11014d, 0xe00 }, - { 0x11104d, 0xe00 }, - { 0x11114d, 0xe00 }, - { 0x11204d, 0xe00 }, - { 0x11214d, 0xe00 }, - { 0x11304d, 0xe00 }, - { 0x11314d, 0xe00 }, - { 0x21004d, 0xe00 }, - { 0x21014d, 0xe00 }, - { 0x21104d, 0xe00 }, - { 0x21114d, 0xe00 }, - { 0x21204d, 0xe00 }, - { 0x21214d, 0xe00 }, - { 0x21304d, 0xe00 }, - { 0x21314d, 0xe00 }, - - { 0x10049, 0xfbe }, - { 0x10149, 0xfbe }, - { 0x11049, 0xfbe }, - { 0x11149, 0xfbe }, - { 0x12049, 0xfbe }, - { 0x12149, 0xfbe }, - { 0x13049, 0xfbe }, - { 0x13149, 0xfbe }, - { 0x110049, 0xfbe }, - { 0x110149, 0xfbe }, - { 0x111049, 0xfbe }, - { 0x111149, 0xfbe }, - { 0x112049, 0xfbe }, - { 0x112149, 0xfbe }, - { 0x113049, 0xfbe }, - { 0x113149, 0xfbe }, - { 0x210049, 0xfbe }, - { 0x210149, 0xfbe }, - { 0x211049, 0xfbe }, - { 0x211149, 0xfbe }, - { 0x212049, 0xfbe }, - { 0x212149, 0xfbe }, - { 0x213049, 0xfbe }, - { 0x213149, 0xfbe }, - - { 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - { 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - { 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - { 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - { 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - { 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - { 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - { 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - { 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - { 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - - { 0x20018, 0x3 }, - { 0x20075, 0x4 }, - { 0x20050, 0x0 }, - { 0x20008, 0x320 }, - { 0x120008, 0x64 }, - { 0x220008, 0x19 }, - { 0x20088, 0x9 }, - { 0x200b2, 0x104 }, - { 0x10043, 0x5a1 }, - { 0x10143, 0x5a1 }, - { 0x11043, 0x5a1 }, - { 0x11143, 0x5a1 }, - { 0x12043, 0x5a1 }, - { 0x12143, 0x5a1 }, - { 0x13043, 0x5a1 }, - { 0x13143, 0x5a1 }, - { 0x1200b2, 0x104 }, - { 0x110043, 0x5a1 }, - { 0x110143, 0x5a1 }, - { 0x111043, 0x5a1 }, - { 0x111143, 0x5a1 }, - { 0x112043, 0x5a1 }, - { 0x112143, 0x5a1 }, - { 0x113043, 0x5a1 }, - { 0x113143, 0x5a1 }, - { 0x2200b2, 0x104 }, - { 0x210043, 0x5a1 }, - { 0x210143, 0x5a1 }, - { 0x211043, 0x5a1 }, - { 0x211143, 0x5a1 }, - { 0x212043, 0x5a1 }, - { 0x212143, 0x5a1 }, - { 0x213043, 0x5a1 }, - { 0x213143, 0x5a1 }, - { 0x200fa, 0x1 }, - { 0x1200fa, 0x1 }, - { 0x2200fa, 0x1 }, - { 0x20019, 0x1 }, - { 0x120019, 0x1 }, - { 0x220019, 0x1 }, - { 0x200f0, 0x660 }, - { 0x200f1, 0x0 }, - { 0x200f2, 0x4444 }, - { 0x200f3, 0x8888 }, - { 0x200f4, 0x5665 }, - { 0x200f5, 0x0 }, - { 0x200f6, 0x0 }, - { 0x200f7, 0xf000 }, - { 0x20025, 0x0 }, - { 0x2002d, 0x0 }, - { 0x12002d, 0x0 }, - { 0x22002d, 0x0 }, - - { 0x200c7, 0x80 }, - { 0x1200c7, 0x80 }, - { 0x2200c7, 0x80 }, - { 0x200ca, 0x106 }, - { 0x1200ca, 0x106 }, - { 0x2200ca, 0x106 }, -}; - -/* P0 message block paremeter for training firmware */ -struct dram_cfg_param lpddr4_fsp0_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, - { 0x54002, 0x0 }, - { 0x54003, 0xc80 }, - { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, /* PHY Ron/Rtt */ - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, - { 0x54008, 0x131f }, - { 0x54009, LPDDR4_HDT_CTL_3200_1D }, - { 0x5400a, 0x0 }, - { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, - { 0x54012, 0x310 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, - - { 0x54019, 0x2dd4 }, -#ifdef WR_POST_EXT_3200 - { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, -#else - { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, -#endif - { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, - { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0 }, - { 0x5401f, 0x2dd4 }, -#ifdef WR_POST_EXT_3200 - { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, -#else - { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, -#endif - { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, - { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1 }, - - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, - { 0x54032, 0xd400 }, - /* MR3/MR2 */ -#ifdef WR_POST_EXT_3200 - { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d /*0x312d*/ }, -#else - { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ }, -#endif - /* MR11/MR4 */ - { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, - /* self:0x284d//MR13/MR12 */ - { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ }, - /* MR16/MR14*/ - { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/ }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x500*/ }, - /* MR1 */ - { 0x54038, 0xd400 }, - /* MR3/MR2 */ -#ifdef WR_POST_EXT_3200 - { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d/*0x312d*/ }, -#else - { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ }, -#endif - /* MR11/MR4 */ - { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, - /* self:0x284d//MR13/MR12 */ - { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ }, - /* MR16/MR14 */ - { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/ }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ }, - /* { 0x5403d, 0x500 } */ - { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, - { 0xd0000, 0x1 }, -}; - -/* P1 message block paremeter for training firmware */ -struct dram_cfg_param lpddr4_fsp1_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, - { 0x54002, 0x101 }, - { 0x54003, 0x190 }, - { 0x54004, 0x2 }, - /* PHY Ron/Rtt */ - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)/*0x2828*/ }, - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, - { 0x54008, LPDDR4_TRAIN_SEQ_400 }, - { 0x54009, LPDDR4_HDT_CTL_400_1D }, - { 0x5400a, 0x0 }, - { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, (LPDDR4_CATRAIN_400 << 8) }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, - { 0x54012, 0x310 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, - { 0x54019, 0x84 }, - /* MR4/MR3 */ - { 0x5401a, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, - /* MR12/MR11 */ - { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | - LPDDR4_RTT_DQ)/*0x4d46*/ }, - /* self:0x4d28//MR14/MR13 */ - { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)/*0x4d08*/ }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0/*0x5*/ }, - { 0x5401f, 0x84 }, - { 0x54020, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, /* MR4/MR3 */ - { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | - LPDDR4_RTT_DQ)/*0x4d46*/ },/* MR12/MR11 */ - /* self:0x4d28//MR14/MR13 */ - { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)/*0x4d08*/ }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, - { 0x54032, 0x8400 }, - { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, - { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, - { 0x54038, 0x8400 }, - { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, - { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, - { 0xd0000, 0x1 }, -}; - -/* P2 message block paremeter for training firmware */ -struct dram_cfg_param lpddr4_fsp2_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, - { 0x54002, 0x102 }, - { 0x54003, 0x64 }, - { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, - { 0x54008, LPDDR4_TRAIN_SEQ_100 }, - { 0x54009, LPDDR4_HDT_CTL_100_1D }, - { 0x5400a, 0x0 }, - { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, (LPDDR4_CATRAIN_100 << 8) }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, - { 0x54012, 0x310 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, - { 0x54019, 0x84 }, - { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, - { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | - LPDDR4_RTT_DQ) }, - { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0 }, - { 0x5401f, 0x84 }, - { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, - { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | - LPDDR4_RTT_DQ) }, - { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, - { 0x54032, 0x8400 }, - { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, - { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, - { 0x54038, 0x8400 }, - { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, - { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, - { 0xd0000, 0x1 }, -}; - -/* P0 2D message block paremeter for training firmware */ -struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, - { 0x54002, 0x0 }, - { 0x54003, 0xc80 }, - { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, - { 0x54008, 0x61 }, - { 0x54009, LPDDR4_HDT_CTL_2D }, - { 0x5400a, 0x0 }, - { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) }, - { 0x5400e, 0x0 }, - { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 }, - { 0x54010, LPDDR4_2D_WEIGHT }, - { 0x54011, 0x0 }, - { 0x54012, 0x310 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, - { 0x54019, 0x2dd4 }, -#ifdef WR_POST_EXT_3200 - { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, -#else - { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, -#endif - { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, - { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0 }, - { 0x5401f, 0x2dd4 }, -#ifdef WR_POST_EXT_3200 - { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, -#else - { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, -#endif - { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, - { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, - - { 0x54032, 0xd400 }, -#ifdef WR_POST_EXT_3200 - { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, -#else - { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d }, -#endif - { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, - { 0x54038, 0xd400 }, -#ifdef WR_POST_EXT_3200 - { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, -#else - { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d }, -#endif - { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, - { 0xd0000, 0x1 }, -}; - -/* DRAM PHY init engine image */ -struct dram_cfg_param lpddr4_phy_pie[] = { - { 0xd0000, 0x0 }, - { 0x90000, 0x10 }, - { 0x90001, 0x400 }, - { 0x90002, 0x10e }, - { 0x90003, 0x0 }, - { 0x90004, 0x0 }, - { 0x90005, 0x8 }, - { 0x90029, 0xb }, - { 0x9002a, 0x480 }, - { 0x9002b, 0x109 }, - { 0x9002c, 0x8 }, - { 0x9002d, 0x448 }, - { 0x9002e, 0x139 }, - { 0x9002f, 0x8 }, - { 0x90030, 0x478 }, - { 0x90031, 0x109 }, - { 0x90032, 0x0 }, - { 0x90033, 0xe8 }, - { 0x90034, 0x109 }, - { 0x90035, 0x2 }, - { 0x90036, 0x10 }, - { 0x90037, 0x139 }, - { 0x90038, 0xf }, - { 0x90039, 0x7c0 }, - { 0x9003a, 0x139 }, - { 0x9003b, 0x44 }, - { 0x9003c, 0x630 }, - { 0x9003d, 0x159 }, - { 0x9003e, 0x14f }, - { 0x9003f, 0x630 }, - { 0x90040, 0x159 }, - { 0x90041, 0x47 }, - { 0x90042, 0x630 }, - { 0x90043, 0x149 }, - { 0x90044, 0x4f }, - { 0x90045, 0x630 }, - { 0x90046, 0x179 }, - { 0x90047, 0x8 }, - { 0x90048, 0xe0 }, - { 0x90049, 0x109 }, - { 0x9004a, 0x0 }, - { 0x9004b, 0x7c8 }, - { 0x9004c, 0x109 }, - { 0x9004d, 0x0 }, - { 0x9004e, 0x1 }, - { 0x9004f, 0x8 }, - { 0x90050, 0x0 }, - { 0x90051, 0x45a }, - { 0x90052, 0x9 }, - { 0x90053, 0x0 }, - { 0x90054, 0x448 }, - { 0x90055, 0x109 }, - { 0x90056, 0x40 }, - { 0x90057, 0x630 }, - { 0x90058, 0x179 }, - { 0x90059, 0x1 }, - { 0x9005a, 0x618 }, - { 0x9005b, 0x109 }, - { 0x9005c, 0x40c0 }, - { 0x9005d, 0x630 }, - { 0x9005e, 0x149 }, - { 0x9005f, 0x8 }, - { 0x90060, 0x4 }, - { 0x90061, 0x48 }, - { 0x90062, 0x4040 }, - { 0x90063, 0x630 }, - { 0x90064, 0x149 }, - { 0x90065, 0x0 }, - { 0x90066, 0x4 }, - { 0x90067, 0x48 }, - { 0x90068, 0x40 }, - { 0x90069, 0x630 }, - { 0x9006a, 0x149 }, - { 0x9006b, 0x10 }, - { 0x9006c, 0x4 }, - { 0x9006d, 0x18 }, - { 0x9006e, 0x0 }, - { 0x9006f, 0x4 }, - { 0x90070, 0x78 }, - { 0x90071, 0x549 }, - { 0x90072, 0x630 }, - { 0x90073, 0x159 }, - { 0x90074, 0xd49 }, - { 0x90075, 0x630 }, - { 0x90076, 0x159 }, - { 0x90077, 0x94a }, - { 0x90078, 0x630 }, - { 0x90079, 0x159 }, - { 0x9007a, 0x441 }, - { 0x9007b, 0x630 }, - { 0x9007c, 0x149 }, - { 0x9007d, 0x42 }, - { 0x9007e, 0x630 }, - { 0x9007f, 0x149 }, - { 0x90080, 0x1 }, - { 0x90081, 0x630 }, - { 0x90082, 0x149 }, - { 0x90083, 0x0 }, - { 0x90084, 0xe0 }, - { 0x90085, 0x109 }, - { 0x90086, 0xa }, - { 0x90087, 0x10 }, - { 0x90088, 0x109 }, - { 0x90089, 0x9 }, - { 0x9008a, 0x3c0 }, - { 0x9008b, 0x149 }, - { 0x9008c, 0x9 }, - { 0x9008d, 0x3c0 }, - { 0x9008e, 0x159 }, - { 0x9008f, 0x18 }, - { 0x90090, 0x10 }, - { 0x90091, 0x109 }, - { 0x90092, 0x0 }, - { 0x90093, 0x3c0 }, - { 0x90094, 0x109 }, - { 0x90095, 0x18 }, - { 0x90096, 0x4 }, - { 0x90097, 0x48 }, - { 0x90098, 0x18 }, - { 0x90099, 0x4 }, - { 0x9009a, 0x58 }, - { 0x9009b, 0xa }, - { 0x9009c, 0x10 }, - { 0x9009d, 0x109 }, - { 0x9009e, 0x2 }, - { 0x9009f, 0x10 }, - { 0x900a0, 0x109 }, - { 0x900a1, 0x5 }, - { 0x900a2, 0x7c0 }, - { 0x900a3, 0x109 }, - { 0x900a4, 0x10 }, - { 0x900a5, 0x10 }, - { 0x900a6, 0x109 }, - { 0x40000, 0x811 }, - { 0x40020, 0x880 }, - { 0x40040, 0x0 }, - { 0x40060, 0x0 }, - { 0x40001, 0x4008 }, - { 0x40021, 0x83 }, - { 0x40041, 0x4f }, - { 0x40061, 0x0 }, - { 0x40002, 0x4040 }, - { 0x40022, 0x83 }, - { 0x40042, 0x51 }, - { 0x40062, 0x0 }, - { 0x40003, 0x811 }, - { 0x40023, 0x880 }, - { 0x40043, 0x0 }, - { 0x40063, 0x0 }, - { 0x40004, 0x720 }, - { 0x40024, 0xf }, - { 0x40044, 0x1740 }, - { 0x40064, 0x0 }, - { 0x40005, 0x16 }, - { 0x40025, 0x83 }, - { 0x40045, 0x4b }, - { 0x40065, 0x0 }, - { 0x40006, 0x716 }, - { 0x40026, 0xf }, - { 0x40046, 0x2001 }, - { 0x40066, 0x0 }, - { 0x40007, 0x716 }, - { 0x40027, 0xf }, - { 0x40047, 0x2800 }, - { 0x40067, 0x0 }, - { 0x40008, 0x716 }, - { 0x40028, 0xf }, - { 0x40048, 0xf00 }, - { 0x40068, 0x0 }, - { 0x40009, 0x720 }, - { 0x40029, 0xf }, - { 0x40049, 0x1400 }, - { 0x40069, 0x0 }, - { 0x4000a, 0xe08 }, - { 0x4002a, 0xc15 }, - { 0x4004a, 0x0 }, - { 0x4006a, 0x0 }, - { 0x4000b, 0x623 }, - { 0x4002b, 0x15 }, - { 0x4004b, 0x0 }, - { 0x4006b, 0x0 }, - { 0x4000c, 0x4028 }, - { 0x4002c, 0x80 }, - { 0x4004c, 0x0 }, - { 0x4006c, 0x0 }, - { 0x4000d, 0xe08 }, - { 0x4002d, 0xc1a }, - { 0x4004d, 0x0 }, - { 0x4006d, 0x0 }, - { 0x4000e, 0x623 }, - { 0x4002e, 0x1a }, - { 0x4004e, 0x0 }, - { 0x4006e, 0x0 }, - { 0x4000f, 0x4040 }, - { 0x4002f, 0x80 }, - { 0x4004f, 0x0 }, - { 0x4006f, 0x0 }, - { 0x40010, 0x2604 }, - { 0x40030, 0x15 }, - { 0x40050, 0x0 }, - { 0x40070, 0x0 }, - { 0x40011, 0x708 }, - { 0x40031, 0x5 }, - { 0x40051, 0x0 }, - { 0x40071, 0x2002 }, - { 0x40012, 0x8 }, - { 0x40032, 0x80 }, - { 0x40052, 0x0 }, - { 0x40072, 0x0 }, - { 0x40013, 0x2604 }, - { 0x40033, 0x1a }, - { 0x40053, 0x0 }, - { 0x40073, 0x0 }, - { 0x40014, 0x708 }, - { 0x40034, 0xa }, - { 0x40054, 0x0 }, - { 0x40074, 0x2002 }, - { 0x40015, 0x4040 }, - { 0x40035, 0x80 }, - { 0x40055, 0x0 }, - { 0x40075, 0x0 }, - { 0x40016, 0x60a }, - { 0x40036, 0x15 }, - { 0x40056, 0x1200 }, - { 0x40076, 0x0 }, - { 0x40017, 0x61a }, - { 0x40037, 0x15 }, - { 0x40057, 0x1300 }, - { 0x40077, 0x0 }, - { 0x40018, 0x60a }, - { 0x40038, 0x1a }, - { 0x40058, 0x1200 }, - { 0x40078, 0x0 }, - { 0x40019, 0x642 }, - { 0x40039, 0x1a }, - { 0x40059, 0x1300 }, - { 0x40079, 0x0 }, - { 0x4001a, 0x4808 }, - { 0x4003a, 0x880 }, - { 0x4005a, 0x0 }, - { 0x4007a, 0x0 }, - { 0x900a7, 0x0 }, - { 0x900a8, 0x790 }, - { 0x900a9, 0x11a }, - { 0x900aa, 0x8 }, - { 0x900ab, 0x7aa }, - { 0x900ac, 0x2a }, - { 0x900ad, 0x10 }, - { 0x900ae, 0x7b2 }, - { 0x900af, 0x2a }, - { 0x900b0, 0x0 }, - { 0x900b1, 0x7c8 }, - { 0x900b2, 0x109 }, - { 0x900b3, 0x10 }, - { 0x900b4, 0x2a8 }, - { 0x900b5, 0x129 }, - { 0x900b6, 0x8 }, - { 0x900b7, 0x370 }, - { 0x900b8, 0x129 }, - { 0x900b9, 0xa }, - { 0x900ba, 0x3c8 }, - { 0x900bb, 0x1a9 }, - { 0x900bc, 0xc }, - { 0x900bd, 0x408 }, - { 0x900be, 0x199 }, - { 0x900bf, 0x14 }, - { 0x900c0, 0x790 }, - { 0x900c1, 0x11a }, - { 0x900c2, 0x8 }, - { 0x900c3, 0x4 }, - { 0x900c4, 0x18 }, - { 0x900c5, 0xe }, - { 0x900c6, 0x408 }, - { 0x900c7, 0x199 }, - { 0x900c8, 0x8 }, - { 0x900c9, 0x8568 }, - { 0x900ca, 0x108 }, - { 0x900cb, 0x18 }, - { 0x900cc, 0x790 }, - { 0x900cd, 0x16a }, - { 0x900ce, 0x8 }, - { 0x900cf, 0x1d8 }, - { 0x900d0, 0x169 }, - { 0x900d1, 0x10 }, - { 0x900d2, 0x8558 }, - { 0x900d3, 0x168 }, - { 0x900d4, 0x70 }, - { 0x900d5, 0x788 }, - { 0x900d6, 0x16a }, - { 0x900d7, 0x1ff8 }, - { 0x900d8, 0x85a8 }, - { 0x900d9, 0x1e8 }, - { 0x900da, 0x50 }, - { 0x900db, 0x798 }, - { 0x900dc, 0x16a }, - { 0x900dd, 0x60 }, - { 0x900de, 0x7a0 }, - { 0x900df, 0x16a }, - { 0x900e0, 0x8 }, - { 0x900e1, 0x8310 }, - { 0x900e2, 0x168 }, - { 0x900e3, 0x8 }, - { 0x900e4, 0xa310 }, - { 0x900e5, 0x168 }, - { 0x900e6, 0xa }, - { 0x900e7, 0x408 }, - { 0x900e8, 0x169 }, - { 0x900e9, 0x6e }, - { 0x900ea, 0x0 }, - { 0x900eb, 0x68 }, - { 0x900ec, 0x0 }, - { 0x900ed, 0x408 }, - { 0x900ee, 0x169 }, - { 0x900ef, 0x0 }, - { 0x900f0, 0x8310 }, - { 0x900f1, 0x168 }, - { 0x900f2, 0x0 }, - { 0x900f3, 0xa310 }, - { 0x900f4, 0x168 }, - { 0x900f5, 0x1ff8 }, - { 0x900f6, 0x85a8 }, - { 0x900f7, 0x1e8 }, - { 0x900f8, 0x68 }, - { 0x900f9, 0x798 }, - { 0x900fa, 0x16a }, - { 0x900fb, 0x78 }, - { 0x900fc, 0x7a0 }, - { 0x900fd, 0x16a }, - { 0x900fe, 0x68 }, - { 0x900ff, 0x790 }, - { 0x90100, 0x16a }, - { 0x90101, 0x8 }, - { 0x90102, 0x8b10 }, - { 0x90103, 0x168 }, - { 0x90104, 0x8 }, - { 0x90105, 0xab10 }, - { 0x90106, 0x168 }, - { 0x90107, 0xa }, - { 0x90108, 0x408 }, - { 0x90109, 0x169 }, - { 0x9010a, 0x58 }, - { 0x9010b, 0x0 }, - { 0x9010c, 0x68 }, - { 0x9010d, 0x0 }, - { 0x9010e, 0x408 }, - { 0x9010f, 0x169 }, - { 0x90110, 0x0 }, - { 0x90111, 0x8b10 }, - { 0x90112, 0x168 }, - { 0x90113, 0x0 }, - { 0x90114, 0xab10 }, - { 0x90115, 0x168 }, - { 0x90116, 0x0 }, - { 0x90117, 0x1d8 }, - { 0x90118, 0x169 }, - { 0x90119, 0x80 }, - { 0x9011a, 0x790 }, - { 0x9011b, 0x16a }, - { 0x9011c, 0x18 }, - { 0x9011d, 0x7aa }, - { 0x9011e, 0x6a }, - { 0x9011f, 0xa }, - { 0x90120, 0x0 }, - { 0x90121, 0x1e9 }, - { 0x90122, 0x8 }, - { 0x90123, 0x8080 }, - { 0x90124, 0x108 }, - { 0x90125, 0xf }, - { 0x90126, 0x408 }, - { 0x90127, 0x169 }, - { 0x90128, 0xc }, - { 0x90129, 0x0 }, - { 0x9012a, 0x68 }, - { 0x9012b, 0x9 }, - { 0x9012c, 0x0 }, - { 0x9012d, 0x1a9 }, - { 0x9012e, 0x0 }, - { 0x9012f, 0x408 }, - { 0x90130, 0x169 }, - { 0x90131, 0x0 }, - { 0x90132, 0x8080 }, - { 0x90133, 0x108 }, - { 0x90134, 0x8 }, - { 0x90135, 0x7aa }, - { 0x90136, 0x6a }, - { 0x90137, 0x0 }, - { 0x90138, 0x8568 }, - { 0x90139, 0x108 }, - { 0x9013a, 0xb7 }, - { 0x9013b, 0x790 }, - { 0x9013c, 0x16a }, - { 0x9013d, 0x1f }, - { 0x9013e, 0x0 }, - { 0x9013f, 0x68 }, - { 0x90140, 0x8 }, - { 0x90141, 0x8558 }, - { 0x90142, 0x168 }, - { 0x90143, 0xf }, - { 0x90144, 0x408 }, - { 0x90145, 0x169 }, - { 0x90146, 0xc }, - { 0x90147, 0x0 }, - { 0x90148, 0x68 }, - { 0x90149, 0x0 }, - { 0x9014a, 0x408 }, - { 0x9014b, 0x169 }, - { 0x9014c, 0x0 }, - { 0x9014d, 0x8558 }, - { 0x9014e, 0x168 }, - { 0x9014f, 0x8 }, - { 0x90150, 0x3c8 }, - { 0x90151, 0x1a9 }, - { 0x90152, 0x3 }, - { 0x90153, 0x370 }, - { 0x90154, 0x129 }, - { 0x90155, 0x20 }, - { 0x90156, 0x2aa }, - { 0x90157, 0x9 }, - { 0x90158, 0x0 }, - { 0x90159, 0x400 }, - { 0x9015a, 0x10e }, - { 0x9015b, 0x8 }, - { 0x9015c, 0xe8 }, - { 0x9015d, 0x109 }, - { 0x9015e, 0x0 }, - { 0x9015f, 0x8140 }, - { 0x90160, 0x10c }, - { 0x90161, 0x10 }, - { 0x90162, 0x8138 }, - { 0x90163, 0x10c }, - { 0x90164, 0x8 }, - { 0x90165, 0x7c8 }, - { 0x90166, 0x101 }, - { 0x90167, 0x8 }, - { 0x90168, 0x0 }, - { 0x90169, 0x8 }, - { 0x9016a, 0x8 }, - { 0x9016b, 0x448 }, - { 0x9016c, 0x109 }, - { 0x9016d, 0xf }, - { 0x9016e, 0x7c0 }, - { 0x9016f, 0x109 }, - { 0x90170, 0x0 }, - { 0x90171, 0xe8 }, - { 0x90172, 0x109 }, - { 0x90173, 0x47 }, - { 0x90174, 0x630 }, - { 0x90175, 0x109 }, - { 0x90176, 0x8 }, - { 0x90177, 0x618 }, - { 0x90178, 0x109 }, - { 0x90179, 0x8 }, - { 0x9017a, 0xe0 }, - { 0x9017b, 0x109 }, - { 0x9017c, 0x0 }, - { 0x9017d, 0x7c8 }, - { 0x9017e, 0x109 }, - { 0x9017f, 0x8 }, - { 0x90180, 0x8140 }, - { 0x90181, 0x10c }, - { 0x90182, 0x0 }, - { 0x90183, 0x1 }, - { 0x90184, 0x8 }, - { 0x90185, 0x8 }, - { 0x90186, 0x4 }, - { 0x90187, 0x8 }, - { 0x90188, 0x8 }, - { 0x90189, 0x7c8 }, - { 0x9018a, 0x101 }, - { 0x90006, 0x0 }, - { 0x90007, 0x0 }, - { 0x90008, 0x8 }, - { 0x90009, 0x0 }, - { 0x9000a, 0x0 }, - { 0x9000b, 0x0 }, - { 0xd00e7, 0x400 }, - { 0x90017, 0x0 }, - { 0x9001f, 0x2a }, - { 0x90026, 0x6a }, - { 0x400d0, 0x0 }, - { 0x400d1, 0x101 }, - { 0x400d2, 0x105 }, - { 0x400d3, 0x107 }, - { 0x400d4, 0x10f }, - { 0x400d5, 0x202 }, - { 0x400d6, 0x20a }, - { 0x400d7, 0x20b }, - { 0x2003a, 0x2 }, - { 0x2000b, 0x64 }, - { 0x2000c, 0xc8 }, - { 0x2000d, 0x7d0 }, - { 0x2000e, 0x2c }, - { 0x12000b, 0xc }, - { 0x12000c, 0x19 }, - { 0x12000d, 0xfa }, - { 0x12000e, 0x10 }, - { 0x22000b, 0x3 }, - { 0x22000c, 0x6 }, - { 0x22000d, 0x3e }, - { 0x22000e, 0x10 }, - { 0x9000c, 0x0 }, - { 0x9000d, 0x173 }, - { 0x9000e, 0x60 }, - { 0x9000f, 0x6110 }, - { 0x90010, 0x2152 }, - { 0x90011, 0xdfbd }, - { 0x90012, 0x60 }, - { 0x90013, 0x6152 }, - { 0x20010, 0x5a }, - { 0x20011, 0x3 }, - { 0x40080, 0xe0 }, - { 0x40081, 0x12 }, - { 0x40082, 0xe0 }, - { 0x40083, 0x12 }, - { 0x40084, 0xe0 }, - { 0x40085, 0x12 }, - { 0x140080, 0xe0 }, - { 0x140081, 0x12 }, - { 0x140082, 0xe0 }, - { 0x140083, 0x12 }, - { 0x140084, 0xe0 }, - { 0x140085, 0x12 }, - { 0x240080, 0xe0 }, - { 0x240081, 0x12 }, - { 0x240082, 0xe0 }, - { 0x240083, 0x12 }, - { 0x240084, 0xe0 }, - { 0x240085, 0x12 }, - { 0x400fd, 0xf }, - { 0x10011, 0x1 }, - { 0x10012, 0x1 }, - { 0x10013, 0x180 }, - { 0x10018, 0x1 }, - { 0x10002, 0x6209 }, - { 0x100b2, 0x1 }, - { 0x101b4, 0x1 }, - { 0x102b4, 0x1 }, - { 0x103b4, 0x1 }, - { 0x104b4, 0x1 }, - { 0x105b4, 0x1 }, - { 0x106b4, 0x1 }, - { 0x107b4, 0x1 }, - { 0x108b4, 0x1 }, - { 0x11011, 0x1 }, - { 0x11012, 0x1 }, - { 0x11013, 0x180 }, - { 0x11018, 0x1 }, - { 0x11002, 0x6209 }, - { 0x110b2, 0x1 }, - { 0x111b4, 0x1 }, - { 0x112b4, 0x1 }, - { 0x113b4, 0x1 }, - { 0x114b4, 0x1 }, - { 0x115b4, 0x1 }, - { 0x116b4, 0x1 }, - { 0x117b4, 0x1 }, - { 0x118b4, 0x1 }, - { 0x12011, 0x1 }, - { 0x12012, 0x1 }, - { 0x12013, 0x180 }, - { 0x12018, 0x1 }, - { 0x12002, 0x6209 }, - { 0x120b2, 0x1 }, - { 0x121b4, 0x1 }, - { 0x122b4, 0x1 }, - { 0x123b4, 0x1 }, - { 0x124b4, 0x1 }, - { 0x125b4, 0x1 }, - { 0x126b4, 0x1 }, - { 0x127b4, 0x1 }, - { 0x128b4, 0x1 }, - { 0x13011, 0x1 }, - { 0x13012, 0x1 }, - { 0x13013, 0x180 }, - { 0x13018, 0x1 }, - { 0x13002, 0x6209 }, - { 0x130b2, 0x1 }, - { 0x131b4, 0x1 }, - { 0x132b4, 0x1 }, - { 0x133b4, 0x1 }, - { 0x134b4, 0x1 }, - { 0x135b4, 0x1 }, - { 0x136b4, 0x1 }, - { 0x137b4, 0x1 }, - { 0x138b4, 0x1 }, - { 0x2003a, 0x2 }, - { 0xc0080, 0x2 }, - { 0xd0000, 0x1 }, -}; - -struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { - { - /* P0 3200mts 1D */ - .drate = 3200, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = lpddr4_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), - }, - { - /* P1 400mts 1D */ - .drate = 400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = lpddr4_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), - }, - { - /* P1 100mts 1D */ - .drate = 100, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = lpddr4_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), - }, - { - /* P0 3200mts 2D */ - .drate = 3200, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = lpddr4_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), - }, -}; - -/* lpddr4 timing config params on EVK board */ -struct dram_timing_info dram_timing = { - .ddrc_cfg = lpddr4_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), - .ddrphy_cfg = lpddr4_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), - .fsp_msg = lpddr4_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), - .ddrphy_pie = lpddr4_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), - .fsp_table = { 3200, 400, 100, }, -}; diff --git a/board/freescale/imx8mq_evk/lpddr4_timing_b0.c b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c deleted file mode 100644 index 5d8f2803be6..00000000000 --- a/board/freescale/imx8mq_evk/lpddr4_timing_b0.c +++ /dev/null @@ -1,1190 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 NXP - */ - -#include -#include -#include - -#define WR_POST_EXT_3200 /* recommened to define */ - -static struct dram_cfg_param lpddr4_ddrc_cfg[] = { - /* Start to config, default 3200mbps */ - /* dis_dq=1, indicates no reads or writes are issued to SDRAM */ - { DDRC_DBG1(0), 0x00000001 }, - /* selfref_en=1, SDRAM enter self-refresh state */ - { DDRC_PWRCTL(0), 0x00000001 }, - { DDRC_MSTR(0), 0xa3080020 }, - { DDRC_MSTR2(0), 0x00000000 }, - { DDRC_RFSHTMG(0), 0x006100E0 }, - { DDRC_INIT0(0), 0xC003061B }, - { DDRC_INIT1(0), 0x009D0000 }, - { DDRC_INIT3(0), 0x00D4002D }, -#ifdef WR_POST_EXT_3200 /* recommened to define */ - { DDRC_INIT4(0), 0x00330008 }, -#else - { DDRC_INIT4(0), 0x00310008 }, -#endif - { DDRC_INIT6(0), 0x0066004a }, - { DDRC_INIT7(0), 0x0006004a }, - - { DDRC_DRAMTMG0(0), 0x1A201B22 }, - { DDRC_DRAMTMG1(0), 0x00060633 }, - { DDRC_DRAMTMG3(0), 0x00C0C000 }, - { DDRC_DRAMTMG4(0), 0x0F04080F }, - { DDRC_DRAMTMG5(0), 0x02040C0C }, - { DDRC_DRAMTMG6(0), 0x01010007 }, - { DDRC_DRAMTMG7(0), 0x00000401 }, - { DDRC_DRAMTMG12(0), 0x00020600 }, - { DDRC_DRAMTMG13(0), 0x0C100002 }, - { DDRC_DRAMTMG14(0), 0x000000E6 }, - { DDRC_DRAMTMG17(0), 0x00A00050 }, - - { DDRC_ZQCTL0(0), 0x03200018 }, - { DDRC_ZQCTL1(0), 0x028061A8 }, - { DDRC_ZQCTL2(0), 0x00000000 }, - - { DDRC_DFITMG0(0), 0x0497820A }, - { DDRC_DFITMG1(0), 0x00080303 }, - { DDRC_DFIUPD0(0), 0xE0400018 }, - { DDRC_DFIUPD1(0), 0x00DF00E4 }, - { DDRC_DFIUPD2(0), 0x80000000 }, - { DDRC_DFIMISC(0), 0x00000011 }, - { DDRC_DFITMG2(0), 0x0000170A }, - - { DDRC_DBICTL(0), 0x00000001 }, - { DDRC_DFIPHYMSTR(0), 0x00000001 }, - - /* need be refined by ddrphy trained value */ - { DDRC_RANKCTL(0), 0x00000c99 }, - { DDRC_DRAMTMG2(0), 0x070E171a }, - - /* address mapping */ - /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */ - { DDRC_ADDRMAP0(0), 0x00000015 }, - { DDRC_ADDRMAP3(0), 0x00000000 }, - /* addrmap_col_b10 addrmap_col_b11 set to de-activated (5-bit width) */ - { DDRC_ADDRMAP4(0), 0x00001F1F }, - /* bank interleave */ - /* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */ - { DDRC_ADDRMAP1(0), 0x00080808 }, - /* addrmap_row_b11 addrmap_row_b10_b2 addrmap_row_b1 addrmap_row_b0 */ - { DDRC_ADDRMAP5(0), 0x07070707 }, - /* addrmap_row_b15 addrmap_row_b14 addrmap_row_b13 addrmap_row_b12 */ - { DDRC_ADDRMAP6(0), 0x08080707 }, - - /* 667mts frequency setting */ - { DDRC_FREQ1_DERATEEN(0), 0x0000000 }, - { DDRC_FREQ1_DERATEINT(0), 0x0800000 }, - { DDRC_FREQ1_RFSHCTL0(0), 0x0210000 }, - { DDRC_FREQ1_RFSHTMG(0), 0x014001E }, - { DDRC_FREQ1_INIT3(0), 0x0140009 }, - { DDRC_FREQ1_INIT4(0), 0x00310008 }, - { DDRC_FREQ1_INIT6(0), 0x0066004a }, - { DDRC_FREQ1_INIT7(0), 0x0006004a }, - { DDRC_FREQ1_DRAMTMG0(0), 0xB070A07 }, - { DDRC_FREQ1_DRAMTMG1(0), 0x003040A }, - { DDRC_FREQ1_DRAMTMG2(0), 0x305080C }, - { DDRC_FREQ1_DRAMTMG3(0), 0x0505000 }, - { DDRC_FREQ1_DRAMTMG4(0), 0x3040203 }, - { DDRC_FREQ1_DRAMTMG5(0), 0x2030303 }, - { DDRC_FREQ1_DRAMTMG6(0), 0x2020004 }, - { DDRC_FREQ1_DRAMTMG7(0), 0x0000302 }, - { DDRC_FREQ1_DRAMTMG12(0), 0x0020310 }, - { DDRC_FREQ1_DRAMTMG13(0), 0xA100002 }, - { DDRC_FREQ1_DRAMTMG14(0), 0x0000020 }, - { DDRC_FREQ1_DRAMTMG17(0), 0x0220011 }, - { DDRC_FREQ1_ZQCTL0(0), 0x0A70005 }, - { DDRC_FREQ1_DFITMG0(0), 0x3858202 }, - { DDRC_FREQ1_DFITMG1(0), 0x0000404 }, - { DDRC_FREQ1_DFITMG2(0), 0x0000502 }, - - /* performance setting */ - { DDRC_ODTCFG(0), 0x0b060908 }, - { DDRC_ODTMAP(0), 0x00000000 }, - { DDRC_SCHED(0), 0x29511505 }, - { DDRC_SCHED1(0), 0x0000002c }, - { DDRC_PERFHPR1(0), 0x5900575b }, - /* 150T starve and 0x90 max tran len */ - { DDRC_PERFLPR1(0), 0x90000096 }, - /* 300T starve and 0x10 max tran len */ - { DDRC_PERFWR1(0), 0x1000012c }, - { DDRC_DBG0(0), 0x00000016 }, - { DDRC_DBG1(0), 0x00000000 }, - { DDRC_DBGCMD(0), 0x00000000 }, - { DDRC_SWCTL(0), 0x00000001 }, - { DDRC_POISONCFG(0), 0x00000011 }, - { DDRC_PCCFG(0), 0x00000111 }, - { DDRC_PCFGR_0(0), 0x000010f3 }, - { DDRC_PCFGW_0(0), 0x000072ff }, - { DDRC_PCTRL_0(0), 0x00000001 }, - /* disable Read Qos*/ - { DDRC_PCFGQOS0_0(0), 0x00000e00 }, - { DDRC_PCFGQOS1_0(0), 0x0062ffff }, - /* disable Write Qos*/ - { DDRC_PCFGWQOS0_0(0), 0x00000e00 }, - { DDRC_PCFGWQOS1_0(0), 0x0000ffff }, - { DDRC_FREQ1_DERATEEN(0), 0x00000202 }, - { DDRC_FREQ1_DERATEINT(0), 0xec78f4b5 }, - { DDRC_FREQ1_RFSHCTL0(0), 0x00618040 }, - { DDRC_FREQ1_RFSHTMG(0), 0x00610090 }, -}; - -/* PHY Initialize Configuration */ -static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { - { 0x20110, 0x02 }, /* MapCAB0toDFI */ - { 0x20111, 0x03 }, /* MapCAB1toDFI */ - { 0x20112, 0x04 }, /* MapCAB2toDFI */ - { 0x20113, 0x05 }, /* MapCAB3toDFI */ - { 0x20114, 0x00 }, /* MapCAB4toDFI */ - { 0x20115, 0x01 }, /* MapCAB5toDFI */ - - /* Initialize PHY Configuration */ - { 0x1005f, 0x1ff }, - { 0x1015f, 0x1ff }, - { 0x1105f, 0x1ff }, - { 0x1115f, 0x1ff }, - { 0x1205f, 0x1ff }, - { 0x1215f, 0x1ff }, - { 0x1305f, 0x1ff }, - { 0x1315f, 0x1ff }, - - { 0x11005f, 0x1ff }, - { 0x11015f, 0x1ff }, - { 0x11105f, 0x1ff }, - { 0x11115f, 0x1ff }, - { 0x11205f, 0x1ff }, - { 0x11215f, 0x1ff }, - { 0x11305f, 0x1ff }, - { 0x11315f, 0x1ff }, - - { 0x21005f, 0x1ff }, - { 0x21015f, 0x1ff }, - { 0x21105f, 0x1ff }, - { 0x21115f, 0x1ff }, - { 0x21205f, 0x1ff }, - { 0x21215f, 0x1ff }, - { 0x21305f, 0x1ff }, - { 0x21315f, 0x1ff }, - - { 0x55, 0x1ff }, - { 0x1055, 0x1ff }, - { 0x2055, 0x1ff }, - { 0x3055, 0x1ff }, - { 0x4055, 0x1ff }, - { 0x5055, 0x1ff }, - { 0x6055, 0x1ff }, - { 0x7055, 0x1ff }, - { 0x8055, 0x1ff }, - { 0x9055, 0x1ff }, - { 0x200c5, 0x19 }, - { 0x1200c5, 0x7 }, - { 0x2200c5, 0x7 }, - { 0x2002e, 0x2 }, - { 0x12002e, 0x1 }, - { 0x22002e, 0x2 }, - { 0x90204, 0x0 }, - { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - - { 0x20024, 0xe3 }, - { 0x2003a, 0x2 }, - { 0x120024, 0xa3 }, - { 0x2003a, 0x2 }, - { 0x220024, 0xa3 }, - { 0x2003a, 0x2 }, - - { 0x20056, 0x3 }, - { 0x120056, 0xa }, - { 0x220056, 0xa }, - - { 0x1004d, 0xe00 }, - { 0x1014d, 0xe00 }, - { 0x1104d, 0xe00 }, - { 0x1114d, 0xe00 }, - { 0x1204d, 0xe00 }, - { 0x1214d, 0xe00 }, - { 0x1304d, 0xe00 }, - { 0x1314d, 0xe00 }, - { 0x11004d, 0xe00 }, - { 0x11014d, 0xe00 }, - { 0x11104d, 0xe00 }, - { 0x11114d, 0xe00 }, - { 0x11204d, 0xe00 }, - { 0x11214d, 0xe00 }, - { 0x11304d, 0xe00 }, - { 0x11314d, 0xe00 }, - { 0x21004d, 0xe00 }, - { 0x21014d, 0xe00 }, - { 0x21104d, 0xe00 }, - { 0x21114d, 0xe00 }, - { 0x21204d, 0xe00 }, - { 0x21214d, 0xe00 }, - { 0x21304d, 0xe00 }, - { 0x21314d, 0xe00 }, - - { 0x10049, 0xfbe }, - { 0x10149, 0xfbe }, - { 0x11049, 0xfbe }, - { 0x11149, 0xfbe }, - { 0x12049, 0xfbe }, - { 0x12149, 0xfbe }, - { 0x13049, 0xfbe }, - { 0x13149, 0xfbe }, - - { 0x110049, 0xfbe }, - { 0x110149, 0xfbe }, - { 0x111049, 0xfbe }, - { 0x111149, 0xfbe }, - { 0x112049, 0xfbe }, - { 0x112149, 0xfbe }, - { 0x113049, 0xfbe }, - { 0x113149, 0xfbe }, - - { 0x210049, 0xfbe }, - { 0x210149, 0xfbe }, - { 0x211049, 0xfbe }, - { 0x211149, 0xfbe }, - { 0x212049, 0xfbe }, - { 0x212149, 0xfbe }, - { 0x213049, 0xfbe }, - { 0x213149, 0xfbe }, - - { 0x43, 0x63 }, - { 0x1043, 0x63 }, - { 0x2043, 0x63 }, - { 0x3043, 0x63 }, - { 0x4043, 0x63 }, - { 0x5043, 0x63 }, - { 0x6043, 0x63 }, - { 0x7043, 0x63 }, - { 0x8043, 0x63 }, - { 0x9043, 0x63 }, - - { 0x20018, 0x3 }, - { 0x20075, 0x4 }, - { 0x20050, 0x0 }, - { 0x20008, 0x320 }, - { 0x120008, 0xa7 }, - { 0x220008, 0x19 }, - { 0x20088, 0x9 }, - { 0x200b2, 0x104 }, - { 0x10043, 0x5a1 }, - { 0x10143, 0x5a1 }, - { 0x11043, 0x5a1 }, - { 0x11143, 0x5a1 }, - { 0x12043, 0x5a1 }, - { 0x12143, 0x5a1 }, - { 0x13043, 0x5a1 }, - { 0x13143, 0x5a1 }, - { 0x1200b2, 0x104 }, - { 0x110043, 0x5a1 }, - { 0x110143, 0x5a1 }, - { 0x111043, 0x5a1 }, - { 0x111143, 0x5a1 }, - { 0x112043, 0x5a1 }, - { 0x112143, 0x5a1 }, - { 0x113043, 0x5a1 }, - { 0x113143, 0x5a1 }, - { 0x2200b2, 0x104 }, - { 0x210043, 0x5a1 }, - { 0x210143, 0x5a1 }, - { 0x211043, 0x5a1 }, - { 0x211143, 0x5a1 }, - { 0x212043, 0x5a1 }, - { 0x212143, 0x5a1 }, - { 0x213043, 0x5a1 }, - { 0x213143, 0x5a1 }, - { 0x200fa, 0x1 }, - { 0x1200fa, 0x1 }, - { 0x2200fa, 0x1 }, - { 0x20019, 0x1 }, - { 0x120019, 0x1 }, - { 0x220019, 0x1 }, - { 0x200f0, 0x600 }, - { 0x200f1, 0x0 }, - { 0x200f2, 0x4444 }, - { 0x200f3, 0x8888 }, - { 0x200f4, 0x5655 }, - { 0x200f5, 0x0 }, - { 0x200f6, 0x0 }, - { 0x200f7, 0xf000 }, - { 0x20025, 0x0 }, - { 0x2002d, 0x0 }, - { 0x12002d, 0x0 }, - { 0x22002d, 0x0 }, -}; - -/* P0 message block paremeter for training firmware */ -static struct dram_cfg_param lpddr4_fsp0_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, - { 0x54002, 0x0 }, - { 0x54003, 0xc80 }, - { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, - { 0x54008, 0x131f }, - { 0x54009, LPDDR4_HDT_CTL_3200_1D }, - { 0x5400a, 0x0 }, - { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, - { 0x54012, 0x310 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, - { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, - { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, - { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, - { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, - { 0x54032, 0xd400 }, - { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, - { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, - { 0x54038, 0xd400 }, - { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, - { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, - { 0xd0000, 0x1 }, -}; - -/* P1 message block paremeter for training firmware */ -static struct dram_cfg_param lpddr4_fsp1_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, - { 0x54002, 0x1 }, - { 0x54003, 0x29c }, - { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400a, 0x0 }, - { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, 0x0 }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, - { 0x54012, 0x310 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, - { 0x54019, 0x914 }, - { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, - { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, - { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, - { 0x5401e, 0x6 }, - { 0x5401f, 0x914 }, - { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, - { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, - { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, - { 0x54032, 0x1400 }, - { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 }, - { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, - { 0x54037, 0x600 }, - { 0x54038, 0x1400 }, - { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 }, - { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0xd0000, 0x1 }, - -}; - -/* P0 2D message block paremeter for training firmware */ -static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, - { 0x54002, 0x0 }, - { 0x54003, 0xc80 }, - { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, - { 0x54008, 0x61 }, - { 0x54009, LPDDR4_HDT_CTL_2D }, - { 0x5400a, 0x0 }, - { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) }, - { 0x5400e, 0x0 }, - { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 }, - { 0x54010, LPDDR4_2D_WEIGHT }, - { 0x54011, 0x0 }, - { 0x54012, 0x310 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, - { 0x54024, 0x5 }, - { 0x54019, 0x2dd4 }, - { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, - { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, - { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0 }, - { 0x5401f, 0x2dd4 }, - { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, - { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, - { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, - { 0x54032, 0xd400 }, - { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, - { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, - { 0x54038, 0xd400 }, - { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, - { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, - { 0xd0000, 0x1 }, - -}; - -/* DRAM PHY init engine image */ -static struct dram_cfg_param lpddr4_phy_pie[] = { - { 0xd0000, 0x0 }, - { 0x90000, 0x10 }, - { 0x90001, 0x400 }, - { 0x90002, 0x10e }, - { 0x90003, 0x0 }, - { 0x90004, 0x0 }, - { 0x90005, 0x8 }, - { 0x90029, 0xb }, - { 0x9002a, 0x480 }, - { 0x9002b, 0x109 }, - { 0x9002c, 0x8 }, - { 0x9002d, 0x448 }, - { 0x9002e, 0x139 }, - { 0x9002f, 0x8 }, - { 0x90030, 0x478 }, - { 0x90031, 0x109 }, - { 0x90032, 0x0 }, - { 0x90033, 0xe8 }, - { 0x90034, 0x109 }, - { 0x90035, 0x2 }, - { 0x90036, 0x10 }, - { 0x90037, 0x139 }, - { 0x90038, 0xb }, - { 0x90039, 0x7c0 }, - { 0x9003a, 0x139 }, - { 0x9003b, 0x44 }, - { 0x9003c, 0x630 }, - { 0x9003d, 0x159 }, - { 0x9003e, 0x14f }, - { 0x9003f, 0x630 }, - { 0x90040, 0x159 }, - { 0x90041, 0x47 }, - { 0x90042, 0x630 }, - { 0x90043, 0x149 }, - { 0x90044, 0x4f }, - { 0x90045, 0x630 }, - { 0x90046, 0x179 }, - { 0x90047, 0x8 }, - { 0x90048, 0xe0 }, - { 0x90049, 0x109 }, - { 0x9004a, 0x0 }, - { 0x9004b, 0x7c8 }, - { 0x9004c, 0x109 }, - { 0x9004d, 0x0 }, - { 0x9004e, 0x1 }, - { 0x9004f, 0x8 }, - { 0x90050, 0x0 }, - { 0x90051, 0x45a }, - { 0x90052, 0x9 }, - { 0x90053, 0x0 }, - { 0x90054, 0x448 }, - { 0x90055, 0x109 }, - { 0x90056, 0x40 }, - { 0x90057, 0x630 }, - { 0x90058, 0x179 }, - { 0x90059, 0x1 }, - { 0x9005a, 0x618 }, - { 0x9005b, 0x109 }, - { 0x9005c, 0x40c0 }, - { 0x9005d, 0x630 }, - { 0x9005e, 0x149 }, - { 0x9005f, 0x8 }, - { 0x90060, 0x4 }, - { 0x90061, 0x48 }, - { 0x90062, 0x4040 }, - { 0x90063, 0x630 }, - { 0x90064, 0x149 }, - { 0x90065, 0x0 }, - { 0x90066, 0x4 }, - { 0x90067, 0x48 }, - { 0x90068, 0x40 }, - { 0x90069, 0x630 }, - { 0x9006a, 0x149 }, - { 0x9006b, 0x10 }, - { 0x9006c, 0x4 }, - { 0x9006d, 0x18 }, - { 0x9006e, 0x0 }, - { 0x9006f, 0x4 }, - { 0x90070, 0x78 }, - { 0x90071, 0x549 }, - { 0x90072, 0x630 }, - { 0x90073, 0x159 }, - { 0x90074, 0xd49 }, - { 0x90075, 0x630 }, - { 0x90076, 0x159 }, - { 0x90077, 0x94a }, - { 0x90078, 0x630 }, - { 0x90079, 0x159 }, - { 0x9007a, 0x441 }, - { 0x9007b, 0x630 }, - { 0x9007c, 0x149 }, - { 0x9007d, 0x42 }, - { 0x9007e, 0x630 }, - { 0x9007f, 0x149 }, - { 0x90080, 0x1 }, - { 0x90081, 0x630 }, - { 0x90082, 0x149 }, - { 0x90083, 0x0 }, - { 0x90084, 0xe0 }, - { 0x90085, 0x109 }, - { 0x90086, 0xa }, - { 0x90087, 0x10 }, - { 0x90088, 0x109 }, - { 0x90089, 0x9 }, - { 0x9008a, 0x3c0 }, - { 0x9008b, 0x149 }, - { 0x9008c, 0x9 }, - { 0x9008d, 0x3c0 }, - { 0x9008e, 0x159 }, - { 0x9008f, 0x18 }, - { 0x90090, 0x10 }, - { 0x90091, 0x109 }, - { 0x90092, 0x0 }, - { 0x90093, 0x3c0 }, - { 0x90094, 0x109 }, - { 0x90095, 0x18 }, - { 0x90096, 0x4 }, - { 0x90097, 0x48 }, - { 0x90098, 0x18 }, - { 0x90099, 0x4 }, - { 0x9009a, 0x58 }, - { 0x9009b, 0xa }, - { 0x9009c, 0x10 }, - { 0x9009d, 0x109 }, - { 0x9009e, 0x2 }, - { 0x9009f, 0x10 }, - { 0x900a0, 0x109 }, - { 0x900a1, 0x5 }, - { 0x900a2, 0x7c0 }, - { 0x900a3, 0x109 }, - { 0x900a4, 0xd }, - { 0x900a5, 0x7c0 }, - { 0x900a6, 0x109 }, - { 0x900a7, 0x4 }, - { 0x900a8, 0x7c0 }, - { 0x900a9, 0x109 }, - { 0x40000, 0x811 }, - { 0x40020, 0x880 }, - { 0x40040, 0x0 }, - { 0x40060, 0x0 }, - { 0x40001, 0x4008 }, - { 0x40021, 0x83 }, - { 0x40041, 0x4f }, - { 0x40061, 0x0 }, - { 0x40002, 0x4040 }, - { 0x40022, 0x83 }, - { 0x40042, 0x51 }, - { 0x40062, 0x0 }, - { 0x40003, 0x811 }, - { 0x40023, 0x880 }, - { 0x40043, 0x0 }, - { 0x40063, 0x0 }, - { 0x40004, 0x720 }, - { 0x40024, 0xf }, - { 0x40044, 0x1740 }, - { 0x40064, 0x0 }, - { 0x40005, 0x16 }, - { 0x40025, 0x83 }, - { 0x40045, 0x4b }, - { 0x40065, 0x0 }, - { 0x40006, 0x716 }, - { 0x40026, 0xf }, - { 0x40046, 0x2001 }, - { 0x40066, 0x0 }, - { 0x40007, 0x716 }, - { 0x40027, 0xf }, - { 0x40047, 0x2800 }, - { 0x40067, 0x0 }, - { 0x40008, 0x716 }, - { 0x40028, 0xf }, - { 0x40048, 0xf00 }, - { 0x40068, 0x0 }, - { 0x40009, 0x720 }, - { 0x40029, 0xf }, - { 0x40049, 0x1400 }, - { 0x40069, 0x0 }, - { 0x4000a, 0xe08 }, - { 0x4002a, 0xc15 }, - { 0x4004a, 0x0 }, - { 0x4006a, 0x0 }, - { 0x4000b, 0x623 }, - { 0x4002b, 0x15 }, - { 0x4004b, 0x0 }, - { 0x4006b, 0x0 }, - { 0x4000c, 0x4028 }, - { 0x4002c, 0x80 }, - { 0x4004c, 0x0 }, - { 0x4006c, 0x0 }, - { 0x4000d, 0xe08 }, - { 0x4002d, 0xc1a }, - { 0x4004d, 0x0 }, - { 0x4006d, 0x0 }, - { 0x4000e, 0x623 }, - { 0x4002e, 0x1a }, - { 0x4004e, 0x0 }, - { 0x4006e, 0x0 }, - { 0x4000f, 0x4040 }, - { 0x4002f, 0x80 }, - { 0x4004f, 0x0 }, - { 0x4006f, 0x0 }, - { 0x40010, 0x2604 }, - { 0x40030, 0x15 }, - { 0x40050, 0x0 }, - { 0x40070, 0x0 }, - { 0x40011, 0x708 }, - { 0x40031, 0x5 }, - { 0x40051, 0x0 }, - { 0x40071, 0x2002 }, - { 0x40012, 0x8 }, - { 0x40032, 0x80 }, - { 0x40052, 0x0 }, - { 0x40072, 0x0 }, - { 0x40013, 0x2604 }, - { 0x40033, 0x1a }, - { 0x40053, 0x0 }, - { 0x40073, 0x0 }, - { 0x40014, 0x708 }, - { 0x40034, 0xa }, - { 0x40054, 0x0 }, - { 0x40074, 0x2002 }, - { 0x40015, 0x4040 }, - { 0x40035, 0x80 }, - { 0x40055, 0x0 }, - { 0x40075, 0x0 }, - { 0x40016, 0x60a }, - { 0x40036, 0x15 }, - { 0x40056, 0x1200 }, - { 0x40076, 0x0 }, - { 0x40017, 0x61a }, - { 0x40037, 0x15 }, - { 0x40057, 0x1300 }, - { 0x40077, 0x0 }, - { 0x40018, 0x60a }, - { 0x40038, 0x1a }, - { 0x40058, 0x1200 }, - { 0x40078, 0x0 }, - { 0x40019, 0x642 }, - { 0x40039, 0x1a }, - { 0x40059, 0x1300 }, - { 0x40079, 0x0 }, - { 0x4001a, 0x4808 }, - { 0x4003a, 0x880 }, - { 0x4005a, 0x0 }, - { 0x4007a, 0x0 }, - { 0x900aa, 0x0 }, - { 0x900ab, 0x790 }, - { 0x900ac, 0x11a }, - { 0x900ad, 0x8 }, - { 0x900ae, 0x7aa }, - { 0x900af, 0x2a }, - { 0x900b0, 0x10 }, - { 0x900b1, 0x7b2 }, - { 0x900b2, 0x2a }, - { 0x900b3, 0x0 }, - { 0x900b4, 0x7c8 }, - { 0x900b5, 0x109 }, - { 0x900b6, 0x10 }, - { 0x900b7, 0x10 }, - { 0x900b8, 0x109 }, - { 0x900b9, 0x10 }, - { 0x900ba, 0x2a8 }, - { 0x900bb, 0x129 }, - { 0x900bc, 0x8 }, - { 0x900bd, 0x370 }, - { 0x900be, 0x129 }, - { 0x900bf, 0xa }, - { 0x900c0, 0x3c8 }, - { 0x900c1, 0x1a9 }, - { 0x900c2, 0xc }, - { 0x900c3, 0x408 }, - { 0x900c4, 0x199 }, - { 0x900c5, 0x14 }, - { 0x900c6, 0x790 }, - { 0x900c7, 0x11a }, - { 0x900c8, 0x8 }, - { 0x900c9, 0x4 }, - { 0x900ca, 0x18 }, - { 0x900cb, 0xe }, - { 0x900cc, 0x408 }, - { 0x900cd, 0x199 }, - { 0x900ce, 0x8 }, - { 0x900cf, 0x8568 }, - { 0x900d0, 0x108 }, - { 0x900d1, 0x18 }, - { 0x900d2, 0x790 }, - { 0x900d3, 0x16a }, - { 0x900d4, 0x8 }, - { 0x900d5, 0x1d8 }, - { 0x900d6, 0x169 }, - { 0x900d7, 0x10 }, - { 0x900d8, 0x8558 }, - { 0x900d9, 0x168 }, - { 0x900da, 0x70 }, - { 0x900db, 0x788 }, - { 0x900dc, 0x16a }, - { 0x900dd, 0x1ff8 }, - { 0x900de, 0x85a8 }, - { 0x900df, 0x1e8 }, - { 0x900e0, 0x50 }, - { 0x900e1, 0x798 }, - { 0x900e2, 0x16a }, - { 0x900e3, 0x60 }, - { 0x900e4, 0x7a0 }, - { 0x900e5, 0x16a }, - { 0x900e6, 0x8 }, - { 0x900e7, 0x8310 }, - { 0x900e8, 0x168 }, - { 0x900e9, 0x8 }, - { 0x900ea, 0xa310 }, - { 0x900eb, 0x168 }, - { 0x900ec, 0xa }, - { 0x900ed, 0x408 }, - { 0x900ee, 0x169 }, - { 0x900ef, 0x6e }, - { 0x900f0, 0x0 }, - { 0x900f1, 0x68 }, - { 0x900f2, 0x0 }, - { 0x900f3, 0x408 }, - { 0x900f4, 0x169 }, - { 0x900f5, 0x0 }, - { 0x900f6, 0x8310 }, - { 0x900f7, 0x168 }, - { 0x900f8, 0x0 }, - { 0x900f9, 0xa310 }, - { 0x900fa, 0x168 }, - { 0x900fb, 0x1ff8 }, - { 0x900fc, 0x85a8 }, - { 0x900fd, 0x1e8 }, - { 0x900fe, 0x68 }, - { 0x900ff, 0x798 }, - { 0x90100, 0x16a }, - { 0x90101, 0x78 }, - { 0x90102, 0x7a0 }, - { 0x90103, 0x16a }, - { 0x90104, 0x68 }, - { 0x90105, 0x790 }, - { 0x90106, 0x16a }, - { 0x90107, 0x8 }, - { 0x90108, 0x8b10 }, - { 0x90109, 0x168 }, - { 0x9010a, 0x8 }, - { 0x9010b, 0xab10 }, - { 0x9010c, 0x168 }, - { 0x9010d, 0xa }, - { 0x9010e, 0x408 }, - { 0x9010f, 0x169 }, - { 0x90110, 0x58 }, - { 0x90111, 0x0 }, - { 0x90112, 0x68 }, - { 0x90113, 0x0 }, - { 0x90114, 0x408 }, - { 0x90115, 0x169 }, - { 0x90116, 0x0 }, - { 0x90117, 0x8b10 }, - { 0x90118, 0x168 }, - { 0x90119, 0x0 }, - { 0x9011a, 0xab10 }, - { 0x9011b, 0x168 }, - { 0x9011c, 0x0 }, - { 0x9011d, 0x1d8 }, - { 0x9011e, 0x169 }, - { 0x9011f, 0x80 }, - { 0x90120, 0x790 }, - { 0x90121, 0x16a }, - { 0x90122, 0x18 }, - { 0x90123, 0x7aa }, - { 0x90124, 0x6a }, - { 0x90125, 0xa }, - { 0x90126, 0x0 }, - { 0x90127, 0x1e9 }, - { 0x90128, 0x8 }, - { 0x90129, 0x8080 }, - { 0x9012a, 0x108 }, - { 0x9012b, 0xf }, - { 0x9012c, 0x408 }, - { 0x9012d, 0x169 }, - { 0x9012e, 0xc }, - { 0x9012f, 0x0 }, - { 0x90130, 0x68 }, - { 0x90131, 0x9 }, - { 0x90132, 0x0 }, - { 0x90133, 0x1a9 }, - { 0x90134, 0x0 }, - { 0x90135, 0x408 }, - { 0x90136, 0x169 }, - { 0x90137, 0x0 }, - { 0x90138, 0x8080 }, - { 0x90139, 0x108 }, - { 0x9013a, 0x8 }, - { 0x9013b, 0x7aa }, - { 0x9013c, 0x6a }, - { 0x9013d, 0x0 }, - { 0x9013e, 0x8568 }, - { 0x9013f, 0x108 }, - { 0x90140, 0xb7 }, - { 0x90141, 0x790 }, - { 0x90142, 0x16a }, - { 0x90143, 0x1f }, - { 0x90144, 0x0 }, - { 0x90145, 0x68 }, - { 0x90146, 0x8 }, - { 0x90147, 0x8558 }, - { 0x90148, 0x168 }, - { 0x90149, 0xf }, - { 0x9014a, 0x408 }, - { 0x9014b, 0x169 }, - { 0x9014c, 0xc }, - { 0x9014d, 0x0 }, - { 0x9014e, 0x68 }, - { 0x9014f, 0x0 }, - { 0x90150, 0x408 }, - { 0x90151, 0x169 }, - { 0x90152, 0x0 }, - { 0x90153, 0x8558 }, - { 0x90154, 0x168 }, - { 0x90155, 0x8 }, - { 0x90156, 0x3c8 }, - { 0x90157, 0x1a9 }, - { 0x90158, 0x3 }, - { 0x90159, 0x370 }, - { 0x9015a, 0x129 }, - { 0x9015b, 0x20 }, - { 0x9015c, 0x2aa }, - { 0x9015d, 0x9 }, - { 0x9015e, 0x0 }, - { 0x9015f, 0x400 }, - { 0x90160, 0x10e }, - { 0x90161, 0x8 }, - { 0x90162, 0xe8 }, - { 0x90163, 0x109 }, - { 0x90164, 0x0 }, - { 0x90165, 0x8140 }, - { 0x90166, 0x10c }, - { 0x90167, 0x10 }, - { 0x90168, 0x8138 }, - { 0x90169, 0x10c }, - { 0x9016a, 0x8 }, - { 0x9016b, 0x7c8 }, - { 0x9016c, 0x101 }, - { 0x9016d, 0x8 }, - { 0x9016e, 0x0 }, - { 0x9016f, 0x8 }, - { 0x90170, 0x8 }, - { 0x90171, 0x448 }, - { 0x90172, 0x109 }, - { 0x90173, 0xf }, - { 0x90174, 0x7c0 }, - { 0x90175, 0x109 }, - { 0x90176, 0x0 }, - { 0x90177, 0xe8 }, - { 0x90178, 0x109 }, - { 0x90179, 0x47 }, - { 0x9017a, 0x630 }, - { 0x9017b, 0x109 }, - { 0x9017c, 0x8 }, - { 0x9017d, 0x618 }, - { 0x9017e, 0x109 }, - { 0x9017f, 0x8 }, - { 0x90180, 0xe0 }, - { 0x90181, 0x109 }, - { 0x90182, 0x0 }, - { 0x90183, 0x7c8 }, - { 0x90184, 0x109 }, - { 0x90185, 0x8 }, - { 0x90186, 0x8140 }, - { 0x90187, 0x10c }, - { 0x90188, 0x0 }, - { 0x90189, 0x1 }, - { 0x9018a, 0x8 }, - { 0x9018b, 0x8 }, - { 0x9018c, 0x4 }, - { 0x9018d, 0x8 }, - { 0x9018e, 0x8 }, - { 0x9018f, 0x7c8 }, - { 0x90190, 0x101 }, - { 0x90006, 0x0 }, - { 0x90007, 0x0 }, - { 0x90008, 0x8 }, - { 0x90009, 0x0 }, - { 0x9000a, 0x0 }, - { 0x9000b, 0x0 }, - { 0xd00e7, 0x400 }, - { 0x90017, 0x0 }, - { 0x9001f, 0x2b }, - { 0x90026, 0x6c }, - { 0x400d0, 0x0 }, - { 0x400d1, 0x101 }, - { 0x400d2, 0x105 }, - { 0x400d3, 0x107 }, - { 0x400d4, 0x10f }, - { 0x400d5, 0x202 }, - { 0x400d6, 0x20a }, - { 0x400d7, 0x20b }, - { 0x2003a, 0x2 }, - { 0x2000b, 0x64 }, - { 0x2000c, 0xc8 }, - { 0x2000d, 0x7d0 }, - { 0x2000e, 0x2c }, - { 0x12000b, 0x14 }, - { 0x12000c, 0x29 }, - { 0x12000d, 0x1a1 }, - { 0x12000e, 0x10 }, - { 0x22000b, 0x3 }, - { 0x22000c, 0x6 }, - { 0x22000d, 0x3e }, - { 0x22000e, 0x10 }, - { 0x9000c, 0x0 }, - { 0x9000d, 0x173 }, - { 0x9000e, 0x60 }, - { 0x9000f, 0x6110 }, - { 0x90010, 0x2152 }, - { 0x90011, 0xdfbd }, - { 0x90012, 0x60 }, - { 0x90013, 0x6152 }, - { 0x20010, 0x5a }, - { 0x20011, 0x3 }, - { 0x40080, 0xe0 }, - { 0x40081, 0x12 }, - { 0x40082, 0xe0 }, - { 0x40083, 0x12 }, - { 0x40084, 0xe0 }, - { 0x40085, 0x12 }, - { 0x140080, 0xe0 }, - { 0x140081, 0x12 }, - { 0x140082, 0xe0 }, - { 0x140083, 0x12 }, - { 0x140084, 0xe0 }, - { 0x140085, 0x12 }, - { 0x240080, 0xe0 }, - { 0x240081, 0x12 }, - { 0x240082, 0xe0 }, - { 0x240083, 0x12 }, - { 0x240084, 0xe0 }, - { 0x240085, 0x12 }, - { 0x400fd, 0xf }, - { 0x10011, 0x1 }, - { 0x10012, 0x1 }, - { 0x10013, 0x180 }, - { 0x10018, 0x1 }, - { 0x10002, 0x6209 }, - { 0x100b2, 0x1 }, - { 0x101b4, 0x1 }, - { 0x102b4, 0x1 }, - { 0x103b4, 0x1 }, - { 0x104b4, 0x1 }, - { 0x105b4, 0x1 }, - { 0x106b4, 0x1 }, - { 0x107b4, 0x1 }, - { 0x108b4, 0x1 }, - { 0x11011, 0x1 }, - { 0x11012, 0x1 }, - { 0x11013, 0x180 }, - { 0x11018, 0x1 }, - { 0x11002, 0x6209 }, - { 0x110b2, 0x1 }, - { 0x111b4, 0x1 }, - { 0x112b4, 0x1 }, - { 0x113b4, 0x1 }, - { 0x114b4, 0x1 }, - { 0x115b4, 0x1 }, - { 0x116b4, 0x1 }, - { 0x117b4, 0x1 }, - { 0x118b4, 0x1 }, - { 0x12011, 0x1 }, - { 0x12012, 0x1 }, - { 0x12013, 0x180 }, - { 0x12018, 0x1 }, - { 0x12002, 0x6209 }, - { 0x120b2, 0x1 }, - { 0x121b4, 0x1 }, - { 0x122b4, 0x1 }, - { 0x123b4, 0x1 }, - { 0x124b4, 0x1 }, - { 0x125b4, 0x1 }, - { 0x126b4, 0x1 }, - { 0x127b4, 0x1 }, - { 0x128b4, 0x1 }, - { 0x13011, 0x1 }, - { 0x13012, 0x1 }, - { 0x13013, 0x180 }, - { 0x13018, 0x1 }, - { 0x13002, 0x6209 }, - { 0x130b2, 0x1 }, - { 0x131b4, 0x1 }, - { 0x132b4, 0x1 }, - { 0x133b4, 0x1 }, - { 0x134b4, 0x1 }, - { 0x135b4, 0x1 }, - { 0x136b4, 0x1 }, - { 0x137b4, 0x1 }, - { 0x138b4, 0x1 }, - { 0x20089, 0x1 }, - { 0x20088, 0x19 }, - { 0xc0080, 0x2 }, - { 0xd0000, 0x1 }, -}; - -static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { - { - /* P0 3200mts 1D */ - .drate = 3200, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = lpddr4_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), - }, - { - /* P1 667mts 1D */ - .drate = 667, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = lpddr4_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), - }, - { - /* P0 3200mts 2D */ - .drate = 3200, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = lpddr4_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), - }, -}; - -/* lpddr4 timing config params on EVK board */ -struct dram_timing_info dram_timing_b0 = { - .ddrc_cfg = lpddr4_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), - .ddrphy_cfg = lpddr4_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), - .fsp_msg = lpddr4_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), - .ddrphy_pie = lpddr4_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), - /* - * this table must be initialized if DDRPHY bypass mode is - * not used: all fsp drate > 666MTS. - */ - .fsp_table = { 3200, 667, }, -}; diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c deleted file mode 100644 index a346305c863..00000000000 --- a/board/freescale/imx8mq_evk/spl.c +++ /dev/null @@ -1,256 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018, 2021 NXP - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/pfuze.h" - -DECLARE_GLOBAL_DATA_PTR; - -extern struct dram_timing_info dram_timing_b0; - -static void spl_dram_init(void) -{ - /* ddr init */ - if (soc_rev() >= CHIP_REV_2_1) - ddr_init(&dram_timing); - else - ddr_init(&dram_timing_b0); -} - -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - -#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) -#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) -#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = 1; - break; - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - return ret; - } - - return 1; -} - -#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ - PAD_CTL_FSEL2) -#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) - -static iomux_v3_cfg_t const usdhc1_pads[] = { - IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc2_pads[] = { - IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ - IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), - IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), -}; - -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC1_BASE_ADDR, 0, 8}, - {USDHC2_BASE_ADDR, 0, 4}, -}; - -int board_mmc_init(struct bd_info *bis) -{ - int i, ret; - /* - * According to the board_mmc_init() the following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 USDHC1 - * mmc1 USDHC2 - */ - for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - init_clk_usdhc(0); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, - ARRAY_SIZE(usdhc1_pads)); - gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); - gpio_direction_output(USDHC1_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC1_PWR_GPIO, 1); - break; - case 1: - init_clk_usdhc(1); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, - ARRAY_SIZE(usdhc2_pads)); - gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); - gpio_direction_output(USDHC2_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC2_PWR_GPIO, 1); - break; - default: - printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} - -#if CONFIG_IS_ENABLED(POWER_LEGACY) -#define I2C_PMIC 0 -int power_init_board(void) -{ - struct pmic *p; - int ret; - unsigned int reg; - - ret = power_pfuze100_init(I2C_PMIC); - if (ret) - return -ENODEV; - - p = pmic_get("PFUZE100"); - ret = pmic_probe(p); - if (ret) - return -ENODEV; - - pmic_reg_read(p, PFUZE100_DEVICEID, ®); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); - - pmic_reg_read(p, PFUZE100_SW3AVOL, ®); - if ((reg & 0x3f) != 0x18) { - reg &= ~0x3f; - reg |= 0x18; - pmic_reg_write(p, PFUZE100_SW3AVOL, reg); - } - - ret = pfuze_mode_init(p, APS_PFM); - if (ret < 0) - return ret; - - /* set SW3A standby mode to off */ - pmic_reg_read(p, PFUZE100_SW3AMODE, ®); - reg &= ~0xf; - reg |= APS_OFF; - pmic_reg_write(p, PFUZE100_SW3AMODE, reg); - - return 0; -} -#endif - -void spl_board_init(void) -{ - if (IS_ENABLED(CONFIG_FSL_CAAM)) { - if (sec_init()) - printf("\nsec_init failed!\n"); - } - puts("Normal Boot\n"); -} - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif - -void board_init_f(ulong dummy) -{ - int ret; - - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); - - arch_cpu_init(); - - init_uart_clk(0); - - board_early_init_f(); - - timer_init(); - - preloader_console_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - ret = spl_init(); - if (ret) { - debug("spl_init() failed: %d\n", ret); - hang(); - } - - enable_tzc380(); - - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - - power_init_board(); - - /* DDR initialization */ - spl_dram_init(); - - board_init_r(NULL, 0); -} diff --git a/board/freescale/imx8qm_mek/Kconfig b/board/freescale/imx8qm_mek/Kconfig deleted file mode 100644 index 5f2413f8dbf..00000000000 --- a/board/freescale/imx8qm_mek/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_IMX8QM_MEK - -config SYS_BOARD - default "imx8qm_mek" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "imx8qm_mek" - -config IMX_CONFIG - default "board/freescale/imx8qm_mek/imximage.cfg" - -endif diff --git a/board/freescale/imx8qm_mek/MAINTAINERS b/board/freescale/imx8qm_mek/MAINTAINERS deleted file mode 100644 index 115830df19b..00000000000 --- a/board/freescale/imx8qm_mek/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -i.MX8QM MEK BOARD -M: Peng Fan -S: Maintained -F: board/freescale/imx8qm_mek/ -F: include/configs/imx8qm_mek.h -F: configs/imx8qm_mek_defconfig diff --git a/board/freescale/imx8qm_mek/Makefile b/board/freescale/imx8qm_mek/Makefile deleted file mode 100644 index 53b33a0dfb1..00000000000 --- a/board/freescale/imx8qm_mek/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2018 NXP -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += imx8qm_mek.o -obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/board/freescale/imx8qm_mek/README b/board/freescale/imx8qm_mek/README deleted file mode 100644 index 47fae3d2843..00000000000 --- a/board/freescale/imx8qm_mek/README +++ /dev/null @@ -1,54 +0,0 @@ -U-Boot for the NXP i.MX8QM EVK board - -Quick Start -=========== - -- Build the ARM Trusted firmware binary -- Get scfw_tcm.bin and ahab-container.img -- Build U-Boot -- Flash the binary into the SD card -- Boot - -Get and Build the ARM Trusted firmware -====================================== - -$ git clone https://github.com/nxp-imx/imx-atf -$ cd imx-atf/ -$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga -$ make PLAT=imx8qm bl31 - -And copy the resulting bl31.bin to u-boot directory: - -$ cp build/imx8qm/release/bl31.bin path/to/u-boot/ - -Get scfw_tcm.bin and ahab-container.img -======================================= - -$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin -$ chmod +x imx-sc-firmware-1.1.bin -$ ./imx-sc-firmware-1.1.bin -$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin -$ chmod +x firmware-imx-8.0.bin -$ ./firmware-imx-8.0.bin - - -And copy the following firmwares to U-Boot folder: - -* `imx-sc-firmware-1.1/mx8qm-mek-scfw-tcm.bin` -* `firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img` - -Build U-Boot -============ -$ make imx8qm_mek_defconfig -$ make - -Flash the binary into the SD card -================================= - -Burn the flash.bin binary to SD card offset 32KB: - -$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 - -Boot -==== -Set Boot switch SW2: 001100. diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c deleted file mode 100644 index 72527f774ca..00000000000 --- a/board/freescale/imx8qm_mek/imx8qm_mek.c +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ - (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ - (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ - (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) - -static iomux_cfg_t uart0_pads[] = { - SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); -} - -int board_early_init_f(void) -{ - sc_pm_clock_rate_t rate = SC_80MHZ; - int ret; - - /* Set UART0 clock root to 80 MHz */ - ret = sc_pm_setup_uart(SC_R_UART_0, rate); - if (ret) - return ret; - - setup_iomux_uart(); - - sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON); - - return 0; -} - -#if CONFIG_IS_ENABLED(DM_GPIO) -static void board_gpio_init(void) -{ - /* TODO */ -} -#else -static inline void board_gpio_init(void) {} -#endif - -#if IS_ENABLED(CONFIG_FEC_MXC) -#include - -int board_phy_config(struct phy_device *phydev) -{ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); - - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} -#endif - -int checkboard(void) -{ - puts("Board: iMX8QM MEK\n"); - - build_info(); - print_bootinfo(); - - return 0; -} - -int board_init(void) -{ - /* Power up base board */ - sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON); - - board_gpio_init(); - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - return 0; -} -#endif - -int board_mmc_get_env_dev(int devno) -{ - return devno; -} - -int board_late_init(void) -{ - char *fdt_file; - bool m4_booted; - -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - env_set("board_name", "MEK"); - env_set("board_rev", "iMX8QM"); -#endif - - fdt_file = env_get("fdt_file"); - m4_booted = m4_parts_booted(); - - if (fdt_file && !strcmp(fdt_file, "undefined")) { - if (m4_booted) - env_set("fdt_file", "imx8qm-mek-rpmsg.dtb"); - else - env_set("fdt_file", "imx8qm-mek.dtb"); - } - - return 0; -} diff --git a/board/freescale/imx8qm_mek/imximage.cfg b/board/freescale/imx8qm_mek/imximage.cfg deleted file mode 100644 index 71612678c99..00000000000 --- a/board/freescale/imx8qm_mek/imximage.cfg +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - - -/* Boot from SD, sector size 0x400 */ -BOOT_FROM SD 0x400 -/* SoC type IMX8QM */ -SOC_TYPE IMX8QM -/* Append seco container image */ -APPEND mx8qm-ahab-container.img -/* Create the 2nd container */ -CONTAINER -/* Add scfw image with exec attribute */ -IMAGE SCU mx8qm-mek-scfw-tcm.bin -/* Add ATF image with exec attribute */ -IMAGE A35 spl/u-boot-spl.bin 0x00100000 diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c deleted file mode 100644 index ad786833309..00000000000 --- a/board/freescale/imx8qm_mek/spl.c +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2018, 2021 NXP - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void spl_board_init(void) -{ - struct udevice *dev; - - uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev); - - uclass_find_first_device(UCLASS_MISC, &dev); - - for (; dev; uclass_find_next_device(&dev)) { - if (device_probe(dev)) - continue; - } - - arch_cpu_init(); - - board_early_init_f(); - - timer_init(); - - preloader_console_init(); - - puts("Normal Boot\n"); -} - -void spl_board_prepare_for_boot(void) -{ - imx8_power_off_pd_devices(NULL, 0); -} - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif - -void board_init_f(ulong dummy) -{ - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - board_init_r(NULL, 0); -} diff --git a/board/freescale/imx8qm_mek/uboot-container.cfg b/board/freescale/imx8qm_mek/uboot-container.cfg deleted file mode 100644 index e25aa76fe18..00000000000 --- a/board/freescale/imx8qm_mek/uboot-container.cfg +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 NXP - */ - - -/* This file is to create a container image could be loaded by SPL */ -BOOT_FROM SD 0x400 -SOC_TYPE IMX8QM -CONTAINER -IMAGE A35 bl31.bin 0x80000000 -IMAGE A35 u-boot.bin CONFIG_TEXT_BASE diff --git a/board/freescale/imx8qxp_mek/Kconfig b/board/freescale/imx8qxp_mek/Kconfig deleted file mode 100644 index 6533b4d9535..00000000000 --- a/board/freescale/imx8qxp_mek/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_IMX8QXP_MEK - -config SYS_BOARD - default "imx8qxp_mek" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "imx8qxp_mek" - -config IMX_CONFIG - default "board/freescale/imx8qxp_mek/imximage.cfg" - -endif diff --git a/board/freescale/imx8qxp_mek/MAINTAINERS b/board/freescale/imx8qxp_mek/MAINTAINERS deleted file mode 100644 index 3a21f5521d8..00000000000 --- a/board/freescale/imx8qxp_mek/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -i.MX8QXP MEK BOARD -M: Peng Fan -M: Fabio Estevam -S: Maintained -F: board/freescale/imx8qxp_mek/ -F: include/configs/imx8qxp_mek.h -F: configs/imx8qxp_mek_defconfig diff --git a/board/freescale/imx8qxp_mek/Makefile b/board/freescale/imx8qxp_mek/Makefile deleted file mode 100644 index 459ec771eea..00000000000 --- a/board/freescale/imx8qxp_mek/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2017 NXP -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += imx8qxp_mek.o -obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c deleted file mode 100644 index adb9556a021..00000000000 --- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ - (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ - (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ - (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) - -#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ - (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ - (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ - (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) - -static iomux_cfg_t uart0_pads[] = { - SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); -} - -int board_early_init_f(void) -{ - sc_pm_clock_rate_t rate = SC_80MHZ; - int ret; - - /* Set UART0 clock root to 80 MHz */ - ret = sc_pm_setup_uart(SC_R_UART_0, rate); - if (ret) - return ret; - - setup_iomux_uart(); - - return 0; -} - -#if CONFIG_IS_ENABLED(DM_GPIO) -static void board_gpio_init(void) -{ - struct gpio_desc desc; - int ret; - - ret = dm_gpio_lookup_name("gpio@1a_3", &desc); - if (ret) - return; - - ret = dm_gpio_request(&desc, "bb_per_rst_b"); - if (ret) - return; - - dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); - dm_gpio_set_value(&desc, 0); - udelay(50); - dm_gpio_set_value(&desc, 1); -} -#else -static inline void board_gpio_init(void) {} -#endif - -#if IS_ENABLED(CONFIG_FEC_MXC) -#include - -int board_phy_config(struct phy_device *phydev) -{ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); - - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} -#endif - -int checkboard(void) -{ - puts("Board: iMX8QXP MEK\n"); - - build_info(); - print_bootinfo(); - - return 0; -} - -int board_init(void) -{ - board_gpio_init(); - -#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO - { - int ret = snvs_security_sc_init(); - - if (ret) - return ret; - } -#endif - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - return 0; -} -#endif - -int board_mmc_get_env_dev(int devno) -{ - return devno; -} - -int board_late_init(void) -{ - char *fdt_file; - bool m4_booted; - -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - env_set("board_name", "MEK"); - env_set("board_rev", "iMX8QXP"); -#endif - - fdt_file = env_get("fdt_file"); - m4_booted = m4_parts_booted(); - - if (fdt_file && !strcmp(fdt_file, "undefined")) { - if (m4_booted) - env_set("fdt_file", "imx8qxp-mek-rpmsg.dtb"); - else - env_set("fdt_file", "imx8qxp-mek.dtb"); - } - - return 0; -} diff --git a/board/freescale/imx8qxp_mek/imximage.cfg b/board/freescale/imx8qxp_mek/imximage.cfg deleted file mode 100644 index 88d6955a9ef..00000000000 --- a/board/freescale/imx8qxp_mek/imximage.cfg +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - * - * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure - * and create imx8image boot image - */ - - -BOOT_FROM sd -/* SoC type IMX8QX */ -SOC_TYPE IMX8QX -/* Append seco container image */ -APPEND ahab-container.img -/* Create the 2nd container */ -CONTAINER -/* Add scfw image with exec attribute */ -IMAGE SCU mx8qx-mek-scfw-tcm.bin -/* Add ATF image with exec attribute */ -IMAGE A35 spl/u-boot-spl.bin 0x00100000 diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c deleted file mode 100644 index 05e3c0a2ff2..00000000000 --- a/board/freescale/imx8qxp_mek/spl.c +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2018, 2021 NXP - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ - (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ - (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ - (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) - -#define USDHC2_SD_PWR IMX_GPIO_NR(4, 19) -static iomux_cfg_t usdhc2_sd_pwr[] = { - SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(GPIO_PAD_CTRL), -}; - -void spl_board_init(void) -{ - struct udevice *dev; - - uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev); - - uclass_find_first_device(UCLASS_MISC, &dev); - - for (; dev; uclass_find_next_device(&dev)) { - if (device_probe(dev)) - continue; - } - - arch_cpu_init(); - - board_early_init_f(); - - timer_init(); - - imx8_iomux_setup_multiple_pads(usdhc2_sd_pwr, ARRAY_SIZE(usdhc2_sd_pwr)); - gpio_direction_output(USDHC2_SD_PWR, 0); - - preloader_console_init(); - - puts("Normal Boot\n"); -} - -void spl_board_prepare_for_boot(void) -{ - imx8_power_off_pd_devices(NULL, 0); -} - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif - -void board_init_f(ulong dummy) -{ - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - board_init_r(NULL, 0); -} diff --git a/board/freescale/imx8qxp_mek/uboot-container.cfg b/board/freescale/imx8qxp_mek/uboot-container.cfg deleted file mode 100644 index b481c98f929..00000000000 --- a/board/freescale/imx8qxp_mek/uboot-container.cfg +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 NXP - */ - - -/* This file is to create a container image could be loaded by SPL */ -BOOT_FROM SD 0x400 -SOC_TYPE IMX8QX -CONTAINER -IMAGE A35 bl31.bin 0x80000000 -IMAGE A35 u-boot.bin CONFIG_TEXT_BASE diff --git a/board/freescale/imx8ulp_evk/Kconfig b/board/freescale/imx8ulp_evk/Kconfig deleted file mode 100644 index 4637b969be6..00000000000 --- a/board/freescale/imx8ulp_evk/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_IMX8ULP_EVK - -config SYS_BOARD - default "imx8ulp_evk" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "imx8ulp_evk" - -endif diff --git a/board/freescale/imx8ulp_evk/MAINTAINERS b/board/freescale/imx8ulp_evk/MAINTAINERS deleted file mode 100644 index 267b7b0caa5..00000000000 --- a/board/freescale/imx8ulp_evk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -i.MX8ULP EVK BOARD -M: Peng Fan -S: Maintained -F: board/freescale/imx8ulp_evk/ -F: include/configs/imx8ulp_evk.h -F: configs/imx8ulp_evk_defconfig diff --git a/board/freescale/imx8ulp_evk/Makefile b/board/freescale/imx8ulp_evk/Makefile deleted file mode 100644 index 7819b2675b3..00000000000 --- a/board/freescale/imx8ulp_evk/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ - -obj-y += imx8ulp_evk.o - -ifdef CONFIG_XPL_BUILD -obj-y += spl.o -ifdef CONFIG_IMX8ULP_ND_MODE -obj-y += lpddr4_timing_264.o -else -obj-y += lpddr4_timing.o -endif -endif diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c deleted file mode 100644 index 4bf77a488cc..00000000000 --- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2020 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if IS_ENABLED(CONFIG_FEC_MXC) -#define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_UP | PAD_CTL_DSE | PAD_CTL_IBE_ENABLE) -static iomux_cfg_t const enet_clk_pads[] = { - IMX8ULP_PAD_PTE19__ENET0_REFCLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), - IMX8ULP_PAD_PTF10__ENET0_1588_CLKIN | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), -}; - -static int setup_fec(void) -{ - /* - * Since ref clock and timestamp clock are from external, - * set the iomux prior the clock enablement - */ - imx8ulp_iomux_setup_multiple_pads(enet_clk_pads, ARRAY_SIZE(enet_clk_pads)); - - /* Select enet time stamp clock: 001 - External Timestamp Clock */ - cgc1_enet_stamp_sel(1); - - /* enable FEC PCC */ - pcc_clock_enable(4, ENET_PCC4_SLOT, true); - pcc_reset_peripheral(4, ENET_PCC4_SLOT, false); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - return 0; -} -#endif - -#define I2C_PAD_CTRL (PAD_CTL_ODE) -static const iomux_cfg_t lpi2c0_pads[] = { - IMX8ULP_PAD_PTA8__LPI2C0_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), - IMX8ULP_PAD_PTA9__LPI2C0_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), -}; - -#define TPM_PAD_CTRL (PAD_CTL_DSE) -static const iomux_cfg_t tpm0_pads[] = { - IMX8ULP_PAD_PTA3__TPM0_CH2 | MUX_PAD_CTRL(TPM_PAD_CTRL), -}; - -void mipi_dsi_mux_panel(void) -{ - int ret; - struct gpio_desc desc; - - /* It is temp solution to directly access i2c, need change to rpmsg later */ - - /* enable lpi2c0 clock and iomux */ - imx8ulp_iomux_setup_multiple_pads(lpi2c0_pads, ARRAY_SIZE(lpi2c0_pads)); - writel(0xD2000000, 0x28091060); - - ret = dm_gpio_lookup_name("gpio@20_9", &desc); - if (ret) { - printf("%s lookup gpio@20_9 failed ret = %d\n", __func__, ret); - return; - } - - ret = dm_gpio_request(&desc, "dsi_mux"); - if (ret) { - printf("%s request dsi_mux failed ret = %d\n", __func__, ret); - return; - } - - dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); -} - -void mipi_dsi_panel_backlight(void) -{ - /* It is temp solution to directly access pwm, need change to rpmsg later */ - imx8ulp_iomux_setup_multiple_pads(tpm0_pads, ARRAY_SIZE(tpm0_pads)); - writel(0xD4000001, 0x28091054); - - /* Use center-aligned PWM mode, CPWMS=1, MSnB:MSnA = 10, ELSnB:ELSnA = 00 */ - writel(1000, 0x28095018); - writel(1000, 0x28095034); /* MOD = CV, full duty */ - writel(0x28, 0x28095010); - writel(0x20, 0x28095030); -} - -int board_init(void) -{ - - if (IS_ENABLED(CONFIG_FEC_MXC)) - setup_fec(); - - /* When sync with M33 is failed, use local driver to set for video */ - if (!is_m33_handshake_necessary() && IS_ENABLED(CONFIG_VIDEO)) { - mipi_dsi_mux_panel(); - mipi_dsi_panel_backlight(); - } - - return 0; -} - -int board_early_init_f(void) -{ - return 0; -} - -int board_late_init(void) -{ - ulong addr; - -#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) - board_late_mmc_env_init(); -#endif - - /* clear fdtaddr to avoid obsolete data */ - addr = env_get_hex("fdt_addr_r", 0); - if (addr) - memset((void *)addr, 0, 0x400); - - return 0; -} diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.env b/board/freescale/imx8ulp_evk/imx8ulp_evk.env deleted file mode 100644 index 52d7f447029..00000000000 --- a/board/freescale/imx8ulp_evk/imx8ulp_evk.env +++ /dev/null @@ -1,97 +0,0 @@ -#ifdef CONFIG_AHAB_BOOT -sec_boot=yes -#else -sec_boot=no -#endif - -jh_clk= -jh_mmcboot=setenv jh_clk kvm.enable_virt_at_load=false clk_ignore_unused mem=896MB; run loadimage; \ - run mmcboot -jh_netboot=setenv jh_clk kvm.enable_virt_at_load=false clk_ignore_unused mem=896MB; run netboot - -initrd_addr=0x83800000 -scriptaddr=0x83500000 -splashimage=0x90000000 -kernel_addr_r=CONFIG_SYS_LOAD_ADDR -fdtoverlay_addr_r=0x83040000 -fdt_addr_r=0x83000000 -fdt_addr=0x83000000 -cntr_addr=0x98000000 -emmc_dev=0 -sd_dev=2 -mmcdev=CONFIG_SYS_MMC_ENV_DEV -mmcpart=1 -image=Image -cntr_file=os_cntr_signed.bin -fdtfile=CONFIG_DEFAULT_FDT_FILE -console=ttyLP1,115200 earlycon -bootm_size=0x10000000 -boot_fit=no -mmcroot=/dev/mmcblk0p2 rootwait rw -mmcautodetect=yes -mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot} -netargs=setenv bootargs ${jh_clk} console=${console} - root=/dev/nfs - ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp -loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; -loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} -loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} -bootscript=echo Running bootscript from mmc ...; source -auth_os=booti ${cntr_addr} -boot_os=booti ${loadaddr} - ${fdt_addr_r} -mmcboot=echo Booting from mmc ...; - run mmcargs; - if test ${sec_boot} = yes; then - run auth_os; - else - if test ${boot_fit} = yes || test ${boot_fit} = try; then - bootm ${loadaddr}; - else - if run loadfdt loadimage; then - run boot_os; - else - echo WARN: Cannot load the fdt and image; - fi; - fi; - fi; -netboot=echo Booting from net ...; - run netargs; - if test ${ip_dyn} = yes; then - setenv get_cmd dhcp; - else - setenv get_cmd tftp; - fi; - if test ${sec_boot} = yes; then - ${get_cmd} ${cntr_addr} ${cntr_file}; - run auth_os; - else - ${get_cmd} ${loadaddr} ${image}; - if test ${boot_fit} = yes || test ${boot_fit} = try; then - bootm ${loadaddr}; - else - if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then - run boot_os; - else - echo WARN: Cannot load the DT; - fi; - fi; - fi; -bsp_bootcmd=echo Running BSP bootcmd ...; - mmc dev ${mmcdev}; if mmc rescan; then - if run loadbootscript; then - run bootscript; - else - if test ${sec_boot} = yes; then - if run loadcntr; then - run mmcboot; - else run netboot; - fi; - else - if run loadimage; then - run mmcboot; - else run netboot; - fi; - fi; - fi; - fi; diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c b/board/freescale/imx8ulp_evk/lpddr4_timing.c deleted file mode 100644 index 6d2805315b4..00000000000 --- a/board/freescale/imx8ulp_evk/lpddr4_timing.c +++ /dev/null @@ -1,1158 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2021 NXP - * - * Generated code from MX8ULP_DDR_tool - * - */ - -#include -#include - -/** CTL settings **/ -struct dram_cfg_param ddr_ctl_cfg[] = { - { 0x2e060000, 0xb00 }, /* 0 */ - { 0x2e060028, 0x258100 }, /* 10 */ - { 0x2e06002c, 0x17702 }, /* 11 */ - { 0x2e060030, 0x5 }, /* 12 */ - { 0x2e060034, 0x61 }, /* 13 */ - { 0x2e060038, 0x4b00 }, /* 14 */ - { 0x2e06003c, 0x2edfa }, /* 15 */ - { 0x2e060040, 0x5 }, /* 16 */ - { 0x2e060044, 0xc0 }, /* 17 */ - { 0x2e060048, 0x19c7d }, /* 18 */ - { 0x2e06004c, 0x101cdf }, /* 19 */ - { 0x2e060050, 0x5 }, /* 20 */ - { 0x2e060054, 0x420 }, /* 21 */ - { 0x2e060058, 0x1010000 }, /* 22 */ - { 0x2e06005c, 0x2011001 }, /* 23 */ - { 0x2e060060, 0x2010000 }, /* 24 */ - { 0x2e060064, 0x102 }, /* 25 */ - { 0x2e060068, 0xa }, /* 26 */ - { 0x2e06006c, 0x19 }, /* 27 */ - { 0x2e060078, 0x2020200 }, /* 30 */ - { 0x2e06007c, 0x1604 }, /* 31 */ - { 0x2e060090, 0x10 }, /* 36 */ - { 0x2e0600a4, 0x40c040c }, /* 41 */ - { 0x2e0600a8, 0x8040614 }, /* 42 */ - { 0x2e0600ac, 0x604 }, /* 43 */ - { 0x2e0600b0, 0x3090003 }, /* 44 */ - { 0x2e0600b4, 0x40002 }, /* 45 */ - { 0x2e0600b8, 0x50008 }, /* 46 */ - { 0x2e0600bc, 0x40309 }, /* 47 */ - { 0x2e0600c0, 0x2106 }, /* 48 */ - { 0x2e0600c4, 0xa090017 }, /* 49 */ - { 0x2e0600c8, 0x8200016 }, /* 50 */ - { 0x2e0600cc, 0xa0a }, /* 51 */ - { 0x2e0600d0, 0x4000694 }, /* 52 */ - { 0x2e0600d4, 0xa0a0804 }, /* 53 */ - { 0x2e0600d8, 0x4000d29 }, /* 54 */ - { 0x2e0600dc, 0xa0a0804 }, /* 55 */ - { 0x2e0600e0, 0x4004864 }, /* 56 */ - { 0x2e0600e4, 0x2030404 }, /* 57 */ - { 0x2e0600e8, 0x4040400 }, /* 58 */ - { 0x2e0600ec, 0x80b0a04 }, /* 59 */ - { 0x2e0600f0, 0x7010100 }, /* 60 */ - { 0x2e0600f4, 0x41507 }, /* 61 */ - { 0x2e0600fc, 0x1010000 }, /* 63 */ - { 0x2e060100, 0x1000000 }, /* 64 */ - { 0x2e060104, 0xe0403 }, /* 65 */ - { 0x2e060108, 0xb3 }, /* 66 */ - { 0x2e06010c, 0x1b }, /* 67 */ - { 0x2e060110, 0x16e }, /* 68 */ - { 0x2e060114, 0x94 }, /* 69 */ - { 0x2e060118, 0x803 }, /* 70 */ - { 0x2e06011c, 0x5 }, /* 71 */ - { 0x2e060120, 0x70000 }, /* 72 */ - { 0x2e060124, 0xe000f }, /* 73 */ - { 0x2e060128, 0x4a0026 }, /* 74 */ - { 0x2e06012c, 0x4000f9 }, /* 75 */ - { 0x2e060130, 0x120103 }, /* 76 */ - { 0x2e060134, 0x50005 }, /* 77 */ - { 0x2e060138, 0x7070005 }, /* 78 */ - { 0x2e06013c, 0x505010d }, /* 79 */ - { 0x2e060140, 0x101030a }, /* 80 */ - { 0x2e060144, 0x30a0505 }, /* 81 */ - { 0x2e060148, 0x5050101 }, /* 82 */ - { 0x2e06014c, 0x1030a }, /* 83 */ - { 0x2e060150, 0xe000e }, /* 84 */ - { 0x2e060154, 0x1c001c }, /* 85 */ - { 0x2e060158, 0x980098 }, /* 86 */ - { 0x2e06015c, 0x3050505 }, /* 87 */ - { 0x2e060160, 0x3010403 }, /* 88 */ - { 0x2e060164, 0x3050505 }, /* 89 */ - { 0x2e060168, 0x3010403 }, /* 90 */ - { 0x2e06016c, 0x8050505 }, /* 91 */ - { 0x2e060170, 0x3010403 }, /* 92 */ - { 0x2e060174, 0x3010000 }, /* 93 */ - { 0x2e060178, 0x10000 }, /* 94 */ - { 0x2e060180, 0x1000000 }, /* 96 */ - { 0x2e060184, 0x80104002 }, /* 97 */ - { 0x2e060188, 0x40003 }, /* 98 */ - { 0x2e06018c, 0x40005 }, /* 99 */ - { 0x2e060190, 0x30000 }, /* 100 */ - { 0x2e060194, 0x50004 }, /* 101 */ - { 0x2e060198, 0x4 }, /* 102 */ - { 0x2e06019c, 0x40003 }, /* 103 */ - { 0x2e0601a0, 0x40005 }, /* 104 */ - { 0x2e0601a8, 0x2cc0 }, /* 106 */ - { 0x2e0601ac, 0x2cc0 }, /* 107 */ - { 0x2e0601b0, 0x2cc0 }, /* 108 */ - { 0x2e0601b4, 0x2cc0 }, /* 109 */ - { 0x2e0601b8, 0x2cc0 }, /* 110 */ - { 0x2e0601c0, 0x4e5 }, /* 112 */ - { 0x2e0601c4, 0x5b80 }, /* 113 */ - { 0x2e0601c8, 0x5b80 }, /* 114 */ - { 0x2e0601cc, 0x5b80 }, /* 115 */ - { 0x2e0601d0, 0x5b80 }, /* 116 */ - { 0x2e0601d4, 0x5b80 }, /* 117 */ - { 0x2e0601dc, 0xa02 }, /* 119 */ - { 0x2e0601e0, 0x200c0 }, /* 120 */ - { 0x2e0601e4, 0x200c0 }, /* 121 */ - { 0x2e0601e8, 0x200c0 }, /* 122 */ - { 0x2e0601ec, 0x200c0 }, /* 123 */ - { 0x2e0601f0, 0x200c0 }, /* 124 */ - { 0x2e0601f8, 0x3815 }, /* 126 */ - { 0x2e06021c, 0x5000000 }, /* 135 */ - { 0x2e060220, 0x5030503 }, /* 136 */ - { 0x2e060224, 0x3 }, /* 137 */ - { 0x2e060228, 0x7010a09 }, /* 138 */ - { 0x2e06022c, 0xe0a09 }, /* 139 */ - { 0x2e060230, 0x10a0900 }, /* 140 */ - { 0x2e060234, 0xe0a0907 }, /* 141 */ - { 0x2e060238, 0xa090000 }, /* 142 */ - { 0x2e06023c, 0xa090701 }, /* 143 */ - { 0x2e060240, 0x101000e }, /* 144 */ - { 0x2e060244, 0x40003 }, /* 145 */ - { 0x2e060248, 0x7 }, /* 146 */ - { 0x2e060264, 0x4040100 }, /* 153 */ - { 0x2e060268, 0x1000000 }, /* 154 */ - { 0x2e06026c, 0x100000c0 }, /* 155 */ - { 0x2e060270, 0x100000c0 }, /* 156 */ - { 0x2e060274, 0x100000c0 }, /* 157 */ - { 0x2e06027c, 0x1600 }, /* 159 */ - { 0x2e060284, 0x1 }, /* 161 */ - { 0x2e060288, 0x2 }, /* 162 */ - { 0x2e06028c, 0x100e }, /* 163 */ - { 0x2e0602a4, 0xa0000 }, /* 169 */ - { 0x2e0602a8, 0xd0005 }, /* 170 */ - { 0x2e0602ac, 0x404 }, /* 171 */ - { 0x2e0602b0, 0xd }, /* 172 */ - { 0x2e0602b4, 0xa0014 }, /* 173 */ - { 0x2e0602b8, 0x4040018 }, /* 174 */ - { 0x2e0602bc, 0x18 }, /* 175 */ - { 0x2e0602c0, 0x35006a }, /* 176 */ - { 0x2e0602c4, 0x4040084 }, /* 177 */ - { 0x2e0602c8, 0x84 }, /* 178 */ - { 0x2e0602d8, 0x40004 }, /* 182 */ - { 0x2e0602dc, 0x30000914 }, /* 183 */ - { 0x2e0602e0, 0x3030 }, /* 184 */ - { 0x2e0602e4, 0x44440000 }, /* 185 */ - { 0x2e0602e8, 0x19191944 }, /* 186 */ - { 0x2e0602ec, 0x19191908 }, /* 187 */ - { 0x2e0602f0, 0x4000000 }, /* 188 */ - { 0x2e0602f4, 0x40404 }, /* 189 */ - { 0x2e0602f8, 0x9140004 }, /* 190 */ - { 0x2e0602fc, 0x30303000 }, /* 191 */ - { 0x2e060304, 0x19444444 }, /* 193 */ - { 0x2e060308, 0x19081919 }, /* 194 */ - { 0x2e06030c, 0x1919 }, /* 195 */ - { 0x2e060310, 0x4040400 }, /* 196 */ - { 0x2e060314, 0x1010120 }, /* 197 */ - { 0x2e060318, 0x1000100 }, /* 198 */ - { 0x2e06031c, 0x1 }, /* 199 */ - { 0x2e060324, 0x1000000 }, /* 201 */ - { 0x2e060328, 0x1 }, /* 202 */ - { 0x2e060354, 0x11000000 }, /* 213 */ - { 0x2e060358, 0x40c1815 }, /* 214 */ - { 0x2e060390, 0x30000 }, /* 228 */ - { 0x2e060394, 0x1000200 }, /* 229 */ - { 0x2e060398, 0x310040 }, /* 230 */ - { 0x2e06039c, 0x20008 }, /* 231 */ - { 0x2e0603a0, 0x400100 }, /* 232 */ - { 0x2e0603a4, 0x80060 }, /* 233 */ - { 0x2e0603a8, 0x1000200 }, /* 234 */ - { 0x2e0603ac, 0x2100040 }, /* 235 */ - { 0x2e0603b0, 0x10 }, /* 236 */ - { 0x2e0603b4, 0x50003 }, /* 237 */ - { 0x2e0603b8, 0x100001b }, /* 238 */ - { 0x2e0603d8, 0xffff0b00 }, /* 246 */ - { 0x2e0603dc, 0x1010001 }, /* 247 */ - { 0x2e0603e0, 0x1010101 }, /* 248 */ - { 0x2e0603e4, 0x10b0101 }, /* 249 */ - { 0x2e0603e8, 0x10000 }, /* 250 */ - { 0x2e0603ec, 0x4010101 }, /* 251 */ - { 0x2e0603f0, 0x1010000 }, /* 252 */ - { 0x2e0603f4, 0x4 }, /* 253 */ - { 0x2e0603fc, 0x3030101 }, /* 255 */ - { 0x2e060400, 0x103 }, /* 256 */ - { 0x2e0604a4, 0x2020101 }, /* 297 */ - { 0x2e0604a8, 0x10100 }, /* 298 */ - { 0x2e0604ac, 0x1000101 }, /* 299 */ - { 0x2e0604b0, 0x1010101 }, /* 300 */ - { 0x2e0604b4, 0x4030300 }, /* 301 */ - { 0x2e0604b8, 0x8080505 }, /* 302 */ - { 0x2e0604bc, 0x8020808 }, /* 303 */ - { 0x2e0604c0, 0x8020e00 }, /* 304 */ - { 0x2e0604c4, 0xa020e00 }, /* 305 */ - { 0x2e0604c8, 0x8000f00 }, /* 306 */ - { 0x2e0604cc, 0xa08 }, /* 307 */ - { 0x2e0604d0, 0x1010101 }, /* 308 */ - { 0x2e0604d4, 0x01000102 }, /* 309 */ - { 0x2e0604d8, 0x00000101 }, /* 310 */ - { 0x2e0604dc, 0x40400 }, /* 311 */ - { 0x2e0604e0, 0x4040000 }, /* 312 */ - { 0x2e0604e4, 0x4000000 }, /* 313 */ - { 0x2e0604e8, 0x10004 }, /* 314 */ - { 0x2e0604f0, 0xfffff }, /* 316 */ - { 0x2e0604f8, 0xfffff }, /* 318 */ - { 0x2e060500, 0xfffff }, /* 320 */ - { 0x2e060508, 0xfffff }, /* 322 */ - { 0x2e060510, 0xfffff }, /* 324 */ - { 0x2e060518, 0xfffff }, /* 326 */ - { 0x2e060520, 0xfffff }, /* 328 */ - { 0x2e060528, 0xfffff }, /* 330 */ - { 0x2e060530, 0xfffff }, /* 332 */ - { 0x2e060538, 0xfffff }, /* 334 */ - { 0x2e060540, 0xfffff }, /* 336 */ - { 0x2e060548, 0xfffff }, /* 338 */ - { 0x2e060550, 0xfffff }, /* 340 */ - { 0x2e060558, 0xfffff }, /* 342 */ - { 0x2e060560, 0xfffff }, /* 344 */ - { 0x2e060568, 0xfffff }, /* 346 */ - { 0x2e060570, 0xfffff }, /* 348 */ - { 0x2e060578, 0xfffff }, /* 350 */ - { 0x2e060580, 0xfffff }, /* 352 */ - { 0x2e060588, 0xfffff }, /* 354 */ - { 0x2e060590, 0xfffff }, /* 356 */ - { 0x2e060598, 0xfffff }, /* 358 */ - { 0x2e0605a0, 0xfffff }, /* 360 */ - { 0x2e0605a8, 0xfffff }, /* 362 */ - { 0x2e0605b0, 0xfffff }, /* 364 */ - { 0x2e0605b8, 0xfffff }, /* 366 */ - { 0x2e0605c0, 0xfffff }, /* 368 */ - { 0x2e0605c8, 0xfffff }, /* 370 */ - { 0x2e0605d0, 0xfffff }, /* 372 */ - { 0x2e0605d8, 0xfffff }, /* 374 */ - { 0x2e0605e0, 0xfffff }, /* 376 */ - { 0x2e0605e8, 0xfffff }, /* 378 */ - { 0x2e0605f0, 0xfffff }, /* 380 */ - { 0x2e0605f8, 0xfffff }, /* 382 */ - { 0x2e060600, 0xfffff }, /* 384 */ - { 0x2e060608, 0xfffff }, /* 386 */ - { 0x2e060610, 0xfffff }, /* 388 */ - { 0x2e060618, 0xfffff }, /* 390 */ - { 0x2e060620, 0xfffff }, /* 392 */ - { 0x2e060628, 0xfffff }, /* 394 */ - { 0x2e060630, 0xfffff }, /* 396 */ - { 0x2e060638, 0xfffff }, /* 398 */ - { 0x2e060640, 0xfffff }, /* 400 */ - { 0x2e060648, 0xfffff }, /* 402 */ - { 0x2e060650, 0xfffff }, /* 404 */ - { 0x2e060658, 0xfffff }, /* 406 */ - { 0x2e060660, 0xfffff }, /* 408 */ - { 0x2e060668, 0xfffff }, /* 410 */ - { 0x2e060670, 0xfffff }, /* 412 */ - { 0x2e060678, 0xfffff }, /* 414 */ - { 0x2e060680, 0xfffff }, /* 416 */ - { 0x2e060688, 0xfffff }, /* 418 */ - { 0x2e060690, 0xfffff }, /* 420 */ - { 0x2e060698, 0xfffff }, /* 422 */ - { 0x2e0606a0, 0xfffff }, /* 424 */ - { 0x2e0606a8, 0xfffff }, /* 426 */ - { 0x2e0606b0, 0xfffff }, /* 428 */ - { 0x2e0606b8, 0xfffff }, /* 430 */ - { 0x2e0606c0, 0xfffff }, /* 432 */ - { 0x2e0606c8, 0xfffff }, /* 434 */ - { 0x2e0606d0, 0xfffff }, /* 436 */ - { 0x2e0606d8, 0xfffff }, /* 438 */ - { 0x2e0606e0, 0xfffff }, /* 440 */ - { 0x2e0606e8, 0x30fffff }, /* 442 */ - { 0x2e0606ec, 0xffffffff }, /* 443 */ - { 0x2e0606f0, 0x30f0f }, /* 444 */ - { 0x2e0606f4, 0xffffffff }, /* 445 */ - { 0x2e0606f8, 0x30f0f }, /* 446 */ - { 0x2e0606fc, 0xffffffff }, /* 447 */ - { 0x2e060700, 0x30f0f }, /* 448 */ - { 0x2e060704, 0xffffffff }, /* 449 */ - { 0x2e060708, 0x30f0f }, /* 450 */ - { 0x2e06070c, 0xffffffff }, /* 451 */ - { 0x2e060710, 0x30f0f }, /* 452 */ - { 0x2e060714, 0xffffffff }, /* 453 */ - { 0x2e060718, 0x30f0f }, /* 454 */ - { 0x2e06071c, 0xffffffff }, /* 455 */ - { 0x2e060720, 0x30f0f }, /* 456 */ - { 0x2e060724, 0xffffffff }, /* 457 */ - { 0x2e060728, 0x30f0f }, /* 458 */ - { 0x2e06072c, 0xffffffff }, /* 459 */ - { 0x2e060730, 0x30f0f }, /* 460 */ - { 0x2e060734, 0xffffffff }, /* 461 */ - { 0x2e060738, 0x30f0f }, /* 462 */ - { 0x2e06073c, 0xffffffff }, /* 463 */ - { 0x2e060740, 0x30f0f }, /* 464 */ - { 0x2e060744, 0xffffffff }, /* 465 */ - { 0x2e060748, 0x30f0f }, /* 466 */ - { 0x2e06074c, 0xffffffff }, /* 467 */ - { 0x2e060750, 0x30f0f }, /* 468 */ - { 0x2e060754, 0xffffffff }, /* 469 */ - { 0x2e060758, 0x30f0f }, /* 470 */ - { 0x2e06075c, 0xffffffff }, /* 471 */ - { 0x2e060760, 0x30f0f }, /* 472 */ - { 0x2e060764, 0xffffffff }, /* 473 */ - { 0x2e060768, 0x30f0f }, /* 474 */ - { 0x2e06076c, 0xffffffff }, /* 475 */ - { 0x2e060770, 0x30f0f }, /* 476 */ - { 0x2e060774, 0xffffffff }, /* 477 */ - { 0x2e060778, 0x30f0f }, /* 478 */ - { 0x2e06077c, 0xffffffff }, /* 479 */ - { 0x2e060780, 0x30f0f }, /* 480 */ - { 0x2e060784, 0xffffffff }, /* 481 */ - { 0x2e060788, 0x30f0f }, /* 482 */ - { 0x2e06078c, 0xffffffff }, /* 483 */ - { 0x2e060790, 0x30f0f }, /* 484 */ - { 0x2e060794, 0xffffffff }, /* 485 */ - { 0x2e060798, 0x30f0f }, /* 486 */ - { 0x2e06079c, 0xffffffff }, /* 487 */ - { 0x2e0607a0, 0x30f0f }, /* 488 */ - { 0x2e0607a4, 0xffffffff }, /* 489 */ - { 0x2e0607a8, 0x30f0f }, /* 490 */ - { 0x2e0607ac, 0xffffffff }, /* 491 */ - { 0x2e0607b0, 0x30f0f }, /* 492 */ - { 0x2e0607b4, 0xffffffff }, /* 493 */ - { 0x2e0607b8, 0x30f0f }, /* 494 */ - { 0x2e0607bc, 0xffffffff }, /* 495 */ - { 0x2e0607c0, 0x30f0f }, /* 496 */ - { 0x2e0607c4, 0xffffffff }, /* 497 */ - { 0x2e0607c8, 0x30f0f }, /* 498 */ - { 0x2e0607cc, 0xffffffff }, /* 499 */ - { 0x2e0607d0, 0x30f0f }, /* 500 */ - { 0x2e0607d4, 0xffffffff }, /* 501 */ - { 0x2e0607d8, 0x30f0f }, /* 502 */ - { 0x2e0607dc, 0xffffffff }, /* 503 */ - { 0x2e0607e0, 0x30f0f }, /* 504 */ - { 0x2e0607e4, 0xffffffff }, /* 505 */ - { 0x2e0607e8, 0x30f0f }, /* 506 */ - { 0x2e0607ec, 0xffffffff }, /* 507 */ - { 0x2e0607f0, 0x30f0f }, /* 508 */ - { 0x2e0607f4, 0xffffffff }, /* 509 */ - { 0x2e0607f8, 0x30f0f }, /* 510 */ - { 0x2e0607fc, 0xffffffff }, /* 511 */ - { 0x2e060800, 0x30f0f }, /* 512 */ - { 0x2e060804, 0xffffffff }, /* 513 */ - { 0x2e060808, 0x30f0f }, /* 514 */ - { 0x2e06080c, 0xffffffff }, /* 515 */ - { 0x2e060810, 0x30f0f }, /* 516 */ - { 0x2e060814, 0xffffffff }, /* 517 */ - { 0x2e060818, 0x30f0f }, /* 518 */ - { 0x2e06081c, 0xffffffff }, /* 519 */ - { 0x2e060820, 0x30f0f }, /* 520 */ - { 0x2e060824, 0xffffffff }, /* 521 */ - { 0x2e060828, 0x30f0f }, /* 522 */ - { 0x2e06082c, 0xffffffff }, /* 523 */ - { 0x2e060830, 0x30f0f }, /* 524 */ - { 0x2e060834, 0xffffffff }, /* 525 */ - { 0x2e060838, 0x30f0f }, /* 526 */ - { 0x2e06083c, 0xffffffff }, /* 527 */ - { 0x2e060840, 0x30f0f }, /* 528 */ - { 0x2e060844, 0xffffffff }, /* 529 */ - { 0x2e060848, 0x30f0f }, /* 530 */ - { 0x2e06084c, 0xffffffff }, /* 531 */ - { 0x2e060850, 0x30f0f }, /* 532 */ - { 0x2e060854, 0xffffffff }, /* 533 */ - { 0x2e060858, 0x30f0f }, /* 534 */ - { 0x2e06085c, 0xffffffff }, /* 535 */ - { 0x2e060860, 0x30f0f }, /* 536 */ - { 0x2e060864, 0xffffffff }, /* 537 */ - { 0x2e060868, 0x30f0f }, /* 538 */ - { 0x2e06086c, 0xffffffff }, /* 539 */ - { 0x2e060870, 0x30f0f }, /* 540 */ - { 0x2e060874, 0xffffffff }, /* 541 */ - { 0x2e060878, 0x30f0f }, /* 542 */ - { 0x2e06087c, 0xffffffff }, /* 543 */ - { 0x2e060880, 0x30f0f }, /* 544 */ - { 0x2e060884, 0xffffffff }, /* 545 */ - { 0x2e060888, 0x30f0f }, /* 546 */ - { 0x2e06088c, 0xffffffff }, /* 547 */ - { 0x2e060890, 0x30f0f }, /* 548 */ - { 0x2e060894, 0xffffffff }, /* 549 */ - { 0x2e060898, 0x30f0f }, /* 550 */ - { 0x2e06089c, 0xffffffff }, /* 551 */ - { 0x2e0608a0, 0x30f0f }, /* 552 */ - { 0x2e0608a4, 0xffffffff }, /* 553 */ - { 0x2e0608a8, 0x30f0f }, /* 554 */ - { 0x2e0608ac, 0xffffffff }, /* 555 */ - { 0x2e0608b0, 0x30f0f }, /* 556 */ - { 0x2e0608b4, 0xffffffff }, /* 557 */ - { 0x2e0608b8, 0x30f0f }, /* 558 */ - { 0x2e0608bc, 0xffffffff }, /* 559 */ - { 0x2e0608c0, 0x30f0f }, /* 560 */ - { 0x2e0608c4, 0xffffffff }, /* 561 */ - { 0x2e0608c8, 0x30f0f }, /* 562 */ - { 0x2e0608cc, 0xffffffff }, /* 563 */ - { 0x2e0608d0, 0x30f0f }, /* 564 */ - { 0x2e0608d4, 0xffffffff }, /* 565 */ - { 0x2e0608d8, 0x30f0f }, /* 566 */ - { 0x2e0608dc, 0xffffffff }, /* 567 */ - { 0x2e0608e0, 0x30f0f }, /* 568 */ - { 0x2e0608e4, 0xffffffff }, /* 569 */ - { 0x2e0608e8, 0x32070f0f }, /* 570 */ - { 0x2e0608ec, 0x1320000 }, /* 571 */ - { 0x2e0608f0, 0x13200 }, /* 572 */ - { 0x2e0608f4, 0x132 }, /* 573 */ - { 0x2e0608fc, 0x1b1b0000 }, /* 575 */ - { 0x2e060900, 0x21 }, /* 576 */ - { 0x2e060904, 0xa }, /* 577 */ - { 0x2e060908, 0x166 }, /* 578 */ - { 0x2e06090c, 0x200 }, /* 579 */ - { 0x2e060910, 0x200 }, /* 580 */ - { 0x2e060914, 0x200 }, /* 581 */ - { 0x2e060918, 0x200 }, /* 582 */ - { 0x2e06091c, 0x432 }, /* 583 */ - { 0x2e060920, 0xdfc }, /* 584 */ - { 0x2e060924, 0x204 }, /* 585 */ - { 0x2e060928, 0x2dc }, /* 586 */ - { 0x2e06092c, 0x200 }, /* 587 */ - { 0x2e060930, 0x200 }, /* 588 */ - { 0x2e060934, 0x200 }, /* 589 */ - { 0x2e060938, 0x200 }, /* 590 */ - { 0x2e06093c, 0x894 }, /* 591 */ - { 0x2e060940, 0x1c98 }, /* 592 */ - { 0x2e060944, 0x204 }, /* 593 */ - { 0x2e060948, 0x1006 }, /* 594 */ - { 0x2e06094c, 0x200 }, /* 595 */ - { 0x2e060950, 0x200 }, /* 596 */ - { 0x2e060954, 0x200 }, /* 597 */ - { 0x2e060958, 0x200 }, /* 598 */ - { 0x2e06095c, 0x3012 }, /* 599 */ - { 0x2e060960, 0xa03c }, /* 600 */ - { 0x2e060964, 0x2020406 }, /* 601 */ - { 0x2e060968, 0x2030202 }, /* 602 */ - { 0x2e06096c, 0x1000202 }, /* 603 */ - { 0x2e060970, 0x3040100 }, /* 604 */ - { 0x2e060974, 0x10105 }, /* 605 */ - { 0x2e060978, 0x10101 }, /* 606 */ - { 0x2e06097c, 0x10101 }, /* 607 */ - { 0x2e060980, 0x10001 }, /* 608 */ - { 0x2e060984, 0x101 }, /* 609 */ - { 0x2e060988, 0x2000201 }, /* 610 */ - { 0x2e06098c, 0x2010000 }, /* 611 */ - { 0x2e060990, 0x6000200 }, /* 612 */ - { 0x2e060994, 0x3000a06 }, /* 613 */ - { 0x2e060998, 0x2000c03 }, /* 614 */ -}; - -/** PI settings **/ -struct dram_cfg_param ddr_pi_cfg[] = { - { 0x2e062000, 0xb00 }, /* 0 */ - { 0x2e062004, 0xbeedb66f }, /* 1 */ - { 0x2e062008, 0xabef6bd }, /* 2 */ - { 0x2e06200c, 0x1001387 }, /* 3 */ - { 0x2e062010, 0x1 }, /* 4 */ - { 0x2e062014, 0x10064 }, /* 5 */ - { 0x2e06202c, 0x201 }, /* 11 */ - { 0x2e062030, 0x7 }, /* 12 */ - { 0x2e062034, 0x50001 }, /* 13 */ - { 0x2e062038, 0x3030800 }, /* 14 */ - { 0x2e06203c, 0x1 }, /* 15 */ - { 0x2e062040, 0x5 }, /* 16 */ - { 0x2e062064, 0x1000000 }, /* 25 */ - { 0x2e062068, 0xa000001 }, /* 26 */ - { 0x2e06206c, 0x28 }, /* 27 */ - { 0x2e062070, 0x1 }, /* 28 */ - { 0x2e062074, 0x320005 }, /* 29 */ - { 0x2e062080, 0x10102 }, /* 32 */ - { 0x2e062084, 0x1 }, /* 33 */ - { 0x2e062088, 0xaa }, /* 34 */ - { 0x2e06208c, 0x55 }, /* 35 */ - { 0x2e062090, 0xb5 }, /* 36 */ - { 0x2e062094, 0x4a }, /* 37 */ - { 0x2e062098, 0x56 }, /* 38 */ - { 0x2e06209c, 0xa9 }, /* 39 */ - { 0x2e0620a0, 0xa9 }, /* 40 */ - { 0x2e0620a4, 0xb5 }, /* 41 */ - { 0x2e0620a8, 0x10000 }, /* 42 */ - { 0x2e0620ac, 0x100 }, /* 43 */ - { 0x2e0620b0, 0x5050000 }, /* 44 */ - { 0x2e0620b4, 0x13 }, /* 45 */ - { 0x2e0620b8, 0x7d0 }, /* 46 */ - { 0x2e0620bc, 0x300 }, /* 47 */ - { 0x2e0620c8, 0x1000000 }, /* 50 */ - { 0x2e0620cc, 0x10101 }, /* 51 */ - { 0x2e0620d8, 0x10003 }, /* 54 */ - { 0x2e0620dc, 0x170500 }, /* 55 */ - { 0x2e0620ec, 0xa140a01 }, /* 59 */ - { 0x2e0620f0, 0x204010a }, /* 60 */ - { 0x2e0620f4, 0x21010 }, /* 61 */ - { 0x2e0620f8, 0x40401 }, /* 62 */ - { 0x2e0620fc, 0x10e0005 }, /* 63 */ - { 0x2e062100, 0x5000001 }, /* 64 */ - { 0x2e062104, 0x204 }, /* 65 */ - { 0x2e062108, 0x34 }, /* 66 */ - { 0x2e062114, 0x1000000 }, /* 69 */ - { 0x2e062118, 0x1000000 }, /* 70 */ - { 0x2e06211c, 0x80200 }, /* 71 */ - { 0x2e062120, 0x2000200 }, /* 72 */ - { 0x2e062124, 0x1000100 }, /* 73 */ - { 0x2e062128, 0x1000000 }, /* 74 */ - { 0x2e06212c, 0x2000200 }, /* 75 */ - { 0x2e062130, 0x200 }, /* 76 */ - { 0x2e062164, 0x400 }, /* 89 */ - { 0x2e062168, 0x2010000 }, /* 90 */ - { 0x2e06216c, 0x80103 }, /* 91 */ - { 0x2e062174, 0x10008 }, /* 93 */ - { 0x2e06217c, 0xaa00 }, /* 95 */ - { 0x2e062188, 0x10000 }, /* 98 */ - { 0x2e0621ec, 0x8 }, /* 123 */ - { 0x2e062218, 0xf0000 }, /* 134 */ - { 0x2e06221c, 0xa }, /* 135 */ - { 0x2e062220, 0x19 }, /* 136 */ - { 0x2e062224, 0x100 }, /* 137 */ - { 0x2e062228, 0x100 }, /* 138 */ - { 0x2e062238, 0x1000000 }, /* 142 */ - { 0x2e06223c, 0x10003 }, /* 143 */ - { 0x2e062240, 0x2000101 }, /* 144 */ - { 0x2e062244, 0x1030001 }, /* 145 */ - { 0x2e062248, 0x10400 }, /* 146 */ - { 0x2e06224c, 0x6000105 }, /* 147 */ - { 0x2e062250, 0x1070001 }, /* 148 */ - { 0x2e062260, 0x10001 }, /* 152 */ - { 0x2e062274, 0x401 }, /* 157 */ - { 0x2e06227c, 0x10000 }, /* 159 */ - { 0x2e062284, 0x2010000 }, /* 161 */ - { 0x2e062288, 0xb }, /* 162 */ - { 0x2e06228c, 0x34 }, /* 163 */ - { 0x2e062290, 0x34 }, /* 164 */ - { 0x2e062294, 0x2003c }, /* 165 */ - { 0x2e062298, 0x2000200 }, /* 166 */ - { 0x2e06229c, 0xc040c04 }, /* 167 */ - { 0x2e0622a0, 0xe1406 }, /* 168 */ - { 0x2e0622a4, 0xb3 }, /* 169 */ - { 0x2e0622a8, 0x1b }, /* 170 */ - { 0x2e0622ac, 0x16e }, /* 171 */ - { 0x2e0622b0, 0x94 }, /* 172 */ - { 0x2e0622b4, 0x4000803 }, /* 173 */ - { 0x2e0622b8, 0x1010404 }, /* 174 */ - { 0x2e0622bc, 0x1501 }, /* 175 */ - { 0x2e0622c0, 0x1a0016 }, /* 176 */ - { 0x2e0622c4, 0x1000100 }, /* 177 */ - { 0x2e0622c8, 0x100 }, /* 178 */ - { 0x2e0622d0, 0x5040303 }, /* 180 */ - { 0x2e0622d4, 0x1010805 }, /* 181 */ - { 0x2e0622d8, 0x1010101 }, /* 182 */ - { 0x2e0622e8, 0x2060404 }, /* 186 */ - { 0x2e0622ec, 0x2020402 }, /* 187 */ - { 0x2e0622f0, 0x3102 }, /* 188 */ - { 0x2e0622f4, 0x320009 }, /* 189 */ - { 0x2e0622f8, 0x36000a }, /* 190 */ - { 0x2e0622fc, 0x101000e }, /* 191 */ - { 0x2e062300, 0xd0101 }, /* 192 */ - { 0x2e062304, 0x1001801 }, /* 193 */ - { 0x2e062308, 0x1000084 }, /* 194 */ - { 0x2e06230c, 0xe000e }, /* 195 */ - { 0x2e062310, 0x190100 }, /* 196 */ - { 0x2e062314, 0x1000019 }, /* 197 */ - { 0x2e062318, 0x850085 }, /* 198 */ - { 0x2e06231c, 0x220f220f }, /* 199 */ - { 0x2e062320, 0x101220f }, /* 200 */ - { 0x2e062324, 0xa070601 }, /* 201 */ - { 0x2e062328, 0xa07060d }, /* 202 */ - { 0x2e06232c, 0xa07070d }, /* 203 */ - { 0x2e062330, 0xc00d }, /* 204 */ - { 0x2e062334, 0xc01000 }, /* 205 */ - { 0x2e062338, 0xc01000 }, /* 206 */ - { 0x2e06233c, 0x21000 }, /* 207 */ - { 0x2e062340, 0x2000d }, /* 208 */ - { 0x2e062344, 0x140018 }, /* 209 */ - { 0x2e062348, 0x190084 }, /* 210 */ - { 0x2e06234c, 0x220f0056 }, /* 211 */ - { 0x2e062350, 0x101 }, /* 212 */ - { 0x2e062354, 0x560019 }, /* 213 */ - { 0x2e062358, 0x101220f }, /* 214 */ - { 0x2e06235c, 0x1b00 }, /* 215 */ - { 0x2e062360, 0x220f0056 }, /* 216 */ - { 0x2e062364, 0x8000101 }, /* 217 */ - { 0x2e062368, 0x4090403 }, /* 218 */ - { 0x2e06236c, 0x5eb }, /* 219 */ - { 0x2e062370, 0x20010003 }, /* 220 */ - { 0x2e062374, 0x80a0a03 }, /* 221 */ - { 0x2e062378, 0x4090403 }, /* 222 */ - { 0x2e06237c, 0xbd8 }, /* 223 */ - { 0x2e062380, 0x20010005 }, /* 224 */ - { 0x2e062384, 0x80a0a03 }, /* 225 */ - { 0x2e062388, 0xb090a0c }, /* 226 */ - { 0x2e06238c, 0x4126 }, /* 227 */ - { 0x2e062390, 0x20020017 }, /* 228 */ - { 0x2e062394, 0xa0a08 }, /* 229 */ - { 0x2e062398, 0x166 }, /* 230 */ - { 0x2e06239c, 0xdfc }, /* 231 */ - { 0x2e0623a0, 0x2dc }, /* 232 */ - { 0x2e0623a4, 0x1c98 }, /* 233 */ - { 0x2e0623a8, 0x1006 }, /* 234 */ - { 0x2e0623ac, 0xa03c }, /* 235 */ - { 0x2e0623b0, 0x1c000e }, /* 236 */ - { 0x2e0623b4, 0x3030098 }, /* 237 */ - { 0x2e0623b8, 0x258103 }, /* 238 */ - { 0x2e0623bc, 0x17702 }, /* 239 */ - { 0x2e0623c0, 0x5 }, /* 240 */ - { 0x2e0623c4, 0x61 }, /* 241 */ - { 0x2e0623c8, 0xe }, /* 242 */ - { 0x2e0623cc, 0x4b00 }, /* 243 */ - { 0x2e0623d0, 0x17702 }, /* 244 */ - { 0x2e0623d4, 0x5 }, /* 245 */ - { 0x2e0623d8, 0xc0 }, /* 246 */ - { 0x2e0623dc, 0x1c }, /* 247 */ - { 0x2e0623e0, 0x19c7d }, /* 248 */ - { 0x2e0623e4, 0x17702 }, /* 249 */ - { 0x2e0623e8, 0x5 }, /* 250 */ - { 0x2e0623ec, 0x420 }, /* 251 */ - { 0x2e0623f0, 0x1000098 }, /* 252 */ - { 0x2e0623f4, 0x310040 }, /* 253 */ - { 0x2e0623f8, 0x10008 }, /* 254 */ - { 0x2e0623fc, 0x600040 }, /* 255 */ - { 0x2e062400, 0x10008 }, /* 256 */ - { 0x2e062404, 0x2100040 }, /* 257 */ - { 0x2e062408, 0x310 }, /* 258 */ - { 0x2e06240c, 0x1b000e }, /* 259 */ - { 0x2e062410, 0x1010101 }, /* 260 */ - { 0x2e062414, 0x2020101 }, /* 261 */ - { 0x2e062418, 0x8080404 }, /* 262 */ - { 0x2e06241c, 0x5508 }, /* 263 */ - { 0x2e062420, 0x83c5a00 }, /* 264 */ - { 0x2e062424, 0x55 }, /* 265 */ - { 0x2e062428, 0x55083c5a }, /* 266 */ - { 0x2e06242c, 0x5a000000 }, /* 267 */ - { 0x2e062430, 0x55083c }, /* 268 */ - { 0x2e062434, 0x3c5a0000 }, /* 269 */ - { 0x2e062438, 0xf0e0d0c }, /* 270 */ - { 0x2e06243c, 0xb0a0908 }, /* 271 */ - { 0x2e062440, 0x7060504 }, /* 272 */ - { 0x2e062444, 0x3020100 }, /* 273 */ - { 0x2e06244c, 0x2020101 }, /* 275 */ - { 0x2e062450, 0x8080404 }, /* 276 */ - { 0x2e062454, 0x44300004 }, /* 277 */ - { 0x2e062458, 0x4041919 }, /* 278 */ - { 0x2e06245c, 0x19443000 }, /* 279 */ - { 0x2e062460, 0x9140419 }, /* 280 */ - { 0x2e062464, 0x19194430 }, /* 281 */ - { 0x2e062468, 0x30000404 }, /* 282 */ - { 0x2e06246c, 0x4191944 }, /* 283 */ - { 0x2e062470, 0x44300004 }, /* 284 */ - { 0x2e062474, 0x14041919 }, /* 285 */ - { 0x2e062478, 0x19443009 }, /* 286 */ - { 0x2e06247c, 0x40419 }, /* 287 */ - { 0x2e062480, 0x19194430 }, /* 288 */ - { 0x2e062484, 0x30000404 }, /* 289 */ - { 0x2e062488, 0x4191944 }, /* 290 */ - { 0x2e06248c, 0x44300914 }, /* 291 */ - { 0x2e062490, 0x44041919 }, /* 292 */ - { 0x2e062494, 0x19443000 }, /* 293 */ - { 0x2e062498, 0x40419 }, /* 294 */ - { 0x2e06249c, 0x19194430 }, /* 295 */ - { 0x2e0624a0, 0x30091404 }, /* 296 */ - { 0x2e0624a4, 0x4191944 }, /* 297 */ -}; - -/** PHY_F1 settings **/ -struct dram_cfg_param ddr_phy_f1_cfg[] = { - { 0x2e064000, 0x4f0 }, /* 0 */ - { 0x2e064008, 0x1030200 }, /* 2 */ - { 0x2e064014, 0x3000000 }, /* 5 */ - { 0x2e064018, 0x1000001 }, /* 6 */ - { 0x2e06401c, 0x3000400 }, /* 7 */ - { 0x2e064020, 0x1 }, /* 8 */ - { 0x2e064024, 0x1 }, /* 9 */ - { 0x2e064030, 0x10000 }, /* 12 */ - { 0x2e064038, 0xc00004 }, /* 14 */ - { 0x2e06403c, 0xcc0008 }, /* 15 */ - { 0x2e064040, 0x660601 }, /* 16 */ - { 0x2e064044, 0x3 }, /* 17 */ - { 0x2e06404c, 0x1 }, /* 19 */ - { 0x2e064050, 0xaaaa }, /* 20 */ - { 0x2e064054, 0x5555 }, /* 21 */ - { 0x2e064058, 0xb5b5 }, /* 22 */ - { 0x2e06405c, 0x4a4a }, /* 23 */ - { 0x2e064060, 0x5656 }, /* 24 */ - { 0x2e064064, 0xa9a9 }, /* 25 */ - { 0x2e064068, 0xb7b7 }, /* 26 */ - { 0x2e06406c, 0x4848 }, /* 27 */ - { 0x2e064078, 0x8000000 }, /* 30 */ - { 0x2e06407c, 0x4010008 }, /* 31 */ - { 0x2e064080, 0x408 }, /* 32 */ - { 0x2e064084, 0x3102000 }, /* 33 */ - { 0x2e064088, 0xc0020 }, /* 34 */ - { 0x2e06408c, 0x10000 }, /* 35 */ - { 0x2e064090, 0x55555555 }, /* 36 */ - { 0x2e064094, 0xaaaaaaaa }, /* 37 */ - { 0x2e064098, 0x55555555 }, /* 38 */ - { 0x2e06409c, 0xaaaaaaaa }, /* 39 */ - { 0x2e0640a0, 0x5555 }, /* 40 */ - { 0x2e0640a4, 0x1000100 }, /* 41 */ - { 0x2e0640a8, 0x800180 }, /* 42 */ - { 0x2e0640ac, 0x1 }, /* 43 */ - { 0x2e064100, 0x4 }, /* 64 */ - { 0x2e06411c, 0x41f07ff }, /* 71 */ - { 0x2e064120, 0x1 }, /* 72 */ - { 0x2e064124, 0x1cc0800 }, /* 73 */ - { 0x2e064128, 0x3003cc08 }, /* 74 */ - { 0x2e06412c, 0x2000014e }, /* 75 */ - { 0x2e064130, 0x7ff0200 }, /* 76 */ - { 0x2e064134, 0x301 }, /* 77 */ - { 0x2e064140, 0x30000 }, /* 80 */ - { 0x2e064154, 0x2000000 }, /* 85 */ - { 0x2e064158, 0x51515042 }, /* 86 */ - { 0x2e06415c, 0x31c06000 }, /* 87 */ - { 0x2e064160, 0x6bf000a }, /* 88 */ - { 0x2e064164, 0xc0c000 }, /* 89 */ - { 0x2e064168, 0x1000000 }, /* 90 */ - { 0x2e06416c, 0x10001000 }, /* 91 */ - { 0x2e064170, 0xc043242 }, /* 92 */ - { 0x2e064174, 0xf0c0e01 }, /* 93 */ - { 0x2e064178, 0x1000140 }, /* 94 */ - { 0x2e06417c, 0xc000120 }, /* 95 */ - { 0x2e064180, 0x118 }, /* 96 */ - { 0x2e064184, 0x1000203 }, /* 97 */ - { 0x2e064188, 0x56417032 }, /* 98 */ - { 0x2e06418c, 0x8 }, /* 99 */ - { 0x2e064190, 0x2980298 }, /* 100 */ - { 0x2e064194, 0x2980298 }, /* 101 */ - { 0x2e064198, 0x2980298 }, /* 102 */ - { 0x2e06419c, 0x2980298 }, /* 103 */ - { 0x2e0641a0, 0x298 }, /* 104 */ - { 0x2e0641a4, 0x8000 }, /* 105 */ - { 0x2e0641a8, 0x800080 }, /* 106 */ - { 0x2e0641ac, 0x800080 }, /* 107 */ - { 0x2e0641b0, 0x800080 }, /* 108 */ - { 0x2e0641b4, 0x800080 }, /* 109 */ - { 0x2e0641b8, 0x800080 }, /* 110 */ - { 0x2e0641bc, 0x800080 }, /* 111 */ - { 0x2e0641c0, 0x800080 }, /* 112 */ - { 0x2e0641c4, 0x800080 }, /* 113 */ - { 0x2e0641c8, 0x1940080 }, /* 114 */ - { 0x2e0641cc, 0x1a00001 }, /* 115 */ - { 0x2e0641d4, 0x10000 }, /* 117 */ - { 0x2e0641d8, 0x80200 }, /* 118 */ - { 0x2e064400, 0x4f0 }, /* 256 */ - { 0x2e064408, 0x1030200 }, /* 258 */ - { 0x2e064414, 0x3000000 }, /* 261 */ - { 0x2e064418, 0x1000001 }, /* 262 */ - { 0x2e06441c, 0x3000400 }, /* 263 */ - { 0x2e064420, 0x1 }, /* 264 */ - { 0x2e064424, 0x1 }, /* 265 */ - { 0x2e064430, 0x10000 }, /* 268 */ - { 0x2e064438, 0xc00004 }, /* 270 */ - { 0x2e06443c, 0xcc0008 }, /* 271 */ - { 0x2e064440, 0x660601 }, /* 272 */ - { 0x2e064444, 0x3 }, /* 273 */ - { 0x2e06444c, 0x1 }, /* 275 */ - { 0x2e064450, 0xaaaa }, /* 276 */ - { 0x2e064454, 0x5555 }, /* 277 */ - { 0x2e064458, 0xb5b5 }, /* 278 */ - { 0x2e06445c, 0x4a4a }, /* 279 */ - { 0x2e064460, 0x5656 }, /* 280 */ - { 0x2e064464, 0xa9a9 }, /* 281 */ - { 0x2e064468, 0xb7b7 }, /* 282 */ - { 0x2e06446c, 0x4848 }, /* 283 */ - { 0x2e064478, 0x8000000 }, /* 286 */ - { 0x2e06447c, 0x4010008 }, /* 287 */ - { 0x2e064480, 0x408 }, /* 288 */ - { 0x2e064484, 0x3102000 }, /* 289 */ - { 0x2e064488, 0xc0020 }, /* 290 */ - { 0x2e06448c, 0x10000 }, /* 291 */ - { 0x2e064490, 0x55555555 }, /* 292 */ - { 0x2e064494, 0xaaaaaaaa }, /* 293 */ - { 0x2e064498, 0x55555555 }, /* 294 */ - { 0x2e06449c, 0xaaaaaaaa }, /* 295 */ - { 0x2e0644a0, 0x5555 }, /* 296 */ - { 0x2e0644a4, 0x1000100 }, /* 297 */ - { 0x2e0644a8, 0x800180 }, /* 298 */ - { 0x2e064500, 0x4 }, /* 320 */ - { 0x2e06451c, 0x41f07ff }, /* 327 */ - { 0x2e064520, 0x1 }, /* 328 */ - { 0x2e064524, 0x1cc0800 }, /* 329 */ - { 0x2e064528, 0x3003cc08 }, /* 330 */ - { 0x2e06452c, 0x2000014e }, /* 331 */ - { 0x2e064530, 0x7ff0200 }, /* 332 */ - { 0x2e064534, 0x301 }, /* 333 */ - { 0x2e064540, 0x30000 }, /* 336 */ - { 0x2e064554, 0x2000000 }, /* 341 */ - { 0x2e064558, 0x51515042 }, /* 342 */ - { 0x2e06455c, 0x31c06000 }, /* 343 */ - { 0x2e064560, 0x6bf000a }, /* 344 */ - { 0x2e064564, 0xc0c000 }, /* 345 */ - { 0x2e064568, 0x1000000 }, /* 346 */ - { 0x2e06456c, 0x10001000 }, /* 347 */ - { 0x2e064570, 0xc043242 }, /* 348 */ - { 0x2e064574, 0xf0c0e01 }, /* 349 */ - { 0x2e064578, 0x1000140 }, /* 350 */ - { 0x2e06457c, 0xc000120 }, /* 351 */ - { 0x2e064580, 0x118 }, /* 352 */ - { 0x2e064584, 0x1000203 }, /* 353 */ - { 0x2e064588, 0x30217465 }, /* 354 */ - { 0x2e06458c, 0x8 }, /* 355 */ - { 0x2e064590, 0x2980298 }, /* 356 */ - { 0x2e064594, 0x2980298 }, /* 357 */ - { 0x2e064598, 0x2980298 }, /* 358 */ - { 0x2e06459c, 0x2980298 }, /* 359 */ - { 0x2e0645a0, 0x298 }, /* 360 */ - { 0x2e0645a4, 0x8000 }, /* 361 */ - { 0x2e0645a8, 0x800080 }, /* 362 */ - { 0x2e0645ac, 0x800080 }, /* 363 */ - { 0x2e0645b0, 0x800080 }, /* 364 */ - { 0x2e0645b4, 0x800080 }, /* 365 */ - { 0x2e0645b8, 0x800080 }, /* 366 */ - { 0x2e0645bc, 0x800080 }, /* 367 */ - { 0x2e0645c0, 0x800080 }, /* 368 */ - { 0x2e0645c4, 0x800080 }, /* 369 */ - { 0x2e0645c8, 0x1940080 }, /* 370 */ - { 0x2e0645cc, 0x1a00001 }, /* 371 */ - { 0x2e0645d4, 0x10000 }, /* 373 */ - { 0x2e0645d8, 0x80200 }, /* 374 */ - { 0x2e064800, 0x4f0 }, /* 512 */ - { 0x2e064808, 0x1030200 }, /* 514 */ - { 0x2e064814, 0x3000000 }, /* 517 */ - { 0x2e064818, 0x1000001 }, /* 518 */ - { 0x2e06481c, 0x3000400 }, /* 519 */ - { 0x2e064820, 0x1 }, /* 520 */ - { 0x2e064824, 0x1 }, /* 521 */ - { 0x2e064830, 0x10000 }, /* 524 */ - { 0x2e064838, 0xc00004 }, /* 526 */ - { 0x2e06483c, 0xcc0008 }, /* 527 */ - { 0x2e064840, 0x660601 }, /* 528 */ - { 0x2e064844, 0x3 }, /* 529 */ - { 0x2e06484c, 0x1 }, /* 531 */ - { 0x2e064850, 0xaaaa }, /* 532 */ - { 0x2e064854, 0x5555 }, /* 533 */ - { 0x2e064858, 0xb5b5 }, /* 534 */ - { 0x2e06485c, 0x4a4a }, /* 535 */ - { 0x2e064860, 0x5656 }, /* 536 */ - { 0x2e064864, 0xa9a9 }, /* 537 */ - { 0x2e064868, 0xb7b7 }, /* 538 */ - { 0x2e06486c, 0x4848 }, /* 539 */ - { 0x2e064878, 0x8000000 }, /* 542 */ - { 0x2e06487c, 0x4010008 }, /* 543 */ - { 0x2e064880, 0x408 }, /* 544 */ - { 0x2e064884, 0x3102000 }, /* 545 */ - { 0x2e064888, 0xc0020 }, /* 546 */ - { 0x2e06488c, 0x10000 }, /* 547 */ - { 0x2e064890, 0x55555555 }, /* 548 */ - { 0x2e064894, 0xaaaaaaaa }, /* 549 */ - { 0x2e064898, 0x55555555 }, /* 550 */ - { 0x2e06489c, 0xaaaaaaaa }, /* 551 */ - { 0x2e0648a0, 0x5555 }, /* 552 */ - { 0x2e0648a4, 0x1000100 }, /* 553 */ - { 0x2e0648a8, 0x800180 }, /* 554 */ - { 0x2e0648ac, 0x1 }, /* 555 */ - { 0x2e064900, 0x4 }, /* 576 */ - { 0x2e06491c, 0x41f07ff }, /* 583 */ - { 0x2e064920, 0x1 }, /* 584 */ - { 0x2e064924, 0x1cc0800 }, /* 585 */ - { 0x2e064928, 0x3003cc08 }, /* 586 */ - { 0x2e06492c, 0x2000014e }, /* 587 */ - { 0x2e064930, 0x7ff0200 }, /* 588 */ - { 0x2e064934, 0x301 }, /* 589 */ - { 0x2e064940, 0x30000 }, /* 592 */ - { 0x2e064954, 0x2000000 }, /* 597 */ - { 0x2e064958, 0x51515042 }, /* 598 */ - { 0x2e06495c, 0x31c06000 }, /* 599 */ - { 0x2e064960, 0x6bf000a }, /* 600 */ - { 0x2e064964, 0xc0c000 }, /* 601 */ - { 0x2e064968, 0x1000000 }, /* 602 */ - { 0x2e06496c, 0x10001000 }, /* 603 */ - { 0x2e064970, 0xc043242 }, /* 604 */ - { 0x2e064974, 0xf0c0e01 }, /* 605 */ - { 0x2e064978, 0x1000140 }, /* 606 */ - { 0x2e06497c, 0xc000120 }, /* 607 */ - { 0x2e064980, 0x118 }, /* 608 */ - { 0x2e064984, 0x1000203 }, /* 609 */ - { 0x2e064988, 0x75436012 }, /* 610 */ - { 0x2e06498c, 0x8 }, /* 611 */ - { 0x2e064990, 0x2980298 }, /* 612 */ - { 0x2e064994, 0x2980298 }, /* 613 */ - { 0x2e064998, 0x2980298 }, /* 614 */ - { 0x2e06499c, 0x2980298 }, /* 615 */ - { 0x2e0649a0, 0x298 }, /* 616 */ - { 0x2e0649a4, 0x8000 }, /* 617 */ - { 0x2e0649a8, 0x800080 }, /* 618 */ - { 0x2e0649ac, 0x800080 }, /* 619 */ - { 0x2e0649b0, 0x800080 }, /* 620 */ - { 0x2e0649b4, 0x800080 }, /* 621 */ - { 0x2e0649b8, 0x800080 }, /* 622 */ - { 0x2e0649bc, 0x800080 }, /* 623 */ - { 0x2e0649c0, 0x800080 }, /* 624 */ - { 0x2e0649c4, 0x800080 }, /* 625 */ - { 0x2e0649c8, 0x1940080 }, /* 626 */ - { 0x2e0649cc, 0x1a00001 }, /* 627 */ - { 0x2e0649d4, 0x10000 }, /* 629 */ - { 0x2e0649d8, 0x80200 }, /* 630 */ - { 0x2e064c00, 0x4f0 }, /* 768 */ - { 0x2e064c08, 0x1030200 }, /* 770 */ - { 0x2e064c14, 0x3000000 }, /* 773 */ - { 0x2e064c18, 0x1000001 }, /* 774 */ - { 0x2e064c1c, 0x3000400 }, /* 775 */ - { 0x2e064c20, 0x1 }, /* 776 */ - { 0x2e064c24, 0x1 }, /* 777 */ - { 0x2e064c30, 0x10000 }, /* 780 */ - { 0x2e064c38, 0xc00004 }, /* 782 */ - { 0x2e064c3c, 0xcc0008 }, /* 783 */ - { 0x2e064c40, 0x660601 }, /* 784 */ - { 0x2e064c44, 0x3 }, /* 785 */ - { 0x2e064c4c, 0x1 }, /* 787 */ - { 0x2e064c50, 0xaaaa }, /* 788 */ - { 0x2e064c54, 0x5555 }, /* 789 */ - { 0x2e064c58, 0xb5b5 }, /* 790 */ - { 0x2e064c5c, 0x4a4a }, /* 791 */ - { 0x2e064c60, 0x5656 }, /* 792 */ - { 0x2e064c64, 0xa9a9 }, /* 793 */ - { 0x2e064c68, 0xb7b7 }, /* 794 */ - { 0x2e064c6c, 0x4848 }, /* 795 */ - { 0x2e064c78, 0x8000000 }, /* 798 */ - { 0x2e064c7c, 0x4010008 }, /* 799 */ - { 0x2e064c80, 0x408 }, /* 800 */ - { 0x2e064c84, 0x3102000 }, /* 801 */ - { 0x2e064c88, 0xc0020 }, /* 802 */ - { 0x2e064c8c, 0x10000 }, /* 803 */ - { 0x2e064c90, 0x55555555 }, /* 804 */ - { 0x2e064c94, 0xaaaaaaaa }, /* 805 */ - { 0x2e064c98, 0x55555555 }, /* 806 */ - { 0x2e064c9c, 0xaaaaaaaa }, /* 807 */ - { 0x2e064ca0, 0x5555 }, /* 808 */ - { 0x2e064ca4, 0x1000100 }, /* 809 */ - { 0x2e064ca8, 0x800180 }, /* 810 */ - { 0x2e064d00, 0x4 }, /* 832 */ - { 0x2e064d1c, 0x41f07ff }, /* 839 */ - { 0x2e064d20, 0x1 }, /* 840 */ - { 0x2e064d24, 0x1cc0800 }, /* 841 */ - { 0x2e064d28, 0x3003cc08 }, /* 842 */ - { 0x2e064d2c, 0x2000014e }, /* 843 */ - { 0x2e064d30, 0x7ff0200 }, /* 844 */ - { 0x2e064d34, 0x301 }, /* 845 */ - { 0x2e064d40, 0x30000 }, /* 848 */ - { 0x2e064d54, 0x2000000 }, /* 853 */ - { 0x2e064d58, 0x51515042 }, /* 854 */ - { 0x2e064d5c, 0x31c06000 }, /* 855 */ - { 0x2e064d60, 0x6bf000a }, /* 856 */ - { 0x2e064d64, 0xc0c000 }, /* 857 */ - { 0x2e064d68, 0x1000000 }, /* 858 */ - { 0x2e064d6c, 0x10001000 }, /* 859 */ - { 0x2e064d70, 0xc043242 }, /* 860 */ - { 0x2e064d74, 0xf0c0e01 }, /* 861 */ - { 0x2e064d78, 0x1000140 }, /* 862 */ - { 0x2e064d7c, 0xc000120 }, /* 863 */ - { 0x2e064d80, 0x118 }, /* 864 */ - { 0x2e064d84, 0x1000203 }, /* 865 */ - { 0x2e064d88, 0x32017465 }, /* 866 */ - { 0x2e064d8c, 0x8 }, /* 867 */ - { 0x2e064d90, 0x2980298 }, /* 868 */ - { 0x2e064d94, 0x2980298 }, /* 869 */ - { 0x2e064d98, 0x2980298 }, /* 870 */ - { 0x2e064d9c, 0x2980298 }, /* 871 */ - { 0x2e064da0, 0x298 }, /* 872 */ - { 0x2e064da4, 0x8000 }, /* 873 */ - { 0x2e064da8, 0x800080 }, /* 874 */ - { 0x2e064dac, 0x800080 }, /* 875 */ - { 0x2e064db0, 0x800080 }, /* 876 */ - { 0x2e064db4, 0x800080 }, /* 877 */ - { 0x2e064db8, 0x800080 }, /* 878 */ - { 0x2e064dbc, 0x800080 }, /* 879 */ - { 0x2e064dc0, 0x800080 }, /* 880 */ - { 0x2e064dc4, 0x800080 }, /* 881 */ - { 0x2e064dc8, 0x1940080 }, /* 882 */ - { 0x2e064dcc, 0x1a00001 }, /* 883 */ - { 0x2e064dd4, 0x10000 }, /* 885 */ - { 0x2e064dd8, 0x80200 }, /* 886 */ - { 0x2e065014, 0x100 }, /* 1029 */ - { 0x2e065018, 0x201 }, /* 1030 */ - { 0x2e06502c, 0x400000 }, /* 1035 */ - { 0x2e065030, 0x80 }, /* 1036 */ - { 0x2e065034, 0xdcba98 }, /* 1037 */ - { 0x2e065038, 0x3000000 }, /* 1038 */ - { 0x2e06504c, 0x2a }, /* 1043 */ - { 0x2e065050, 0x15 }, /* 1044 */ - { 0x2e065054, 0x15 }, /* 1045 */ - { 0x2e065058, 0x2a }, /* 1046 */ - { 0x2e06505c, 0x33 }, /* 1047 */ - { 0x2e065060, 0xc }, /* 1048 */ - { 0x2e065064, 0xc }, /* 1049 */ - { 0x2e065068, 0x33 }, /* 1050 */ - { 0x2e06506c, 0x543210 }, /* 1051 */ - { 0x2e065070, 0x3f0000 }, /* 1052 */ - { 0x2e065074, 0xf013f }, /* 1053 */ - { 0x2e065078, 0xf }, /* 1054 */ - { 0x2e06507c, 0x3cc }, /* 1055 */ - { 0x2e065080, 0x30000 }, /* 1056 */ - { 0x2e065084, 0x300 }, /* 1057 */ - { 0x2e065088, 0x300 }, /* 1058 */ - { 0x2e06508c, 0x300 }, /* 1059 */ - { 0x2e065090, 0x300 }, /* 1060 */ - { 0x2e065094, 0x300 }, /* 1061 */ - { 0x2e065098, 0x42080010 }, /* 1062 */ - { 0x2e06509c, 0x332 }, /* 1063 */ - { 0x2e0650a0, 0x2 }, /* 1064 */ - { 0x2e065414, 0x100 }, /* 1285 */ - { 0x2e065418, 0x201 }, /* 1286 */ - { 0x2e06542c, 0x400000 }, /* 1291 */ - { 0x2e065430, 0x80 }, /* 1292 */ - { 0x2e065434, 0xdcba98 }, /* 1293 */ - { 0x2e065438, 0x3000000 }, /* 1294 */ - { 0x2e06544c, 0x2a }, /* 1299 */ - { 0x2e065450, 0x15 }, /* 1300 */ - { 0x2e065454, 0x15 }, /* 1301 */ - { 0x2e065458, 0x2a }, /* 1302 */ - { 0x2e06545c, 0x33 }, /* 1303 */ - { 0x2e065460, 0xc }, /* 1304 */ - { 0x2e065464, 0xc }, /* 1305 */ - { 0x2e065468, 0x33 }, /* 1306 */ - { 0x2e06546c, 0x543210 }, /* 1307 */ - { 0x2e065470, 0x3f0000 }, /* 1308 */ - { 0x2e065474, 0xf013f }, /* 1309 */ - { 0x2e065478, 0xf }, /* 1310 */ - { 0x2e06547c, 0x3cc }, /* 1311 */ - { 0x2e065480, 0x30000 }, /* 1312 */ - { 0x2e065484, 0x300 }, /* 1313 */ - { 0x2e065488, 0x300 }, /* 1314 */ - { 0x2e06548c, 0x300 }, /* 1315 */ - { 0x2e065490, 0x300 }, /* 1316 */ - { 0x2e065494, 0x300 }, /* 1317 */ - { 0x2e065498, 0x42080010 }, /* 1318 */ - { 0x2e06549c, 0x332 }, /* 1319 */ - { 0x2e0654a0, 0x2 }, /* 1320 */ - { 0x2e065804, 0x100 }, /* 1537 */ - { 0x2e065814, 0x50000 }, /* 1541 */ - { 0x2e065818, 0x4000100 }, /* 1542 */ - { 0x2e06581c, 0x55 }, /* 1543 */ - { 0x2e06582c, 0xf0001 }, /* 1547 */ - { 0x2e065830, 0x280040 }, /* 1548 */ - { 0x2e065834, 0x5002 }, /* 1549 */ - { 0x2e065838, 0x10101 }, /* 1550 */ - { 0x2e065840, 0x90e0000 }, /* 1552 */ - { 0x2e065844, 0x101010f }, /* 1553 */ - { 0x2e065848, 0x10f0004 }, /* 1554 */ - { 0x2e065854, 0x64 }, /* 1557 */ - { 0x2e06585c, 0x1000000 }, /* 1559 */ - { 0x2e065860, 0x8040201 }, /* 1560 */ - { 0x2e065864, 0x2010201 }, /* 1561 */ - { 0x2e065868, 0xf0f0f }, /* 1562 */ - { 0x2e06586c, 0x241342 }, /* 1563 */ - { 0x2e065874, 0x1020000 }, /* 1565 */ - { 0x2e065878, 0x10701 }, /* 1566 */ - { 0x2e06587c, 0x54 }, /* 1567 */ - { 0x2e065880, 0x4102000 }, /* 1568 */ - { 0x2e065884, 0x24410 }, /* 1569 */ - { 0x2e065888, 0x4410 }, /* 1570 */ - { 0x2e06588c, 0x4410 }, /* 1571 */ - { 0x2e065890, 0x4410 }, /* 1572 */ - { 0x2e065894, 0x4410 }, /* 1573 */ - { 0x2e065898, 0x4410 }, /* 1574 */ - { 0x2e06589c, 0x4410 }, /* 1575 */ - { 0x2e0658a0, 0x4410 }, /* 1576 */ - { 0x2e0658a4, 0x4410 }, /* 1577 */ - { 0x2e0658b0, 0x60000 }, /* 1580 */ - { 0x2e0658b8, 0x64 }, /* 1582 */ - { 0x2e0658bc, 0x10000 }, /* 1583 */ - { 0x2e0658c0, 0x8 }, /* 1584 */ - { 0x2e0658d8, 0x3000000 }, /* 1590 */ - { 0x2e0658e8, 0x4102006 }, /* 1594 */ - { 0x2e0658ec, 0x41020 }, /* 1595 */ - { 0x2e0658f0, 0x1c98c98 }, /* 1596 */ - { 0x2e0658f4, 0x3f400000 }, /* 1597 */ - { 0x2e0658f8, 0x3f3f1f3f }, /* 1598 */ - { 0x2e0658fc, 0x1f }, /* 1599 */ - { 0x2e06590c, 0x1 }, /* 1603 */ - { 0x2e06591c, 0x1 }, /* 1607 */ - { 0x2e065920, 0x76543210 }, /* 1608 */ - { 0x2e065924, 0x10198 }, /* 1609 */ - { 0x2e065934, 0x40700 }, /* 1613 */ - { 0x2e06594c, 0x2 }, /* 1619 */ - { 0x2e065958, 0xf3c3 }, /* 1622 */ - { 0x2e065964, 0x11742 }, /* 1625 */ - { 0x2e065968, 0x3020600 }, /* 1626 */ - { 0x2e06596c, 0x30000 }, /* 1627 */ - { 0x2e065970, 0x3000300 }, /* 1628 */ - { 0x2e065974, 0x3000300 }, /* 1629 */ - { 0x2e065978, 0x3000300 }, /* 1630 */ - { 0x2e06597c, 0x3000300 }, /* 1631 */ - { 0x2e065980, 0x300 }, /* 1632 */ - { 0x2e065984, 0x300 }, /* 1633 */ - { 0x2e065988, 0x300 }, /* 1634 */ - { 0x2e06598c, 0x337cc }, /* 1635 */ - { 0x2e065990, 0x8 }, /* 1636 */ - { 0x2e065994, 0x1b7 }, /* 1637 */ - { 0x2e06599c, 0x1b7 }, /* 1639 */ - { 0x2e0659a4, 0x1b700 }, /* 1641 */ - { 0x2e0659a8, 0x1980000 }, /* 1642 */ - { 0x2e0659ac, 0x1b7cc }, /* 1643 */ - { 0x2e0659b4, 0x1b700 }, /* 1645 */ - { 0x2e0659b8, 0x1980000 }, /* 1646 */ - { 0x2e0659bc, 0x1b700 }, /* 1647 */ - { 0x2e0659c0, 0x1980000 }, /* 1648 */ - { 0x2e0659c4, 0x1b700 }, /* 1649 */ - { 0x2e0659c8, 0x1980000 }, /* 1650 */ - { 0x2e0659cc, 0x1b700 }, /* 1651 */ - { 0x2e0659d0, 0x1980000 }, /* 1652 */ - { 0x2e0659d4, 0x20040003 }, /* 1653 */ -}; - -/** PHY_F2 settings **/ -struct dram_cfg_param ddr_phy_f2_cfg[] = { - { 0x2e064168, 0x3020000 }, /* 90 */ - { 0x2e064170, 0xc043e42 }, /* 92 */ - { 0x2e064174, 0xf0c1701 }, /* 93 */ - { 0x2e064180, 0x187 }, /* 96 */ - { 0x2e064184, 0x3200203 }, /* 97 */ - { 0x2e064190, 0x3070307 }, /* 100 */ - { 0x2e064194, 0x3070307 }, /* 101 */ - { 0x2e064198, 0x3070307 }, /* 102 */ - { 0x2e06419c, 0x3070307 }, /* 103 */ - { 0x2e0641a0, 0x307 }, /* 104 */ - { 0x2e0641c8, 0x1bd0080 }, /* 114 */ - { 0x2e064568, 0x3020000 }, /* 346 */ - { 0x2e064570, 0xc043e42 }, /* 348 */ - { 0x2e064574, 0xf0c1701 }, /* 349 */ - { 0x2e064580, 0x187 }, /* 352 */ - { 0x2e064584, 0x3200203 }, /* 353 */ - { 0x2e064590, 0x3070307 }, /* 356 */ - { 0x2e064594, 0x3070307 }, /* 357 */ - { 0x2e064598, 0x3070307 }, /* 358 */ - { 0x2e06459c, 0x3070307 }, /* 359 */ - { 0x2e0645a0, 0x307 }, /* 360 */ - { 0x2e0645c8, 0x1bd0080 }, /* 370 */ - { 0x2e064968, 0x3020000 }, /* 602 */ - { 0x2e064970, 0xc043e42 }, /* 604 */ - { 0x2e064974, 0xf0c1701 }, /* 605 */ - { 0x2e064980, 0x187 }, /* 608 */ - { 0x2e064984, 0x3200203 }, /* 609 */ - { 0x2e064990, 0x3070307 }, /* 612 */ - { 0x2e064994, 0x3070307 }, /* 613 */ - { 0x2e064998, 0x3070307 }, /* 614 */ - { 0x2e06499c, 0x3070307 }, /* 615 */ - { 0x2e0649a0, 0x307 }, /* 616 */ - { 0x2e0649c8, 0x1bd0080 }, /* 626 */ - { 0x2e064d68, 0x3020000 }, /* 858 */ - { 0x2e064d70, 0xc043e42 }, /* 860 */ - { 0x2e064d74, 0xf0c1701 }, /* 861 */ - { 0x2e064d80, 0x187 }, /* 864 */ - { 0x2e064d84, 0x3200203 }, /* 865 */ - { 0x2e064d90, 0x3070307 }, /* 868 */ - { 0x2e064d94, 0x3070307 }, /* 869 */ - { 0x2e064d98, 0x3070307 }, /* 870 */ - { 0x2e064d9c, 0x3070307 }, /* 871 */ - { 0x2e064da0, 0x307 }, /* 872 */ - { 0x2e064dc8, 0x1bd0080 }, /* 882 */ - { 0x2e06509c, 0x33e }, /* 1063 */ - { 0x2e06549c, 0x33e }, /* 1319 */ - { 0x2e065878, 0x10703 }, /* 1566 */ - { 0x2e065964, 0x1342 }, /* 1625 */ -}; - -/* ddr timing config params */ -struct dram_timing_info2 dram_timing = { - .ctl_cfg = ddr_ctl_cfg, - .ctl_cfg_num = ARRAY_SIZE(ddr_ctl_cfg), - .pi_cfg = ddr_pi_cfg, - .pi_cfg_num = ARRAY_SIZE(ddr_pi_cfg), - .phy_f1_cfg = ddr_phy_f1_cfg, - .phy_f1_cfg_num = ARRAY_SIZE(ddr_phy_f1_cfg), - .phy_f2_cfg = ddr_phy_f2_cfg, - .phy_f2_cfg_num = ARRAY_SIZE(ddr_phy_f2_cfg), - .fsp_table = { 96, 192, 1056 }, -}; diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c deleted file mode 100644 index 79457601461..00000000000 --- a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c +++ /dev/null @@ -1,1109 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2021 NXP - * - * Generated code from MX8ULP_DDR_tool - */ - -#include -#include - -/** CTL settings **/ -struct dram_cfg_param ddr_ctl_cfg[] = { - { 0x2e060000, 0xb00 }, /* 0 */ - { 0x2e060028, 0x258100 }, /* 10 */ - { 0x2e06002c, 0x17702 }, /* 11 */ - { 0x2e060030, 0x5 }, /* 12 */ - { 0x2e060034, 0x61 }, /* 13 */ - { 0x2e060038, 0xce3f }, /* 14 */ - { 0x2e06003c, 0x80e70 }, /* 15 */ - { 0x2e060040, 0x5 }, /* 16 */ - { 0x2e060044, 0x210 }, /* 17 */ - { 0x2e060048, 0x19c7d }, /* 18 */ - { 0x2e06004c, 0x101cdf }, /* 19 */ - { 0x2e060050, 0x5 }, /* 20 */ - { 0x2e060054, 0x420 }, /* 21 */ - { 0x2e060058, 0x1010000 }, /* 22 */ - { 0x2e06005c, 0x1011001 }, /* 23 */ - { 0x2e060060, 0x10000 }, /* 24 */ - { 0x2e060064, 0x102 }, /* 25 */ - { 0x2e060068, 0xa }, /* 26 */ - { 0x2e06006c, 0x19 }, /* 27 */ - { 0x2e060078, 0x2020200 }, /* 30 */ - { 0x2e06007c, 0x160b }, /* 31 */ - { 0x2e060090, 0x10 }, /* 36 */ - { 0x2e0600a4, 0x40c040c }, /* 41 */ - { 0x2e0600a8, 0x8040614 }, /* 42 */ - { 0x2e0600ac, 0x604 }, /* 43 */ - { 0x2e0600b0, 0x3090003 }, /* 44 */ - { 0x2e0600b4, 0x40002 }, /* 45 */ - { 0x2e0600b8, 0xc0011 }, /* 46 */ - { 0x2e0600bc, 0xb0509 }, /* 47 */ - { 0x2e0600c0, 0x2106 }, /* 48 */ - { 0x2e0600c4, 0xa090017 }, /* 49 */ - { 0x2e0600c8, 0x8200016 }, /* 50 */ - { 0x2e0600cc, 0xa0a }, /* 51 */ - { 0x2e0600d0, 0x4000694 }, /* 52 */ - { 0x2e0600d4, 0xa0a0804 }, /* 53 */ - { 0x2e0600d8, 0x4002432 }, /* 54 */ - { 0x2e0600dc, 0xa0a0804 }, /* 55 */ - { 0x2e0600e0, 0x4004864 }, /* 56 */ - { 0x2e0600e4, 0x2030404 }, /* 57 */ - { 0x2e0600e8, 0x5040400 }, /* 58 */ - { 0x2e0600ec, 0x80b0a06 }, /* 59 */ - { 0x2e0600f0, 0x7010100 }, /* 60 */ - { 0x2e0600f4, 0x4150b }, /* 61 */ - { 0x2e0600fc, 0x1010000 }, /* 63 */ - { 0x2e060100, 0x1000000 }, /* 64 */ - { 0x2e060104, 0xe0403 }, /* 65 */ - { 0x2e060108, 0xb3 }, /* 66 */ - { 0x2e06010c, 0x4a }, /* 67 */ - { 0x2e060110, 0x3fd }, /* 68 */ - { 0x2e060114, 0x94 }, /* 69 */ - { 0x2e060118, 0x803 }, /* 70 */ - { 0x2e06011c, 0x5 }, /* 71 */ - { 0x2e060120, 0x70000 }, /* 72 */ - { 0x2e060124, 0x25000f }, /* 73 */ - { 0x2e060128, 0x4a0078 }, /* 74 */ - { 0x2e06012c, 0x4000f9 }, /* 75 */ - { 0x2e060130, 0x120103 }, /* 76 */ - { 0x2e060134, 0x50005 }, /* 77 */ - { 0x2e060138, 0x8070005 }, /* 78 */ - { 0x2e06013c, 0x505010d }, /* 79 */ - { 0x2e060140, 0x101030a }, /* 80 */ - { 0x2e060144, 0x30a0505 }, /* 81 */ - { 0x2e060148, 0x5050101 }, /* 82 */ - { 0x2e06014c, 0x1030a }, /* 83 */ - { 0x2e060150, 0xe000e }, /* 84 */ - { 0x2e060154, 0x4c004c }, /* 85 */ - { 0x2e060158, 0x980098 }, /* 86 */ - { 0x2e06015c, 0x3050505 }, /* 87 */ - { 0x2e060160, 0x3010403 }, /* 88 */ - { 0x2e060164, 0x4050505 }, /* 89 */ - { 0x2e060168, 0x3010403 }, /* 90 */ - { 0x2e06016c, 0x8050505 }, /* 91 */ - { 0x2e060170, 0x3010403 }, /* 92 */ - { 0x2e060174, 0x3010000 }, /* 93 */ - { 0x2e060178, 0x10000 }, /* 94 */ - { 0x2e060180, 0x1000000 }, /* 96 */ - { 0x2e060184, 0x80104002 }, /* 97 */ - { 0x2e060188, 0x40003 }, /* 98 */ - { 0x2e06018c, 0x40005 }, /* 99 */ - { 0x2e060190, 0x30000 }, /* 100 */ - { 0x2e060194, 0x50004 }, /* 101 */ - { 0x2e060198, 0x4 }, /* 102 */ - { 0x2e06019c, 0x40003 }, /* 103 */ - { 0x2e0601a0, 0x40005 }, /* 104 */ - { 0x2e0601a8, 0x2cc0 }, /* 106 */ - { 0x2e0601ac, 0x2cc0 }, /* 107 */ - { 0x2e0601b0, 0x2cc0 }, /* 108 */ - { 0x2e0601b4, 0x2cc0 }, /* 109 */ - { 0x2e0601b8, 0x2cc0 }, /* 110 */ - { 0x2e0601c0, 0x4e5 }, /* 112 */ - { 0x2e0601c4, 0xff40 }, /* 113 */ - { 0x2e0601c8, 0xff40 }, /* 114 */ - { 0x2e0601cc, 0xff40 }, /* 115 */ - { 0x2e0601d0, 0xff40 }, /* 116 */ - { 0x2e0601d4, 0xff40 }, /* 117 */ - { 0x2e0601dc, 0x1beb }, /* 119 */ - { 0x2e0601e0, 0x200c0 }, /* 120 */ - { 0x2e0601e4, 0x200c0 }, /* 121 */ - { 0x2e0601e8, 0x200c0 }, /* 122 */ - { 0x2e0601ec, 0x200c0 }, /* 123 */ - { 0x2e0601f0, 0x200c0 }, /* 124 */ - { 0x2e0601f8, 0x3815 }, /* 126 */ - { 0x2e06021c, 0x5000000 }, /* 135 */ - { 0x2e060220, 0x5030503 }, /* 136 */ - { 0x2e060224, 0x3 }, /* 137 */ - { 0x2e060228, 0x7010a09 }, /* 138 */ - { 0x2e06022c, 0xe0a09 }, /* 139 */ - { 0x2e060230, 0x10a0900 }, /* 140 */ - { 0x2e060234, 0xe0a0907 }, /* 141 */ - { 0x2e060238, 0xa090000 }, /* 142 */ - { 0x2e06023c, 0xa090701 }, /* 143 */ - { 0x2e060240, 0x101000e }, /* 144 */ - { 0x2e060244, 0x40003 }, /* 145 */ - { 0x2e060248, 0x7 }, /* 146 */ - { 0x2e060264, 0x4040100 }, /* 153 */ - { 0x2e060268, 0x1000000 }, /* 154 */ - { 0x2e06026c, 0x100000c0 }, /* 155 */ - { 0x2e060270, 0x100000c0 }, /* 156 */ - { 0x2e060274, 0x100000c0 }, /* 157 */ - { 0x2e06027c, 0x1600 }, /* 159 */ - { 0x2e060284, 0x1 }, /* 161 */ - { 0x2e060288, 0x2 }, /* 162 */ - { 0x2e06028c, 0x100e }, /* 163 */ - { 0x2e0602a4, 0xa0000 }, /* 169 */ - { 0x2e0602a8, 0xd0005 }, /* 170 */ - { 0x2e0602ac, 0x404 }, /* 171 */ - { 0x2e0602b0, 0xd }, /* 172 */ - { 0x2e0602b4, 0x1b0035 }, /* 173 */ - { 0x2e0602b8, 0x4040042 }, /* 174 */ - { 0x2e0602bc, 0x42 }, /* 175 */ - { 0x2e0602c0, 0x35006a }, /* 176 */ - { 0x2e0602c4, 0x4040084 }, /* 177 */ - { 0x2e0602c8, 0x84 }, /* 178 */ - { 0x2e0602d8, 0x40004 }, /* 182 */ - { 0x2e0602dc, 0x30000914 }, /* 183 */ - { 0x2e0602e0, 0x3030 }, /* 184 */ - { 0x2e0602e4, 0x44440000 }, /* 185 */ - { 0x2e0602e8, 0x19191944 }, /* 186 */ - { 0x2e0602ec, 0x19191908 }, /* 187 */ - { 0x2e0602f0, 0x4000000 }, /* 188 */ - { 0x2e0602f4, 0x40404 }, /* 189 */ - { 0x2e0602f8, 0x9140004 }, /* 190 */ - { 0x2e0602fc, 0x30303000 }, /* 191 */ - { 0x2e060304, 0x19444444 }, /* 193 */ - { 0x2e060308, 0x19081919 }, /* 194 */ - { 0x2e06030c, 0x1919 }, /* 195 */ - { 0x2e060310, 0x4040400 }, /* 196 */ - { 0x2e060314, 0x1010120 }, /* 197 */ - { 0x2e060318, 0x1000100 }, /* 198 */ - { 0x2e06031c, 0x1 }, /* 199 */ - { 0x2e060324, 0x1000000 }, /* 201 */ - { 0x2e060328, 0x1 }, /* 202 */ - { 0x2e060354, 0x11000000 }, /* 213 */ - { 0x2e060358, 0x40c1815 }, /* 214 */ - { 0x2e060390, 0x30000 }, /* 228 */ - { 0x2e060394, 0x1000200 }, /* 229 */ - { 0x2e060398, 0x310040 }, /* 230 */ - { 0x2e06039c, 0x20002 }, /* 231 */ - { 0x2e0603a0, 0x400100 }, /* 232 */ - { 0x2e0603a4, 0x80108 }, /* 233 */ - { 0x2e0603a8, 0x1000200 }, /* 234 */ - { 0x2e0603ac, 0x2100040 }, /* 235 */ - { 0x2e0603b0, 0x10 }, /* 236 */ - { 0x2e0603b4, 0xe0003 }, /* 237 */ - { 0x2e0603b8, 0x100001b }, /* 238 */ - { 0x2e0603d8, 0xffff0b00 }, /* 246 */ - { 0x2e0603dc, 0x1010001 }, /* 247 */ - { 0x2e0603e0, 0x1010101 }, /* 248 */ - { 0x2e0603e4, 0x10b0101 }, /* 249 */ - { 0x2e0603e8, 0x10000 }, /* 250 */ - { 0x2e0603ec, 0x4010101 }, /* 251 */ - { 0x2e0603f0, 0x1010000 }, /* 252 */ - { 0x2e0603f4, 0x4 }, /* 253 */ - { 0x2e0603fc, 0x3030101 }, /* 255 */ - { 0x2e060400, 0x103 }, /* 256 */ - { 0x2e0604a4, 0x2020101 }, /* 297 */ - { 0x2e0604a8, 0x10100 }, /* 298 */ - { 0x2e0604ac, 0x1000101 }, /* 299 */ - { 0x2e0604b0, 0x1010101 }, /* 300 */ - { 0x2e0604b4, 0x4030300 }, /* 301 */ - { 0x2e0604b8, 0x8080505 }, /* 302 */ - { 0x2e0604bc, 0x8020808 }, /* 303 */ - { 0x2e0604c0, 0x8020e00 }, /* 304 */ - { 0x2e0604c4, 0xa020e00 }, /* 305 */ - { 0x2e0604c8, 0x8000f00 }, /* 306 */ - { 0x2e0604cc, 0xa08 }, /* 307 */ - { 0x2e0604d0, 0x1010101 }, /* 308 */ - { 0x2e0604d4, 0x01000102 }, /* 309 */ - { 0x2e0604d8, 0x00000101 }, /* 310 */ - { 0x2e0604dc, 0x40400 }, /* 311 */ - { 0x2e0604e0, 0x4040000 }, /* 312 */ - { 0x2e0604e4, 0x4000000 }, /* 313 */ - { 0x2e0604e8, 0x10004 }, /* 314 */ - { 0x2e0604f0, 0xfffff }, /* 316 */ - { 0x2e0604f8, 0xfffff }, /* 318 */ - { 0x2e060500, 0xfffff }, /* 320 */ - { 0x2e060508, 0xfffff }, /* 322 */ - { 0x2e060510, 0xfffff }, /* 324 */ - { 0x2e060518, 0xfffff }, /* 326 */ - { 0x2e060520, 0xfffff }, /* 328 */ - { 0x2e060528, 0xfffff }, /* 330 */ - { 0x2e060530, 0xfffff }, /* 332 */ - { 0x2e060538, 0xfffff }, /* 334 */ - { 0x2e060540, 0xfffff }, /* 336 */ - { 0x2e060548, 0xfffff }, /* 338 */ - { 0x2e060550, 0xfffff }, /* 340 */ - { 0x2e060558, 0xfffff }, /* 342 */ - { 0x2e060560, 0xfffff }, /* 344 */ - { 0x2e060568, 0xfffff }, /* 346 */ - { 0x2e060570, 0xfffff }, /* 348 */ - { 0x2e060578, 0xfffff }, /* 350 */ - { 0x2e060580, 0xfffff }, /* 352 */ - { 0x2e060588, 0xfffff }, /* 354 */ - { 0x2e060590, 0xfffff }, /* 356 */ - { 0x2e060598, 0xfffff }, /* 358 */ - { 0x2e0605a0, 0xfffff }, /* 360 */ - { 0x2e0605a8, 0xfffff }, /* 362 */ - { 0x2e0605b0, 0xfffff }, /* 364 */ - { 0x2e0605b8, 0xfffff }, /* 366 */ - { 0x2e0605c0, 0xfffff }, /* 368 */ - { 0x2e0605c8, 0xfffff }, /* 370 */ - { 0x2e0605d0, 0xfffff }, /* 372 */ - { 0x2e0605d8, 0xfffff }, /* 374 */ - { 0x2e0605e0, 0xfffff }, /* 376 */ - { 0x2e0605e8, 0xfffff }, /* 378 */ - { 0x2e0605f0, 0xfffff }, /* 380 */ - { 0x2e0605f8, 0xfffff }, /* 382 */ - { 0x2e060600, 0xfffff }, /* 384 */ - { 0x2e060608, 0xfffff }, /* 386 */ - { 0x2e060610, 0xfffff }, /* 388 */ - { 0x2e060618, 0xfffff }, /* 390 */ - { 0x2e060620, 0xfffff }, /* 392 */ - { 0x2e060628, 0xfffff }, /* 394 */ - { 0x2e060630, 0xfffff }, /* 396 */ - { 0x2e060638, 0xfffff }, /* 398 */ - { 0x2e060640, 0xfffff }, /* 400 */ - { 0x2e060648, 0xfffff }, /* 402 */ - { 0x2e060650, 0xfffff }, /* 404 */ - { 0x2e060658, 0xfffff }, /* 406 */ - { 0x2e060660, 0xfffff }, /* 408 */ - { 0x2e060668, 0xfffff }, /* 410 */ - { 0x2e060670, 0xfffff }, /* 412 */ - { 0x2e060678, 0xfffff }, /* 414 */ - { 0x2e060680, 0xfffff }, /* 416 */ - { 0x2e060688, 0xfffff }, /* 418 */ - { 0x2e060690, 0xfffff }, /* 420 */ - { 0x2e060698, 0xfffff }, /* 422 */ - { 0x2e0606a0, 0xfffff }, /* 424 */ - { 0x2e0606a8, 0xfffff }, /* 426 */ - { 0x2e0606b0, 0xfffff }, /* 428 */ - { 0x2e0606b8, 0xfffff }, /* 430 */ - { 0x2e0606c0, 0xfffff }, /* 432 */ - { 0x2e0606c8, 0xfffff }, /* 434 */ - { 0x2e0606d0, 0xfffff }, /* 436 */ - { 0x2e0606d8, 0xfffff }, /* 438 */ - { 0x2e0606e0, 0xfffff }, /* 440 */ - { 0x2e0606e8, 0x30fffff }, /* 442 */ - { 0x2e0606ec, 0xffffffff }, /* 443 */ - { 0x2e0606f0, 0x30f0f }, /* 444 */ - { 0x2e0606f4, 0xffffffff }, /* 445 */ - { 0x2e0606f8, 0x30f0f }, /* 446 */ - { 0x2e0606fc, 0xffffffff }, /* 447 */ - { 0x2e060700, 0x30f0f }, /* 448 */ - { 0x2e060704, 0xffffffff }, /* 449 */ - { 0x2e060708, 0x30f0f }, /* 450 */ - { 0x2e06070c, 0xffffffff }, /* 451 */ - { 0x2e060710, 0x30f0f }, /* 452 */ - { 0x2e060714, 0xffffffff }, /* 453 */ - { 0x2e060718, 0x30f0f }, /* 454 */ - { 0x2e06071c, 0xffffffff }, /* 455 */ - { 0x2e060720, 0x30f0f }, /* 456 */ - { 0x2e060724, 0xffffffff }, /* 457 */ - { 0x2e060728, 0x30f0f }, /* 458 */ - { 0x2e06072c, 0xffffffff }, /* 459 */ - { 0x2e060730, 0x30f0f }, /* 460 */ - { 0x2e060734, 0xffffffff }, /* 461 */ - { 0x2e060738, 0x30f0f }, /* 462 */ - { 0x2e06073c, 0xffffffff }, /* 463 */ - { 0x2e060740, 0x30f0f }, /* 464 */ - { 0x2e060744, 0xffffffff }, /* 465 */ - { 0x2e060748, 0x30f0f }, /* 466 */ - { 0x2e06074c, 0xffffffff }, /* 467 */ - { 0x2e060750, 0x30f0f }, /* 468 */ - { 0x2e060754, 0xffffffff }, /* 469 */ - { 0x2e060758, 0x30f0f }, /* 470 */ - { 0x2e06075c, 0xffffffff }, /* 471 */ - { 0x2e060760, 0x30f0f }, /* 472 */ - { 0x2e060764, 0xffffffff }, /* 473 */ - { 0x2e060768, 0x30f0f }, /* 474 */ - { 0x2e06076c, 0xffffffff }, /* 475 */ - { 0x2e060770, 0x30f0f }, /* 476 */ - { 0x2e060774, 0xffffffff }, /* 477 */ - { 0x2e060778, 0x30f0f }, /* 478 */ - { 0x2e06077c, 0xffffffff }, /* 479 */ - { 0x2e060780, 0x30f0f }, /* 480 */ - { 0x2e060784, 0xffffffff }, /* 481 */ - { 0x2e060788, 0x30f0f }, /* 482 */ - { 0x2e06078c, 0xffffffff }, /* 483 */ - { 0x2e060790, 0x30f0f }, /* 484 */ - { 0x2e060794, 0xffffffff }, /* 485 */ - { 0x2e060798, 0x30f0f }, /* 486 */ - { 0x2e06079c, 0xffffffff }, /* 487 */ - { 0x2e0607a0, 0x30f0f }, /* 488 */ - { 0x2e0607a4, 0xffffffff }, /* 489 */ - { 0x2e0607a8, 0x30f0f }, /* 490 */ - { 0x2e0607ac, 0xffffffff }, /* 491 */ - { 0x2e0607b0, 0x30f0f }, /* 492 */ - { 0x2e0607b4, 0xffffffff }, /* 493 */ - { 0x2e0607b8, 0x30f0f }, /* 494 */ - { 0x2e0607bc, 0xffffffff }, /* 495 */ - { 0x2e0607c0, 0x30f0f }, /* 496 */ - { 0x2e0607c4, 0xffffffff }, /* 497 */ - { 0x2e0607c8, 0x30f0f }, /* 498 */ - { 0x2e0607cc, 0xffffffff }, /* 499 */ - { 0x2e0607d0, 0x30f0f }, /* 500 */ - { 0x2e0607d4, 0xffffffff }, /* 501 */ - { 0x2e0607d8, 0x30f0f }, /* 502 */ - { 0x2e0607dc, 0xffffffff }, /* 503 */ - { 0x2e0607e0, 0x30f0f }, /* 504 */ - { 0x2e0607e4, 0xffffffff }, /* 505 */ - { 0x2e0607e8, 0x30f0f }, /* 506 */ - { 0x2e0607ec, 0xffffffff }, /* 507 */ - { 0x2e0607f0, 0x30f0f }, /* 508 */ - { 0x2e0607f4, 0xffffffff }, /* 509 */ - { 0x2e0607f8, 0x30f0f }, /* 510 */ - { 0x2e0607fc, 0xffffffff }, /* 511 */ - { 0x2e060800, 0x30f0f }, /* 512 */ - { 0x2e060804, 0xffffffff }, /* 513 */ - { 0x2e060808, 0x30f0f }, /* 514 */ - { 0x2e06080c, 0xffffffff }, /* 515 */ - { 0x2e060810, 0x30f0f }, /* 516 */ - { 0x2e060814, 0xffffffff }, /* 517 */ - { 0x2e060818, 0x30f0f }, /* 518 */ - { 0x2e06081c, 0xffffffff }, /* 519 */ - { 0x2e060820, 0x30f0f }, /* 520 */ - { 0x2e060824, 0xffffffff }, /* 521 */ - { 0x2e060828, 0x30f0f }, /* 522 */ - { 0x2e06082c, 0xffffffff }, /* 523 */ - { 0x2e060830, 0x30f0f }, /* 524 */ - { 0x2e060834, 0xffffffff }, /* 525 */ - { 0x2e060838, 0x30f0f }, /* 526 */ - { 0x2e06083c, 0xffffffff }, /* 527 */ - { 0x2e060840, 0x30f0f }, /* 528 */ - { 0x2e060844, 0xffffffff }, /* 529 */ - { 0x2e060848, 0x30f0f }, /* 530 */ - { 0x2e06084c, 0xffffffff }, /* 531 */ - { 0x2e060850, 0x30f0f }, /* 532 */ - { 0x2e060854, 0xffffffff }, /* 533 */ - { 0x2e060858, 0x30f0f }, /* 534 */ - { 0x2e06085c, 0xffffffff }, /* 535 */ - { 0x2e060860, 0x30f0f }, /* 536 */ - { 0x2e060864, 0xffffffff }, /* 537 */ - { 0x2e060868, 0x30f0f }, /* 538 */ - { 0x2e06086c, 0xffffffff }, /* 539 */ - { 0x2e060870, 0x30f0f }, /* 540 */ - { 0x2e060874, 0xffffffff }, /* 541 */ - { 0x2e060878, 0x30f0f }, /* 542 */ - { 0x2e06087c, 0xffffffff }, /* 543 */ - { 0x2e060880, 0x30f0f }, /* 544 */ - { 0x2e060884, 0xffffffff }, /* 545 */ - { 0x2e060888, 0x30f0f }, /* 546 */ - { 0x2e06088c, 0xffffffff }, /* 547 */ - { 0x2e060890, 0x30f0f }, /* 548 */ - { 0x2e060894, 0xffffffff }, /* 549 */ - { 0x2e060898, 0x30f0f }, /* 550 */ - { 0x2e06089c, 0xffffffff }, /* 551 */ - { 0x2e0608a0, 0x30f0f }, /* 552 */ - { 0x2e0608a4, 0xffffffff }, /* 553 */ - { 0x2e0608a8, 0x30f0f }, /* 554 */ - { 0x2e0608ac, 0xffffffff }, /* 555 */ - { 0x2e0608b0, 0x30f0f }, /* 556 */ - { 0x2e0608b4, 0xffffffff }, /* 557 */ - { 0x2e0608b8, 0x30f0f }, /* 558 */ - { 0x2e0608bc, 0xffffffff }, /* 559 */ - { 0x2e0608c0, 0x30f0f }, /* 560 */ - { 0x2e0608c4, 0xffffffff }, /* 561 */ - { 0x2e0608c8, 0x30f0f }, /* 562 */ - { 0x2e0608cc, 0xffffffff }, /* 563 */ - { 0x2e0608d0, 0x30f0f }, /* 564 */ - { 0x2e0608d4, 0xffffffff }, /* 565 */ - { 0x2e0608d8, 0x30f0f }, /* 566 */ - { 0x2e0608dc, 0xffffffff }, /* 567 */ - { 0x2e0608e0, 0x30f0f }, /* 568 */ - { 0x2e0608e4, 0xffffffff }, /* 569 */ - { 0x2e0608e8, 0x32070f0f }, /* 570 */ - { 0x2e0608ec, 0x1320000 }, /* 571 */ - { 0x2e0608f0, 0x13200 }, /* 572 */ - { 0x2e0608f4, 0x132 }, /* 573 */ - { 0x2e0608fc, 0x1d1b0000 }, /* 575 */ - { 0x2e060900, 0x21 }, /* 576 */ - { 0x2e060904, 0xa }, /* 577 */ - { 0x2e060908, 0x166 }, /* 578 */ - { 0x2e06090c, 0x200 }, /* 579 */ - { 0x2e060910, 0x200 }, /* 580 */ - { 0x2e060914, 0x200 }, /* 581 */ - { 0x2e060918, 0x200 }, /* 582 */ - { 0x2e06091c, 0x432 }, /* 583 */ - { 0x2e060920, 0xdfc }, /* 584 */ - { 0x2e060924, 0x204 }, /* 585 */ - { 0x2e060928, 0x7fa }, /* 586 */ - { 0x2e06092c, 0x200 }, /* 587 */ - { 0x2e060930, 0x200 }, /* 588 */ - { 0x2e060934, 0x200 }, /* 589 */ - { 0x2e060938, 0x200 }, /* 590 */ - { 0x2e06093c, 0x17ee }, /* 591 */ - { 0x2e060940, 0x4fc4 }, /* 592 */ - { 0x2e060944, 0x204 }, /* 593 */ - { 0x2e060948, 0x1006 }, /* 594 */ - { 0x2e06094c, 0x200 }, /* 595 */ - { 0x2e060950, 0x200 }, /* 596 */ - { 0x2e060954, 0x200 }, /* 597 */ - { 0x2e060958, 0x200 }, /* 598 */ - { 0x2e06095c, 0x3012 }, /* 599 */ - { 0x2e060960, 0xa03c }, /* 600 */ - { 0x2e060964, 0x2020406 }, /* 601 */ - { 0x2e060968, 0x2030202 }, /* 602 */ - { 0x2e06096c, 0x1000202 }, /* 603 */ - { 0x2e060970, 0x3040100 }, /* 604 */ - { 0x2e060974, 0x10105 }, /* 605 */ - { 0x2e060978, 0x10101 }, /* 606 */ - { 0x2e06097c, 0x10101 }, /* 607 */ - { 0x2e060980, 0x10001 }, /* 608 */ - { 0x2e060984, 0x101 }, /* 609 */ - { 0x2e060988, 0x2000201 }, /* 610 */ - { 0x2e06098c, 0x2010000 }, /* 611 */ - { 0x2e060990, 0x6000200 }, /* 612 */ - { 0x2e060994, 0x3000a06 }, /* 613 */ - { 0x2e060998, 0x2000c06 }, /* 614 */ -}; - -/** PI settings **/ -struct dram_cfg_param ddr_pi_cfg[] = { - { 0x2e062000, 0xb00 }, /* 0 */ - { 0x2e062004, 0xbeedb66f }, /* 1 */ - { 0x2e062008, 0xabef6bd }, /* 2 */ - { 0x2e06200c, 0x1001387 }, /* 3 */ - { 0x2e062010, 0x1 }, /* 4 */ - { 0x2e062014, 0x10064 }, /* 5 */ - { 0x2e06202c, 0x101 }, /* 11 */ - { 0x2e062030, 0x3 }, /* 12 */ - { 0x2e062034, 0x50001 }, /* 13 */ - { 0x2e062038, 0x3030800 }, /* 14 */ - { 0x2e06203c, 0x1 }, /* 15 */ - { 0x2e062040, 0x5 }, /* 16 */ - { 0x2e062064, 0x1000000 }, /* 25 */ - { 0x2e062068, 0xa000001 }, /* 26 */ - { 0x2e06206c, 0x28 }, /* 27 */ - { 0x2e062070, 0x1 }, /* 28 */ - { 0x2e062074, 0x320005 }, /* 29 */ - { 0x2e062080, 0x10102 }, /* 32 */ - { 0x2e062084, 0x1 }, /* 33 */ - { 0x2e062088, 0xaa }, /* 34 */ - { 0x2e06208c, 0x55 }, /* 35 */ - { 0x2e062090, 0xb5 }, /* 36 */ - { 0x2e062094, 0x4a }, /* 37 */ - { 0x2e062098, 0x56 }, /* 38 */ - { 0x2e06209c, 0xa9 }, /* 39 */ - { 0x2e0620a0, 0xa9 }, /* 40 */ - { 0x2e0620a4, 0xb5 }, /* 41 */ - { 0x2e0620a8, 0x10000 }, /* 42 */ - { 0x2e0620ac, 0x100 }, /* 43 */ - { 0x2e0620b0, 0x5050000 }, /* 44 */ - { 0x2e0620b4, 0x13 }, /* 45 */ - { 0x2e0620b8, 0x7d0 }, /* 46 */ - { 0x2e0620bc, 0x300 }, /* 47 */ - { 0x2e0620c8, 0x1000000 }, /* 50 */ - { 0x2e0620cc, 0x10101 }, /* 51 */ - { 0x2e0620d8, 0x10003 }, /* 54 */ - { 0x2e0620dc, 0x170500 }, /* 55 */ - { 0x2e0620ec, 0xa140a01 }, /* 59 */ - { 0x2e0620f0, 0x204010a }, /* 60 */ - { 0x2e0620f4, 0x21010 }, /* 61 */ - { 0x2e0620f8, 0x40401 }, /* 62 */ - { 0x2e0620fc, 0x10e0005 }, /* 63 */ - { 0x2e062100, 0x5000001 }, /* 64 */ - { 0x2e062104, 0x204 }, /* 65 */ - { 0x2e062108, 0x34 }, /* 66 */ - { 0x2e062114, 0x1000000 }, /* 69 */ - { 0x2e062118, 0x1000000 }, /* 70 */ - { 0x2e06211c, 0x80200 }, /* 71 */ - { 0x2e062120, 0x2000200 }, /* 72 */ - { 0x2e062124, 0x1000100 }, /* 73 */ - { 0x2e062128, 0x1000000 }, /* 74 */ - { 0x2e06212c, 0x2000200 }, /* 75 */ - { 0x2e062130, 0x200 }, /* 76 */ - { 0x2e062164, 0x400 }, /* 89 */ - { 0x2e062168, 0x2010000 }, /* 90 */ - { 0x2e06216c, 0x80103 }, /* 91 */ - { 0x2e062174, 0x10008 }, /* 93 */ - { 0x2e06217c, 0xaa00 }, /* 95 */ - { 0x2e062188, 0x10000 }, /* 98 */ - { 0x2e0621ec, 0x8 }, /* 123 */ - { 0x2e062218, 0xf0000 }, /* 134 */ - { 0x2e06221c, 0xa }, /* 135 */ - { 0x2e062220, 0x19 }, /* 136 */ - { 0x2e062224, 0x100 }, /* 137 */ - { 0x2e062228, 0x100 }, /* 138 */ - { 0x2e062238, 0x1000000 }, /* 142 */ - { 0x2e06223c, 0x10003 }, /* 143 */ - { 0x2e062240, 0x2000101 }, /* 144 */ - { 0x2e062244, 0x1030001 }, /* 145 */ - { 0x2e062248, 0x10400 }, /* 146 */ - { 0x2e06224c, 0x6000105 }, /* 147 */ - { 0x2e062250, 0x1070001 }, /* 148 */ - { 0x2e062260, 0x10001 }, /* 152 */ - { 0x2e062274, 0x401 }, /* 157 */ - { 0x2e06227c, 0x10000 }, /* 159 */ - { 0x2e062284, 0x6010000 }, /* 161 */ - { 0x2e062288, 0xb }, /* 162 */ - { 0x2e06228c, 0x34 }, /* 163 */ - { 0x2e062290, 0x36 }, /* 164 */ - { 0x2e062294, 0x2003c }, /* 165 */ - { 0x2e062298, 0x2000200 }, /* 166 */ - { 0x2e06229c, 0xc040c04 }, /* 167 */ - { 0x2e0622a0, 0xe1406 }, /* 168 */ - { 0x2e0622a4, 0xb3 }, /* 169 */ - { 0x2e0622a8, 0x4a }, /* 170 */ - { 0x2e0622ac, 0x3fd }, /* 171 */ - { 0x2e0622b0, 0x94 }, /* 172 */ - { 0x2e0622b4, 0x4000803 }, /* 173 */ - { 0x2e0622b8, 0x1010404 }, /* 174 */ - { 0x2e0622bc, 0x1501 }, /* 175 */ - { 0x2e0622c0, 0x1a0018 }, /* 176 */ - { 0x2e0622c4, 0x1000100 }, /* 177 */ - { 0x2e0622c8, 0x100 }, /* 178 */ - { 0x2e0622d0, 0x5040303 }, /* 180 */ - { 0x2e0622d4, 0x1010805 }, /* 181 */ - { 0x2e0622d8, 0x1010101 }, /* 182 */ - { 0x2e0622e8, 0x2060404 }, /* 186 */ - { 0x2e0622ec, 0x2020402 }, /* 187 */ - { 0x2e0622f0, 0x3102 }, /* 188 */ - { 0x2e0622f4, 0x340009 }, /* 189 */ - { 0x2e0622f8, 0x36000c }, /* 190 */ - { 0x2e0622fc, 0x101000e }, /* 191 */ - { 0x2e062300, 0xd0101 }, /* 192 */ - { 0x2e062304, 0x1004201 }, /* 193 */ - { 0x2e062308, 0x1000084 }, /* 194 */ - { 0x2e06230c, 0xe000e }, /* 195 */ - { 0x2e062310, 0x430100 }, /* 196 */ - { 0x2e062314, 0x1000043 }, /* 197 */ - { 0x2e062318, 0x850085 }, /* 198 */ - { 0x2e06231c, 0x220f220f }, /* 199 */ - { 0x2e062320, 0x101220f }, /* 200 */ - { 0x2e062324, 0xa070601 }, /* 201 */ - { 0x2e062328, 0xa07060d }, /* 202 */ - { 0x2e06232c, 0xa07070d }, /* 203 */ - { 0x2e062330, 0xc00d }, /* 204 */ - { 0x2e062334, 0xc01000 }, /* 205 */ - { 0x2e062338, 0xc01000 }, /* 206 */ - { 0x2e06233c, 0x21000 }, /* 207 */ - { 0x2e062340, 0x11000d }, /* 208 */ - { 0x2e062344, 0x140042 }, /* 209 */ - { 0x2e062348, 0x190084 }, /* 210 */ - { 0x2e06234c, 0x220f0056 }, /* 211 */ - { 0x2e062350, 0x101 }, /* 212 */ - { 0x2e062354, 0x560019 }, /* 213 */ - { 0x2e062358, 0x101220f }, /* 214 */ - { 0x2e06235c, 0x1b00 }, /* 215 */ - { 0x2e062360, 0x220f0056 }, /* 216 */ - { 0x2e062364, 0x8000101 }, /* 217 */ - { 0x2e062368, 0x4090403 }, /* 218 */ - { 0x2e06236c, 0x5eb }, /* 219 */ - { 0x2e062370, 0x20010003 }, /* 220 */ - { 0x2e062374, 0x80a0a03 }, /* 221 */ - { 0x2e062378, 0x6090506 }, /* 222 */ - { 0x2e06237c, 0x2093 }, /* 223 */ - { 0x2e062380, 0x2001000c }, /* 224 */ - { 0x2e062384, 0x80a0a04 }, /* 225 */ - { 0x2e062388, 0xb090a0c }, /* 226 */ - { 0x2e06238c, 0x4126 }, /* 227 */ - { 0x2e062390, 0x20020017 }, /* 228 */ - { 0x2e062394, 0xa0a08 }, /* 229 */ - { 0x2e062398, 0x166 }, /* 230 */ - { 0x2e06239c, 0xdfc }, /* 231 */ - { 0x2e0623a0, 0x7fa }, /* 232 */ - { 0x2e0623a4, 0x4fc4 }, /* 233 */ - { 0x2e0623a8, 0x1006 }, /* 234 */ - { 0x2e0623ac, 0xa03c }, /* 235 */ - { 0x2e0623b0, 0x4c000e }, /* 236 */ - { 0x2e0623b4, 0x3030098 }, /* 237 */ - { 0x2e0623b8, 0x258103 }, /* 238 */ - { 0x2e0623bc, 0x17702 }, /* 239 */ - { 0x2e0623c0, 0x5 }, /* 240 */ - { 0x2e0623c4, 0x61 }, /* 241 */ - { 0x2e0623c8, 0xe }, /* 242 */ - { 0x2e0623cc, 0xce3f }, /* 243 */ - { 0x2e0623d0, 0x80e70 }, /* 244 */ - { 0x2e0623d4, 0x5 }, /* 245 */ - { 0x2e0623d8, 0x210 }, /* 246 */ - { 0x2e0623dc, 0x4c }, /* 247 */ - { 0x2e0623e0, 0x19c7d }, /* 248 */ - { 0x2e0623e4, 0x101cdf }, /* 249 */ - { 0x2e0623e8, 0x5 }, /* 250 */ - { 0x2e0623ec, 0x420 }, /* 251 */ - { 0x2e0623f0, 0x1000098 }, /* 252 */ - { 0x2e0623f4, 0x310040 }, /* 253 */ - { 0x2e0623f8, 0x10002 }, /* 254 */ - { 0x2e0623fc, 0x1080040 }, /* 255 */ - { 0x2e062400, 0x10008 }, /* 256 */ - { 0x2e062404, 0x2100040 }, /* 257 */ - { 0x2e062408, 0x310 }, /* 258 */ - { 0x2e06240c, 0x1b000e }, /* 259 */ - { 0x2e062410, 0x1010101 }, /* 260 */ - { 0x2e062414, 0x2020101 }, /* 261 */ - { 0x2e062418, 0x8080404 }, /* 262 */ - { 0x2e06241c, 0x5508 }, /* 263 */ - { 0x2e062420, 0x83c5a00 }, /* 264 */ - { 0x2e062424, 0x55 }, /* 265 */ - { 0x2e062428, 0x55083c5a }, /* 266 */ - { 0x2e06242c, 0x5a000000 }, /* 267 */ - { 0x2e062430, 0x55083c }, /* 268 */ - { 0x2e062434, 0x3c5a0000 }, /* 269 */ - { 0x2e062438, 0xf0e0d0c }, /* 270 */ - { 0x2e06243c, 0xb0a0908 }, /* 271 */ - { 0x2e062440, 0x7060504 }, /* 272 */ - { 0x2e062444, 0x3020100 }, /* 273 */ - { 0x2e06244c, 0x2020101 }, /* 275 */ - { 0x2e062450, 0x8080404 }, /* 276 */ - { 0x2e062454, 0x44300004 }, /* 277 */ - { 0x2e062458, 0x4041919 }, /* 278 */ - { 0x2e06245c, 0x19443000 }, /* 279 */ - { 0x2e062460, 0x9140419 }, /* 280 */ - { 0x2e062464, 0x19194430 }, /* 281 */ - { 0x2e062468, 0x30000404 }, /* 282 */ - { 0x2e06246c, 0x4191944 }, /* 283 */ - { 0x2e062470, 0x44300004 }, /* 284 */ - { 0x2e062474, 0x14041919 }, /* 285 */ - { 0x2e062478, 0x19443009 }, /* 286 */ - { 0x2e06247c, 0x40419 }, /* 287 */ - { 0x2e062480, 0x19194430 }, /* 288 */ - { 0x2e062484, 0x30000404 }, /* 289 */ - { 0x2e062488, 0x4191944 }, /* 290 */ - { 0x2e06248c, 0x44300914 }, /* 291 */ - { 0x2e062490, 0x44041919 }, /* 292 */ - { 0x2e062494, 0x19443000 }, /* 293 */ - { 0x2e062498, 0x40419 }, /* 294 */ - { 0x2e06249c, 0x19194430 }, /* 295 */ - { 0x2e0624a0, 0x30091404 }, /* 296 */ - { 0x2e0624a4, 0x4191944 }, /* 297 */ -}; - -/** PHY_F1 settings **/ -struct dram_cfg_param ddr_phy_f1_cfg[] = { - { 0x2e064000, 0x4f0 }, /* 0 */ - { 0x2e064008, 0x1030200 }, /* 2 */ - { 0x2e064014, 0x3000000 }, /* 5 */ - { 0x2e064018, 0x1000001 }, /* 6 */ - { 0x2e06401c, 0x3000400 }, /* 7 */ - { 0x2e064020, 0x1 }, /* 8 */ - { 0x2e064024, 0x1 }, /* 9 */ - { 0x2e064030, 0x10000 }, /* 12 */ - { 0x2e064038, 0xc00004 }, /* 14 */ - { 0x2e06403c, 0xcc0008 }, /* 15 */ - { 0x2e064040, 0x660601 }, /* 16 */ - { 0x2e064044, 0x3 }, /* 17 */ - { 0x2e06404c, 0x1 }, /* 19 */ - { 0x2e064050, 0xaaaa }, /* 20 */ - { 0x2e064054, 0x5555 }, /* 21 */ - { 0x2e064058, 0xb5b5 }, /* 22 */ - { 0x2e06405c, 0x4a4a }, /* 23 */ - { 0x2e064060, 0x5656 }, /* 24 */ - { 0x2e064064, 0xa9a9 }, /* 25 */ - { 0x2e064068, 0xb7b7 }, /* 26 */ - { 0x2e06406c, 0x4848 }, /* 27 */ - { 0x2e064078, 0x8000000 }, /* 30 */ - { 0x2e06407c, 0x4010008 }, /* 31 */ - { 0x2e064080, 0x408 }, /* 32 */ - { 0x2e064084, 0x3102000 }, /* 33 */ - { 0x2e064088, 0xc0020 }, /* 34 */ - { 0x2e06408c, 0x10000 }, /* 35 */ - { 0x2e064090, 0x55555555 }, /* 36 */ - { 0x2e064094, 0xaaaaaaaa }, /* 37 */ - { 0x2e064098, 0x55555555 }, /* 38 */ - { 0x2e06409c, 0xaaaaaaaa }, /* 39 */ - { 0x2e0640a0, 0x5555 }, /* 40 */ - { 0x2e0640a4, 0x1000100 }, /* 41 */ - { 0x2e0640a8, 0x800180 }, /* 42 */ - { 0x2e0640ac, 0x1 }, /* 43 */ - { 0x2e064100, 0x4 }, /* 64 */ - { 0x2e06411c, 0x41f07ff }, /* 71 */ - { 0x2e064120, 0x1 }, /* 72 */ - { 0x2e064124, 0x1cc0800 }, /* 73 */ - { 0x2e064128, 0x3003cc08 }, /* 74 */ - { 0x2e06412c, 0x2000014e }, /* 75 */ - { 0x2e064130, 0x7ff0200 }, /* 76 */ - { 0x2e064134, 0x301 }, /* 77 */ - { 0x2e064140, 0x30000 }, /* 80 */ - { 0x2e064154, 0x2000000 }, /* 85 */ - { 0x2e064158, 0x51515042 }, /* 86 */ - { 0x2e06415c, 0x31c06000 }, /* 87 */ - { 0x2e064160, 0x6bf000a }, /* 88 */ - { 0x2e064164, 0xc0c000 }, /* 89 */ - { 0x2e064168, 0x1000000 }, /* 90 */ - { 0x2e06416c, 0x10001000 }, /* 91 */ - { 0x2e064170, 0xc043242 }, /* 92 */ - { 0x2e064174, 0xf0c1201 }, /* 93 */ - { 0x2e064178, 0x1000140 }, /* 94 */ - { 0x2e06417c, 0xc000120 }, /* 95 */ - { 0x2e064180, 0x143 }, /* 96 */ - { 0x2e064184, 0x1000203 }, /* 97 */ - { 0x2e064188, 0x56417032 }, /* 98 */ - { 0x2e06418c, 0x8 }, /* 99 */ - { 0x2e064190, 0x2c302c3 }, /* 100 */ - { 0x2e064194, 0x2c302c3 }, /* 101 */ - { 0x2e064198, 0x2c302c3 }, /* 102 */ - { 0x2e06419c, 0x2c302c3 }, /* 103 */ - { 0x2e0641a0, 0x2c3 }, /* 104 */ - { 0x2e0641a4, 0x8000 }, /* 105 */ - { 0x2e0641a8, 0x800080 }, /* 106 */ - { 0x2e0641ac, 0x800080 }, /* 107 */ - { 0x2e0641b0, 0x800080 }, /* 108 */ - { 0x2e0641b4, 0x800080 }, /* 109 */ - { 0x2e0641b8, 0x800080 }, /* 110 */ - { 0x2e0641bc, 0x800080 }, /* 111 */ - { 0x2e0641c0, 0x800080 }, /* 112 */ - { 0x2e0641c4, 0x800080 }, /* 113 */ - { 0x2e0641c8, 0x6b0080 }, /* 114 */ - { 0x2e0641cc, 0x1a00001 }, /* 115 */ - { 0x2e0641d4, 0x10000 }, /* 117 */ - { 0x2e0641d8, 0x80200 }, /* 118 */ - { 0x2e064400, 0x4f0 }, /* 256 */ - { 0x2e064408, 0x1030200 }, /* 258 */ - { 0x2e064414, 0x3000000 }, /* 261 */ - { 0x2e064418, 0x1000001 }, /* 262 */ - { 0x2e06441c, 0x3000400 }, /* 263 */ - { 0x2e064420, 0x1 }, /* 264 */ - { 0x2e064424, 0x1 }, /* 265 */ - { 0x2e064430, 0x10000 }, /* 268 */ - { 0x2e064438, 0xc00004 }, /* 270 */ - { 0x2e06443c, 0xcc0008 }, /* 271 */ - { 0x2e064440, 0x660601 }, /* 272 */ - { 0x2e064444, 0x3 }, /* 273 */ - { 0x2e06444c, 0x1 }, /* 275 */ - { 0x2e064450, 0xaaaa }, /* 276 */ - { 0x2e064454, 0x5555 }, /* 277 */ - { 0x2e064458, 0xb5b5 }, /* 278 */ - { 0x2e06445c, 0x4a4a }, /* 279 */ - { 0x2e064460, 0x5656 }, /* 280 */ - { 0x2e064464, 0xa9a9 }, /* 281 */ - { 0x2e064468, 0xb7b7 }, /* 282 */ - { 0x2e06446c, 0x4848 }, /* 283 */ - { 0x2e064478, 0x8000000 }, /* 286 */ - { 0x2e06447c, 0x4010008 }, /* 287 */ - { 0x2e064480, 0x408 }, /* 288 */ - { 0x2e064484, 0x3102000 }, /* 289 */ - { 0x2e064488, 0xc0020 }, /* 290 */ - { 0x2e06448c, 0x10000 }, /* 291 */ - { 0x2e064490, 0x55555555 }, /* 292 */ - { 0x2e064494, 0xaaaaaaaa }, /* 293 */ - { 0x2e064498, 0x55555555 }, /* 294 */ - { 0x2e06449c, 0xaaaaaaaa }, /* 295 */ - { 0x2e0644a0, 0x5555 }, /* 296 */ - { 0x2e0644a4, 0x1000100 }, /* 297 */ - { 0x2e0644a8, 0x800180 }, /* 298 */ - { 0x2e064500, 0x4 }, /* 320 */ - { 0x2e06451c, 0x41f07ff }, /* 327 */ - { 0x2e064520, 0x1 }, /* 328 */ - { 0x2e064524, 0x1cc0800 }, /* 329 */ - { 0x2e064528, 0x3003cc08 }, /* 330 */ - { 0x2e06452c, 0x2000014e }, /* 331 */ - { 0x2e064530, 0x7ff0200 }, /* 332 */ - { 0x2e064534, 0x301 }, /* 333 */ - { 0x2e064540, 0x30000 }, /* 336 */ - { 0x2e064554, 0x2000000 }, /* 341 */ - { 0x2e064558, 0x51515042 }, /* 342 */ - { 0x2e06455c, 0x31c06000 }, /* 343 */ - { 0x2e064560, 0x6bf000a }, /* 344 */ - { 0x2e064564, 0xc0c000 }, /* 345 */ - { 0x2e064568, 0x1000000 }, /* 346 */ - { 0x2e06456c, 0x10001000 }, /* 347 */ - { 0x2e064570, 0xc043242 }, /* 348 */ - { 0x2e064574, 0xf0c1201 }, /* 349 */ - { 0x2e064578, 0x1000140 }, /* 350 */ - { 0x2e06457c, 0xc000120 }, /* 351 */ - { 0x2e064580, 0x143 }, /* 352 */ - { 0x2e064584, 0x1000203 }, /* 353 */ - { 0x2e064588, 0x30217465 }, /* 354 */ - { 0x2e06458c, 0x8 }, /* 355 */ - { 0x2e064590, 0x2c302c3 }, /* 356 */ - { 0x2e064594, 0x2c302c3 }, /* 357 */ - { 0x2e064598, 0x2c302c3 }, /* 358 */ - { 0x2e06459c, 0x2c302c3 }, /* 359 */ - { 0x2e0645a0, 0x2c3 }, /* 360 */ - { 0x2e0645a4, 0x8000 }, /* 361 */ - { 0x2e0645a8, 0x800080 }, /* 362 */ - { 0x2e0645ac, 0x800080 }, /* 363 */ - { 0x2e0645b0, 0x800080 }, /* 364 */ - { 0x2e0645b4, 0x800080 }, /* 365 */ - { 0x2e0645b8, 0x800080 }, /* 366 */ - { 0x2e0645bc, 0x800080 }, /* 367 */ - { 0x2e0645c0, 0x800080 }, /* 368 */ - { 0x2e0645c4, 0x800080 }, /* 369 */ - { 0x2e0645c8, 0x6b0080 }, /* 370 */ - { 0x2e0645cc, 0x1a00001 }, /* 371 */ - { 0x2e0645d4, 0x10000 }, /* 373 */ - { 0x2e0645d8, 0x80200 }, /* 374 */ - { 0x2e064800, 0x4f0 }, /* 512 */ - { 0x2e064808, 0x1030200 }, /* 514 */ - { 0x2e064814, 0x3000000 }, /* 517 */ - { 0x2e064818, 0x1000001 }, /* 518 */ - { 0x2e06481c, 0x3000400 }, /* 519 */ - { 0x2e064820, 0x1 }, /* 520 */ - { 0x2e064824, 0x1 }, /* 521 */ - { 0x2e064830, 0x10000 }, /* 524 */ - { 0x2e064838, 0xc00004 }, /* 526 */ - { 0x2e06483c, 0xcc0008 }, /* 527 */ - { 0x2e064840, 0x660601 }, /* 528 */ - { 0x2e064844, 0x3 }, /* 529 */ - { 0x2e06484c, 0x1 }, /* 531 */ - { 0x2e064850, 0xaaaa }, /* 532 */ - { 0x2e064854, 0x5555 }, /* 533 */ - { 0x2e064858, 0xb5b5 }, /* 534 */ - { 0x2e06485c, 0x4a4a }, /* 535 */ - { 0x2e064860, 0x5656 }, /* 536 */ - { 0x2e064864, 0xa9a9 }, /* 537 */ - { 0x2e064868, 0xb7b7 }, /* 538 */ - { 0x2e06486c, 0x4848 }, /* 539 */ - { 0x2e064878, 0x8000000 }, /* 542 */ - { 0x2e06487c, 0x4010008 }, /* 543 */ - { 0x2e064880, 0x408 }, /* 544 */ - { 0x2e064884, 0x3102000 }, /* 545 */ - { 0x2e064888, 0xc0020 }, /* 546 */ - { 0x2e06488c, 0x10000 }, /* 547 */ - { 0x2e064890, 0x55555555 }, /* 548 */ - { 0x2e064894, 0xaaaaaaaa }, /* 549 */ - { 0x2e064898, 0x55555555 }, /* 550 */ - { 0x2e06489c, 0xaaaaaaaa }, /* 551 */ - { 0x2e0648a0, 0x5555 }, /* 552 */ - { 0x2e0648a4, 0x1000100 }, /* 553 */ - { 0x2e0648a8, 0x800180 }, /* 554 */ - { 0x2e0648ac, 0x1 }, /* 555 */ - { 0x2e064900, 0x4 }, /* 576 */ - { 0x2e06491c, 0x41f07ff }, /* 583 */ - { 0x2e064920, 0x1 }, /* 584 */ - { 0x2e064924, 0x1cc0800 }, /* 585 */ - { 0x2e064928, 0x3003cc08 }, /* 586 */ - { 0x2e06492c, 0x2000014e }, /* 587 */ - { 0x2e064930, 0x7ff0200 }, /* 588 */ - { 0x2e064934, 0x301 }, /* 589 */ - { 0x2e064940, 0x30000 }, /* 592 */ - { 0x2e064954, 0x2000000 }, /* 597 */ - { 0x2e064958, 0x51515042 }, /* 598 */ - { 0x2e06495c, 0x31c06000 }, /* 599 */ - { 0x2e064960, 0x6bf000a }, /* 600 */ - { 0x2e064964, 0xc0c000 }, /* 601 */ - { 0x2e064968, 0x1000000 }, /* 602 */ - { 0x2e06496c, 0x10001000 }, /* 603 */ - { 0x2e064970, 0xc043242 }, /* 604 */ - { 0x2e064974, 0xf0c1201 }, /* 605 */ - { 0x2e064978, 0x1000140 }, /* 606 */ - { 0x2e06497c, 0xc000120 }, /* 607 */ - { 0x2e064980, 0x143 }, /* 608 */ - { 0x2e064984, 0x1000203 }, /* 609 */ - { 0x2e064988, 0x75436012 }, /* 610 */ - { 0x2e06498c, 0x8 }, /* 611 */ - { 0x2e064990, 0x2c302c3 }, /* 612 */ - { 0x2e064994, 0x2c302c3 }, /* 613 */ - { 0x2e064998, 0x2c302c3 }, /* 614 */ - { 0x2e06499c, 0x2c302c3 }, /* 615 */ - { 0x2e0649a0, 0x2c3 }, /* 616 */ - { 0x2e0649a4, 0x8000 }, /* 617 */ - { 0x2e0649a8, 0x800080 }, /* 618 */ - { 0x2e0649ac, 0x800080 }, /* 619 */ - { 0x2e0649b0, 0x800080 }, /* 620 */ - { 0x2e0649b4, 0x800080 }, /* 621 */ - { 0x2e0649b8, 0x800080 }, /* 622 */ - { 0x2e0649bc, 0x800080 }, /* 623 */ - { 0x2e0649c0, 0x800080 }, /* 624 */ - { 0x2e0649c4, 0x800080 }, /* 625 */ - { 0x2e0649c8, 0x6b0080 }, /* 626 */ - { 0x2e0649cc, 0x1a00001 }, /* 627 */ - { 0x2e0649d4, 0x10000 }, /* 629 */ - { 0x2e0649d8, 0x80200 }, /* 630 */ - { 0x2e064c00, 0x4f0 }, /* 768 */ - { 0x2e064c08, 0x1030200 }, /* 770 */ - { 0x2e064c14, 0x3000000 }, /* 773 */ - { 0x2e064c18, 0x1000001 }, /* 774 */ - { 0x2e064c1c, 0x3000400 }, /* 775 */ - { 0x2e064c20, 0x1 }, /* 776 */ - { 0x2e064c24, 0x1 }, /* 777 */ - { 0x2e064c30, 0x10000 }, /* 780 */ - { 0x2e064c38, 0xc00004 }, /* 782 */ - { 0x2e064c3c, 0xcc0008 }, /* 783 */ - { 0x2e064c40, 0x660601 }, /* 784 */ - { 0x2e064c44, 0x3 }, /* 785 */ - { 0x2e064c4c, 0x1 }, /* 787 */ - { 0x2e064c50, 0xaaaa }, /* 788 */ - { 0x2e064c54, 0x5555 }, /* 789 */ - { 0x2e064c58, 0xb5b5 }, /* 790 */ - { 0x2e064c5c, 0x4a4a }, /* 791 */ - { 0x2e064c60, 0x5656 }, /* 792 */ - { 0x2e064c64, 0xa9a9 }, /* 793 */ - { 0x2e064c68, 0xb7b7 }, /* 794 */ - { 0x2e064c6c, 0x4848 }, /* 795 */ - { 0x2e064c78, 0x8000000 }, /* 798 */ - { 0x2e064c7c, 0x4010008 }, /* 799 */ - { 0x2e064c80, 0x408 }, /* 800 */ - { 0x2e064c84, 0x3102000 }, /* 801 */ - { 0x2e064c88, 0xc0020 }, /* 802 */ - { 0x2e064c8c, 0x10000 }, /* 803 */ - { 0x2e064c90, 0x55555555 }, /* 804 */ - { 0x2e064c94, 0xaaaaaaaa }, /* 805 */ - { 0x2e064c98, 0x55555555 }, /* 806 */ - { 0x2e064c9c, 0xaaaaaaaa }, /* 807 */ - { 0x2e064ca0, 0x5555 }, /* 808 */ - { 0x2e064ca4, 0x1000100 }, /* 809 */ - { 0x2e064ca8, 0x800180 }, /* 810 */ - { 0x2e064d00, 0x4 }, /* 832 */ - { 0x2e064d1c, 0x41f07ff }, /* 839 */ - { 0x2e064d20, 0x1 }, /* 840 */ - { 0x2e064d24, 0x1cc0800 }, /* 841 */ - { 0x2e064d28, 0x3003cc08 }, /* 842 */ - { 0x2e064d2c, 0x2000014e }, /* 843 */ - { 0x2e064d30, 0x7ff0200 }, /* 844 */ - { 0x2e064d34, 0x301 }, /* 845 */ - { 0x2e064d40, 0x30000 }, /* 848 */ - { 0x2e064d54, 0x2000000 }, /* 853 */ - { 0x2e064d58, 0x51515042 }, /* 854 */ - { 0x2e064d5c, 0x31c06000 }, /* 855 */ - { 0x2e064d60, 0x6bf000a }, /* 856 */ - { 0x2e064d64, 0xc0c000 }, /* 857 */ - { 0x2e064d68, 0x1000000 }, /* 858 */ - { 0x2e064d6c, 0x10001000 }, /* 859 */ - { 0x2e064d70, 0xc043242 }, /* 860 */ - { 0x2e064d74, 0xf0c1201 }, /* 861 */ - { 0x2e064d78, 0x1000140 }, /* 862 */ - { 0x2e064d7c, 0xc000120 }, /* 863 */ - { 0x2e064d80, 0x143 }, /* 864 */ - { 0x2e064d84, 0x1000203 }, /* 865 */ - { 0x2e064d88, 0x32017465 }, /* 866 */ - { 0x2e064d8c, 0x8 }, /* 867 */ - { 0x2e064d90, 0x2c302c3 }, /* 868 */ - { 0x2e064d94, 0x2c302c3 }, /* 869 */ - { 0x2e064d98, 0x2c302c3 }, /* 870 */ - { 0x2e064d9c, 0x2c302c3 }, /* 871 */ - { 0x2e064da0, 0x2c3 }, /* 872 */ - { 0x2e064da4, 0x8000 }, /* 873 */ - { 0x2e064da8, 0x800080 }, /* 874 */ - { 0x2e064dac, 0x800080 }, /* 875 */ - { 0x2e064db0, 0x800080 }, /* 876 */ - { 0x2e064db4, 0x800080 }, /* 877 */ - { 0x2e064db8, 0x800080 }, /* 878 */ - { 0x2e064dbc, 0x800080 }, /* 879 */ - { 0x2e064dc0, 0x800080 }, /* 880 */ - { 0x2e064dc4, 0x800080 }, /* 881 */ - { 0x2e064dc8, 0x6b0080 }, /* 882 */ - { 0x2e064dcc, 0x1a00001 }, /* 883 */ - { 0x2e064dd4, 0x10000 }, /* 885 */ - { 0x2e064dd8, 0x80200 }, /* 886 */ - { 0x2e065014, 0x100 }, /* 1029 */ - { 0x2e065018, 0x201 }, /* 1030 */ - { 0x2e06502c, 0x400000 }, /* 1035 */ - { 0x2e065030, 0x80 }, /* 1036 */ - { 0x2e065034, 0xdcba98 }, /* 1037 */ - { 0x2e065038, 0x3000000 }, /* 1038 */ - { 0x2e06504c, 0x2a }, /* 1043 */ - { 0x2e065050, 0x15 }, /* 1044 */ - { 0x2e065054, 0x15 }, /* 1045 */ - { 0x2e065058, 0x2a }, /* 1046 */ - { 0x2e06505c, 0x33 }, /* 1047 */ - { 0x2e065060, 0xc }, /* 1048 */ - { 0x2e065064, 0xc }, /* 1049 */ - { 0x2e065068, 0x33 }, /* 1050 */ - { 0x2e06506c, 0x543210 }, /* 1051 */ - { 0x2e065070, 0x3f0000 }, /* 1052 */ - { 0x2e065074, 0xf013f }, /* 1053 */ - { 0x2e065078, 0xf }, /* 1054 */ - { 0x2e06507c, 0x3cc }, /* 1055 */ - { 0x2e065080, 0x30000 }, /* 1056 */ - { 0x2e065084, 0x300 }, /* 1057 */ - { 0x2e065088, 0x300 }, /* 1058 */ - { 0x2e06508c, 0x300 }, /* 1059 */ - { 0x2e065090, 0x300 }, /* 1060 */ - { 0x2e065094, 0x300 }, /* 1061 */ - { 0x2e065098, 0x42080010 }, /* 1062 */ - { 0x2e06509c, 0x332 }, /* 1063 */ - { 0x2e0650a0, 0x2 }, /* 1064 */ - { 0x2e065414, 0x100 }, /* 1285 */ - { 0x2e065418, 0x201 }, /* 1286 */ - { 0x2e06542c, 0x400000 }, /* 1291 */ - { 0x2e065430, 0x80 }, /* 1292 */ - { 0x2e065434, 0xdcba98 }, /* 1293 */ - { 0x2e065438, 0x3000000 }, /* 1294 */ - { 0x2e06544c, 0x2a }, /* 1299 */ - { 0x2e065450, 0x15 }, /* 1300 */ - { 0x2e065454, 0x15 }, /* 1301 */ - { 0x2e065458, 0x2a }, /* 1302 */ - { 0x2e06545c, 0x33 }, /* 1303 */ - { 0x2e065460, 0xc }, /* 1304 */ - { 0x2e065464, 0xc }, /* 1305 */ - { 0x2e065468, 0x33 }, /* 1306 */ - { 0x2e06546c, 0x543210 }, /* 1307 */ - { 0x2e065470, 0x3f0000 }, /* 1308 */ - { 0x2e065474, 0xf013f }, /* 1309 */ - { 0x2e065478, 0xf }, /* 1310 */ - { 0x2e06547c, 0x3cc }, /* 1311 */ - { 0x2e065480, 0x30000 }, /* 1312 */ - { 0x2e065484, 0x300 }, /* 1313 */ - { 0x2e065488, 0x300 }, /* 1314 */ - { 0x2e06548c, 0x300 }, /* 1315 */ - { 0x2e065490, 0x300 }, /* 1316 */ - { 0x2e065494, 0x300 }, /* 1317 */ - { 0x2e065498, 0x42080010 }, /* 1318 */ - { 0x2e06549c, 0x332 }, /* 1319 */ - { 0x2e0654a0, 0x2 }, /* 1320 */ - { 0x2e065804, 0x100 }, /* 1537 */ - { 0x2e065814, 0x50000 }, /* 1541 */ - { 0x2e065818, 0x4000100 }, /* 1542 */ - { 0x2e06581c, 0x55 }, /* 1543 */ - { 0x2e06582c, 0xf0001 }, /* 1547 */ - { 0x2e065830, 0x280040 }, /* 1548 */ - { 0x2e065834, 0x5002 }, /* 1549 */ - { 0x2e065838, 0x10101 }, /* 1550 */ - { 0x2e065840, 0x90e0000 }, /* 1552 */ - { 0x2e065844, 0x101010f }, /* 1553 */ - { 0x2e065848, 0x10f0004 }, /* 1554 */ - { 0x2e065854, 0x64 }, /* 1557 */ - { 0x2e06585c, 0x1000000 }, /* 1559 */ - { 0x2e065860, 0x8040201 }, /* 1560 */ - { 0x2e065864, 0x2010201 }, /* 1561 */ - { 0x2e065868, 0xf0f0f }, /* 1562 */ - { 0x2e06586c, 0x241342 }, /* 1563 */ - { 0x2e065874, 0x1020000 }, /* 1565 */ - { 0x2e065878, 0x701 }, /* 1566 */ - { 0x2e06587c, 0x54 }, /* 1567 */ - { 0x2e065880, 0x4102000 }, /* 1568 */ - { 0x2e065884, 0x24410 }, /* 1569 */ - { 0x2e065888, 0x4410 }, /* 1570 */ - { 0x2e06588c, 0x4410 }, /* 1571 */ - { 0x2e065890, 0x4410 }, /* 1572 */ - { 0x2e065894, 0x4410 }, /* 1573 */ - { 0x2e065898, 0x4410 }, /* 1574 */ - { 0x2e06589c, 0x4410 }, /* 1575 */ - { 0x2e0658a0, 0x4410 }, /* 1576 */ - { 0x2e0658a4, 0x4410 }, /* 1577 */ - { 0x2e0658b0, 0x60000 }, /* 1580 */ - { 0x2e0658b8, 0x66 }, /* 1582 */ - { 0x2e0658bc, 0x10000 }, /* 1583 */ - { 0x2e0658c0, 0x8 }, /* 1584 */ - { 0x2e0658d8, 0x3000000 }, /* 1590 */ - { 0x2e0658e8, 0x4102006 }, /* 1594 */ - { 0x2e0658ec, 0x41020 }, /* 1595 */ - { 0x2e0658f0, 0x1c98c98 }, /* 1596 */ - { 0x2e0658f4, 0x3f400000 }, /* 1597 */ - { 0x2e0658f8, 0x3f3f1f3f }, /* 1598 */ - { 0x2e0658fc, 0x1f }, /* 1599 */ - { 0x2e06590c, 0x1 }, /* 1603 */ - { 0x2e06591c, 0x1 }, /* 1607 */ - { 0x2e065920, 0x76543210 }, /* 1608 */ - { 0x2e065924, 0x10198 }, /* 1609 */ - { 0x2e065934, 0x40700 }, /* 1613 */ - { 0x2e06594c, 0x2 }, /* 1619 */ - { 0x2e065958, 0xf3c3 }, /* 1622 */ - { 0x2e065964, 0x11542 }, /* 1625 */ - { 0x2e065968, 0x30209bf }, /* 1626 */ - { 0x2e06596c, 0x30000 }, /* 1627 */ - { 0x2e065970, 0x3000300 }, /* 1628 */ - { 0x2e065974, 0x3000300 }, /* 1629 */ - { 0x2e065978, 0x3000300 }, /* 1630 */ - { 0x2e06597c, 0x3000300 }, /* 1631 */ - { 0x2e065980, 0x300 }, /* 1632 */ - { 0x2e065984, 0x300 }, /* 1633 */ - { 0x2e065988, 0x300 }, /* 1634 */ - { 0x2e06598c, 0x337cc }, /* 1635 */ - { 0x2e065990, 0x8 }, /* 1636 */ - { 0x2e065994, 0x1b7 }, /* 1637 */ - { 0x2e06599c, 0x1b7 }, /* 1639 */ - { 0x2e0659a4, 0x1b700 }, /* 1641 */ - { 0x2e0659a8, 0x1980000 }, /* 1642 */ - { 0x2e0659ac, 0x1b7cc }, /* 1643 */ - { 0x2e0659b4, 0x1b700 }, /* 1645 */ - { 0x2e0659b8, 0x1980000 }, /* 1646 */ - { 0x2e0659bc, 0x1b700 }, /* 1647 */ - { 0x2e0659c0, 0x1980000 }, /* 1648 */ - { 0x2e0659c4, 0x1b700 }, /* 1649 */ - { 0x2e0659c8, 0x1980000 }, /* 1650 */ - { 0x2e0659cc, 0x1b700 }, /* 1651 */ - { 0x2e0659d0, 0x1980000 }, /* 1652 */ - { 0x2e0659d4, 0x20040003 }, /* 1653 */ -}; - -/** PHY_F2 settings **/ -struct dram_cfg_param ddr_phy_f2_cfg[] = { -}; - -/* ddr timing config params */ -struct dram_timing_info2 dram_timing = { - .ctl_cfg = ddr_ctl_cfg, - .ctl_cfg_num = ARRAY_SIZE(ddr_ctl_cfg), - .pi_cfg = ddr_pi_cfg, - .pi_cfg_num = ARRAY_SIZE(ddr_pi_cfg), - .phy_f1_cfg = ddr_phy_f1_cfg, - .phy_f1_cfg_num = ARRAY_SIZE(ddr_phy_f1_cfg), - .phy_f2_cfg = ddr_phy_f2_cfg, - .phy_f2_cfg_num = ARRAY_SIZE(ddr_phy_f2_cfg), - .fsp_table = { 96, 528 }, -}; diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c deleted file mode 100644 index fe637077928..00000000000 --- a/board/freescale/imx8ulp_evk/spl.c +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2021 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void spl_dram_init(void) -{ - /* Reboot in dual boot setting no need to init ddr again */ - bool ddr_enable = pcc_clock_is_enable(5, LPDDR4_PCC5_SLOT); - - if (!ddr_enable) { - init_clk_ddr(); - ddr_init(&dram_timing); - } else { - /* reinit pfd/pfddiv and lpavnic except pll4*/ - cgc2_pll4_init(false); - } -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_BOOTROM; -} - -int power_init_board(void) -{ - if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) { - /* Set buck3 to 0.9v LD */ - upower_pmic_i2c_write(0x22, 0x18); - } else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) { - /* Set buck3 to 1.0v ND */ - upower_pmic_i2c_write(0x22, 0x20); - } else { - /* Set buck3 to 1.1v OD */ - upower_pmic_i2c_write(0x22, 0x28); - } - - return 0; -} - -void display_ele_fw_version(void) -{ - u32 fw_version, sha1, res; - int ret; - - ret = ele_get_fw_version(&fw_version, &sha1, &res); - if (ret) { - printf("ele get firmware version failed %d, 0x%x\n", ret, res); - } else { - printf("ELE firmware version %u.%u.%u-%x", - (fw_version & (0x00ff0000)) >> 16, - (fw_version & (0x0000fff0)) >> 4, - (fw_version & (0x0000000f)), sha1); - ((fw_version & (0x80000000)) >> 31) == 1 ? puts("-dirty\n") : puts("\n"); - } -} - -void spl_board_init(void) -{ - u32 res; - int ret; - - ret = imx8ulp_dm_post_init(); - if (ret) - return; - - board_early_init_f(); - - preloader_console_init(); - - puts("Normal Boot\n"); - - display_ele_fw_version(); - - /* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */ - - /* Load the lposc fuse to work around ROM issue. The fuse depends on S400 to read. */ - if (is_soc_rev(CHIP_REV_1_0)) - load_lposc_fuse(); - - upower_init(); - - power_init_board(); - - clock_init_late(); - - /* This must place after upower init, so access to MDA and MRC are valid */ - /* Init XRDC MDA */ - xrdc_init_mda(); - - /* Init XRDC MRC for VIDEO, DSP domains */ - xrdc_init_mrc(); - - xrdc_init_pdac_msc(); - - /* DDR initialization */ - spl_dram_init(); - - /* Call it after PS16 power up */ - set_lpav_qos(); - - /* Enable A35 access to the CAAM */ - ret = ele_release_caam(0x7, &res); - if (ret) - printf("ele release caam failed %d, 0x%x\n", ret, res); - - /* - * RNG start only available on the A1 soc revision. - * Check some JTAG register for the SoC revision. - */ - if (!is_soc_rev(CHIP_REV_1_0)) { - ret = ele_start_rng(); - if (ret) - printf("Fail to start RNG: %d\n", ret); - } -} - -void board_init_f(ulong dummy) -{ - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - timer_init(); - - arch_cpu_init(); - - board_init_r(NULL, 0); -} diff --git a/board/freescale/imx91_evk/Kconfig b/board/freescale/imx91_evk/Kconfig deleted file mode 100644 index caaa82b4af8..00000000000 --- a/board/freescale/imx91_evk/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -if TARGET_IMX91_11X11_EVK - -config SYS_BOARD - default "imx91_evk" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "imx91_evk" - -config IMX91_EVK_LPDDR4 - bool "Using LPDDR4 Timing and PMIC voltage" - default y - select IMX9_LPDDR4X - help - Select the LPDDR4 timing and 1.1V VDDQ - -endif diff --git a/board/freescale/imx91_evk/MAINTAINERS b/board/freescale/imx91_evk/MAINTAINERS deleted file mode 100644 index f7d39bfb0a3..00000000000 --- a/board/freescale/imx91_evk/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -i.MX91 11x11 EVK BOARD -M: Peng Fan -S: Maintained -F: board/freescale/imx91_evk/ -F: include/configs/imx91_evk.h -F: configs/imx91_11x11_evk_defconfig -F: configs/imx91_11x11_evk_inline_ecc_defconfig diff --git a/board/freescale/imx91_evk/Makefile b/board/freescale/imx91_evk/Makefile deleted file mode 100644 index a96228af959..00000000000 --- a/board/freescale/imx91_evk/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright 2024 NXP -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += imx91_evk.o - -ifdef CONFIG_XPL_BUILD -obj-y += spl.o -ifdef CONFIG_IMX9_DRAM_INLINE_ECC -obj-$(CONFIG_IMX91_EVK_LPDDR4) += lpddr4_timing_2400mts_ecc.o lpddr4_timing_1600mts_ecc.o -else -obj-$(CONFIG_IMX91_EVK_LPDDR4) += lpddr4_timing_2400mts.o lpddr4_timing_1600mts.o -endif -endif diff --git a/board/freescale/imx91_evk/imx91_evk.c b/board/freescale/imx91_evk/imx91_evk.c deleted file mode 100644 index fca2521081b..00000000000 --- a/board/freescale/imx91_evk/imx91_evk.c +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2024 NXP - */ - -#include -#include -#include - -int board_late_init(void) -{ -#ifdef CONFIG_ENV_IS_IN_MMC - board_late_mmc_env_init(); -#endif - - env_set("sec_boot", "no"); -#ifdef CONFIG_AHAB_BOOT - env_set("sec_boot", "yes"); -#endif - -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - env_set("board_name", "11X11_EVK"); - env_set("board_rev", "iMX93"); -#endif - return 0; -} diff --git a/board/freescale/imx91_evk/imx91_evk.env b/board/freescale/imx91_evk/imx91_evk.env deleted file mode 100644 index 6c10784cf61..00000000000 --- a/board/freescale/imx91_evk/imx91_evk.env +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ - -boot_targets=mmc0 mmc1 -boot_fit=no -bootm_size=0x10000000 -cntr_addr=0x98000000 -cntr_file=os_cntr_signed.bin -console=ttyLP0,115200 earlycon -fdt_addr_r=0x83000000 -fdt_addr=0x83000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE -image=Image -mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX -mmcpart=1 -mmcroot=/dev/mmcblk1p2 rootwait rw -mmcautodetect=yes -mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} -prepare_mcore=setenv mcore_clk clk-imx93.mcore_booted -loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} -loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} -auth_os=auth_cntr ${cntr_addr} -sec_boot=no -boot_os=booti ${loadaddr} - ${fdt_addr_r} -mmcboot= - echo Booting from mmc ...; - run mmcargs; - if test ${sec_boot} = yes; then - if run true; then - run boot_os; - else - echo ERR: failed to authenticate; - fi; - else - if run loadfdt; then - run boot_os; - else - echo WARN: Cannot load the DT; - fi; - fi; -netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs - ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp -netboot= - echo Booting from net ...; - run netargs; - if test ${ip_dyn} = yes; then - setenv get_cmd dhcp; - else - setenv get_cmd tftp; - fi; - if test ${sec_boot} = yes; then - ${get_cmd} ${cntr_addr} ${cntr_file}; - if true; then - run boot_os; - else - echo ERR: failed to authenticate; - fi; - else - ${get_cmd} ${loadaddr} ${image}; - if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then - run boot_os; - else - echo WARN: Cannot load the DT; - fi; - fi; -bsp_bootcmd= - echo Running BSP bootcmd ...; - mmc dev ${mmcdev}; - if mmc rescan; then - if run loadbootscript; then - run bootscript; - else - if test ${sec_boot} = yes; then - if run loadcntr; then - run mmcboot; - else - run netboot; - fi; - else - if run loadimage; then - run mmcboot; - else - run netboot; - fi; - fi; - fi; - fi; -scriptaddr=0x83500000 diff --git a/board/freescale/imx91_evk/lpddr4_timing_1600mts.c b/board/freescale/imx91_evk/lpddr4_timing_1600mts.c deleted file mode 100644 index 45e19daa028..00000000000 --- a/board/freescale/imx91_evk/lpddr4_timing_1600mts.c +++ /dev/null @@ -1,1995 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright 2024 NXP - * - * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3. - * DDR PHY FW2022.01 - */ - -#include -#include - -/* Initialize DDRC registers */ -static struct dram_cfg_param ddr_ddrc_cfg[] = { - {0x4e300110, 0x44100001}, - {0x4e300000, 0x8000ff}, - {0x4e300008, 0x0}, - {0x4e300080, 0x80000512}, - {0x4e300084, 0x0}, - {0x4e300114, 0x1002}, - {0x4e300260, 0x80}, - {0x4e300f04, 0x80}, - {0x4e300800, 0x43b30002}, - {0x4e300804, 0x1f1f1f1f}, - {0x4e301000, 0x0}, - {0x4e301240, 0x0}, - {0x4e301244, 0x0}, - {0x4e301248, 0x0}, - {0x4e30124c, 0x0}, - {0x4e301250, 0x0}, - {0x4e301254, 0x0}, - {0x4e301258, 0x0}, - {0x4e30125c, 0x0}, -}; - -/* dram fsp cfg */ -static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { - { - { - {0x4e300100, 0x02121100}, - {0x4e300104, 0xF866000C}, - {0x4e300108, 0xF2FA8088}, - {0x4e30010C, 0x0061E1A0}, - {0x4e300124, 0x0C340000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30700000}, - {0x4e300170, 0x8A0A0508}, - {0x4e300250, 0x00000011}, - {0x4e300254, 0x00900090}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - {0x4e300300, 0x0F220F09}, - {0x4e300304, 0x00901008}, - {0x4e300308, 0x063C061A}, - }, - { - {0x01, 0xA4}, - {0x02, 0x52}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x00091000}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0x81820A48}, - {0x4e30010C, 0x00310110}, - {0x4e300124, 0x061A0000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30100000}, - {0x4e300170, 0x89090408}, - {0x4e300250, 0x00000009}, - {0x4e300254, 0x00440044}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0x94}, - {0x02, 0x9}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x00061000}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0x6E62FA48}, - {0x4e30010C, 0x0031010D}, - {0x4e300124, 0x04C50000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30000000}, - {0x4e300170, 0x89090408}, - {0x4e300250, 0x00000007}, - {0x4e300254, 0x00340034}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0x94}, - {0x02, 0x9}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 1, - }, -}; - -/* PHY Initialize Configuration */ -static struct dram_cfg_param ddr_ddrphy_cfg[] = { - {0x100a0, 0x4}, - {0x100a1, 0x5}, - {0x100a2, 0x6}, - {0x100a3, 0x7}, - {0x100a4, 0x0}, - {0x100a5, 0x1}, - {0x100a6, 0x2}, - {0x100a7, 0x3}, - {0x110a0, 0x3}, - {0x110a1, 0x2}, - {0x110a2, 0x0}, - {0x110a3, 0x1}, - {0x110a4, 0x7}, - {0x110a5, 0x6}, - {0x110a6, 0x4}, - {0x110a7, 0x5}, - {0x1005f, 0x1ff}, - {0x1015f, 0x1ff}, - {0x1105f, 0x1ff}, - {0x1115f, 0x1ff}, - {0x11005f, 0x1ff}, - {0x11015f, 0x1ff}, - {0x11105f, 0x1ff}, - {0x11115f, 0x1ff}, - {0x21005f, 0x1ff}, - {0x21015f, 0x1ff}, - {0x21105f, 0x1ff}, - {0x21115f, 0x1ff}, - {0x55, 0x1ff}, - {0x1055, 0x1ff}, - {0x2055, 0x1ff}, - {0x200c5, 0xb}, - {0x1200c5, 0x3}, - {0x2200c5, 0x7}, - {0x2002e, 0x1}, - {0x12002e, 0x1}, - {0x22002e, 0x2}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x1e3}, - {0x2003a, 0x2}, - {0x2007d, 0x212}, - {0x2007c, 0x61}, - {0x120024, 0x1e3}, - {0x2003a, 0x2}, - {0x12007d, 0x212}, - {0x12007c, 0x61}, - {0x220024, 0x1e3}, - {0x2003a, 0x2}, - {0x22007d, 0x212}, - {0x22007c, 0x61}, - {0x20056, 0x3}, - {0x120056, 0x3}, - {0x220056, 0x3}, - {0x1004d, 0x600}, - {0x1014d, 0x600}, - {0x1104d, 0x600}, - {0x1114d, 0x600}, - {0x11004d, 0x600}, - {0x11014d, 0x600}, - {0x11104d, 0x600}, - {0x11114d, 0x600}, - {0x21004d, 0x600}, - {0x21014d, 0x600}, - {0x21104d, 0x600}, - {0x21114d, 0x600}, - {0x10049, 0xe3f}, - {0x10149, 0xe3f}, - {0x11049, 0xe3f}, - {0x11149, 0xe3f}, - {0x110049, 0xe3f}, - {0x110149, 0xe3f}, - {0x111049, 0xe3f}, - {0x111149, 0xe3f}, - {0x210049, 0xe3f}, - {0x210149, 0xe3f}, - {0x211049, 0xe3f}, - {0x211149, 0xe3f}, - {0x43, 0x7f}, - {0x1043, 0x7f}, - {0x2043, 0x7f}, - {0x20018, 0x1}, - {0x20075, 0x4}, - {0x20050, 0x11}, - {0x2009b, 0x2}, - {0x20008, 0x190}, - {0x120008, 0xc8}, - {0x220008, 0x9c}, - {0x20088, 0x9}, - {0x200b2, 0x10c}, - {0x10043, 0x5a1}, - {0x10143, 0x5a1}, - {0x11043, 0x5a1}, - {0x11143, 0x5a1}, - {0x1200b2, 0x10c}, - {0x110043, 0x5a1}, - {0x110143, 0x5a1}, - {0x111043, 0x5a1}, - {0x111143, 0x5a1}, - {0x2200b2, 0x10c}, - {0x210043, 0x5a1}, - {0x210143, 0x5a1}, - {0x211043, 0x5a1}, - {0x211143, 0x5a1}, - {0x200fa, 0x2}, - {0x1200fa, 0x2}, - {0x2200fa, 0x2}, - {0x20019, 0x1}, - {0x120019, 0x1}, - {0x220019, 0x1}, - {0x200f0, 0x600}, - {0x200f1, 0x0}, - {0x200f2, 0x4444}, - {0x200f3, 0x8888}, - {0x200f4, 0x5655}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0xf000}, - {0x1004a, 0x500}, - {0x1104a, 0x500}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0x20021, 0x0}, - {0x200c7, 0x21}, - {0x1200c7, 0x41}, - {0x200ca, 0x24}, - {0x1200ca, 0x24}, -}; - -/* PHY trained csr */ -static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - {0x1005f, 0x0}, - {0x1015f, 0x0}, - {0x1105f, 0x0}, - {0x1115f, 0x0}, - {0x11005f, 0x0}, - {0x11015f, 0x0}, - {0x11105f, 0x0}, - {0x11115f, 0x0}, - {0x21005f, 0x0}, - {0x21015f, 0x0}, - {0x21105f, 0x0}, - {0x21115f, 0x0}, - {0x55, 0x0}, - {0x1055, 0x0}, - {0x2055, 0x0}, - {0x200c5, 0x0}, - {0x1200c5, 0x0}, - {0x2200c5, 0x0}, - {0x2002e, 0x0}, - {0x12002e, 0x0}, - {0x22002e, 0x0}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x0}, - {0x2003a, 0x0}, - {0x2007d, 0x0}, - {0x2007c, 0x0}, - {0x120024, 0x0}, - {0x12007d, 0x0}, - {0x12007c, 0x0}, - {0x220024, 0x0}, - {0x22007d, 0x0}, - {0x22007c, 0x0}, - {0x20056, 0x0}, - {0x120056, 0x0}, - {0x220056, 0x0}, - {0x1004d, 0x0}, - {0x1014d, 0x0}, - {0x1104d, 0x0}, - {0x1114d, 0x0}, - {0x11004d, 0x0}, - {0x11014d, 0x0}, - {0x11104d, 0x0}, - {0x11114d, 0x0}, - {0x21004d, 0x0}, - {0x21014d, 0x0}, - {0x21104d, 0x0}, - {0x21114d, 0x0}, - {0x10049, 0x0}, - {0x10149, 0x0}, - {0x11049, 0x0}, - {0x11149, 0x0}, - {0x110049, 0x0}, - {0x110149, 0x0}, - {0x111049, 0x0}, - {0x111149, 0x0}, - {0x210049, 0x0}, - {0x210149, 0x0}, - {0x211049, 0x0}, - {0x211149, 0x0}, - {0x43, 0x0}, - {0x1043, 0x0}, - {0x2043, 0x0}, - {0x20018, 0x0}, - {0x20075, 0x0}, - {0x20050, 0x0}, - {0x2009b, 0x0}, - {0x20008, 0x0}, - {0x120008, 0x0}, - {0x220008, 0x0}, - {0x20088, 0x0}, - {0x200b2, 0x0}, - {0x10043, 0x0}, - {0x10143, 0x0}, - {0x11043, 0x0}, - {0x11143, 0x0}, - {0x1200b2, 0x0}, - {0x110043, 0x0}, - {0x110143, 0x0}, - {0x111043, 0x0}, - {0x111143, 0x0}, - {0x2200b2, 0x0}, - {0x210043, 0x0}, - {0x210143, 0x0}, - {0x211043, 0x0}, - {0x211143, 0x0}, - {0x200fa, 0x0}, - {0x1200fa, 0x0}, - {0x2200fa, 0x0}, - {0x20019, 0x0}, - {0x120019, 0x0}, - {0x220019, 0x0}, - {0x200f0, 0x0}, - {0x200f1, 0x0}, - {0x200f2, 0x0}, - {0x200f3, 0x0}, - {0x200f4, 0x0}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0x0}, - {0x1004a, 0x0}, - {0x1104a, 0x0}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0xd0000, 0x0}, - {0x90000, 0x0}, - {0x90001, 0x0}, - {0x90002, 0x0}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x0}, - {0x90029, 0x0}, - {0x9002a, 0x0}, - {0x9002b, 0x0}, - {0x9002c, 0x0}, - {0x9002d, 0x0}, - {0x9002e, 0x0}, - {0x9002f, 0x0}, - {0x90030, 0x0}, - {0x90031, 0x0}, - {0x90032, 0x0}, - {0x90033, 0x0}, - {0x90034, 0x0}, - {0x90035, 0x0}, - {0x90036, 0x0}, - {0x90037, 0x0}, - {0x90038, 0x0}, - {0x90039, 0x0}, - {0x9003a, 0x0}, - {0x9003b, 0x0}, - {0x9003c, 0x0}, - {0x9003d, 0x0}, - {0x9003e, 0x0}, - {0x9003f, 0x0}, - {0x90040, 0x0}, - {0x90041, 0x0}, - {0x90042, 0x0}, - {0x90043, 0x0}, - {0x90044, 0x0}, - {0x90045, 0x0}, - {0x90046, 0x0}, - {0x90047, 0x0}, - {0x90048, 0x0}, - {0x90049, 0x0}, - {0x9004a, 0x0}, - {0x9004b, 0x0}, - {0x9004c, 0x0}, - {0x9004d, 0x0}, - {0x9004e, 0x0}, - {0x9004f, 0x0}, - {0x90050, 0x0}, - {0x90051, 0x0}, - {0x90052, 0x0}, - {0x90053, 0x0}, - {0x90054, 0x0}, - {0x90055, 0x0}, - {0x90056, 0x0}, - {0x90057, 0x0}, - {0x90058, 0x0}, - {0x90059, 0x0}, - {0x9005a, 0x0}, - {0x9005b, 0x0}, - {0x9005c, 0x0}, - {0x9005d, 0x0}, - {0x9005e, 0x0}, - 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{0x115c1, 0x0}, - {0x116c0, 0x0}, - {0x116c1, 0x0}, - {0x117c0, 0x0}, - {0x117c1, 0x0}, - {0x118c0, 0x0}, - {0x118c1, 0x0}, - {0x110ae, 0x0}, - {0x110af, 0x0}, - {0x90201, 0x0}, - {0x90202, 0x0}, - {0x90203, 0x0}, - {0x90205, 0x0}, - {0x90206, 0x0}, - {0x90207, 0x0}, - {0x90208, 0x0}, - {0x20020, 0x0}, - {0x100080, 0x0}, - {0x101080, 0x0}, - {0x102080, 0x0}, - {0x110020, 0x0}, - {0x110080, 0x0}, - {0x110081, 0x0}, - {0x1100d0, 0x0}, - {0x1100d1, 0x0}, - {0x11008c, 0x0}, - {0x11008d, 0x0}, - {0x110180, 0x0}, - {0x110181, 0x0}, - {0x1101d0, 0x0}, - {0x1101d1, 0x0}, - {0x11018c, 0x0}, - {0x11018d, 0x0}, - {0x1100c0, 0x0}, - {0x1100c1, 0x0}, - {0x1101c0, 0x0}, - {0x1101c1, 0x0}, - {0x1102c0, 0x0}, - {0x1102c1, 0x0}, - {0x1103c0, 0x0}, - {0x1103c1, 0x0}, - {0x1104c0, 0x0}, - {0x1104c1, 0x0}, - {0x1105c0, 0x0}, - {0x1105c1, 0x0}, - {0x1106c0, 0x0}, - {0x1106c1, 0x0}, - {0x1107c0, 0x0}, - {0x1107c1, 0x0}, - {0x1108c0, 0x0}, - {0x1108c1, 0x0}, - {0x1100ae, 0x0}, - {0x1100af, 0x0}, - {0x111020, 0x0}, - {0x111080, 0x0}, - {0x111081, 0x0}, - {0x1110d0, 0x0}, - {0x1110d1, 0x0}, - {0x11108c, 0x0}, - {0x11108d, 0x0}, - {0x111180, 0x0}, - {0x111181, 0x0}, - {0x1111d0, 0x0}, - {0x1111d1, 0x0}, - {0x11118c, 0x0}, - {0x11118d, 0x0}, - {0x1110c0, 0x0}, - {0x1110c1, 0x0}, - {0x1111c0, 0x0}, - {0x1111c1, 0x0}, - {0x1112c0, 0x0}, - {0x1112c1, 0x0}, - {0x1113c0, 0x0}, - {0x1113c1, 0x0}, - {0x1114c0, 0x0}, - {0x1114c1, 0x0}, - {0x1115c0, 0x0}, - {0x1115c1, 0x0}, - {0x1116c0, 0x0}, - {0x1116c1, 0x0}, - {0x1117c0, 0x0}, - {0x1117c1, 0x0}, - {0x1118c0, 0x0}, - {0x1118c1, 0x0}, - {0x1110ae, 0x0}, - {0x1110af, 0x0}, - {0x190201, 0x0}, - {0x190202, 0x0}, - {0x190203, 0x0}, - {0x190205, 0x0}, - {0x190206, 0x0}, - {0x190207, 0x0}, - {0x190208, 0x0}, - {0x120020, 0x0}, - {0x200080, 0x0}, - {0x201080, 0x0}, - {0x202080, 0x0}, - {0x210020, 0x0}, - {0x210080, 0x0}, - {0x210081, 0x0}, - {0x2100d0, 0x0}, - {0x2100d1, 0x0}, - {0x21008c, 0x0}, - {0x21008d, 0x0}, - {0x210180, 0x0}, - {0x210181, 0x0}, - {0x2101d0, 0x0}, - {0x2101d1, 0x0}, - {0x21018c, 0x0}, - {0x21018d, 0x0}, - {0x2100c0, 0x0}, - {0x2100c1, 0x0}, - {0x2101c0, 0x0}, - {0x2101c1, 0x0}, - {0x2102c0, 0x0}, - {0x2102c1, 0x0}, - {0x2103c0, 0x0}, - {0x2103c1, 0x0}, - {0x2104c0, 0x0}, - {0x2104c1, 0x0}, - {0x2105c0, 0x0}, - {0x2105c1, 0x0}, - {0x2106c0, 0x0}, - {0x2106c1, 0x0}, - {0x2107c0, 0x0}, - {0x2107c1, 0x0}, - {0x2108c0, 0x0}, - {0x2108c1, 0x0}, - {0x2100ae, 0x0}, - {0x2100af, 0x0}, - {0x211020, 0x0}, - {0x211080, 0x0}, - {0x211081, 0x0}, - {0x2110d0, 0x0}, - {0x2110d1, 0x0}, - {0x21108c, 0x0}, - {0x21108d, 0x0}, - {0x211180, 0x0}, - {0x211181, 0x0}, - {0x2111d0, 0x0}, - {0x2111d1, 0x0}, - {0x21118c, 0x0}, - {0x21118d, 0x0}, - {0x2110c0, 0x0}, - {0x2110c1, 0x0}, - {0x2111c0, 0x0}, - {0x2111c1, 0x0}, - {0x2112c0, 0x0}, - {0x2112c1, 0x0}, - {0x2113c0, 0x0}, - {0x2113c1, 0x0}, - {0x2114c0, 0x0}, - {0x2114c1, 0x0}, - {0x2115c0, 0x0}, - {0x2115c1, 0x0}, - {0x2116c0, 0x0}, - {0x2116c1, 0x0}, - {0x2117c0, 0x0}, - {0x2117c1, 0x0}, - {0x2118c0, 0x0}, - {0x2118c1, 0x0}, - {0x2110ae, 0x0}, - {0x2110af, 0x0}, - {0x290201, 0x0}, - {0x290202, 0x0}, - {0x290203, 0x0}, - {0x290205, 0x0}, - {0x290206, 0x0}, - {0x290207, 0x0}, - {0x290208, 0x0}, - {0x220020, 0x0}, - {0x20077, 0x0}, - {0x20072, 0x0}, - {0x20073, 0x0}, - {0x400c0, 0x0}, - {0x10040, 0x0}, - {0x10140, 0x0}, - {0x10240, 0x0}, - {0x10340, 0x0}, - {0x10440, 0x0}, - {0x10540, 0x0}, - {0x10640, 0x0}, - {0x10740, 0x0}, - {0x10840, 0x0}, - {0x11040, 0x0}, - {0x11140, 0x0}, - {0x11240, 0x0}, - {0x11340, 0x0}, - {0x11440, 0x0}, - {0x11540, 0x0}, - {0x11640, 0x0}, - {0x11740, 0x0}, - {0x11840, 0x0}, -}; - -/* P0 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0x640}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x131f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x52a4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x52a4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xa400}, - {0x54033, 0x3352}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xa400}, - {0x54039, 0x3352}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P1 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp1_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x1}, - {0x54003, 0x320}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x994}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x994}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0x9400}, - {0x54033, 0x3309}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0x9400}, - {0x54039, 0x3309}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P2 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp2_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x102}, - {0x54003, 0x270}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x994}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4800}, - {0x5401e, 0x4}, - {0x5401f, 0x994}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4800}, - {0x54024, 0x4}, - {0x54032, 0x9400}, - {0x54033, 0x3309}, - {0x54034, 0x4600}, - {0x54035, 0x11}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0x9400}, - {0x54039, 0x3309}, - {0x5403a, 0x4600}, - {0x5403b, 0x11}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P0 2D message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0x640}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x61}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54010, 0x2080}, - {0x54012, 0x110}, - {0x54019, 0x52a4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x52a4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xa400}, - {0x54033, 0x3352}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xa400}, - {0x54039, 0x3352}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* DRAM PHY init engine image */ -static struct dram_cfg_param ddr_phy_pie[] = { - {0xd0000, 0x0}, - {0x90000, 0x10}, - {0x90001, 0x400}, - {0x90002, 0x10e}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x8}, - {0x90029, 0xb}, - {0x9002a, 0x480}, - {0x9002b, 0x109}, - {0x9002c, 0x8}, - {0x9002d, 0x448}, - {0x9002e, 0x139}, - {0x9002f, 0x8}, - {0x90030, 0x478}, - {0x90031, 0x109}, - {0x90032, 0x0}, - {0x90033, 0xe8}, - {0x90034, 0x109}, - {0x90035, 0x2}, - {0x90036, 0x10}, - {0x90037, 0x139}, - {0x90038, 0xb}, - {0x90039, 0x7c0}, - {0x9003a, 0x139}, - {0x9003b, 0x44}, - {0x9003c, 0x633}, - {0x9003d, 0x159}, - {0x9003e, 0x14f}, - {0x9003f, 0x630}, - {0x90040, 0x159}, - {0x90041, 0x47}, - {0x90042, 0x633}, - {0x90043, 0x149}, - {0x90044, 0x4f}, - {0x90045, 0x633}, - {0x90046, 0x179}, - {0x90047, 0x8}, - {0x90048, 0xe0}, - {0x90049, 0x109}, - {0x9004a, 0x0}, - {0x9004b, 0x7c8}, - {0x9004c, 0x109}, - {0x9004d, 0x0}, - {0x9004e, 0x1}, - {0x9004f, 0x8}, - {0x90050, 0x30}, - {0x90051, 0x65a}, - {0x90052, 0x9}, - {0x90053, 0x0}, - {0x90054, 0x45a}, - {0x90055, 0x9}, - {0x90056, 0x0}, - {0x90057, 0x448}, - {0x90058, 0x109}, - {0x90059, 0x40}, - {0x9005a, 0x633}, - {0x9005b, 0x179}, - {0x9005c, 0x1}, - {0x9005d, 0x618}, - {0x9005e, 0x109}, - {0x9005f, 0x40c0}, - {0x90060, 0x633}, - {0x90061, 0x149}, - {0x90062, 0x8}, - {0x90063, 0x4}, - {0x90064, 0x48}, - {0x90065, 0x4040}, - {0x90066, 0x633}, - {0x90067, 0x149}, - {0x90068, 0x0}, - {0x90069, 0x4}, - {0x9006a, 0x48}, - {0x9006b, 0x40}, - {0x9006c, 0x633}, - {0x9006d, 0x149}, - {0x9006e, 0x0}, - {0x9006f, 0x658}, - {0x90070, 0x109}, - {0x90071, 0x10}, - {0x90072, 0x4}, - {0x90073, 0x18}, - {0x90074, 0x0}, - {0x90075, 0x4}, - {0x90076, 0x78}, - {0x90077, 0x549}, - {0x90078, 0x633}, - {0x90079, 0x159}, - {0x9007a, 0xd49}, - {0x9007b, 0x633}, - {0x9007c, 0x159}, - {0x9007d, 0x94a}, - {0x9007e, 0x633}, - {0x9007f, 0x159}, - {0x90080, 0x441}, - {0x90081, 0x633}, - {0x90082, 0x149}, - {0x90083, 0x42}, - {0x90084, 0x633}, - {0x90085, 0x149}, - {0x90086, 0x1}, - {0x90087, 0x633}, - {0x90088, 0x149}, - {0x90089, 0x0}, - {0x9008a, 0xe0}, - {0x9008b, 0x109}, - {0x9008c, 0xa}, - {0x9008d, 0x10}, - {0x9008e, 0x109}, - {0x9008f, 0x9}, - {0x90090, 0x3c0}, - {0x90091, 0x149}, - {0x90092, 0x9}, - {0x90093, 0x3c0}, - {0x90094, 0x159}, - {0x90095, 0x18}, - {0x90096, 0x10}, - {0x90097, 0x109}, - {0x90098, 0x0}, - {0x90099, 0x3c0}, - {0x9009a, 0x109}, - {0x9009b, 0x18}, - {0x9009c, 0x4}, - {0x9009d, 0x48}, - {0x9009e, 0x18}, - {0x9009f, 0x4}, - {0x900a0, 0x58}, - {0x900a1, 0xb}, - {0x900a2, 0x10}, - {0x900a3, 0x109}, - {0x900a4, 0x1}, - {0x900a5, 0x10}, - {0x900a6, 0x109}, - {0x900a7, 0x5}, - {0x900a8, 0x7c0}, - {0x900a9, 0x109}, - {0x40000, 0x811}, - {0x40020, 0x880}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x4008}, - {0x40021, 0x83}, - {0x40041, 0x4f}, - {0x40061, 0x0}, - {0x40002, 0x4040}, - {0x40022, 0x83}, - {0x40042, 0x51}, - {0x40062, 0x0}, - {0x40003, 0x811}, - {0x40023, 0x880}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x720}, - {0x40024, 0xf}, - {0x40044, 0x1740}, - {0x40064, 0x0}, - {0x40005, 0x16}, - {0x40025, 0x83}, - {0x40045, 0x4b}, - {0x40065, 0x0}, - {0x40006, 0x716}, - {0x40026, 0xf}, - {0x40046, 0x2001}, - {0x40066, 0x0}, - {0x40007, 0x716}, - {0x40027, 0xf}, - {0x40047, 0x2800}, - {0x40067, 0x0}, - {0x40008, 0x716}, - {0x40028, 0xf}, - {0x40048, 0xf00}, - {0x40068, 0x0}, - {0x40009, 0x720}, - {0x40029, 0xf}, - {0x40049, 0x1400}, - {0x40069, 0x0}, - {0x4000a, 0xe08}, - {0x4002a, 0xc15}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x625}, - {0x4002b, 0x15}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x4028}, - {0x4002c, 0x80}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0xe08}, - {0x4002d, 0xc1a}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x625}, - {0x4002e, 0x1a}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x4040}, - {0x4002f, 0x80}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x2604}, - {0x40030, 0x15}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x708}, - {0x40031, 0x5}, - {0x40051, 0x0}, - {0x40071, 0x2002}, - {0x40012, 0x8}, - {0x40032, 0x80}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x2604}, - {0x40033, 0x1a}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x708}, - {0x40034, 0xa}, - {0x40054, 0x0}, - {0x40074, 0x2002}, - {0x40015, 0x4040}, - {0x40035, 0x80}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x60a}, - {0x40036, 0x15}, - {0x40056, 0x1200}, - {0x40076, 0x0}, - {0x40017, 0x61a}, - {0x40037, 0x15}, - {0x40057, 0x1300}, - {0x40077, 0x0}, - {0x40018, 0x60a}, - {0x40038, 0x1a}, - {0x40058, 0x1200}, - {0x40078, 0x0}, - {0x40019, 0x642}, - {0x40039, 0x1a}, - {0x40059, 0x1300}, - {0x40079, 0x0}, - {0x4001a, 0x4808}, - {0x4003a, 0x880}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x790}, - {0x900ac, 0x11a}, - {0x900ad, 0x8}, - {0x900ae, 0x7aa}, - {0x900af, 0x2a}, - {0x900b0, 0x10}, - {0x900b1, 0x7b2}, - {0x900b2, 0x2a}, - {0x900b3, 0x0}, - {0x900b4, 0x7c8}, - {0x900b5, 0x109}, - {0x900b6, 0x10}, - {0x900b7, 0x10}, - {0x900b8, 0x109}, - {0x900b9, 0x10}, - {0x900ba, 0x2a8}, - {0x900bb, 0x129}, - {0x900bc, 0x8}, - {0x900bd, 0x370}, - {0x900be, 0x129}, - {0x900bf, 0xa}, - {0x900c0, 0x3c8}, - {0x900c1, 0x1a9}, - {0x900c2, 0xc}, - {0x900c3, 0x408}, - {0x900c4, 0x199}, - {0x900c5, 0x14}, - {0x900c6, 0x790}, - {0x900c7, 0x11a}, - {0x900c8, 0x8}, - {0x900c9, 0x4}, - {0x900ca, 0x18}, - {0x900cb, 0xe}, - {0x900cc, 0x408}, - {0x900cd, 0x199}, - {0x900ce, 0x8}, - {0x900cf, 0x8568}, - {0x900d0, 0x108}, - {0x900d1, 0x18}, - {0x900d2, 0x790}, - {0x900d3, 0x16a}, - {0x900d4, 0x8}, - {0x900d5, 0x1d8}, - {0x900d6, 0x169}, - {0x900d7, 0x10}, - {0x900d8, 0x8558}, - {0x900d9, 0x168}, - {0x900da, 0x1ff8}, - {0x900db, 0x85a8}, - {0x900dc, 0x1e8}, - {0x900dd, 0x50}, - {0x900de, 0x798}, - {0x900df, 0x16a}, - {0x900e0, 0x60}, - {0x900e1, 0x7a0}, - {0x900e2, 0x16a}, - {0x900e3, 0x8}, - {0x900e4, 0x8310}, - {0x900e5, 0x168}, - {0x900e6, 0x8}, - {0x900e7, 0xa310}, - {0x900e8, 0x168}, - {0x900e9, 0xa}, - {0x900ea, 0x408}, - {0x900eb, 0x169}, - {0x900ec, 0x6e}, - {0x900ed, 0x0}, - {0x900ee, 0x68}, - {0x900ef, 0x0}, - {0x900f0, 0x408}, - {0x900f1, 0x169}, - {0x900f2, 0x0}, - {0x900f3, 0x8310}, - {0x900f4, 0x168}, - {0x900f5, 0x0}, - {0x900f6, 0xa310}, - {0x900f7, 0x168}, - {0x900f8, 0x1ff8}, - {0x900f9, 0x85a8}, - {0x900fa, 0x1e8}, - {0x900fb, 0x68}, - {0x900fc, 0x798}, - {0x900fd, 0x16a}, - {0x900fe, 0x78}, - {0x900ff, 0x7a0}, - {0x90100, 0x16a}, - {0x90101, 0x68}, - {0x90102, 0x790}, - {0x90103, 0x16a}, - {0x90104, 0x8}, - {0x90105, 0x8b10}, - {0x90106, 0x168}, - {0x90107, 0x8}, - {0x90108, 0xab10}, - {0x90109, 0x168}, - {0x9010a, 0xa}, - {0x9010b, 0x408}, - {0x9010c, 0x169}, - {0x9010d, 0x58}, - {0x9010e, 0x0}, - {0x9010f, 0x68}, - {0x90110, 0x0}, - {0x90111, 0x408}, - {0x90112, 0x169}, - {0x90113, 0x0}, - {0x90114, 0x8b10}, - {0x90115, 0x168}, - {0x90116, 0x1}, - {0x90117, 0xab10}, - {0x90118, 0x168}, - {0x90119, 0x0}, - {0x9011a, 0x1d8}, - {0x9011b, 0x169}, - {0x9011c, 0x80}, - {0x9011d, 0x790}, - {0x9011e, 0x16a}, - {0x9011f, 0x18}, - {0x90120, 0x7aa}, - {0x90121, 0x6a}, - {0x90122, 0xa}, - {0x90123, 0x0}, - {0x90124, 0x1e9}, - {0x90125, 0x8}, - {0x90126, 0x8080}, - {0x90127, 0x108}, - {0x90128, 0xf}, - {0x90129, 0x408}, - {0x9012a, 0x169}, - {0x9012b, 0xc}, - {0x9012c, 0x0}, - {0x9012d, 0x68}, - {0x9012e, 0x9}, - {0x9012f, 0x0}, - {0x90130, 0x1a9}, - {0x90131, 0x0}, - {0x90132, 0x408}, - {0x90133, 0x169}, - {0x90134, 0x0}, - {0x90135, 0x8080}, - {0x90136, 0x108}, - {0x90137, 0x8}, - {0x90138, 0x7aa}, - {0x90139, 0x6a}, - {0x9013a, 0x0}, - {0x9013b, 0x8568}, - {0x9013c, 0x108}, - {0x9013d, 0xb7}, - {0x9013e, 0x790}, - {0x9013f, 0x16a}, - {0x90140, 0x1f}, - {0x90141, 0x0}, - {0x90142, 0x68}, - {0x90143, 0x8}, - {0x90144, 0x8558}, - {0x90145, 0x168}, - {0x90146, 0xf}, - {0x90147, 0x408}, - {0x90148, 0x169}, - {0x90149, 0xd}, - {0x9014a, 0x0}, - {0x9014b, 0x68}, - {0x9014c, 0x0}, - {0x9014d, 0x408}, - {0x9014e, 0x169}, - {0x9014f, 0x0}, - {0x90150, 0x8558}, - {0x90151, 0x168}, - {0x90152, 0x8}, - {0x90153, 0x3c8}, - {0x90154, 0x1a9}, - {0x90155, 0x3}, - {0x90156, 0x370}, - {0x90157, 0x129}, - {0x90158, 0x20}, - {0x90159, 0x2aa}, - {0x9015a, 0x9}, - {0x9015b, 0x8}, - {0x9015c, 0xe8}, - {0x9015d, 0x109}, - {0x9015e, 0x0}, - {0x9015f, 0x8140}, - {0x90160, 0x10c}, - {0x90161, 0x10}, - {0x90162, 0x8138}, - {0x90163, 0x104}, - {0x90164, 0x8}, - {0x90165, 0x448}, - {0x90166, 0x109}, - {0x90167, 0xf}, - {0x90168, 0x7c0}, - {0x90169, 0x109}, - {0x9016a, 0x0}, - {0x9016b, 0xe8}, - {0x9016c, 0x109}, - {0x9016d, 0x47}, - {0x9016e, 0x630}, - {0x9016f, 0x109}, - {0x90170, 0x8}, - {0x90171, 0x618}, - {0x90172, 0x109}, - {0x90173, 0x8}, - {0x90174, 0xe0}, - {0x90175, 0x109}, - {0x90176, 0x0}, - {0x90177, 0x7c8}, - {0x90178, 0x109}, - {0x90179, 0x8}, - {0x9017a, 0x8140}, - {0x9017b, 0x10c}, - {0x9017c, 0x0}, - {0x9017d, 0x478}, - {0x9017e, 0x109}, - {0x9017f, 0x0}, - {0x90180, 0x1}, - {0x90181, 0x8}, - {0x90182, 0x8}, - {0x90183, 0x4}, - {0x90184, 0x0}, - {0x90006, 0x8}, - {0x90007, 0x7c8}, - {0x90008, 0x109}, - {0x90009, 0x0}, - {0x9000a, 0x400}, - {0x9000b, 0x106}, - {0xd00e7, 0x400}, - {0x90017, 0x0}, - {0x9001f, 0x2b}, - {0x90026, 0x69}, - {0x400d0, 0x0}, - {0x400d1, 0x101}, - {0x400d2, 0x105}, - {0x400d3, 0x107}, - {0x400d4, 0x10f}, - {0x400d5, 0x202}, - {0x400d6, 0x20a}, - {0x400d7, 0x20b}, - {0x2003a, 0x2}, - {0x200be, 0x3}, - {0x2000b, 0x1c2}, - {0x2000c, 0x64}, - {0x2000d, 0x3e8}, - {0x2000e, 0x2c}, - {0x12000b, 0xe1}, - {0x12000c, 0x32}, - {0x12000d, 0x1f4}, - {0x12000e, 0x10}, - {0x22000b, 0xb0}, - {0x22000c, 0x27}, - {0x22000d, 0x186}, - {0x22000e, 0x10}, - {0x9000c, 0x0}, - {0x9000d, 0x173}, - {0x9000e, 0x60}, - {0x9000f, 0x6110}, - {0x90010, 0x2152}, - {0x90011, 0xdfbd}, - {0x90012, 0x2060}, - {0x90013, 0x6152}, - {0x20010, 0x5a}, - {0x20011, 0x3}, - {0x120010, 0x5a}, - {0x120011, 0x3}, - {0x40080, 0xe0}, - {0x40081, 0x12}, - {0x40082, 0xe0}, - {0x40083, 0x12}, - {0x40084, 0xe0}, - {0x40085, 0x12}, - {0x140080, 0xe0}, - {0x140081, 0x12}, - {0x140082, 0xe0}, - {0x140083, 0x12}, - {0x140084, 0xe0}, - {0x140085, 0x12}, - {0x240080, 0xe0}, - {0x240081, 0x12}, - {0x240082, 0xe0}, - {0x240083, 0x12}, - {0x240084, 0xe0}, - {0x240085, 0x12}, - {0x400fd, 0xf}, - {0x400f1, 0xe}, - {0x10011, 0x1}, - {0x10012, 0x1}, - {0x10013, 0x180}, - {0x10018, 0x1}, - {0x10002, 0x6209}, - {0x100b2, 0x1}, - {0x101b4, 0x1}, - {0x102b4, 0x1}, - {0x103b4, 0x1}, - {0x104b4, 0x1}, - {0x105b4, 0x1}, - {0x106b4, 0x1}, - {0x107b4, 0x1}, - {0x108b4, 0x1}, - {0x11011, 0x1}, - {0x11012, 0x1}, - {0x11013, 0x180}, - {0x11018, 0x1}, - {0x11002, 0x6209}, - {0x110b2, 0x1}, - {0x111b4, 0x1}, - {0x112b4, 0x1}, - {0x113b4, 0x1}, - {0x114b4, 0x1}, - {0x115b4, 0x1}, - {0x116b4, 0x1}, - {0x117b4, 0x1}, - {0x118b4, 0x1}, - {0x20089, 0x1}, - {0x20088, 0x19}, - {0xc0080, 0x0}, - {0xd0000, 0x1}, -}; - -static struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 1600mts 1D */ - .drate = 1600, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 800mts 1D */ - .drate = 800, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 625mts 1D */ - .drate = 625, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 1600mts 2D */ - .drate = 1600, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing_1600mts = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 1600, 800, 625, }, - .fsp_cfg = ddr_dram_fsp_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), -}; diff --git a/board/freescale/imx91_evk/lpddr4_timing_1600mts_ecc.c b/board/freescale/imx91_evk/lpddr4_timing_1600mts_ecc.c deleted file mode 100644 index 4594ab68aa0..00000000000 --- a/board/freescale/imx91_evk/lpddr4_timing_1600mts_ecc.c +++ /dev/null @@ -1,1995 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright 2024 NXP - * - * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3. - * DDR PHY FW2022.01 - */ - -#include -#include - -/* Initialize DDRC registers */ -static struct dram_cfg_param ddr_ddrc_cfg[] = { - {0x4e300110, 0x44100001}, - {0x4e300000, 0x8000ef}, - {0x4e300008, 0x0}, - {0x4e300080, 0x80000512}, - {0x4e300084, 0x0}, - {0x4e300114, 0x1012}, - {0x4e300260, 0x80}, - {0x4e300f04, 0x80}, - {0x4e300800, 0x43b30d00}, - {0x4e300804, 0x1f1f1f1f}, - {0x4e301000, 0xc0000000}, - {0x4e301240, 0x0}, - {0x4e301244, 0x0}, - {0x4e301248, 0x0}, - {0x4e30124c, 0x0}, - {0x4e301250, 0x0}, - {0x4e301254, 0x0}, - {0x4e301258, 0x0}, - {0x4e30125c, 0x0}, -}; - -/* dram fsp cfg */ -static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { - { - { - {0x4e300100, 0x02121100}, - {0x4e300104, 0xF866000C}, - {0x4e300108, 0xF2FA8088}, - {0x4e30010C, 0x0061E1A0}, - {0x4e300124, 0x0C340000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30700000}, - {0x4e300170, 0x8A0A0508}, - {0x4e300250, 0x00000011}, - {0x4e300254, 0x00900090}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - {0x4e300300, 0x0F220F09}, - {0x4e300304, 0x00901008}, - {0x4e300308, 0x063C061A}, - }, - { - {0x01, 0xA4}, - {0x02, 0x52}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x00091000}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0x81820A48}, - {0x4e30010C, 0x00310110}, - {0x4e300124, 0x061A0000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30100000}, - {0x4e300170, 0x89090408}, - {0x4e300250, 0x00000009}, - {0x4e300254, 0x00440044}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0x94}, - {0x02, 0x9}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x00061000}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0x6E62FA48}, - {0x4e30010C, 0x0031010D}, - {0x4e300124, 0x04C50000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30000000}, - {0x4e300170, 0x89090408}, - {0x4e300250, 0x00000007}, - {0x4e300254, 0x00340034}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0x94}, - {0x02, 0x9}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 1, - }, -}; - -/* PHY Initialize Configuration */ -static struct dram_cfg_param ddr_ddrphy_cfg[] = { - {0x100a0, 0x4}, - {0x100a1, 0x5}, - {0x100a2, 0x6}, - {0x100a3, 0x7}, - {0x100a4, 0x0}, - {0x100a5, 0x1}, - {0x100a6, 0x2}, - {0x100a7, 0x3}, - {0x110a0, 0x3}, - {0x110a1, 0x2}, - {0x110a2, 0x0}, - {0x110a3, 0x1}, - {0x110a4, 0x7}, - {0x110a5, 0x6}, - {0x110a6, 0x4}, - {0x110a7, 0x5}, - {0x1005f, 0x1ff}, - {0x1015f, 0x1ff}, - {0x1105f, 0x1ff}, - {0x1115f, 0x1ff}, - {0x11005f, 0x1ff}, - {0x11015f, 0x1ff}, - {0x11105f, 0x1ff}, - {0x11115f, 0x1ff}, - {0x21005f, 0x1ff}, - {0x21015f, 0x1ff}, - {0x21105f, 0x1ff}, - {0x21115f, 0x1ff}, - {0x55, 0x1ff}, - {0x1055, 0x1ff}, - {0x2055, 0x1ff}, - {0x200c5, 0xb}, - {0x1200c5, 0x3}, - {0x2200c5, 0x7}, - {0x2002e, 0x1}, - {0x12002e, 0x1}, - {0x22002e, 0x2}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x1e3}, - {0x2003a, 0x2}, - {0x2007d, 0x212}, - {0x2007c, 0x61}, - {0x120024, 0x1e3}, - {0x2003a, 0x2}, - {0x12007d, 0x212}, - {0x12007c, 0x61}, - {0x220024, 0x1e3}, - {0x2003a, 0x2}, - {0x22007d, 0x212}, - {0x22007c, 0x61}, - {0x20056, 0x3}, - {0x120056, 0x3}, - {0x220056, 0x3}, - {0x1004d, 0x600}, - {0x1014d, 0x600}, - {0x1104d, 0x600}, - {0x1114d, 0x600}, - {0x11004d, 0x600}, - {0x11014d, 0x600}, - {0x11104d, 0x600}, - {0x11114d, 0x600}, - {0x21004d, 0x600}, - {0x21014d, 0x600}, - {0x21104d, 0x600}, - {0x21114d, 0x600}, - {0x10049, 0xe3f}, - {0x10149, 0xe3f}, - {0x11049, 0xe3f}, - {0x11149, 0xe3f}, - {0x110049, 0xe3f}, - {0x110149, 0xe3f}, - {0x111049, 0xe3f}, - {0x111149, 0xe3f}, - {0x210049, 0xe3f}, - {0x210149, 0xe3f}, - {0x211049, 0xe3f}, - {0x211149, 0xe3f}, - {0x43, 0x7f}, - {0x1043, 0x7f}, - {0x2043, 0x7f}, - {0x20018, 0x1}, - {0x20075, 0x4}, - {0x20050, 0x11}, - {0x2009b, 0x2}, - {0x20008, 0x190}, - {0x120008, 0xc8}, - {0x220008, 0x9c}, - {0x20088, 0x9}, - {0x200b2, 0x10c}, - {0x10043, 0x5a1}, - {0x10143, 0x5a1}, - {0x11043, 0x5a1}, - {0x11143, 0x5a1}, - {0x1200b2, 0x10c}, - {0x110043, 0x5a1}, - {0x110143, 0x5a1}, - {0x111043, 0x5a1}, - {0x111143, 0x5a1}, - {0x2200b2, 0x10c}, - {0x210043, 0x5a1}, - {0x210143, 0x5a1}, - {0x211043, 0x5a1}, - {0x211143, 0x5a1}, - {0x200fa, 0x2}, - {0x1200fa, 0x2}, - {0x2200fa, 0x2}, - {0x20019, 0x1}, - {0x120019, 0x1}, - {0x220019, 0x1}, - {0x200f0, 0x600}, - {0x200f1, 0x0}, - {0x200f2, 0x4444}, - {0x200f3, 0x8888}, - {0x200f4, 0x5655}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0xf000}, - {0x1004a, 0x500}, - {0x1104a, 0x500}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0x20021, 0x0}, - {0x200c7, 0x21}, - {0x1200c7, 0x41}, - {0x200ca, 0x24}, - {0x1200ca, 0x24}, -}; - -/* PHY trained csr */ -static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - {0x1005f, 0x0}, - {0x1015f, 0x0}, - {0x1105f, 0x0}, - {0x1115f, 0x0}, - {0x11005f, 0x0}, - {0x11015f, 0x0}, - {0x11105f, 0x0}, - {0x11115f, 0x0}, - {0x21005f, 0x0}, - {0x21015f, 0x0}, - {0x21105f, 0x0}, - {0x21115f, 0x0}, - {0x55, 0x0}, - {0x1055, 0x0}, - {0x2055, 0x0}, - {0x200c5, 0x0}, - {0x1200c5, 0x0}, - {0x2200c5, 0x0}, - {0x2002e, 0x0}, - {0x12002e, 0x0}, - {0x22002e, 0x0}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x0}, - {0x2003a, 0x0}, - {0x2007d, 0x0}, - {0x2007c, 0x0}, - {0x120024, 0x0}, - {0x12007d, 0x0}, - {0x12007c, 0x0}, - {0x220024, 0x0}, - {0x22007d, 0x0}, - {0x22007c, 0x0}, - {0x20056, 0x0}, - {0x120056, 0x0}, - {0x220056, 0x0}, - {0x1004d, 0x0}, - {0x1014d, 0x0}, - {0x1104d, 0x0}, - {0x1114d, 0x0}, - {0x11004d, 0x0}, - {0x11014d, 0x0}, - {0x11104d, 0x0}, - {0x11114d, 0x0}, - {0x21004d, 0x0}, - {0x21014d, 0x0}, - {0x21104d, 0x0}, - {0x21114d, 0x0}, - {0x10049, 0x0}, - {0x10149, 0x0}, - {0x11049, 0x0}, - {0x11149, 0x0}, - {0x110049, 0x0}, - {0x110149, 0x0}, - {0x111049, 0x0}, - {0x111149, 0x0}, - {0x210049, 0x0}, - {0x210149, 0x0}, - {0x211049, 0x0}, - {0x211149, 0x0}, - {0x43, 0x0}, - {0x1043, 0x0}, - {0x2043, 0x0}, - {0x20018, 0x0}, - {0x20075, 0x0}, - {0x20050, 0x0}, - {0x2009b, 0x0}, - {0x20008, 0x0}, - {0x120008, 0x0}, - {0x220008, 0x0}, - {0x20088, 0x0}, - {0x200b2, 0x0}, - {0x10043, 0x0}, - {0x10143, 0x0}, - {0x11043, 0x0}, - {0x11143, 0x0}, - {0x1200b2, 0x0}, - {0x110043, 0x0}, - {0x110143, 0x0}, - {0x111043, 0x0}, - {0x111143, 0x0}, - {0x2200b2, 0x0}, - {0x210043, 0x0}, - {0x210143, 0x0}, - {0x211043, 0x0}, - {0x211143, 0x0}, - {0x200fa, 0x0}, - {0x1200fa, 0x0}, - {0x2200fa, 0x0}, - {0x20019, 0x0}, - {0x120019, 0x0}, - {0x220019, 0x0}, - {0x200f0, 0x0}, - {0x200f1, 0x0}, - {0x200f2, 0x0}, - {0x200f3, 0x0}, - {0x200f4, 0x0}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0x0}, - {0x1004a, 0x0}, - {0x1104a, 0x0}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0xd0000, 0x0}, - {0x90000, 0x0}, - {0x90001, 0x0}, - {0x90002, 0x0}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x0}, - {0x90029, 0x0}, - {0x9002a, 0x0}, - {0x9002b, 0x0}, - {0x9002c, 0x0}, - {0x9002d, 0x0}, - {0x9002e, 0x0}, - {0x9002f, 0x0}, - {0x90030, 0x0}, - {0x90031, 0x0}, - {0x90032, 0x0}, - {0x90033, 0x0}, - {0x90034, 0x0}, - {0x90035, 0x0}, - {0x90036, 0x0}, - {0x90037, 0x0}, - {0x90038, 0x0}, - {0x90039, 0x0}, - {0x9003a, 0x0}, - {0x9003b, 0x0}, - {0x9003c, 0x0}, - {0x9003d, 0x0}, - {0x9003e, 0x0}, - {0x9003f, 0x0}, - {0x90040, 0x0}, - {0x90041, 0x0}, - {0x90042, 0x0}, - {0x90043, 0x0}, - {0x90044, 0x0}, - {0x90045, 0x0}, - {0x90046, 0x0}, - {0x90047, 0x0}, - {0x90048, 0x0}, - {0x90049, 0x0}, - {0x9004a, 0x0}, - {0x9004b, 0x0}, - {0x9004c, 0x0}, - {0x9004d, 0x0}, - {0x9004e, 0x0}, - {0x9004f, 0x0}, - {0x90050, 0x0}, - {0x90051, 0x0}, - {0x90052, 0x0}, - {0x90053, 0x0}, - {0x90054, 0x0}, - {0x90055, 0x0}, - {0x90056, 0x0}, - {0x90057, 0x0}, - {0x90058, 0x0}, - {0x90059, 0x0}, - {0x9005a, 0x0}, - {0x9005b, 0x0}, - {0x9005c, 0x0}, - {0x9005d, 0x0}, - {0x9005e, 0x0}, - {0x9005f, 0x0}, - {0x90060, 0x0}, - {0x90061, 0x0}, - {0x90062, 0x0}, - {0x90063, 0x0}, - {0x90064, 0x0}, - {0x90065, 0x0}, - {0x90066, 0x0}, - {0x90067, 0x0}, - {0x90068, 0x0}, - {0x90069, 0x0}, - {0x9006a, 0x0}, - {0x9006b, 0x0}, - {0x9006c, 0x0}, - {0x9006d, 0x0}, - {0x9006e, 0x0}, - {0x9006f, 0x0}, - {0x90070, 0x0}, - {0x90071, 0x0}, - {0x90072, 0x0}, - {0x90073, 0x0}, - {0x90074, 0x0}, - {0x90075, 0x0}, - {0x90076, 0x0}, - {0x90077, 0x0}, - {0x90078, 0x0}, - {0x90079, 0x0}, - {0x9007a, 0x0}, - {0x9007b, 0x0}, - {0x9007c, 0x0}, - {0x9007d, 0x0}, - {0x9007e, 0x0}, - {0x9007f, 0x0}, - {0x90080, 0x0}, - {0x90081, 0x0}, - {0x90082, 0x0}, - {0x90083, 0x0}, - {0x90084, 0x0}, - {0x90085, 0x0}, - {0x90086, 0x0}, - {0x90087, 0x0}, - {0x90088, 0x0}, - {0x90089, 0x0}, - {0x9008a, 0x0}, - {0x9008b, 0x0}, - {0x9008c, 0x0}, - {0x9008d, 0x0}, - {0x9008e, 0x0}, - {0x9008f, 0x0}, - {0x90090, 0x0}, - {0x90091, 0x0}, - {0x90092, 0x0}, - {0x90093, 0x0}, - {0x90094, 0x0}, - {0x90095, 0x0}, - {0x90096, 0x0}, - {0x90097, 0x0}, - {0x90098, 0x0}, - {0x90099, 0x0}, - {0x9009a, 0x0}, - {0x9009b, 0x0}, - {0x9009c, 0x0}, - {0x9009d, 0x0}, - {0x9009e, 0x0}, - {0x9009f, 0x0}, - {0x900a0, 0x0}, - {0x900a1, 0x0}, - {0x900a2, 0x0}, - {0x900a3, 0x0}, - {0x900a4, 0x0}, - {0x900a5, 0x0}, - {0x900a6, 0x0}, - {0x900a7, 0x0}, - {0x900a8, 0x0}, - {0x900a9, 0x0}, - {0x40000, 0x0}, - {0x40020, 0x0}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x0}, - {0x40021, 0x0}, - {0x40041, 0x0}, - {0x40061, 0x0}, - {0x40002, 0x0}, - {0x40022, 0x0}, - {0x40042, 0x0}, - {0x40062, 0x0}, - {0x40003, 0x0}, - {0x40023, 0x0}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x0}, - {0x40024, 0x0}, - {0x40044, 0x0}, - {0x40064, 0x0}, - {0x40005, 0x0}, - {0x40025, 0x0}, - {0x40045, 0x0}, - {0x40065, 0x0}, - {0x40006, 0x0}, - {0x40026, 0x0}, - {0x40046, 0x0}, - {0x40066, 0x0}, - {0x40007, 0x0}, - {0x40027, 0x0}, - {0x40047, 0x0}, - {0x40067, 0x0}, - {0x40008, 0x0}, - {0x40028, 0x0}, - {0x40048, 0x0}, - {0x40068, 0x0}, - {0x40009, 0x0}, - {0x40029, 0x0}, - {0x40049, 0x0}, - {0x40069, 0x0}, - {0x4000a, 0x0}, - {0x4002a, 0x0}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x0}, - {0x4002b, 0x0}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x0}, - {0x4002c, 0x0}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0x0}, - {0x4002d, 0x0}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x0}, - {0x4002e, 0x0}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x0}, - {0x4002f, 0x0}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x0}, - {0x40030, 0x0}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x0}, - {0x40031, 0x0}, - {0x40051, 0x0}, - {0x40071, 0x0}, - {0x40012, 0x0}, - {0x40032, 0x0}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x0}, - {0x40033, 0x0}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x0}, - {0x40034, 0x0}, - {0x40054, 0x0}, - {0x40074, 0x0}, - {0x40015, 0x0}, - {0x40035, 0x0}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x0}, - {0x40036, 0x0}, - {0x40056, 0x0}, - {0x40076, 0x0}, - {0x40017, 0x0}, - {0x40037, 0x0}, - {0x40057, 0x0}, - {0x40077, 0x0}, - {0x40018, 0x0}, - {0x40038, 0x0}, - {0x40058, 0x0}, - {0x40078, 0x0}, - {0x40019, 0x0}, - {0x40039, 0x0}, - {0x40059, 0x0}, - {0x40079, 0x0}, - {0x4001a, 0x0}, - {0x4003a, 0x0}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x0}, - {0x900ac, 0x0}, - {0x900ad, 0x0}, - {0x900ae, 0x0}, - {0x900af, 0x0}, - {0x900b0, 0x0}, - {0x900b1, 0x0}, - {0x900b2, 0x0}, - {0x900b3, 0x0}, - {0x900b4, 0x0}, - {0x900b5, 0x0}, - {0x900b6, 0x0}, - {0x900b7, 0x0}, - {0x900b8, 0x0}, - {0x900b9, 0x0}, - {0x900ba, 0x0}, - {0x900bb, 0x0}, - {0x900bc, 0x0}, - {0x900bd, 0x0}, - {0x900be, 0x0}, - {0x900bf, 0x0}, - {0x900c0, 0x0}, - {0x900c1, 0x0}, - {0x900c2, 0x0}, - {0x900c3, 0x0}, - {0x900c4, 0x0}, - {0x900c5, 0x0}, - {0x900c6, 0x0}, - {0x900c7, 0x0}, - {0x900c8, 0x0}, - {0x900c9, 0x0}, - {0x900ca, 0x0}, - {0x900cb, 0x0}, - {0x900cc, 0x0}, - {0x900cd, 0x0}, - {0x900ce, 0x0}, - {0x900cf, 0x0}, - {0x900d0, 0x0}, - {0x900d1, 0x0}, - {0x900d2, 0x0}, - {0x900d3, 0x0}, - {0x900d4, 0x0}, - {0x900d5, 0x0}, - {0x900d6, 0x0}, - {0x900d7, 0x0}, - {0x900d8, 0x0}, - {0x900d9, 0x0}, - {0x900da, 0x0}, - {0x900db, 0x0}, - {0x900dc, 0x0}, - {0x900dd, 0x0}, - {0x900de, 0x0}, - {0x900df, 0x0}, - {0x900e0, 0x0}, - {0x900e1, 0x0}, - {0x900e2, 0x0}, - {0x900e3, 0x0}, - {0x900e4, 0x0}, - {0x900e5, 0x0}, - {0x900e6, 0x0}, - {0x900e7, 0x0}, - {0x900e8, 0x0}, - {0x900e9, 0x0}, - {0x900ea, 0x0}, - {0x900eb, 0x0}, - {0x900ec, 0x0}, - {0x900ed, 0x0}, - {0x900ee, 0x0}, - {0x900ef, 0x0}, - {0x900f0, 0x0}, - {0x900f1, 0x0}, - {0x900f2, 0x0}, - {0x900f3, 0x0}, - {0x900f4, 0x0}, - {0x900f5, 0x0}, - {0x900f6, 0x0}, - {0x900f7, 0x0}, - {0x900f8, 0x0}, - {0x900f9, 0x0}, - {0x900fa, 0x0}, - {0x900fb, 0x0}, - {0x900fc, 0x0}, - {0x900fd, 0x0}, - {0x900fe, 0x0}, - {0x900ff, 0x0}, - {0x90100, 0x0}, - {0x90101, 0x0}, - {0x90102, 0x0}, - {0x90103, 0x0}, - {0x90104, 0x0}, - {0x90105, 0x0}, - {0x90106, 0x0}, - {0x90107, 0x0}, - {0x90108, 0x0}, - {0x90109, 0x0}, - {0x9010a, 0x0}, - {0x9010b, 0x0}, - {0x9010c, 0x0}, - {0x9010d, 0x0}, - {0x9010e, 0x0}, - {0x9010f, 0x0}, - {0x90110, 0x0}, - {0x90111, 0x0}, - {0x90112, 0x0}, - {0x90113, 0x0}, - {0x90114, 0x0}, - {0x90115, 0x0}, - {0x90116, 0x0}, - {0x90117, 0x0}, - {0x90118, 0x0}, - {0x90119, 0x0}, - {0x9011a, 0x0}, - {0x9011b, 0x0}, - {0x9011c, 0x0}, - {0x9011d, 0x0}, - {0x9011e, 0x0}, - {0x9011f, 0x0}, - {0x90120, 0x0}, - {0x90121, 0x0}, - {0x90122, 0x0}, - {0x90123, 0x0}, - {0x90124, 0x0}, - {0x90125, 0x0}, - {0x90126, 0x0}, - {0x90127, 0x0}, - {0x90128, 0x0}, - {0x90129, 0x0}, - {0x9012a, 0x0}, - {0x9012b, 0x0}, - {0x9012c, 0x0}, - {0x9012d, 0x0}, - {0x9012e, 0x0}, - {0x9012f, 0x0}, - {0x90130, 0x0}, - {0x90131, 0x0}, - {0x90132, 0x0}, - {0x90133, 0x0}, - {0x90134, 0x0}, - {0x90135, 0x0}, - {0x90136, 0x0}, - {0x90137, 0x0}, - {0x90138, 0x0}, - {0x90139, 0x0}, - {0x9013a, 0x0}, - {0x9013b, 0x0}, - {0x9013c, 0x0}, - {0x9013d, 0x0}, - {0x9013e, 0x0}, - {0x9013f, 0x0}, - {0x90140, 0x0}, - {0x90141, 0x0}, - {0x90142, 0x0}, - {0x90143, 0x0}, - {0x90144, 0x0}, - {0x90145, 0x0}, - {0x90146, 0x0}, - {0x90147, 0x0}, - {0x90148, 0x0}, - {0x90149, 0x0}, - {0x9014a, 0x0}, - {0x9014b, 0x0}, - {0x9014c, 0x0}, - {0x9014d, 0x0}, - {0x9014e, 0x0}, - {0x9014f, 0x0}, - {0x90150, 0x0}, - {0x90151, 0x0}, - {0x90152, 0x0}, - {0x90153, 0x0}, - {0x90154, 0x0}, - {0x90155, 0x0}, - {0x90156, 0x0}, - {0x90157, 0x0}, - {0x90158, 0x0}, - {0x90159, 0x0}, - {0x9015a, 0x0}, - {0x9015b, 0x0}, - {0x9015c, 0x0}, - {0x9015d, 0x0}, - {0x9015e, 0x0}, - {0x9015f, 0x0}, - {0x90160, 0x0}, - {0x90161, 0x0}, - {0x90162, 0x0}, - {0x90163, 0x0}, - {0x90164, 0x0}, - {0x90165, 0x0}, - {0x90166, 0x0}, - {0x90167, 0x0}, - {0x90168, 0x0}, - {0x90169, 0x0}, - {0x9016a, 0x0}, - {0x9016b, 0x0}, - {0x9016c, 0x0}, - {0x9016d, 0x0}, - {0x9016e, 0x0}, - {0x9016f, 0x0}, - {0x90170, 0x0}, - {0x90171, 0x0}, - {0x90172, 0x0}, - {0x90173, 0x0}, - {0x90174, 0x0}, - {0x90175, 0x0}, - {0x90176, 0x0}, - {0x90177, 0x0}, - {0x90178, 0x0}, - {0x90179, 0x0}, - {0x9017a, 0x0}, - {0x9017b, 0x0}, - {0x9017c, 0x0}, - {0x9017d, 0x0}, - {0x9017e, 0x0}, - {0x9017f, 0x0}, - {0x90180, 0x0}, - {0x90181, 0x0}, - {0x90182, 0x0}, - {0x90183, 0x0}, - {0x90184, 0x0}, - {0x90006, 0x0}, - {0x90007, 0x0}, - {0x90008, 0x0}, - {0x90009, 0x0}, - {0x9000a, 0x0}, - {0x9000b, 0x0}, - {0xd00e7, 0x0}, - {0x90017, 0x0}, - {0x9001f, 0x0}, - {0x90026, 0x0}, - {0x400d0, 0x0}, - {0x400d1, 0x0}, - {0x400d2, 0x0}, - {0x400d3, 0x0}, - {0x400d4, 0x0}, - {0x400d5, 0x0}, - {0x400d6, 0x0}, - {0x400d7, 0x0}, - {0x200be, 0x0}, - {0x2000b, 0x0}, - {0x2000c, 0x0}, - {0x2000d, 0x0}, - {0x2000e, 0x0}, - {0x12000b, 0x0}, - {0x12000c, 0x0}, - {0x12000d, 0x0}, - {0x12000e, 0x0}, - {0x22000b, 0x0}, - {0x22000c, 0x0}, - {0x22000d, 0x0}, - {0x22000e, 0x0}, - {0x9000c, 0x0}, - {0x9000d, 0x0}, - {0x9000e, 0x0}, - {0x9000f, 0x0}, - {0x90010, 0x0}, - {0x90011, 0x0}, - {0x90012, 0x0}, - {0x90013, 0x0}, - {0x20010, 0x0}, - {0x20011, 0x0}, - {0x120010, 0x0}, - {0x120011, 0x0}, - {0x40080, 0x0}, - {0x40081, 0x0}, - {0x40082, 0x0}, - {0x40083, 0x0}, - {0x40084, 0x0}, - {0x40085, 0x0}, - {0x140080, 0x0}, - {0x140081, 0x0}, - {0x140082, 0x0}, - {0x140083, 0x0}, - {0x140084, 0x0}, - {0x140085, 0x0}, - {0x240080, 0x0}, - {0x240081, 0x0}, - {0x240082, 0x0}, - {0x240083, 0x0}, - {0x240084, 0x0}, - {0x240085, 0x0}, - {0x400fd, 0x0}, - {0x400f1, 0x0}, - {0x10011, 0x0}, - {0x10012, 0x0}, - {0x10013, 0x0}, - {0x10018, 0x0}, - {0x10002, 0x0}, - {0x100b2, 0x0}, - {0x101b4, 0x0}, - {0x102b4, 0x0}, - {0x103b4, 0x0}, - {0x104b4, 0x0}, - {0x105b4, 0x0}, - {0x106b4, 0x0}, - {0x107b4, 0x0}, - {0x108b4, 0x0}, - {0x11011, 0x0}, - {0x11012, 0x0}, - {0x11013, 0x0}, - {0x11018, 0x0}, - {0x11002, 0x0}, - {0x110b2, 0x0}, - {0x111b4, 0x0}, - {0x112b4, 0x0}, - {0x113b4, 0x0}, - {0x114b4, 0x0}, - {0x115b4, 0x0}, - {0x116b4, 0x0}, - {0x117b4, 0x0}, - {0x118b4, 0x0}, - {0x20089, 0x0}, - {0xc0080, 0x0}, - {0x200cb, 0x0}, - {0x10068, 0x0}, - {0x10069, 0x0}, - {0x10168, 0x0}, - {0x10169, 0x0}, - {0x10268, 0x0}, - {0x10269, 0x0}, - {0x10368, 0x0}, - {0x10369, 0x0}, - {0x10468, 0x0}, - {0x10469, 0x0}, - {0x10568, 0x0}, - {0x10569, 0x0}, - {0x10668, 0x0}, - {0x10669, 0x0}, - {0x10768, 0x0}, - {0x10769, 0x0}, - {0x10868, 0x0}, - {0x10869, 0x0}, - {0x100aa, 0x0}, - {0x10062, 0x0}, - {0x10001, 0x0}, - {0x100a0, 0x0}, - {0x100a1, 0x0}, - {0x100a2, 0x0}, - {0x100a3, 0x0}, - {0x100a4, 0x0}, - {0x100a5, 0x0}, - {0x100a6, 0x0}, - {0x100a7, 0x0}, - {0x11068, 0x0}, - {0x11069, 0x0}, - {0x11168, 0x0}, - {0x11169, 0x0}, - {0x11268, 0x0}, - {0x11269, 0x0}, - {0x11368, 0x0}, - {0x11369, 0x0}, - {0x11468, 0x0}, - {0x11469, 0x0}, - {0x11568, 0x0}, - {0x11569, 0x0}, - {0x11668, 0x0}, - {0x11669, 0x0}, - {0x11768, 0x0}, - {0x11769, 0x0}, - {0x11868, 0x0}, - {0x11869, 0x0}, - {0x110aa, 0x0}, - {0x11062, 0x0}, - {0x11001, 0x0}, - {0x110a0, 0x0}, - {0x110a1, 0x0}, - {0x110a2, 0x0}, - {0x110a3, 0x0}, - {0x110a4, 0x0}, - {0x110a5, 0x0}, - {0x110a6, 0x0}, - {0x110a7, 0x0}, - {0x80, 0x0}, - {0x1080, 0x0}, - {0x2080, 0x0}, - {0x10020, 0x0}, - {0x10080, 0x0}, - {0x10081, 0x0}, - {0x100d0, 0x0}, - {0x100d1, 0x0}, - {0x1008c, 0x0}, - {0x1008d, 0x0}, - {0x10180, 0x0}, - {0x10181, 0x0}, - {0x101d0, 0x0}, - {0x101d1, 0x0}, - {0x1018c, 0x0}, - {0x1018d, 0x0}, - {0x100c0, 0x0}, - {0x100c1, 0x0}, - {0x101c0, 0x0}, - {0x101c1, 0x0}, - {0x102c0, 0x0}, - {0x102c1, 0x0}, - {0x103c0, 0x0}, - {0x103c1, 0x0}, - {0x104c0, 0x0}, - {0x104c1, 0x0}, - {0x105c0, 0x0}, - {0x105c1, 0x0}, - {0x106c0, 0x0}, - {0x106c1, 0x0}, - {0x107c0, 0x0}, - {0x107c1, 0x0}, - {0x108c0, 0x0}, - {0x108c1, 0x0}, - {0x100ae, 0x0}, - {0x100af, 0x0}, - {0x11020, 0x0}, - {0x11080, 0x0}, - {0x11081, 0x0}, - {0x110d0, 0x0}, - {0x110d1, 0x0}, - {0x1108c, 0x0}, - {0x1108d, 0x0}, - {0x11180, 0x0}, - {0x11181, 0x0}, - {0x111d0, 0x0}, - {0x111d1, 0x0}, - {0x1118c, 0x0}, - {0x1118d, 0x0}, - {0x110c0, 0x0}, - {0x110c1, 0x0}, - {0x111c0, 0x0}, - {0x111c1, 0x0}, - {0x112c0, 0x0}, - {0x112c1, 0x0}, - {0x113c0, 0x0}, - {0x113c1, 0x0}, - {0x114c0, 0x0}, - {0x114c1, 0x0}, - {0x115c0, 0x0}, - {0x115c1, 0x0}, - {0x116c0, 0x0}, - {0x116c1, 0x0}, - {0x117c0, 0x0}, - {0x117c1, 0x0}, - {0x118c0, 0x0}, - {0x118c1, 0x0}, - {0x110ae, 0x0}, - {0x110af, 0x0}, - {0x90201, 0x0}, - {0x90202, 0x0}, - {0x90203, 0x0}, - {0x90205, 0x0}, - {0x90206, 0x0}, - {0x90207, 0x0}, - {0x90208, 0x0}, - {0x20020, 0x0}, - {0x100080, 0x0}, - {0x101080, 0x0}, - {0x102080, 0x0}, - {0x110020, 0x0}, - {0x110080, 0x0}, - {0x110081, 0x0}, - {0x1100d0, 0x0}, - {0x1100d1, 0x0}, - {0x11008c, 0x0}, - {0x11008d, 0x0}, - {0x110180, 0x0}, - {0x110181, 0x0}, - {0x1101d0, 0x0}, - {0x1101d1, 0x0}, - {0x11018c, 0x0}, - {0x11018d, 0x0}, - {0x1100c0, 0x0}, - {0x1100c1, 0x0}, - {0x1101c0, 0x0}, - {0x1101c1, 0x0}, - {0x1102c0, 0x0}, - {0x1102c1, 0x0}, - {0x1103c0, 0x0}, - {0x1103c1, 0x0}, - {0x1104c0, 0x0}, - {0x1104c1, 0x0}, - {0x1105c0, 0x0}, - {0x1105c1, 0x0}, - {0x1106c0, 0x0}, - {0x1106c1, 0x0}, - {0x1107c0, 0x0}, - {0x1107c1, 0x0}, - {0x1108c0, 0x0}, - {0x1108c1, 0x0}, - {0x1100ae, 0x0}, - {0x1100af, 0x0}, - {0x111020, 0x0}, - {0x111080, 0x0}, - {0x111081, 0x0}, - {0x1110d0, 0x0}, - {0x1110d1, 0x0}, - {0x11108c, 0x0}, - {0x11108d, 0x0}, - {0x111180, 0x0}, - {0x111181, 0x0}, - {0x1111d0, 0x0}, - {0x1111d1, 0x0}, - {0x11118c, 0x0}, - {0x11118d, 0x0}, - {0x1110c0, 0x0}, - {0x1110c1, 0x0}, - {0x1111c0, 0x0}, - {0x1111c1, 0x0}, - {0x1112c0, 0x0}, - {0x1112c1, 0x0}, - {0x1113c0, 0x0}, - {0x1113c1, 0x0}, - {0x1114c0, 0x0}, - {0x1114c1, 0x0}, - {0x1115c0, 0x0}, - {0x1115c1, 0x0}, - {0x1116c0, 0x0}, - {0x1116c1, 0x0}, - {0x1117c0, 0x0}, - {0x1117c1, 0x0}, - {0x1118c0, 0x0}, - {0x1118c1, 0x0}, - {0x1110ae, 0x0}, - {0x1110af, 0x0}, - {0x190201, 0x0}, - {0x190202, 0x0}, - {0x190203, 0x0}, - {0x190205, 0x0}, - {0x190206, 0x0}, - {0x190207, 0x0}, - {0x190208, 0x0}, - {0x120020, 0x0}, - {0x200080, 0x0}, - {0x201080, 0x0}, - {0x202080, 0x0}, - {0x210020, 0x0}, - {0x210080, 0x0}, - {0x210081, 0x0}, - {0x2100d0, 0x0}, - {0x2100d1, 0x0}, - {0x21008c, 0x0}, - {0x21008d, 0x0}, - {0x210180, 0x0}, - {0x210181, 0x0}, - {0x2101d0, 0x0}, - {0x2101d1, 0x0}, - {0x21018c, 0x0}, - {0x21018d, 0x0}, - {0x2100c0, 0x0}, - {0x2100c1, 0x0}, - {0x2101c0, 0x0}, - {0x2101c1, 0x0}, - {0x2102c0, 0x0}, - {0x2102c1, 0x0}, - {0x2103c0, 0x0}, - {0x2103c1, 0x0}, - {0x2104c0, 0x0}, - {0x2104c1, 0x0}, - {0x2105c0, 0x0}, - {0x2105c1, 0x0}, - {0x2106c0, 0x0}, - {0x2106c1, 0x0}, - {0x2107c0, 0x0}, - {0x2107c1, 0x0}, - {0x2108c0, 0x0}, - {0x2108c1, 0x0}, - {0x2100ae, 0x0}, - {0x2100af, 0x0}, - {0x211020, 0x0}, - {0x211080, 0x0}, - {0x211081, 0x0}, - {0x2110d0, 0x0}, - {0x2110d1, 0x0}, - {0x21108c, 0x0}, - {0x21108d, 0x0}, - {0x211180, 0x0}, - {0x211181, 0x0}, - {0x2111d0, 0x0}, - {0x2111d1, 0x0}, - {0x21118c, 0x0}, - {0x21118d, 0x0}, - {0x2110c0, 0x0}, - {0x2110c1, 0x0}, - {0x2111c0, 0x0}, - {0x2111c1, 0x0}, - {0x2112c0, 0x0}, - {0x2112c1, 0x0}, - {0x2113c0, 0x0}, - {0x2113c1, 0x0}, - {0x2114c0, 0x0}, - {0x2114c1, 0x0}, - {0x2115c0, 0x0}, - {0x2115c1, 0x0}, - {0x2116c0, 0x0}, - {0x2116c1, 0x0}, - {0x2117c0, 0x0}, - {0x2117c1, 0x0}, - {0x2118c0, 0x0}, - {0x2118c1, 0x0}, - {0x2110ae, 0x0}, - {0x2110af, 0x0}, - {0x290201, 0x0}, - {0x290202, 0x0}, - {0x290203, 0x0}, - {0x290205, 0x0}, - {0x290206, 0x0}, - {0x290207, 0x0}, - {0x290208, 0x0}, - {0x220020, 0x0}, - {0x20077, 0x0}, - {0x20072, 0x0}, - {0x20073, 0x0}, - {0x400c0, 0x0}, - {0x10040, 0x0}, - {0x10140, 0x0}, - {0x10240, 0x0}, - {0x10340, 0x0}, - {0x10440, 0x0}, - {0x10540, 0x0}, - {0x10640, 0x0}, - {0x10740, 0x0}, - {0x10840, 0x0}, - {0x11040, 0x0}, - {0x11140, 0x0}, - {0x11240, 0x0}, - {0x11340, 0x0}, - {0x11440, 0x0}, - {0x11540, 0x0}, - {0x11640, 0x0}, - {0x11740, 0x0}, - {0x11840, 0x0}, -}; - -/* P0 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0x640}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x131f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x52a4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x52a4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xa400}, - {0x54033, 0x3352}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xa400}, - {0x54039, 0x3352}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P1 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp1_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x1}, - {0x54003, 0x320}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x994}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x994}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0x9400}, - {0x54033, 0x3309}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0x9400}, - {0x54039, 0x3309}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P2 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp2_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x102}, - {0x54003, 0x270}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x994}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4800}, - {0x5401e, 0x4}, - {0x5401f, 0x994}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4800}, - {0x54024, 0x4}, - {0x54032, 0x9400}, - {0x54033, 0x3309}, - {0x54034, 0x4600}, - {0x54035, 0x11}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0x9400}, - {0x54039, 0x3309}, - {0x5403a, 0x4600}, - {0x5403b, 0x11}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P0 2D message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0x640}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x61}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54010, 0x2080}, - {0x54012, 0x110}, - {0x54019, 0x52a4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x52a4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xa400}, - {0x54033, 0x3352}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xa400}, - {0x54039, 0x3352}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* DRAM PHY init engine image */ -static struct dram_cfg_param ddr_phy_pie[] = { - {0xd0000, 0x0}, - {0x90000, 0x10}, - {0x90001, 0x400}, - {0x90002, 0x10e}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x8}, - {0x90029, 0xb}, - {0x9002a, 0x480}, - {0x9002b, 0x109}, - {0x9002c, 0x8}, - {0x9002d, 0x448}, - {0x9002e, 0x139}, - {0x9002f, 0x8}, - {0x90030, 0x478}, - {0x90031, 0x109}, - {0x90032, 0x0}, - {0x90033, 0xe8}, - {0x90034, 0x109}, - {0x90035, 0x2}, - {0x90036, 0x10}, - {0x90037, 0x139}, - {0x90038, 0xb}, - {0x90039, 0x7c0}, - {0x9003a, 0x139}, - {0x9003b, 0x44}, - {0x9003c, 0x633}, - {0x9003d, 0x159}, - {0x9003e, 0x14f}, - {0x9003f, 0x630}, - {0x90040, 0x159}, - {0x90041, 0x47}, - {0x90042, 0x633}, - {0x90043, 0x149}, - {0x90044, 0x4f}, - {0x90045, 0x633}, - {0x90046, 0x179}, - {0x90047, 0x8}, - {0x90048, 0xe0}, - {0x90049, 0x109}, - {0x9004a, 0x0}, - {0x9004b, 0x7c8}, - {0x9004c, 0x109}, - {0x9004d, 0x0}, - {0x9004e, 0x1}, - {0x9004f, 0x8}, - {0x90050, 0x30}, - {0x90051, 0x65a}, - {0x90052, 0x9}, - {0x90053, 0x0}, - {0x90054, 0x45a}, - {0x90055, 0x9}, - {0x90056, 0x0}, - {0x90057, 0x448}, - {0x90058, 0x109}, - {0x90059, 0x40}, - {0x9005a, 0x633}, - {0x9005b, 0x179}, - {0x9005c, 0x1}, - {0x9005d, 0x618}, - {0x9005e, 0x109}, - {0x9005f, 0x40c0}, - {0x90060, 0x633}, - {0x90061, 0x149}, - {0x90062, 0x8}, - {0x90063, 0x4}, - {0x90064, 0x48}, - {0x90065, 0x4040}, - {0x90066, 0x633}, - {0x90067, 0x149}, - {0x90068, 0x0}, - {0x90069, 0x4}, - {0x9006a, 0x48}, - {0x9006b, 0x40}, - {0x9006c, 0x633}, - {0x9006d, 0x149}, - {0x9006e, 0x0}, - {0x9006f, 0x658}, - {0x90070, 0x109}, - {0x90071, 0x10}, - {0x90072, 0x4}, - {0x90073, 0x18}, - {0x90074, 0x0}, - {0x90075, 0x4}, - {0x90076, 0x78}, - {0x90077, 0x549}, - {0x90078, 0x633}, - {0x90079, 0x159}, - {0x9007a, 0xd49}, - {0x9007b, 0x633}, - {0x9007c, 0x159}, - {0x9007d, 0x94a}, - {0x9007e, 0x633}, - {0x9007f, 0x159}, - {0x90080, 0x441}, - {0x90081, 0x633}, - {0x90082, 0x149}, - {0x90083, 0x42}, - {0x90084, 0x633}, - {0x90085, 0x149}, - {0x90086, 0x1}, - {0x90087, 0x633}, - {0x90088, 0x149}, - {0x90089, 0x0}, - {0x9008a, 0xe0}, - {0x9008b, 0x109}, - {0x9008c, 0xa}, - {0x9008d, 0x10}, - {0x9008e, 0x109}, - {0x9008f, 0x9}, - {0x90090, 0x3c0}, - {0x90091, 0x149}, - {0x90092, 0x9}, - {0x90093, 0x3c0}, - {0x90094, 0x159}, - {0x90095, 0x18}, - {0x90096, 0x10}, - {0x90097, 0x109}, - {0x90098, 0x0}, - {0x90099, 0x3c0}, - {0x9009a, 0x109}, - {0x9009b, 0x18}, - {0x9009c, 0x4}, - {0x9009d, 0x48}, - {0x9009e, 0x18}, - {0x9009f, 0x4}, - {0x900a0, 0x58}, - {0x900a1, 0xb}, - {0x900a2, 0x10}, - {0x900a3, 0x109}, - {0x900a4, 0x1}, - {0x900a5, 0x10}, - {0x900a6, 0x109}, - {0x900a7, 0x5}, - {0x900a8, 0x7c0}, - {0x900a9, 0x109}, - {0x40000, 0x811}, - {0x40020, 0x880}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x4008}, - {0x40021, 0x83}, - {0x40041, 0x4f}, - {0x40061, 0x0}, - {0x40002, 0x4040}, - {0x40022, 0x83}, - {0x40042, 0x51}, - {0x40062, 0x0}, - {0x40003, 0x811}, - {0x40023, 0x880}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x720}, - {0x40024, 0xf}, - {0x40044, 0x1740}, - {0x40064, 0x0}, - {0x40005, 0x16}, - {0x40025, 0x83}, - {0x40045, 0x4b}, - {0x40065, 0x0}, - {0x40006, 0x716}, - {0x40026, 0xf}, - {0x40046, 0x2001}, - {0x40066, 0x0}, - {0x40007, 0x716}, - {0x40027, 0xf}, - {0x40047, 0x2800}, - {0x40067, 0x0}, - {0x40008, 0x716}, - {0x40028, 0xf}, - {0x40048, 0xf00}, - {0x40068, 0x0}, - {0x40009, 0x720}, - {0x40029, 0xf}, - {0x40049, 0x1400}, - {0x40069, 0x0}, - {0x4000a, 0xe08}, - {0x4002a, 0xc15}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x625}, - {0x4002b, 0x15}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x4028}, - {0x4002c, 0x80}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0xe08}, - {0x4002d, 0xc1a}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x625}, - {0x4002e, 0x1a}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x4040}, - {0x4002f, 0x80}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x2604}, - {0x40030, 0x15}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x708}, - {0x40031, 0x5}, - {0x40051, 0x0}, - {0x40071, 0x2002}, - {0x40012, 0x8}, - {0x40032, 0x80}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x2604}, - {0x40033, 0x1a}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x708}, - {0x40034, 0xa}, - {0x40054, 0x0}, - {0x40074, 0x2002}, - {0x40015, 0x4040}, - {0x40035, 0x80}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x60a}, - {0x40036, 0x15}, - {0x40056, 0x1200}, - {0x40076, 0x0}, - {0x40017, 0x61a}, - {0x40037, 0x15}, - {0x40057, 0x1300}, - {0x40077, 0x0}, - {0x40018, 0x60a}, - {0x40038, 0x1a}, - {0x40058, 0x1200}, - {0x40078, 0x0}, - {0x40019, 0x642}, - {0x40039, 0x1a}, - {0x40059, 0x1300}, - {0x40079, 0x0}, - {0x4001a, 0x4808}, - {0x4003a, 0x880}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x790}, - {0x900ac, 0x11a}, - {0x900ad, 0x8}, - {0x900ae, 0x7aa}, - {0x900af, 0x2a}, - {0x900b0, 0x10}, - {0x900b1, 0x7b2}, - {0x900b2, 0x2a}, - {0x900b3, 0x0}, - {0x900b4, 0x7c8}, - {0x900b5, 0x109}, - {0x900b6, 0x10}, - {0x900b7, 0x10}, - {0x900b8, 0x109}, - {0x900b9, 0x10}, - {0x900ba, 0x2a8}, - {0x900bb, 0x129}, - {0x900bc, 0x8}, - {0x900bd, 0x370}, - {0x900be, 0x129}, - {0x900bf, 0xa}, - {0x900c0, 0x3c8}, - {0x900c1, 0x1a9}, - {0x900c2, 0xc}, - {0x900c3, 0x408}, - {0x900c4, 0x199}, - {0x900c5, 0x14}, - {0x900c6, 0x790}, - {0x900c7, 0x11a}, - {0x900c8, 0x8}, - {0x900c9, 0x4}, - {0x900ca, 0x18}, - {0x900cb, 0xe}, - {0x900cc, 0x408}, - {0x900cd, 0x199}, - {0x900ce, 0x8}, - {0x900cf, 0x8568}, - {0x900d0, 0x108}, - {0x900d1, 0x18}, - {0x900d2, 0x790}, - {0x900d3, 0x16a}, - {0x900d4, 0x8}, - {0x900d5, 0x1d8}, - {0x900d6, 0x169}, - {0x900d7, 0x10}, - {0x900d8, 0x8558}, - {0x900d9, 0x168}, - {0x900da, 0x1ff8}, - {0x900db, 0x85a8}, - {0x900dc, 0x1e8}, - {0x900dd, 0x50}, - {0x900de, 0x798}, - {0x900df, 0x16a}, - {0x900e0, 0x60}, - {0x900e1, 0x7a0}, - {0x900e2, 0x16a}, - {0x900e3, 0x8}, - {0x900e4, 0x8310}, - {0x900e5, 0x168}, - {0x900e6, 0x8}, - {0x900e7, 0xa310}, - {0x900e8, 0x168}, - {0x900e9, 0xa}, - {0x900ea, 0x408}, - {0x900eb, 0x169}, - {0x900ec, 0x6e}, - {0x900ed, 0x0}, - {0x900ee, 0x68}, - {0x900ef, 0x0}, - {0x900f0, 0x408}, - {0x900f1, 0x169}, - {0x900f2, 0x0}, - {0x900f3, 0x8310}, - {0x900f4, 0x168}, - {0x900f5, 0x0}, - {0x900f6, 0xa310}, - {0x900f7, 0x168}, - {0x900f8, 0x1ff8}, - {0x900f9, 0x85a8}, - {0x900fa, 0x1e8}, - {0x900fb, 0x68}, - {0x900fc, 0x798}, - {0x900fd, 0x16a}, - {0x900fe, 0x78}, - {0x900ff, 0x7a0}, - {0x90100, 0x16a}, - {0x90101, 0x68}, - {0x90102, 0x790}, - {0x90103, 0x16a}, - {0x90104, 0x8}, - {0x90105, 0x8b10}, - {0x90106, 0x168}, - {0x90107, 0x8}, - {0x90108, 0xab10}, - {0x90109, 0x168}, - {0x9010a, 0xa}, - {0x9010b, 0x408}, - {0x9010c, 0x169}, - {0x9010d, 0x58}, - {0x9010e, 0x0}, - {0x9010f, 0x68}, - {0x90110, 0x0}, - {0x90111, 0x408}, - {0x90112, 0x169}, - {0x90113, 0x0}, - {0x90114, 0x8b10}, - {0x90115, 0x168}, - {0x90116, 0x1}, - {0x90117, 0xab10}, - {0x90118, 0x168}, - {0x90119, 0x0}, - {0x9011a, 0x1d8}, - {0x9011b, 0x169}, - {0x9011c, 0x80}, - {0x9011d, 0x790}, - {0x9011e, 0x16a}, - {0x9011f, 0x18}, - {0x90120, 0x7aa}, - {0x90121, 0x6a}, - {0x90122, 0xa}, - {0x90123, 0x0}, - {0x90124, 0x1e9}, - {0x90125, 0x8}, - {0x90126, 0x8080}, - {0x90127, 0x108}, - {0x90128, 0xf}, - {0x90129, 0x408}, - {0x9012a, 0x169}, - {0x9012b, 0xc}, - {0x9012c, 0x0}, - {0x9012d, 0x68}, - {0x9012e, 0x9}, - {0x9012f, 0x0}, - {0x90130, 0x1a9}, - {0x90131, 0x0}, - {0x90132, 0x408}, - {0x90133, 0x169}, - {0x90134, 0x0}, - {0x90135, 0x8080}, - {0x90136, 0x108}, - {0x90137, 0x8}, - {0x90138, 0x7aa}, - {0x90139, 0x6a}, - {0x9013a, 0x0}, - {0x9013b, 0x8568}, - {0x9013c, 0x108}, - {0x9013d, 0xb7}, - {0x9013e, 0x790}, - {0x9013f, 0x16a}, - {0x90140, 0x1f}, - {0x90141, 0x0}, - {0x90142, 0x68}, - {0x90143, 0x8}, - {0x90144, 0x8558}, - {0x90145, 0x168}, - {0x90146, 0xf}, - {0x90147, 0x408}, - {0x90148, 0x169}, - {0x90149, 0xd}, - {0x9014a, 0x0}, - {0x9014b, 0x68}, - {0x9014c, 0x0}, - {0x9014d, 0x408}, - {0x9014e, 0x169}, - {0x9014f, 0x0}, - {0x90150, 0x8558}, - {0x90151, 0x168}, - {0x90152, 0x8}, - {0x90153, 0x3c8}, - {0x90154, 0x1a9}, - {0x90155, 0x3}, - {0x90156, 0x370}, - {0x90157, 0x129}, - {0x90158, 0x20}, - {0x90159, 0x2aa}, - {0x9015a, 0x9}, - {0x9015b, 0x8}, - {0x9015c, 0xe8}, - {0x9015d, 0x109}, - {0x9015e, 0x0}, - {0x9015f, 0x8140}, - {0x90160, 0x10c}, - {0x90161, 0x10}, - {0x90162, 0x8138}, - {0x90163, 0x104}, - {0x90164, 0x8}, - {0x90165, 0x448}, - {0x90166, 0x109}, - {0x90167, 0xf}, - {0x90168, 0x7c0}, - {0x90169, 0x109}, - {0x9016a, 0x0}, - {0x9016b, 0xe8}, - {0x9016c, 0x109}, - {0x9016d, 0x47}, - {0x9016e, 0x630}, - {0x9016f, 0x109}, - {0x90170, 0x8}, - {0x90171, 0x618}, - {0x90172, 0x109}, - {0x90173, 0x8}, - {0x90174, 0xe0}, - {0x90175, 0x109}, - {0x90176, 0x0}, - {0x90177, 0x7c8}, - {0x90178, 0x109}, - {0x90179, 0x8}, - {0x9017a, 0x8140}, - {0x9017b, 0x10c}, - {0x9017c, 0x0}, - {0x9017d, 0x478}, - {0x9017e, 0x109}, - {0x9017f, 0x0}, - {0x90180, 0x1}, - {0x90181, 0x8}, - {0x90182, 0x8}, - {0x90183, 0x4}, - {0x90184, 0x0}, - {0x90006, 0x8}, - {0x90007, 0x7c8}, - {0x90008, 0x109}, - {0x90009, 0x0}, - {0x9000a, 0x400}, - {0x9000b, 0x106}, - {0xd00e7, 0x400}, - {0x90017, 0x0}, - {0x9001f, 0x2b}, - {0x90026, 0x69}, - {0x400d0, 0x0}, - {0x400d1, 0x101}, - {0x400d2, 0x105}, - {0x400d3, 0x107}, - {0x400d4, 0x10f}, - {0x400d5, 0x202}, - {0x400d6, 0x20a}, - {0x400d7, 0x20b}, - {0x2003a, 0x2}, - {0x200be, 0x3}, - {0x2000b, 0x1c2}, - {0x2000c, 0x64}, - {0x2000d, 0x3e8}, - {0x2000e, 0x2c}, - {0x12000b, 0xe1}, - {0x12000c, 0x32}, - {0x12000d, 0x1f4}, - {0x12000e, 0x10}, - {0x22000b, 0xb0}, - {0x22000c, 0x27}, - {0x22000d, 0x186}, - {0x22000e, 0x10}, - {0x9000c, 0x0}, - {0x9000d, 0x173}, - {0x9000e, 0x60}, - {0x9000f, 0x6110}, - {0x90010, 0x2152}, - {0x90011, 0xdfbd}, - {0x90012, 0x2060}, - {0x90013, 0x6152}, - {0x20010, 0x5a}, - {0x20011, 0x3}, - {0x120010, 0x5a}, - {0x120011, 0x3}, - {0x40080, 0xe0}, - {0x40081, 0x12}, - {0x40082, 0xe0}, - {0x40083, 0x12}, - {0x40084, 0xe0}, - {0x40085, 0x12}, - {0x140080, 0xe0}, - {0x140081, 0x12}, - {0x140082, 0xe0}, - {0x140083, 0x12}, - {0x140084, 0xe0}, - {0x140085, 0x12}, - {0x240080, 0xe0}, - {0x240081, 0x12}, - {0x240082, 0xe0}, - {0x240083, 0x12}, - {0x240084, 0xe0}, - {0x240085, 0x12}, - {0x400fd, 0xf}, - {0x400f1, 0xe}, - {0x10011, 0x1}, - {0x10012, 0x1}, - {0x10013, 0x180}, - {0x10018, 0x1}, - {0x10002, 0x6209}, - {0x100b2, 0x1}, - {0x101b4, 0x1}, - {0x102b4, 0x1}, - {0x103b4, 0x1}, - {0x104b4, 0x1}, - {0x105b4, 0x1}, - {0x106b4, 0x1}, - {0x107b4, 0x1}, - {0x108b4, 0x1}, - {0x11011, 0x1}, - {0x11012, 0x1}, - {0x11013, 0x180}, - {0x11018, 0x1}, - {0x11002, 0x6209}, - {0x110b2, 0x1}, - {0x111b4, 0x1}, - {0x112b4, 0x1}, - {0x113b4, 0x1}, - {0x114b4, 0x1}, - {0x115b4, 0x1}, - {0x116b4, 0x1}, - {0x117b4, 0x1}, - {0x118b4, 0x1}, - {0x20089, 0x1}, - {0x20088, 0x19}, - {0xc0080, 0x0}, - {0xd0000, 0x1}, -}; - -static struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 1600mts 1D */ - .drate = 1600, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 800mts 1D */ - .drate = 800, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 625mts 1D */ - .drate = 625, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 1600mts 2D */ - .drate = 1600, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing_1600mts = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 1600, 800, 625, }, - .fsp_cfg = ddr_dram_fsp_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), -}; diff --git a/board/freescale/imx91_evk/lpddr4_timing_2400mts.c b/board/freescale/imx91_evk/lpddr4_timing_2400mts.c deleted file mode 100644 index e0e6f5da3d6..00000000000 --- a/board/freescale/imx91_evk/lpddr4_timing_2400mts.c +++ /dev/null @@ -1,1995 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright 2024 NXP - * - * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3. - * DDR PHY FW2022.01 - */ - -#include -#include - -/* Initialize DDRC registers */ -static struct dram_cfg_param ddr_ddrc_cfg[] = { - {0x4e300110, 0x44100001}, - {0x4e300000, 0x8000ff}, - {0x4e300008, 0x0}, - {0x4e300080, 0x80000512}, - {0x4e300084, 0x0}, - {0x4e300114, 0x1002}, - {0x4e300260, 0x80}, - {0x4e300f04, 0x80}, - {0x4e300800, 0x43b30002}, - {0x4e300804, 0x1f1f1f1f}, - {0x4e301000, 0x0}, - {0x4e301240, 0x0}, - {0x4e301244, 0x0}, - {0x4e301248, 0x0}, - {0x4e30124c, 0x0}, - {0x4e301250, 0x0}, - {0x4e301254, 0x0}, - {0x4e301258, 0x0}, - {0x4e30125c, 0x0}, -}; - -/* dram fsp cfg */ -static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { - { - { - {0x4e300100, 0x135C2110}, - {0x4e300104, 0xF8990011}, - {0x4e300108, 0x636E08CC}, - {0x4e30010C, 0x0061E070}, - {0x4e300124, 0x124E0000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x31D00000}, - {0x4e300170, 0x8B0B0608}, - {0x4e300250, 0x0000001A}, - {0x4e300254, 0x00DC00DC}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - {0x4e300300, 0x1633160D}, - {0x4e300304, 0x00DC180C}, - {0x4e300308, 0x0C3C0927}, - }, - { - {0x01, 0xC4}, - {0x02, 0x24}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x010D1100}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0xBABAC068}, - {0x4e30010C, 0x00610158}, - {0x4e300124, 0x09270000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30400000}, - {0x4e300170, 0x8A0A0508}, - {0x4e300250, 0x0000000D}, - {0x4e300254, 0x006A006A}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0xA4}, - {0x02, 0x52}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x00061000}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0x6E62FA48}, - {0x4e30010C, 0x0031010D}, - {0x4e300124, 0x04C50000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30000000}, - {0x4e300170, 0x89090408}, - {0x4e300250, 0x00000007}, - {0x4e300254, 0x00340034}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0x94}, - {0x02, 0x9}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 1, - }, -}; - -/* PHY Initialize Configuration */ -static struct dram_cfg_param ddr_ddrphy_cfg[] = { - {0x100a0, 0x4}, - {0x100a1, 0x5}, - {0x100a2, 0x6}, - {0x100a3, 0x7}, - {0x100a4, 0x0}, - {0x100a5, 0x1}, - {0x100a6, 0x2}, - {0x100a7, 0x3}, - {0x110a0, 0x3}, - {0x110a1, 0x2}, - {0x110a2, 0x0}, - {0x110a3, 0x1}, - {0x110a4, 0x7}, - {0x110a5, 0x6}, - {0x110a6, 0x4}, - {0x110a7, 0x5}, - {0x1005f, 0x1ff}, - {0x1015f, 0x1ff}, - {0x1105f, 0x1ff}, - {0x1115f, 0x1ff}, - {0x11005f, 0x1ff}, - {0x11015f, 0x1ff}, - {0x11105f, 0x1ff}, - {0x11115f, 0x1ff}, - {0x21005f, 0x1ff}, - {0x21015f, 0x1ff}, - {0x21105f, 0x1ff}, - {0x21115f, 0x1ff}, - {0x55, 0x1ff}, - {0x1055, 0x1ff}, - {0x2055, 0x1ff}, - {0x200c5, 0xa}, - {0x1200c5, 0x2}, - {0x2200c5, 0x7}, - {0x2002e, 0x2}, - {0x12002e, 0x1}, - {0x22002e, 0x2}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x1e3}, - {0x2003a, 0x2}, - {0x2007d, 0x212}, - {0x2007c, 0x61}, - {0x120024, 0x1e3}, - {0x2003a, 0x2}, - {0x12007d, 0x212}, - {0x12007c, 0x61}, - {0x220024, 0x1e3}, - {0x2003a, 0x2}, - {0x22007d, 0x212}, - {0x22007c, 0x61}, - {0x20056, 0x3}, - {0x120056, 0x3}, - {0x220056, 0x3}, - {0x1004d, 0x600}, - {0x1014d, 0x600}, - {0x1104d, 0x600}, - {0x1114d, 0x600}, - {0x11004d, 0x600}, - {0x11014d, 0x600}, - {0x11104d, 0x600}, - {0x11114d, 0x600}, - {0x21004d, 0x600}, - {0x21014d, 0x600}, - {0x21104d, 0x600}, - {0x21114d, 0x600}, - {0x10049, 0xe3f}, - {0x10149, 0xe3f}, - {0x11049, 0xe3f}, - {0x11149, 0xe3f}, - {0x110049, 0xe3f}, - {0x110149, 0xe3f}, - {0x111049, 0xe3f}, - {0x111149, 0xe3f}, - {0x210049, 0xe3f}, - {0x210149, 0xe3f}, - {0x211049, 0xe3f}, - {0x211149, 0xe3f}, - {0x43, 0x7f}, - {0x1043, 0x7f}, - {0x2043, 0x7f}, - {0x20018, 0x1}, - {0x20075, 0x4}, - {0x20050, 0x11}, - {0x2009b, 0x2}, - {0x20008, 0x258}, - {0x120008, 0x12c}, - {0x220008, 0x9c}, - {0x20088, 0x9}, - {0x200b2, 0x10c}, - {0x10043, 0x5a1}, - {0x10143, 0x5a1}, - {0x11043, 0x5a1}, - {0x11143, 0x5a1}, - {0x1200b2, 0x10c}, - {0x110043, 0x5a1}, - {0x110143, 0x5a1}, - {0x111043, 0x5a1}, - {0x111143, 0x5a1}, - {0x2200b2, 0x10c}, - {0x210043, 0x5a1}, - {0x210143, 0x5a1}, - {0x211043, 0x5a1}, - {0x211143, 0x5a1}, - {0x200fa, 0x2}, - {0x1200fa, 0x2}, - {0x2200fa, 0x2}, - {0x20019, 0x1}, - {0x120019, 0x1}, - {0x220019, 0x1}, - {0x200f0, 0x600}, - {0x200f1, 0x0}, - {0x200f2, 0x4444}, - {0x200f3, 0x8888}, - {0x200f4, 0x5655}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0xf000}, - {0x1004a, 0x500}, - {0x1104a, 0x500}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0x20021, 0x0}, - {0x200c7, 0x21}, - {0x1200c7, 0x41}, - {0x200ca, 0x24}, - {0x1200ca, 0x24}, -}; - -/* PHY trained csr */ -static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - {0x1005f, 0x0}, - {0x1015f, 0x0}, - {0x1105f, 0x0}, - {0x1115f, 0x0}, - {0x11005f, 0x0}, - {0x11015f, 0x0}, - {0x11105f, 0x0}, - {0x11115f, 0x0}, - {0x21005f, 0x0}, - {0x21015f, 0x0}, - {0x21105f, 0x0}, - {0x21115f, 0x0}, - {0x55, 0x0}, - {0x1055, 0x0}, - {0x2055, 0x0}, - {0x200c5, 0x0}, - {0x1200c5, 0x0}, - {0x2200c5, 0x0}, - {0x2002e, 0x0}, - {0x12002e, 0x0}, - {0x22002e, 0x0}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x0}, - {0x2003a, 0x0}, - {0x2007d, 0x0}, - {0x2007c, 0x0}, - {0x120024, 0x0}, - {0x12007d, 0x0}, - {0x12007c, 0x0}, - {0x220024, 0x0}, - {0x22007d, 0x0}, - {0x22007c, 0x0}, - {0x20056, 0x0}, - {0x120056, 0x0}, - {0x220056, 0x0}, - {0x1004d, 0x0}, - {0x1014d, 0x0}, - {0x1104d, 0x0}, - {0x1114d, 0x0}, - {0x11004d, 0x0}, - {0x11014d, 0x0}, - {0x11104d, 0x0}, - {0x11114d, 0x0}, - {0x21004d, 0x0}, - {0x21014d, 0x0}, - {0x21104d, 0x0}, - {0x21114d, 0x0}, - {0x10049, 0x0}, - {0x10149, 0x0}, - {0x11049, 0x0}, - {0x11149, 0x0}, - {0x110049, 0x0}, - {0x110149, 0x0}, - {0x111049, 0x0}, - {0x111149, 0x0}, - {0x210049, 0x0}, - {0x210149, 0x0}, - {0x211049, 0x0}, - {0x211149, 0x0}, - {0x43, 0x0}, - {0x1043, 0x0}, - {0x2043, 0x0}, - {0x20018, 0x0}, - {0x20075, 0x0}, - {0x20050, 0x0}, - {0x2009b, 0x0}, - {0x20008, 0x0}, - {0x120008, 0x0}, - {0x220008, 0x0}, - {0x20088, 0x0}, - {0x200b2, 0x0}, - {0x10043, 0x0}, - {0x10143, 0x0}, - {0x11043, 0x0}, - {0x11143, 0x0}, - {0x1200b2, 0x0}, - {0x110043, 0x0}, - {0x110143, 0x0}, - {0x111043, 0x0}, - {0x111143, 0x0}, - {0x2200b2, 0x0}, - {0x210043, 0x0}, - {0x210143, 0x0}, - {0x211043, 0x0}, - {0x211143, 0x0}, - {0x200fa, 0x0}, - {0x1200fa, 0x0}, - {0x2200fa, 0x0}, - {0x20019, 0x0}, - {0x120019, 0x0}, - {0x220019, 0x0}, - {0x200f0, 0x0}, - {0x200f1, 0x0}, - {0x200f2, 0x0}, - {0x200f3, 0x0}, - {0x200f4, 0x0}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0x0}, - {0x1004a, 0x0}, - {0x1104a, 0x0}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0xd0000, 0x0}, - {0x90000, 0x0}, - {0x90001, 0x0}, - {0x90002, 0x0}, - {0x90003, 0x0}, - {0x90004, 0x0}, - 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{0x116c0, 0x0}, - {0x116c1, 0x0}, - {0x117c0, 0x0}, - {0x117c1, 0x0}, - {0x118c0, 0x0}, - {0x118c1, 0x0}, - {0x110ae, 0x0}, - {0x110af, 0x0}, - {0x90201, 0x0}, - {0x90202, 0x0}, - {0x90203, 0x0}, - {0x90205, 0x0}, - {0x90206, 0x0}, - {0x90207, 0x0}, - {0x90208, 0x0}, - {0x20020, 0x0}, - {0x100080, 0x0}, - {0x101080, 0x0}, - {0x102080, 0x0}, - {0x110020, 0x0}, - {0x110080, 0x0}, - {0x110081, 0x0}, - {0x1100d0, 0x0}, - {0x1100d1, 0x0}, - {0x11008c, 0x0}, - {0x11008d, 0x0}, - {0x110180, 0x0}, - {0x110181, 0x0}, - {0x1101d0, 0x0}, - {0x1101d1, 0x0}, - {0x11018c, 0x0}, - {0x11018d, 0x0}, - {0x1100c0, 0x0}, - {0x1100c1, 0x0}, - {0x1101c0, 0x0}, - {0x1101c1, 0x0}, - {0x1102c0, 0x0}, - {0x1102c1, 0x0}, - {0x1103c0, 0x0}, - {0x1103c1, 0x0}, - {0x1104c0, 0x0}, - {0x1104c1, 0x0}, - {0x1105c0, 0x0}, - {0x1105c1, 0x0}, - {0x1106c0, 0x0}, - {0x1106c1, 0x0}, - {0x1107c0, 0x0}, - {0x1107c1, 0x0}, - {0x1108c0, 0x0}, - {0x1108c1, 0x0}, - {0x1100ae, 0x0}, - {0x1100af, 0x0}, - {0x111020, 0x0}, - {0x111080, 0x0}, - {0x111081, 0x0}, - {0x1110d0, 0x0}, - {0x1110d1, 0x0}, - {0x11108c, 0x0}, - {0x11108d, 0x0}, - {0x111180, 0x0}, - {0x111181, 0x0}, - {0x1111d0, 0x0}, - {0x1111d1, 0x0}, - {0x11118c, 0x0}, - {0x11118d, 0x0}, - {0x1110c0, 0x0}, - {0x1110c1, 0x0}, - {0x1111c0, 0x0}, - {0x1111c1, 0x0}, - {0x1112c0, 0x0}, - {0x1112c1, 0x0}, - {0x1113c0, 0x0}, - {0x1113c1, 0x0}, - {0x1114c0, 0x0}, - {0x1114c1, 0x0}, - {0x1115c0, 0x0}, - {0x1115c1, 0x0}, - {0x1116c0, 0x0}, - {0x1116c1, 0x0}, - {0x1117c0, 0x0}, - {0x1117c1, 0x0}, - {0x1118c0, 0x0}, - {0x1118c1, 0x0}, - {0x1110ae, 0x0}, - {0x1110af, 0x0}, - {0x190201, 0x0}, - {0x190202, 0x0}, - {0x190203, 0x0}, - {0x190205, 0x0}, - {0x190206, 0x0}, - {0x190207, 0x0}, - {0x190208, 0x0}, - {0x120020, 0x0}, - {0x200080, 0x0}, - {0x201080, 0x0}, - {0x202080, 0x0}, - {0x210020, 0x0}, - {0x210080, 0x0}, - {0x210081, 0x0}, - {0x2100d0, 0x0}, - {0x2100d1, 0x0}, - {0x21008c, 0x0}, - {0x21008d, 0x0}, - {0x210180, 0x0}, - {0x210181, 0x0}, - {0x2101d0, 0x0}, - {0x2101d1, 0x0}, - {0x21018c, 0x0}, - {0x21018d, 0x0}, - {0x2100c0, 0x0}, - {0x2100c1, 0x0}, - {0x2101c0, 0x0}, - {0x2101c1, 0x0}, - {0x2102c0, 0x0}, - {0x2102c1, 0x0}, - {0x2103c0, 0x0}, - {0x2103c1, 0x0}, - {0x2104c0, 0x0}, - {0x2104c1, 0x0}, - {0x2105c0, 0x0}, - {0x2105c1, 0x0}, - {0x2106c0, 0x0}, - {0x2106c1, 0x0}, - {0x2107c0, 0x0}, - {0x2107c1, 0x0}, - {0x2108c0, 0x0}, - {0x2108c1, 0x0}, - {0x2100ae, 0x0}, - {0x2100af, 0x0}, - {0x211020, 0x0}, - {0x211080, 0x0}, - {0x211081, 0x0}, - {0x2110d0, 0x0}, - {0x2110d1, 0x0}, - {0x21108c, 0x0}, - {0x21108d, 0x0}, - {0x211180, 0x0}, - {0x211181, 0x0}, - {0x2111d0, 0x0}, - {0x2111d1, 0x0}, - {0x21118c, 0x0}, - {0x21118d, 0x0}, - {0x2110c0, 0x0}, - {0x2110c1, 0x0}, - {0x2111c0, 0x0}, - {0x2111c1, 0x0}, - {0x2112c0, 0x0}, - {0x2112c1, 0x0}, - {0x2113c0, 0x0}, - {0x2113c1, 0x0}, - {0x2114c0, 0x0}, - {0x2114c1, 0x0}, - {0x2115c0, 0x0}, - {0x2115c1, 0x0}, - {0x2116c0, 0x0}, - {0x2116c1, 0x0}, - {0x2117c0, 0x0}, - {0x2117c1, 0x0}, - {0x2118c0, 0x0}, - {0x2118c1, 0x0}, - {0x2110ae, 0x0}, - {0x2110af, 0x0}, - {0x290201, 0x0}, - {0x290202, 0x0}, - {0x290203, 0x0}, - {0x290205, 0x0}, - {0x290206, 0x0}, - {0x290207, 0x0}, - {0x290208, 0x0}, - {0x220020, 0x0}, - {0x20077, 0x0}, - {0x20072, 0x0}, - {0x20073, 0x0}, - {0x400c0, 0x0}, - {0x10040, 0x0}, - {0x10140, 0x0}, - {0x10240, 0x0}, - {0x10340, 0x0}, - {0x10440, 0x0}, - {0x10540, 0x0}, - {0x10640, 0x0}, - {0x10740, 0x0}, - {0x10840, 0x0}, - {0x11040, 0x0}, - {0x11140, 0x0}, - {0x11240, 0x0}, - {0x11340, 0x0}, - {0x11440, 0x0}, - {0x11540, 0x0}, - {0x11640, 0x0}, - {0x11740, 0x0}, - {0x11840, 0x0}, -}; - -/* P0 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0x960}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x131f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x24c4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x24c4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xc400}, - {0x54033, 0x3324}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xc400}, - {0x54039, 0x3324}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P1 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp1_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x1}, - {0x54003, 0x4b0}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x52a4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x52a4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xa400}, - {0x54033, 0x3352}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xa400}, - {0x54039, 0x3352}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P2 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp2_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x102}, - {0x54003, 0x270}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x994}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4800}, - {0x5401e, 0x4}, - {0x5401f, 0x994}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4800}, - {0x54024, 0x4}, - {0x54032, 0x9400}, - {0x54033, 0x3309}, - {0x54034, 0x4600}, - {0x54035, 0x11}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0x9400}, - {0x54039, 0x3309}, - {0x5403a, 0x4600}, - {0x5403b, 0x11}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P0 2D message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0x960}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x61}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54010, 0x2080}, - {0x54012, 0x110}, - {0x54019, 0x24c4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x24c4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xc400}, - {0x54033, 0x3324}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xc400}, - {0x54039, 0x3324}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* DRAM PHY init engine image */ -static struct dram_cfg_param ddr_phy_pie[] = { - {0xd0000, 0x0}, - {0x90000, 0x10}, - {0x90001, 0x400}, - {0x90002, 0x10e}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x8}, - {0x90029, 0xb}, - {0x9002a, 0x480}, - {0x9002b, 0x109}, - {0x9002c, 0x8}, - {0x9002d, 0x448}, - {0x9002e, 0x139}, - {0x9002f, 0x8}, - {0x90030, 0x478}, - {0x90031, 0x109}, - {0x90032, 0x0}, - {0x90033, 0xe8}, - {0x90034, 0x109}, - {0x90035, 0x2}, - {0x90036, 0x10}, - {0x90037, 0x139}, - {0x90038, 0xb}, - {0x90039, 0x7c0}, - {0x9003a, 0x139}, - {0x9003b, 0x44}, - {0x9003c, 0x633}, - {0x9003d, 0x159}, - {0x9003e, 0x14f}, - {0x9003f, 0x630}, - {0x90040, 0x159}, - {0x90041, 0x47}, - {0x90042, 0x633}, - {0x90043, 0x149}, - {0x90044, 0x4f}, - {0x90045, 0x633}, - {0x90046, 0x179}, - {0x90047, 0x8}, - {0x90048, 0xe0}, - {0x90049, 0x109}, - {0x9004a, 0x0}, - {0x9004b, 0x7c8}, - {0x9004c, 0x109}, - {0x9004d, 0x0}, - {0x9004e, 0x1}, - {0x9004f, 0x8}, - {0x90050, 0x30}, - {0x90051, 0x65a}, - {0x90052, 0x9}, - {0x90053, 0x0}, - {0x90054, 0x45a}, - {0x90055, 0x9}, - {0x90056, 0x0}, - {0x90057, 0x448}, - {0x90058, 0x109}, - {0x90059, 0x40}, - {0x9005a, 0x633}, - {0x9005b, 0x179}, - {0x9005c, 0x1}, - {0x9005d, 0x618}, - {0x9005e, 0x109}, - {0x9005f, 0x40c0}, - {0x90060, 0x633}, - {0x90061, 0x149}, - {0x90062, 0x8}, - {0x90063, 0x4}, - {0x90064, 0x48}, - {0x90065, 0x4040}, - {0x90066, 0x633}, - {0x90067, 0x149}, - {0x90068, 0x0}, - {0x90069, 0x4}, - {0x9006a, 0x48}, - {0x9006b, 0x40}, - {0x9006c, 0x633}, - {0x9006d, 0x149}, - {0x9006e, 0x0}, - {0x9006f, 0x658}, - {0x90070, 0x109}, - {0x90071, 0x10}, - {0x90072, 0x4}, - {0x90073, 0x18}, - {0x90074, 0x0}, - {0x90075, 0x4}, - {0x90076, 0x78}, - {0x90077, 0x549}, - {0x90078, 0x633}, - {0x90079, 0x159}, - {0x9007a, 0xd49}, - {0x9007b, 0x633}, - {0x9007c, 0x159}, - {0x9007d, 0x94a}, - {0x9007e, 0x633}, - {0x9007f, 0x159}, - {0x90080, 0x441}, - {0x90081, 0x633}, - {0x90082, 0x149}, - {0x90083, 0x42}, - {0x90084, 0x633}, - {0x90085, 0x149}, - {0x90086, 0x1}, - {0x90087, 0x633}, - {0x90088, 0x149}, - {0x90089, 0x0}, - {0x9008a, 0xe0}, - {0x9008b, 0x109}, - {0x9008c, 0xa}, - {0x9008d, 0x10}, - {0x9008e, 0x109}, - {0x9008f, 0x9}, - {0x90090, 0x3c0}, - {0x90091, 0x149}, - {0x90092, 0x9}, - {0x90093, 0x3c0}, - {0x90094, 0x159}, - {0x90095, 0x18}, - {0x90096, 0x10}, - {0x90097, 0x109}, - {0x90098, 0x0}, - {0x90099, 0x3c0}, - {0x9009a, 0x109}, - {0x9009b, 0x18}, - {0x9009c, 0x4}, - {0x9009d, 0x48}, - {0x9009e, 0x18}, - {0x9009f, 0x4}, - {0x900a0, 0x58}, - {0x900a1, 0xb}, - {0x900a2, 0x10}, - {0x900a3, 0x109}, - {0x900a4, 0x1}, - {0x900a5, 0x10}, - {0x900a6, 0x109}, - {0x900a7, 0x5}, - {0x900a8, 0x7c0}, - {0x900a9, 0x109}, - {0x40000, 0x811}, - {0x40020, 0x880}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x4008}, - {0x40021, 0x83}, - {0x40041, 0x4f}, - {0x40061, 0x0}, - {0x40002, 0x4040}, - {0x40022, 0x83}, - {0x40042, 0x51}, - {0x40062, 0x0}, - {0x40003, 0x811}, - {0x40023, 0x880}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x720}, - {0x40024, 0xf}, - {0x40044, 0x1740}, - {0x40064, 0x0}, - {0x40005, 0x16}, - {0x40025, 0x83}, - {0x40045, 0x4b}, - {0x40065, 0x0}, - {0x40006, 0x716}, - {0x40026, 0xf}, - {0x40046, 0x2001}, - {0x40066, 0x0}, - {0x40007, 0x716}, - {0x40027, 0xf}, - {0x40047, 0x2800}, - {0x40067, 0x0}, - {0x40008, 0x716}, - {0x40028, 0xf}, - {0x40048, 0xf00}, - {0x40068, 0x0}, - {0x40009, 0x720}, - {0x40029, 0xf}, - {0x40049, 0x1400}, - {0x40069, 0x0}, - {0x4000a, 0xe08}, - {0x4002a, 0xc15}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x625}, - {0x4002b, 0x15}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x4028}, - {0x4002c, 0x80}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0xe08}, - {0x4002d, 0xc1a}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x625}, - {0x4002e, 0x1a}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x4040}, - {0x4002f, 0x80}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x2604}, - {0x40030, 0x15}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x708}, - {0x40031, 0x5}, - {0x40051, 0x0}, - {0x40071, 0x2002}, - {0x40012, 0x8}, - {0x40032, 0x80}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x2604}, - {0x40033, 0x1a}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x708}, - {0x40034, 0xa}, - {0x40054, 0x0}, - {0x40074, 0x2002}, - {0x40015, 0x4040}, - {0x40035, 0x80}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x60a}, - {0x40036, 0x15}, - {0x40056, 0x1200}, - {0x40076, 0x0}, - {0x40017, 0x61a}, - {0x40037, 0x15}, - {0x40057, 0x1300}, - {0x40077, 0x0}, - {0x40018, 0x60a}, - {0x40038, 0x1a}, - {0x40058, 0x1200}, - {0x40078, 0x0}, - {0x40019, 0x642}, - {0x40039, 0x1a}, - {0x40059, 0x1300}, - {0x40079, 0x0}, - {0x4001a, 0x4808}, - {0x4003a, 0x880}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x790}, - {0x900ac, 0x11a}, - {0x900ad, 0x8}, - {0x900ae, 0x7aa}, - {0x900af, 0x2a}, - {0x900b0, 0x10}, - {0x900b1, 0x7b2}, - {0x900b2, 0x2a}, - {0x900b3, 0x0}, - {0x900b4, 0x7c8}, - {0x900b5, 0x109}, - {0x900b6, 0x10}, - {0x900b7, 0x10}, - {0x900b8, 0x109}, - {0x900b9, 0x10}, - {0x900ba, 0x2a8}, - {0x900bb, 0x129}, - {0x900bc, 0x8}, - {0x900bd, 0x370}, - {0x900be, 0x129}, - {0x900bf, 0xa}, - {0x900c0, 0x3c8}, - {0x900c1, 0x1a9}, - {0x900c2, 0xc}, - {0x900c3, 0x408}, - {0x900c4, 0x199}, - {0x900c5, 0x14}, - {0x900c6, 0x790}, - {0x900c7, 0x11a}, - {0x900c8, 0x8}, - {0x900c9, 0x4}, - {0x900ca, 0x18}, - {0x900cb, 0xe}, - {0x900cc, 0x408}, - {0x900cd, 0x199}, - {0x900ce, 0x8}, - {0x900cf, 0x8568}, - {0x900d0, 0x108}, - {0x900d1, 0x18}, - {0x900d2, 0x790}, - {0x900d3, 0x16a}, - {0x900d4, 0x8}, - {0x900d5, 0x1d8}, - {0x900d6, 0x169}, - {0x900d7, 0x10}, - {0x900d8, 0x8558}, - {0x900d9, 0x168}, - {0x900da, 0x1ff8}, - {0x900db, 0x85a8}, - {0x900dc, 0x1e8}, - {0x900dd, 0x50}, - {0x900de, 0x798}, - {0x900df, 0x16a}, - {0x900e0, 0x60}, - {0x900e1, 0x7a0}, - {0x900e2, 0x16a}, - {0x900e3, 0x8}, - {0x900e4, 0x8310}, - {0x900e5, 0x168}, - {0x900e6, 0x8}, - {0x900e7, 0xa310}, - {0x900e8, 0x168}, - {0x900e9, 0xa}, - {0x900ea, 0x408}, - {0x900eb, 0x169}, - {0x900ec, 0x6e}, - {0x900ed, 0x0}, - {0x900ee, 0x68}, - {0x900ef, 0x0}, - {0x900f0, 0x408}, - {0x900f1, 0x169}, - {0x900f2, 0x0}, - {0x900f3, 0x8310}, - {0x900f4, 0x168}, - {0x900f5, 0x0}, - {0x900f6, 0xa310}, - {0x900f7, 0x168}, - {0x900f8, 0x1ff8}, - {0x900f9, 0x85a8}, - {0x900fa, 0x1e8}, - {0x900fb, 0x68}, - {0x900fc, 0x798}, - {0x900fd, 0x16a}, - {0x900fe, 0x78}, - {0x900ff, 0x7a0}, - {0x90100, 0x16a}, - {0x90101, 0x68}, - {0x90102, 0x790}, - {0x90103, 0x16a}, - {0x90104, 0x8}, - {0x90105, 0x8b10}, - {0x90106, 0x168}, - {0x90107, 0x8}, - {0x90108, 0xab10}, - {0x90109, 0x168}, - {0x9010a, 0xa}, - {0x9010b, 0x408}, - {0x9010c, 0x169}, - {0x9010d, 0x58}, - {0x9010e, 0x0}, - {0x9010f, 0x68}, - {0x90110, 0x0}, - {0x90111, 0x408}, - {0x90112, 0x169}, - {0x90113, 0x0}, - {0x90114, 0x8b10}, - {0x90115, 0x168}, - {0x90116, 0x1}, - {0x90117, 0xab10}, - {0x90118, 0x168}, - {0x90119, 0x0}, - {0x9011a, 0x1d8}, - {0x9011b, 0x169}, - {0x9011c, 0x80}, - {0x9011d, 0x790}, - {0x9011e, 0x16a}, - {0x9011f, 0x18}, - {0x90120, 0x7aa}, - {0x90121, 0x6a}, - {0x90122, 0xa}, - {0x90123, 0x0}, - {0x90124, 0x1e9}, - {0x90125, 0x8}, - {0x90126, 0x8080}, - {0x90127, 0x108}, - {0x90128, 0xf}, - {0x90129, 0x408}, - {0x9012a, 0x169}, - {0x9012b, 0xc}, - {0x9012c, 0x0}, - {0x9012d, 0x68}, - {0x9012e, 0x9}, - {0x9012f, 0x0}, - {0x90130, 0x1a9}, - {0x90131, 0x0}, - {0x90132, 0x408}, - {0x90133, 0x169}, - {0x90134, 0x0}, - {0x90135, 0x8080}, - {0x90136, 0x108}, - {0x90137, 0x8}, - {0x90138, 0x7aa}, - {0x90139, 0x6a}, - {0x9013a, 0x0}, - {0x9013b, 0x8568}, - {0x9013c, 0x108}, - {0x9013d, 0xb7}, - {0x9013e, 0x790}, - {0x9013f, 0x16a}, - {0x90140, 0x1f}, - {0x90141, 0x0}, - {0x90142, 0x68}, - {0x90143, 0x8}, - {0x90144, 0x8558}, - {0x90145, 0x168}, - {0x90146, 0xf}, - {0x90147, 0x408}, - {0x90148, 0x169}, - {0x90149, 0xd}, - {0x9014a, 0x0}, - {0x9014b, 0x68}, - {0x9014c, 0x0}, - {0x9014d, 0x408}, - {0x9014e, 0x169}, - {0x9014f, 0x0}, - {0x90150, 0x8558}, - {0x90151, 0x168}, - {0x90152, 0x8}, - {0x90153, 0x3c8}, - {0x90154, 0x1a9}, - {0x90155, 0x3}, - {0x90156, 0x370}, - {0x90157, 0x129}, - {0x90158, 0x20}, - {0x90159, 0x2aa}, - {0x9015a, 0x9}, - {0x9015b, 0x8}, - {0x9015c, 0xe8}, - {0x9015d, 0x109}, - {0x9015e, 0x0}, - {0x9015f, 0x8140}, - {0x90160, 0x10c}, - {0x90161, 0x10}, - {0x90162, 0x8138}, - {0x90163, 0x104}, - {0x90164, 0x8}, - {0x90165, 0x448}, - {0x90166, 0x109}, - {0x90167, 0xf}, - {0x90168, 0x7c0}, - {0x90169, 0x109}, - {0x9016a, 0x0}, - {0x9016b, 0xe8}, - {0x9016c, 0x109}, - {0x9016d, 0x47}, - {0x9016e, 0x630}, - {0x9016f, 0x109}, - {0x90170, 0x8}, - {0x90171, 0x618}, - {0x90172, 0x109}, - {0x90173, 0x8}, - {0x90174, 0xe0}, - {0x90175, 0x109}, - {0x90176, 0x0}, - {0x90177, 0x7c8}, - {0x90178, 0x109}, - {0x90179, 0x8}, - {0x9017a, 0x8140}, - {0x9017b, 0x10c}, - {0x9017c, 0x0}, - {0x9017d, 0x478}, - {0x9017e, 0x109}, - {0x9017f, 0x0}, - {0x90180, 0x1}, - {0x90181, 0x8}, - {0x90182, 0x8}, - {0x90183, 0x4}, - {0x90184, 0x0}, - {0x90006, 0x8}, - {0x90007, 0x7c8}, - {0x90008, 0x109}, - {0x90009, 0x0}, - {0x9000a, 0x400}, - {0x9000b, 0x106}, - {0xd00e7, 0x400}, - {0x90017, 0x0}, - {0x9001f, 0x2b}, - {0x90026, 0x69}, - {0x400d0, 0x0}, - {0x400d1, 0x101}, - {0x400d2, 0x105}, - {0x400d3, 0x107}, - {0x400d4, 0x10f}, - {0x400d5, 0x202}, - {0x400d6, 0x20a}, - {0x400d7, 0x20b}, - {0x2003a, 0x2}, - {0x200be, 0x3}, - {0x2000b, 0x2a3}, - {0x2000c, 0x96}, - {0x2000d, 0x5dc}, - {0x2000e, 0x2c}, - {0x12000b, 0x152}, - {0x12000c, 0x4b}, - {0x12000d, 0x2ee}, - {0x12000e, 0x2c}, - {0x22000b, 0xb0}, - {0x22000c, 0x27}, - {0x22000d, 0x186}, - {0x22000e, 0x10}, - {0x9000c, 0x0}, - {0x9000d, 0x173}, - {0x9000e, 0x60}, - {0x9000f, 0x6110}, - {0x90010, 0x2152}, - {0x90011, 0xdfbd}, - {0x90012, 0x2060}, - {0x90013, 0x6152}, - {0x20010, 0x5a}, - {0x20011, 0x3}, - {0x120010, 0x5a}, - {0x120011, 0x3}, - {0x40080, 0xe0}, - {0x40081, 0x12}, - {0x40082, 0xe0}, - {0x40083, 0x12}, - {0x40084, 0xe0}, - {0x40085, 0x12}, - {0x140080, 0xe0}, - {0x140081, 0x12}, - {0x140082, 0xe0}, - {0x140083, 0x12}, - {0x140084, 0xe0}, - {0x140085, 0x12}, - {0x240080, 0xe0}, - {0x240081, 0x12}, - {0x240082, 0xe0}, - {0x240083, 0x12}, - {0x240084, 0xe0}, - {0x240085, 0x12}, - {0x400fd, 0xf}, - {0x400f1, 0xe}, - {0x10011, 0x1}, - {0x10012, 0x1}, - {0x10013, 0x180}, - {0x10018, 0x1}, - {0x10002, 0x6209}, - {0x100b2, 0x1}, - {0x101b4, 0x1}, - {0x102b4, 0x1}, - {0x103b4, 0x1}, - {0x104b4, 0x1}, - {0x105b4, 0x1}, - {0x106b4, 0x1}, - {0x107b4, 0x1}, - {0x108b4, 0x1}, - {0x11011, 0x1}, - {0x11012, 0x1}, - {0x11013, 0x180}, - {0x11018, 0x1}, - {0x11002, 0x6209}, - {0x110b2, 0x1}, - {0x111b4, 0x1}, - {0x112b4, 0x1}, - {0x113b4, 0x1}, - {0x114b4, 0x1}, - {0x115b4, 0x1}, - {0x116b4, 0x1}, - {0x117b4, 0x1}, - {0x118b4, 0x1}, - {0x20089, 0x1}, - {0x20088, 0x19}, - {0xc0080, 0x0}, - {0xd0000, 0x1}, -}; - -static struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 2400mts 1D */ - .drate = 2400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 1200mts 1D */ - .drate = 1200, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 625mts 1D */ - .drate = 625, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 2400mts 2D */ - .drate = 2400, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 2400, 1200, 625, }, - .fsp_cfg = ddr_dram_fsp_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), -}; diff --git a/board/freescale/imx91_evk/lpddr4_timing_2400mts_ecc.c b/board/freescale/imx91_evk/lpddr4_timing_2400mts_ecc.c deleted file mode 100644 index 811687170c3..00000000000 --- a/board/freescale/imx91_evk/lpddr4_timing_2400mts_ecc.c +++ /dev/null @@ -1,1995 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright 2024 NXP - * - * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3. - * DDR PHY FW2022.01 - */ - -#include -#include - -/* Initialize DDRC registers */ -static struct dram_cfg_param ddr_ddrc_cfg[] = { - {0x4e300110, 0x44100001}, - {0x4e300000, 0x8000ef}, - {0x4e300008, 0x0}, - {0x4e300080, 0x80000512}, - {0x4e300084, 0x0}, - {0x4e300114, 0x1012}, - {0x4e300260, 0x80}, - {0x4e300f04, 0x80}, - {0x4e300800, 0x43b30d00}, - {0x4e300804, 0x1f1f1f1f}, - {0x4e301000, 0xc0000000}, - {0x4e301240, 0x0}, - {0x4e301244, 0x0}, - {0x4e301248, 0x0}, - {0x4e30124c, 0x0}, - {0x4e301250, 0x0}, - {0x4e301254, 0x0}, - {0x4e301258, 0x0}, - {0x4e30125c, 0x0}, -}; - -/* dram fsp cfg */ -static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { - { - { - {0x4e300100, 0x135C2110}, - {0x4e300104, 0xF8990011}, - {0x4e300108, 0x636E08CC}, - {0x4e30010C, 0x0061E070}, - {0x4e300124, 0x124E0000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x31D00000}, - {0x4e300170, 0x8B0B0608}, - {0x4e300250, 0x0000001A}, - {0x4e300254, 0x00DC00DC}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - {0x4e300300, 0x1633160D}, - {0x4e300304, 0x00DC180C}, - {0x4e300308, 0x0C3C0927}, - }, - { - {0x01, 0xC4}, - {0x02, 0x24}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x010D1100}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0xBABAC068}, - {0x4e30010C, 0x00610158}, - {0x4e300124, 0x09270000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30400000}, - {0x4e300170, 0x8A0A0508}, - {0x4e300250, 0x0000000D}, - {0x4e300254, 0x006A006A}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0xA4}, - {0x02, 0x52}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x00061000}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0x6E62FA48}, - {0x4e30010C, 0x0031010D}, - {0x4e300124, 0x04C50000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30000000}, - {0x4e300170, 0x89090408}, - {0x4e300250, 0x00000007}, - {0x4e300254, 0x00340034}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0x94}, - {0x02, 0x9}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 1, - }, -}; - -/* PHY Initialize Configuration */ -static struct dram_cfg_param ddr_ddrphy_cfg[] = { - {0x100a0, 0x4}, - {0x100a1, 0x5}, - {0x100a2, 0x6}, - {0x100a3, 0x7}, - {0x100a4, 0x0}, - {0x100a5, 0x1}, - {0x100a6, 0x2}, - {0x100a7, 0x3}, - {0x110a0, 0x3}, - {0x110a1, 0x2}, - {0x110a2, 0x0}, - {0x110a3, 0x1}, - {0x110a4, 0x7}, - {0x110a5, 0x6}, - {0x110a6, 0x4}, - {0x110a7, 0x5}, - {0x1005f, 0x1ff}, - {0x1015f, 0x1ff}, - {0x1105f, 0x1ff}, - {0x1115f, 0x1ff}, - {0x11005f, 0x1ff}, - {0x11015f, 0x1ff}, - {0x11105f, 0x1ff}, - {0x11115f, 0x1ff}, - {0x21005f, 0x1ff}, - {0x21015f, 0x1ff}, - {0x21105f, 0x1ff}, - {0x21115f, 0x1ff}, - {0x55, 0x1ff}, - {0x1055, 0x1ff}, - {0x2055, 0x1ff}, - {0x200c5, 0xa}, - {0x1200c5, 0x2}, - {0x2200c5, 0x7}, - {0x2002e, 0x2}, - {0x12002e, 0x1}, - {0x22002e, 0x2}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x1e3}, - {0x2003a, 0x2}, - {0x2007d, 0x212}, - {0x2007c, 0x61}, - {0x120024, 0x1e3}, - {0x2003a, 0x2}, - {0x12007d, 0x212}, - {0x12007c, 0x61}, - {0x220024, 0x1e3}, - {0x2003a, 0x2}, - {0x22007d, 0x212}, - {0x22007c, 0x61}, - {0x20056, 0x3}, - {0x120056, 0x3}, - {0x220056, 0x3}, - {0x1004d, 0x600}, - {0x1014d, 0x600}, - {0x1104d, 0x600}, - {0x1114d, 0x600}, - {0x11004d, 0x600}, - {0x11014d, 0x600}, - {0x11104d, 0x600}, - {0x11114d, 0x600}, - {0x21004d, 0x600}, - {0x21014d, 0x600}, - {0x21104d, 0x600}, - {0x21114d, 0x600}, - {0x10049, 0xe3f}, - {0x10149, 0xe3f}, - {0x11049, 0xe3f}, - {0x11149, 0xe3f}, - {0x110049, 0xe3f}, - {0x110149, 0xe3f}, - {0x111049, 0xe3f}, - {0x111149, 0xe3f}, - {0x210049, 0xe3f}, - {0x210149, 0xe3f}, - {0x211049, 0xe3f}, - {0x211149, 0xe3f}, - {0x43, 0x7f}, - {0x1043, 0x7f}, - {0x2043, 0x7f}, - {0x20018, 0x1}, - {0x20075, 0x4}, - {0x20050, 0x11}, - {0x2009b, 0x2}, - {0x20008, 0x258}, - {0x120008, 0x12c}, - {0x220008, 0x9c}, - {0x20088, 0x9}, - {0x200b2, 0x10c}, - {0x10043, 0x5a1}, - {0x10143, 0x5a1}, - {0x11043, 0x5a1}, - {0x11143, 0x5a1}, - {0x1200b2, 0x10c}, - {0x110043, 0x5a1}, - {0x110143, 0x5a1}, - {0x111043, 0x5a1}, - {0x111143, 0x5a1}, - {0x2200b2, 0x10c}, - {0x210043, 0x5a1}, - {0x210143, 0x5a1}, - {0x211043, 0x5a1}, - {0x211143, 0x5a1}, - {0x200fa, 0x2}, - {0x1200fa, 0x2}, - {0x2200fa, 0x2}, - {0x20019, 0x1}, - {0x120019, 0x1}, - {0x220019, 0x1}, - {0x200f0, 0x600}, - {0x200f1, 0x0}, - {0x200f2, 0x4444}, - {0x200f3, 0x8888}, - {0x200f4, 0x5655}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0xf000}, - {0x1004a, 0x500}, - {0x1104a, 0x500}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0x20021, 0x0}, - {0x200c7, 0x21}, - {0x1200c7, 0x41}, - {0x200ca, 0x24}, - {0x1200ca, 0x24}, -}; - -/* PHY trained csr */ -static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - {0x1005f, 0x0}, - {0x1015f, 0x0}, - {0x1105f, 0x0}, - {0x1115f, 0x0}, - {0x11005f, 0x0}, - {0x11015f, 0x0}, - {0x11105f, 0x0}, - {0x11115f, 0x0}, - {0x21005f, 0x0}, - {0x21015f, 0x0}, - {0x21105f, 0x0}, - {0x21115f, 0x0}, - {0x55, 0x0}, - {0x1055, 0x0}, - {0x2055, 0x0}, - {0x200c5, 0x0}, - {0x1200c5, 0x0}, - {0x2200c5, 0x0}, - {0x2002e, 0x0}, - {0x12002e, 0x0}, - {0x22002e, 0x0}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x0}, - {0x2003a, 0x0}, - {0x2007d, 0x0}, - {0x2007c, 0x0}, - {0x120024, 0x0}, - {0x12007d, 0x0}, - {0x12007c, 0x0}, - {0x220024, 0x0}, - {0x22007d, 0x0}, - {0x22007c, 0x0}, - {0x20056, 0x0}, - {0x120056, 0x0}, - {0x220056, 0x0}, - {0x1004d, 0x0}, - {0x1014d, 0x0}, - {0x1104d, 0x0}, - {0x1114d, 0x0}, - {0x11004d, 0x0}, - {0x11014d, 0x0}, - {0x11104d, 0x0}, - {0x11114d, 0x0}, - {0x21004d, 0x0}, - {0x21014d, 0x0}, - {0x21104d, 0x0}, - {0x21114d, 0x0}, - {0x10049, 0x0}, - {0x10149, 0x0}, - {0x11049, 0x0}, - {0x11149, 0x0}, - {0x110049, 0x0}, - {0x110149, 0x0}, - {0x111049, 0x0}, - {0x111149, 0x0}, - {0x210049, 0x0}, - {0x210149, 0x0}, - {0x211049, 0x0}, - {0x211149, 0x0}, - {0x43, 0x0}, - {0x1043, 0x0}, - {0x2043, 0x0}, - {0x20018, 0x0}, - {0x20075, 0x0}, - {0x20050, 0x0}, - {0x2009b, 0x0}, - {0x20008, 0x0}, - {0x120008, 0x0}, - {0x220008, 0x0}, - {0x20088, 0x0}, - {0x200b2, 0x0}, - {0x10043, 0x0}, - {0x10143, 0x0}, - {0x11043, 0x0}, - {0x11143, 0x0}, - {0x1200b2, 0x0}, - {0x110043, 0x0}, - {0x110143, 0x0}, - {0x111043, 0x0}, - {0x111143, 0x0}, - {0x2200b2, 0x0}, - {0x210043, 0x0}, - {0x210143, 0x0}, - {0x211043, 0x0}, - {0x211143, 0x0}, - {0x200fa, 0x0}, - {0x1200fa, 0x0}, - {0x2200fa, 0x0}, - {0x20019, 0x0}, - {0x120019, 0x0}, - {0x220019, 0x0}, - {0x200f0, 0x0}, - {0x200f1, 0x0}, - {0x200f2, 0x0}, - {0x200f3, 0x0}, - {0x200f4, 0x0}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0x0}, - {0x1004a, 0x0}, - {0x1104a, 0x0}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0xd0000, 0x0}, - {0x90000, 0x0}, - {0x90001, 0x0}, - {0x90002, 0x0}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x0}, - {0x90029, 0x0}, - {0x9002a, 0x0}, - {0x9002b, 0x0}, - {0x9002c, 0x0}, - {0x9002d, 0x0}, - {0x9002e, 0x0}, - {0x9002f, 0x0}, - {0x90030, 0x0}, - {0x90031, 0x0}, - {0x90032, 0x0}, - {0x90033, 0x0}, - {0x90034, 0x0}, - {0x90035, 0x0}, - {0x90036, 0x0}, - {0x90037, 0x0}, - {0x90038, 0x0}, - {0x90039, 0x0}, - {0x9003a, 0x0}, - {0x9003b, 0x0}, - {0x9003c, 0x0}, - {0x9003d, 0x0}, - {0x9003e, 0x0}, - {0x9003f, 0x0}, - {0x90040, 0x0}, - {0x90041, 0x0}, - {0x90042, 0x0}, - {0x90043, 0x0}, - {0x90044, 0x0}, - {0x90045, 0x0}, - {0x90046, 0x0}, - {0x90047, 0x0}, - {0x90048, 0x0}, - {0x90049, 0x0}, - {0x9004a, 0x0}, - {0x9004b, 0x0}, - {0x9004c, 0x0}, - {0x9004d, 0x0}, - {0x9004e, 0x0}, - {0x9004f, 0x0}, - {0x90050, 0x0}, - {0x90051, 0x0}, - {0x90052, 0x0}, - {0x90053, 0x0}, - {0x90054, 0x0}, - {0x90055, 0x0}, - {0x90056, 0x0}, - {0x90057, 0x0}, - {0x90058, 0x0}, - {0x90059, 0x0}, - {0x9005a, 0x0}, - {0x9005b, 0x0}, - {0x9005c, 0x0}, - {0x9005d, 0x0}, - {0x9005e, 0x0}, - {0x9005f, 0x0}, - {0x90060, 0x0}, - {0x90061, 0x0}, - {0x90062, 0x0}, - {0x90063, 0x0}, - {0x90064, 0x0}, - {0x90065, 0x0}, - {0x90066, 0x0}, - {0x90067, 0x0}, - {0x90068, 0x0}, - {0x90069, 0x0}, - {0x9006a, 0x0}, - {0x9006b, 0x0}, - {0x9006c, 0x0}, - {0x9006d, 0x0}, - {0x9006e, 0x0}, - {0x9006f, 0x0}, - {0x90070, 0x0}, - {0x90071, 0x0}, - {0x90072, 0x0}, - {0x90073, 0x0}, - {0x90074, 0x0}, - {0x90075, 0x0}, - {0x90076, 0x0}, - {0x90077, 0x0}, - {0x90078, 0x0}, - {0x90079, 0x0}, - {0x9007a, 0x0}, - {0x9007b, 0x0}, - {0x9007c, 0x0}, - {0x9007d, 0x0}, - {0x9007e, 0x0}, - {0x9007f, 0x0}, - {0x90080, 0x0}, - {0x90081, 0x0}, - {0x90082, 0x0}, - {0x90083, 0x0}, - {0x90084, 0x0}, - {0x90085, 0x0}, - {0x90086, 0x0}, - {0x90087, 0x0}, - {0x90088, 0x0}, - {0x90089, 0x0}, - {0x9008a, 0x0}, - {0x9008b, 0x0}, - {0x9008c, 0x0}, - {0x9008d, 0x0}, - {0x9008e, 0x0}, - {0x9008f, 0x0}, - {0x90090, 0x0}, - {0x90091, 0x0}, - {0x90092, 0x0}, - {0x90093, 0x0}, - {0x90094, 0x0}, - {0x90095, 0x0}, - {0x90096, 0x0}, - {0x90097, 0x0}, - {0x90098, 0x0}, - {0x90099, 0x0}, - {0x9009a, 0x0}, - {0x9009b, 0x0}, - {0x9009c, 0x0}, - {0x9009d, 0x0}, - {0x9009e, 0x0}, - {0x9009f, 0x0}, - {0x900a0, 0x0}, - {0x900a1, 0x0}, - {0x900a2, 0x0}, - {0x900a3, 0x0}, - {0x900a4, 0x0}, - {0x900a5, 0x0}, - {0x900a6, 0x0}, - {0x900a7, 0x0}, - {0x900a8, 0x0}, - {0x900a9, 0x0}, - {0x40000, 0x0}, - {0x40020, 0x0}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x0}, - {0x40021, 0x0}, - {0x40041, 0x0}, - {0x40061, 0x0}, - {0x40002, 0x0}, - {0x40022, 0x0}, - {0x40042, 0x0}, - {0x40062, 0x0}, - {0x40003, 0x0}, - {0x40023, 0x0}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x0}, - {0x40024, 0x0}, - {0x40044, 0x0}, - {0x40064, 0x0}, - {0x40005, 0x0}, - {0x40025, 0x0}, - {0x40045, 0x0}, - {0x40065, 0x0}, - {0x40006, 0x0}, - {0x40026, 0x0}, - {0x40046, 0x0}, - {0x40066, 0x0}, - {0x40007, 0x0}, - {0x40027, 0x0}, - {0x40047, 0x0}, - {0x40067, 0x0}, - {0x40008, 0x0}, - {0x40028, 0x0}, - {0x40048, 0x0}, - {0x40068, 0x0}, - {0x40009, 0x0}, - {0x40029, 0x0}, - {0x40049, 0x0}, - {0x40069, 0x0}, - {0x4000a, 0x0}, - {0x4002a, 0x0}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x0}, - {0x4002b, 0x0}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x0}, - {0x4002c, 0x0}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0x0}, - {0x4002d, 0x0}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x0}, - {0x4002e, 0x0}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x0}, - {0x4002f, 0x0}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x0}, - {0x40030, 0x0}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x0}, - {0x40031, 0x0}, - {0x40051, 0x0}, - {0x40071, 0x0}, - {0x40012, 0x0}, - {0x40032, 0x0}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x0}, - {0x40033, 0x0}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x0}, - {0x40034, 0x0}, - {0x40054, 0x0}, - {0x40074, 0x0}, - {0x40015, 0x0}, - {0x40035, 0x0}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x0}, - {0x40036, 0x0}, - {0x40056, 0x0}, - {0x40076, 0x0}, - {0x40017, 0x0}, - {0x40037, 0x0}, - {0x40057, 0x0}, - {0x40077, 0x0}, - {0x40018, 0x0}, - {0x40038, 0x0}, - {0x40058, 0x0}, - {0x40078, 0x0}, - {0x40019, 0x0}, - {0x40039, 0x0}, - {0x40059, 0x0}, - {0x40079, 0x0}, - {0x4001a, 0x0}, - {0x4003a, 0x0}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x0}, - {0x900ac, 0x0}, - {0x900ad, 0x0}, - {0x900ae, 0x0}, - {0x900af, 0x0}, - {0x900b0, 0x0}, - {0x900b1, 0x0}, - {0x900b2, 0x0}, - {0x900b3, 0x0}, - {0x900b4, 0x0}, - {0x900b5, 0x0}, - {0x900b6, 0x0}, - {0x900b7, 0x0}, - {0x900b8, 0x0}, - {0x900b9, 0x0}, - {0x900ba, 0x0}, - {0x900bb, 0x0}, - {0x900bc, 0x0}, - {0x900bd, 0x0}, - {0x900be, 0x0}, - {0x900bf, 0x0}, - {0x900c0, 0x0}, - {0x900c1, 0x0}, - {0x900c2, 0x0}, - {0x900c3, 0x0}, - {0x900c4, 0x0}, - {0x900c5, 0x0}, - {0x900c6, 0x0}, - {0x900c7, 0x0}, - {0x900c8, 0x0}, - {0x900c9, 0x0}, - {0x900ca, 0x0}, - {0x900cb, 0x0}, - {0x900cc, 0x0}, - {0x900cd, 0x0}, - {0x900ce, 0x0}, - {0x900cf, 0x0}, - {0x900d0, 0x0}, - {0x900d1, 0x0}, - {0x900d2, 0x0}, - {0x900d3, 0x0}, - {0x900d4, 0x0}, - {0x900d5, 0x0}, - {0x900d6, 0x0}, - {0x900d7, 0x0}, - {0x900d8, 0x0}, - {0x900d9, 0x0}, - {0x900da, 0x0}, - {0x900db, 0x0}, - {0x900dc, 0x0}, - {0x900dd, 0x0}, - {0x900de, 0x0}, - {0x900df, 0x0}, - {0x900e0, 0x0}, - {0x900e1, 0x0}, - {0x900e2, 0x0}, - {0x900e3, 0x0}, - {0x900e4, 0x0}, - {0x900e5, 0x0}, - {0x900e6, 0x0}, - {0x900e7, 0x0}, - {0x900e8, 0x0}, - {0x900e9, 0x0}, - {0x900ea, 0x0}, - {0x900eb, 0x0}, - {0x900ec, 0x0}, - {0x900ed, 0x0}, - {0x900ee, 0x0}, - {0x900ef, 0x0}, - {0x900f0, 0x0}, - {0x900f1, 0x0}, - {0x900f2, 0x0}, - {0x900f3, 0x0}, - {0x900f4, 0x0}, - {0x900f5, 0x0}, - {0x900f6, 0x0}, - {0x900f7, 0x0}, - {0x900f8, 0x0}, - {0x900f9, 0x0}, - {0x900fa, 0x0}, - {0x900fb, 0x0}, - {0x900fc, 0x0}, - {0x900fd, 0x0}, - {0x900fe, 0x0}, - {0x900ff, 0x0}, - {0x90100, 0x0}, - {0x90101, 0x0}, - {0x90102, 0x0}, - {0x90103, 0x0}, - {0x90104, 0x0}, - {0x90105, 0x0}, - {0x90106, 0x0}, - {0x90107, 0x0}, - {0x90108, 0x0}, - {0x90109, 0x0}, - {0x9010a, 0x0}, - {0x9010b, 0x0}, - {0x9010c, 0x0}, - {0x9010d, 0x0}, - {0x9010e, 0x0}, - {0x9010f, 0x0}, - {0x90110, 0x0}, - {0x90111, 0x0}, - {0x90112, 0x0}, - {0x90113, 0x0}, - {0x90114, 0x0}, - {0x90115, 0x0}, - {0x90116, 0x0}, - {0x90117, 0x0}, - {0x90118, 0x0}, - {0x90119, 0x0}, - {0x9011a, 0x0}, - {0x9011b, 0x0}, - {0x9011c, 0x0}, - {0x9011d, 0x0}, - {0x9011e, 0x0}, - {0x9011f, 0x0}, - {0x90120, 0x0}, - {0x90121, 0x0}, - {0x90122, 0x0}, - {0x90123, 0x0}, - {0x90124, 0x0}, - {0x90125, 0x0}, - {0x90126, 0x0}, - {0x90127, 0x0}, - {0x90128, 0x0}, - {0x90129, 0x0}, - {0x9012a, 0x0}, - {0x9012b, 0x0}, - {0x9012c, 0x0}, - {0x9012d, 0x0}, - {0x9012e, 0x0}, - {0x9012f, 0x0}, - {0x90130, 0x0}, - {0x90131, 0x0}, - {0x90132, 0x0}, - {0x90133, 0x0}, - {0x90134, 0x0}, - {0x90135, 0x0}, - {0x90136, 0x0}, - {0x90137, 0x0}, - {0x90138, 0x0}, - {0x90139, 0x0}, - {0x9013a, 0x0}, - {0x9013b, 0x0}, - {0x9013c, 0x0}, - {0x9013d, 0x0}, - {0x9013e, 0x0}, - {0x9013f, 0x0}, - {0x90140, 0x0}, - {0x90141, 0x0}, - {0x90142, 0x0}, - {0x90143, 0x0}, - {0x90144, 0x0}, - {0x90145, 0x0}, - {0x90146, 0x0}, - {0x90147, 0x0}, - {0x90148, 0x0}, - {0x90149, 0x0}, - {0x9014a, 0x0}, - {0x9014b, 0x0}, - {0x9014c, 0x0}, - {0x9014d, 0x0}, - {0x9014e, 0x0}, - {0x9014f, 0x0}, - {0x90150, 0x0}, - {0x90151, 0x0}, - {0x90152, 0x0}, - {0x90153, 0x0}, - {0x90154, 0x0}, - {0x90155, 0x0}, - {0x90156, 0x0}, - {0x90157, 0x0}, - {0x90158, 0x0}, - {0x90159, 0x0}, - {0x9015a, 0x0}, - {0x9015b, 0x0}, - {0x9015c, 0x0}, - {0x9015d, 0x0}, - {0x9015e, 0x0}, - {0x9015f, 0x0}, - {0x90160, 0x0}, - {0x90161, 0x0}, - {0x90162, 0x0}, - {0x90163, 0x0}, - {0x90164, 0x0}, - {0x90165, 0x0}, - {0x90166, 0x0}, - {0x90167, 0x0}, - {0x90168, 0x0}, - {0x90169, 0x0}, - {0x9016a, 0x0}, - {0x9016b, 0x0}, - {0x9016c, 0x0}, - {0x9016d, 0x0}, - {0x9016e, 0x0}, - {0x9016f, 0x0}, - {0x90170, 0x0}, - {0x90171, 0x0}, - {0x90172, 0x0}, - {0x90173, 0x0}, - {0x90174, 0x0}, - {0x90175, 0x0}, - {0x90176, 0x0}, - {0x90177, 0x0}, - {0x90178, 0x0}, - {0x90179, 0x0}, - {0x9017a, 0x0}, - {0x9017b, 0x0}, - {0x9017c, 0x0}, - {0x9017d, 0x0}, - {0x9017e, 0x0}, - {0x9017f, 0x0}, - {0x90180, 0x0}, - {0x90181, 0x0}, - {0x90182, 0x0}, - {0x90183, 0x0}, - {0x90184, 0x0}, - {0x90006, 0x0}, - {0x90007, 0x0}, - {0x90008, 0x0}, - {0x90009, 0x0}, - {0x9000a, 0x0}, - {0x9000b, 0x0}, - {0xd00e7, 0x0}, - {0x90017, 0x0}, - {0x9001f, 0x0}, - {0x90026, 0x0}, - {0x400d0, 0x0}, - {0x400d1, 0x0}, - {0x400d2, 0x0}, - {0x400d3, 0x0}, - {0x400d4, 0x0}, - {0x400d5, 0x0}, - {0x400d6, 0x0}, - {0x400d7, 0x0}, - {0x200be, 0x0}, - {0x2000b, 0x0}, - {0x2000c, 0x0}, - {0x2000d, 0x0}, - {0x2000e, 0x0}, - {0x12000b, 0x0}, - {0x12000c, 0x0}, - {0x12000d, 0x0}, - {0x12000e, 0x0}, - {0x22000b, 0x0}, - {0x22000c, 0x0}, - {0x22000d, 0x0}, - {0x22000e, 0x0}, - {0x9000c, 0x0}, - {0x9000d, 0x0}, - {0x9000e, 0x0}, - {0x9000f, 0x0}, - {0x90010, 0x0}, - {0x90011, 0x0}, - {0x90012, 0x0}, - {0x90013, 0x0}, - {0x20010, 0x0}, - {0x20011, 0x0}, - {0x120010, 0x0}, - {0x120011, 0x0}, - {0x40080, 0x0}, - {0x40081, 0x0}, - {0x40082, 0x0}, - {0x40083, 0x0}, - {0x40084, 0x0}, - {0x40085, 0x0}, - {0x140080, 0x0}, - {0x140081, 0x0}, - {0x140082, 0x0}, - {0x140083, 0x0}, - {0x140084, 0x0}, - {0x140085, 0x0}, - {0x240080, 0x0}, - {0x240081, 0x0}, - {0x240082, 0x0}, - {0x240083, 0x0}, - {0x240084, 0x0}, - {0x240085, 0x0}, - {0x400fd, 0x0}, - {0x400f1, 0x0}, - {0x10011, 0x0}, - {0x10012, 0x0}, - {0x10013, 0x0}, - {0x10018, 0x0}, - {0x10002, 0x0}, - {0x100b2, 0x0}, - {0x101b4, 0x0}, - {0x102b4, 0x0}, - {0x103b4, 0x0}, - {0x104b4, 0x0}, - {0x105b4, 0x0}, - {0x106b4, 0x0}, - {0x107b4, 0x0}, - {0x108b4, 0x0}, - {0x11011, 0x0}, - {0x11012, 0x0}, - {0x11013, 0x0}, - {0x11018, 0x0}, - {0x11002, 0x0}, - {0x110b2, 0x0}, - {0x111b4, 0x0}, - {0x112b4, 0x0}, - {0x113b4, 0x0}, - {0x114b4, 0x0}, - {0x115b4, 0x0}, - {0x116b4, 0x0}, - {0x117b4, 0x0}, - {0x118b4, 0x0}, - {0x20089, 0x0}, - {0xc0080, 0x0}, - {0x200cb, 0x0}, - {0x10068, 0x0}, - {0x10069, 0x0}, - {0x10168, 0x0}, - {0x10169, 0x0}, - {0x10268, 0x0}, - {0x10269, 0x0}, - {0x10368, 0x0}, - {0x10369, 0x0}, - {0x10468, 0x0}, - {0x10469, 0x0}, - {0x10568, 0x0}, - {0x10569, 0x0}, - {0x10668, 0x0}, - {0x10669, 0x0}, - {0x10768, 0x0}, - {0x10769, 0x0}, - {0x10868, 0x0}, - {0x10869, 0x0}, - {0x100aa, 0x0}, - {0x10062, 0x0}, - {0x10001, 0x0}, - {0x100a0, 0x0}, - {0x100a1, 0x0}, - {0x100a2, 0x0}, - {0x100a3, 0x0}, - {0x100a4, 0x0}, - {0x100a5, 0x0}, - {0x100a6, 0x0}, - {0x100a7, 0x0}, - {0x11068, 0x0}, - {0x11069, 0x0}, - {0x11168, 0x0}, - {0x11169, 0x0}, - {0x11268, 0x0}, - {0x11269, 0x0}, - {0x11368, 0x0}, - {0x11369, 0x0}, - {0x11468, 0x0}, - {0x11469, 0x0}, - {0x11568, 0x0}, - {0x11569, 0x0}, - {0x11668, 0x0}, - {0x11669, 0x0}, - {0x11768, 0x0}, - {0x11769, 0x0}, - {0x11868, 0x0}, - {0x11869, 0x0}, - {0x110aa, 0x0}, - {0x11062, 0x0}, - {0x11001, 0x0}, - {0x110a0, 0x0}, - {0x110a1, 0x0}, - {0x110a2, 0x0}, - {0x110a3, 0x0}, - {0x110a4, 0x0}, - {0x110a5, 0x0}, - {0x110a6, 0x0}, - {0x110a7, 0x0}, - {0x80, 0x0}, - {0x1080, 0x0}, - {0x2080, 0x0}, - {0x10020, 0x0}, - {0x10080, 0x0}, - {0x10081, 0x0}, - {0x100d0, 0x0}, - {0x100d1, 0x0}, - {0x1008c, 0x0}, - {0x1008d, 0x0}, - {0x10180, 0x0}, - {0x10181, 0x0}, - {0x101d0, 0x0}, - {0x101d1, 0x0}, - {0x1018c, 0x0}, - {0x1018d, 0x0}, - {0x100c0, 0x0}, - {0x100c1, 0x0}, - {0x101c0, 0x0}, - {0x101c1, 0x0}, - {0x102c0, 0x0}, - {0x102c1, 0x0}, - {0x103c0, 0x0}, - {0x103c1, 0x0}, - {0x104c0, 0x0}, - {0x104c1, 0x0}, - {0x105c0, 0x0}, - {0x105c1, 0x0}, - {0x106c0, 0x0}, - {0x106c1, 0x0}, - {0x107c0, 0x0}, - {0x107c1, 0x0}, - {0x108c0, 0x0}, - {0x108c1, 0x0}, - {0x100ae, 0x0}, - {0x100af, 0x0}, - {0x11020, 0x0}, - {0x11080, 0x0}, - {0x11081, 0x0}, - {0x110d0, 0x0}, - {0x110d1, 0x0}, - {0x1108c, 0x0}, - {0x1108d, 0x0}, - {0x11180, 0x0}, - {0x11181, 0x0}, - {0x111d0, 0x0}, - {0x111d1, 0x0}, - {0x1118c, 0x0}, - {0x1118d, 0x0}, - {0x110c0, 0x0}, - {0x110c1, 0x0}, - {0x111c0, 0x0}, - {0x111c1, 0x0}, - {0x112c0, 0x0}, - {0x112c1, 0x0}, - {0x113c0, 0x0}, - {0x113c1, 0x0}, - {0x114c0, 0x0}, - {0x114c1, 0x0}, - {0x115c0, 0x0}, - {0x115c1, 0x0}, - {0x116c0, 0x0}, - {0x116c1, 0x0}, - {0x117c0, 0x0}, - {0x117c1, 0x0}, - {0x118c0, 0x0}, - {0x118c1, 0x0}, - {0x110ae, 0x0}, - {0x110af, 0x0}, - {0x90201, 0x0}, - {0x90202, 0x0}, - {0x90203, 0x0}, - {0x90205, 0x0}, - {0x90206, 0x0}, - {0x90207, 0x0}, - {0x90208, 0x0}, - {0x20020, 0x0}, - {0x100080, 0x0}, - {0x101080, 0x0}, - {0x102080, 0x0}, - {0x110020, 0x0}, - {0x110080, 0x0}, - {0x110081, 0x0}, - {0x1100d0, 0x0}, - {0x1100d1, 0x0}, - {0x11008c, 0x0}, - {0x11008d, 0x0}, - {0x110180, 0x0}, - {0x110181, 0x0}, - {0x1101d0, 0x0}, - {0x1101d1, 0x0}, - {0x11018c, 0x0}, - {0x11018d, 0x0}, - {0x1100c0, 0x0}, - {0x1100c1, 0x0}, - {0x1101c0, 0x0}, - {0x1101c1, 0x0}, - {0x1102c0, 0x0}, - {0x1102c1, 0x0}, - {0x1103c0, 0x0}, - {0x1103c1, 0x0}, - {0x1104c0, 0x0}, - {0x1104c1, 0x0}, - {0x1105c0, 0x0}, - {0x1105c1, 0x0}, - {0x1106c0, 0x0}, - {0x1106c1, 0x0}, - {0x1107c0, 0x0}, - {0x1107c1, 0x0}, - {0x1108c0, 0x0}, - {0x1108c1, 0x0}, - {0x1100ae, 0x0}, - {0x1100af, 0x0}, - {0x111020, 0x0}, - {0x111080, 0x0}, - {0x111081, 0x0}, - {0x1110d0, 0x0}, - {0x1110d1, 0x0}, - {0x11108c, 0x0}, - {0x11108d, 0x0}, - {0x111180, 0x0}, - {0x111181, 0x0}, - {0x1111d0, 0x0}, - {0x1111d1, 0x0}, - {0x11118c, 0x0}, - {0x11118d, 0x0}, - {0x1110c0, 0x0}, - {0x1110c1, 0x0}, - {0x1111c0, 0x0}, - {0x1111c1, 0x0}, - {0x1112c0, 0x0}, - {0x1112c1, 0x0}, - {0x1113c0, 0x0}, - {0x1113c1, 0x0}, - {0x1114c0, 0x0}, - {0x1114c1, 0x0}, - {0x1115c0, 0x0}, - {0x1115c1, 0x0}, - {0x1116c0, 0x0}, - {0x1116c1, 0x0}, - {0x1117c0, 0x0}, - {0x1117c1, 0x0}, - {0x1118c0, 0x0}, - {0x1118c1, 0x0}, - {0x1110ae, 0x0}, - {0x1110af, 0x0}, - {0x190201, 0x0}, - {0x190202, 0x0}, - {0x190203, 0x0}, - {0x190205, 0x0}, - {0x190206, 0x0}, - {0x190207, 0x0}, - {0x190208, 0x0}, - {0x120020, 0x0}, - {0x200080, 0x0}, - {0x201080, 0x0}, - {0x202080, 0x0}, - {0x210020, 0x0}, - {0x210080, 0x0}, - {0x210081, 0x0}, - {0x2100d0, 0x0}, - {0x2100d1, 0x0}, - {0x21008c, 0x0}, - {0x21008d, 0x0}, - {0x210180, 0x0}, - {0x210181, 0x0}, - {0x2101d0, 0x0}, - {0x2101d1, 0x0}, - {0x21018c, 0x0}, - {0x21018d, 0x0}, - {0x2100c0, 0x0}, - {0x2100c1, 0x0}, - {0x2101c0, 0x0}, - {0x2101c1, 0x0}, - {0x2102c0, 0x0}, - {0x2102c1, 0x0}, - {0x2103c0, 0x0}, - {0x2103c1, 0x0}, - {0x2104c0, 0x0}, - {0x2104c1, 0x0}, - {0x2105c0, 0x0}, - {0x2105c1, 0x0}, - {0x2106c0, 0x0}, - {0x2106c1, 0x0}, - {0x2107c0, 0x0}, - {0x2107c1, 0x0}, - {0x2108c0, 0x0}, - {0x2108c1, 0x0}, - {0x2100ae, 0x0}, - {0x2100af, 0x0}, - {0x211020, 0x0}, - {0x211080, 0x0}, - {0x211081, 0x0}, - {0x2110d0, 0x0}, - {0x2110d1, 0x0}, - {0x21108c, 0x0}, - {0x21108d, 0x0}, - {0x211180, 0x0}, - {0x211181, 0x0}, - {0x2111d0, 0x0}, - {0x2111d1, 0x0}, - {0x21118c, 0x0}, - {0x21118d, 0x0}, - {0x2110c0, 0x0}, - {0x2110c1, 0x0}, - {0x2111c0, 0x0}, - {0x2111c1, 0x0}, - {0x2112c0, 0x0}, - {0x2112c1, 0x0}, - {0x2113c0, 0x0}, - {0x2113c1, 0x0}, - {0x2114c0, 0x0}, - {0x2114c1, 0x0}, - {0x2115c0, 0x0}, - {0x2115c1, 0x0}, - {0x2116c0, 0x0}, - {0x2116c1, 0x0}, - {0x2117c0, 0x0}, - {0x2117c1, 0x0}, - {0x2118c0, 0x0}, - {0x2118c1, 0x0}, - {0x2110ae, 0x0}, - {0x2110af, 0x0}, - {0x290201, 0x0}, - {0x290202, 0x0}, - {0x290203, 0x0}, - {0x290205, 0x0}, - {0x290206, 0x0}, - {0x290207, 0x0}, - {0x290208, 0x0}, - {0x220020, 0x0}, - {0x20077, 0x0}, - {0x20072, 0x0}, - {0x20073, 0x0}, - {0x400c0, 0x0}, - {0x10040, 0x0}, - {0x10140, 0x0}, - {0x10240, 0x0}, - {0x10340, 0x0}, - {0x10440, 0x0}, - {0x10540, 0x0}, - {0x10640, 0x0}, - {0x10740, 0x0}, - {0x10840, 0x0}, - {0x11040, 0x0}, - {0x11140, 0x0}, - {0x11240, 0x0}, - {0x11340, 0x0}, - {0x11440, 0x0}, - {0x11540, 0x0}, - {0x11640, 0x0}, - {0x11740, 0x0}, - {0x11840, 0x0}, -}; - -/* P0 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0x960}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x131f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x24c4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x24c4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xc400}, - {0x54033, 0x3324}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xc400}, - {0x54039, 0x3324}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P1 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp1_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x1}, - {0x54003, 0x4b0}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x52a4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x52a4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xa400}, - {0x54033, 0x3352}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xa400}, - {0x54039, 0x3352}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P2 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp2_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x102}, - {0x54003, 0x270}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x994}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4800}, - {0x5401e, 0x4}, - {0x5401f, 0x994}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4800}, - {0x54024, 0x4}, - {0x54032, 0x9400}, - {0x54033, 0x3309}, - {0x54034, 0x4600}, - {0x54035, 0x11}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0x9400}, - {0x54039, 0x3309}, - {0x5403a, 0x4600}, - {0x5403b, 0x11}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P0 2D message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0x960}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x61}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54010, 0x2080}, - {0x54012, 0x110}, - {0x54019, 0x24c4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x24c4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xc400}, - {0x54033, 0x3324}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xc400}, - {0x54039, 0x3324}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* DRAM PHY init engine image */ -static struct dram_cfg_param ddr_phy_pie[] = { - {0xd0000, 0x0}, - {0x90000, 0x10}, - {0x90001, 0x400}, - {0x90002, 0x10e}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x8}, - {0x90029, 0xb}, - {0x9002a, 0x480}, - {0x9002b, 0x109}, - {0x9002c, 0x8}, - {0x9002d, 0x448}, - {0x9002e, 0x139}, - {0x9002f, 0x8}, - {0x90030, 0x478}, - {0x90031, 0x109}, - {0x90032, 0x0}, - {0x90033, 0xe8}, - {0x90034, 0x109}, - {0x90035, 0x2}, - {0x90036, 0x10}, - {0x90037, 0x139}, - {0x90038, 0xb}, - {0x90039, 0x7c0}, - {0x9003a, 0x139}, - {0x9003b, 0x44}, - {0x9003c, 0x633}, - {0x9003d, 0x159}, - {0x9003e, 0x14f}, - {0x9003f, 0x630}, - {0x90040, 0x159}, - {0x90041, 0x47}, - {0x90042, 0x633}, - {0x90043, 0x149}, - {0x90044, 0x4f}, - {0x90045, 0x633}, - {0x90046, 0x179}, - {0x90047, 0x8}, - {0x90048, 0xe0}, - {0x90049, 0x109}, - {0x9004a, 0x0}, - {0x9004b, 0x7c8}, - {0x9004c, 0x109}, - {0x9004d, 0x0}, - {0x9004e, 0x1}, - {0x9004f, 0x8}, - {0x90050, 0x30}, - {0x90051, 0x65a}, - {0x90052, 0x9}, - {0x90053, 0x0}, - {0x90054, 0x45a}, - {0x90055, 0x9}, - {0x90056, 0x0}, - {0x90057, 0x448}, - {0x90058, 0x109}, - {0x90059, 0x40}, - {0x9005a, 0x633}, - {0x9005b, 0x179}, - {0x9005c, 0x1}, - {0x9005d, 0x618}, - {0x9005e, 0x109}, - {0x9005f, 0x40c0}, - {0x90060, 0x633}, - {0x90061, 0x149}, - {0x90062, 0x8}, - {0x90063, 0x4}, - {0x90064, 0x48}, - {0x90065, 0x4040}, - {0x90066, 0x633}, - {0x90067, 0x149}, - {0x90068, 0x0}, - {0x90069, 0x4}, - {0x9006a, 0x48}, - {0x9006b, 0x40}, - {0x9006c, 0x633}, - {0x9006d, 0x149}, - {0x9006e, 0x0}, - {0x9006f, 0x658}, - {0x90070, 0x109}, - {0x90071, 0x10}, - {0x90072, 0x4}, - {0x90073, 0x18}, - {0x90074, 0x0}, - {0x90075, 0x4}, - {0x90076, 0x78}, - {0x90077, 0x549}, - {0x90078, 0x633}, - {0x90079, 0x159}, - {0x9007a, 0xd49}, - {0x9007b, 0x633}, - {0x9007c, 0x159}, - {0x9007d, 0x94a}, - {0x9007e, 0x633}, - {0x9007f, 0x159}, - {0x90080, 0x441}, - {0x90081, 0x633}, - {0x90082, 0x149}, - {0x90083, 0x42}, - {0x90084, 0x633}, - {0x90085, 0x149}, - {0x90086, 0x1}, - {0x90087, 0x633}, - {0x90088, 0x149}, - {0x90089, 0x0}, - {0x9008a, 0xe0}, - {0x9008b, 0x109}, - {0x9008c, 0xa}, - {0x9008d, 0x10}, - {0x9008e, 0x109}, - {0x9008f, 0x9}, - {0x90090, 0x3c0}, - {0x90091, 0x149}, - {0x90092, 0x9}, - {0x90093, 0x3c0}, - {0x90094, 0x159}, - {0x90095, 0x18}, - {0x90096, 0x10}, - {0x90097, 0x109}, - {0x90098, 0x0}, - {0x90099, 0x3c0}, - {0x9009a, 0x109}, - {0x9009b, 0x18}, - {0x9009c, 0x4}, - {0x9009d, 0x48}, - {0x9009e, 0x18}, - {0x9009f, 0x4}, - {0x900a0, 0x58}, - {0x900a1, 0xb}, - {0x900a2, 0x10}, - {0x900a3, 0x109}, - {0x900a4, 0x1}, - {0x900a5, 0x10}, - {0x900a6, 0x109}, - {0x900a7, 0x5}, - {0x900a8, 0x7c0}, - {0x900a9, 0x109}, - {0x40000, 0x811}, - {0x40020, 0x880}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x4008}, - {0x40021, 0x83}, - {0x40041, 0x4f}, - {0x40061, 0x0}, - {0x40002, 0x4040}, - {0x40022, 0x83}, - {0x40042, 0x51}, - {0x40062, 0x0}, - {0x40003, 0x811}, - {0x40023, 0x880}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x720}, - {0x40024, 0xf}, - {0x40044, 0x1740}, - {0x40064, 0x0}, - {0x40005, 0x16}, - {0x40025, 0x83}, - {0x40045, 0x4b}, - {0x40065, 0x0}, - {0x40006, 0x716}, - {0x40026, 0xf}, - {0x40046, 0x2001}, - {0x40066, 0x0}, - {0x40007, 0x716}, - {0x40027, 0xf}, - {0x40047, 0x2800}, - {0x40067, 0x0}, - {0x40008, 0x716}, - {0x40028, 0xf}, - {0x40048, 0xf00}, - {0x40068, 0x0}, - {0x40009, 0x720}, - {0x40029, 0xf}, - {0x40049, 0x1400}, - {0x40069, 0x0}, - {0x4000a, 0xe08}, - {0x4002a, 0xc15}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x625}, - {0x4002b, 0x15}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x4028}, - {0x4002c, 0x80}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0xe08}, - {0x4002d, 0xc1a}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x625}, - {0x4002e, 0x1a}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x4040}, - {0x4002f, 0x80}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x2604}, - {0x40030, 0x15}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x708}, - {0x40031, 0x5}, - {0x40051, 0x0}, - {0x40071, 0x2002}, - {0x40012, 0x8}, - {0x40032, 0x80}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x2604}, - {0x40033, 0x1a}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x708}, - {0x40034, 0xa}, - {0x40054, 0x0}, - {0x40074, 0x2002}, - {0x40015, 0x4040}, - {0x40035, 0x80}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x60a}, - {0x40036, 0x15}, - {0x40056, 0x1200}, - {0x40076, 0x0}, - {0x40017, 0x61a}, - {0x40037, 0x15}, - {0x40057, 0x1300}, - {0x40077, 0x0}, - {0x40018, 0x60a}, - {0x40038, 0x1a}, - {0x40058, 0x1200}, - {0x40078, 0x0}, - {0x40019, 0x642}, - {0x40039, 0x1a}, - {0x40059, 0x1300}, - {0x40079, 0x0}, - {0x4001a, 0x4808}, - {0x4003a, 0x880}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x790}, - {0x900ac, 0x11a}, - {0x900ad, 0x8}, - {0x900ae, 0x7aa}, - {0x900af, 0x2a}, - {0x900b0, 0x10}, - {0x900b1, 0x7b2}, - {0x900b2, 0x2a}, - {0x900b3, 0x0}, - {0x900b4, 0x7c8}, - {0x900b5, 0x109}, - {0x900b6, 0x10}, - {0x900b7, 0x10}, - {0x900b8, 0x109}, - {0x900b9, 0x10}, - {0x900ba, 0x2a8}, - {0x900bb, 0x129}, - {0x900bc, 0x8}, - {0x900bd, 0x370}, - {0x900be, 0x129}, - {0x900bf, 0xa}, - {0x900c0, 0x3c8}, - {0x900c1, 0x1a9}, - {0x900c2, 0xc}, - {0x900c3, 0x408}, - {0x900c4, 0x199}, - {0x900c5, 0x14}, - {0x900c6, 0x790}, - {0x900c7, 0x11a}, - {0x900c8, 0x8}, - {0x900c9, 0x4}, - {0x900ca, 0x18}, - {0x900cb, 0xe}, - {0x900cc, 0x408}, - {0x900cd, 0x199}, - {0x900ce, 0x8}, - {0x900cf, 0x8568}, - {0x900d0, 0x108}, - {0x900d1, 0x18}, - {0x900d2, 0x790}, - {0x900d3, 0x16a}, - {0x900d4, 0x8}, - {0x900d5, 0x1d8}, - {0x900d6, 0x169}, - {0x900d7, 0x10}, - {0x900d8, 0x8558}, - {0x900d9, 0x168}, - {0x900da, 0x1ff8}, - {0x900db, 0x85a8}, - {0x900dc, 0x1e8}, - {0x900dd, 0x50}, - {0x900de, 0x798}, - {0x900df, 0x16a}, - {0x900e0, 0x60}, - {0x900e1, 0x7a0}, - {0x900e2, 0x16a}, - {0x900e3, 0x8}, - {0x900e4, 0x8310}, - {0x900e5, 0x168}, - {0x900e6, 0x8}, - {0x900e7, 0xa310}, - {0x900e8, 0x168}, - {0x900e9, 0xa}, - {0x900ea, 0x408}, - {0x900eb, 0x169}, - {0x900ec, 0x6e}, - {0x900ed, 0x0}, - {0x900ee, 0x68}, - {0x900ef, 0x0}, - {0x900f0, 0x408}, - {0x900f1, 0x169}, - {0x900f2, 0x0}, - {0x900f3, 0x8310}, - {0x900f4, 0x168}, - {0x900f5, 0x0}, - {0x900f6, 0xa310}, - {0x900f7, 0x168}, - {0x900f8, 0x1ff8}, - {0x900f9, 0x85a8}, - {0x900fa, 0x1e8}, - {0x900fb, 0x68}, - {0x900fc, 0x798}, - {0x900fd, 0x16a}, - {0x900fe, 0x78}, - {0x900ff, 0x7a0}, - {0x90100, 0x16a}, - {0x90101, 0x68}, - {0x90102, 0x790}, - {0x90103, 0x16a}, - {0x90104, 0x8}, - {0x90105, 0x8b10}, - {0x90106, 0x168}, - {0x90107, 0x8}, - {0x90108, 0xab10}, - {0x90109, 0x168}, - {0x9010a, 0xa}, - {0x9010b, 0x408}, - {0x9010c, 0x169}, - {0x9010d, 0x58}, - {0x9010e, 0x0}, - {0x9010f, 0x68}, - {0x90110, 0x0}, - {0x90111, 0x408}, - {0x90112, 0x169}, - {0x90113, 0x0}, - {0x90114, 0x8b10}, - {0x90115, 0x168}, - {0x90116, 0x1}, - {0x90117, 0xab10}, - {0x90118, 0x168}, - {0x90119, 0x0}, - {0x9011a, 0x1d8}, - {0x9011b, 0x169}, - {0x9011c, 0x80}, - {0x9011d, 0x790}, - {0x9011e, 0x16a}, - {0x9011f, 0x18}, - {0x90120, 0x7aa}, - {0x90121, 0x6a}, - {0x90122, 0xa}, - {0x90123, 0x0}, - {0x90124, 0x1e9}, - {0x90125, 0x8}, - {0x90126, 0x8080}, - {0x90127, 0x108}, - {0x90128, 0xf}, - {0x90129, 0x408}, - {0x9012a, 0x169}, - {0x9012b, 0xc}, - {0x9012c, 0x0}, - {0x9012d, 0x68}, - {0x9012e, 0x9}, - {0x9012f, 0x0}, - {0x90130, 0x1a9}, - {0x90131, 0x0}, - {0x90132, 0x408}, - {0x90133, 0x169}, - {0x90134, 0x0}, - {0x90135, 0x8080}, - {0x90136, 0x108}, - {0x90137, 0x8}, - {0x90138, 0x7aa}, - {0x90139, 0x6a}, - {0x9013a, 0x0}, - {0x9013b, 0x8568}, - {0x9013c, 0x108}, - {0x9013d, 0xb7}, - {0x9013e, 0x790}, - {0x9013f, 0x16a}, - {0x90140, 0x1f}, - {0x90141, 0x0}, - {0x90142, 0x68}, - {0x90143, 0x8}, - {0x90144, 0x8558}, - {0x90145, 0x168}, - {0x90146, 0xf}, - {0x90147, 0x408}, - {0x90148, 0x169}, - {0x90149, 0xd}, - {0x9014a, 0x0}, - {0x9014b, 0x68}, - {0x9014c, 0x0}, - {0x9014d, 0x408}, - {0x9014e, 0x169}, - {0x9014f, 0x0}, - {0x90150, 0x8558}, - {0x90151, 0x168}, - {0x90152, 0x8}, - {0x90153, 0x3c8}, - {0x90154, 0x1a9}, - {0x90155, 0x3}, - {0x90156, 0x370}, - {0x90157, 0x129}, - {0x90158, 0x20}, - {0x90159, 0x2aa}, - {0x9015a, 0x9}, - {0x9015b, 0x8}, - {0x9015c, 0xe8}, - {0x9015d, 0x109}, - {0x9015e, 0x0}, - {0x9015f, 0x8140}, - {0x90160, 0x10c}, - {0x90161, 0x10}, - {0x90162, 0x8138}, - {0x90163, 0x104}, - {0x90164, 0x8}, - {0x90165, 0x448}, - {0x90166, 0x109}, - {0x90167, 0xf}, - {0x90168, 0x7c0}, - {0x90169, 0x109}, - {0x9016a, 0x0}, - {0x9016b, 0xe8}, - {0x9016c, 0x109}, - {0x9016d, 0x47}, - {0x9016e, 0x630}, - {0x9016f, 0x109}, - {0x90170, 0x8}, - {0x90171, 0x618}, - {0x90172, 0x109}, - {0x90173, 0x8}, - {0x90174, 0xe0}, - {0x90175, 0x109}, - {0x90176, 0x0}, - {0x90177, 0x7c8}, - {0x90178, 0x109}, - {0x90179, 0x8}, - {0x9017a, 0x8140}, - {0x9017b, 0x10c}, - {0x9017c, 0x0}, - {0x9017d, 0x478}, - {0x9017e, 0x109}, - {0x9017f, 0x0}, - {0x90180, 0x1}, - {0x90181, 0x8}, - {0x90182, 0x8}, - {0x90183, 0x4}, - {0x90184, 0x0}, - {0x90006, 0x8}, - {0x90007, 0x7c8}, - {0x90008, 0x109}, - {0x90009, 0x0}, - {0x9000a, 0x400}, - {0x9000b, 0x106}, - {0xd00e7, 0x400}, - {0x90017, 0x0}, - {0x9001f, 0x2b}, - {0x90026, 0x69}, - {0x400d0, 0x0}, - {0x400d1, 0x101}, - {0x400d2, 0x105}, - {0x400d3, 0x107}, - {0x400d4, 0x10f}, - {0x400d5, 0x202}, - {0x400d6, 0x20a}, - {0x400d7, 0x20b}, - {0x2003a, 0x2}, - {0x200be, 0x3}, - {0x2000b, 0x2a3}, - {0x2000c, 0x96}, - {0x2000d, 0x5dc}, - {0x2000e, 0x2c}, - {0x12000b, 0x152}, - {0x12000c, 0x4b}, - {0x12000d, 0x2ee}, - {0x12000e, 0x2c}, - {0x22000b, 0xb0}, - {0x22000c, 0x27}, - {0x22000d, 0x186}, - {0x22000e, 0x10}, - {0x9000c, 0x0}, - {0x9000d, 0x173}, - {0x9000e, 0x60}, - {0x9000f, 0x6110}, - {0x90010, 0x2152}, - {0x90011, 0xdfbd}, - {0x90012, 0x2060}, - {0x90013, 0x6152}, - {0x20010, 0x5a}, - {0x20011, 0x3}, - {0x120010, 0x5a}, - {0x120011, 0x3}, - {0x40080, 0xe0}, - {0x40081, 0x12}, - {0x40082, 0xe0}, - {0x40083, 0x12}, - {0x40084, 0xe0}, - {0x40085, 0x12}, - {0x140080, 0xe0}, - {0x140081, 0x12}, - {0x140082, 0xe0}, - {0x140083, 0x12}, - {0x140084, 0xe0}, - {0x140085, 0x12}, - {0x240080, 0xe0}, - {0x240081, 0x12}, - {0x240082, 0xe0}, - {0x240083, 0x12}, - {0x240084, 0xe0}, - {0x240085, 0x12}, - {0x400fd, 0xf}, - {0x400f1, 0xe}, - {0x10011, 0x1}, - {0x10012, 0x1}, - {0x10013, 0x180}, - {0x10018, 0x1}, - {0x10002, 0x6209}, - {0x100b2, 0x1}, - {0x101b4, 0x1}, - {0x102b4, 0x1}, - {0x103b4, 0x1}, - {0x104b4, 0x1}, - {0x105b4, 0x1}, - {0x106b4, 0x1}, - {0x107b4, 0x1}, - {0x108b4, 0x1}, - {0x11011, 0x1}, - {0x11012, 0x1}, - {0x11013, 0x180}, - {0x11018, 0x1}, - {0x11002, 0x6209}, - {0x110b2, 0x1}, - {0x111b4, 0x1}, - {0x112b4, 0x1}, - {0x113b4, 0x1}, - {0x114b4, 0x1}, - {0x115b4, 0x1}, - {0x116b4, 0x1}, - {0x117b4, 0x1}, - {0x118b4, 0x1}, - {0x20089, 0x1}, - {0x20088, 0x19}, - {0xc0080, 0x0}, - {0xd0000, 0x1}, -}; - -static struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 2400mts 1D */ - .drate = 2400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 1200mts 1D */ - .drate = 1200, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 625mts 1D */ - .drate = 625, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 2400mts 2D */ - .drate = 2400, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 2400, 1200, 625, }, - .fsp_cfg = ddr_dram_fsp_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), -}; diff --git a/board/freescale/imx91_evk/spl.c b/board/freescale/imx91_evk/spl.c deleted file mode 100644 index 2aa63a61b74..00000000000 --- a/board/freescale/imx91_evk/spl.c +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2024 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int spl_board_boot_device(enum boot_device boot_dev_spl) -{ - return BOOT_DEVICE_BOOTROM; -} - -void spl_board_init(void) -{ - int ret; - - ret = ele_start_rng(); - if (ret) - printf("Fail to start RNG: %d\n", ret); - - puts("Normal Boot\n"); -} - -extern struct dram_timing_info dram_timing_1600mts; -void spl_dram_init(void) -{ - struct dram_timing_info *ptiming = &dram_timing; - - if (is_voltage_mode(VOLT_LOW_DRIVE)) - ptiming = &dram_timing_1600mts; - - printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate); - ddr_init(ptiming); -} - -#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) -int power_init_board(void) -{ - struct udevice *dev; - int ret; - unsigned int val = 0, buck_val; - - ret = pmic_get("pmic@25", &dev); - if (ret == -ENODEV) { - puts("ERROR: Get PMIC PCA9451A failed!\n"); - return ret; - } - if (ret != 0) - return ret; - - /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); - - /* enable DVS control through PMIC_STBY_REQ */ - pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); - - ret = pmic_reg_read(dev, PCA9450_PWR_CTRL); - if (ret < 0) - return ret; - - val = ret; - - if (is_voltage_mode(VOLT_LOW_DRIVE)) { - buck_val = 0x0c; /* 0.8V for Low drive mode */ - printf("PMIC: Low Drive Voltage Mode\n"); - } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) { - buck_val = 0x10; /* 0.85V for Nominal drive mode */ - printf("PMIC: Nominal Voltage Mode\n"); - } else { - buck_val = 0x14; /* 0.9V for Over drive mode */ - printf("PMIC: Over Drive Voltage Mode\n"); - } - - if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val); - } else { - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4); - } - - /* Set VDDQ to 1.1V from buck2 (buck2 not used for iMX91 EVK) */ - pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28); - - /* set standby voltage to 0.65V */ - if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0); - else - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); - - /* I2C_LT_EN*/ - pmic_reg_write(dev, 0xa, 0x3); - return 0; -} -#endif - -void board_init_f(ulong dummy) -{ - int ret; - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - timer_init(); - - arch_cpu_init(); - - spl_early_init(); - - preloader_console_init(); - - ret = imx9_probe_mu(); - if (ret) { - printf("Fail to init ELE API\n"); - } else { - debug("SOC: 0x%x\n", gd->arch.soc_rev); - debug("LC: 0x%x\n", gd->arch.lifecycle); - } - - clock_init_late(); - - power_init_board(); - - if (!is_voltage_mode(VOLT_LOW_DRIVE)) - set_arm_clk(get_cpu_speed_grade_hz()); - - /* Init power of mix */ - soc_power_init(); - - /* Setup TRDC for DDR access */ - trdc_init(); - - /* DDR initialization */ - spl_dram_init(); - - board_init_r(NULL, 0); -} diff --git a/board/freescale/imx91_frdm/Kconfig b/board/freescale/imx91_frdm/Kconfig deleted file mode 100644 index 68f4bb5c7ec..00000000000 --- a/board/freescale/imx91_frdm/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_IMX91_11X11_FRDM - -config SYS_BOARD - default "imx91_frdm" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "imx91_frdm" - -endif diff --git a/board/freescale/imx91_frdm/MAINTAINERS b/board/freescale/imx91_frdm/MAINTAINERS deleted file mode 100644 index bf5320f03db..00000000000 --- a/board/freescale/imx91_frdm/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -FRDM-IMX91 BOARD -M: Joseph Guo -S: Maintained -F: board/freescale/imx91_frdm/ -F: include/configs/imx91_frdm.h -F: configs/imx91_11x11_frdm_defconfig -F: configs/imx91_11x11_frdm_inline_ecc_defconfig diff --git a/board/freescale/imx91_frdm/Makefile b/board/freescale/imx91_frdm/Makefile deleted file mode 100644 index 75510b13b44..00000000000 --- a/board/freescale/imx91_frdm/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright 2025 NXP -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += imx91_frdm.o - -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -ifdef CONFIG_IMX9_DRAM_INLINE_ECC -obj-y += lpddr4_2400mts_ecc_1gb_timing.o lpddr4_2400mts_ecc_2gb_timing.o -else -obj-y += lpddr4_2400mts_1gb_timing.o lpddr4_2400mts_2gb_timing.o -endif -endif diff --git a/board/freescale/imx91_frdm/imx91_frdm.c b/board/freescale/imx91_frdm/imx91_frdm.c deleted file mode 100644 index 14ad464ded1..00000000000 --- a/board/freescale/imx91_frdm/imx91_frdm.c +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2025 NXP - */ - -#include -#include -#include -#include - -#define TCPC_ALERT 0x10 -#define TCPC_ALERT_MASK 0x12 -#define TCPC_FAULT_STATUS_MASK 0x15 -#define USB_I2C_BUS 2 -#define USB_I2C_ADDR 0x50 - -/* - * Since tcpc driver is not upstream. PTN5110 interrupt will cause - * kernel panic because nobody cares the interrupt. So add workaround here. - * Clear PTN5110 USB Power Delivery controller alert status by - * masking interrupts and clearing pending alerts via I2C communication. - * This is typically called during board initialization to ensure the USB PD - * controller starts in a clean state without any stale alert conditions. - */ -static int clear_pd_alert(void) -{ - struct udevice *bus; - struct udevice *i2c_dev = NULL; - int ret; - u8 buffer_0[2] = {0, 0}; - u8 buffer_1[2] = {0xff, 0xff}; - - ret = uclass_get_device_by_seq(UCLASS_I2C, USB_I2C_BUS, &bus); - if (ret) { - printf("Failed to get I2C bus %d\n", USB_I2C_BUS); - return ret; - } - - ret = dm_i2c_probe(bus, USB_I2C_ADDR, 0, &i2c_dev); - if (ret) { - printf("Can't find USB PD device at 0x%02x\n", USB_I2C_ADDR); - return ret; - } - - /* Mask all alert status*/ - ret = dm_i2c_write(i2c_dev, TCPC_ALERT_MASK, buffer_0, 2); - if (ret) { - printf("%s dm_i2c_write failed: %d\n", __func__, ret); - return ret; - } - - ret = dm_i2c_write(i2c_dev, TCPC_FAULT_STATUS_MASK, buffer_0, 2); - if (ret) { - printf("%s dm_i2c_write failed: %d\n", __func__, ret); - return ret; - } - - ret = dm_i2c_write(i2c_dev, TCPC_ALERT, buffer_1, 2); - if (ret) { - printf("%s dm_i2c_write failed: %d\n", __func__, ret); - return ret; - } - - return 0; -} - -int board_late_init(void) -{ - if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) - board_late_mmc_env_init(); - - env_set("sec_boot", "no"); - - if (IS_ENABLED(CONFIG_AHAB_BOOT)) - env_set("sec_boot", "yes"); - - if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { - env_set("board_name", "11X11_FRDM"); - env_set("board_rev", "iMX91"); - } - - clear_pd_alert(); - return 0; -} diff --git a/board/freescale/imx91_frdm/imx91_frdm.env b/board/freescale/imx91_frdm/imx91_frdm.env deleted file mode 100644 index b0450ff576c..00000000000 --- a/board/freescale/imx91_frdm/imx91_frdm.env +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ - -boot_targets=mmc0 mmc1 -boot_fit=no -bootm_size=0x10000000 -cntr_addr=0x98000000 -cntr_file=os_cntr_signed.bin -console=ttyLP0,115200 earlycon -fdt_addr_r=0x83000000 -fdt_addr=0x83000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE -image=Image -mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX -mmcpart=1 -mmcroot=/dev/mmcblk1p2 rootwait rw -mmcautodetect=yes -mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} -loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} -loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; -bootscript=echo Running bootscript from mmc ...; source -loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} -auth_os=auth_cntr ${cntr_addr} -sec_boot=no -boot_os=booti ${loadaddr} - ${fdt_addr_r} -mmcboot= - echo Booting from mmc ...; - run mmcargs; - if test ${sec_boot} = yes; then - if run true; then - run boot_os; - else - echo ERR: failed to authenticate; - fi; - else - if run loadfdt; then - run boot_os; - else - echo WARN: Cannot load the DT; - fi; - fi; -netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs - ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp -netboot= - echo Booting from net ...; - run netargs; - if test ${ip_dyn} = yes; then - setenv get_cmd dhcp; - else - setenv get_cmd tftp; - fi; - if test ${sec_boot} = yes; then - ${get_cmd} ${cntr_addr} ${cntr_file}; - if true; then - run boot_os; - else - echo ERR: failed to authenticate; - fi; - else - ${get_cmd} ${loadaddr} ${image}; - if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then - run boot_os; - else - echo WARN: Cannot load the DT; - fi; - fi; -bsp_bootcmd= - echo Running BSP bootcmd ...; - mmc dev ${mmcdev}; - if mmc rescan; then - if run loadbootscript; then - run bootscript; - else - if test ${sec_boot} = yes; then - if run loadcntr; then - run mmcboot; - else - run netboot; - fi; - else - if run loadimage; then - run mmcboot; - else - run netboot; - fi; - fi; - fi; - fi; -scriptaddr=0x83500000 diff --git a/board/freescale/imx91_frdm/lpddr4_2400mts_1gb_timing.c b/board/freescale/imx91_frdm/lpddr4_2400mts_1gb_timing.c deleted file mode 100644 index 0a52cb9762f..00000000000 --- a/board/freescale/imx91_frdm/lpddr4_2400mts_1gb_timing.c +++ /dev/null @@ -1,1996 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright 2025 NXP - * - * Code generated with DDR Tool v3.3.0_1.8-d1cdb7d3. - * DDR PHY FW2022.01 - */ - -#include -#include - -/* Initialize DDRC registers */ -static struct dram_cfg_param ddr_ddrc_cfg[] = { - {0x4e300110, 0x44100001}, - {0x4e300000, 0x8000bf}, - {0x4e300008, 0x0}, - {0x4e300080, 0x80000412}, - {0x4e300084, 0x0}, - {0x4e300114, 0x1002}, - {0x4e300260, 0x80}, - {0x4e300f04, 0x80}, - {0x4e300800, 0x43b30002}, - {0x4e300804, 0x1f1f1f1f}, - {0x4e301000, 0x0}, - {0x4e301240, 0x0}, - {0x4e301244, 0x0}, - {0x4e301248, 0x0}, - {0x4e30124c, 0x0}, - {0x4e301250, 0x0}, - {0x4e301254, 0x0}, - {0x4e301258, 0x0}, - {0x4e30125c, 0x0}, -}; - -/* dram fsp cfg */ -static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { - { - { - {0x4e300100, 0x13542110}, - {0x4e300104, 0xF8990011}, - {0x4e300108, 0x636E88CC}, - {0x4e30010C, 0x00614070}, - {0x4e300124, 0x124E0000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x31D00000}, - {0x4e300170, 0x8B0B0608}, - {0x4e300250, 0x0000001A}, - {0x4e300254, 0x00A000A0}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - {0x4e300300, 0x1633160D}, - {0x4e300304, 0x00A0180C}, - {0x4e300308, 0x0C280927}, - }, - { - {0x01, 0xC4}, - {0x02, 0x24}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x010A1100}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0xBABA0068}, - {0x4e30010C, 0x00610158}, - {0x4e300124, 0x09270000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30400000}, - {0x4e300170, 0x8A0A0508}, - {0x4e300250, 0x0000000D}, - {0x4e300254, 0x004C004C}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0xA4}, - {0x02, 0x52}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x00051000}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0x6E620A48}, - {0x4e30010C, 0x0031010D}, - {0x4e300124, 0x04C50000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30000000}, - {0x4e300170, 0x89090408}, - {0x4e300250, 0x00000007}, - {0x4e300254, 0x00240024}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0x94}, - {0x02, 0x9}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 1, - }, - -}; - -/* PHY Initialize Configuration */ -static struct dram_cfg_param ddr_ddrphy_cfg[] = { - {0x100a0, 0x4}, - {0x100a1, 0x5}, - {0x100a2, 0x6}, - {0x100a3, 0x7}, - {0x100a4, 0x0}, - {0x100a5, 0x1}, - {0x100a6, 0x2}, - {0x100a7, 0x3}, - {0x110a0, 0x3}, - {0x110a1, 0x2}, - {0x110a2, 0x0}, - {0x110a3, 0x1}, - {0x110a4, 0x7}, - {0x110a5, 0x6}, - {0x110a6, 0x4}, - {0x110a7, 0x5}, - {0x1005f, 0x1ff}, - {0x1015f, 0x1ff}, - {0x1105f, 0x1ff}, - {0x1115f, 0x1ff}, - {0x11005f, 0x1ff}, - {0x11015f, 0x1ff}, - {0x11105f, 0x1ff}, - {0x11115f, 0x1ff}, - {0x21005f, 0x1ff}, - {0x21015f, 0x1ff}, - {0x21105f, 0x1ff}, - {0x21115f, 0x1ff}, - {0x55, 0x1ff}, - {0x1055, 0x1ff}, - {0x2055, 0x1ff}, - {0x200c5, 0xa}, - {0x1200c5, 0x2}, - {0x2200c5, 0x7}, - {0x2002e, 0x2}, - {0x12002e, 0x1}, - {0x22002e, 0x2}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x1e3}, - {0x2003a, 0x2}, - {0x2007d, 0x212}, - {0x2007c, 0x61}, - {0x120024, 0x1e3}, - {0x2003a, 0x2}, - {0x12007d, 0x212}, - {0x12007c, 0x61}, - {0x220024, 0x1e3}, - {0x2003a, 0x2}, - {0x22007d, 0x212}, - {0x22007c, 0x61}, - {0x20056, 0x3}, - {0x120056, 0x3}, - {0x220056, 0x3}, - {0x1004d, 0x600}, - {0x1014d, 0x600}, - {0x1104d, 0x600}, - {0x1114d, 0x600}, - {0x11004d, 0x600}, - {0x11014d, 0x600}, - {0x11104d, 0x600}, - {0x11114d, 0x600}, - {0x21004d, 0x600}, - {0x21014d, 0x600}, - {0x21104d, 0x600}, - {0x21114d, 0x600}, - {0x10049, 0xe3f}, - {0x10149, 0xe3f}, - {0x11049, 0xe3f}, - {0x11149, 0xe3f}, - {0x110049, 0xe3f}, - {0x110149, 0xe3f}, - {0x111049, 0xe3f}, - {0x111149, 0xe3f}, - {0x210049, 0xe3f}, - {0x210149, 0xe3f}, - {0x211049, 0xe3f}, - {0x211149, 0xe3f}, - {0x43, 0x7f}, - {0x1043, 0x7f}, - {0x2043, 0x7f}, - {0x20018, 0x1}, - {0x20075, 0x4}, - {0x20050, 0x11}, - {0x2009b, 0x2}, - {0x20008, 0x258}, - {0x120008, 0x12c}, - {0x220008, 0x9c}, - {0x20088, 0x9}, - {0x200b2, 0x10c}, - {0x10043, 0x5a1}, - {0x10143, 0x5a1}, - {0x11043, 0x5a1}, - {0x11143, 0x5a1}, - {0x1200b2, 0x10c}, - {0x110043, 0x5a1}, - {0x110143, 0x5a1}, - {0x111043, 0x5a1}, - {0x111143, 0x5a1}, - {0x2200b2, 0x10c}, - {0x210043, 0x5a1}, - {0x210143, 0x5a1}, - {0x211043, 0x5a1}, - {0x211143, 0x5a1}, - {0x200fa, 0x2}, - {0x1200fa, 0x2}, - {0x2200fa, 0x2}, - {0x20019, 0x1}, - {0x120019, 0x1}, - {0x220019, 0x1}, - {0x200f0, 0x600}, - {0x200f1, 0x0}, - {0x200f2, 0x4444}, - {0x200f3, 0x8888}, - {0x200f4, 0x5655}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0xf000}, - {0x1004a, 0x500}, - {0x1104a, 0x500}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0x20021, 0x0}, - {0x200c7, 0x21}, - {0x1200c7, 0x41}, - {0x200ca, 0x24}, - {0x1200ca, 0x24}, -}; - -/* PHY trained csr */ -static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - {0x1005f, 0x0}, - {0x1015f, 0x0}, - {0x1105f, 0x0}, - {0x1115f, 0x0}, - {0x11005f, 0x0}, - {0x11015f, 0x0}, - {0x11105f, 0x0}, - {0x11115f, 0x0}, - {0x21005f, 0x0}, - {0x21015f, 0x0}, - {0x21105f, 0x0}, - {0x21115f, 0x0}, - {0x55, 0x0}, - {0x1055, 0x0}, - {0x2055, 0x0}, - {0x200c5, 0x0}, - {0x1200c5, 0x0}, - {0x2200c5, 0x0}, - {0x2002e, 0x0}, - {0x12002e, 0x0}, - {0x22002e, 0x0}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x0}, - {0x2003a, 0x0}, - {0x2007d, 0x0}, - {0x2007c, 0x0}, - {0x120024, 0x0}, - {0x12007d, 0x0}, - {0x12007c, 0x0}, - {0x220024, 0x0}, - {0x22007d, 0x0}, - {0x22007c, 0x0}, - {0x20056, 0x0}, - {0x120056, 0x0}, - {0x220056, 0x0}, - {0x1004d, 0x0}, - {0x1014d, 0x0}, - {0x1104d, 0x0}, - {0x1114d, 0x0}, - {0x11004d, 0x0}, - {0x11014d, 0x0}, - {0x11104d, 0x0}, - {0x11114d, 0x0}, - {0x21004d, 0x0}, - {0x21014d, 0x0}, - {0x21104d, 0x0}, - {0x21114d, 0x0}, - {0x10049, 0x0}, - {0x10149, 0x0}, - {0x11049, 0x0}, - {0x11149, 0x0}, - {0x110049, 0x0}, - {0x110149, 0x0}, - {0x111049, 0x0}, - {0x111149, 0x0}, - {0x210049, 0x0}, - {0x210149, 0x0}, - {0x211049, 0x0}, - {0x211149, 0x0}, - {0x43, 0x0}, - {0x1043, 0x0}, - {0x2043, 0x0}, - {0x20018, 0x0}, - {0x20075, 0x0}, - {0x20050, 0x0}, - {0x2009b, 0x0}, - {0x20008, 0x0}, - {0x120008, 0x0}, - {0x220008, 0x0}, - {0x20088, 0x0}, - {0x200b2, 0x0}, - {0x10043, 0x0}, - {0x10143, 0x0}, - {0x11043, 0x0}, - {0x11143, 0x0}, - {0x1200b2, 0x0}, - {0x110043, 0x0}, - {0x110143, 0x0}, - {0x111043, 0x0}, - {0x111143, 0x0}, - {0x2200b2, 0x0}, - {0x210043, 0x0}, - {0x210143, 0x0}, - {0x211043, 0x0}, - {0x211143, 0x0}, - {0x200fa, 0x0}, - {0x1200fa, 0x0}, - {0x2200fa, 0x0}, - {0x20019, 0x0}, - {0x120019, 0x0}, - {0x220019, 0x0}, - {0x200f0, 0x0}, - {0x200f1, 0x0}, - {0x200f2, 0x0}, - {0x200f3, 0x0}, - {0x200f4, 0x0}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0x0}, - {0x1004a, 0x0}, - {0x1104a, 0x0}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0xd0000, 0x0}, - {0x90000, 0x0}, - {0x90001, 0x0}, - {0x90002, 0x0}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x0}, - {0x90029, 0x0}, - {0x9002a, 0x0}, - {0x9002b, 0x0}, - {0x9002c, 0x0}, - {0x9002d, 0x0}, - {0x9002e, 0x0}, - {0x9002f, 0x0}, - {0x90030, 0x0}, - {0x90031, 0x0}, - {0x90032, 0x0}, - {0x90033, 0x0}, - {0x90034, 0x0}, - {0x90035, 0x0}, - {0x90036, 0x0}, - {0x90037, 0x0}, - {0x90038, 0x0}, - {0x90039, 0x0}, - {0x9003a, 0x0}, - {0x9003b, 0x0}, - {0x9003c, 0x0}, - {0x9003d, 0x0}, - {0x9003e, 0x0}, - {0x9003f, 0x0}, - {0x90040, 0x0}, - {0x90041, 0x0}, - {0x90042, 0x0}, - {0x90043, 0x0}, - {0x90044, 0x0}, - {0x90045, 0x0}, - {0x90046, 0x0}, - {0x90047, 0x0}, - {0x90048, 0x0}, - {0x90049, 0x0}, - {0x9004a, 0x0}, - {0x9004b, 0x0}, - {0x9004c, 0x0}, - {0x9004d, 0x0}, - {0x9004e, 0x0}, - {0x9004f, 0x0}, - {0x90050, 0x0}, - {0x90051, 0x0}, - {0x90052, 0x0}, - {0x90053, 0x0}, - {0x90054, 0x0}, - {0x90055, 0x0}, - {0x90056, 0x0}, - {0x90057, 0x0}, - {0x90058, 0x0}, - {0x90059, 0x0}, - {0x9005a, 0x0}, - {0x9005b, 0x0}, - {0x9005c, 0x0}, - {0x9005d, 0x0}, - {0x9005e, 0x0}, - {0x9005f, 0x0}, - {0x90060, 0x0}, - {0x90061, 0x0}, - {0x90062, 0x0}, - {0x90063, 0x0}, - {0x90064, 0x0}, - {0x90065, 0x0}, - {0x90066, 0x0}, - {0x90067, 0x0}, - {0x90068, 0x0}, - {0x90069, 0x0}, - {0x9006a, 0x0}, - {0x9006b, 0x0}, - {0x9006c, 0x0}, - {0x9006d, 0x0}, - {0x9006e, 0x0}, - {0x9006f, 0x0}, - {0x90070, 0x0}, - {0x90071, 0x0}, - {0x90072, 0x0}, - {0x90073, 0x0}, - {0x90074, 0x0}, - {0x90075, 0x0}, - {0x90076, 0x0}, - {0x90077, 0x0}, - {0x90078, 0x0}, - {0x90079, 0x0}, - {0x9007a, 0x0}, - {0x9007b, 0x0}, - {0x9007c, 0x0}, - {0x9007d, 0x0}, - {0x9007e, 0x0}, - {0x9007f, 0x0}, - {0x90080, 0x0}, - {0x90081, 0x0}, - {0x90082, 0x0}, - {0x90083, 0x0}, - {0x90084, 0x0}, - {0x90085, 0x0}, - {0x90086, 0x0}, - {0x90087, 0x0}, - {0x90088, 0x0}, - {0x90089, 0x0}, - {0x9008a, 0x0}, - {0x9008b, 0x0}, - {0x9008c, 0x0}, - {0x9008d, 0x0}, - {0x9008e, 0x0}, - {0x9008f, 0x0}, - {0x90090, 0x0}, - {0x90091, 0x0}, - {0x90092, 0x0}, - {0x90093, 0x0}, - {0x90094, 0x0}, - {0x90095, 0x0}, - {0x90096, 0x0}, - {0x90097, 0x0}, - {0x90098, 0x0}, - {0x90099, 0x0}, - {0x9009a, 0x0}, - {0x9009b, 0x0}, - {0x9009c, 0x0}, - {0x9009d, 0x0}, - {0x9009e, 0x0}, - {0x9009f, 0x0}, - {0x900a0, 0x0}, - {0x900a1, 0x0}, - {0x900a2, 0x0}, - {0x900a3, 0x0}, - {0x900a4, 0x0}, - {0x900a5, 0x0}, - {0x900a6, 0x0}, - {0x900a7, 0x0}, - {0x900a8, 0x0}, - {0x900a9, 0x0}, - {0x40000, 0x0}, - {0x40020, 0x0}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x0}, - {0x40021, 0x0}, - {0x40041, 0x0}, - {0x40061, 0x0}, - {0x40002, 0x0}, - {0x40022, 0x0}, - {0x40042, 0x0}, - {0x40062, 0x0}, - {0x40003, 0x0}, - {0x40023, 0x0}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x0}, - {0x40024, 0x0}, - {0x40044, 0x0}, - {0x40064, 0x0}, - {0x40005, 0x0}, - {0x40025, 0x0}, - {0x40045, 0x0}, - {0x40065, 0x0}, - {0x40006, 0x0}, - {0x40026, 0x0}, - {0x40046, 0x0}, - {0x40066, 0x0}, - {0x40007, 0x0}, - {0x40027, 0x0}, - {0x40047, 0x0}, - {0x40067, 0x0}, - {0x40008, 0x0}, - {0x40028, 0x0}, - {0x40048, 0x0}, - {0x40068, 0x0}, - {0x40009, 0x0}, - {0x40029, 0x0}, - {0x40049, 0x0}, - {0x40069, 0x0}, - {0x4000a, 0x0}, - {0x4002a, 0x0}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x0}, - {0x4002b, 0x0}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x0}, - {0x4002c, 0x0}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0x0}, - {0x4002d, 0x0}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x0}, - {0x4002e, 0x0}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x0}, - {0x4002f, 0x0}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x0}, - {0x40030, 0x0}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x0}, - {0x40031, 0x0}, - {0x40051, 0x0}, - {0x40071, 0x0}, - {0x40012, 0x0}, - {0x40032, 0x0}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x0}, - {0x40033, 0x0}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x0}, - {0x40034, 0x0}, - {0x40054, 0x0}, - {0x40074, 0x0}, - {0x40015, 0x0}, - {0x40035, 0x0}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x0}, - {0x40036, 0x0}, - {0x40056, 0x0}, - {0x40076, 0x0}, - {0x40017, 0x0}, - {0x40037, 0x0}, - {0x40057, 0x0}, - {0x40077, 0x0}, - {0x40018, 0x0}, - {0x40038, 0x0}, - {0x40058, 0x0}, - {0x40078, 0x0}, - {0x40019, 0x0}, - {0x40039, 0x0}, - {0x40059, 0x0}, - {0x40079, 0x0}, - {0x4001a, 0x0}, - {0x4003a, 0x0}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x0}, - {0x900ac, 0x0}, - {0x900ad, 0x0}, - {0x900ae, 0x0}, - {0x900af, 0x0}, - {0x900b0, 0x0}, - {0x900b1, 0x0}, - {0x900b2, 0x0}, - {0x900b3, 0x0}, - {0x900b4, 0x0}, - {0x900b5, 0x0}, - {0x900b6, 0x0}, - {0x900b7, 0x0}, - {0x900b8, 0x0}, - {0x900b9, 0x0}, - {0x900ba, 0x0}, - {0x900bb, 0x0}, - {0x900bc, 0x0}, - {0x900bd, 0x0}, - {0x900be, 0x0}, - {0x900bf, 0x0}, - {0x900c0, 0x0}, - {0x900c1, 0x0}, - {0x900c2, 0x0}, - {0x900c3, 0x0}, - {0x900c4, 0x0}, - {0x900c5, 0x0}, - {0x900c6, 0x0}, - {0x900c7, 0x0}, - {0x900c8, 0x0}, - {0x900c9, 0x0}, - {0x900ca, 0x0}, - {0x900cb, 0x0}, - {0x900cc, 0x0}, - {0x900cd, 0x0}, - {0x900ce, 0x0}, - {0x900cf, 0x0}, - {0x900d0, 0x0}, - {0x900d1, 0x0}, - {0x900d2, 0x0}, - {0x900d3, 0x0}, - {0x900d4, 0x0}, - {0x900d5, 0x0}, - {0x900d6, 0x0}, - {0x900d7, 0x0}, - {0x900d8, 0x0}, - {0x900d9, 0x0}, - {0x900da, 0x0}, - {0x900db, 0x0}, - {0x900dc, 0x0}, - {0x900dd, 0x0}, - {0x900de, 0x0}, - {0x900df, 0x0}, - {0x900e0, 0x0}, - {0x900e1, 0x0}, - {0x900e2, 0x0}, - {0x900e3, 0x0}, - {0x900e4, 0x0}, - {0x900e5, 0x0}, - {0x900e6, 0x0}, - {0x900e7, 0x0}, - {0x900e8, 0x0}, - {0x900e9, 0x0}, - {0x900ea, 0x0}, - {0x900eb, 0x0}, - {0x900ec, 0x0}, - {0x900ed, 0x0}, - {0x900ee, 0x0}, - {0x900ef, 0x0}, - {0x900f0, 0x0}, - {0x900f1, 0x0}, - {0x900f2, 0x0}, - {0x900f3, 0x0}, - {0x900f4, 0x0}, - {0x900f5, 0x0}, - {0x900f6, 0x0}, - {0x900f7, 0x0}, - {0x900f8, 0x0}, - {0x900f9, 0x0}, - {0x900fa, 0x0}, - {0x900fb, 0x0}, - {0x900fc, 0x0}, - {0x900fd, 0x0}, - {0x900fe, 0x0}, - {0x900ff, 0x0}, - {0x90100, 0x0}, - {0x90101, 0x0}, - {0x90102, 0x0}, - {0x90103, 0x0}, - {0x90104, 0x0}, - {0x90105, 0x0}, - {0x90106, 0x0}, - {0x90107, 0x0}, - {0x90108, 0x0}, - {0x90109, 0x0}, - {0x9010a, 0x0}, - {0x9010b, 0x0}, - {0x9010c, 0x0}, - {0x9010d, 0x0}, - {0x9010e, 0x0}, - {0x9010f, 0x0}, - {0x90110, 0x0}, - {0x90111, 0x0}, - {0x90112, 0x0}, - {0x90113, 0x0}, - {0x90114, 0x0}, - {0x90115, 0x0}, - {0x90116, 0x0}, - {0x90117, 0x0}, - {0x90118, 0x0}, - {0x90119, 0x0}, - {0x9011a, 0x0}, - {0x9011b, 0x0}, - {0x9011c, 0x0}, - {0x9011d, 0x0}, - {0x9011e, 0x0}, - {0x9011f, 0x0}, - {0x90120, 0x0}, - {0x90121, 0x0}, - {0x90122, 0x0}, - {0x90123, 0x0}, - {0x90124, 0x0}, - {0x90125, 0x0}, - {0x90126, 0x0}, - {0x90127, 0x0}, - {0x90128, 0x0}, - {0x90129, 0x0}, - {0x9012a, 0x0}, - {0x9012b, 0x0}, - {0x9012c, 0x0}, - {0x9012d, 0x0}, - {0x9012e, 0x0}, - {0x9012f, 0x0}, - {0x90130, 0x0}, - {0x90131, 0x0}, - {0x90132, 0x0}, - {0x90133, 0x0}, - {0x90134, 0x0}, - {0x90135, 0x0}, - {0x90136, 0x0}, - {0x90137, 0x0}, - {0x90138, 0x0}, - {0x90139, 0x0}, - {0x9013a, 0x0}, - {0x9013b, 0x0}, - {0x9013c, 0x0}, - {0x9013d, 0x0}, - {0x9013e, 0x0}, - {0x9013f, 0x0}, - {0x90140, 0x0}, - {0x90141, 0x0}, - {0x90142, 0x0}, - {0x90143, 0x0}, - {0x90144, 0x0}, - {0x90145, 0x0}, - {0x90146, 0x0}, - {0x90147, 0x0}, - {0x90148, 0x0}, - {0x90149, 0x0}, - {0x9014a, 0x0}, - {0x9014b, 0x0}, - {0x9014c, 0x0}, - {0x9014d, 0x0}, - {0x9014e, 0x0}, - {0x9014f, 0x0}, - {0x90150, 0x0}, - {0x90151, 0x0}, - {0x90152, 0x0}, - {0x90153, 0x0}, - {0x90154, 0x0}, - {0x90155, 0x0}, - {0x90156, 0x0}, - {0x90157, 0x0}, - {0x90158, 0x0}, - {0x90159, 0x0}, - {0x9015a, 0x0}, - {0x9015b, 0x0}, - {0x9015c, 0x0}, - {0x9015d, 0x0}, - {0x9015e, 0x0}, - {0x9015f, 0x0}, - {0x90160, 0x0}, - {0x90161, 0x0}, - {0x90162, 0x0}, - {0x90163, 0x0}, - {0x90164, 0x0}, - {0x90165, 0x0}, - {0x90166, 0x0}, - {0x90167, 0x0}, - {0x90168, 0x0}, - {0x90169, 0x0}, - {0x9016a, 0x0}, - {0x9016b, 0x0}, - {0x9016c, 0x0}, - {0x9016d, 0x0}, - {0x9016e, 0x0}, - {0x9016f, 0x0}, - {0x90170, 0x0}, - {0x90171, 0x0}, - {0x90172, 0x0}, - {0x90173, 0x0}, - {0x90174, 0x0}, - {0x90175, 0x0}, - {0x90176, 0x0}, - {0x90177, 0x0}, - {0x90178, 0x0}, - {0x90179, 0x0}, - {0x9017a, 0x0}, - {0x9017b, 0x0}, - {0x9017c, 0x0}, - {0x9017d, 0x0}, - {0x9017e, 0x0}, - {0x9017f, 0x0}, - {0x90180, 0x0}, - {0x90181, 0x0}, - {0x90182, 0x0}, - {0x90183, 0x0}, - {0x90184, 0x0}, - {0x90006, 0x0}, - {0x90007, 0x0}, - {0x90008, 0x0}, - {0x90009, 0x0}, - {0x9000a, 0x0}, - {0x9000b, 0x0}, - {0xd00e7, 0x0}, - {0x90017, 0x0}, - {0x9001f, 0x0}, - {0x90026, 0x0}, - {0x400d0, 0x0}, - {0x400d1, 0x0}, - {0x400d2, 0x0}, - {0x400d3, 0x0}, - {0x400d4, 0x0}, - {0x400d5, 0x0}, - {0x400d6, 0x0}, - {0x400d7, 0x0}, - {0x200be, 0x0}, - {0x2000b, 0x0}, - {0x2000c, 0x0}, - {0x2000d, 0x0}, - {0x2000e, 0x0}, - {0x12000b, 0x0}, - {0x12000c, 0x0}, - {0x12000d, 0x0}, - {0x12000e, 0x0}, - {0x22000b, 0x0}, - {0x22000c, 0x0}, - {0x22000d, 0x0}, - {0x22000e, 0x0}, - {0x9000c, 0x0}, - {0x9000d, 0x0}, - {0x9000e, 0x0}, - {0x9000f, 0x0}, - {0x90010, 0x0}, - {0x90011, 0x0}, - {0x90012, 0x0}, - {0x90013, 0x0}, - {0x20010, 0x0}, - {0x20011, 0x0}, - {0x120010, 0x0}, - {0x120011, 0x0}, - {0x40080, 0x0}, - {0x40081, 0x0}, - {0x40082, 0x0}, - {0x40083, 0x0}, - {0x40084, 0x0}, - {0x40085, 0x0}, - {0x140080, 0x0}, - {0x140081, 0x0}, - {0x140082, 0x0}, - {0x140083, 0x0}, - {0x140084, 0x0}, - {0x140085, 0x0}, - {0x240080, 0x0}, - {0x240081, 0x0}, - {0x240082, 0x0}, - {0x240083, 0x0}, - {0x240084, 0x0}, - {0x240085, 0x0}, - {0x400fd, 0x0}, - {0x400f1, 0x0}, - {0x10011, 0x0}, - {0x10012, 0x0}, - {0x10013, 0x0}, - {0x10018, 0x0}, - {0x10002, 0x0}, - {0x100b2, 0x0}, - {0x101b4, 0x0}, - {0x102b4, 0x0}, - {0x103b4, 0x0}, - {0x104b4, 0x0}, - {0x105b4, 0x0}, - {0x106b4, 0x0}, - {0x107b4, 0x0}, - {0x108b4, 0x0}, - {0x11011, 0x0}, - {0x11012, 0x0}, - {0x11013, 0x0}, - {0x11018, 0x0}, - {0x11002, 0x0}, - {0x110b2, 0x0}, - {0x111b4, 0x0}, - {0x112b4, 0x0}, - {0x113b4, 0x0}, - {0x114b4, 0x0}, - {0x115b4, 0x0}, - {0x116b4, 0x0}, - {0x117b4, 0x0}, - {0x118b4, 0x0}, - {0x20089, 0x0}, - {0xc0080, 0x0}, - {0x200cb, 0x0}, - {0x10068, 0x0}, - {0x10069, 0x0}, - {0x10168, 0x0}, - {0x10169, 0x0}, - {0x10268, 0x0}, - {0x10269, 0x0}, - {0x10368, 0x0}, - {0x10369, 0x0}, - {0x10468, 0x0}, - {0x10469, 0x0}, - {0x10568, 0x0}, - {0x10569, 0x0}, - {0x10668, 0x0}, - {0x10669, 0x0}, - {0x10768, 0x0}, - {0x10769, 0x0}, - {0x10868, 0x0}, - {0x10869, 0x0}, - {0x100aa, 0x0}, - {0x10062, 0x0}, - {0x10001, 0x0}, - {0x100a0, 0x0}, - {0x100a1, 0x0}, - {0x100a2, 0x0}, - {0x100a3, 0x0}, - {0x100a4, 0x0}, - {0x100a5, 0x0}, - {0x100a6, 0x0}, - {0x100a7, 0x0}, - {0x11068, 0x0}, - {0x11069, 0x0}, - {0x11168, 0x0}, - {0x11169, 0x0}, - {0x11268, 0x0}, - {0x11269, 0x0}, - {0x11368, 0x0}, - {0x11369, 0x0}, - {0x11468, 0x0}, - {0x11469, 0x0}, - {0x11568, 0x0}, - {0x11569, 0x0}, - {0x11668, 0x0}, - {0x11669, 0x0}, - {0x11768, 0x0}, - {0x11769, 0x0}, - {0x11868, 0x0}, - {0x11869, 0x0}, - {0x110aa, 0x0}, - {0x11062, 0x0}, - {0x11001, 0x0}, - {0x110a0, 0x0}, - {0x110a1, 0x0}, - {0x110a2, 0x0}, - {0x110a3, 0x0}, - {0x110a4, 0x0}, - {0x110a5, 0x0}, - {0x110a6, 0x0}, - {0x110a7, 0x0}, - {0x80, 0x0}, - {0x1080, 0x0}, - {0x2080, 0x0}, - {0x10020, 0x0}, - {0x10080, 0x0}, - {0x10081, 0x0}, - {0x100d0, 0x0}, - {0x100d1, 0x0}, - {0x1008c, 0x0}, - {0x1008d, 0x0}, - {0x10180, 0x0}, - {0x10181, 0x0}, - {0x101d0, 0x0}, - {0x101d1, 0x0}, - {0x1018c, 0x0}, - {0x1018d, 0x0}, - {0x100c0, 0x0}, - {0x100c1, 0x0}, - {0x101c0, 0x0}, - {0x101c1, 0x0}, - {0x102c0, 0x0}, - {0x102c1, 0x0}, - {0x103c0, 0x0}, - {0x103c1, 0x0}, - {0x104c0, 0x0}, - {0x104c1, 0x0}, - {0x105c0, 0x0}, - {0x105c1, 0x0}, - {0x106c0, 0x0}, - {0x106c1, 0x0}, - {0x107c0, 0x0}, - {0x107c1, 0x0}, - {0x108c0, 0x0}, - {0x108c1, 0x0}, - {0x100ae, 0x0}, - {0x100af, 0x0}, - {0x11020, 0x0}, - {0x11080, 0x0}, - {0x11081, 0x0}, - {0x110d0, 0x0}, - {0x110d1, 0x0}, - {0x1108c, 0x0}, - {0x1108d, 0x0}, - {0x11180, 0x0}, - {0x11181, 0x0}, - {0x111d0, 0x0}, - {0x111d1, 0x0}, - {0x1118c, 0x0}, - {0x1118d, 0x0}, - {0x110c0, 0x0}, - {0x110c1, 0x0}, - {0x111c0, 0x0}, - {0x111c1, 0x0}, - {0x112c0, 0x0}, - {0x112c1, 0x0}, - {0x113c0, 0x0}, - {0x113c1, 0x0}, - {0x114c0, 0x0}, - {0x114c1, 0x0}, - {0x115c0, 0x0}, - {0x115c1, 0x0}, - {0x116c0, 0x0}, - {0x116c1, 0x0}, - {0x117c0, 0x0}, - {0x117c1, 0x0}, - {0x118c0, 0x0}, - {0x118c1, 0x0}, - {0x110ae, 0x0}, - {0x110af, 0x0}, - {0x90201, 0x0}, - {0x90202, 0x0}, - {0x90203, 0x0}, - {0x90205, 0x0}, - {0x90206, 0x0}, - {0x90207, 0x0}, - {0x90208, 0x0}, - {0x20020, 0x0}, - {0x100080, 0x0}, - {0x101080, 0x0}, - {0x102080, 0x0}, - {0x110020, 0x0}, - {0x110080, 0x0}, - {0x110081, 0x0}, - {0x1100d0, 0x0}, - {0x1100d1, 0x0}, - {0x11008c, 0x0}, - {0x11008d, 0x0}, - {0x110180, 0x0}, - {0x110181, 0x0}, - {0x1101d0, 0x0}, - {0x1101d1, 0x0}, - {0x11018c, 0x0}, - {0x11018d, 0x0}, - {0x1100c0, 0x0}, - {0x1100c1, 0x0}, - {0x1101c0, 0x0}, - {0x1101c1, 0x0}, - {0x1102c0, 0x0}, - {0x1102c1, 0x0}, - {0x1103c0, 0x0}, - {0x1103c1, 0x0}, - {0x1104c0, 0x0}, - {0x1104c1, 0x0}, - {0x1105c0, 0x0}, - {0x1105c1, 0x0}, - {0x1106c0, 0x0}, - {0x1106c1, 0x0}, - {0x1107c0, 0x0}, - {0x1107c1, 0x0}, - {0x1108c0, 0x0}, - {0x1108c1, 0x0}, - {0x1100ae, 0x0}, - {0x1100af, 0x0}, - {0x111020, 0x0}, - {0x111080, 0x0}, - {0x111081, 0x0}, - {0x1110d0, 0x0}, - {0x1110d1, 0x0}, - {0x11108c, 0x0}, - {0x11108d, 0x0}, - {0x111180, 0x0}, - {0x111181, 0x0}, - {0x1111d0, 0x0}, - {0x1111d1, 0x0}, - {0x11118c, 0x0}, - {0x11118d, 0x0}, - {0x1110c0, 0x0}, - {0x1110c1, 0x0}, - {0x1111c0, 0x0}, - {0x1111c1, 0x0}, - {0x1112c0, 0x0}, - {0x1112c1, 0x0}, - {0x1113c0, 0x0}, - {0x1113c1, 0x0}, - {0x1114c0, 0x0}, - {0x1114c1, 0x0}, - {0x1115c0, 0x0}, - {0x1115c1, 0x0}, - {0x1116c0, 0x0}, - {0x1116c1, 0x0}, - {0x1117c0, 0x0}, - {0x1117c1, 0x0}, - {0x1118c0, 0x0}, - {0x1118c1, 0x0}, - {0x1110ae, 0x0}, - {0x1110af, 0x0}, - {0x190201, 0x0}, - {0x190202, 0x0}, - {0x190203, 0x0}, - {0x190205, 0x0}, - {0x190206, 0x0}, - {0x190207, 0x0}, - {0x190208, 0x0}, - {0x120020, 0x0}, - {0x200080, 0x0}, - {0x201080, 0x0}, - {0x202080, 0x0}, - {0x210020, 0x0}, - {0x210080, 0x0}, - {0x210081, 0x0}, - {0x2100d0, 0x0}, - {0x2100d1, 0x0}, - {0x21008c, 0x0}, - {0x21008d, 0x0}, - {0x210180, 0x0}, - {0x210181, 0x0}, - {0x2101d0, 0x0}, - {0x2101d1, 0x0}, - {0x21018c, 0x0}, - {0x21018d, 0x0}, - {0x2100c0, 0x0}, - {0x2100c1, 0x0}, - {0x2101c0, 0x0}, - {0x2101c1, 0x0}, - {0x2102c0, 0x0}, - {0x2102c1, 0x0}, - {0x2103c0, 0x0}, - {0x2103c1, 0x0}, - {0x2104c0, 0x0}, - {0x2104c1, 0x0}, - {0x2105c0, 0x0}, - {0x2105c1, 0x0}, - {0x2106c0, 0x0}, - {0x2106c1, 0x0}, - {0x2107c0, 0x0}, - {0x2107c1, 0x0}, - {0x2108c0, 0x0}, - {0x2108c1, 0x0}, - {0x2100ae, 0x0}, - {0x2100af, 0x0}, - {0x211020, 0x0}, - {0x211080, 0x0}, - {0x211081, 0x0}, - {0x2110d0, 0x0}, - {0x2110d1, 0x0}, - {0x21108c, 0x0}, - {0x21108d, 0x0}, - {0x211180, 0x0}, - {0x211181, 0x0}, - {0x2111d0, 0x0}, - {0x2111d1, 0x0}, - {0x21118c, 0x0}, - {0x21118d, 0x0}, - {0x2110c0, 0x0}, - {0x2110c1, 0x0}, - {0x2111c0, 0x0}, - {0x2111c1, 0x0}, - {0x2112c0, 0x0}, - {0x2112c1, 0x0}, - {0x2113c0, 0x0}, - {0x2113c1, 0x0}, - {0x2114c0, 0x0}, - {0x2114c1, 0x0}, - {0x2115c0, 0x0}, - {0x2115c1, 0x0}, - {0x2116c0, 0x0}, - {0x2116c1, 0x0}, - {0x2117c0, 0x0}, - {0x2117c1, 0x0}, - {0x2118c0, 0x0}, - {0x2118c1, 0x0}, - {0x2110ae, 0x0}, - {0x2110af, 0x0}, - {0x290201, 0x0}, - {0x290202, 0x0}, - {0x290203, 0x0}, - {0x290205, 0x0}, - {0x290206, 0x0}, - {0x290207, 0x0}, - {0x290208, 0x0}, - {0x220020, 0x0}, - {0x20077, 0x0}, - {0x20072, 0x0}, - {0x20073, 0x0}, - {0x400c0, 0x0}, - {0x10040, 0x0}, - {0x10140, 0x0}, - {0x10240, 0x0}, - {0x10340, 0x0}, - {0x10440, 0x0}, - {0x10540, 0x0}, - {0x10640, 0x0}, - {0x10740, 0x0}, - {0x10840, 0x0}, - {0x11040, 0x0}, - {0x11140, 0x0}, - {0x11240, 0x0}, - {0x11340, 0x0}, - {0x11440, 0x0}, - {0x11540, 0x0}, - {0x11640, 0x0}, - {0x11740, 0x0}, - {0x11840, 0x0}, -}; - -/* P0 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0x960}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x131f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x24c4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x24c4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xc400}, - {0x54033, 0x3324}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xc400}, - {0x54039, 0x3324}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P1 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp1_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x1}, - {0x54003, 0x4b0}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x52a4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x52a4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xa400}, - {0x54033, 0x3352}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xa400}, - {0x54039, 0x3352}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P2 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp2_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x102}, - {0x54003, 0x270}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x994}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4800}, - {0x5401e, 0x4}, - {0x5401f, 0x994}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4800}, - {0x54024, 0x4}, - {0x54032, 0x9400}, - {0x54033, 0x3309}, - {0x54034, 0x4600}, - {0x54035, 0x11}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0x9400}, - {0x54039, 0x3309}, - {0x5403a, 0x4600}, - {0x5403b, 0x11}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P0 2D message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0x960}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x61}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54010, 0x2080}, - {0x54012, 0x110}, - {0x54019, 0x24c4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x24c4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xc400}, - {0x54033, 0x3324}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xc400}, - {0x54039, 0x3324}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* DRAM PHY init engine image */ -static struct dram_cfg_param ddr_phy_pie[] = { - {0xd0000, 0x0}, - {0x90000, 0x10}, - {0x90001, 0x400}, - {0x90002, 0x10e}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x8}, - {0x90029, 0xb}, - {0x9002a, 0x480}, - {0x9002b, 0x109}, - {0x9002c, 0x8}, - {0x9002d, 0x448}, - {0x9002e, 0x139}, - {0x9002f, 0x8}, - {0x90030, 0x478}, - {0x90031, 0x109}, - {0x90032, 0x0}, - {0x90033, 0xe8}, - {0x90034, 0x109}, - {0x90035, 0x2}, - {0x90036, 0x10}, - {0x90037, 0x139}, - {0x90038, 0xb}, - {0x90039, 0x7c0}, - {0x9003a, 0x139}, - {0x9003b, 0x44}, - {0x9003c, 0x633}, - {0x9003d, 0x159}, - {0x9003e, 0x14f}, - {0x9003f, 0x630}, - {0x90040, 0x159}, - {0x90041, 0x47}, - {0x90042, 0x633}, - {0x90043, 0x149}, - {0x90044, 0x4f}, - {0x90045, 0x633}, - {0x90046, 0x179}, - {0x90047, 0x8}, - {0x90048, 0xe0}, - {0x90049, 0x109}, - {0x9004a, 0x0}, - {0x9004b, 0x7c8}, - {0x9004c, 0x109}, - {0x9004d, 0x0}, - {0x9004e, 0x1}, - {0x9004f, 0x8}, - {0x90050, 0x30}, - {0x90051, 0x65a}, - {0x90052, 0x9}, - {0x90053, 0x0}, - {0x90054, 0x45a}, - {0x90055, 0x9}, - {0x90056, 0x0}, - {0x90057, 0x448}, - {0x90058, 0x109}, - {0x90059, 0x40}, - {0x9005a, 0x633}, - {0x9005b, 0x179}, - {0x9005c, 0x1}, - {0x9005d, 0x618}, - {0x9005e, 0x109}, - {0x9005f, 0x40c0}, - {0x90060, 0x633}, - {0x90061, 0x149}, - {0x90062, 0x8}, - {0x90063, 0x4}, - {0x90064, 0x48}, - {0x90065, 0x4040}, - {0x90066, 0x633}, - {0x90067, 0x149}, - {0x90068, 0x0}, - {0x90069, 0x4}, - {0x9006a, 0x48}, - {0x9006b, 0x40}, - {0x9006c, 0x633}, - {0x9006d, 0x149}, - {0x9006e, 0x0}, - {0x9006f, 0x658}, - {0x90070, 0x109}, - {0x90071, 0x10}, - {0x90072, 0x4}, - {0x90073, 0x18}, - {0x90074, 0x0}, - {0x90075, 0x4}, - {0x90076, 0x78}, - {0x90077, 0x549}, - {0x90078, 0x633}, - {0x90079, 0x159}, - {0x9007a, 0xd49}, - {0x9007b, 0x633}, - {0x9007c, 0x159}, - {0x9007d, 0x94a}, - {0x9007e, 0x633}, - {0x9007f, 0x159}, - {0x90080, 0x441}, - {0x90081, 0x633}, - {0x90082, 0x149}, - {0x90083, 0x42}, - {0x90084, 0x633}, - {0x90085, 0x149}, - {0x90086, 0x1}, - {0x90087, 0x633}, - {0x90088, 0x149}, - {0x90089, 0x0}, - {0x9008a, 0xe0}, - {0x9008b, 0x109}, - {0x9008c, 0xa}, - {0x9008d, 0x10}, - {0x9008e, 0x109}, - {0x9008f, 0x9}, - {0x90090, 0x3c0}, - {0x90091, 0x149}, - {0x90092, 0x9}, - {0x90093, 0x3c0}, - {0x90094, 0x159}, - {0x90095, 0x18}, - {0x90096, 0x10}, - {0x90097, 0x109}, - {0x90098, 0x0}, - {0x90099, 0x3c0}, - {0x9009a, 0x109}, - {0x9009b, 0x18}, - {0x9009c, 0x4}, - {0x9009d, 0x48}, - {0x9009e, 0x18}, - {0x9009f, 0x4}, - {0x900a0, 0x58}, - {0x900a1, 0xb}, - {0x900a2, 0x10}, - {0x900a3, 0x109}, - {0x900a4, 0x1}, - {0x900a5, 0x10}, - {0x900a6, 0x109}, - {0x900a7, 0x5}, - {0x900a8, 0x7c0}, - {0x900a9, 0x109}, - {0x40000, 0x811}, - {0x40020, 0x880}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x4008}, - {0x40021, 0x83}, - {0x40041, 0x4f}, - {0x40061, 0x0}, - {0x40002, 0x4040}, - {0x40022, 0x83}, - {0x40042, 0x51}, - {0x40062, 0x0}, - {0x40003, 0x811}, - {0x40023, 0x880}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x720}, - {0x40024, 0xf}, - {0x40044, 0x1740}, - {0x40064, 0x0}, - {0x40005, 0x16}, - {0x40025, 0x83}, - {0x40045, 0x4b}, - {0x40065, 0x0}, - {0x40006, 0x716}, - {0x40026, 0xf}, - {0x40046, 0x2001}, - {0x40066, 0x0}, - {0x40007, 0x716}, - {0x40027, 0xf}, - {0x40047, 0x2800}, - {0x40067, 0x0}, - {0x40008, 0x716}, - {0x40028, 0xf}, - {0x40048, 0xf00}, - {0x40068, 0x0}, - {0x40009, 0x720}, - {0x40029, 0xf}, - {0x40049, 0x1400}, - {0x40069, 0x0}, - {0x4000a, 0xe08}, - {0x4002a, 0xc15}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x625}, - {0x4002b, 0x15}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x4028}, - {0x4002c, 0x80}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0xe08}, - {0x4002d, 0xc1a}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x625}, - {0x4002e, 0x1a}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x4040}, - {0x4002f, 0x80}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x2604}, - {0x40030, 0x15}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x708}, - {0x40031, 0x5}, - {0x40051, 0x0}, - {0x40071, 0x2002}, - {0x40012, 0x8}, - {0x40032, 0x80}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x2604}, - {0x40033, 0x1a}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x708}, - {0x40034, 0xa}, - {0x40054, 0x0}, - {0x40074, 0x2002}, - {0x40015, 0x4040}, - {0x40035, 0x80}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x60a}, - {0x40036, 0x15}, - {0x40056, 0x1200}, - {0x40076, 0x0}, - {0x40017, 0x61a}, - {0x40037, 0x15}, - {0x40057, 0x1300}, - {0x40077, 0x0}, - {0x40018, 0x60a}, - {0x40038, 0x1a}, - {0x40058, 0x1200}, - {0x40078, 0x0}, - {0x40019, 0x642}, - {0x40039, 0x1a}, - {0x40059, 0x1300}, - {0x40079, 0x0}, - {0x4001a, 0x4808}, - {0x4003a, 0x880}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x790}, - {0x900ac, 0x11a}, - {0x900ad, 0x8}, - {0x900ae, 0x7aa}, - {0x900af, 0x2a}, - {0x900b0, 0x10}, - {0x900b1, 0x7b2}, - {0x900b2, 0x2a}, - {0x900b3, 0x0}, - {0x900b4, 0x7c8}, - {0x900b5, 0x109}, - {0x900b6, 0x10}, - {0x900b7, 0x10}, - {0x900b8, 0x109}, - {0x900b9, 0x10}, - {0x900ba, 0x2a8}, - {0x900bb, 0x129}, - {0x900bc, 0x8}, - {0x900bd, 0x370}, - {0x900be, 0x129}, - {0x900bf, 0xa}, - {0x900c0, 0x3c8}, - {0x900c1, 0x1a9}, - {0x900c2, 0xc}, - {0x900c3, 0x408}, - {0x900c4, 0x199}, - {0x900c5, 0x14}, - {0x900c6, 0x790}, - {0x900c7, 0x11a}, - {0x900c8, 0x8}, - {0x900c9, 0x4}, - {0x900ca, 0x18}, - {0x900cb, 0xe}, - {0x900cc, 0x408}, - {0x900cd, 0x199}, - {0x900ce, 0x8}, - {0x900cf, 0x8568}, - {0x900d0, 0x108}, - {0x900d1, 0x18}, - {0x900d2, 0x790}, - {0x900d3, 0x16a}, - {0x900d4, 0x8}, - {0x900d5, 0x1d8}, - {0x900d6, 0x169}, - {0x900d7, 0x10}, - {0x900d8, 0x8558}, - {0x900d9, 0x168}, - {0x900da, 0x1ff8}, - {0x900db, 0x85a8}, - {0x900dc, 0x1e8}, - {0x900dd, 0x50}, - {0x900de, 0x798}, - {0x900df, 0x16a}, - {0x900e0, 0x60}, - {0x900e1, 0x7a0}, - {0x900e2, 0x16a}, - {0x900e3, 0x8}, - {0x900e4, 0x8310}, - {0x900e5, 0x168}, - {0x900e6, 0x8}, - {0x900e7, 0xa310}, - {0x900e8, 0x168}, - {0x900e9, 0xa}, - {0x900ea, 0x408}, - {0x900eb, 0x169}, - {0x900ec, 0x6e}, - {0x900ed, 0x0}, - {0x900ee, 0x68}, - {0x900ef, 0x0}, - {0x900f0, 0x408}, - {0x900f1, 0x169}, - {0x900f2, 0x0}, - {0x900f3, 0x8310}, - {0x900f4, 0x168}, - {0x900f5, 0x0}, - {0x900f6, 0xa310}, - {0x900f7, 0x168}, - {0x900f8, 0x1ff8}, - {0x900f9, 0x85a8}, - {0x900fa, 0x1e8}, - {0x900fb, 0x68}, - {0x900fc, 0x798}, - {0x900fd, 0x16a}, - {0x900fe, 0x78}, - {0x900ff, 0x7a0}, - {0x90100, 0x16a}, - {0x90101, 0x68}, - {0x90102, 0x790}, - {0x90103, 0x16a}, - {0x90104, 0x8}, - {0x90105, 0x8b10}, - {0x90106, 0x168}, - {0x90107, 0x8}, - {0x90108, 0xab10}, - {0x90109, 0x168}, - {0x9010a, 0xa}, - {0x9010b, 0x408}, - {0x9010c, 0x169}, - {0x9010d, 0x58}, - {0x9010e, 0x0}, - {0x9010f, 0x68}, - {0x90110, 0x0}, - {0x90111, 0x408}, - {0x90112, 0x169}, - {0x90113, 0x0}, - {0x90114, 0x8b10}, - {0x90115, 0x168}, - {0x90116, 0x1}, - {0x90117, 0xab10}, - {0x90118, 0x168}, - {0x90119, 0x0}, - {0x9011a, 0x1d8}, - {0x9011b, 0x169}, - {0x9011c, 0x80}, - {0x9011d, 0x790}, - {0x9011e, 0x16a}, - {0x9011f, 0x18}, - {0x90120, 0x7aa}, - {0x90121, 0x6a}, - {0x90122, 0xa}, - {0x90123, 0x0}, - {0x90124, 0x1e9}, - {0x90125, 0x8}, - {0x90126, 0x8080}, - {0x90127, 0x108}, - {0x90128, 0xf}, - {0x90129, 0x408}, - {0x9012a, 0x169}, - {0x9012b, 0xc}, - {0x9012c, 0x0}, - {0x9012d, 0x68}, - {0x9012e, 0x9}, - {0x9012f, 0x0}, - {0x90130, 0x1a9}, - {0x90131, 0x0}, - {0x90132, 0x408}, - {0x90133, 0x169}, - {0x90134, 0x0}, - {0x90135, 0x8080}, - {0x90136, 0x108}, - {0x90137, 0x8}, - {0x90138, 0x7aa}, - {0x90139, 0x6a}, - {0x9013a, 0x0}, - {0x9013b, 0x8568}, - {0x9013c, 0x108}, - {0x9013d, 0xb7}, - {0x9013e, 0x790}, - {0x9013f, 0x16a}, - {0x90140, 0x1f}, - {0x90141, 0x0}, - {0x90142, 0x68}, - {0x90143, 0x8}, - {0x90144, 0x8558}, - {0x90145, 0x168}, - {0x90146, 0xf}, - {0x90147, 0x408}, - {0x90148, 0x169}, - {0x90149, 0xd}, - {0x9014a, 0x0}, - {0x9014b, 0x68}, - {0x9014c, 0x0}, - {0x9014d, 0x408}, - {0x9014e, 0x169}, - {0x9014f, 0x0}, - {0x90150, 0x8558}, - {0x90151, 0x168}, - {0x90152, 0x8}, - {0x90153, 0x3c8}, - {0x90154, 0x1a9}, - {0x90155, 0x3}, - {0x90156, 0x370}, - {0x90157, 0x129}, - {0x90158, 0x20}, - {0x90159, 0x2aa}, - {0x9015a, 0x9}, - {0x9015b, 0x8}, - {0x9015c, 0xe8}, - {0x9015d, 0x109}, - {0x9015e, 0x0}, - {0x9015f, 0x8140}, - {0x90160, 0x10c}, - {0x90161, 0x10}, - {0x90162, 0x8138}, - {0x90163, 0x104}, - {0x90164, 0x8}, - {0x90165, 0x448}, - {0x90166, 0x109}, - {0x90167, 0xf}, - {0x90168, 0x7c0}, - {0x90169, 0x109}, - {0x9016a, 0x0}, - {0x9016b, 0xe8}, - {0x9016c, 0x109}, - {0x9016d, 0x47}, - {0x9016e, 0x630}, - {0x9016f, 0x109}, - {0x90170, 0x8}, - {0x90171, 0x618}, - {0x90172, 0x109}, - {0x90173, 0x8}, - {0x90174, 0xe0}, - {0x90175, 0x109}, - {0x90176, 0x0}, - {0x90177, 0x7c8}, - {0x90178, 0x109}, - {0x90179, 0x8}, - {0x9017a, 0x8140}, - {0x9017b, 0x10c}, - {0x9017c, 0x0}, - {0x9017d, 0x478}, - {0x9017e, 0x109}, - {0x9017f, 0x0}, - {0x90180, 0x1}, - {0x90181, 0x8}, - {0x90182, 0x8}, - {0x90183, 0x4}, - {0x90184, 0x0}, - {0x90006, 0x8}, - {0x90007, 0x7c8}, - {0x90008, 0x109}, - {0x90009, 0x0}, - {0x9000a, 0x400}, - {0x9000b, 0x106}, - {0xd00e7, 0x400}, - {0x90017, 0x0}, - {0x9001f, 0x2b}, - {0x90026, 0x69}, - {0x400d0, 0x0}, - {0x400d1, 0x101}, - {0x400d2, 0x105}, - {0x400d3, 0x107}, - {0x400d4, 0x10f}, - {0x400d5, 0x202}, - {0x400d6, 0x20a}, - {0x400d7, 0x20b}, - {0x2003a, 0x2}, - {0x200be, 0x3}, - {0x2000b, 0x2a3}, - {0x2000c, 0x96}, - {0x2000d, 0x5dc}, - {0x2000e, 0x2c}, - {0x12000b, 0x152}, - {0x12000c, 0x4b}, - {0x12000d, 0x2ee}, - {0x12000e, 0x2c}, - {0x22000b, 0xb0}, - {0x22000c, 0x27}, - {0x22000d, 0x186}, - {0x22000e, 0x10}, - {0x9000c, 0x0}, - {0x9000d, 0x173}, - {0x9000e, 0x60}, - {0x9000f, 0x6110}, - {0x90010, 0x2152}, - {0x90011, 0xdfbd}, - {0x90012, 0x2060}, - {0x90013, 0x6152}, - {0x20010, 0x5a}, - {0x20011, 0x3}, - {0x120010, 0x5a}, - {0x120011, 0x3}, - {0x40080, 0xe0}, - {0x40081, 0x12}, - {0x40082, 0xe0}, - {0x40083, 0x12}, - {0x40084, 0xe0}, - {0x40085, 0x12}, - {0x140080, 0xe0}, - {0x140081, 0x12}, - {0x140082, 0xe0}, - {0x140083, 0x12}, - {0x140084, 0xe0}, - {0x140085, 0x12}, - {0x240080, 0xe0}, - {0x240081, 0x12}, - {0x240082, 0xe0}, - {0x240083, 0x12}, - {0x240084, 0xe0}, - {0x240085, 0x12}, - {0x400fd, 0xf}, - {0x400f1, 0xe}, - {0x10011, 0x1}, - {0x10012, 0x1}, - {0x10013, 0x180}, - {0x10018, 0x1}, - {0x10002, 0x6209}, - {0x100b2, 0x1}, - {0x101b4, 0x1}, - {0x102b4, 0x1}, - {0x103b4, 0x1}, - {0x104b4, 0x1}, - {0x105b4, 0x1}, - {0x106b4, 0x1}, - {0x107b4, 0x1}, - {0x108b4, 0x1}, - {0x11011, 0x1}, - {0x11012, 0x1}, - {0x11013, 0x180}, - {0x11018, 0x1}, - {0x11002, 0x6209}, - {0x110b2, 0x1}, - {0x111b4, 0x1}, - {0x112b4, 0x1}, - {0x113b4, 0x1}, - {0x114b4, 0x1}, - {0x115b4, 0x1}, - {0x116b4, 0x1}, - {0x117b4, 0x1}, - {0x118b4, 0x1}, - {0x20089, 0x1}, - {0x20088, 0x19}, - {0xc0080, 0x0}, - {0xd0000, 0x1}, -}; - -static struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 2400mts 1D */ - .drate = 2400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 1200mts 1D */ - .drate = 1200, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 625mts 1D */ - .drate = 625, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 2400mts 2D */ - .drate = 2400, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing_1GB = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 2400, 1200, 625, }, - .fsp_cfg = ddr_dram_fsp_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), -}; diff --git a/board/freescale/imx91_frdm/lpddr4_2400mts_2gb_timing.c b/board/freescale/imx91_frdm/lpddr4_2400mts_2gb_timing.c deleted file mode 100644 index 017677fbbe9..00000000000 --- a/board/freescale/imx91_frdm/lpddr4_2400mts_2gb_timing.c +++ /dev/null @@ -1,1996 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright 2025 NXP - * - * Code generated with DDR Tool v3.3.0_1.8-d1cdb7d3. - * DDR PHY FW2022.01 - */ - -#include -#include - -/* Initialize DDRC registers */ -static struct dram_cfg_param ddr_ddrc_cfg[] = { - {0x4e300110, 0x44100001}, - {0x4e300000, 0x8000ff}, - {0x4e300008, 0x0}, - {0x4e300080, 0x80000512}, - {0x4e300084, 0x0}, - {0x4e300114, 0x1002}, - {0x4e300260, 0x80}, - {0x4e300f04, 0x80}, - {0x4e300800, 0x43b30002}, - {0x4e300804, 0x1f1f1f1f}, - {0x4e301000, 0x0}, - {0x4e301240, 0x0}, - {0x4e301244, 0x0}, - {0x4e301248, 0x0}, - {0x4e30124c, 0x0}, - {0x4e301250, 0x0}, - {0x4e301254, 0x0}, - {0x4e301258, 0x0}, - {0x4e30125c, 0x0}, -}; - -/* dram fsp cfg */ -static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { - { - { - {0x4e300100, 0x135C2110}, - {0x4e300104, 0xF8990011}, - {0x4e300108, 0x636E08CC}, - {0x4e30010C, 0x00614070}, - {0x4e300124, 0x124E0000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x31D00000}, - {0x4e300170, 0x8B0B0608}, - {0x4e300250, 0x0000001A}, - {0x4e300254, 0x00DC00DC}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - {0x4e300300, 0x1633160D}, - {0x4e300304, 0x00DC180C}, - {0x4e300308, 0x0C280927}, - }, - { - {0x01, 0xC4}, - {0x02, 0x24}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x010D1100}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0xBABAC068}, - {0x4e30010C, 0x00610158}, - {0x4e300124, 0x09270000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30400000}, - {0x4e300170, 0x8A0A0508}, - {0x4e300250, 0x0000000D}, - {0x4e300254, 0x006A006A}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0xA4}, - {0x02, 0x52}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x00061000}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0x6E62FA48}, - {0x4e30010C, 0x0031010D}, - {0x4e300124, 0x04C50000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30000000}, - {0x4e300170, 0x89090408}, - {0x4e300250, 0x00000007}, - {0x4e300254, 0x00340034}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0x94}, - {0x02, 0x9}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 1, - }, - -}; - -/* PHY Initialize Configuration */ -static struct dram_cfg_param ddr_ddrphy_cfg[] = { - {0x100a0, 0x4}, - {0x100a1, 0x5}, - {0x100a2, 0x6}, - {0x100a3, 0x7}, - {0x100a4, 0x0}, - {0x100a5, 0x1}, - {0x100a6, 0x2}, - {0x100a7, 0x3}, - {0x110a0, 0x3}, - {0x110a1, 0x2}, - {0x110a2, 0x0}, - {0x110a3, 0x1}, - {0x110a4, 0x7}, - {0x110a5, 0x6}, - {0x110a6, 0x4}, - {0x110a7, 0x5}, - {0x1005f, 0x1ff}, - {0x1015f, 0x1ff}, - {0x1105f, 0x1ff}, - {0x1115f, 0x1ff}, - {0x11005f, 0x1ff}, - {0x11015f, 0x1ff}, - {0x11105f, 0x1ff}, - {0x11115f, 0x1ff}, - {0x21005f, 0x1ff}, - {0x21015f, 0x1ff}, - {0x21105f, 0x1ff}, - {0x21115f, 0x1ff}, - {0x55, 0x1ff}, - {0x1055, 0x1ff}, - {0x2055, 0x1ff}, - {0x200c5, 0xa}, - {0x1200c5, 0x2}, - {0x2200c5, 0x7}, - {0x2002e, 0x2}, - {0x12002e, 0x1}, - {0x22002e, 0x2}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x1e3}, - {0x2003a, 0x2}, - {0x2007d, 0x212}, - {0x2007c, 0x61}, - {0x120024, 0x1e3}, - {0x2003a, 0x2}, - {0x12007d, 0x212}, - {0x12007c, 0x61}, - {0x220024, 0x1e3}, - {0x2003a, 0x2}, - {0x22007d, 0x212}, - {0x22007c, 0x61}, - {0x20056, 0x3}, - {0x120056, 0x3}, - {0x220056, 0x3}, - {0x1004d, 0x600}, - {0x1014d, 0x600}, - {0x1104d, 0x600}, - {0x1114d, 0x600}, - {0x11004d, 0x600}, - {0x11014d, 0x600}, - {0x11104d, 0x600}, - {0x11114d, 0x600}, - {0x21004d, 0x600}, - {0x21014d, 0x600}, - {0x21104d, 0x600}, - {0x21114d, 0x600}, - {0x10049, 0xe3f}, - {0x10149, 0xe3f}, - {0x11049, 0xe3f}, - {0x11149, 0xe3f}, - {0x110049, 0xe3f}, - {0x110149, 0xe3f}, - {0x111049, 0xe3f}, - {0x111149, 0xe3f}, - {0x210049, 0xe3f}, - {0x210149, 0xe3f}, - {0x211049, 0xe3f}, - {0x211149, 0xe3f}, - {0x43, 0x7f}, - {0x1043, 0x7f}, - {0x2043, 0x7f}, - {0x20018, 0x1}, - {0x20075, 0x4}, - {0x20050, 0x11}, - {0x2009b, 0x2}, - {0x20008, 0x258}, - {0x120008, 0x12c}, - {0x220008, 0x9c}, - {0x20088, 0x9}, - {0x200b2, 0x10c}, - {0x10043, 0x5a1}, - {0x10143, 0x5a1}, - {0x11043, 0x5a1}, - {0x11143, 0x5a1}, - {0x1200b2, 0x10c}, - {0x110043, 0x5a1}, - {0x110143, 0x5a1}, - {0x111043, 0x5a1}, - {0x111143, 0x5a1}, - {0x2200b2, 0x10c}, - {0x210043, 0x5a1}, - {0x210143, 0x5a1}, - {0x211043, 0x5a1}, - {0x211143, 0x5a1}, - {0x200fa, 0x2}, - {0x1200fa, 0x2}, - {0x2200fa, 0x2}, - {0x20019, 0x1}, - {0x120019, 0x1}, - {0x220019, 0x1}, - {0x200f0, 0x600}, - {0x200f1, 0x0}, - {0x200f2, 0x4444}, - {0x200f3, 0x8888}, - {0x200f4, 0x5655}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0xf000}, - {0x1004a, 0x500}, - {0x1104a, 0x500}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0x20021, 0x0}, - {0x200c7, 0x21}, - {0x1200c7, 0x41}, - {0x200ca, 0x24}, - {0x1200ca, 0x24}, -}; - -/* PHY trained csr */ -static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - {0x1005f, 0x0}, - {0x1015f, 0x0}, - {0x1105f, 0x0}, - {0x1115f, 0x0}, - {0x11005f, 0x0}, - {0x11015f, 0x0}, - {0x11105f, 0x0}, - {0x11115f, 0x0}, - {0x21005f, 0x0}, - {0x21015f, 0x0}, - {0x21105f, 0x0}, - {0x21115f, 0x0}, - {0x55, 0x0}, - {0x1055, 0x0}, - {0x2055, 0x0}, - {0x200c5, 0x0}, - {0x1200c5, 0x0}, - {0x2200c5, 0x0}, - {0x2002e, 0x0}, - {0x12002e, 0x0}, - {0x22002e, 0x0}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x0}, - {0x2003a, 0x0}, - {0x2007d, 0x0}, - {0x2007c, 0x0}, - {0x120024, 0x0}, - {0x12007d, 0x0}, - {0x12007c, 0x0}, - {0x220024, 0x0}, - {0x22007d, 0x0}, - {0x22007c, 0x0}, - {0x20056, 0x0}, - {0x120056, 0x0}, - {0x220056, 0x0}, - {0x1004d, 0x0}, - {0x1014d, 0x0}, - {0x1104d, 0x0}, - {0x1114d, 0x0}, - {0x11004d, 0x0}, - {0x11014d, 0x0}, - {0x11104d, 0x0}, - {0x11114d, 0x0}, - {0x21004d, 0x0}, - {0x21014d, 0x0}, - {0x21104d, 0x0}, - {0x21114d, 0x0}, - {0x10049, 0x0}, - {0x10149, 0x0}, - {0x11049, 0x0}, - {0x11149, 0x0}, - {0x110049, 0x0}, - {0x110149, 0x0}, - {0x111049, 0x0}, - {0x111149, 0x0}, - {0x210049, 0x0}, - {0x210149, 0x0}, - {0x211049, 0x0}, - {0x211149, 0x0}, - {0x43, 0x0}, - {0x1043, 0x0}, - {0x2043, 0x0}, - {0x20018, 0x0}, - {0x20075, 0x0}, - {0x20050, 0x0}, - {0x2009b, 0x0}, - {0x20008, 0x0}, - {0x120008, 0x0}, - {0x220008, 0x0}, - {0x20088, 0x0}, - {0x200b2, 0x0}, - {0x10043, 0x0}, - {0x10143, 0x0}, - {0x11043, 0x0}, - {0x11143, 0x0}, - {0x1200b2, 0x0}, - {0x110043, 0x0}, - {0x110143, 0x0}, - {0x111043, 0x0}, - {0x111143, 0x0}, - {0x2200b2, 0x0}, - {0x210043, 0x0}, - {0x210143, 0x0}, - {0x211043, 0x0}, - {0x211143, 0x0}, - {0x200fa, 0x0}, - {0x1200fa, 0x0}, - {0x2200fa, 0x0}, - {0x20019, 0x0}, - {0x120019, 0x0}, - {0x220019, 0x0}, - {0x200f0, 0x0}, - {0x200f1, 0x0}, - {0x200f2, 0x0}, - {0x200f3, 0x0}, - {0x200f4, 0x0}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0x0}, - {0x1004a, 0x0}, - {0x1104a, 0x0}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0xd0000, 0x0}, - {0x90000, 0x0}, - {0x90001, 0x0}, - {0x90002, 0x0}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x0}, - {0x90029, 0x0}, - {0x9002a, 0x0}, - {0x9002b, 0x0}, - {0x9002c, 0x0}, - {0x9002d, 0x0}, - {0x9002e, 0x0}, - {0x9002f, 0x0}, - {0x90030, 0x0}, - {0x90031, 0x0}, - {0x90032, 0x0}, - {0x90033, 0x0}, - {0x90034, 0x0}, - {0x90035, 0x0}, - {0x90036, 0x0}, - {0x90037, 0x0}, - {0x90038, 0x0}, - {0x90039, 0x0}, - {0x9003a, 0x0}, - {0x9003b, 0x0}, - {0x9003c, 0x0}, - {0x9003d, 0x0}, - {0x9003e, 0x0}, - {0x9003f, 0x0}, - {0x90040, 0x0}, - {0x90041, 0x0}, - {0x90042, 0x0}, - {0x90043, 0x0}, - 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{0x1101d0, 0x0}, - {0x1101d1, 0x0}, - {0x11018c, 0x0}, - {0x11018d, 0x0}, - {0x1100c0, 0x0}, - {0x1100c1, 0x0}, - {0x1101c0, 0x0}, - {0x1101c1, 0x0}, - {0x1102c0, 0x0}, - {0x1102c1, 0x0}, - {0x1103c0, 0x0}, - {0x1103c1, 0x0}, - {0x1104c0, 0x0}, - {0x1104c1, 0x0}, - {0x1105c0, 0x0}, - {0x1105c1, 0x0}, - {0x1106c0, 0x0}, - {0x1106c1, 0x0}, - {0x1107c0, 0x0}, - {0x1107c1, 0x0}, - {0x1108c0, 0x0}, - {0x1108c1, 0x0}, - {0x1100ae, 0x0}, - {0x1100af, 0x0}, - {0x111020, 0x0}, - {0x111080, 0x0}, - {0x111081, 0x0}, - {0x1110d0, 0x0}, - {0x1110d1, 0x0}, - {0x11108c, 0x0}, - {0x11108d, 0x0}, - {0x111180, 0x0}, - {0x111181, 0x0}, - {0x1111d0, 0x0}, - {0x1111d1, 0x0}, - {0x11118c, 0x0}, - {0x11118d, 0x0}, - {0x1110c0, 0x0}, - {0x1110c1, 0x0}, - {0x1111c0, 0x0}, - {0x1111c1, 0x0}, - {0x1112c0, 0x0}, - {0x1112c1, 0x0}, - {0x1113c0, 0x0}, - {0x1113c1, 0x0}, - {0x1114c0, 0x0}, - {0x1114c1, 0x0}, - {0x1115c0, 0x0}, - {0x1115c1, 0x0}, - {0x1116c0, 0x0}, - {0x1116c1, 0x0}, - {0x1117c0, 0x0}, - {0x1117c1, 0x0}, - {0x1118c0, 0x0}, - {0x1118c1, 0x0}, - {0x1110ae, 0x0}, - {0x1110af, 0x0}, - {0x190201, 0x0}, - {0x190202, 0x0}, - {0x190203, 0x0}, - {0x190205, 0x0}, - {0x190206, 0x0}, - {0x190207, 0x0}, - {0x190208, 0x0}, - {0x120020, 0x0}, - {0x200080, 0x0}, - {0x201080, 0x0}, - {0x202080, 0x0}, - {0x210020, 0x0}, - {0x210080, 0x0}, - {0x210081, 0x0}, - {0x2100d0, 0x0}, - {0x2100d1, 0x0}, - {0x21008c, 0x0}, - {0x21008d, 0x0}, - {0x210180, 0x0}, - {0x210181, 0x0}, - {0x2101d0, 0x0}, - {0x2101d1, 0x0}, - {0x21018c, 0x0}, - {0x21018d, 0x0}, - {0x2100c0, 0x0}, - {0x2100c1, 0x0}, - {0x2101c0, 0x0}, - {0x2101c1, 0x0}, - {0x2102c0, 0x0}, - {0x2102c1, 0x0}, - {0x2103c0, 0x0}, - {0x2103c1, 0x0}, - {0x2104c0, 0x0}, - {0x2104c1, 0x0}, - {0x2105c0, 0x0}, - {0x2105c1, 0x0}, - {0x2106c0, 0x0}, - {0x2106c1, 0x0}, - {0x2107c0, 0x0}, - {0x2107c1, 0x0}, - {0x2108c0, 0x0}, - {0x2108c1, 0x0}, - {0x2100ae, 0x0}, - {0x2100af, 0x0}, - {0x211020, 0x0}, - {0x211080, 0x0}, - {0x211081, 0x0}, - {0x2110d0, 0x0}, - {0x2110d1, 0x0}, - {0x21108c, 0x0}, - {0x21108d, 0x0}, - {0x211180, 0x0}, - {0x211181, 0x0}, - {0x2111d0, 0x0}, - {0x2111d1, 0x0}, - {0x21118c, 0x0}, - {0x21118d, 0x0}, - {0x2110c0, 0x0}, - {0x2110c1, 0x0}, - {0x2111c0, 0x0}, - {0x2111c1, 0x0}, - {0x2112c0, 0x0}, - {0x2112c1, 0x0}, - {0x2113c0, 0x0}, - {0x2113c1, 0x0}, - {0x2114c0, 0x0}, - {0x2114c1, 0x0}, - {0x2115c0, 0x0}, - {0x2115c1, 0x0}, - {0x2116c0, 0x0}, - {0x2116c1, 0x0}, - {0x2117c0, 0x0}, - {0x2117c1, 0x0}, - {0x2118c0, 0x0}, - {0x2118c1, 0x0}, - {0x2110ae, 0x0}, - {0x2110af, 0x0}, - {0x290201, 0x0}, - {0x290202, 0x0}, - {0x290203, 0x0}, - {0x290205, 0x0}, - {0x290206, 0x0}, - {0x290207, 0x0}, - {0x290208, 0x0}, - {0x220020, 0x0}, - {0x20077, 0x0}, - {0x20072, 0x0}, - {0x20073, 0x0}, - {0x400c0, 0x0}, - {0x10040, 0x0}, - {0x10140, 0x0}, - {0x10240, 0x0}, - {0x10340, 0x0}, - {0x10440, 0x0}, - {0x10540, 0x0}, - {0x10640, 0x0}, - {0x10740, 0x0}, - {0x10840, 0x0}, - {0x11040, 0x0}, - {0x11140, 0x0}, - {0x11240, 0x0}, - {0x11340, 0x0}, - {0x11440, 0x0}, - {0x11540, 0x0}, - {0x11640, 0x0}, - {0x11740, 0x0}, - {0x11840, 0x0}, -}; - -/* P0 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0x960}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x131f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x24c4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x24c4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xc400}, - {0x54033, 0x3324}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xc400}, - {0x54039, 0x3324}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P1 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp1_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x1}, - {0x54003, 0x4b0}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x52a4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x52a4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xa400}, - {0x54033, 0x3352}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xa400}, - {0x54039, 0x3352}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P2 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp2_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x102}, - {0x54003, 0x270}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x994}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4800}, - {0x5401e, 0x4}, - {0x5401f, 0x994}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4800}, - {0x54024, 0x4}, - {0x54032, 0x9400}, - {0x54033, 0x3309}, - {0x54034, 0x4600}, - {0x54035, 0x11}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0x9400}, - {0x54039, 0x3309}, - {0x5403a, 0x4600}, - {0x5403b, 0x11}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P0 2D message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0x960}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x61}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54010, 0x2080}, - {0x54012, 0x110}, - {0x54019, 0x24c4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x24c4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xc400}, - {0x54033, 0x3324}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xc400}, - {0x54039, 0x3324}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* DRAM PHY init engine image */ -static struct dram_cfg_param ddr_phy_pie[] = { - {0xd0000, 0x0}, - {0x90000, 0x10}, - {0x90001, 0x400}, - {0x90002, 0x10e}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x8}, - {0x90029, 0xb}, - {0x9002a, 0x480}, - {0x9002b, 0x109}, - {0x9002c, 0x8}, - {0x9002d, 0x448}, - {0x9002e, 0x139}, - {0x9002f, 0x8}, - {0x90030, 0x478}, - {0x90031, 0x109}, - {0x90032, 0x0}, - {0x90033, 0xe8}, - {0x90034, 0x109}, - {0x90035, 0x2}, - {0x90036, 0x10}, - {0x90037, 0x139}, - {0x90038, 0xb}, - {0x90039, 0x7c0}, - {0x9003a, 0x139}, - {0x9003b, 0x44}, - {0x9003c, 0x633}, - {0x9003d, 0x159}, - {0x9003e, 0x14f}, - {0x9003f, 0x630}, - {0x90040, 0x159}, - {0x90041, 0x47}, - {0x90042, 0x633}, - {0x90043, 0x149}, - {0x90044, 0x4f}, - {0x90045, 0x633}, - {0x90046, 0x179}, - {0x90047, 0x8}, - {0x90048, 0xe0}, - {0x90049, 0x109}, - {0x9004a, 0x0}, - {0x9004b, 0x7c8}, - {0x9004c, 0x109}, - {0x9004d, 0x0}, - {0x9004e, 0x1}, - {0x9004f, 0x8}, - {0x90050, 0x30}, - {0x90051, 0x65a}, - {0x90052, 0x9}, - {0x90053, 0x0}, - {0x90054, 0x45a}, - {0x90055, 0x9}, - {0x90056, 0x0}, - {0x90057, 0x448}, - {0x90058, 0x109}, - {0x90059, 0x40}, - {0x9005a, 0x633}, - {0x9005b, 0x179}, - {0x9005c, 0x1}, - {0x9005d, 0x618}, - {0x9005e, 0x109}, - {0x9005f, 0x40c0}, - {0x90060, 0x633}, - {0x90061, 0x149}, - {0x90062, 0x8}, - {0x90063, 0x4}, - {0x90064, 0x48}, - {0x90065, 0x4040}, - {0x90066, 0x633}, - {0x90067, 0x149}, - {0x90068, 0x0}, - {0x90069, 0x4}, - {0x9006a, 0x48}, - {0x9006b, 0x40}, - {0x9006c, 0x633}, - {0x9006d, 0x149}, - {0x9006e, 0x0}, - {0x9006f, 0x658}, - {0x90070, 0x109}, - {0x90071, 0x10}, - {0x90072, 0x4}, - {0x90073, 0x18}, - {0x90074, 0x0}, - {0x90075, 0x4}, - {0x90076, 0x78}, - {0x90077, 0x549}, - {0x90078, 0x633}, - {0x90079, 0x159}, - {0x9007a, 0xd49}, - {0x9007b, 0x633}, - {0x9007c, 0x159}, - {0x9007d, 0x94a}, - {0x9007e, 0x633}, - {0x9007f, 0x159}, - {0x90080, 0x441}, - {0x90081, 0x633}, - {0x90082, 0x149}, - {0x90083, 0x42}, - {0x90084, 0x633}, - {0x90085, 0x149}, - {0x90086, 0x1}, - {0x90087, 0x633}, - {0x90088, 0x149}, - {0x90089, 0x0}, - {0x9008a, 0xe0}, - {0x9008b, 0x109}, - {0x9008c, 0xa}, - {0x9008d, 0x10}, - {0x9008e, 0x109}, - {0x9008f, 0x9}, - {0x90090, 0x3c0}, - {0x90091, 0x149}, - {0x90092, 0x9}, - {0x90093, 0x3c0}, - {0x90094, 0x159}, - {0x90095, 0x18}, - {0x90096, 0x10}, - {0x90097, 0x109}, - {0x90098, 0x0}, - {0x90099, 0x3c0}, - {0x9009a, 0x109}, - {0x9009b, 0x18}, - {0x9009c, 0x4}, - {0x9009d, 0x48}, - {0x9009e, 0x18}, - {0x9009f, 0x4}, - {0x900a0, 0x58}, - {0x900a1, 0xb}, - {0x900a2, 0x10}, - {0x900a3, 0x109}, - {0x900a4, 0x1}, - {0x900a5, 0x10}, - {0x900a6, 0x109}, - {0x900a7, 0x5}, - {0x900a8, 0x7c0}, - {0x900a9, 0x109}, - {0x40000, 0x811}, - {0x40020, 0x880}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x4008}, - {0x40021, 0x83}, - {0x40041, 0x4f}, - {0x40061, 0x0}, - {0x40002, 0x4040}, - {0x40022, 0x83}, - {0x40042, 0x51}, - {0x40062, 0x0}, - {0x40003, 0x811}, - {0x40023, 0x880}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x720}, - {0x40024, 0xf}, - {0x40044, 0x1740}, - {0x40064, 0x0}, - {0x40005, 0x16}, - {0x40025, 0x83}, - {0x40045, 0x4b}, - {0x40065, 0x0}, - {0x40006, 0x716}, - {0x40026, 0xf}, - {0x40046, 0x2001}, - {0x40066, 0x0}, - {0x40007, 0x716}, - {0x40027, 0xf}, - {0x40047, 0x2800}, - {0x40067, 0x0}, - {0x40008, 0x716}, - {0x40028, 0xf}, - {0x40048, 0xf00}, - {0x40068, 0x0}, - {0x40009, 0x720}, - {0x40029, 0xf}, - {0x40049, 0x1400}, - {0x40069, 0x0}, - {0x4000a, 0xe08}, - {0x4002a, 0xc15}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x625}, - {0x4002b, 0x15}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x4028}, - {0x4002c, 0x80}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0xe08}, - {0x4002d, 0xc1a}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x625}, - {0x4002e, 0x1a}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x4040}, - {0x4002f, 0x80}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x2604}, - {0x40030, 0x15}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x708}, - {0x40031, 0x5}, - {0x40051, 0x0}, - {0x40071, 0x2002}, - {0x40012, 0x8}, - {0x40032, 0x80}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x2604}, - {0x40033, 0x1a}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x708}, - {0x40034, 0xa}, - {0x40054, 0x0}, - {0x40074, 0x2002}, - {0x40015, 0x4040}, - {0x40035, 0x80}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x60a}, - {0x40036, 0x15}, - {0x40056, 0x1200}, - {0x40076, 0x0}, - {0x40017, 0x61a}, - {0x40037, 0x15}, - {0x40057, 0x1300}, - {0x40077, 0x0}, - {0x40018, 0x60a}, - {0x40038, 0x1a}, - {0x40058, 0x1200}, - {0x40078, 0x0}, - {0x40019, 0x642}, - {0x40039, 0x1a}, - {0x40059, 0x1300}, - {0x40079, 0x0}, - {0x4001a, 0x4808}, - {0x4003a, 0x880}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x790}, - {0x900ac, 0x11a}, - {0x900ad, 0x8}, - {0x900ae, 0x7aa}, - {0x900af, 0x2a}, - {0x900b0, 0x10}, - {0x900b1, 0x7b2}, - {0x900b2, 0x2a}, - {0x900b3, 0x0}, - {0x900b4, 0x7c8}, - {0x900b5, 0x109}, - {0x900b6, 0x10}, - {0x900b7, 0x10}, - {0x900b8, 0x109}, - {0x900b9, 0x10}, - {0x900ba, 0x2a8}, - {0x900bb, 0x129}, - {0x900bc, 0x8}, - {0x900bd, 0x370}, - {0x900be, 0x129}, - {0x900bf, 0xa}, - {0x900c0, 0x3c8}, - {0x900c1, 0x1a9}, - {0x900c2, 0xc}, - {0x900c3, 0x408}, - {0x900c4, 0x199}, - {0x900c5, 0x14}, - {0x900c6, 0x790}, - {0x900c7, 0x11a}, - {0x900c8, 0x8}, - {0x900c9, 0x4}, - {0x900ca, 0x18}, - {0x900cb, 0xe}, - {0x900cc, 0x408}, - {0x900cd, 0x199}, - {0x900ce, 0x8}, - {0x900cf, 0x8568}, - {0x900d0, 0x108}, - {0x900d1, 0x18}, - {0x900d2, 0x790}, - {0x900d3, 0x16a}, - {0x900d4, 0x8}, - {0x900d5, 0x1d8}, - {0x900d6, 0x169}, - {0x900d7, 0x10}, - {0x900d8, 0x8558}, - {0x900d9, 0x168}, - {0x900da, 0x1ff8}, - {0x900db, 0x85a8}, - {0x900dc, 0x1e8}, - {0x900dd, 0x50}, - {0x900de, 0x798}, - {0x900df, 0x16a}, - {0x900e0, 0x60}, - {0x900e1, 0x7a0}, - {0x900e2, 0x16a}, - {0x900e3, 0x8}, - {0x900e4, 0x8310}, - {0x900e5, 0x168}, - {0x900e6, 0x8}, - {0x900e7, 0xa310}, - {0x900e8, 0x168}, - {0x900e9, 0xa}, - {0x900ea, 0x408}, - {0x900eb, 0x169}, - {0x900ec, 0x6e}, - {0x900ed, 0x0}, - {0x900ee, 0x68}, - {0x900ef, 0x0}, - {0x900f0, 0x408}, - {0x900f1, 0x169}, - {0x900f2, 0x0}, - {0x900f3, 0x8310}, - {0x900f4, 0x168}, - {0x900f5, 0x0}, - {0x900f6, 0xa310}, - {0x900f7, 0x168}, - {0x900f8, 0x1ff8}, - {0x900f9, 0x85a8}, - {0x900fa, 0x1e8}, - {0x900fb, 0x68}, - {0x900fc, 0x798}, - {0x900fd, 0x16a}, - {0x900fe, 0x78}, - {0x900ff, 0x7a0}, - {0x90100, 0x16a}, - {0x90101, 0x68}, - {0x90102, 0x790}, - {0x90103, 0x16a}, - {0x90104, 0x8}, - {0x90105, 0x8b10}, - {0x90106, 0x168}, - {0x90107, 0x8}, - {0x90108, 0xab10}, - {0x90109, 0x168}, - {0x9010a, 0xa}, - {0x9010b, 0x408}, - {0x9010c, 0x169}, - {0x9010d, 0x58}, - {0x9010e, 0x0}, - {0x9010f, 0x68}, - {0x90110, 0x0}, - {0x90111, 0x408}, - {0x90112, 0x169}, - {0x90113, 0x0}, - {0x90114, 0x8b10}, - {0x90115, 0x168}, - {0x90116, 0x1}, - {0x90117, 0xab10}, - {0x90118, 0x168}, - {0x90119, 0x0}, - {0x9011a, 0x1d8}, - {0x9011b, 0x169}, - {0x9011c, 0x80}, - {0x9011d, 0x790}, - {0x9011e, 0x16a}, - {0x9011f, 0x18}, - {0x90120, 0x7aa}, - {0x90121, 0x6a}, - {0x90122, 0xa}, - {0x90123, 0x0}, - {0x90124, 0x1e9}, - {0x90125, 0x8}, - {0x90126, 0x8080}, - {0x90127, 0x108}, - {0x90128, 0xf}, - {0x90129, 0x408}, - {0x9012a, 0x169}, - {0x9012b, 0xc}, - {0x9012c, 0x0}, - {0x9012d, 0x68}, - {0x9012e, 0x9}, - {0x9012f, 0x0}, - {0x90130, 0x1a9}, - {0x90131, 0x0}, - {0x90132, 0x408}, - {0x90133, 0x169}, - {0x90134, 0x0}, - {0x90135, 0x8080}, - {0x90136, 0x108}, - {0x90137, 0x8}, - {0x90138, 0x7aa}, - {0x90139, 0x6a}, - {0x9013a, 0x0}, - {0x9013b, 0x8568}, - {0x9013c, 0x108}, - {0x9013d, 0xb7}, - {0x9013e, 0x790}, - {0x9013f, 0x16a}, - {0x90140, 0x1f}, - {0x90141, 0x0}, - {0x90142, 0x68}, - {0x90143, 0x8}, - {0x90144, 0x8558}, - {0x90145, 0x168}, - {0x90146, 0xf}, - {0x90147, 0x408}, - {0x90148, 0x169}, - {0x90149, 0xd}, - {0x9014a, 0x0}, - {0x9014b, 0x68}, - {0x9014c, 0x0}, - {0x9014d, 0x408}, - {0x9014e, 0x169}, - {0x9014f, 0x0}, - {0x90150, 0x8558}, - {0x90151, 0x168}, - {0x90152, 0x8}, - {0x90153, 0x3c8}, - {0x90154, 0x1a9}, - {0x90155, 0x3}, - {0x90156, 0x370}, - {0x90157, 0x129}, - {0x90158, 0x20}, - {0x90159, 0x2aa}, - {0x9015a, 0x9}, - {0x9015b, 0x8}, - {0x9015c, 0xe8}, - {0x9015d, 0x109}, - {0x9015e, 0x0}, - {0x9015f, 0x8140}, - {0x90160, 0x10c}, - {0x90161, 0x10}, - {0x90162, 0x8138}, - {0x90163, 0x104}, - {0x90164, 0x8}, - {0x90165, 0x448}, - {0x90166, 0x109}, - {0x90167, 0xf}, - {0x90168, 0x7c0}, - {0x90169, 0x109}, - {0x9016a, 0x0}, - {0x9016b, 0xe8}, - {0x9016c, 0x109}, - {0x9016d, 0x47}, - {0x9016e, 0x630}, - {0x9016f, 0x109}, - {0x90170, 0x8}, - {0x90171, 0x618}, - {0x90172, 0x109}, - {0x90173, 0x8}, - {0x90174, 0xe0}, - {0x90175, 0x109}, - {0x90176, 0x0}, - {0x90177, 0x7c8}, - {0x90178, 0x109}, - {0x90179, 0x8}, - {0x9017a, 0x8140}, - {0x9017b, 0x10c}, - {0x9017c, 0x0}, - {0x9017d, 0x478}, - {0x9017e, 0x109}, - {0x9017f, 0x0}, - {0x90180, 0x1}, - {0x90181, 0x8}, - {0x90182, 0x8}, - {0x90183, 0x4}, - {0x90184, 0x0}, - {0x90006, 0x8}, - {0x90007, 0x7c8}, - {0x90008, 0x109}, - {0x90009, 0x0}, - {0x9000a, 0x400}, - {0x9000b, 0x106}, - {0xd00e7, 0x400}, - {0x90017, 0x0}, - {0x9001f, 0x2b}, - {0x90026, 0x69}, - {0x400d0, 0x0}, - {0x400d1, 0x101}, - {0x400d2, 0x105}, - {0x400d3, 0x107}, - {0x400d4, 0x10f}, - {0x400d5, 0x202}, - {0x400d6, 0x20a}, - {0x400d7, 0x20b}, - {0x2003a, 0x2}, - {0x200be, 0x3}, - {0x2000b, 0x2a3}, - {0x2000c, 0x96}, - {0x2000d, 0x5dc}, - {0x2000e, 0x2c}, - {0x12000b, 0x152}, - {0x12000c, 0x4b}, - {0x12000d, 0x2ee}, - {0x12000e, 0x2c}, - {0x22000b, 0xb0}, - {0x22000c, 0x27}, - {0x22000d, 0x186}, - {0x22000e, 0x10}, - {0x9000c, 0x0}, - {0x9000d, 0x173}, - {0x9000e, 0x60}, - {0x9000f, 0x6110}, - {0x90010, 0x2152}, - {0x90011, 0xdfbd}, - {0x90012, 0x2060}, - {0x90013, 0x6152}, - {0x20010, 0x5a}, - {0x20011, 0x3}, - {0x120010, 0x5a}, - {0x120011, 0x3}, - {0x40080, 0xe0}, - {0x40081, 0x12}, - {0x40082, 0xe0}, - {0x40083, 0x12}, - {0x40084, 0xe0}, - {0x40085, 0x12}, - {0x140080, 0xe0}, - {0x140081, 0x12}, - {0x140082, 0xe0}, - {0x140083, 0x12}, - {0x140084, 0xe0}, - {0x140085, 0x12}, - {0x240080, 0xe0}, - {0x240081, 0x12}, - {0x240082, 0xe0}, - {0x240083, 0x12}, - {0x240084, 0xe0}, - {0x240085, 0x12}, - {0x400fd, 0xf}, - {0x400f1, 0xe}, - {0x10011, 0x1}, - {0x10012, 0x1}, - {0x10013, 0x180}, - {0x10018, 0x1}, - {0x10002, 0x6209}, - {0x100b2, 0x1}, - {0x101b4, 0x1}, - {0x102b4, 0x1}, - {0x103b4, 0x1}, - {0x104b4, 0x1}, - {0x105b4, 0x1}, - {0x106b4, 0x1}, - {0x107b4, 0x1}, - {0x108b4, 0x1}, - {0x11011, 0x1}, - {0x11012, 0x1}, - {0x11013, 0x180}, - {0x11018, 0x1}, - {0x11002, 0x6209}, - {0x110b2, 0x1}, - {0x111b4, 0x1}, - {0x112b4, 0x1}, - {0x113b4, 0x1}, - {0x114b4, 0x1}, - {0x115b4, 0x1}, - {0x116b4, 0x1}, - {0x117b4, 0x1}, - {0x118b4, 0x1}, - {0x20089, 0x1}, - {0x20088, 0x19}, - {0xc0080, 0x0}, - {0xd0000, 0x1}, -}; - -static struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 2400mts 1D */ - .drate = 2400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 1200mts 1D */ - .drate = 1200, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 625mts 1D */ - .drate = 625, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 2400mts 2D */ - .drate = 2400, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing_2GB = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 2400, 1200, 625, }, - .fsp_cfg = ddr_dram_fsp_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), -}; diff --git a/board/freescale/imx91_frdm/lpddr4_2400mts_ecc_1gb_timing.c b/board/freescale/imx91_frdm/lpddr4_2400mts_ecc_1gb_timing.c deleted file mode 100644 index d57e083557c..00000000000 --- a/board/freescale/imx91_frdm/lpddr4_2400mts_ecc_1gb_timing.c +++ /dev/null @@ -1,1996 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright 2025 NXP - * - * Code generated with DDR Tool v3.3.0_1.8-d1cdb7d3. - * DDR PHY FW2022.01 - */ - -#include -#include - -/* Initialize DDRC registers */ -static struct dram_cfg_param ddr_ddrc_cfg[] = { - {0x4e300110, 0x44100001}, - {0x4e300000, 0x8000b7}, - {0x4e300008, 0x0}, - {0x4e300080, 0x80000412}, - {0x4e300084, 0x0}, - {0x4e300114, 0x1012}, - {0x4e300260, 0x80}, - {0x4e300f04, 0x80}, - {0x4e300800, 0x43b30d00}, - {0x4e300804, 0x1f1f1f1f}, - {0x4e301000, 0xc0000000}, - {0x4e301240, 0x0}, - {0x4e301244, 0x0}, - {0x4e301248, 0x0}, - {0x4e30124c, 0x0}, - {0x4e301250, 0x0}, - {0x4e301254, 0x0}, - {0x4e301258, 0x0}, - {0x4e30125c, 0x0}, -}; - -/* dram fsp cfg */ -static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { - { - { - {0x4e300100, 0x13542110}, - {0x4e300104, 0xF8990011}, - {0x4e300108, 0x636E88CC}, - {0x4e30010C, 0x00614070}, - {0x4e300124, 0x124E0000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x31D00000}, - {0x4e300170, 0x8B0B0608}, - {0x4e300250, 0x0000001A}, - {0x4e300254, 0x00A000A0}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - {0x4e300300, 0x1633160D}, - {0x4e300304, 0x00A0180C}, - {0x4e300308, 0x0C280927}, - }, - { - {0x01, 0xC4}, - {0x02, 0x24}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x010A1100}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0xBABA0068}, - {0x4e30010C, 0x00610158}, - {0x4e300124, 0x09270000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30400000}, - {0x4e300170, 0x8A0A0508}, - {0x4e300250, 0x0000000D}, - {0x4e300254, 0x004C004C}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0xA4}, - {0x02, 0x52}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x00051000}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0x6E620A48}, - {0x4e30010C, 0x0031010D}, - {0x4e300124, 0x04C50000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30000000}, - {0x4e300170, 0x89090408}, - {0x4e300250, 0x00000007}, - {0x4e300254, 0x00240024}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0x94}, - {0x02, 0x9}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 1, - }, - -}; - -/* PHY Initialize Configuration */ -static struct dram_cfg_param ddr_ddrphy_cfg[] = { - {0x100a0, 0x4}, - {0x100a1, 0x5}, - {0x100a2, 0x6}, - {0x100a3, 0x7}, - {0x100a4, 0x0}, - {0x100a5, 0x1}, - {0x100a6, 0x2}, - {0x100a7, 0x3}, - {0x110a0, 0x3}, - {0x110a1, 0x2}, - {0x110a2, 0x0}, - {0x110a3, 0x1}, - {0x110a4, 0x7}, - {0x110a5, 0x6}, - {0x110a6, 0x4}, - {0x110a7, 0x5}, - {0x1005f, 0x1ff}, - {0x1015f, 0x1ff}, - {0x1105f, 0x1ff}, - {0x1115f, 0x1ff}, - {0x11005f, 0x1ff}, - {0x11015f, 0x1ff}, - {0x11105f, 0x1ff}, - {0x11115f, 0x1ff}, - {0x21005f, 0x1ff}, - {0x21015f, 0x1ff}, - {0x21105f, 0x1ff}, - {0x21115f, 0x1ff}, - {0x55, 0x1ff}, - {0x1055, 0x1ff}, - {0x2055, 0x1ff}, - {0x200c5, 0xa}, - {0x1200c5, 0x2}, - {0x2200c5, 0x7}, - {0x2002e, 0x2}, - {0x12002e, 0x1}, - {0x22002e, 0x2}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x1e3}, - {0x2003a, 0x2}, - {0x2007d, 0x212}, - {0x2007c, 0x61}, - {0x120024, 0x1e3}, - {0x2003a, 0x2}, - {0x12007d, 0x212}, - {0x12007c, 0x61}, - {0x220024, 0x1e3}, - {0x2003a, 0x2}, - {0x22007d, 0x212}, - {0x22007c, 0x61}, - {0x20056, 0x3}, - {0x120056, 0x3}, - {0x220056, 0x3}, - {0x1004d, 0x600}, - {0x1014d, 0x600}, - {0x1104d, 0x600}, - {0x1114d, 0x600}, - {0x11004d, 0x600}, - {0x11014d, 0x600}, - {0x11104d, 0x600}, - {0x11114d, 0x600}, - {0x21004d, 0x600}, - {0x21014d, 0x600}, - {0x21104d, 0x600}, - {0x21114d, 0x600}, - {0x10049, 0xe3f}, - {0x10149, 0xe3f}, - {0x11049, 0xe3f}, - {0x11149, 0xe3f}, - {0x110049, 0xe3f}, - {0x110149, 0xe3f}, - {0x111049, 0xe3f}, - {0x111149, 0xe3f}, - {0x210049, 0xe3f}, - {0x210149, 0xe3f}, - {0x211049, 0xe3f}, - {0x211149, 0xe3f}, - {0x43, 0x7f}, - {0x1043, 0x7f}, - {0x2043, 0x7f}, - {0x20018, 0x1}, - {0x20075, 0x4}, - {0x20050, 0x11}, - {0x2009b, 0x2}, - {0x20008, 0x258}, - {0x120008, 0x12c}, - {0x220008, 0x9c}, - {0x20088, 0x9}, - {0x200b2, 0x10c}, - {0x10043, 0x5a1}, - {0x10143, 0x5a1}, - {0x11043, 0x5a1}, - {0x11143, 0x5a1}, - {0x1200b2, 0x10c}, - {0x110043, 0x5a1}, - {0x110143, 0x5a1}, - {0x111043, 0x5a1}, - {0x111143, 0x5a1}, - {0x2200b2, 0x10c}, - {0x210043, 0x5a1}, - {0x210143, 0x5a1}, - {0x211043, 0x5a1}, - {0x211143, 0x5a1}, - {0x200fa, 0x2}, - {0x1200fa, 0x2}, - {0x2200fa, 0x2}, - {0x20019, 0x1}, - {0x120019, 0x1}, - {0x220019, 0x1}, - {0x200f0, 0x600}, - {0x200f1, 0x0}, - {0x200f2, 0x4444}, - {0x200f3, 0x8888}, - {0x200f4, 0x5655}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0xf000}, - {0x1004a, 0x500}, - {0x1104a, 0x500}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0x20021, 0x0}, - {0x200c7, 0x21}, - {0x1200c7, 0x41}, - {0x200ca, 0x24}, - {0x1200ca, 0x24}, -}; - -/* PHY trained csr */ -static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - {0x1005f, 0x0}, - {0x1015f, 0x0}, - {0x1105f, 0x0}, - {0x1115f, 0x0}, - {0x11005f, 0x0}, - {0x11015f, 0x0}, - {0x11105f, 0x0}, - {0x11115f, 0x0}, - {0x21005f, 0x0}, - {0x21015f, 0x0}, - {0x21105f, 0x0}, - {0x21115f, 0x0}, - {0x55, 0x0}, - {0x1055, 0x0}, - {0x2055, 0x0}, - {0x200c5, 0x0}, - {0x1200c5, 0x0}, - {0x2200c5, 0x0}, - {0x2002e, 0x0}, - {0x12002e, 0x0}, - {0x22002e, 0x0}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x0}, - {0x2003a, 0x0}, - {0x2007d, 0x0}, - {0x2007c, 0x0}, - {0x120024, 0x0}, - {0x12007d, 0x0}, - {0x12007c, 0x0}, - {0x220024, 0x0}, - {0x22007d, 0x0}, - {0x22007c, 0x0}, - {0x20056, 0x0}, - {0x120056, 0x0}, - {0x220056, 0x0}, - {0x1004d, 0x0}, - {0x1014d, 0x0}, - {0x1104d, 0x0}, - {0x1114d, 0x0}, - {0x11004d, 0x0}, - {0x11014d, 0x0}, - {0x11104d, 0x0}, - {0x11114d, 0x0}, - {0x21004d, 0x0}, - {0x21014d, 0x0}, - {0x21104d, 0x0}, - {0x21114d, 0x0}, - {0x10049, 0x0}, - {0x10149, 0x0}, - {0x11049, 0x0}, - {0x11149, 0x0}, - {0x110049, 0x0}, - {0x110149, 0x0}, - {0x111049, 0x0}, - {0x111149, 0x0}, - {0x210049, 0x0}, - {0x210149, 0x0}, - {0x211049, 0x0}, - {0x211149, 0x0}, - {0x43, 0x0}, - {0x1043, 0x0}, - {0x2043, 0x0}, - {0x20018, 0x0}, - {0x20075, 0x0}, - {0x20050, 0x0}, - {0x2009b, 0x0}, - {0x20008, 0x0}, - {0x120008, 0x0}, - {0x220008, 0x0}, - {0x20088, 0x0}, - {0x200b2, 0x0}, - {0x10043, 0x0}, - {0x10143, 0x0}, - {0x11043, 0x0}, - {0x11143, 0x0}, - {0x1200b2, 0x0}, - {0x110043, 0x0}, - {0x110143, 0x0}, - {0x111043, 0x0}, - {0x111143, 0x0}, - {0x2200b2, 0x0}, - {0x210043, 0x0}, - {0x210143, 0x0}, - {0x211043, 0x0}, - {0x211143, 0x0}, - {0x200fa, 0x0}, - {0x1200fa, 0x0}, - {0x2200fa, 0x0}, - {0x20019, 0x0}, - {0x120019, 0x0}, - {0x220019, 0x0}, - {0x200f0, 0x0}, - {0x200f1, 0x0}, - {0x200f2, 0x0}, - {0x200f3, 0x0}, - {0x200f4, 0x0}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0x0}, - {0x1004a, 0x0}, - {0x1104a, 0x0}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0xd0000, 0x0}, - {0x90000, 0x0}, - {0x90001, 0x0}, - {0x90002, 0x0}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x0}, - {0x90029, 0x0}, - {0x9002a, 0x0}, - {0x9002b, 0x0}, - {0x9002c, 0x0}, - {0x9002d, 0x0}, - {0x9002e, 0x0}, - {0x9002f, 0x0}, - {0x90030, 0x0}, - {0x90031, 0x0}, - {0x90032, 0x0}, - {0x90033, 0x0}, - {0x90034, 0x0}, - {0x90035, 0x0}, - {0x90036, 0x0}, - {0x90037, 0x0}, - {0x90038, 0x0}, - {0x90039, 0x0}, - {0x9003a, 0x0}, - {0x9003b, 0x0}, - {0x9003c, 0x0}, - {0x9003d, 0x0}, - {0x9003e, 0x0}, - {0x9003f, 0x0}, - {0x90040, 0x0}, - {0x90041, 0x0}, - {0x90042, 0x0}, - {0x90043, 0x0}, - {0x90044, 0x0}, - {0x90045, 0x0}, - {0x90046, 0x0}, - {0x90047, 0x0}, - {0x90048, 0x0}, - {0x90049, 0x0}, - {0x9004a, 0x0}, - {0x9004b, 0x0}, - {0x9004c, 0x0}, - {0x9004d, 0x0}, - {0x9004e, 0x0}, - {0x9004f, 0x0}, - {0x90050, 0x0}, - {0x90051, 0x0}, - {0x90052, 0x0}, - {0x90053, 0x0}, - {0x90054, 0x0}, - {0x90055, 0x0}, - {0x90056, 0x0}, - {0x90057, 0x0}, - {0x90058, 0x0}, - {0x90059, 0x0}, - {0x9005a, 0x0}, - {0x9005b, 0x0}, - {0x9005c, 0x0}, - {0x9005d, 0x0}, - {0x9005e, 0x0}, - {0x9005f, 0x0}, - {0x90060, 0x0}, - {0x90061, 0x0}, - {0x90062, 0x0}, - {0x90063, 0x0}, - {0x90064, 0x0}, - {0x90065, 0x0}, - {0x90066, 0x0}, - {0x90067, 0x0}, - {0x90068, 0x0}, - {0x90069, 0x0}, - {0x9006a, 0x0}, - {0x9006b, 0x0}, - {0x9006c, 0x0}, - {0x9006d, 0x0}, - {0x9006e, 0x0}, - {0x9006f, 0x0}, - {0x90070, 0x0}, - {0x90071, 0x0}, - {0x90072, 0x0}, - {0x90073, 0x0}, - {0x90074, 0x0}, - {0x90075, 0x0}, - {0x90076, 0x0}, - {0x90077, 0x0}, - {0x90078, 0x0}, - {0x90079, 0x0}, - {0x9007a, 0x0}, - {0x9007b, 0x0}, - {0x9007c, 0x0}, - {0x9007d, 0x0}, - {0x9007e, 0x0}, - {0x9007f, 0x0}, - {0x90080, 0x0}, - {0x90081, 0x0}, - {0x90082, 0x0}, - {0x90083, 0x0}, - {0x90084, 0x0}, - {0x90085, 0x0}, - {0x90086, 0x0}, - {0x90087, 0x0}, - {0x90088, 0x0}, - {0x90089, 0x0}, - {0x9008a, 0x0}, - {0x9008b, 0x0}, - {0x9008c, 0x0}, - {0x9008d, 0x0}, - {0x9008e, 0x0}, - {0x9008f, 0x0}, - {0x90090, 0x0}, - {0x90091, 0x0}, - {0x90092, 0x0}, - {0x90093, 0x0}, - {0x90094, 0x0}, - {0x90095, 0x0}, - {0x90096, 0x0}, - {0x90097, 0x0}, - {0x90098, 0x0}, - {0x90099, 0x0}, - {0x9009a, 0x0}, - {0x9009b, 0x0}, - {0x9009c, 0x0}, - {0x9009d, 0x0}, - {0x9009e, 0x0}, - {0x9009f, 0x0}, - {0x900a0, 0x0}, - {0x900a1, 0x0}, - {0x900a2, 0x0}, - {0x900a3, 0x0}, - {0x900a4, 0x0}, - {0x900a5, 0x0}, - {0x900a6, 0x0}, - {0x900a7, 0x0}, - {0x900a8, 0x0}, - {0x900a9, 0x0}, - {0x40000, 0x0}, - {0x40020, 0x0}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x0}, - {0x40021, 0x0}, - {0x40041, 0x0}, - {0x40061, 0x0}, - {0x40002, 0x0}, - {0x40022, 0x0}, - {0x40042, 0x0}, - {0x40062, 0x0}, - {0x40003, 0x0}, - {0x40023, 0x0}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x0}, - {0x40024, 0x0}, - {0x40044, 0x0}, - {0x40064, 0x0}, - {0x40005, 0x0}, - {0x40025, 0x0}, - {0x40045, 0x0}, - {0x40065, 0x0}, - {0x40006, 0x0}, - {0x40026, 0x0}, - {0x40046, 0x0}, - {0x40066, 0x0}, - {0x40007, 0x0}, - {0x40027, 0x0}, - {0x40047, 0x0}, - {0x40067, 0x0}, - {0x40008, 0x0}, - {0x40028, 0x0}, - {0x40048, 0x0}, - {0x40068, 0x0}, - {0x40009, 0x0}, - {0x40029, 0x0}, - {0x40049, 0x0}, - {0x40069, 0x0}, - {0x4000a, 0x0}, - {0x4002a, 0x0}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x0}, - {0x4002b, 0x0}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x0}, - {0x4002c, 0x0}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0x0}, - {0x4002d, 0x0}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x0}, - {0x4002e, 0x0}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x0}, - {0x4002f, 0x0}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x0}, - {0x40030, 0x0}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x0}, - {0x40031, 0x0}, - {0x40051, 0x0}, - {0x40071, 0x0}, - {0x40012, 0x0}, - {0x40032, 0x0}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x0}, - {0x40033, 0x0}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x0}, - {0x40034, 0x0}, - {0x40054, 0x0}, - {0x40074, 0x0}, - {0x40015, 0x0}, - {0x40035, 0x0}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x0}, - {0x40036, 0x0}, - {0x40056, 0x0}, - {0x40076, 0x0}, - {0x40017, 0x0}, - {0x40037, 0x0}, - {0x40057, 0x0}, - {0x40077, 0x0}, - {0x40018, 0x0}, - {0x40038, 0x0}, - {0x40058, 0x0}, - {0x40078, 0x0}, - {0x40019, 0x0}, - {0x40039, 0x0}, - {0x40059, 0x0}, - {0x40079, 0x0}, - {0x4001a, 0x0}, - {0x4003a, 0x0}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x0}, - {0x900ac, 0x0}, - {0x900ad, 0x0}, - {0x900ae, 0x0}, - {0x900af, 0x0}, - {0x900b0, 0x0}, - {0x900b1, 0x0}, - {0x900b2, 0x0}, - {0x900b3, 0x0}, - {0x900b4, 0x0}, - {0x900b5, 0x0}, - {0x900b6, 0x0}, - {0x900b7, 0x0}, - {0x900b8, 0x0}, - {0x900b9, 0x0}, - {0x900ba, 0x0}, - {0x900bb, 0x0}, - {0x900bc, 0x0}, - {0x900bd, 0x0}, - {0x900be, 0x0}, - {0x900bf, 0x0}, - {0x900c0, 0x0}, - {0x900c1, 0x0}, - {0x900c2, 0x0}, - {0x900c3, 0x0}, - {0x900c4, 0x0}, - {0x900c5, 0x0}, - {0x900c6, 0x0}, - {0x900c7, 0x0}, - {0x900c8, 0x0}, - {0x900c9, 0x0}, - {0x900ca, 0x0}, - {0x900cb, 0x0}, - {0x900cc, 0x0}, - {0x900cd, 0x0}, - {0x900ce, 0x0}, - {0x900cf, 0x0}, - {0x900d0, 0x0}, - {0x900d1, 0x0}, - {0x900d2, 0x0}, - {0x900d3, 0x0}, - {0x900d4, 0x0}, - {0x900d5, 0x0}, - {0x900d6, 0x0}, - {0x900d7, 0x0}, - {0x900d8, 0x0}, - {0x900d9, 0x0}, - {0x900da, 0x0}, - {0x900db, 0x0}, - {0x900dc, 0x0}, - {0x900dd, 0x0}, - {0x900de, 0x0}, - {0x900df, 0x0}, - {0x900e0, 0x0}, - {0x900e1, 0x0}, - {0x900e2, 0x0}, - {0x900e3, 0x0}, - {0x900e4, 0x0}, - {0x900e5, 0x0}, - {0x900e6, 0x0}, - {0x900e7, 0x0}, - {0x900e8, 0x0}, - {0x900e9, 0x0}, - {0x900ea, 0x0}, - {0x900eb, 0x0}, - {0x900ec, 0x0}, - {0x900ed, 0x0}, - {0x900ee, 0x0}, - {0x900ef, 0x0}, - {0x900f0, 0x0}, - {0x900f1, 0x0}, - {0x900f2, 0x0}, - {0x900f3, 0x0}, - {0x900f4, 0x0}, - {0x900f5, 0x0}, - {0x900f6, 0x0}, - {0x900f7, 0x0}, - {0x900f8, 0x0}, - {0x900f9, 0x0}, - {0x900fa, 0x0}, - {0x900fb, 0x0}, - {0x900fc, 0x0}, - {0x900fd, 0x0}, - {0x900fe, 0x0}, - {0x900ff, 0x0}, - {0x90100, 0x0}, - {0x90101, 0x0}, - {0x90102, 0x0}, - {0x90103, 0x0}, - {0x90104, 0x0}, - {0x90105, 0x0}, - {0x90106, 0x0}, - {0x90107, 0x0}, - {0x90108, 0x0}, - {0x90109, 0x0}, - {0x9010a, 0x0}, - {0x9010b, 0x0}, - {0x9010c, 0x0}, - {0x9010d, 0x0}, - {0x9010e, 0x0}, - {0x9010f, 0x0}, - {0x90110, 0x0}, - {0x90111, 0x0}, - {0x90112, 0x0}, - {0x90113, 0x0}, - {0x90114, 0x0}, - {0x90115, 0x0}, - {0x90116, 0x0}, - {0x90117, 0x0}, - {0x90118, 0x0}, - {0x90119, 0x0}, - {0x9011a, 0x0}, - {0x9011b, 0x0}, - {0x9011c, 0x0}, - {0x9011d, 0x0}, - {0x9011e, 0x0}, - {0x9011f, 0x0}, - {0x90120, 0x0}, - {0x90121, 0x0}, - {0x90122, 0x0}, - {0x90123, 0x0}, - {0x90124, 0x0}, - {0x90125, 0x0}, - {0x90126, 0x0}, - {0x90127, 0x0}, - {0x90128, 0x0}, - {0x90129, 0x0}, - {0x9012a, 0x0}, - {0x9012b, 0x0}, - {0x9012c, 0x0}, - {0x9012d, 0x0}, - {0x9012e, 0x0}, - {0x9012f, 0x0}, - {0x90130, 0x0}, - {0x90131, 0x0}, - {0x90132, 0x0}, - {0x90133, 0x0}, - {0x90134, 0x0}, - {0x90135, 0x0}, - {0x90136, 0x0}, - {0x90137, 0x0}, - {0x90138, 0x0}, - {0x90139, 0x0}, - {0x9013a, 0x0}, - {0x9013b, 0x0}, - {0x9013c, 0x0}, - {0x9013d, 0x0}, - {0x9013e, 0x0}, - {0x9013f, 0x0}, - {0x90140, 0x0}, - {0x90141, 0x0}, - {0x90142, 0x0}, - {0x90143, 0x0}, - {0x90144, 0x0}, - {0x90145, 0x0}, - {0x90146, 0x0}, - {0x90147, 0x0}, - {0x90148, 0x0}, - {0x90149, 0x0}, - {0x9014a, 0x0}, - {0x9014b, 0x0}, - {0x9014c, 0x0}, - {0x9014d, 0x0}, - {0x9014e, 0x0}, - {0x9014f, 0x0}, - {0x90150, 0x0}, - {0x90151, 0x0}, - {0x90152, 0x0}, - {0x90153, 0x0}, - {0x90154, 0x0}, - {0x90155, 0x0}, - {0x90156, 0x0}, - {0x90157, 0x0}, - {0x90158, 0x0}, - {0x90159, 0x0}, - {0x9015a, 0x0}, - {0x9015b, 0x0}, - {0x9015c, 0x0}, - {0x9015d, 0x0}, - {0x9015e, 0x0}, - {0x9015f, 0x0}, - {0x90160, 0x0}, - {0x90161, 0x0}, - {0x90162, 0x0}, - {0x90163, 0x0}, - {0x90164, 0x0}, - {0x90165, 0x0}, - {0x90166, 0x0}, - {0x90167, 0x0}, - {0x90168, 0x0}, - {0x90169, 0x0}, - {0x9016a, 0x0}, - {0x9016b, 0x0}, - {0x9016c, 0x0}, - {0x9016d, 0x0}, - {0x9016e, 0x0}, - {0x9016f, 0x0}, - {0x90170, 0x0}, - {0x90171, 0x0}, - {0x90172, 0x0}, - {0x90173, 0x0}, - {0x90174, 0x0}, - {0x90175, 0x0}, - {0x90176, 0x0}, - {0x90177, 0x0}, - {0x90178, 0x0}, - {0x90179, 0x0}, - {0x9017a, 0x0}, - {0x9017b, 0x0}, - {0x9017c, 0x0}, - {0x9017d, 0x0}, - {0x9017e, 0x0}, - {0x9017f, 0x0}, - {0x90180, 0x0}, - {0x90181, 0x0}, - {0x90182, 0x0}, - {0x90183, 0x0}, - {0x90184, 0x0}, - {0x90006, 0x0}, - {0x90007, 0x0}, - {0x90008, 0x0}, - {0x90009, 0x0}, - {0x9000a, 0x0}, - {0x9000b, 0x0}, - {0xd00e7, 0x0}, - {0x90017, 0x0}, - {0x9001f, 0x0}, - {0x90026, 0x0}, - {0x400d0, 0x0}, - {0x400d1, 0x0}, - {0x400d2, 0x0}, - {0x400d3, 0x0}, - {0x400d4, 0x0}, - {0x400d5, 0x0}, - {0x400d6, 0x0}, - {0x400d7, 0x0}, - {0x200be, 0x0}, - {0x2000b, 0x0}, - {0x2000c, 0x0}, - {0x2000d, 0x0}, - {0x2000e, 0x0}, - {0x12000b, 0x0}, - {0x12000c, 0x0}, - {0x12000d, 0x0}, - {0x12000e, 0x0}, - {0x22000b, 0x0}, - {0x22000c, 0x0}, - {0x22000d, 0x0}, - {0x22000e, 0x0}, - {0x9000c, 0x0}, - {0x9000d, 0x0}, - {0x9000e, 0x0}, - {0x9000f, 0x0}, - {0x90010, 0x0}, - {0x90011, 0x0}, - {0x90012, 0x0}, - {0x90013, 0x0}, - {0x20010, 0x0}, - {0x20011, 0x0}, - {0x120010, 0x0}, - {0x120011, 0x0}, - {0x40080, 0x0}, - {0x40081, 0x0}, - {0x40082, 0x0}, - {0x40083, 0x0}, - {0x40084, 0x0}, - {0x40085, 0x0}, - {0x140080, 0x0}, - {0x140081, 0x0}, - {0x140082, 0x0}, - {0x140083, 0x0}, - {0x140084, 0x0}, - {0x140085, 0x0}, - {0x240080, 0x0}, - {0x240081, 0x0}, - {0x240082, 0x0}, - {0x240083, 0x0}, - {0x240084, 0x0}, - {0x240085, 0x0}, - {0x400fd, 0x0}, - {0x400f1, 0x0}, - {0x10011, 0x0}, - {0x10012, 0x0}, - {0x10013, 0x0}, - {0x10018, 0x0}, - {0x10002, 0x0}, - {0x100b2, 0x0}, - {0x101b4, 0x0}, - {0x102b4, 0x0}, - {0x103b4, 0x0}, - {0x104b4, 0x0}, - {0x105b4, 0x0}, - {0x106b4, 0x0}, - {0x107b4, 0x0}, - {0x108b4, 0x0}, - {0x11011, 0x0}, - {0x11012, 0x0}, - {0x11013, 0x0}, - {0x11018, 0x0}, - {0x11002, 0x0}, - {0x110b2, 0x0}, - {0x111b4, 0x0}, - {0x112b4, 0x0}, - {0x113b4, 0x0}, - {0x114b4, 0x0}, - {0x115b4, 0x0}, - {0x116b4, 0x0}, - {0x117b4, 0x0}, - {0x118b4, 0x0}, - {0x20089, 0x0}, - {0xc0080, 0x0}, - {0x200cb, 0x0}, - {0x10068, 0x0}, - {0x10069, 0x0}, - {0x10168, 0x0}, - {0x10169, 0x0}, - {0x10268, 0x0}, - {0x10269, 0x0}, - {0x10368, 0x0}, - {0x10369, 0x0}, - {0x10468, 0x0}, - {0x10469, 0x0}, - {0x10568, 0x0}, - {0x10569, 0x0}, - {0x10668, 0x0}, - {0x10669, 0x0}, - {0x10768, 0x0}, - {0x10769, 0x0}, - {0x10868, 0x0}, - {0x10869, 0x0}, - {0x100aa, 0x0}, - {0x10062, 0x0}, - {0x10001, 0x0}, - {0x100a0, 0x0}, - {0x100a1, 0x0}, - {0x100a2, 0x0}, - {0x100a3, 0x0}, - {0x100a4, 0x0}, - {0x100a5, 0x0}, - {0x100a6, 0x0}, - {0x100a7, 0x0}, - {0x11068, 0x0}, - {0x11069, 0x0}, - {0x11168, 0x0}, - {0x11169, 0x0}, - {0x11268, 0x0}, - {0x11269, 0x0}, - {0x11368, 0x0}, - {0x11369, 0x0}, - {0x11468, 0x0}, - {0x11469, 0x0}, - {0x11568, 0x0}, - {0x11569, 0x0}, - {0x11668, 0x0}, - {0x11669, 0x0}, - {0x11768, 0x0}, - {0x11769, 0x0}, - {0x11868, 0x0}, - {0x11869, 0x0}, - {0x110aa, 0x0}, - {0x11062, 0x0}, - {0x11001, 0x0}, - {0x110a0, 0x0}, - {0x110a1, 0x0}, - {0x110a2, 0x0}, - {0x110a3, 0x0}, - {0x110a4, 0x0}, - {0x110a5, 0x0}, - {0x110a6, 0x0}, - {0x110a7, 0x0}, - {0x80, 0x0}, - {0x1080, 0x0}, - {0x2080, 0x0}, - {0x10020, 0x0}, - {0x10080, 0x0}, - {0x10081, 0x0}, - {0x100d0, 0x0}, - {0x100d1, 0x0}, - {0x1008c, 0x0}, - {0x1008d, 0x0}, - {0x10180, 0x0}, - {0x10181, 0x0}, - {0x101d0, 0x0}, - {0x101d1, 0x0}, - {0x1018c, 0x0}, - {0x1018d, 0x0}, - {0x100c0, 0x0}, - {0x100c1, 0x0}, - {0x101c0, 0x0}, - {0x101c1, 0x0}, - {0x102c0, 0x0}, - {0x102c1, 0x0}, - {0x103c0, 0x0}, - {0x103c1, 0x0}, - {0x104c0, 0x0}, - {0x104c1, 0x0}, - {0x105c0, 0x0}, - {0x105c1, 0x0}, - {0x106c0, 0x0}, - {0x106c1, 0x0}, - {0x107c0, 0x0}, - {0x107c1, 0x0}, - {0x108c0, 0x0}, - {0x108c1, 0x0}, - {0x100ae, 0x0}, - {0x100af, 0x0}, - {0x11020, 0x0}, - {0x11080, 0x0}, - {0x11081, 0x0}, - {0x110d0, 0x0}, - {0x110d1, 0x0}, - {0x1108c, 0x0}, - {0x1108d, 0x0}, - {0x11180, 0x0}, - {0x11181, 0x0}, - {0x111d0, 0x0}, - {0x111d1, 0x0}, - {0x1118c, 0x0}, - {0x1118d, 0x0}, - {0x110c0, 0x0}, - {0x110c1, 0x0}, - {0x111c0, 0x0}, - {0x111c1, 0x0}, - {0x112c0, 0x0}, - {0x112c1, 0x0}, - {0x113c0, 0x0}, - {0x113c1, 0x0}, - {0x114c0, 0x0}, - {0x114c1, 0x0}, - {0x115c0, 0x0}, - {0x115c1, 0x0}, - {0x116c0, 0x0}, - {0x116c1, 0x0}, - {0x117c0, 0x0}, - {0x117c1, 0x0}, - {0x118c0, 0x0}, - {0x118c1, 0x0}, - {0x110ae, 0x0}, - {0x110af, 0x0}, - {0x90201, 0x0}, - {0x90202, 0x0}, - {0x90203, 0x0}, - {0x90205, 0x0}, - {0x90206, 0x0}, - {0x90207, 0x0}, - {0x90208, 0x0}, - {0x20020, 0x0}, - {0x100080, 0x0}, - {0x101080, 0x0}, - {0x102080, 0x0}, - {0x110020, 0x0}, - {0x110080, 0x0}, - {0x110081, 0x0}, - {0x1100d0, 0x0}, - {0x1100d1, 0x0}, - {0x11008c, 0x0}, - {0x11008d, 0x0}, - {0x110180, 0x0}, - {0x110181, 0x0}, - {0x1101d0, 0x0}, - {0x1101d1, 0x0}, - {0x11018c, 0x0}, - {0x11018d, 0x0}, - {0x1100c0, 0x0}, - {0x1100c1, 0x0}, - {0x1101c0, 0x0}, - {0x1101c1, 0x0}, - {0x1102c0, 0x0}, - {0x1102c1, 0x0}, - {0x1103c0, 0x0}, - {0x1103c1, 0x0}, - {0x1104c0, 0x0}, - {0x1104c1, 0x0}, - {0x1105c0, 0x0}, - {0x1105c1, 0x0}, - {0x1106c0, 0x0}, - {0x1106c1, 0x0}, - {0x1107c0, 0x0}, - {0x1107c1, 0x0}, - {0x1108c0, 0x0}, - {0x1108c1, 0x0}, - {0x1100ae, 0x0}, - {0x1100af, 0x0}, - {0x111020, 0x0}, - {0x111080, 0x0}, - {0x111081, 0x0}, - {0x1110d0, 0x0}, - {0x1110d1, 0x0}, - {0x11108c, 0x0}, - {0x11108d, 0x0}, - {0x111180, 0x0}, - {0x111181, 0x0}, - {0x1111d0, 0x0}, - {0x1111d1, 0x0}, - {0x11118c, 0x0}, - {0x11118d, 0x0}, - {0x1110c0, 0x0}, - {0x1110c1, 0x0}, - {0x1111c0, 0x0}, - {0x1111c1, 0x0}, - {0x1112c0, 0x0}, - {0x1112c1, 0x0}, - {0x1113c0, 0x0}, - {0x1113c1, 0x0}, - {0x1114c0, 0x0}, - {0x1114c1, 0x0}, - {0x1115c0, 0x0}, - {0x1115c1, 0x0}, - {0x1116c0, 0x0}, - {0x1116c1, 0x0}, - {0x1117c0, 0x0}, - {0x1117c1, 0x0}, - {0x1118c0, 0x0}, - {0x1118c1, 0x0}, - {0x1110ae, 0x0}, - {0x1110af, 0x0}, - {0x190201, 0x0}, - {0x190202, 0x0}, - {0x190203, 0x0}, - {0x190205, 0x0}, - {0x190206, 0x0}, - {0x190207, 0x0}, - {0x190208, 0x0}, - {0x120020, 0x0}, - {0x200080, 0x0}, - {0x201080, 0x0}, - {0x202080, 0x0}, - {0x210020, 0x0}, - {0x210080, 0x0}, - {0x210081, 0x0}, - {0x2100d0, 0x0}, - {0x2100d1, 0x0}, - {0x21008c, 0x0}, - {0x21008d, 0x0}, - {0x210180, 0x0}, - {0x210181, 0x0}, - {0x2101d0, 0x0}, - {0x2101d1, 0x0}, - {0x21018c, 0x0}, - {0x21018d, 0x0}, - {0x2100c0, 0x0}, - {0x2100c1, 0x0}, - {0x2101c0, 0x0}, - {0x2101c1, 0x0}, - {0x2102c0, 0x0}, - {0x2102c1, 0x0}, - {0x2103c0, 0x0}, - {0x2103c1, 0x0}, - {0x2104c0, 0x0}, - {0x2104c1, 0x0}, - {0x2105c0, 0x0}, - {0x2105c1, 0x0}, - {0x2106c0, 0x0}, - {0x2106c1, 0x0}, - {0x2107c0, 0x0}, - {0x2107c1, 0x0}, - {0x2108c0, 0x0}, - {0x2108c1, 0x0}, - {0x2100ae, 0x0}, - {0x2100af, 0x0}, - {0x211020, 0x0}, - {0x211080, 0x0}, - {0x211081, 0x0}, - {0x2110d0, 0x0}, - {0x2110d1, 0x0}, - {0x21108c, 0x0}, - {0x21108d, 0x0}, - {0x211180, 0x0}, - {0x211181, 0x0}, - {0x2111d0, 0x0}, - {0x2111d1, 0x0}, - {0x21118c, 0x0}, - {0x21118d, 0x0}, - {0x2110c0, 0x0}, - {0x2110c1, 0x0}, - {0x2111c0, 0x0}, - {0x2111c1, 0x0}, - {0x2112c0, 0x0}, - {0x2112c1, 0x0}, - {0x2113c0, 0x0}, - {0x2113c1, 0x0}, - {0x2114c0, 0x0}, - {0x2114c1, 0x0}, - {0x2115c0, 0x0}, - {0x2115c1, 0x0}, - {0x2116c0, 0x0}, - {0x2116c1, 0x0}, - {0x2117c0, 0x0}, - {0x2117c1, 0x0}, - {0x2118c0, 0x0}, - {0x2118c1, 0x0}, - {0x2110ae, 0x0}, - {0x2110af, 0x0}, - {0x290201, 0x0}, - {0x290202, 0x0}, - {0x290203, 0x0}, - {0x290205, 0x0}, - {0x290206, 0x0}, - {0x290207, 0x0}, - {0x290208, 0x0}, - {0x220020, 0x0}, - {0x20077, 0x0}, - {0x20072, 0x0}, - {0x20073, 0x0}, - {0x400c0, 0x0}, - {0x10040, 0x0}, - {0x10140, 0x0}, - {0x10240, 0x0}, - {0x10340, 0x0}, - {0x10440, 0x0}, - {0x10540, 0x0}, - {0x10640, 0x0}, - {0x10740, 0x0}, - {0x10840, 0x0}, - {0x11040, 0x0}, - {0x11140, 0x0}, - {0x11240, 0x0}, - {0x11340, 0x0}, - {0x11440, 0x0}, - {0x11540, 0x0}, - {0x11640, 0x0}, - {0x11740, 0x0}, - {0x11840, 0x0}, -}; - -/* P0 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0x960}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x131f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x24c4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x24c4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xc400}, - {0x54033, 0x3324}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xc400}, - {0x54039, 0x3324}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P1 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp1_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x1}, - {0x54003, 0x4b0}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x52a4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x52a4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xa400}, - {0x54033, 0x3352}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xa400}, - {0x54039, 0x3352}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P2 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp2_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x102}, - {0x54003, 0x270}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x994}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4800}, - {0x5401e, 0x4}, - {0x5401f, 0x994}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4800}, - {0x54024, 0x4}, - {0x54032, 0x9400}, - {0x54033, 0x3309}, - {0x54034, 0x4600}, - {0x54035, 0x11}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0x9400}, - {0x54039, 0x3309}, - {0x5403a, 0x4600}, - {0x5403b, 0x11}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P0 2D message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0x960}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x61}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54010, 0x2080}, - {0x54012, 0x110}, - {0x54019, 0x24c4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x24c4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xc400}, - {0x54033, 0x3324}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xc400}, - {0x54039, 0x3324}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* DRAM PHY init engine image */ -static struct dram_cfg_param ddr_phy_pie[] = { - {0xd0000, 0x0}, - {0x90000, 0x10}, - {0x90001, 0x400}, - {0x90002, 0x10e}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x8}, - {0x90029, 0xb}, - {0x9002a, 0x480}, - {0x9002b, 0x109}, - {0x9002c, 0x8}, - {0x9002d, 0x448}, - {0x9002e, 0x139}, - {0x9002f, 0x8}, - {0x90030, 0x478}, - {0x90031, 0x109}, - {0x90032, 0x0}, - {0x90033, 0xe8}, - {0x90034, 0x109}, - {0x90035, 0x2}, - {0x90036, 0x10}, - {0x90037, 0x139}, - {0x90038, 0xb}, - {0x90039, 0x7c0}, - {0x9003a, 0x139}, - {0x9003b, 0x44}, - {0x9003c, 0x633}, - {0x9003d, 0x159}, - {0x9003e, 0x14f}, - {0x9003f, 0x630}, - {0x90040, 0x159}, - {0x90041, 0x47}, - {0x90042, 0x633}, - {0x90043, 0x149}, - {0x90044, 0x4f}, - {0x90045, 0x633}, - {0x90046, 0x179}, - {0x90047, 0x8}, - {0x90048, 0xe0}, - {0x90049, 0x109}, - {0x9004a, 0x0}, - {0x9004b, 0x7c8}, - {0x9004c, 0x109}, - {0x9004d, 0x0}, - {0x9004e, 0x1}, - {0x9004f, 0x8}, - {0x90050, 0x30}, - {0x90051, 0x65a}, - {0x90052, 0x9}, - {0x90053, 0x0}, - {0x90054, 0x45a}, - {0x90055, 0x9}, - {0x90056, 0x0}, - {0x90057, 0x448}, - {0x90058, 0x109}, - {0x90059, 0x40}, - {0x9005a, 0x633}, - {0x9005b, 0x179}, - {0x9005c, 0x1}, - {0x9005d, 0x618}, - {0x9005e, 0x109}, - {0x9005f, 0x40c0}, - {0x90060, 0x633}, - {0x90061, 0x149}, - {0x90062, 0x8}, - {0x90063, 0x4}, - {0x90064, 0x48}, - {0x90065, 0x4040}, - {0x90066, 0x633}, - {0x90067, 0x149}, - {0x90068, 0x0}, - {0x90069, 0x4}, - {0x9006a, 0x48}, - {0x9006b, 0x40}, - {0x9006c, 0x633}, - {0x9006d, 0x149}, - {0x9006e, 0x0}, - {0x9006f, 0x658}, - {0x90070, 0x109}, - {0x90071, 0x10}, - {0x90072, 0x4}, - {0x90073, 0x18}, - {0x90074, 0x0}, - {0x90075, 0x4}, - {0x90076, 0x78}, - {0x90077, 0x549}, - {0x90078, 0x633}, - {0x90079, 0x159}, - {0x9007a, 0xd49}, - {0x9007b, 0x633}, - {0x9007c, 0x159}, - {0x9007d, 0x94a}, - {0x9007e, 0x633}, - {0x9007f, 0x159}, - {0x90080, 0x441}, - {0x90081, 0x633}, - {0x90082, 0x149}, - {0x90083, 0x42}, - {0x90084, 0x633}, - {0x90085, 0x149}, - {0x90086, 0x1}, - {0x90087, 0x633}, - {0x90088, 0x149}, - {0x90089, 0x0}, - {0x9008a, 0xe0}, - {0x9008b, 0x109}, - {0x9008c, 0xa}, - {0x9008d, 0x10}, - {0x9008e, 0x109}, - {0x9008f, 0x9}, - {0x90090, 0x3c0}, - {0x90091, 0x149}, - {0x90092, 0x9}, - {0x90093, 0x3c0}, - {0x90094, 0x159}, - {0x90095, 0x18}, - {0x90096, 0x10}, - {0x90097, 0x109}, - {0x90098, 0x0}, - {0x90099, 0x3c0}, - {0x9009a, 0x109}, - {0x9009b, 0x18}, - {0x9009c, 0x4}, - {0x9009d, 0x48}, - {0x9009e, 0x18}, - {0x9009f, 0x4}, - {0x900a0, 0x58}, - {0x900a1, 0xb}, - {0x900a2, 0x10}, - {0x900a3, 0x109}, - {0x900a4, 0x1}, - {0x900a5, 0x10}, - {0x900a6, 0x109}, - {0x900a7, 0x5}, - {0x900a8, 0x7c0}, - {0x900a9, 0x109}, - {0x40000, 0x811}, - {0x40020, 0x880}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x4008}, - {0x40021, 0x83}, - {0x40041, 0x4f}, - {0x40061, 0x0}, - {0x40002, 0x4040}, - {0x40022, 0x83}, - {0x40042, 0x51}, - {0x40062, 0x0}, - {0x40003, 0x811}, - {0x40023, 0x880}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x720}, - {0x40024, 0xf}, - {0x40044, 0x1740}, - {0x40064, 0x0}, - {0x40005, 0x16}, - {0x40025, 0x83}, - {0x40045, 0x4b}, - {0x40065, 0x0}, - {0x40006, 0x716}, - {0x40026, 0xf}, - {0x40046, 0x2001}, - {0x40066, 0x0}, - {0x40007, 0x716}, - {0x40027, 0xf}, - {0x40047, 0x2800}, - {0x40067, 0x0}, - {0x40008, 0x716}, - {0x40028, 0xf}, - {0x40048, 0xf00}, - {0x40068, 0x0}, - {0x40009, 0x720}, - {0x40029, 0xf}, - {0x40049, 0x1400}, - {0x40069, 0x0}, - {0x4000a, 0xe08}, - {0x4002a, 0xc15}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x625}, - {0x4002b, 0x15}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x4028}, - {0x4002c, 0x80}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0xe08}, - {0x4002d, 0xc1a}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x625}, - {0x4002e, 0x1a}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x4040}, - {0x4002f, 0x80}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x2604}, - {0x40030, 0x15}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x708}, - {0x40031, 0x5}, - {0x40051, 0x0}, - {0x40071, 0x2002}, - {0x40012, 0x8}, - {0x40032, 0x80}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x2604}, - {0x40033, 0x1a}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x708}, - {0x40034, 0xa}, - {0x40054, 0x0}, - {0x40074, 0x2002}, - {0x40015, 0x4040}, - {0x40035, 0x80}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x60a}, - {0x40036, 0x15}, - {0x40056, 0x1200}, - {0x40076, 0x0}, - {0x40017, 0x61a}, - {0x40037, 0x15}, - {0x40057, 0x1300}, - {0x40077, 0x0}, - {0x40018, 0x60a}, - {0x40038, 0x1a}, - {0x40058, 0x1200}, - {0x40078, 0x0}, - {0x40019, 0x642}, - {0x40039, 0x1a}, - {0x40059, 0x1300}, - {0x40079, 0x0}, - {0x4001a, 0x4808}, - {0x4003a, 0x880}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x790}, - {0x900ac, 0x11a}, - {0x900ad, 0x8}, - {0x900ae, 0x7aa}, - {0x900af, 0x2a}, - {0x900b0, 0x10}, - {0x900b1, 0x7b2}, - {0x900b2, 0x2a}, - {0x900b3, 0x0}, - {0x900b4, 0x7c8}, - {0x900b5, 0x109}, - {0x900b6, 0x10}, - {0x900b7, 0x10}, - {0x900b8, 0x109}, - {0x900b9, 0x10}, - {0x900ba, 0x2a8}, - {0x900bb, 0x129}, - {0x900bc, 0x8}, - {0x900bd, 0x370}, - {0x900be, 0x129}, - {0x900bf, 0xa}, - {0x900c0, 0x3c8}, - {0x900c1, 0x1a9}, - {0x900c2, 0xc}, - {0x900c3, 0x408}, - {0x900c4, 0x199}, - {0x900c5, 0x14}, - {0x900c6, 0x790}, - {0x900c7, 0x11a}, - {0x900c8, 0x8}, - {0x900c9, 0x4}, - {0x900ca, 0x18}, - {0x900cb, 0xe}, - {0x900cc, 0x408}, - {0x900cd, 0x199}, - {0x900ce, 0x8}, - {0x900cf, 0x8568}, - {0x900d0, 0x108}, - {0x900d1, 0x18}, - {0x900d2, 0x790}, - {0x900d3, 0x16a}, - {0x900d4, 0x8}, - {0x900d5, 0x1d8}, - {0x900d6, 0x169}, - {0x900d7, 0x10}, - {0x900d8, 0x8558}, - {0x900d9, 0x168}, - {0x900da, 0x1ff8}, - {0x900db, 0x85a8}, - {0x900dc, 0x1e8}, - {0x900dd, 0x50}, - {0x900de, 0x798}, - {0x900df, 0x16a}, - {0x900e0, 0x60}, - {0x900e1, 0x7a0}, - {0x900e2, 0x16a}, - {0x900e3, 0x8}, - {0x900e4, 0x8310}, - {0x900e5, 0x168}, - {0x900e6, 0x8}, - {0x900e7, 0xa310}, - {0x900e8, 0x168}, - {0x900e9, 0xa}, - {0x900ea, 0x408}, - {0x900eb, 0x169}, - {0x900ec, 0x6e}, - {0x900ed, 0x0}, - {0x900ee, 0x68}, - {0x900ef, 0x0}, - {0x900f0, 0x408}, - {0x900f1, 0x169}, - {0x900f2, 0x0}, - {0x900f3, 0x8310}, - {0x900f4, 0x168}, - {0x900f5, 0x0}, - {0x900f6, 0xa310}, - {0x900f7, 0x168}, - {0x900f8, 0x1ff8}, - {0x900f9, 0x85a8}, - {0x900fa, 0x1e8}, - {0x900fb, 0x68}, - {0x900fc, 0x798}, - {0x900fd, 0x16a}, - {0x900fe, 0x78}, - {0x900ff, 0x7a0}, - {0x90100, 0x16a}, - {0x90101, 0x68}, - {0x90102, 0x790}, - {0x90103, 0x16a}, - {0x90104, 0x8}, - {0x90105, 0x8b10}, - {0x90106, 0x168}, - {0x90107, 0x8}, - {0x90108, 0xab10}, - {0x90109, 0x168}, - {0x9010a, 0xa}, - {0x9010b, 0x408}, - {0x9010c, 0x169}, - {0x9010d, 0x58}, - {0x9010e, 0x0}, - {0x9010f, 0x68}, - {0x90110, 0x0}, - {0x90111, 0x408}, - {0x90112, 0x169}, - {0x90113, 0x0}, - {0x90114, 0x8b10}, - {0x90115, 0x168}, - {0x90116, 0x1}, - {0x90117, 0xab10}, - {0x90118, 0x168}, - {0x90119, 0x0}, - {0x9011a, 0x1d8}, - {0x9011b, 0x169}, - {0x9011c, 0x80}, - {0x9011d, 0x790}, - {0x9011e, 0x16a}, - {0x9011f, 0x18}, - {0x90120, 0x7aa}, - {0x90121, 0x6a}, - {0x90122, 0xa}, - {0x90123, 0x0}, - {0x90124, 0x1e9}, - {0x90125, 0x8}, - {0x90126, 0x8080}, - {0x90127, 0x108}, - {0x90128, 0xf}, - {0x90129, 0x408}, - {0x9012a, 0x169}, - {0x9012b, 0xc}, - {0x9012c, 0x0}, - {0x9012d, 0x68}, - {0x9012e, 0x9}, - {0x9012f, 0x0}, - {0x90130, 0x1a9}, - {0x90131, 0x0}, - {0x90132, 0x408}, - {0x90133, 0x169}, - {0x90134, 0x0}, - {0x90135, 0x8080}, - {0x90136, 0x108}, - {0x90137, 0x8}, - {0x90138, 0x7aa}, - {0x90139, 0x6a}, - {0x9013a, 0x0}, - {0x9013b, 0x8568}, - {0x9013c, 0x108}, - {0x9013d, 0xb7}, - {0x9013e, 0x790}, - {0x9013f, 0x16a}, - {0x90140, 0x1f}, - {0x90141, 0x0}, - {0x90142, 0x68}, - {0x90143, 0x8}, - {0x90144, 0x8558}, - {0x90145, 0x168}, - {0x90146, 0xf}, - {0x90147, 0x408}, - {0x90148, 0x169}, - {0x90149, 0xd}, - {0x9014a, 0x0}, - {0x9014b, 0x68}, - {0x9014c, 0x0}, - {0x9014d, 0x408}, - {0x9014e, 0x169}, - {0x9014f, 0x0}, - {0x90150, 0x8558}, - {0x90151, 0x168}, - {0x90152, 0x8}, - {0x90153, 0x3c8}, - {0x90154, 0x1a9}, - {0x90155, 0x3}, - {0x90156, 0x370}, - {0x90157, 0x129}, - {0x90158, 0x20}, - {0x90159, 0x2aa}, - {0x9015a, 0x9}, - {0x9015b, 0x8}, - {0x9015c, 0xe8}, - {0x9015d, 0x109}, - {0x9015e, 0x0}, - {0x9015f, 0x8140}, - {0x90160, 0x10c}, - {0x90161, 0x10}, - {0x90162, 0x8138}, - {0x90163, 0x104}, - {0x90164, 0x8}, - {0x90165, 0x448}, - {0x90166, 0x109}, - {0x90167, 0xf}, - {0x90168, 0x7c0}, - {0x90169, 0x109}, - {0x9016a, 0x0}, - {0x9016b, 0xe8}, - {0x9016c, 0x109}, - {0x9016d, 0x47}, - {0x9016e, 0x630}, - {0x9016f, 0x109}, - {0x90170, 0x8}, - {0x90171, 0x618}, - {0x90172, 0x109}, - {0x90173, 0x8}, - {0x90174, 0xe0}, - {0x90175, 0x109}, - {0x90176, 0x0}, - {0x90177, 0x7c8}, - {0x90178, 0x109}, - {0x90179, 0x8}, - {0x9017a, 0x8140}, - {0x9017b, 0x10c}, - {0x9017c, 0x0}, - {0x9017d, 0x478}, - {0x9017e, 0x109}, - {0x9017f, 0x0}, - {0x90180, 0x1}, - {0x90181, 0x8}, - {0x90182, 0x8}, - {0x90183, 0x4}, - {0x90184, 0x0}, - {0x90006, 0x8}, - {0x90007, 0x7c8}, - {0x90008, 0x109}, - {0x90009, 0x0}, - {0x9000a, 0x400}, - {0x9000b, 0x106}, - {0xd00e7, 0x400}, - {0x90017, 0x0}, - {0x9001f, 0x2b}, - {0x90026, 0x69}, - {0x400d0, 0x0}, - {0x400d1, 0x101}, - {0x400d2, 0x105}, - {0x400d3, 0x107}, - {0x400d4, 0x10f}, - {0x400d5, 0x202}, - {0x400d6, 0x20a}, - {0x400d7, 0x20b}, - {0x2003a, 0x2}, - {0x200be, 0x3}, - {0x2000b, 0x2a3}, - {0x2000c, 0x96}, - {0x2000d, 0x5dc}, - {0x2000e, 0x2c}, - {0x12000b, 0x152}, - {0x12000c, 0x4b}, - {0x12000d, 0x2ee}, - {0x12000e, 0x2c}, - {0x22000b, 0xb0}, - {0x22000c, 0x27}, - {0x22000d, 0x186}, - {0x22000e, 0x10}, - {0x9000c, 0x0}, - {0x9000d, 0x173}, - {0x9000e, 0x60}, - {0x9000f, 0x6110}, - {0x90010, 0x2152}, - {0x90011, 0xdfbd}, - {0x90012, 0x2060}, - {0x90013, 0x6152}, - {0x20010, 0x5a}, - {0x20011, 0x3}, - {0x120010, 0x5a}, - {0x120011, 0x3}, - {0x40080, 0xe0}, - {0x40081, 0x12}, - {0x40082, 0xe0}, - {0x40083, 0x12}, - {0x40084, 0xe0}, - {0x40085, 0x12}, - {0x140080, 0xe0}, - {0x140081, 0x12}, - {0x140082, 0xe0}, - {0x140083, 0x12}, - {0x140084, 0xe0}, - {0x140085, 0x12}, - {0x240080, 0xe0}, - {0x240081, 0x12}, - {0x240082, 0xe0}, - {0x240083, 0x12}, - {0x240084, 0xe0}, - {0x240085, 0x12}, - {0x400fd, 0xf}, - {0x400f1, 0xe}, - {0x10011, 0x1}, - {0x10012, 0x1}, - {0x10013, 0x180}, - {0x10018, 0x1}, - {0x10002, 0x6209}, - {0x100b2, 0x1}, - {0x101b4, 0x1}, - {0x102b4, 0x1}, - {0x103b4, 0x1}, - {0x104b4, 0x1}, - {0x105b4, 0x1}, - {0x106b4, 0x1}, - {0x107b4, 0x1}, - {0x108b4, 0x1}, - {0x11011, 0x1}, - {0x11012, 0x1}, - {0x11013, 0x180}, - {0x11018, 0x1}, - {0x11002, 0x6209}, - {0x110b2, 0x1}, - {0x111b4, 0x1}, - {0x112b4, 0x1}, - {0x113b4, 0x1}, - {0x114b4, 0x1}, - {0x115b4, 0x1}, - {0x116b4, 0x1}, - {0x117b4, 0x1}, - {0x118b4, 0x1}, - {0x20089, 0x1}, - {0x20088, 0x19}, - {0xc0080, 0x0}, - {0xd0000, 0x1}, -}; - -static struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 2400mts 1D */ - .drate = 2400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 1200mts 1D */ - .drate = 1200, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 625mts 1D */ - .drate = 625, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 2400mts 2D */ - .drate = 2400, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing_1GB = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 2400, 1200, 625, }, - .fsp_cfg = ddr_dram_fsp_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), -}; diff --git a/board/freescale/imx91_frdm/lpddr4_2400mts_ecc_2gb_timing.c b/board/freescale/imx91_frdm/lpddr4_2400mts_ecc_2gb_timing.c deleted file mode 100644 index 4859796be38..00000000000 --- a/board/freescale/imx91_frdm/lpddr4_2400mts_ecc_2gb_timing.c +++ /dev/null @@ -1,1996 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright 2025 NXP - * - * Code generated with DDR Tool v3.3.0_1.8-d1cdb7d3. - * DDR PHY FW2022.01 - */ - -#include -#include - -/* Initialize DDRC registers */ -static struct dram_cfg_param ddr_ddrc_cfg[] = { - {0x4e300110, 0x44100001}, - {0x4e300000, 0x8000ef}, - {0x4e300008, 0x0}, - {0x4e300080, 0x80000512}, - {0x4e300084, 0x0}, - {0x4e300114, 0x1012}, - {0x4e300260, 0x80}, - {0x4e300f04, 0x80}, - {0x4e300800, 0x43b30d00}, - {0x4e300804, 0x1f1f1f1f}, - {0x4e301000, 0xc0000000}, - {0x4e301240, 0x0}, - {0x4e301244, 0x0}, - {0x4e301248, 0x0}, - {0x4e30124c, 0x0}, - {0x4e301250, 0x0}, - {0x4e301254, 0x0}, - {0x4e301258, 0x0}, - {0x4e30125c, 0x0}, -}; - -/* dram fsp cfg */ -static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { - { - { - {0x4e300100, 0x135C2110}, - {0x4e300104, 0xF8990011}, - {0x4e300108, 0x636E08CC}, - {0x4e30010C, 0x00614070}, - {0x4e300124, 0x124E0000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x31D00000}, - {0x4e300170, 0x8B0B0608}, - {0x4e300250, 0x0000001A}, - {0x4e300254, 0x00DC00DC}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - {0x4e300300, 0x1633160D}, - {0x4e300304, 0x00DC180C}, - {0x4e300308, 0x0C280927}, - }, - { - {0x01, 0xC4}, - {0x02, 0x24}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x010D1100}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0xBABAC068}, - {0x4e30010C, 0x00610158}, - {0x4e300124, 0x09270000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30400000}, - {0x4e300170, 0x8A0A0508}, - {0x4e300250, 0x0000000D}, - {0x4e300254, 0x006A006A}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0xA4}, - {0x02, 0x52}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x00061000}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0x6E62FA48}, - {0x4e30010C, 0x0031010D}, - {0x4e300124, 0x04C50000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30000000}, - {0x4e300170, 0x89090408}, - {0x4e300250, 0x00000007}, - {0x4e300254, 0x00340034}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0x94}, - {0x02, 0x9}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 1, - }, - -}; - -/* PHY Initialize Configuration */ -static struct dram_cfg_param ddr_ddrphy_cfg[] = { - {0x100a0, 0x4}, - {0x100a1, 0x5}, - {0x100a2, 0x6}, - {0x100a3, 0x7}, - {0x100a4, 0x0}, - {0x100a5, 0x1}, - {0x100a6, 0x2}, - {0x100a7, 0x3}, - {0x110a0, 0x3}, - {0x110a1, 0x2}, - {0x110a2, 0x0}, - {0x110a3, 0x1}, - {0x110a4, 0x7}, - {0x110a5, 0x6}, - {0x110a6, 0x4}, - {0x110a7, 0x5}, - {0x1005f, 0x1ff}, - {0x1015f, 0x1ff}, - {0x1105f, 0x1ff}, - {0x1115f, 0x1ff}, - {0x11005f, 0x1ff}, - {0x11015f, 0x1ff}, - {0x11105f, 0x1ff}, - {0x11115f, 0x1ff}, - {0x21005f, 0x1ff}, - {0x21015f, 0x1ff}, - {0x21105f, 0x1ff}, - {0x21115f, 0x1ff}, - {0x55, 0x1ff}, - {0x1055, 0x1ff}, - {0x2055, 0x1ff}, - {0x200c5, 0xa}, - {0x1200c5, 0x2}, - {0x2200c5, 0x7}, - {0x2002e, 0x2}, - {0x12002e, 0x1}, - {0x22002e, 0x2}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x1e3}, - {0x2003a, 0x2}, - {0x2007d, 0x212}, - {0x2007c, 0x61}, - {0x120024, 0x1e3}, - {0x2003a, 0x2}, - {0x12007d, 0x212}, - {0x12007c, 0x61}, - {0x220024, 0x1e3}, - {0x2003a, 0x2}, - {0x22007d, 0x212}, - {0x22007c, 0x61}, - {0x20056, 0x3}, - {0x120056, 0x3}, - {0x220056, 0x3}, - {0x1004d, 0x600}, - {0x1014d, 0x600}, - {0x1104d, 0x600}, - {0x1114d, 0x600}, - {0x11004d, 0x600}, - {0x11014d, 0x600}, - {0x11104d, 0x600}, - {0x11114d, 0x600}, - {0x21004d, 0x600}, - {0x21014d, 0x600}, - {0x21104d, 0x600}, - {0x21114d, 0x600}, - {0x10049, 0xe3f}, - {0x10149, 0xe3f}, - {0x11049, 0xe3f}, - {0x11149, 0xe3f}, - {0x110049, 0xe3f}, - {0x110149, 0xe3f}, - {0x111049, 0xe3f}, - {0x111149, 0xe3f}, - {0x210049, 0xe3f}, - {0x210149, 0xe3f}, - {0x211049, 0xe3f}, - {0x211149, 0xe3f}, - {0x43, 0x7f}, - {0x1043, 0x7f}, - {0x2043, 0x7f}, - {0x20018, 0x1}, - {0x20075, 0x4}, - {0x20050, 0x11}, - {0x2009b, 0x2}, - {0x20008, 0x258}, - {0x120008, 0x12c}, - {0x220008, 0x9c}, - {0x20088, 0x9}, - {0x200b2, 0x10c}, - {0x10043, 0x5a1}, - {0x10143, 0x5a1}, - {0x11043, 0x5a1}, - {0x11143, 0x5a1}, - {0x1200b2, 0x10c}, - {0x110043, 0x5a1}, - {0x110143, 0x5a1}, - {0x111043, 0x5a1}, - {0x111143, 0x5a1}, - {0x2200b2, 0x10c}, - {0x210043, 0x5a1}, - {0x210143, 0x5a1}, - {0x211043, 0x5a1}, - {0x211143, 0x5a1}, - {0x200fa, 0x2}, - {0x1200fa, 0x2}, - {0x2200fa, 0x2}, - {0x20019, 0x1}, - {0x120019, 0x1}, - {0x220019, 0x1}, - {0x200f0, 0x600}, - {0x200f1, 0x0}, - {0x200f2, 0x4444}, - {0x200f3, 0x8888}, - {0x200f4, 0x5655}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0xf000}, - {0x1004a, 0x500}, - {0x1104a, 0x500}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0x20021, 0x0}, - {0x200c7, 0x21}, - {0x1200c7, 0x41}, - {0x200ca, 0x24}, - {0x1200ca, 0x24}, -}; - -/* PHY trained csr */ -static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - {0x1005f, 0x0}, - {0x1015f, 0x0}, - {0x1105f, 0x0}, - {0x1115f, 0x0}, - {0x11005f, 0x0}, - {0x11015f, 0x0}, - {0x11105f, 0x0}, - {0x11115f, 0x0}, - {0x21005f, 0x0}, - {0x21015f, 0x0}, - {0x21105f, 0x0}, - {0x21115f, 0x0}, - {0x55, 0x0}, - {0x1055, 0x0}, - {0x2055, 0x0}, - {0x200c5, 0x0}, - {0x1200c5, 0x0}, - {0x2200c5, 0x0}, - {0x2002e, 0x0}, - {0x12002e, 0x0}, - {0x22002e, 0x0}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x0}, - {0x2003a, 0x0}, - {0x2007d, 0x0}, - {0x2007c, 0x0}, - {0x120024, 0x0}, - {0x12007d, 0x0}, - {0x12007c, 0x0}, - {0x220024, 0x0}, - {0x22007d, 0x0}, - {0x22007c, 0x0}, - {0x20056, 0x0}, - {0x120056, 0x0}, - {0x220056, 0x0}, - {0x1004d, 0x0}, - {0x1014d, 0x0}, - {0x1104d, 0x0}, - {0x1114d, 0x0}, - {0x11004d, 0x0}, - {0x11014d, 0x0}, - {0x11104d, 0x0}, - {0x11114d, 0x0}, - {0x21004d, 0x0}, - {0x21014d, 0x0}, - {0x21104d, 0x0}, - {0x21114d, 0x0}, - {0x10049, 0x0}, - {0x10149, 0x0}, - {0x11049, 0x0}, - {0x11149, 0x0}, - {0x110049, 0x0}, - {0x110149, 0x0}, - {0x111049, 0x0}, - {0x111149, 0x0}, - {0x210049, 0x0}, - {0x210149, 0x0}, - {0x211049, 0x0}, - {0x211149, 0x0}, - {0x43, 0x0}, - {0x1043, 0x0}, - {0x2043, 0x0}, - {0x20018, 0x0}, - {0x20075, 0x0}, - {0x20050, 0x0}, - {0x2009b, 0x0}, - {0x20008, 0x0}, - {0x120008, 0x0}, - {0x220008, 0x0}, - {0x20088, 0x0}, - {0x200b2, 0x0}, - {0x10043, 0x0}, - {0x10143, 0x0}, - {0x11043, 0x0}, - {0x11143, 0x0}, - {0x1200b2, 0x0}, - {0x110043, 0x0}, - {0x110143, 0x0}, - {0x111043, 0x0}, - {0x111143, 0x0}, - {0x2200b2, 0x0}, - {0x210043, 0x0}, - {0x210143, 0x0}, - {0x211043, 0x0}, - {0x211143, 0x0}, - {0x200fa, 0x0}, - {0x1200fa, 0x0}, - {0x2200fa, 0x0}, - {0x20019, 0x0}, - {0x120019, 0x0}, - {0x220019, 0x0}, - {0x200f0, 0x0}, - {0x200f1, 0x0}, - {0x200f2, 0x0}, - {0x200f3, 0x0}, - {0x200f4, 0x0}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0x0}, - {0x1004a, 0x0}, - {0x1104a, 0x0}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0xd0000, 0x0}, - {0x90000, 0x0}, - {0x90001, 0x0}, - {0x90002, 0x0}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x0}, - {0x90029, 0x0}, - {0x9002a, 0x0}, - {0x9002b, 0x0}, - {0x9002c, 0x0}, - {0x9002d, 0x0}, - {0x9002e, 0x0}, - {0x9002f, 0x0}, - {0x90030, 0x0}, - {0x90031, 0x0}, - {0x90032, 0x0}, - {0x90033, 0x0}, - {0x90034, 0x0}, - {0x90035, 0x0}, - {0x90036, 0x0}, - {0x90037, 0x0}, - {0x90038, 0x0}, - {0x90039, 0x0}, - {0x9003a, 0x0}, - {0x9003b, 0x0}, - {0x9003c, 0x0}, - {0x9003d, 0x0}, - {0x9003e, 0x0}, - {0x9003f, 0x0}, - {0x90040, 0x0}, - {0x90041, 0x0}, - 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{0x110180, 0x0}, - {0x110181, 0x0}, - {0x1101d0, 0x0}, - {0x1101d1, 0x0}, - {0x11018c, 0x0}, - {0x11018d, 0x0}, - {0x1100c0, 0x0}, - {0x1100c1, 0x0}, - {0x1101c0, 0x0}, - {0x1101c1, 0x0}, - {0x1102c0, 0x0}, - {0x1102c1, 0x0}, - {0x1103c0, 0x0}, - {0x1103c1, 0x0}, - {0x1104c0, 0x0}, - {0x1104c1, 0x0}, - {0x1105c0, 0x0}, - {0x1105c1, 0x0}, - {0x1106c0, 0x0}, - {0x1106c1, 0x0}, - {0x1107c0, 0x0}, - {0x1107c1, 0x0}, - {0x1108c0, 0x0}, - {0x1108c1, 0x0}, - {0x1100ae, 0x0}, - {0x1100af, 0x0}, - {0x111020, 0x0}, - {0x111080, 0x0}, - {0x111081, 0x0}, - {0x1110d0, 0x0}, - {0x1110d1, 0x0}, - {0x11108c, 0x0}, - {0x11108d, 0x0}, - {0x111180, 0x0}, - {0x111181, 0x0}, - {0x1111d0, 0x0}, - {0x1111d1, 0x0}, - {0x11118c, 0x0}, - {0x11118d, 0x0}, - {0x1110c0, 0x0}, - {0x1110c1, 0x0}, - {0x1111c0, 0x0}, - {0x1111c1, 0x0}, - {0x1112c0, 0x0}, - {0x1112c1, 0x0}, - {0x1113c0, 0x0}, - {0x1113c1, 0x0}, - {0x1114c0, 0x0}, - {0x1114c1, 0x0}, - {0x1115c0, 0x0}, - {0x1115c1, 0x0}, - {0x1116c0, 0x0}, - {0x1116c1, 0x0}, - {0x1117c0, 0x0}, - {0x1117c1, 0x0}, - {0x1118c0, 0x0}, - {0x1118c1, 0x0}, - {0x1110ae, 0x0}, - {0x1110af, 0x0}, - {0x190201, 0x0}, - {0x190202, 0x0}, - {0x190203, 0x0}, - {0x190205, 0x0}, - {0x190206, 0x0}, - {0x190207, 0x0}, - {0x190208, 0x0}, - {0x120020, 0x0}, - {0x200080, 0x0}, - {0x201080, 0x0}, - {0x202080, 0x0}, - {0x210020, 0x0}, - {0x210080, 0x0}, - {0x210081, 0x0}, - {0x2100d0, 0x0}, - {0x2100d1, 0x0}, - {0x21008c, 0x0}, - {0x21008d, 0x0}, - {0x210180, 0x0}, - {0x210181, 0x0}, - {0x2101d0, 0x0}, - {0x2101d1, 0x0}, - {0x21018c, 0x0}, - {0x21018d, 0x0}, - {0x2100c0, 0x0}, - {0x2100c1, 0x0}, - {0x2101c0, 0x0}, - {0x2101c1, 0x0}, - {0x2102c0, 0x0}, - {0x2102c1, 0x0}, - {0x2103c0, 0x0}, - {0x2103c1, 0x0}, - {0x2104c0, 0x0}, - {0x2104c1, 0x0}, - {0x2105c0, 0x0}, - {0x2105c1, 0x0}, - {0x2106c0, 0x0}, - {0x2106c1, 0x0}, - {0x2107c0, 0x0}, - {0x2107c1, 0x0}, - {0x2108c0, 0x0}, - {0x2108c1, 0x0}, - {0x2100ae, 0x0}, - {0x2100af, 0x0}, - {0x211020, 0x0}, - {0x211080, 0x0}, - {0x211081, 0x0}, - {0x2110d0, 0x0}, - {0x2110d1, 0x0}, - {0x21108c, 0x0}, - {0x21108d, 0x0}, - {0x211180, 0x0}, - {0x211181, 0x0}, - {0x2111d0, 0x0}, - {0x2111d1, 0x0}, - {0x21118c, 0x0}, - {0x21118d, 0x0}, - {0x2110c0, 0x0}, - {0x2110c1, 0x0}, - {0x2111c0, 0x0}, - {0x2111c1, 0x0}, - {0x2112c0, 0x0}, - {0x2112c1, 0x0}, - {0x2113c0, 0x0}, - {0x2113c1, 0x0}, - {0x2114c0, 0x0}, - {0x2114c1, 0x0}, - {0x2115c0, 0x0}, - {0x2115c1, 0x0}, - {0x2116c0, 0x0}, - {0x2116c1, 0x0}, - {0x2117c0, 0x0}, - {0x2117c1, 0x0}, - {0x2118c0, 0x0}, - {0x2118c1, 0x0}, - {0x2110ae, 0x0}, - {0x2110af, 0x0}, - {0x290201, 0x0}, - {0x290202, 0x0}, - {0x290203, 0x0}, - {0x290205, 0x0}, - {0x290206, 0x0}, - {0x290207, 0x0}, - {0x290208, 0x0}, - {0x220020, 0x0}, - {0x20077, 0x0}, - {0x20072, 0x0}, - {0x20073, 0x0}, - {0x400c0, 0x0}, - {0x10040, 0x0}, - {0x10140, 0x0}, - {0x10240, 0x0}, - {0x10340, 0x0}, - {0x10440, 0x0}, - {0x10540, 0x0}, - {0x10640, 0x0}, - {0x10740, 0x0}, - {0x10840, 0x0}, - {0x11040, 0x0}, - {0x11140, 0x0}, - {0x11240, 0x0}, - {0x11340, 0x0}, - {0x11440, 0x0}, - {0x11540, 0x0}, - {0x11640, 0x0}, - {0x11740, 0x0}, - {0x11840, 0x0}, -}; - -/* P0 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0x960}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x131f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x24c4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x24c4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xc400}, - {0x54033, 0x3324}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xc400}, - {0x54039, 0x3324}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P1 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp1_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x1}, - {0x54003, 0x4b0}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x52a4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x52a4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xa400}, - {0x54033, 0x3352}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xa400}, - {0x54039, 0x3352}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P2 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp2_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x102}, - {0x54003, 0x270}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x994}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4800}, - {0x5401e, 0x4}, - {0x5401f, 0x994}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4800}, - {0x54024, 0x4}, - {0x54032, 0x9400}, - {0x54033, 0x3309}, - {0x54034, 0x4600}, - {0x54035, 0x11}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0x9400}, - {0x54039, 0x3309}, - {0x5403a, 0x4600}, - {0x5403b, 0x11}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P0 2D message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0x960}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x61}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54010, 0x2080}, - {0x54012, 0x110}, - {0x54019, 0x24c4}, - {0x5401a, 0x33}, - {0x5401b, 0x1146}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x24c4}, - {0x54020, 0x33}, - {0x54021, 0x1146}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xc400}, - {0x54033, 0x3324}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xc400}, - {0x54039, 0x3324}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* DRAM PHY init engine image */ -static struct dram_cfg_param ddr_phy_pie[] = { - {0xd0000, 0x0}, - {0x90000, 0x10}, - {0x90001, 0x400}, - {0x90002, 0x10e}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x8}, - {0x90029, 0xb}, - {0x9002a, 0x480}, - {0x9002b, 0x109}, - {0x9002c, 0x8}, - {0x9002d, 0x448}, - {0x9002e, 0x139}, - {0x9002f, 0x8}, - {0x90030, 0x478}, - {0x90031, 0x109}, - {0x90032, 0x0}, - {0x90033, 0xe8}, - {0x90034, 0x109}, - {0x90035, 0x2}, - {0x90036, 0x10}, - {0x90037, 0x139}, - {0x90038, 0xb}, - {0x90039, 0x7c0}, - {0x9003a, 0x139}, - {0x9003b, 0x44}, - {0x9003c, 0x633}, - {0x9003d, 0x159}, - {0x9003e, 0x14f}, - {0x9003f, 0x630}, - {0x90040, 0x159}, - {0x90041, 0x47}, - {0x90042, 0x633}, - {0x90043, 0x149}, - {0x90044, 0x4f}, - {0x90045, 0x633}, - {0x90046, 0x179}, - {0x90047, 0x8}, - {0x90048, 0xe0}, - {0x90049, 0x109}, - {0x9004a, 0x0}, - {0x9004b, 0x7c8}, - {0x9004c, 0x109}, - {0x9004d, 0x0}, - {0x9004e, 0x1}, - {0x9004f, 0x8}, - {0x90050, 0x30}, - {0x90051, 0x65a}, - {0x90052, 0x9}, - {0x90053, 0x0}, - {0x90054, 0x45a}, - {0x90055, 0x9}, - {0x90056, 0x0}, - {0x90057, 0x448}, - {0x90058, 0x109}, - {0x90059, 0x40}, - {0x9005a, 0x633}, - {0x9005b, 0x179}, - {0x9005c, 0x1}, - {0x9005d, 0x618}, - {0x9005e, 0x109}, - {0x9005f, 0x40c0}, - {0x90060, 0x633}, - {0x90061, 0x149}, - {0x90062, 0x8}, - {0x90063, 0x4}, - {0x90064, 0x48}, - {0x90065, 0x4040}, - {0x90066, 0x633}, - {0x90067, 0x149}, - {0x90068, 0x0}, - {0x90069, 0x4}, - {0x9006a, 0x48}, - {0x9006b, 0x40}, - {0x9006c, 0x633}, - {0x9006d, 0x149}, - {0x9006e, 0x0}, - {0x9006f, 0x658}, - {0x90070, 0x109}, - {0x90071, 0x10}, - {0x90072, 0x4}, - {0x90073, 0x18}, - {0x90074, 0x0}, - {0x90075, 0x4}, - {0x90076, 0x78}, - {0x90077, 0x549}, - {0x90078, 0x633}, - {0x90079, 0x159}, - {0x9007a, 0xd49}, - {0x9007b, 0x633}, - {0x9007c, 0x159}, - {0x9007d, 0x94a}, - {0x9007e, 0x633}, - {0x9007f, 0x159}, - {0x90080, 0x441}, - {0x90081, 0x633}, - {0x90082, 0x149}, - {0x90083, 0x42}, - {0x90084, 0x633}, - {0x90085, 0x149}, - {0x90086, 0x1}, - {0x90087, 0x633}, - {0x90088, 0x149}, - {0x90089, 0x0}, - {0x9008a, 0xe0}, - {0x9008b, 0x109}, - {0x9008c, 0xa}, - {0x9008d, 0x10}, - {0x9008e, 0x109}, - {0x9008f, 0x9}, - {0x90090, 0x3c0}, - {0x90091, 0x149}, - {0x90092, 0x9}, - {0x90093, 0x3c0}, - {0x90094, 0x159}, - {0x90095, 0x18}, - {0x90096, 0x10}, - {0x90097, 0x109}, - {0x90098, 0x0}, - {0x90099, 0x3c0}, - {0x9009a, 0x109}, - {0x9009b, 0x18}, - {0x9009c, 0x4}, - {0x9009d, 0x48}, - {0x9009e, 0x18}, - {0x9009f, 0x4}, - {0x900a0, 0x58}, - {0x900a1, 0xb}, - {0x900a2, 0x10}, - {0x900a3, 0x109}, - {0x900a4, 0x1}, - {0x900a5, 0x10}, - {0x900a6, 0x109}, - {0x900a7, 0x5}, - {0x900a8, 0x7c0}, - {0x900a9, 0x109}, - {0x40000, 0x811}, - {0x40020, 0x880}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x4008}, - {0x40021, 0x83}, - {0x40041, 0x4f}, - {0x40061, 0x0}, - {0x40002, 0x4040}, - {0x40022, 0x83}, - {0x40042, 0x51}, - {0x40062, 0x0}, - {0x40003, 0x811}, - {0x40023, 0x880}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x720}, - {0x40024, 0xf}, - {0x40044, 0x1740}, - {0x40064, 0x0}, - {0x40005, 0x16}, - {0x40025, 0x83}, - {0x40045, 0x4b}, - {0x40065, 0x0}, - {0x40006, 0x716}, - {0x40026, 0xf}, - {0x40046, 0x2001}, - {0x40066, 0x0}, - {0x40007, 0x716}, - {0x40027, 0xf}, - {0x40047, 0x2800}, - {0x40067, 0x0}, - {0x40008, 0x716}, - {0x40028, 0xf}, - {0x40048, 0xf00}, - {0x40068, 0x0}, - {0x40009, 0x720}, - {0x40029, 0xf}, - {0x40049, 0x1400}, - {0x40069, 0x0}, - {0x4000a, 0xe08}, - {0x4002a, 0xc15}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x625}, - {0x4002b, 0x15}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x4028}, - {0x4002c, 0x80}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0xe08}, - {0x4002d, 0xc1a}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x625}, - {0x4002e, 0x1a}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x4040}, - {0x4002f, 0x80}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x2604}, - {0x40030, 0x15}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x708}, - {0x40031, 0x5}, - {0x40051, 0x0}, - {0x40071, 0x2002}, - {0x40012, 0x8}, - {0x40032, 0x80}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x2604}, - {0x40033, 0x1a}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x708}, - {0x40034, 0xa}, - {0x40054, 0x0}, - {0x40074, 0x2002}, - {0x40015, 0x4040}, - {0x40035, 0x80}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x60a}, - {0x40036, 0x15}, - {0x40056, 0x1200}, - {0x40076, 0x0}, - {0x40017, 0x61a}, - {0x40037, 0x15}, - {0x40057, 0x1300}, - {0x40077, 0x0}, - {0x40018, 0x60a}, - {0x40038, 0x1a}, - {0x40058, 0x1200}, - {0x40078, 0x0}, - {0x40019, 0x642}, - {0x40039, 0x1a}, - {0x40059, 0x1300}, - {0x40079, 0x0}, - {0x4001a, 0x4808}, - {0x4003a, 0x880}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x790}, - {0x900ac, 0x11a}, - {0x900ad, 0x8}, - {0x900ae, 0x7aa}, - {0x900af, 0x2a}, - {0x900b0, 0x10}, - {0x900b1, 0x7b2}, - {0x900b2, 0x2a}, - {0x900b3, 0x0}, - {0x900b4, 0x7c8}, - {0x900b5, 0x109}, - {0x900b6, 0x10}, - {0x900b7, 0x10}, - {0x900b8, 0x109}, - {0x900b9, 0x10}, - {0x900ba, 0x2a8}, - {0x900bb, 0x129}, - {0x900bc, 0x8}, - {0x900bd, 0x370}, - {0x900be, 0x129}, - {0x900bf, 0xa}, - {0x900c0, 0x3c8}, - {0x900c1, 0x1a9}, - {0x900c2, 0xc}, - {0x900c3, 0x408}, - {0x900c4, 0x199}, - {0x900c5, 0x14}, - {0x900c6, 0x790}, - {0x900c7, 0x11a}, - {0x900c8, 0x8}, - {0x900c9, 0x4}, - {0x900ca, 0x18}, - {0x900cb, 0xe}, - {0x900cc, 0x408}, - {0x900cd, 0x199}, - {0x900ce, 0x8}, - {0x900cf, 0x8568}, - {0x900d0, 0x108}, - {0x900d1, 0x18}, - {0x900d2, 0x790}, - {0x900d3, 0x16a}, - {0x900d4, 0x8}, - {0x900d5, 0x1d8}, - {0x900d6, 0x169}, - {0x900d7, 0x10}, - {0x900d8, 0x8558}, - {0x900d9, 0x168}, - {0x900da, 0x1ff8}, - {0x900db, 0x85a8}, - {0x900dc, 0x1e8}, - {0x900dd, 0x50}, - {0x900de, 0x798}, - {0x900df, 0x16a}, - {0x900e0, 0x60}, - {0x900e1, 0x7a0}, - {0x900e2, 0x16a}, - {0x900e3, 0x8}, - {0x900e4, 0x8310}, - {0x900e5, 0x168}, - {0x900e6, 0x8}, - {0x900e7, 0xa310}, - {0x900e8, 0x168}, - {0x900e9, 0xa}, - {0x900ea, 0x408}, - {0x900eb, 0x169}, - {0x900ec, 0x6e}, - {0x900ed, 0x0}, - {0x900ee, 0x68}, - {0x900ef, 0x0}, - {0x900f0, 0x408}, - {0x900f1, 0x169}, - {0x900f2, 0x0}, - {0x900f3, 0x8310}, - {0x900f4, 0x168}, - {0x900f5, 0x0}, - {0x900f6, 0xa310}, - {0x900f7, 0x168}, - {0x900f8, 0x1ff8}, - {0x900f9, 0x85a8}, - {0x900fa, 0x1e8}, - {0x900fb, 0x68}, - {0x900fc, 0x798}, - {0x900fd, 0x16a}, - {0x900fe, 0x78}, - {0x900ff, 0x7a0}, - {0x90100, 0x16a}, - {0x90101, 0x68}, - {0x90102, 0x790}, - {0x90103, 0x16a}, - {0x90104, 0x8}, - {0x90105, 0x8b10}, - {0x90106, 0x168}, - {0x90107, 0x8}, - {0x90108, 0xab10}, - {0x90109, 0x168}, - {0x9010a, 0xa}, - {0x9010b, 0x408}, - {0x9010c, 0x169}, - {0x9010d, 0x58}, - {0x9010e, 0x0}, - {0x9010f, 0x68}, - {0x90110, 0x0}, - {0x90111, 0x408}, - {0x90112, 0x169}, - {0x90113, 0x0}, - {0x90114, 0x8b10}, - {0x90115, 0x168}, - {0x90116, 0x1}, - {0x90117, 0xab10}, - {0x90118, 0x168}, - {0x90119, 0x0}, - {0x9011a, 0x1d8}, - {0x9011b, 0x169}, - {0x9011c, 0x80}, - {0x9011d, 0x790}, - {0x9011e, 0x16a}, - {0x9011f, 0x18}, - {0x90120, 0x7aa}, - {0x90121, 0x6a}, - {0x90122, 0xa}, - {0x90123, 0x0}, - {0x90124, 0x1e9}, - {0x90125, 0x8}, - {0x90126, 0x8080}, - {0x90127, 0x108}, - {0x90128, 0xf}, - {0x90129, 0x408}, - {0x9012a, 0x169}, - {0x9012b, 0xc}, - {0x9012c, 0x0}, - {0x9012d, 0x68}, - {0x9012e, 0x9}, - {0x9012f, 0x0}, - {0x90130, 0x1a9}, - {0x90131, 0x0}, - {0x90132, 0x408}, - {0x90133, 0x169}, - {0x90134, 0x0}, - {0x90135, 0x8080}, - {0x90136, 0x108}, - {0x90137, 0x8}, - {0x90138, 0x7aa}, - {0x90139, 0x6a}, - {0x9013a, 0x0}, - {0x9013b, 0x8568}, - {0x9013c, 0x108}, - {0x9013d, 0xb7}, - {0x9013e, 0x790}, - {0x9013f, 0x16a}, - {0x90140, 0x1f}, - {0x90141, 0x0}, - {0x90142, 0x68}, - {0x90143, 0x8}, - {0x90144, 0x8558}, - {0x90145, 0x168}, - {0x90146, 0xf}, - {0x90147, 0x408}, - {0x90148, 0x169}, - {0x90149, 0xd}, - {0x9014a, 0x0}, - {0x9014b, 0x68}, - {0x9014c, 0x0}, - {0x9014d, 0x408}, - {0x9014e, 0x169}, - {0x9014f, 0x0}, - {0x90150, 0x8558}, - {0x90151, 0x168}, - {0x90152, 0x8}, - {0x90153, 0x3c8}, - {0x90154, 0x1a9}, - {0x90155, 0x3}, - {0x90156, 0x370}, - {0x90157, 0x129}, - {0x90158, 0x20}, - {0x90159, 0x2aa}, - {0x9015a, 0x9}, - {0x9015b, 0x8}, - {0x9015c, 0xe8}, - {0x9015d, 0x109}, - {0x9015e, 0x0}, - {0x9015f, 0x8140}, - {0x90160, 0x10c}, - {0x90161, 0x10}, - {0x90162, 0x8138}, - {0x90163, 0x104}, - {0x90164, 0x8}, - {0x90165, 0x448}, - {0x90166, 0x109}, - {0x90167, 0xf}, - {0x90168, 0x7c0}, - {0x90169, 0x109}, - {0x9016a, 0x0}, - {0x9016b, 0xe8}, - {0x9016c, 0x109}, - {0x9016d, 0x47}, - {0x9016e, 0x630}, - {0x9016f, 0x109}, - {0x90170, 0x8}, - {0x90171, 0x618}, - {0x90172, 0x109}, - {0x90173, 0x8}, - {0x90174, 0xe0}, - {0x90175, 0x109}, - {0x90176, 0x0}, - {0x90177, 0x7c8}, - {0x90178, 0x109}, - {0x90179, 0x8}, - {0x9017a, 0x8140}, - {0x9017b, 0x10c}, - {0x9017c, 0x0}, - {0x9017d, 0x478}, - {0x9017e, 0x109}, - {0x9017f, 0x0}, - {0x90180, 0x1}, - {0x90181, 0x8}, - {0x90182, 0x8}, - {0x90183, 0x4}, - {0x90184, 0x0}, - {0x90006, 0x8}, - {0x90007, 0x7c8}, - {0x90008, 0x109}, - {0x90009, 0x0}, - {0x9000a, 0x400}, - {0x9000b, 0x106}, - {0xd00e7, 0x400}, - {0x90017, 0x0}, - {0x9001f, 0x2b}, - {0x90026, 0x69}, - {0x400d0, 0x0}, - {0x400d1, 0x101}, - {0x400d2, 0x105}, - {0x400d3, 0x107}, - {0x400d4, 0x10f}, - {0x400d5, 0x202}, - {0x400d6, 0x20a}, - {0x400d7, 0x20b}, - {0x2003a, 0x2}, - {0x200be, 0x3}, - {0x2000b, 0x2a3}, - {0x2000c, 0x96}, - {0x2000d, 0x5dc}, - {0x2000e, 0x2c}, - {0x12000b, 0x152}, - {0x12000c, 0x4b}, - {0x12000d, 0x2ee}, - {0x12000e, 0x2c}, - {0x22000b, 0xb0}, - {0x22000c, 0x27}, - {0x22000d, 0x186}, - {0x22000e, 0x10}, - {0x9000c, 0x0}, - {0x9000d, 0x173}, - {0x9000e, 0x60}, - {0x9000f, 0x6110}, - {0x90010, 0x2152}, - {0x90011, 0xdfbd}, - {0x90012, 0x2060}, - {0x90013, 0x6152}, - {0x20010, 0x5a}, - {0x20011, 0x3}, - {0x120010, 0x5a}, - {0x120011, 0x3}, - {0x40080, 0xe0}, - {0x40081, 0x12}, - {0x40082, 0xe0}, - {0x40083, 0x12}, - {0x40084, 0xe0}, - {0x40085, 0x12}, - {0x140080, 0xe0}, - {0x140081, 0x12}, - {0x140082, 0xe0}, - {0x140083, 0x12}, - {0x140084, 0xe0}, - {0x140085, 0x12}, - {0x240080, 0xe0}, - {0x240081, 0x12}, - {0x240082, 0xe0}, - {0x240083, 0x12}, - {0x240084, 0xe0}, - {0x240085, 0x12}, - {0x400fd, 0xf}, - {0x400f1, 0xe}, - {0x10011, 0x1}, - {0x10012, 0x1}, - {0x10013, 0x180}, - {0x10018, 0x1}, - {0x10002, 0x6209}, - {0x100b2, 0x1}, - {0x101b4, 0x1}, - {0x102b4, 0x1}, - {0x103b4, 0x1}, - {0x104b4, 0x1}, - {0x105b4, 0x1}, - {0x106b4, 0x1}, - {0x107b4, 0x1}, - {0x108b4, 0x1}, - {0x11011, 0x1}, - {0x11012, 0x1}, - {0x11013, 0x180}, - {0x11018, 0x1}, - {0x11002, 0x6209}, - {0x110b2, 0x1}, - {0x111b4, 0x1}, - {0x112b4, 0x1}, - {0x113b4, 0x1}, - {0x114b4, 0x1}, - {0x115b4, 0x1}, - {0x116b4, 0x1}, - {0x117b4, 0x1}, - {0x118b4, 0x1}, - {0x20089, 0x1}, - {0x20088, 0x19}, - {0xc0080, 0x0}, - {0xd0000, 0x1}, -}; - -static struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 2400mts 1D */ - .drate = 2400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 1200mts 1D */ - .drate = 1200, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 625mts 1D */ - .drate = 625, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 2400mts 2D */ - .drate = 2400, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing_2GB = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 2400, 1200, 625, }, - .fsp_cfg = ddr_dram_fsp_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), -}; diff --git a/board/freescale/imx91_frdm/lpddr4_timing.h b/board/freescale/imx91_frdm/lpddr4_timing.h deleted file mode 100644 index 9b483bbc3ed..00000000000 --- a/board/freescale/imx91_frdm/lpddr4_timing.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2025 NXP - */ - -#ifndef __LPDDR4_TIMING_H__ -#define __LPDDR4_TIMING_H__ - -extern struct dram_timing_info dram_timing_1GB; -extern struct dram_timing_info dram_timing_2GB; - -#endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/freescale/imx91_frdm/spl.c b/board/freescale/imx91_frdm/spl.c deleted file mode 100644 index cd59479d3b3..00000000000 --- a/board/freescale/imx91_frdm/spl.c +++ /dev/null @@ -1,193 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2025 NXP - */ - -#include "lpddr4_timing.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define SRC_DDRC_SW_CTRL (0x44461020) -#define SRC_DDRPHY_SINGLE_RESET_SW_CTRL (0x44461424) - -static struct _drams { - u8 mr8; - struct dram_timing_info *pdram_timing; - char *name; -} frdm_drams[2] = { - {0x10, &dram_timing_1GB, "1GB DRAM" }, - {0x18, &dram_timing_2GB, "2GB DRAM" }, -}; - -int spl_board_boot_device(enum boot_device boot_dev_spl) -{ - return BOOT_DEVICE_BOOTROM; -} - -void spl_board_init(void) -{ - int ret; - - ret = ele_start_rng(); - if (ret) - printf("Fail to start RNG: %d\n", ret); - - puts("Normal Boot\n"); -} - -void spl_dram_init(void) -{ - int i; - int ret; - - for (i = 0; i < ARRAY_SIZE(frdm_drams); i++) { - struct dram_timing_info *ptiming = frdm_drams[i].pdram_timing; - - printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate); - ret = ddr_init(ptiming); - if (ret == 0) { - if (lpddr4_mr_read(1, 8) == frdm_drams[i].mr8) { - printf("found DRAM %s matched\n", frdm_drams[i].name); - break; - } - - /* Power down and Power up DDR Mixer */ - - /* Clear PwrOkIn via DDRMIX register */ - setbits_32(SRC_DDRPHY_SINGLE_RESET_SW_CTRL, BIT(0)); - /* Power off the DDRMIX */ - setbits_32(SRC_DDRC_SW_CTRL, BIT(31)); - - udelay(50); - - /* Power up the DDRMIX */ - clrbits_32(SRC_DDRC_SW_CTRL, BIT(31)); - setbits_32(SRC_DDRC_SW_CTRL, BIT(0)); - udelay(10); - clrbits_32(SRC_DDRC_SW_CTRL, BIT(0)); - udelay(10); - } - } -} - -#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) -int power_init_board(void) -{ - struct udevice *dev; - int ret; - unsigned int val = 0, buck_val; - - ret = pmic_get("pmic@25", &dev); - if (ret == -ENODEV) { - puts("ERROR: Get PMIC PCA9451A failed!\n"); - return ret; - } - if (ret != 0) - return ret; - - /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); - - /* enable DVS control through PMIC_STBY_REQ */ - pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); - - ret = pmic_reg_read(dev, PCA9450_PWR_CTRL); - if (ret < 0) - return ret; - - val = ret; - - if (is_voltage_mode(VOLT_LOW_DRIVE)) { - buck_val = 0x0c; /* 0.8V for Low drive mode */ - printf("PMIC: Low Drive Voltage Mode\n"); - } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) { - buck_val = 0x10; /* 0.85V for Nominal drive mode */ - printf("PMIC: Nominal Voltage Mode\n"); - } else { - buck_val = 0x14; /* 0.9V for Over drive mode */ - printf("PMIC: Over Drive Voltage Mode\n"); - } - - if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val); - } else { - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4); - } - - /* Set VDDQ to 1.1V from buck2 (buck2 not used for iMX91 EVK) */ - pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28); - - /* set standby voltage to 0.65V */ - if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0); - else - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); - - /* I2C_LT_EN*/ - pmic_reg_write(dev, 0xa, 0x3); - return 0; -} -#endif - -void board_init_f(ulong dummy) -{ - int ret; - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - timer_init(); - - arch_cpu_init(); - - spl_early_init(); - - preloader_console_init(); - - ret = imx9_probe_mu(); - if (ret) { - printf("Fail to init ELE API\n"); - } else { - debug("SOC: 0x%x\n", gd->arch.soc_rev); - debug("LC: 0x%x\n", gd->arch.lifecycle); - } - - clock_init_late(); - - power_init_board(); - - if (!is_voltage_mode(VOLT_LOW_DRIVE)) - set_arm_clk(get_cpu_speed_grade_hz()); - - /* Init power of mix */ - soc_power_init(); - - /* Setup TRDC for DDR access */ - trdc_init(); - - /* DDR initialization */ - spl_dram_init(); - - board_init_r(NULL, 0); -} diff --git a/board/freescale/imx93_evk/Kconfig b/board/freescale/imx93_evk/Kconfig deleted file mode 100644 index 821144c9382..00000000000 --- a/board/freescale/imx93_evk/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -if TARGET_IMX93_11X11_EVK - -config SYS_BOARD - default "imx93_evk" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "imx93_evk" - -config IMX93_EVK_LPDDR4X - bool "Using LPDDR4X Timing and PMIC voltage" - default y - select IMX9_LPDDR4X - help - Select the LPDDR4X timing and 0.6V VDDQ - -endif diff --git a/board/freescale/imx93_evk/MAINTAINERS b/board/freescale/imx93_evk/MAINTAINERS deleted file mode 100644 index eb6e669bd17..00000000000 --- a/board/freescale/imx93_evk/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -i.MX93 EVK BOARD -M: Peng Fan -S: Maintained -F: board/freescale/imx93_evk/ -F: include/configs/imx93_evk.h -F: configs/imx93_11x11_evk_defconfig -F: configs/imx93_11x11_evk_ld_defconfig diff --git a/board/freescale/imx93_evk/Makefile b/board/freescale/imx93_evk/Makefile deleted file mode 100644 index b077acc70a5..00000000000 --- a/board/freescale/imx93_evk/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright 2022 NXP -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += imx93_evk.o - -ifdef CONFIG_XPL_BUILD -obj-y += spl.o -obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o lpddr4x_timing_1866mts.o -endif diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c deleted file mode 100644 index 70b07fa3c6f..00000000000 --- a/board/freescale/imx93_evk/imx93_evk.c +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2022 NXP - */ - -#include -#include -#include -#include - -#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) -#define IMX_BOOT_IMAGE_GUID \ - EFI_GUID(0xbc550d86, 0xda26, 0x4b70, 0xac, 0x05, \ - 0x2a, 0x44, 0x8e, 0xda, 0x6f, 0x21) - -struct efi_fw_image fw_images[] = { - { - .image_type_id = IMX_BOOT_IMAGE_GUID, - .fw_name = u"IMX93-11X11-EVK-RAW", - .image_index = 1, - }, -}; - -struct efi_capsule_update_info update_info = { - .dfu_string = "mmc 0=flash-bin raw 0 0x2000 mmcpart 1", - .num_images = ARRAY_SIZE(fw_images), - .images = fw_images, -}; -#endif /* EFI_HAVE_CAPSULE_SUPPORT */ - -int board_late_init(void) -{ -#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) || CONFIG_IS_ENABLED(ENV_IS_NOWHERE) - board_late_mmc_env_init(); -#endif - -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - env_set("board_name", "11X11_EVK"); - env_set("board_rev", "iMX93"); -#endif - return 0; -} diff --git a/board/freescale/imx93_evk/imx93_evk.env b/board/freescale/imx93_evk/imx93_evk.env deleted file mode 100644 index d5ed216f54b..00000000000 --- a/board/freescale/imx93_evk/imx93_evk.env +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ - -boot_targets=mmc0 mmc1 -boot_fit=no -bootm_size=0x10000000 -cntr_addr=0x98000000 -cntr_file=os_cntr_signed.bin -console=ttyLP0,115200 earlycon -fdt_addr_r=0x83000000 -fdt_addr=0x83000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE -image=Image -mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX -mmcpart=1 -mmcroot=/dev/mmcblk1p2 rootwait rw -mmcautodetect=yes -mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} -prepare_mcore=setenv mcore_clk clk-imx93.mcore_booted -kernel_addr_r=CONFIG_SYS_LOAD_ADDR -loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} -loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} -auth_os=auth_cntr ${cntr_addr} -sec_boot=no -boot_os=booti ${loadaddr} - ${fdt_addr_r} -mmcboot= - echo Booting from mmc ...; - run mmcargs; - if test ${sec_boot} = yes; then - if true; then - run boot_os; - else - echo ERR: failed to authenticate; - fi; - else - if run loadfdt; then - run boot_os; - else - echo WARN: Cannot load the DT; - fi; - fi; -netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs - ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp -netboot= - echo Booting from net ...; - run netargs; - if test ${ip_dyn} = yes; then - setenv get_cmd dhcp; - else - setenv get_cmd tftp; - fi; - if test ${sec_boot} = yes; then - ${get_cmd} ${cntr_addr} ${cntr_file}; - if true; then - run boot_os; - else - echo ERR: failed to authenticate; - fi; - else - ${get_cmd} ${loadaddr} ${image}; - if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then - run boot_os; - else - echo WARN: Cannot load the DT; - fi; - fi; -bsp_bootcmd= - echo Running BSP bootcmd ...; - mmc dev ${mmcdev}; - if mmc rescan; then - if run loadbootscript; then - run bootscript; - else - if test ${sec_boot} = yes; then - if run loadcntr; then - run mmcboot; - else - run netboot; - fi; - else - if run loadimage; then - run mmcboot; - else - run netboot; - fi; - fi; - fi; - fi; -scriptaddr=0x83500000 diff --git a/board/freescale/imx93_evk/lpddr4x_timing.c b/board/freescale/imx93_evk/lpddr4x_timing.c deleted file mode 100644 index ffdf96b739f..00000000000 --- a/board/freescale/imx93_evk/lpddr4x_timing.c +++ /dev/null @@ -1,1994 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2023 NXP - * - * Code generated with DDR Tool v2.0.0_5.3. - */ - -#include -#include - -struct dram_cfg_param ddr_ddrc_cfg[] = { - /** Initialize DDRC registers **/ - {0x4e300110, 0x44100001}, - {0x4e300000, 0x8000ff}, - {0x4e300008, 0x0}, - {0x4e300080, 0x80000512}, - {0x4e300084, 0x0}, - {0x4e300114, 0x1002}, - {0x4e300260, 0x80}, - {0x4e300f04, 0x80}, - {0x4e300800, 0x43b30002}, - {0x4e300804, 0x1f1f1f1f}, - {0x4e301000, 0x0}, - {0x4e301240, 0x0}, - {0x4e301244, 0x0}, - {0x4e301248, 0x0}, - {0x4e30124c, 0x0}, - {0x4e301250, 0x0}, - {0x4e301254, 0x0}, - {0x4e301258, 0x0}, - {0x4e30125c, 0x0}, -}; - -/* dram fsp cfg */ -static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { - { - { - {0x4e300100, 0x24AB321B}, - {0x4e300104, 0xF8EE001B}, - {0x4e300108, 0x2F2EE233}, - {0x4e30010C, 0x0005E18B}, - {0x4e300124, 0x1C770000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x35F00000}, - {0x4e300170, 0x8B0B0608}, - {0x4e300250, 0x00000028}, - {0x4e300254, 0x015B015B}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - {0x4e300300, 0x224F2213}, - {0x4e300304, 0x015B2213}, - {0x4e300308, 0x0A3C0E3C}, - }, - { - {0x01, 0xE4}, - {0x02, 0x36}, - {0x03, 0x32}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x11}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x12552100}, - {0x4e300104, 0xF877000E}, - {0x4e300108, 0x1816B4AA}, - {0x4e30010C, 0x005101E6}, - {0x4e300124, 0x0E3C0000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30900000}, - {0x4e300170, 0x8A0A0508}, - {0x4e300250, 0x00000014}, - {0x4e300254, 0x00AA00AA}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0xB4}, - {0x02, 0x1B}, - {0x03, 0x32}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x11}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x00061000}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0x6E62FA48}, - {0x4e30010C, 0x0031010D}, - {0x4e300124, 0x04C50000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x30000000}, - {0x4e300170, 0x89090408}, - {0x4e300250, 0x00000007}, - {0x4e300254, 0x00340034}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0x94}, - {0x02, 0x9}, - {0x03, 0x32}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x11}, - {0x16, 0x04}, - }, - 1, - } -}; - -/* PHY Initialize Configuration */ -struct dram_cfg_param ddr_ddrphy_cfg[] = { - {0x100a0, 0x4}, - {0x100a1, 0x5}, - {0x100a2, 0x6}, - {0x100a3, 0x7}, - {0x100a4, 0x0}, - {0x100a5, 0x1}, - {0x100a6, 0x2}, - {0x100a7, 0x3}, - {0x110a0, 0x3}, - {0x110a1, 0x2}, - {0x110a2, 0x0}, - {0x110a3, 0x1}, - {0x110a4, 0x7}, - {0x110a5, 0x6}, - {0x110a6, 0x4}, - {0x110a7, 0x5}, - {0x1005f, 0x5ff}, - {0x1015f, 0x5ff}, - {0x1105f, 0x5ff}, - {0x1115f, 0x5ff}, - {0x11005f, 0x5ff}, - {0x11015f, 0x5ff}, - {0x11105f, 0x5ff}, - {0x11115f, 0x5ff}, - {0x21005f, 0x5ff}, - {0x21015f, 0x5ff}, - {0x21105f, 0x5ff}, - {0x21115f, 0x5ff}, - {0x55, 0x1ff}, - {0x1055, 0x1ff}, - {0x2055, 0x1ff}, - {0x200c5, 0x19}, - {0x1200c5, 0xb}, - {0x2200c5, 0x7}, - {0x2002e, 0x2}, - {0x12002e, 0x2}, - {0x22002e, 0x2}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x1e3}, - {0x2003a, 0x2}, - {0x2007d, 0x212}, - {0x2007c, 0x61}, - {0x120024, 0x1e3}, - {0x2003a, 0x2}, - {0x12007d, 0x212}, - {0x12007c, 0x61}, - {0x220024, 0x1e3}, - {0x2003a, 0x2}, - {0x22007d, 0x212}, - {0x22007c, 0x61}, - {0x20056, 0x3}, - {0x120056, 0x3}, - {0x220056, 0x3}, - {0x1004d, 0x600}, - {0x1014d, 0x600}, - {0x1104d, 0x600}, - {0x1114d, 0x600}, - {0x11004d, 0x600}, - {0x11014d, 0x600}, - {0x11104d, 0x600}, - {0x11114d, 0x600}, - {0x21004d, 0x600}, - {0x21014d, 0x600}, - {0x21104d, 0x600}, - {0x21114d, 0x600}, - {0x10049, 0xe00}, - {0x10149, 0xe00}, - {0x11049, 0xe00}, - {0x11149, 0xe00}, - {0x110049, 0xe00}, - {0x110149, 0xe00}, - {0x111049, 0xe00}, - {0x111149, 0xe00}, - {0x210049, 0xe00}, - {0x210149, 0xe00}, - {0x211049, 0xe00}, - {0x211149, 0xe00}, - {0x43, 0x60}, - {0x1043, 0x60}, - {0x2043, 0x60}, - {0x20018, 0x1}, - {0x20075, 0x4}, - {0x20050, 0x0}, - {0x2009b, 0x2}, - {0x20008, 0x3a5}, - {0x120008, 0x1d3}, - {0x220008, 0x9c}, - {0x20088, 0x9}, - {0x200b2, 0x10c}, - {0x10043, 0x5a1}, - {0x10143, 0x5a1}, - {0x11043, 0x5a1}, - {0x11143, 0x5a1}, - {0x1200b2, 0x10c}, - {0x110043, 0x5a1}, - {0x110143, 0x5a1}, - {0x111043, 0x5a1}, - {0x111143, 0x5a1}, - {0x2200b2, 0x10c}, - {0x210043, 0x5a1}, - {0x210143, 0x5a1}, - {0x211043, 0x5a1}, - {0x211143, 0x5a1}, - {0x200fa, 0x2}, - {0x1200fa, 0x2}, - {0x2200fa, 0x2}, - {0x20019, 0x1}, - {0x120019, 0x1}, - {0x220019, 0x1}, - {0x200f0, 0x600}, - {0x200f1, 0x0}, - {0x200f2, 0x4444}, - {0x200f3, 0x8888}, - {0x200f4, 0x5655}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0xf000}, - {0x1004a, 0x500}, - {0x1104a, 0x500}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0x20021, 0x0}, - {0x200c7, 0x21}, - {0x1200c7, 0x21}, - {0x200ca, 0x24}, - {0x1200ca, 0x24} -}; - -/* ddr phy trained csr */ -struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - {0x1005f, 0x0}, - {0x1015f, 0x0}, - {0x1105f, 0x0}, - {0x1115f, 0x0}, - {0x11005f, 0x0}, - {0x11015f, 0x0}, - {0x11105f, 0x0}, - {0x11115f, 0x0}, - {0x21005f, 0x0}, - {0x21015f, 0x0}, - {0x21105f, 0x0}, - {0x21115f, 0x0}, - {0x55, 0x0}, - {0x1055, 0x0}, - {0x2055, 0x0}, - {0x200c5, 0x0}, - {0x1200c5, 0x0}, - {0x2200c5, 0x0}, - {0x2002e, 0x0}, - {0x12002e, 0x0}, - {0x22002e, 0x0}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x0}, - {0x2003a, 0x0}, - {0x2007d, 0x0}, - {0x2007c, 0x0}, - {0x120024, 0x0}, - {0x12007d, 0x0}, - {0x12007c, 0x0}, - {0x220024, 0x0}, - {0x22007d, 0x0}, - {0x22007c, 0x0}, - {0x20056, 0x0}, - {0x120056, 0x0}, - {0x220056, 0x0}, - {0x1004d, 0x0}, - {0x1014d, 0x0}, - {0x1104d, 0x0}, - {0x1114d, 0x0}, - {0x11004d, 0x0}, - {0x11014d, 0x0}, - {0x11104d, 0x0}, - {0x11114d, 0x0}, - {0x21004d, 0x0}, - {0x21014d, 0x0}, - {0x21104d, 0x0}, - {0x21114d, 0x0}, - {0x10049, 0x0}, - {0x10149, 0x0}, - {0x11049, 0x0}, - {0x11149, 0x0}, - {0x110049, 0x0}, - {0x110149, 0x0}, - {0x111049, 0x0}, - {0x111149, 0x0}, - {0x210049, 0x0}, - {0x210149, 0x0}, - {0x211049, 0x0}, - {0x211149, 0x0}, - {0x43, 0x0}, - {0x1043, 0x0}, - {0x2043, 0x0}, - {0x20018, 0x0}, - {0x20075, 0x0}, - {0x20050, 0x0}, - {0x2009b, 0x0}, - {0x20008, 0x0}, - {0x120008, 0x0}, - {0x220008, 0x0}, - {0x20088, 0x0}, - {0x200b2, 0x0}, - {0x10043, 0x0}, - {0x10143, 0x0}, - {0x11043, 0x0}, - {0x11143, 0x0}, - {0x1200b2, 0x0}, - {0x110043, 0x0}, - {0x110143, 0x0}, - {0x111043, 0x0}, - {0x111143, 0x0}, - {0x2200b2, 0x0}, - {0x210043, 0x0}, - {0x210143, 0x0}, - {0x211043, 0x0}, - {0x211143, 0x0}, - {0x200fa, 0x0}, - {0x1200fa, 0x0}, - {0x2200fa, 0x0}, - {0x20019, 0x0}, - {0x120019, 0x0}, - {0x220019, 0x0}, - {0x200f0, 0x0}, - {0x200f1, 0x0}, - {0x200f2, 0x0}, - {0x200f3, 0x0}, - {0x200f4, 0x0}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0x0}, - {0x1004a, 0x0}, - {0x1104a, 0x0}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0xd0000, 0x0}, - {0x90000, 0x0}, - {0x90001, 0x0}, - {0x90002, 0x0}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x0}, - {0x90029, 0x0}, - {0x9002a, 0x0}, - {0x9002b, 0x0}, - {0x9002c, 0x0}, - {0x9002d, 0x0}, - {0x9002e, 0x0}, - {0x9002f, 0x0}, - {0x90030, 0x0}, - {0x90031, 0x0}, - {0x90032, 0x0}, - {0x90033, 0x0}, - {0x90034, 0x0}, - {0x90035, 0x0}, - {0x90036, 0x0}, - {0x90037, 0x0}, - {0x90038, 0x0}, - {0x90039, 0x0}, - {0x9003a, 0x0}, - {0x9003b, 0x0}, - {0x9003c, 0x0}, - {0x9003d, 0x0}, - {0x9003e, 0x0}, - {0x9003f, 0x0}, - {0x90040, 0x0}, - {0x90041, 0x0}, - {0x90042, 0x0}, - {0x90043, 0x0}, - {0x90044, 0x0}, - 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{0x100af, 0x0}, - {0x11020, 0x0}, - {0x11080, 0x0}, - {0x11081, 0x0}, - {0x110d0, 0x0}, - {0x110d1, 0x0}, - {0x1108c, 0x0}, - {0x1108d, 0x0}, - {0x11180, 0x0}, - {0x11181, 0x0}, - {0x111d0, 0x0}, - {0x111d1, 0x0}, - {0x1118c, 0x0}, - {0x1118d, 0x0}, - {0x110c0, 0x0}, - {0x110c1, 0x0}, - {0x111c0, 0x0}, - {0x111c1, 0x0}, - {0x112c0, 0x0}, - {0x112c1, 0x0}, - {0x113c0, 0x0}, - {0x113c1, 0x0}, - {0x114c0, 0x0}, - {0x114c1, 0x0}, - {0x115c0, 0x0}, - {0x115c1, 0x0}, - {0x116c0, 0x0}, - {0x116c1, 0x0}, - {0x117c0, 0x0}, - {0x117c1, 0x0}, - {0x118c0, 0x0}, - {0x118c1, 0x0}, - {0x110ae, 0x0}, - {0x110af, 0x0}, - {0x90201, 0x0}, - {0x90202, 0x0}, - {0x90203, 0x0}, - {0x90205, 0x0}, - {0x90206, 0x0}, - {0x90207, 0x0}, - {0x90208, 0x0}, - {0x20020, 0x0}, - {0x100080, 0x0}, - {0x101080, 0x0}, - {0x102080, 0x0}, - {0x110020, 0x0}, - {0x110080, 0x0}, - {0x110081, 0x0}, - {0x1100d0, 0x0}, - {0x1100d1, 0x0}, - {0x11008c, 0x0}, - {0x11008d, 0x0}, - {0x110180, 0x0}, - {0x110181, 0x0}, - {0x1101d0, 0x0}, - {0x1101d1, 0x0}, - {0x11018c, 0x0}, - {0x11018d, 0x0}, - {0x1100c0, 0x0}, - {0x1100c1, 0x0}, - {0x1101c0, 0x0}, - {0x1101c1, 0x0}, - {0x1102c0, 0x0}, - {0x1102c1, 0x0}, - {0x1103c0, 0x0}, - {0x1103c1, 0x0}, - {0x1104c0, 0x0}, - {0x1104c1, 0x0}, - {0x1105c0, 0x0}, - {0x1105c1, 0x0}, - {0x1106c0, 0x0}, - {0x1106c1, 0x0}, - {0x1107c0, 0x0}, - {0x1107c1, 0x0}, - {0x1108c0, 0x0}, - {0x1108c1, 0x0}, - {0x1100ae, 0x0}, - {0x1100af, 0x0}, - {0x111020, 0x0}, - {0x111080, 0x0}, - {0x111081, 0x0}, - {0x1110d0, 0x0}, - {0x1110d1, 0x0}, - {0x11108c, 0x0}, - {0x11108d, 0x0}, - {0x111180, 0x0}, - {0x111181, 0x0}, - {0x1111d0, 0x0}, - {0x1111d1, 0x0}, - {0x11118c, 0x0}, - {0x11118d, 0x0}, - {0x1110c0, 0x0}, - {0x1110c1, 0x0}, - {0x1111c0, 0x0}, - {0x1111c1, 0x0}, - {0x1112c0, 0x0}, - {0x1112c1, 0x0}, - {0x1113c0, 0x0}, - {0x1113c1, 0x0}, - {0x1114c0, 0x0}, - {0x1114c1, 0x0}, - {0x1115c0, 0x0}, - {0x1115c1, 0x0}, - {0x1116c0, 0x0}, - {0x1116c1, 0x0}, - {0x1117c0, 0x0}, - {0x1117c1, 0x0}, - {0x1118c0, 0x0}, - {0x1118c1, 0x0}, - {0x1110ae, 0x0}, - {0x1110af, 0x0}, - {0x190201, 0x0}, - {0x190202, 0x0}, - {0x190203, 0x0}, - {0x190205, 0x0}, - {0x190206, 0x0}, - {0x190207, 0x0}, - {0x190208, 0x0}, - {0x120020, 0x0}, - {0x200080, 0x0}, - {0x201080, 0x0}, - {0x202080, 0x0}, - {0x210020, 0x0}, - {0x210080, 0x0}, - {0x210081, 0x0}, - {0x2100d0, 0x0}, - {0x2100d1, 0x0}, - {0x21008c, 0x0}, - {0x21008d, 0x0}, - {0x210180, 0x0}, - {0x210181, 0x0}, - {0x2101d0, 0x0}, - {0x2101d1, 0x0}, - {0x21018c, 0x0}, - {0x21018d, 0x0}, - {0x2100c0, 0x0}, - {0x2100c1, 0x0}, - {0x2101c0, 0x0}, - {0x2101c1, 0x0}, - {0x2102c0, 0x0}, - {0x2102c1, 0x0}, - {0x2103c0, 0x0}, - {0x2103c1, 0x0}, - {0x2104c0, 0x0}, - {0x2104c1, 0x0}, - {0x2105c0, 0x0}, - {0x2105c1, 0x0}, - {0x2106c0, 0x0}, - {0x2106c1, 0x0}, - {0x2107c0, 0x0}, - {0x2107c1, 0x0}, - {0x2108c0, 0x0}, - {0x2108c1, 0x0}, - {0x2100ae, 0x0}, - {0x2100af, 0x0}, - {0x211020, 0x0}, - {0x211080, 0x0}, - {0x211081, 0x0}, - {0x2110d0, 0x0}, - {0x2110d1, 0x0}, - {0x21108c, 0x0}, - {0x21108d, 0x0}, - {0x211180, 0x0}, - {0x211181, 0x0}, - {0x2111d0, 0x0}, - {0x2111d1, 0x0}, - {0x21118c, 0x0}, - {0x21118d, 0x0}, - {0x2110c0, 0x0}, - {0x2110c1, 0x0}, - {0x2111c0, 0x0}, - {0x2111c1, 0x0}, - {0x2112c0, 0x0}, - {0x2112c1, 0x0}, - {0x2113c0, 0x0}, - {0x2113c1, 0x0}, - {0x2114c0, 0x0}, - {0x2114c1, 0x0}, - {0x2115c0, 0x0}, - {0x2115c1, 0x0}, - {0x2116c0, 0x0}, - {0x2116c1, 0x0}, - {0x2117c0, 0x0}, - {0x2117c1, 0x0}, - {0x2118c0, 0x0}, - {0x2118c1, 0x0}, - {0x2110ae, 0x0}, - {0x2110af, 0x0}, - {0x290201, 0x0}, - {0x290202, 0x0}, - {0x290203, 0x0}, - {0x290205, 0x0}, - {0x290206, 0x0}, - {0x290207, 0x0}, - {0x290208, 0x0}, - {0x220020, 0x0}, - {0x20077, 0x0}, - {0x20072, 0x0}, - {0x20073, 0x0}, - {0x400c0, 0x0}, - {0x10040, 0x0}, - {0x10140, 0x0}, - {0x10240, 0x0}, - {0x10340, 0x0}, - {0x10440, 0x0}, - {0x10540, 0x0}, - {0x10640, 0x0}, - {0x10740, 0x0}, - {0x10840, 0x0}, - {0x11040, 0x0}, - {0x11140, 0x0}, - {0x11240, 0x0}, - {0x11340, 0x0}, - {0x11440, 0x0}, - {0x11540, 0x0}, - {0x11640, 0x0}, - {0x11740, 0x0}, - {0x11840, 0x0}, -}; - -/* P0 message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp0_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0xe94}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x131f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x36e4}, - {0x5401a, 0x32}, - {0x5401b, 0x1146}, - {0x5401c, 0x1108}, - {0x5401e, 0x4}, - {0x5401f, 0x36e4}, - {0x54020, 0x32}, - {0x54021, 0x1146}, - {0x54022, 0x1108}, - {0x54024, 0x4}, - {0x54032, 0xe400}, - {0x54033, 0x3236}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x11}, - {0x54037, 0x400}, - {0x54038, 0xe400}, - {0x54039, 0x3236}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x11}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P1 message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp1_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x1}, - {0x54003, 0x74a}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x1bb4}, - {0x5401a, 0x32}, - {0x5401b, 0x1146}, - {0x5401c, 0x1108}, - {0x5401e, 0x4}, - {0x5401f, 0x1bb4}, - {0x54020, 0x32}, - {0x54021, 0x1146}, - {0x54022, 0x1108}, - {0x54024, 0x4}, - {0x54032, 0xb400}, - {0x54033, 0x321b}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x11}, - {0x54037, 0x400}, - {0x54038, 0xb400}, - {0x54039, 0x321b}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x11}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P2 message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp2_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x102}, - {0x54003, 0x270}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x994}, - {0x5401a, 0x32}, - {0x5401b, 0x1146}, - {0x5401c, 0x1100}, - {0x5401e, 0x4}, - {0x5401f, 0x994}, - {0x54020, 0x32}, - {0x54021, 0x1146}, - {0x54022, 0x1100}, - {0x54024, 0x4}, - {0x54032, 0x9400}, - {0x54033, 0x3209}, - {0x54034, 0x4600}, - {0x54035, 0x11}, - {0x54036, 0x11}, - {0x54037, 0x400}, - {0x54038, 0x9400}, - {0x54039, 0x3209}, - {0x5403a, 0x4600}, - {0x5403b, 0x11}, - {0x5403c, 0x11}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P0 2D message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0xe94}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x61}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54010, 0x2080}, - {0x54012, 0x110}, - {0x54019, 0x36e4}, - {0x5401a, 0x32}, - {0x5401b, 0x1146}, - {0x5401c, 0x1108}, - {0x5401e, 0x4}, - {0x5401f, 0x36e4}, - {0x54020, 0x32}, - {0x54021, 0x1146}, - {0x54022, 0x1108}, - {0x54024, 0x4}, - {0x54032, 0xe400}, - {0x54033, 0x3236}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x11}, - {0x54037, 0x400}, - {0x54038, 0xe400}, - {0x54039, 0x3236}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x11}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* DRAM PHY init engine image */ -struct dram_cfg_param ddr_phy_pie[] = { - {0xd0000, 0x0}, - {0x90000, 0x10}, - {0x90001, 0x400}, - {0x90002, 0x10e}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x8}, - {0x90029, 0xb}, - {0x9002a, 0x480}, - {0x9002b, 0x109}, - {0x9002c, 0x8}, - {0x9002d, 0x448}, - {0x9002e, 0x139}, - {0x9002f, 0x8}, - {0x90030, 0x478}, - {0x90031, 0x109}, - {0x90032, 0x0}, - {0x90033, 0xe8}, - {0x90034, 0x109}, - {0x90035, 0x2}, - {0x90036, 0x10}, - {0x90037, 0x139}, - {0x90038, 0xb}, - {0x90039, 0x7c0}, - {0x9003a, 0x139}, - {0x9003b, 0x44}, - {0x9003c, 0x633}, - {0x9003d, 0x159}, - {0x9003e, 0x14f}, - {0x9003f, 0x630}, - {0x90040, 0x159}, - {0x90041, 0x47}, - {0x90042, 0x633}, - {0x90043, 0x149}, - {0x90044, 0x4f}, - {0x90045, 0x633}, - {0x90046, 0x179}, - {0x90047, 0x8}, - {0x90048, 0xe0}, - {0x90049, 0x109}, - {0x9004a, 0x0}, - {0x9004b, 0x7c8}, - {0x9004c, 0x109}, - {0x9004d, 0x0}, - {0x9004e, 0x1}, - {0x9004f, 0x8}, - {0x90050, 0x30}, - {0x90051, 0x65a}, - {0x90052, 0x9}, - {0x90053, 0x0}, - {0x90054, 0x45a}, - {0x90055, 0x9}, - {0x90056, 0x0}, - {0x90057, 0x448}, - {0x90058, 0x109}, - {0x90059, 0x40}, - {0x9005a, 0x633}, - {0x9005b, 0x179}, - {0x9005c, 0x1}, - {0x9005d, 0x618}, - {0x9005e, 0x109}, - {0x9005f, 0x40c0}, - {0x90060, 0x633}, - {0x90061, 0x149}, - {0x90062, 0x8}, - {0x90063, 0x4}, - {0x90064, 0x48}, - {0x90065, 0x4040}, - {0x90066, 0x633}, - {0x90067, 0x149}, - {0x90068, 0x0}, - {0x90069, 0x4}, - {0x9006a, 0x48}, - {0x9006b, 0x40}, - {0x9006c, 0x633}, - {0x9006d, 0x149}, - {0x9006e, 0x0}, - {0x9006f, 0x658}, - {0x90070, 0x109}, - {0x90071, 0x10}, - {0x90072, 0x4}, - {0x90073, 0x18}, - {0x90074, 0x0}, - {0x90075, 0x4}, - {0x90076, 0x78}, - {0x90077, 0x549}, - {0x90078, 0x633}, - {0x90079, 0x159}, - {0x9007a, 0xd49}, - {0x9007b, 0x633}, - {0x9007c, 0x159}, - {0x9007d, 0x94a}, - {0x9007e, 0x633}, - {0x9007f, 0x159}, - {0x90080, 0x441}, - {0x90081, 0x633}, - {0x90082, 0x149}, - {0x90083, 0x42}, - {0x90084, 0x633}, - {0x90085, 0x149}, - {0x90086, 0x1}, - {0x90087, 0x633}, - {0x90088, 0x149}, - {0x90089, 0x0}, - {0x9008a, 0xe0}, - {0x9008b, 0x109}, - {0x9008c, 0xa}, - {0x9008d, 0x10}, - {0x9008e, 0x109}, - {0x9008f, 0x9}, - {0x90090, 0x3c0}, - {0x90091, 0x149}, - {0x90092, 0x9}, - {0x90093, 0x3c0}, - {0x90094, 0x159}, - {0x90095, 0x18}, - {0x90096, 0x10}, - {0x90097, 0x109}, - {0x90098, 0x0}, - {0x90099, 0x3c0}, - {0x9009a, 0x109}, - {0x9009b, 0x18}, - {0x9009c, 0x4}, - {0x9009d, 0x48}, - {0x9009e, 0x18}, - {0x9009f, 0x4}, - {0x900a0, 0x58}, - {0x900a1, 0xb}, - {0x900a2, 0x10}, - {0x900a3, 0x109}, - {0x900a4, 0x1}, - {0x900a5, 0x10}, - {0x900a6, 0x109}, - {0x900a7, 0x5}, - {0x900a8, 0x7c0}, - {0x900a9, 0x109}, - {0x40000, 0x811}, - {0x40020, 0x880}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x4008}, - {0x40021, 0x83}, - {0x40041, 0x4f}, - {0x40061, 0x0}, - {0x40002, 0x4040}, - {0x40022, 0x83}, - {0x40042, 0x51}, - {0x40062, 0x0}, - {0x40003, 0x811}, - {0x40023, 0x880}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x720}, - {0x40024, 0xf}, - {0x40044, 0x1740}, - {0x40064, 0x0}, - {0x40005, 0x16}, - {0x40025, 0x83}, - {0x40045, 0x4b}, - {0x40065, 0x0}, - {0x40006, 0x716}, - {0x40026, 0xf}, - {0x40046, 0x2001}, - {0x40066, 0x0}, - {0x40007, 0x716}, - {0x40027, 0xf}, - {0x40047, 0x2800}, - {0x40067, 0x0}, - {0x40008, 0x716}, - {0x40028, 0xf}, - {0x40048, 0xf00}, - {0x40068, 0x0}, - {0x40009, 0x720}, - {0x40029, 0xf}, - {0x40049, 0x1400}, - {0x40069, 0x0}, - {0x4000a, 0xe08}, - {0x4002a, 0xc15}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x625}, - {0x4002b, 0x15}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x4028}, - {0x4002c, 0x80}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0xe08}, - {0x4002d, 0xc1a}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x625}, - {0x4002e, 0x1a}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x4040}, - {0x4002f, 0x80}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x2604}, - {0x40030, 0x15}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x708}, - {0x40031, 0x5}, - {0x40051, 0x0}, - {0x40071, 0x2002}, - {0x40012, 0x8}, - {0x40032, 0x80}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x2604}, - {0x40033, 0x1a}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x708}, - {0x40034, 0xa}, - {0x40054, 0x0}, - {0x40074, 0x2002}, - {0x40015, 0x4040}, - {0x40035, 0x80}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x60a}, - {0x40036, 0x15}, - {0x40056, 0x1200}, - {0x40076, 0x0}, - {0x40017, 0x61a}, - {0x40037, 0x15}, - {0x40057, 0x1300}, - {0x40077, 0x0}, - {0x40018, 0x60a}, - {0x40038, 0x1a}, - {0x40058, 0x1200}, - {0x40078, 0x0}, - {0x40019, 0x642}, - {0x40039, 0x1a}, - {0x40059, 0x1300}, - {0x40079, 0x0}, - {0x4001a, 0x4808}, - {0x4003a, 0x880}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x790}, - {0x900ac, 0x11a}, - {0x900ad, 0x8}, - {0x900ae, 0x7aa}, - {0x900af, 0x2a}, - {0x900b0, 0x10}, - {0x900b1, 0x7b2}, - {0x900b2, 0x2a}, - {0x900b3, 0x0}, - {0x900b4, 0x7c8}, - {0x900b5, 0x109}, - {0x900b6, 0x10}, - {0x900b7, 0x10}, - {0x900b8, 0x109}, - {0x900b9, 0x10}, - {0x900ba, 0x2a8}, - {0x900bb, 0x129}, - {0x900bc, 0x8}, - {0x900bd, 0x370}, - {0x900be, 0x129}, - {0x900bf, 0xa}, - {0x900c0, 0x3c8}, - {0x900c1, 0x1a9}, - {0x900c2, 0xc}, - {0x900c3, 0x408}, - {0x900c4, 0x199}, - {0x900c5, 0x14}, - {0x900c6, 0x790}, - {0x900c7, 0x11a}, - {0x900c8, 0x8}, - {0x900c9, 0x4}, - {0x900ca, 0x18}, - {0x900cb, 0xe}, - {0x900cc, 0x408}, - {0x900cd, 0x199}, - {0x900ce, 0x8}, - {0x900cf, 0x8568}, - {0x900d0, 0x108}, - {0x900d1, 0x18}, - {0x900d2, 0x790}, - {0x900d3, 0x16a}, - {0x900d4, 0x8}, - {0x900d5, 0x1d8}, - {0x900d6, 0x169}, - {0x900d7, 0x10}, - {0x900d8, 0x8558}, - {0x900d9, 0x168}, - {0x900da, 0x1ff8}, - {0x900db, 0x85a8}, - {0x900dc, 0x1e8}, - {0x900dd, 0x50}, - {0x900de, 0x798}, - {0x900df, 0x16a}, - {0x900e0, 0x60}, - {0x900e1, 0x7a0}, - {0x900e2, 0x16a}, - {0x900e3, 0x8}, - {0x900e4, 0x8310}, - {0x900e5, 0x168}, - {0x900e6, 0x8}, - {0x900e7, 0xa310}, - {0x900e8, 0x168}, - {0x900e9, 0xa}, - {0x900ea, 0x408}, - {0x900eb, 0x169}, - {0x900ec, 0x6e}, - {0x900ed, 0x0}, - {0x900ee, 0x68}, - {0x900ef, 0x0}, - {0x900f0, 0x408}, - {0x900f1, 0x169}, - {0x900f2, 0x0}, - {0x900f3, 0x8310}, - {0x900f4, 0x168}, - {0x900f5, 0x0}, - {0x900f6, 0xa310}, - {0x900f7, 0x168}, - {0x900f8, 0x1ff8}, - {0x900f9, 0x85a8}, - {0x900fa, 0x1e8}, - {0x900fb, 0x68}, - {0x900fc, 0x798}, - {0x900fd, 0x16a}, - {0x900fe, 0x78}, - {0x900ff, 0x7a0}, - {0x90100, 0x16a}, - {0x90101, 0x68}, - {0x90102, 0x790}, - {0x90103, 0x16a}, - {0x90104, 0x8}, - {0x90105, 0x8b10}, - {0x90106, 0x168}, - {0x90107, 0x8}, - {0x90108, 0xab10}, - {0x90109, 0x168}, - {0x9010a, 0xa}, - {0x9010b, 0x408}, - {0x9010c, 0x169}, - {0x9010d, 0x58}, - {0x9010e, 0x0}, - {0x9010f, 0x68}, - {0x90110, 0x0}, - {0x90111, 0x408}, - {0x90112, 0x169}, - {0x90113, 0x0}, - {0x90114, 0x8b10}, - {0x90115, 0x168}, - {0x90116, 0x1}, - {0x90117, 0xab10}, - {0x90118, 0x168}, - {0x90119, 0x0}, - {0x9011a, 0x1d8}, - {0x9011b, 0x169}, - {0x9011c, 0x80}, - {0x9011d, 0x790}, - {0x9011e, 0x16a}, - {0x9011f, 0x18}, - {0x90120, 0x7aa}, - {0x90121, 0x6a}, - {0x90122, 0xa}, - {0x90123, 0x0}, - {0x90124, 0x1e9}, - {0x90125, 0x8}, - {0x90126, 0x8080}, - {0x90127, 0x108}, - {0x90128, 0xf}, - {0x90129, 0x408}, - {0x9012a, 0x169}, - {0x9012b, 0xc}, - {0x9012c, 0x0}, - {0x9012d, 0x68}, - {0x9012e, 0x9}, - {0x9012f, 0x0}, - {0x90130, 0x1a9}, - {0x90131, 0x0}, - {0x90132, 0x408}, - {0x90133, 0x169}, - {0x90134, 0x0}, - {0x90135, 0x8080}, - {0x90136, 0x108}, - {0x90137, 0x8}, - {0x90138, 0x7aa}, - {0x90139, 0x6a}, - {0x9013a, 0x0}, - {0x9013b, 0x8568}, - {0x9013c, 0x108}, - {0x9013d, 0xb7}, - {0x9013e, 0x790}, - {0x9013f, 0x16a}, - {0x90140, 0x1f}, - {0x90141, 0x0}, - {0x90142, 0x68}, - {0x90143, 0x8}, - {0x90144, 0x8558}, - {0x90145, 0x168}, - {0x90146, 0xf}, - {0x90147, 0x408}, - {0x90148, 0x169}, - {0x90149, 0xd}, - {0x9014a, 0x0}, - {0x9014b, 0x68}, - {0x9014c, 0x0}, - {0x9014d, 0x408}, - {0x9014e, 0x169}, - {0x9014f, 0x0}, - {0x90150, 0x8558}, - {0x90151, 0x168}, - {0x90152, 0x8}, - {0x90153, 0x3c8}, - {0x90154, 0x1a9}, - {0x90155, 0x3}, - {0x90156, 0x370}, - {0x90157, 0x129}, - {0x90158, 0x20}, - {0x90159, 0x2aa}, - {0x9015a, 0x9}, - {0x9015b, 0x8}, - {0x9015c, 0xe8}, - {0x9015d, 0x109}, - {0x9015e, 0x0}, - {0x9015f, 0x8140}, - {0x90160, 0x10c}, - {0x90161, 0x10}, - {0x90162, 0x8138}, - {0x90163, 0x104}, - {0x90164, 0x8}, - {0x90165, 0x448}, - {0x90166, 0x109}, - {0x90167, 0xf}, - {0x90168, 0x7c0}, - {0x90169, 0x109}, - {0x9016a, 0x0}, - {0x9016b, 0xe8}, - {0x9016c, 0x109}, - {0x9016d, 0x47}, - {0x9016e, 0x630}, - {0x9016f, 0x109}, - {0x90170, 0x8}, - {0x90171, 0x618}, - {0x90172, 0x109}, - {0x90173, 0x8}, - {0x90174, 0xe0}, - {0x90175, 0x109}, - {0x90176, 0x0}, - {0x90177, 0x7c8}, - {0x90178, 0x109}, - {0x90179, 0x8}, - {0x9017a, 0x8140}, - {0x9017b, 0x10c}, - {0x9017c, 0x0}, - {0x9017d, 0x478}, - {0x9017e, 0x109}, - {0x9017f, 0x0}, - {0x90180, 0x1}, - {0x90181, 0x8}, - {0x90182, 0x8}, - {0x90183, 0x4}, - {0x90184, 0x0}, - {0x90006, 0x8}, - {0x90007, 0x7c8}, - {0x90008, 0x109}, - {0x90009, 0x0}, - {0x9000a, 0x400}, - {0x9000b, 0x106}, - {0xd00e7, 0x400}, - {0x90017, 0x0}, - {0x9001f, 0x2b}, - {0x90026, 0x69}, - {0x400d0, 0x0}, - {0x400d1, 0x101}, - {0x400d2, 0x105}, - {0x400d3, 0x107}, - {0x400d4, 0x10f}, - {0x400d5, 0x202}, - {0x400d6, 0x20a}, - {0x400d7, 0x20b}, - {0x2003a, 0x2}, - {0x200be, 0x3}, - {0x2000b, 0x41a}, - {0x2000c, 0xe9}, - {0x2000d, 0x91c}, - {0x2000e, 0x2c}, - {0x12000b, 0x20d}, - {0x12000c, 0x74}, - {0x12000d, 0x48e}, - {0x12000e, 0x2c}, - {0x22000b, 0xb0}, - {0x22000c, 0x27}, - {0x22000d, 0x186}, - {0x22000e, 0x10}, - {0x9000c, 0x0}, - {0x9000d, 0x173}, - {0x9000e, 0x60}, - {0x9000f, 0x6110}, - {0x90010, 0x2152}, - {0x90011, 0xdfbd}, - {0x90012, 0x2060}, - {0x90013, 0x6152}, - {0x20010, 0x5a}, - {0x20011, 0x3}, - {0x120010, 0x5a}, - {0x120011, 0x3}, - {0x40080, 0xe0}, - {0x40081, 0x12}, - {0x40082, 0xe0}, - {0x40083, 0x12}, - {0x40084, 0xe0}, - {0x40085, 0x12}, - {0x140080, 0xe0}, - {0x140081, 0x12}, - {0x140082, 0xe0}, - {0x140083, 0x12}, - {0x140084, 0xe0}, - {0x140085, 0x12}, - {0x240080, 0xe0}, - {0x240081, 0x12}, - {0x240082, 0xe0}, - {0x240083, 0x12}, - {0x240084, 0xe0}, - {0x240085, 0x12}, - {0x400fd, 0xf}, - {0x400f1, 0xe}, - {0x10011, 0x1}, - {0x10012, 0x1}, - {0x10013, 0x180}, - {0x10018, 0x1}, - {0x10002, 0x6209}, - {0x100b2, 0x1}, - {0x101b4, 0x1}, - {0x102b4, 0x1}, - {0x103b4, 0x1}, - {0x104b4, 0x1}, - {0x105b4, 0x1}, - {0x106b4, 0x1}, - {0x107b4, 0x1}, - {0x108b4, 0x1}, - {0x11011, 0x1}, - {0x11012, 0x1}, - {0x11013, 0x180}, - {0x11018, 0x1}, - {0x11002, 0x6209}, - {0x110b2, 0x1}, - {0x111b4, 0x1}, - {0x112b4, 0x1}, - {0x113b4, 0x1}, - {0x114b4, 0x1}, - {0x115b4, 0x1}, - {0x116b4, 0x1}, - {0x117b4, 0x1}, - {0x118b4, 0x1}, - {0x20089, 0x1}, - {0x20088, 0x19}, - {0xc0080, 0x0}, - {0xd0000, 0x1}, -}; - -struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 3733mts 1D */ - .drate = 3733, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 1866mts 1D */ - .drate = 1866, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 625mts 1D */ - .drate = 625, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 3733mts 2D */ - .drate = 3733, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3733, 1866, 625, }, - .fsp_cfg = ddr_dram_fsp_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), -}; diff --git a/board/freescale/imx93_evk/lpddr4x_timing_1866mts.c b/board/freescale/imx93_evk/lpddr4x_timing_1866mts.c deleted file mode 100644 index f4e910b2536..00000000000 --- a/board/freescale/imx93_evk/lpddr4x_timing_1866mts.c +++ /dev/null @@ -1,1995 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright 2024 NXP - * - * Code generated with DDR Tool v3.4.0_8.3-4e2b550a. - * DDR PHY FW2022.01 - */ - -#include -#include - -/* Initialize DDRC registers */ -static struct dram_cfg_param ddr_ddrc_cfg[] = { - {0x4e300110, 0x44100001}, - {0x4e300000, 0x8000ff}, - {0x4e300008, 0x0}, - {0x4e300080, 0x80000512}, - {0x4e300084, 0x0}, - {0x4e300114, 0x1002}, - {0x4e300260, 0x80}, - {0x4e300f04, 0x80}, - {0x4e300800, 0x43b30002}, - {0x4e300804, 0x1f1f1f1f}, - {0x4e301000, 0x0}, - {0x4e301240, 0x0}, - {0x4e301244, 0x0}, - {0x4e301248, 0x0}, - {0x4e30124c, 0x0}, - {0x4e301250, 0x0}, - {0x4e301254, 0x0}, - {0x4e301258, 0x0}, - {0x4e30125c, 0x0}, -}; - -/* dram fsp cfg */ -static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { - { - { - {0x4e300100, 0x12552100}, - {0x4e300104, 0xF877000E}, - {0x4e300108, 0x1816B4AA}, - {0x4e30010C, 0x0051E1E6}, - {0x4e300124, 0x0E3A0000}, - {0x4e300160, 0x00009101}, - {0x4e30016C, 0x30900000}, - {0x4e300170, 0x8A0A0508}, - {0x4e300250, 0x00000014}, - {0x4e300254, 0x00AA00AA}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - {0x4e300300, 0x11281109}, - {0x4e300304, 0x00AA140A}, - {0x4e300308, 0x063C071E}, - }, - { - {0x01, 0xB4}, - {0x02, 0x1B}, - {0x03, 0x32}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x11}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x010A1000}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0x9492AA58}, - {0x4e30010C, 0x00310113}, - {0x4e300124, 0x071E0000}, - {0x4e300160, 0x00009100}, - {0x4e30016C, 0x30200000}, - {0x4e300170, 0x89090408}, - {0x4e300250, 0x0000000A}, - {0x4e300254, 0x00510051}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0x94}, - {0x02, 0x9}, - {0x03, 0x32}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x11}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x00061000}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0x6E62FA48}, - {0x4e30010C, 0x0031010D}, - {0x4e300124, 0x04C50000}, - {0x4e300160, 0x00009100}, - {0x4e30016C, 0x30000000}, - {0x4e300170, 0x89090408}, - {0x4e300250, 0x00000007}, - {0x4e300254, 0x00340034}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0x94}, - {0x02, 0x9}, - {0x03, 0x32}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x11}, - {0x16, 0x04}, - }, - 1, - }, -}; - -/* PHY Initialize Configuration */ -static struct dram_cfg_param ddr_ddrphy_cfg[] = { - {0x100a0, 0x4}, - {0x100a1, 0x5}, - {0x100a2, 0x6}, - {0x100a3, 0x7}, - {0x100a4, 0x0}, - {0x100a5, 0x1}, - {0x100a6, 0x2}, - {0x100a7, 0x3}, - {0x110a0, 0x3}, - {0x110a1, 0x2}, - {0x110a2, 0x0}, - {0x110a3, 0x1}, - {0x110a4, 0x7}, - {0x110a5, 0x6}, - {0x110a6, 0x4}, - {0x110a7, 0x5}, - {0x1005f, 0x5ff}, - {0x1015f, 0x5ff}, - {0x1105f, 0x5ff}, - {0x1115f, 0x5ff}, - {0x11005f, 0x5ff}, - {0x11015f, 0x5ff}, - {0x11105f, 0x5ff}, - {0x11115f, 0x5ff}, - {0x21005f, 0x5ff}, - {0x21015f, 0x5ff}, - {0x21105f, 0x5ff}, - {0x21115f, 0x5ff}, - {0x55, 0x1ff}, - {0x1055, 0x1ff}, - {0x2055, 0x1ff}, - {0x200c5, 0xb}, - {0x1200c5, 0x3}, - {0x2200c5, 0x7}, - {0x2002e, 0x2}, - {0x12002e, 0x1}, - {0x22002e, 0x2}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x1e3}, - {0x2003a, 0x2}, - {0x2007d, 0x212}, - {0x2007c, 0x61}, - {0x120024, 0x1e3}, - {0x2003a, 0x2}, - {0x12007d, 0x212}, - {0x12007c, 0x61}, - {0x220024, 0x1e3}, - {0x2003a, 0x2}, - {0x22007d, 0x212}, - {0x22007c, 0x61}, - {0x20056, 0x3}, - {0x120056, 0x3}, - {0x220056, 0x3}, - {0x1004d, 0x600}, - {0x1014d, 0x600}, - {0x1104d, 0x600}, - {0x1114d, 0x600}, - {0x11004d, 0x600}, - {0x11014d, 0x600}, - {0x11104d, 0x600}, - {0x11114d, 0x600}, - {0x21004d, 0x600}, - {0x21014d, 0x600}, - {0x21104d, 0x600}, - {0x21114d, 0x600}, - {0x10049, 0xe00}, - {0x10149, 0xe00}, - {0x11049, 0xe00}, - {0x11149, 0xe00}, - {0x110049, 0xe00}, - {0x110149, 0xe00}, - {0x111049, 0xe00}, - {0x111149, 0xe00}, - {0x210049, 0xe00}, - {0x210149, 0xe00}, - {0x211049, 0xe00}, - {0x211149, 0xe00}, - {0x43, 0x60}, - {0x1043, 0x60}, - {0x2043, 0x60}, - {0x20018, 0x1}, - {0x20075, 0x4}, - {0x20050, 0x0}, - {0x2009b, 0x2}, - {0x20008, 0x1d3}, - {0x120008, 0xe9}, - {0x220008, 0x9c}, - {0x20088, 0x9}, - {0x200b2, 0x10c}, - {0x10043, 0x5a1}, - {0x10143, 0x5a1}, - {0x11043, 0x5a1}, - {0x11143, 0x5a1}, - {0x1200b2, 0x10c}, - {0x110043, 0x5a1}, - {0x110143, 0x5a1}, - {0x111043, 0x5a1}, - {0x111143, 0x5a1}, - {0x2200b2, 0x10c}, - {0x210043, 0x5a1}, - {0x210143, 0x5a1}, - {0x211043, 0x5a1}, - {0x211143, 0x5a1}, - {0x200fa, 0x2}, - {0x1200fa, 0x2}, - {0x2200fa, 0x2}, - {0x20019, 0x1}, - {0x120019, 0x1}, - {0x220019, 0x1}, - {0x200f0, 0x600}, - {0x200f1, 0x0}, - {0x200f2, 0x4444}, - {0x200f3, 0x8888}, - {0x200f4, 0x5655}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0xf000}, - {0x1004a, 0x500}, - {0x1104a, 0x500}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0x20021, 0x0}, - {0x200c7, 0x21}, - {0x1200c7, 0x41}, - {0x200ca, 0x24}, - {0x1200ca, 0x24}, -}; - -/* PHY trained csr */ -static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - {0x1005f, 0x0}, - {0x1015f, 0x0}, - {0x1105f, 0x0}, - {0x1115f, 0x0}, - {0x11005f, 0x0}, - {0x11015f, 0x0}, - {0x11105f, 0x0}, - {0x11115f, 0x0}, - {0x21005f, 0x0}, - {0x21015f, 0x0}, - {0x21105f, 0x0}, - {0x21115f, 0x0}, - {0x55, 0x0}, - {0x1055, 0x0}, - {0x2055, 0x0}, - {0x200c5, 0x0}, - {0x1200c5, 0x0}, - {0x2200c5, 0x0}, - {0x2002e, 0x0}, - {0x12002e, 0x0}, - {0x22002e, 0x0}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x0}, - {0x2003a, 0x0}, - {0x2007d, 0x0}, - {0x2007c, 0x0}, - {0x120024, 0x0}, - {0x12007d, 0x0}, - {0x12007c, 0x0}, - {0x220024, 0x0}, - {0x22007d, 0x0}, - {0x22007c, 0x0}, - {0x20056, 0x0}, - {0x120056, 0x0}, - {0x220056, 0x0}, - {0x1004d, 0x0}, - {0x1014d, 0x0}, - {0x1104d, 0x0}, - {0x1114d, 0x0}, - {0x11004d, 0x0}, - {0x11014d, 0x0}, - {0x11104d, 0x0}, - {0x11114d, 0x0}, - {0x21004d, 0x0}, - {0x21014d, 0x0}, - {0x21104d, 0x0}, - {0x21114d, 0x0}, - {0x10049, 0x0}, - {0x10149, 0x0}, - {0x11049, 0x0}, - {0x11149, 0x0}, - {0x110049, 0x0}, - {0x110149, 0x0}, - {0x111049, 0x0}, - {0x111149, 0x0}, - {0x210049, 0x0}, - {0x210149, 0x0}, - {0x211049, 0x0}, - {0x211149, 0x0}, - {0x43, 0x0}, - {0x1043, 0x0}, - {0x2043, 0x0}, - {0x20018, 0x0}, - {0x20075, 0x0}, - {0x20050, 0x0}, - {0x2009b, 0x0}, - {0x20008, 0x0}, - {0x120008, 0x0}, - {0x220008, 0x0}, - {0x20088, 0x0}, - {0x200b2, 0x0}, - {0x10043, 0x0}, - {0x10143, 0x0}, - {0x11043, 0x0}, - {0x11143, 0x0}, - {0x1200b2, 0x0}, - {0x110043, 0x0}, - {0x110143, 0x0}, - {0x111043, 0x0}, - {0x111143, 0x0}, - {0x2200b2, 0x0}, - {0x210043, 0x0}, - {0x210143, 0x0}, - {0x211043, 0x0}, - {0x211143, 0x0}, - {0x200fa, 0x0}, - {0x1200fa, 0x0}, - {0x2200fa, 0x0}, - {0x20019, 0x0}, - {0x120019, 0x0}, - {0x220019, 0x0}, - {0x200f0, 0x0}, - {0x200f1, 0x0}, - {0x200f2, 0x0}, - {0x200f3, 0x0}, - {0x200f4, 0x0}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0x0}, - {0x1004a, 0x0}, - {0x1104a, 0x0}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0xd0000, 0x0}, - {0x90000, 0x0}, - {0x90001, 0x0}, - {0x90002, 0x0}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x0}, - {0x90029, 0x0}, - {0x9002a, 0x0}, - {0x9002b, 0x0}, - {0x9002c, 0x0}, - {0x9002d, 0x0}, - {0x9002e, 0x0}, - {0x9002f, 0x0}, - {0x90030, 0x0}, - {0x90031, 0x0}, - {0x90032, 0x0}, - {0x90033, 0x0}, - {0x90034, 0x0}, - {0x90035, 0x0}, - {0x90036, 0x0}, - {0x90037, 0x0}, - {0x90038, 0x0}, - {0x90039, 0x0}, - {0x9003a, 0x0}, - {0x9003b, 0x0}, - {0x9003c, 0x0}, - {0x9003d, 0x0}, - {0x9003e, 0x0}, - {0x9003f, 0x0}, - {0x90040, 0x0}, - {0x90041, 0x0}, - {0x90042, 0x0}, - {0x90043, 0x0}, - {0x90044, 0x0}, - {0x90045, 0x0}, - {0x90046, 0x0}, - {0x90047, 0x0}, - {0x90048, 0x0}, - {0x90049, 0x0}, - {0x9004a, 0x0}, - {0x9004b, 0x0}, - {0x9004c, 0x0}, - {0x9004d, 0x0}, - {0x9004e, 0x0}, - {0x9004f, 0x0}, - {0x90050, 0x0}, - {0x90051, 0x0}, - {0x90052, 0x0}, - {0x90053, 0x0}, - {0x90054, 0x0}, - {0x90055, 0x0}, - {0x90056, 0x0}, - {0x90057, 0x0}, - {0x90058, 0x0}, - {0x90059, 0x0}, - {0x9005a, 0x0}, - {0x9005b, 0x0}, - {0x9005c, 0x0}, - {0x9005d, 0x0}, - {0x9005e, 0x0}, - {0x9005f, 0x0}, - {0x90060, 0x0}, - {0x90061, 0x0}, - {0x90062, 0x0}, - {0x90063, 0x0}, - {0x90064, 0x0}, - {0x90065, 0x0}, - {0x90066, 0x0}, - {0x90067, 0x0}, - {0x90068, 0x0}, - {0x90069, 0x0}, - {0x9006a, 0x0}, - {0x9006b, 0x0}, - {0x9006c, 0x0}, - {0x9006d, 0x0}, - {0x9006e, 0x0}, - {0x9006f, 0x0}, - {0x90070, 0x0}, - {0x90071, 0x0}, - {0x90072, 0x0}, - {0x90073, 0x0}, - {0x90074, 0x0}, - {0x90075, 0x0}, - {0x90076, 0x0}, - {0x90077, 0x0}, - {0x90078, 0x0}, - {0x90079, 0x0}, - {0x9007a, 0x0}, - {0x9007b, 0x0}, - {0x9007c, 0x0}, - {0x9007d, 0x0}, - {0x9007e, 0x0}, - {0x9007f, 0x0}, - {0x90080, 0x0}, - {0x90081, 0x0}, - {0x90082, 0x0}, - {0x90083, 0x0}, - {0x90084, 0x0}, - {0x90085, 0x0}, - {0x90086, 0x0}, - {0x90087, 0x0}, - {0x90088, 0x0}, - {0x90089, 0x0}, - {0x9008a, 0x0}, - {0x9008b, 0x0}, - {0x9008c, 0x0}, - {0x9008d, 0x0}, - {0x9008e, 0x0}, - {0x9008f, 0x0}, - {0x90090, 0x0}, - {0x90091, 0x0}, - {0x90092, 0x0}, - {0x90093, 0x0}, - {0x90094, 0x0}, - {0x90095, 0x0}, - {0x90096, 0x0}, - {0x90097, 0x0}, - {0x90098, 0x0}, - {0x90099, 0x0}, - {0x9009a, 0x0}, - {0x9009b, 0x0}, - {0x9009c, 0x0}, - {0x9009d, 0x0}, - {0x9009e, 0x0}, - {0x9009f, 0x0}, - {0x900a0, 0x0}, - {0x900a1, 0x0}, - {0x900a2, 0x0}, - {0x900a3, 0x0}, - {0x900a4, 0x0}, - {0x900a5, 0x0}, - {0x900a6, 0x0}, - {0x900a7, 0x0}, - {0x900a8, 0x0}, - {0x900a9, 0x0}, - {0x40000, 0x0}, - {0x40020, 0x0}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x0}, - {0x40021, 0x0}, - {0x40041, 0x0}, - {0x40061, 0x0}, - {0x40002, 0x0}, - {0x40022, 0x0}, - {0x40042, 0x0}, - {0x40062, 0x0}, - {0x40003, 0x0}, - {0x40023, 0x0}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x0}, - {0x40024, 0x0}, - {0x40044, 0x0}, - {0x40064, 0x0}, - {0x40005, 0x0}, - {0x40025, 0x0}, - {0x40045, 0x0}, - {0x40065, 0x0}, - {0x40006, 0x0}, - {0x40026, 0x0}, - {0x40046, 0x0}, - {0x40066, 0x0}, - {0x40007, 0x0}, - {0x40027, 0x0}, - {0x40047, 0x0}, - {0x40067, 0x0}, - {0x40008, 0x0}, - {0x40028, 0x0}, - {0x40048, 0x0}, - {0x40068, 0x0}, - {0x40009, 0x0}, - {0x40029, 0x0}, - {0x40049, 0x0}, - {0x40069, 0x0}, - {0x4000a, 0x0}, - {0x4002a, 0x0}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x0}, - {0x4002b, 0x0}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x0}, - {0x4002c, 0x0}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0x0}, - {0x4002d, 0x0}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x0}, - {0x4002e, 0x0}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x0}, - {0x4002f, 0x0}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x0}, - {0x40030, 0x0}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x0}, - {0x40031, 0x0}, - {0x40051, 0x0}, - {0x40071, 0x0}, - {0x40012, 0x0}, - {0x40032, 0x0}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x0}, - {0x40033, 0x0}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x0}, - {0x40034, 0x0}, - {0x40054, 0x0}, - {0x40074, 0x0}, - {0x40015, 0x0}, - {0x40035, 0x0}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x0}, - {0x40036, 0x0}, - {0x40056, 0x0}, - {0x40076, 0x0}, - {0x40017, 0x0}, - {0x40037, 0x0}, - {0x40057, 0x0}, - {0x40077, 0x0}, - {0x40018, 0x0}, - {0x40038, 0x0}, - {0x40058, 0x0}, - {0x40078, 0x0}, - {0x40019, 0x0}, - {0x40039, 0x0}, - {0x40059, 0x0}, - {0x40079, 0x0}, - {0x4001a, 0x0}, - {0x4003a, 0x0}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x0}, - {0x900ac, 0x0}, - {0x900ad, 0x0}, - {0x900ae, 0x0}, - {0x900af, 0x0}, - {0x900b0, 0x0}, - {0x900b1, 0x0}, - {0x900b2, 0x0}, - {0x900b3, 0x0}, - {0x900b4, 0x0}, - {0x900b5, 0x0}, - {0x900b6, 0x0}, - {0x900b7, 0x0}, - {0x900b8, 0x0}, - {0x900b9, 0x0}, - {0x900ba, 0x0}, - {0x900bb, 0x0}, - {0x900bc, 0x0}, - {0x900bd, 0x0}, - {0x900be, 0x0}, - {0x900bf, 0x0}, - {0x900c0, 0x0}, - {0x900c1, 0x0}, - {0x900c2, 0x0}, - {0x900c3, 0x0}, - {0x900c4, 0x0}, - {0x900c5, 0x0}, - {0x900c6, 0x0}, - {0x900c7, 0x0}, - {0x900c8, 0x0}, - {0x900c9, 0x0}, - {0x900ca, 0x0}, - {0x900cb, 0x0}, - {0x900cc, 0x0}, - {0x900cd, 0x0}, - {0x900ce, 0x0}, - {0x900cf, 0x0}, - {0x900d0, 0x0}, - {0x900d1, 0x0}, - {0x900d2, 0x0}, - {0x900d3, 0x0}, - {0x900d4, 0x0}, - {0x900d5, 0x0}, - {0x900d6, 0x0}, - {0x900d7, 0x0}, - {0x900d8, 0x0}, - {0x900d9, 0x0}, - {0x900da, 0x0}, - {0x900db, 0x0}, - {0x900dc, 0x0}, - {0x900dd, 0x0}, - {0x900de, 0x0}, - {0x900df, 0x0}, - {0x900e0, 0x0}, - {0x900e1, 0x0}, - {0x900e2, 0x0}, - {0x900e3, 0x0}, - {0x900e4, 0x0}, - {0x900e5, 0x0}, - {0x900e6, 0x0}, - {0x900e7, 0x0}, - {0x900e8, 0x0}, - {0x900e9, 0x0}, - {0x900ea, 0x0}, - {0x900eb, 0x0}, - {0x900ec, 0x0}, - {0x900ed, 0x0}, - {0x900ee, 0x0}, - {0x900ef, 0x0}, - {0x900f0, 0x0}, - {0x900f1, 0x0}, - {0x900f2, 0x0}, - {0x900f3, 0x0}, - {0x900f4, 0x0}, - {0x900f5, 0x0}, - {0x900f6, 0x0}, - {0x900f7, 0x0}, - {0x900f8, 0x0}, - {0x900f9, 0x0}, - {0x900fa, 0x0}, - {0x900fb, 0x0}, - {0x900fc, 0x0}, - {0x900fd, 0x0}, - {0x900fe, 0x0}, - {0x900ff, 0x0}, - {0x90100, 0x0}, - {0x90101, 0x0}, - {0x90102, 0x0}, - {0x90103, 0x0}, - {0x90104, 0x0}, - {0x90105, 0x0}, - {0x90106, 0x0}, - {0x90107, 0x0}, - {0x90108, 0x0}, - {0x90109, 0x0}, - {0x9010a, 0x0}, - {0x9010b, 0x0}, - {0x9010c, 0x0}, - {0x9010d, 0x0}, - {0x9010e, 0x0}, - {0x9010f, 0x0}, - {0x90110, 0x0}, - {0x90111, 0x0}, - {0x90112, 0x0}, - {0x90113, 0x0}, - {0x90114, 0x0}, - {0x90115, 0x0}, - {0x90116, 0x0}, - {0x90117, 0x0}, - {0x90118, 0x0}, - {0x90119, 0x0}, - {0x9011a, 0x0}, - {0x9011b, 0x0}, - {0x9011c, 0x0}, - {0x9011d, 0x0}, - {0x9011e, 0x0}, - {0x9011f, 0x0}, - {0x90120, 0x0}, - {0x90121, 0x0}, - {0x90122, 0x0}, - {0x90123, 0x0}, - {0x90124, 0x0}, - {0x90125, 0x0}, - {0x90126, 0x0}, - {0x90127, 0x0}, - {0x90128, 0x0}, - {0x90129, 0x0}, - {0x9012a, 0x0}, - {0x9012b, 0x0}, - {0x9012c, 0x0}, - {0x9012d, 0x0}, - {0x9012e, 0x0}, - {0x9012f, 0x0}, - {0x90130, 0x0}, - {0x90131, 0x0}, - {0x90132, 0x0}, - {0x90133, 0x0}, - {0x90134, 0x0}, - {0x90135, 0x0}, - {0x90136, 0x0}, - {0x90137, 0x0}, - {0x90138, 0x0}, - {0x90139, 0x0}, - {0x9013a, 0x0}, - {0x9013b, 0x0}, - {0x9013c, 0x0}, - {0x9013d, 0x0}, - {0x9013e, 0x0}, - {0x9013f, 0x0}, - {0x90140, 0x0}, - {0x90141, 0x0}, - {0x90142, 0x0}, - {0x90143, 0x0}, - {0x90144, 0x0}, - {0x90145, 0x0}, - {0x90146, 0x0}, - {0x90147, 0x0}, - {0x90148, 0x0}, - {0x90149, 0x0}, - {0x9014a, 0x0}, - {0x9014b, 0x0}, - {0x9014c, 0x0}, - {0x9014d, 0x0}, - {0x9014e, 0x0}, - {0x9014f, 0x0}, - {0x90150, 0x0}, - {0x90151, 0x0}, - {0x90152, 0x0}, - {0x90153, 0x0}, - {0x90154, 0x0}, - {0x90155, 0x0}, - {0x90156, 0x0}, - {0x90157, 0x0}, - {0x90158, 0x0}, - {0x90159, 0x0}, - {0x9015a, 0x0}, - {0x9015b, 0x0}, - {0x9015c, 0x0}, - {0x9015d, 0x0}, - {0x9015e, 0x0}, - {0x9015f, 0x0}, - {0x90160, 0x0}, - {0x90161, 0x0}, - {0x90162, 0x0}, - {0x90163, 0x0}, - {0x90164, 0x0}, - {0x90165, 0x0}, - {0x90166, 0x0}, - {0x90167, 0x0}, - {0x90168, 0x0}, - {0x90169, 0x0}, - {0x9016a, 0x0}, - {0x9016b, 0x0}, - {0x9016c, 0x0}, - {0x9016d, 0x0}, - {0x9016e, 0x0}, - {0x9016f, 0x0}, - {0x90170, 0x0}, - {0x90171, 0x0}, - {0x90172, 0x0}, - {0x90173, 0x0}, - {0x90174, 0x0}, - {0x90175, 0x0}, - {0x90176, 0x0}, - {0x90177, 0x0}, - {0x90178, 0x0}, - {0x90179, 0x0}, - {0x9017a, 0x0}, - {0x9017b, 0x0}, - {0x9017c, 0x0}, - {0x9017d, 0x0}, - {0x9017e, 0x0}, - {0x9017f, 0x0}, - {0x90180, 0x0}, - {0x90181, 0x0}, - {0x90182, 0x0}, - {0x90183, 0x0}, - {0x90184, 0x0}, - {0x90006, 0x0}, - {0x90007, 0x0}, - {0x90008, 0x0}, - {0x90009, 0x0}, - {0x9000a, 0x0}, - {0x9000b, 0x0}, - {0xd00e7, 0x0}, - {0x90017, 0x0}, - {0x9001f, 0x0}, - {0x90026, 0x0}, - {0x400d0, 0x0}, - {0x400d1, 0x0}, - {0x400d2, 0x0}, - {0x400d3, 0x0}, - {0x400d4, 0x0}, - {0x400d5, 0x0}, - {0x400d6, 0x0}, - {0x400d7, 0x0}, - {0x200be, 0x0}, - {0x2000b, 0x0}, - {0x2000c, 0x0}, - {0x2000d, 0x0}, - {0x2000e, 0x0}, - {0x12000b, 0x0}, - {0x12000c, 0x0}, - {0x12000d, 0x0}, - {0x12000e, 0x0}, - {0x22000b, 0x0}, - {0x22000c, 0x0}, - {0x22000d, 0x0}, - {0x22000e, 0x0}, - {0x9000c, 0x0}, - {0x9000d, 0x0}, - {0x9000e, 0x0}, - {0x9000f, 0x0}, - {0x90010, 0x0}, - {0x90011, 0x0}, - {0x90012, 0x0}, - {0x90013, 0x0}, - {0x20010, 0x0}, - {0x20011, 0x0}, - {0x120010, 0x0}, - {0x120011, 0x0}, - {0x40080, 0x0}, - {0x40081, 0x0}, - {0x40082, 0x0}, - {0x40083, 0x0}, - {0x40084, 0x0}, - {0x40085, 0x0}, - {0x140080, 0x0}, - {0x140081, 0x0}, - {0x140082, 0x0}, - {0x140083, 0x0}, - {0x140084, 0x0}, - {0x140085, 0x0}, - {0x240080, 0x0}, - {0x240081, 0x0}, - {0x240082, 0x0}, - {0x240083, 0x0}, - {0x240084, 0x0}, - {0x240085, 0x0}, - {0x400fd, 0x0}, - {0x400f1, 0x0}, - {0x10011, 0x0}, - {0x10012, 0x0}, - {0x10013, 0x0}, - {0x10018, 0x0}, - {0x10002, 0x0}, - {0x100b2, 0x0}, - {0x101b4, 0x0}, - {0x102b4, 0x0}, - {0x103b4, 0x0}, - {0x104b4, 0x0}, - {0x105b4, 0x0}, - {0x106b4, 0x0}, - {0x107b4, 0x0}, - {0x108b4, 0x0}, - {0x11011, 0x0}, - {0x11012, 0x0}, - {0x11013, 0x0}, - {0x11018, 0x0}, - {0x11002, 0x0}, - {0x110b2, 0x0}, - {0x111b4, 0x0}, - {0x112b4, 0x0}, - {0x113b4, 0x0}, - {0x114b4, 0x0}, - {0x115b4, 0x0}, - {0x116b4, 0x0}, - {0x117b4, 0x0}, - {0x118b4, 0x0}, - {0x20089, 0x0}, - {0xc0080, 0x0}, - {0x200cb, 0x0}, - {0x10068, 0x0}, - {0x10069, 0x0}, - {0x10168, 0x0}, - {0x10169, 0x0}, - {0x10268, 0x0}, - {0x10269, 0x0}, - {0x10368, 0x0}, - {0x10369, 0x0}, - {0x10468, 0x0}, - {0x10469, 0x0}, - {0x10568, 0x0}, - {0x10569, 0x0}, - {0x10668, 0x0}, - {0x10669, 0x0}, - {0x10768, 0x0}, - {0x10769, 0x0}, - {0x10868, 0x0}, - {0x10869, 0x0}, - {0x100aa, 0x0}, - {0x10062, 0x0}, - {0x10001, 0x0}, - {0x100a0, 0x0}, - {0x100a1, 0x0}, - {0x100a2, 0x0}, - {0x100a3, 0x0}, - {0x100a4, 0x0}, - {0x100a5, 0x0}, - {0x100a6, 0x0}, - {0x100a7, 0x0}, - {0x11068, 0x0}, - {0x11069, 0x0}, - {0x11168, 0x0}, - {0x11169, 0x0}, - {0x11268, 0x0}, - {0x11269, 0x0}, - {0x11368, 0x0}, - {0x11369, 0x0}, - {0x11468, 0x0}, - {0x11469, 0x0}, - {0x11568, 0x0}, - {0x11569, 0x0}, - {0x11668, 0x0}, - {0x11669, 0x0}, - {0x11768, 0x0}, - {0x11769, 0x0}, - {0x11868, 0x0}, - {0x11869, 0x0}, - {0x110aa, 0x0}, - {0x11062, 0x0}, - {0x11001, 0x0}, - {0x110a0, 0x0}, - {0x110a1, 0x0}, - {0x110a2, 0x0}, - {0x110a3, 0x0}, - {0x110a4, 0x0}, - {0x110a5, 0x0}, - {0x110a6, 0x0}, - {0x110a7, 0x0}, - {0x80, 0x0}, - {0x1080, 0x0}, - {0x2080, 0x0}, - {0x10020, 0x0}, - {0x10080, 0x0}, - {0x10081, 0x0}, - {0x100d0, 0x0}, - {0x100d1, 0x0}, - {0x1008c, 0x0}, - {0x1008d, 0x0}, - {0x10180, 0x0}, - {0x10181, 0x0}, - {0x101d0, 0x0}, - {0x101d1, 0x0}, - {0x1018c, 0x0}, - {0x1018d, 0x0}, - {0x100c0, 0x0}, - {0x100c1, 0x0}, - {0x101c0, 0x0}, - {0x101c1, 0x0}, - {0x102c0, 0x0}, - {0x102c1, 0x0}, - {0x103c0, 0x0}, - {0x103c1, 0x0}, - {0x104c0, 0x0}, - {0x104c1, 0x0}, - {0x105c0, 0x0}, - {0x105c1, 0x0}, - {0x106c0, 0x0}, - {0x106c1, 0x0}, - {0x107c0, 0x0}, - {0x107c1, 0x0}, - {0x108c0, 0x0}, - {0x108c1, 0x0}, - {0x100ae, 0x0}, - {0x100af, 0x0}, - {0x11020, 0x0}, - {0x11080, 0x0}, - {0x11081, 0x0}, - {0x110d0, 0x0}, - {0x110d1, 0x0}, - {0x1108c, 0x0}, - {0x1108d, 0x0}, - {0x11180, 0x0}, - {0x11181, 0x0}, - {0x111d0, 0x0}, - {0x111d1, 0x0}, - {0x1118c, 0x0}, - {0x1118d, 0x0}, - {0x110c0, 0x0}, - {0x110c1, 0x0}, - {0x111c0, 0x0}, - {0x111c1, 0x0}, - {0x112c0, 0x0}, - {0x112c1, 0x0}, - {0x113c0, 0x0}, - {0x113c1, 0x0}, - {0x114c0, 0x0}, - {0x114c1, 0x0}, - {0x115c0, 0x0}, - {0x115c1, 0x0}, - {0x116c0, 0x0}, - {0x116c1, 0x0}, - {0x117c0, 0x0}, - {0x117c1, 0x0}, - {0x118c0, 0x0}, - {0x118c1, 0x0}, - {0x110ae, 0x0}, - {0x110af, 0x0}, - {0x90201, 0x0}, - {0x90202, 0x0}, - {0x90203, 0x0}, - {0x90205, 0x0}, - {0x90206, 0x0}, - {0x90207, 0x0}, - {0x90208, 0x0}, - {0x20020, 0x0}, - {0x100080, 0x0}, - {0x101080, 0x0}, - {0x102080, 0x0}, - {0x110020, 0x0}, - {0x110080, 0x0}, - {0x110081, 0x0}, - {0x1100d0, 0x0}, - {0x1100d1, 0x0}, - {0x11008c, 0x0}, - {0x11008d, 0x0}, - {0x110180, 0x0}, - {0x110181, 0x0}, - {0x1101d0, 0x0}, - {0x1101d1, 0x0}, - {0x11018c, 0x0}, - {0x11018d, 0x0}, - {0x1100c0, 0x0}, - {0x1100c1, 0x0}, - {0x1101c0, 0x0}, - {0x1101c1, 0x0}, - {0x1102c0, 0x0}, - {0x1102c1, 0x0}, - {0x1103c0, 0x0}, - {0x1103c1, 0x0}, - {0x1104c0, 0x0}, - {0x1104c1, 0x0}, - {0x1105c0, 0x0}, - {0x1105c1, 0x0}, - {0x1106c0, 0x0}, - {0x1106c1, 0x0}, - {0x1107c0, 0x0}, - {0x1107c1, 0x0}, - {0x1108c0, 0x0}, - {0x1108c1, 0x0}, - {0x1100ae, 0x0}, - {0x1100af, 0x0}, - {0x111020, 0x0}, - {0x111080, 0x0}, - {0x111081, 0x0}, - {0x1110d0, 0x0}, - {0x1110d1, 0x0}, - {0x11108c, 0x0}, - {0x11108d, 0x0}, - {0x111180, 0x0}, - {0x111181, 0x0}, - {0x1111d0, 0x0}, - {0x1111d1, 0x0}, - {0x11118c, 0x0}, - {0x11118d, 0x0}, - {0x1110c0, 0x0}, - {0x1110c1, 0x0}, - {0x1111c0, 0x0}, - {0x1111c1, 0x0}, - {0x1112c0, 0x0}, - {0x1112c1, 0x0}, - {0x1113c0, 0x0}, - {0x1113c1, 0x0}, - {0x1114c0, 0x0}, - {0x1114c1, 0x0}, - {0x1115c0, 0x0}, - {0x1115c1, 0x0}, - {0x1116c0, 0x0}, - {0x1116c1, 0x0}, - {0x1117c0, 0x0}, - {0x1117c1, 0x0}, - {0x1118c0, 0x0}, - {0x1118c1, 0x0}, - {0x1110ae, 0x0}, - {0x1110af, 0x0}, - {0x190201, 0x0}, - {0x190202, 0x0}, - {0x190203, 0x0}, - {0x190205, 0x0}, - {0x190206, 0x0}, - {0x190207, 0x0}, - {0x190208, 0x0}, - {0x120020, 0x0}, - {0x200080, 0x0}, - {0x201080, 0x0}, - {0x202080, 0x0}, - {0x210020, 0x0}, - {0x210080, 0x0}, - {0x210081, 0x0}, - {0x2100d0, 0x0}, - {0x2100d1, 0x0}, - {0x21008c, 0x0}, - {0x21008d, 0x0}, - {0x210180, 0x0}, - {0x210181, 0x0}, - {0x2101d0, 0x0}, - {0x2101d1, 0x0}, - {0x21018c, 0x0}, - {0x21018d, 0x0}, - {0x2100c0, 0x0}, - {0x2100c1, 0x0}, - {0x2101c0, 0x0}, - {0x2101c1, 0x0}, - {0x2102c0, 0x0}, - {0x2102c1, 0x0}, - {0x2103c0, 0x0}, - {0x2103c1, 0x0}, - {0x2104c0, 0x0}, - {0x2104c1, 0x0}, - {0x2105c0, 0x0}, - {0x2105c1, 0x0}, - {0x2106c0, 0x0}, - {0x2106c1, 0x0}, - {0x2107c0, 0x0}, - {0x2107c1, 0x0}, - {0x2108c0, 0x0}, - {0x2108c1, 0x0}, - {0x2100ae, 0x0}, - {0x2100af, 0x0}, - {0x211020, 0x0}, - {0x211080, 0x0}, - {0x211081, 0x0}, - {0x2110d0, 0x0}, - {0x2110d1, 0x0}, - {0x21108c, 0x0}, - {0x21108d, 0x0}, - {0x211180, 0x0}, - {0x211181, 0x0}, - {0x2111d0, 0x0}, - {0x2111d1, 0x0}, - {0x21118c, 0x0}, - {0x21118d, 0x0}, - {0x2110c0, 0x0}, - {0x2110c1, 0x0}, - {0x2111c0, 0x0}, - {0x2111c1, 0x0}, - {0x2112c0, 0x0}, - {0x2112c1, 0x0}, - {0x2113c0, 0x0}, - {0x2113c1, 0x0}, - {0x2114c0, 0x0}, - {0x2114c1, 0x0}, - {0x2115c0, 0x0}, - {0x2115c1, 0x0}, - {0x2116c0, 0x0}, - {0x2116c1, 0x0}, - {0x2117c0, 0x0}, - {0x2117c1, 0x0}, - {0x2118c0, 0x0}, - {0x2118c1, 0x0}, - {0x2110ae, 0x0}, - {0x2110af, 0x0}, - {0x290201, 0x0}, - {0x290202, 0x0}, - {0x290203, 0x0}, - {0x290205, 0x0}, - {0x290206, 0x0}, - {0x290207, 0x0}, - {0x290208, 0x0}, - {0x220020, 0x0}, - {0x20077, 0x0}, - {0x20072, 0x0}, - {0x20073, 0x0}, - {0x400c0, 0x0}, - {0x10040, 0x0}, - {0x10140, 0x0}, - {0x10240, 0x0}, - {0x10340, 0x0}, - {0x10440, 0x0}, - {0x10540, 0x0}, - {0x10640, 0x0}, - {0x10740, 0x0}, - {0x10840, 0x0}, - {0x11040, 0x0}, - {0x11140, 0x0}, - {0x11240, 0x0}, - {0x11340, 0x0}, - {0x11440, 0x0}, - {0x11540, 0x0}, - {0x11640, 0x0}, - {0x11740, 0x0}, - {0x11840, 0x0}, -}; - -/* P0 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0x74a}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x131f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x1bb4}, - {0x5401a, 0x32}, - {0x5401b, 0x1146}, - {0x5401c, 0x1108}, - {0x5401e, 0x4}, - {0x5401f, 0x1bb4}, - {0x54020, 0x32}, - {0x54021, 0x1146}, - {0x54022, 0x1108}, - {0x54024, 0x4}, - {0x54032, 0xb400}, - {0x54033, 0x321b}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x11}, - {0x54037, 0x400}, - {0x54038, 0xb400}, - {0x54039, 0x321b}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x11}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P1 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp1_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x1}, - {0x54003, 0x3a4}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x994}, - {0x5401a, 0x32}, - {0x5401b, 0x1146}, - {0x5401c, 0x1108}, - {0x5401e, 0x4}, - {0x5401f, 0x994}, - {0x54020, 0x32}, - {0x54021, 0x1146}, - {0x54022, 0x1108}, - {0x54024, 0x4}, - {0x54032, 0x9400}, - {0x54033, 0x3209}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x11}, - {0x54037, 0x400}, - {0x54038, 0x9400}, - {0x54039, 0x3209}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x11}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P2 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp2_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x102}, - {0x54003, 0x270}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x994}, - {0x5401a, 0x32}, - {0x5401b, 0x1146}, - {0x5401c, 0x1100}, - {0x5401e, 0x4}, - {0x5401f, 0x994}, - {0x54020, 0x32}, - {0x54021, 0x1146}, - {0x54022, 0x1100}, - {0x54024, 0x4}, - {0x54032, 0x9400}, - {0x54033, 0x3209}, - {0x54034, 0x4600}, - {0x54035, 0x11}, - {0x54036, 0x11}, - {0x54037, 0x400}, - {0x54038, 0x9400}, - {0x54039, 0x3209}, - {0x5403a, 0x4600}, - {0x5403b, 0x11}, - {0x5403c, 0x11}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P0 2D message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0x74a}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x61}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54010, 0x2080}, - {0x54012, 0x110}, - {0x54019, 0x1bb4}, - {0x5401a, 0x32}, - {0x5401b, 0x1146}, - {0x5401c, 0x1108}, - {0x5401e, 0x4}, - {0x5401f, 0x1bb4}, - {0x54020, 0x32}, - {0x54021, 0x1146}, - {0x54022, 0x1108}, - {0x54024, 0x4}, - {0x54032, 0xb400}, - {0x54033, 0x321b}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x11}, - {0x54037, 0x400}, - {0x54038, 0xb400}, - {0x54039, 0x321b}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x11}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* DRAM PHY init engine image */ -static struct dram_cfg_param ddr_phy_pie[] = { - {0xd0000, 0x0}, - {0x90000, 0x10}, - {0x90001, 0x400}, - {0x90002, 0x10e}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x8}, - {0x90029, 0xb}, - {0x9002a, 0x480}, - {0x9002b, 0x109}, - {0x9002c, 0x8}, - {0x9002d, 0x448}, - {0x9002e, 0x139}, - {0x9002f, 0x8}, - {0x90030, 0x478}, - {0x90031, 0x109}, - {0x90032, 0x0}, - {0x90033, 0xe8}, - {0x90034, 0x109}, - {0x90035, 0x2}, - {0x90036, 0x10}, - {0x90037, 0x139}, - {0x90038, 0xb}, - {0x90039, 0x7c0}, - {0x9003a, 0x139}, - {0x9003b, 0x44}, - {0x9003c, 0x633}, - {0x9003d, 0x159}, - {0x9003e, 0x14f}, - {0x9003f, 0x630}, - {0x90040, 0x159}, - {0x90041, 0x47}, - {0x90042, 0x633}, - {0x90043, 0x149}, - {0x90044, 0x4f}, - {0x90045, 0x633}, - {0x90046, 0x179}, - {0x90047, 0x8}, - {0x90048, 0xe0}, - {0x90049, 0x109}, - {0x9004a, 0x0}, - {0x9004b, 0x7c8}, - {0x9004c, 0x109}, - {0x9004d, 0x0}, - {0x9004e, 0x1}, - {0x9004f, 0x8}, - {0x90050, 0x30}, - {0x90051, 0x65a}, - {0x90052, 0x9}, - {0x90053, 0x0}, - {0x90054, 0x45a}, - {0x90055, 0x9}, - {0x90056, 0x0}, - {0x90057, 0x448}, - {0x90058, 0x109}, - {0x90059, 0x40}, - {0x9005a, 0x633}, - {0x9005b, 0x179}, - {0x9005c, 0x1}, - {0x9005d, 0x618}, - {0x9005e, 0x109}, - {0x9005f, 0x40c0}, - {0x90060, 0x633}, - {0x90061, 0x149}, - {0x90062, 0x8}, - {0x90063, 0x4}, - {0x90064, 0x48}, - {0x90065, 0x4040}, - {0x90066, 0x633}, - {0x90067, 0x149}, - {0x90068, 0x0}, - {0x90069, 0x4}, - {0x9006a, 0x48}, - {0x9006b, 0x40}, - {0x9006c, 0x633}, - {0x9006d, 0x149}, - {0x9006e, 0x0}, - {0x9006f, 0x658}, - {0x90070, 0x109}, - {0x90071, 0x10}, - {0x90072, 0x4}, - {0x90073, 0x18}, - {0x90074, 0x0}, - {0x90075, 0x4}, - {0x90076, 0x78}, - {0x90077, 0x549}, - {0x90078, 0x633}, - {0x90079, 0x159}, - {0x9007a, 0xd49}, - {0x9007b, 0x633}, - {0x9007c, 0x159}, - {0x9007d, 0x94a}, - {0x9007e, 0x633}, - {0x9007f, 0x159}, - {0x90080, 0x441}, - {0x90081, 0x633}, - {0x90082, 0x149}, - {0x90083, 0x42}, - {0x90084, 0x633}, - {0x90085, 0x149}, - {0x90086, 0x1}, - {0x90087, 0x633}, - {0x90088, 0x149}, - {0x90089, 0x0}, - {0x9008a, 0xe0}, - {0x9008b, 0x109}, - {0x9008c, 0xa}, - {0x9008d, 0x10}, - {0x9008e, 0x109}, - {0x9008f, 0x9}, - {0x90090, 0x3c0}, - {0x90091, 0x149}, - {0x90092, 0x9}, - {0x90093, 0x3c0}, - {0x90094, 0x159}, - {0x90095, 0x18}, - {0x90096, 0x10}, - {0x90097, 0x109}, - {0x90098, 0x0}, - {0x90099, 0x3c0}, - {0x9009a, 0x109}, - {0x9009b, 0x18}, - {0x9009c, 0x4}, - {0x9009d, 0x48}, - {0x9009e, 0x18}, - {0x9009f, 0x4}, - {0x900a0, 0x58}, - {0x900a1, 0xb}, - {0x900a2, 0x10}, - {0x900a3, 0x109}, - {0x900a4, 0x1}, - {0x900a5, 0x10}, - {0x900a6, 0x109}, - {0x900a7, 0x5}, - {0x900a8, 0x7c0}, - {0x900a9, 0x109}, - {0x40000, 0x811}, - {0x40020, 0x880}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x4008}, - {0x40021, 0x83}, - {0x40041, 0x4f}, - {0x40061, 0x0}, - {0x40002, 0x4040}, - {0x40022, 0x83}, - {0x40042, 0x51}, - {0x40062, 0x0}, - {0x40003, 0x811}, - {0x40023, 0x880}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x720}, - {0x40024, 0xf}, - {0x40044, 0x1740}, - {0x40064, 0x0}, - {0x40005, 0x16}, - {0x40025, 0x83}, - {0x40045, 0x4b}, - {0x40065, 0x0}, - {0x40006, 0x716}, - {0x40026, 0xf}, - {0x40046, 0x2001}, - {0x40066, 0x0}, - {0x40007, 0x716}, - {0x40027, 0xf}, - {0x40047, 0x2800}, - {0x40067, 0x0}, - {0x40008, 0x716}, - {0x40028, 0xf}, - {0x40048, 0xf00}, - {0x40068, 0x0}, - {0x40009, 0x720}, - {0x40029, 0xf}, - {0x40049, 0x1400}, - {0x40069, 0x0}, - {0x4000a, 0xe08}, - {0x4002a, 0xc15}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x625}, - {0x4002b, 0x15}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x4028}, - {0x4002c, 0x80}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0xe08}, - {0x4002d, 0xc1a}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x625}, - {0x4002e, 0x1a}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x4040}, - {0x4002f, 0x80}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x2604}, - {0x40030, 0x15}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x708}, - {0x40031, 0x5}, - {0x40051, 0x0}, - {0x40071, 0x2002}, - {0x40012, 0x8}, - {0x40032, 0x80}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x2604}, - {0x40033, 0x1a}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x708}, - {0x40034, 0xa}, - {0x40054, 0x0}, - {0x40074, 0x2002}, - {0x40015, 0x4040}, - {0x40035, 0x80}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x60a}, - {0x40036, 0x15}, - {0x40056, 0x1200}, - {0x40076, 0x0}, - {0x40017, 0x61a}, - {0x40037, 0x15}, - {0x40057, 0x1300}, - {0x40077, 0x0}, - {0x40018, 0x60a}, - {0x40038, 0x1a}, - {0x40058, 0x1200}, - {0x40078, 0x0}, - {0x40019, 0x642}, - {0x40039, 0x1a}, - {0x40059, 0x1300}, - {0x40079, 0x0}, - {0x4001a, 0x4808}, - {0x4003a, 0x880}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x790}, - {0x900ac, 0x11a}, - {0x900ad, 0x8}, - {0x900ae, 0x7aa}, - {0x900af, 0x2a}, - {0x900b0, 0x10}, - {0x900b1, 0x7b2}, - {0x900b2, 0x2a}, - {0x900b3, 0x0}, - {0x900b4, 0x7c8}, - {0x900b5, 0x109}, - {0x900b6, 0x10}, - {0x900b7, 0x10}, - {0x900b8, 0x109}, - {0x900b9, 0x10}, - {0x900ba, 0x2a8}, - {0x900bb, 0x129}, - {0x900bc, 0x8}, - {0x900bd, 0x370}, - {0x900be, 0x129}, - {0x900bf, 0xa}, - {0x900c0, 0x3c8}, - {0x900c1, 0x1a9}, - {0x900c2, 0xc}, - {0x900c3, 0x408}, - {0x900c4, 0x199}, - {0x900c5, 0x14}, - {0x900c6, 0x790}, - {0x900c7, 0x11a}, - {0x900c8, 0x8}, - {0x900c9, 0x4}, - {0x900ca, 0x18}, - {0x900cb, 0xe}, - {0x900cc, 0x408}, - {0x900cd, 0x199}, - {0x900ce, 0x8}, - {0x900cf, 0x8568}, - {0x900d0, 0x108}, - {0x900d1, 0x18}, - {0x900d2, 0x790}, - {0x900d3, 0x16a}, - {0x900d4, 0x8}, - {0x900d5, 0x1d8}, - {0x900d6, 0x169}, - {0x900d7, 0x10}, - {0x900d8, 0x8558}, - {0x900d9, 0x168}, - {0x900da, 0x1ff8}, - {0x900db, 0x85a8}, - {0x900dc, 0x1e8}, - {0x900dd, 0x50}, - {0x900de, 0x798}, - {0x900df, 0x16a}, - {0x900e0, 0x60}, - {0x900e1, 0x7a0}, - {0x900e2, 0x16a}, - {0x900e3, 0x8}, - {0x900e4, 0x8310}, - {0x900e5, 0x168}, - {0x900e6, 0x8}, - {0x900e7, 0xa310}, - {0x900e8, 0x168}, - {0x900e9, 0xa}, - {0x900ea, 0x408}, - {0x900eb, 0x169}, - {0x900ec, 0x6e}, - {0x900ed, 0x0}, - {0x900ee, 0x68}, - {0x900ef, 0x0}, - {0x900f0, 0x408}, - {0x900f1, 0x169}, - {0x900f2, 0x0}, - {0x900f3, 0x8310}, - {0x900f4, 0x168}, - {0x900f5, 0x0}, - {0x900f6, 0xa310}, - {0x900f7, 0x168}, - {0x900f8, 0x1ff8}, - {0x900f9, 0x85a8}, - {0x900fa, 0x1e8}, - {0x900fb, 0x68}, - {0x900fc, 0x798}, - {0x900fd, 0x16a}, - {0x900fe, 0x78}, - {0x900ff, 0x7a0}, - {0x90100, 0x16a}, - {0x90101, 0x68}, - {0x90102, 0x790}, - {0x90103, 0x16a}, - {0x90104, 0x8}, - {0x90105, 0x8b10}, - {0x90106, 0x168}, - {0x90107, 0x8}, - {0x90108, 0xab10}, - {0x90109, 0x168}, - {0x9010a, 0xa}, - {0x9010b, 0x408}, - {0x9010c, 0x169}, - {0x9010d, 0x58}, - {0x9010e, 0x0}, - {0x9010f, 0x68}, - {0x90110, 0x0}, - {0x90111, 0x408}, - {0x90112, 0x169}, - {0x90113, 0x0}, - {0x90114, 0x8b10}, - {0x90115, 0x168}, - {0x90116, 0x1}, - {0x90117, 0xab10}, - {0x90118, 0x168}, - {0x90119, 0x0}, - {0x9011a, 0x1d8}, - {0x9011b, 0x169}, - {0x9011c, 0x80}, - {0x9011d, 0x790}, - {0x9011e, 0x16a}, - {0x9011f, 0x18}, - {0x90120, 0x7aa}, - {0x90121, 0x6a}, - {0x90122, 0xa}, - {0x90123, 0x0}, - {0x90124, 0x1e9}, - {0x90125, 0x8}, - {0x90126, 0x8080}, - {0x90127, 0x108}, - {0x90128, 0xf}, - {0x90129, 0x408}, - {0x9012a, 0x169}, - {0x9012b, 0xc}, - {0x9012c, 0x0}, - {0x9012d, 0x68}, - {0x9012e, 0x9}, - {0x9012f, 0x0}, - {0x90130, 0x1a9}, - {0x90131, 0x0}, - {0x90132, 0x408}, - {0x90133, 0x169}, - {0x90134, 0x0}, - {0x90135, 0x8080}, - {0x90136, 0x108}, - {0x90137, 0x8}, - {0x90138, 0x7aa}, - {0x90139, 0x6a}, - {0x9013a, 0x0}, - {0x9013b, 0x8568}, - {0x9013c, 0x108}, - {0x9013d, 0xb7}, - {0x9013e, 0x790}, - {0x9013f, 0x16a}, - {0x90140, 0x1f}, - {0x90141, 0x0}, - {0x90142, 0x68}, - {0x90143, 0x8}, - {0x90144, 0x8558}, - {0x90145, 0x168}, - {0x90146, 0xf}, - {0x90147, 0x408}, - {0x90148, 0x169}, - {0x90149, 0xd}, - {0x9014a, 0x0}, - {0x9014b, 0x68}, - {0x9014c, 0x0}, - {0x9014d, 0x408}, - {0x9014e, 0x169}, - {0x9014f, 0x0}, - {0x90150, 0x8558}, - {0x90151, 0x168}, - {0x90152, 0x8}, - {0x90153, 0x3c8}, - {0x90154, 0x1a9}, - {0x90155, 0x3}, - {0x90156, 0x370}, - {0x90157, 0x129}, - {0x90158, 0x20}, - {0x90159, 0x2aa}, - {0x9015a, 0x9}, - {0x9015b, 0x8}, - {0x9015c, 0xe8}, - {0x9015d, 0x109}, - {0x9015e, 0x0}, - {0x9015f, 0x8140}, - {0x90160, 0x10c}, - {0x90161, 0x10}, - {0x90162, 0x8138}, - {0x90163, 0x104}, - {0x90164, 0x8}, - {0x90165, 0x448}, - {0x90166, 0x109}, - {0x90167, 0xf}, - {0x90168, 0x7c0}, - {0x90169, 0x109}, - {0x9016a, 0x0}, - {0x9016b, 0xe8}, - {0x9016c, 0x109}, - {0x9016d, 0x47}, - {0x9016e, 0x630}, - {0x9016f, 0x109}, - {0x90170, 0x8}, - {0x90171, 0x618}, - {0x90172, 0x109}, - {0x90173, 0x8}, - {0x90174, 0xe0}, - {0x90175, 0x109}, - {0x90176, 0x0}, - {0x90177, 0x7c8}, - {0x90178, 0x109}, - {0x90179, 0x8}, - {0x9017a, 0x8140}, - {0x9017b, 0x10c}, - {0x9017c, 0x0}, - {0x9017d, 0x478}, - {0x9017e, 0x109}, - {0x9017f, 0x0}, - {0x90180, 0x1}, - {0x90181, 0x8}, - {0x90182, 0x8}, - {0x90183, 0x4}, - {0x90184, 0x0}, - {0x90006, 0x8}, - {0x90007, 0x7c8}, - {0x90008, 0x109}, - {0x90009, 0x0}, - {0x9000a, 0x400}, - {0x9000b, 0x106}, - {0xd00e7, 0x400}, - {0x90017, 0x0}, - {0x9001f, 0x2b}, - {0x90026, 0x69}, - {0x400d0, 0x0}, - {0x400d1, 0x101}, - {0x400d2, 0x105}, - {0x400d3, 0x107}, - {0x400d4, 0x10f}, - {0x400d5, 0x202}, - {0x400d6, 0x20a}, - {0x400d7, 0x20b}, - {0x2003a, 0x2}, - {0x200be, 0x3}, - {0x2000b, 0x20d}, - {0x2000c, 0x74}, - {0x2000d, 0x48e}, - {0x2000e, 0x2c}, - {0x12000b, 0x107}, - {0x12000c, 0x3a}, - {0x12000d, 0x246}, - {0x12000e, 0x21}, - {0x22000b, 0xb0}, - {0x22000c, 0x27}, - {0x22000d, 0x186}, - {0x22000e, 0x10}, - {0x9000c, 0x0}, - {0x9000d, 0x173}, - {0x9000e, 0x60}, - {0x9000f, 0x6110}, - {0x90010, 0x2152}, - {0x90011, 0xdfbd}, - {0x90012, 0x2060}, - {0x90013, 0x6152}, - {0x20010, 0x5a}, - {0x20011, 0x3}, - {0x120010, 0x5a}, - {0x120011, 0x3}, - {0x40080, 0xe0}, - {0x40081, 0x12}, - {0x40082, 0xe0}, - {0x40083, 0x12}, - {0x40084, 0xe0}, - {0x40085, 0x12}, - {0x140080, 0xe0}, - {0x140081, 0x12}, - {0x140082, 0xe0}, - {0x140083, 0x12}, - {0x140084, 0xe0}, - {0x140085, 0x12}, - {0x240080, 0xe0}, - {0x240081, 0x12}, - {0x240082, 0xe0}, - {0x240083, 0x12}, - {0x240084, 0xe0}, - {0x240085, 0x12}, - {0x400fd, 0xf}, - {0x400f1, 0xe}, - {0x10011, 0x1}, - {0x10012, 0x1}, - {0x10013, 0x180}, - {0x10018, 0x1}, - {0x10002, 0x6209}, - {0x100b2, 0x1}, - {0x101b4, 0x1}, - {0x102b4, 0x1}, - {0x103b4, 0x1}, - {0x104b4, 0x1}, - {0x105b4, 0x1}, - {0x106b4, 0x1}, - {0x107b4, 0x1}, - {0x108b4, 0x1}, - {0x11011, 0x1}, - {0x11012, 0x1}, - {0x11013, 0x180}, - {0x11018, 0x1}, - {0x11002, 0x6209}, - {0x110b2, 0x1}, - {0x111b4, 0x1}, - {0x112b4, 0x1}, - {0x113b4, 0x1}, - {0x114b4, 0x1}, - {0x115b4, 0x1}, - {0x116b4, 0x1}, - {0x117b4, 0x1}, - {0x118b4, 0x1}, - {0x20089, 0x1}, - {0x20088, 0x19}, - {0xc0080, 0x0}, - {0xd0000, 0x1}, -}; - -static struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 1866mts 1D */ - .drate = 1866, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 933mts 1D */ - .drate = 933, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 625mts 1D */ - .drate = 625, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 1866mts 2D */ - .drate = 1866, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing_1866mts = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 1866, 933, 625, }, - .fsp_cfg = ddr_dram_fsp_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), -}; diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c deleted file mode 100644 index 176d25a74a6..00000000000 --- a/board/freescale/imx93_evk/spl.c +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2022 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int spl_board_boot_device(enum boot_device boot_dev_spl) -{ - return BOOT_DEVICE_BOOTROM; -} - -void spl_board_init(void) -{ - int ret; - - ret = ele_start_rng(); - if (ret) - printf("Fail to start RNG: %d\n", ret); - - puts("Normal Boot\n"); -} - -extern struct dram_timing_info dram_timing_1866mts; -void spl_dram_init(void) -{ - struct dram_timing_info *ptiming = &dram_timing; - - if (is_voltage_mode(VOLT_LOW_DRIVE)) - ptiming = &dram_timing_1866mts; - - printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate); - ddr_init(ptiming); -} - -#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) -int power_init_board(void) -{ - struct udevice *dev; - int ret; - unsigned int val = 0, buck_val; - - ret = pmic_get("pmic@25", &dev); - if (ret == -ENODEV) { - puts("No pca9450@25\n"); - return 0; - } - if (ret != 0) - return ret; - - /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); - - /* enable DVS control through PMIC_STBY_REQ */ - pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); - - ret = pmic_reg_read(dev, PCA9450_PWR_CTRL); - if (ret < 0) - return ret; - - val = ret; - - if (is_voltage_mode(VOLT_LOW_DRIVE)) { - buck_val = 0x0c; /* 0.8v for Low drive mode */ - printf("PMIC: Low Drive Voltage Mode\n"); - } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) { - buck_val = 0x10; /* 0.85v for Nominal drive mode */ - printf("PMIC: Nominal Voltage Mode\n"); - } else { - buck_val = 0x14; /* 0.9v for Over drive mode */ - printf("PMIC: Over Drive Voltage Mode\n"); - } - - ele_volt_change_start_req(); - - if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val); - } else { - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4); - } - - ele_volt_change_finish_req(); - - /* set standby voltage to 0.65v */ - if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0); - else - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); - - /* I2C_LT_EN*/ - pmic_reg_write(dev, 0xa, 0x3); - return 0; -} -#endif - -void board_init_f(ulong dummy) -{ - int ret; - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - timer_init(); - - arch_cpu_init(); - - spl_early_init(); - - preloader_console_init(); - - ret = imx9_probe_mu(); - if (ret) { - printf("Fail to init Sentinel API\n"); - } else { - debug("SOC: 0x%x\n", gd->arch.soc_rev); - debug("LC: 0x%x\n", gd->arch.lifecycle); - } - - clock_init_late(); - - power_init_board(); - - if (!is_voltage_mode(VOLT_LOW_DRIVE)) - set_arm_clk(get_cpu_speed_grade_hz()); - - /* Init power of mix */ - soc_power_init(); - - /* Setup TRDC for DDR access */ - trdc_init(); - - /* DDR initialization */ - spl_dram_init(); - - /* Put M33 into CPUWAIT for following kick */ - ret = m33_prepare(); - if (!ret) - printf("M33 prepare ok\n"); - - board_init_r(NULL, 0); -} diff --git a/board/freescale/imx93_frdm/Kconfig b/board/freescale/imx93_frdm/Kconfig deleted file mode 100644 index 5f5ac7f8f04..00000000000 --- a/board/freescale/imx93_frdm/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_IMX93_FRDM - -config SYS_BOARD - default "imx93_frdm" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "imx93_frdm" - -endif diff --git a/board/freescale/imx93_frdm/MAINTAINERS b/board/freescale/imx93_frdm/MAINTAINERS deleted file mode 100644 index 59595bb2118..00000000000 --- a/board/freescale/imx93_frdm/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -i.MX93 FRDM BOARD -M: Fabio Estevam -S: Maintained -F: board/freescale/imx93_frdm/ -F: include/configs/imx93_frdm.h -F: configs/imx93_frdm_defconfig diff --git a/board/freescale/imx93_frdm/Makefile b/board/freescale/imx93_frdm/Makefile deleted file mode 100644 index 9612b1fa55b..00000000000 --- a/board/freescale/imx93_frdm/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright 2025 NXP -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += imx93_frdm.o - -ifdef CONFIG_XPL_BUILD -obj-y += spl.o lpddr4x_1gb_timing.o lpddr4x_2gb_timing.o -endif diff --git a/board/freescale/imx93_frdm/imx93_frdm.c b/board/freescale/imx93_frdm/imx93_frdm.c deleted file mode 100644 index cfbcde2e1a5..00000000000 --- a/board/freescale/imx93_frdm/imx93_frdm.c +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2025 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) -#define IMX_BOOT_IMAGE_GUID \ - EFI_GUID(0xbc550d86, 0xda26, 0x4b70, 0xac, 0x05, \ - 0x2a, 0x44, 0x8e, 0xda, 0x6f, 0x21) - -struct efi_fw_image fw_images[] = { - { - .image_type_id = IMX_BOOT_IMAGE_GUID, - .fw_name = u"IMX93-11X11-FRDM-RAW", - .image_index = 1, - }, -}; - -struct efi_capsule_update_info update_info = { - .dfu_string = "mmc 0=flash-bin raw 0 0x2000 mmcpart 1", - .num_images = ARRAY_SIZE(fw_images), - .images = fw_images, -}; -#endif /* EFI_HAVE_CAPSULE_SUPPORT */ - -#define TCPC_ALERT 0x10 -#define TCPC_ALERT_MASK 0x12 -#define TCPC_FAULT_STATUS_MASK 0x15 - -#define TCPC1_I2C_BUS 2 -#define TCPC1_I2C_ADDR 0x50 - -/* - * Mask all interrupts and clear alert status for the PTN5110 TCPC USB Power - * Delivery controller. This is required to avoid an interrupt storm on OS - * startup, since the interrupt line for the PTN5110 is shared also by the - * PCAL6524 I/O expander. - */ -static int clear_pd_alert(void) -{ - struct udevice *bus; - struct udevice *i2c_dev = NULL; - int ret; - u8 buffer_0[2] = {0, 0}; - u8 buffer_1[2] = {0xff, 0xff}; - - ret = uclass_get_device_by_seq(UCLASS_I2C, TCPC1_I2C_BUS, &bus); - if (ret) { - printf("Failed to get I2C bus %d\n", TCPC1_I2C_BUS); - return ret; - } - - ret = dm_i2c_probe(bus, TCPC1_I2C_ADDR, 0, &i2c_dev); - if (ret) { - printf("Can't find USB PD device at 0x%02x\n", TCPC1_I2C_ADDR); - return ret; - } - - /* Mask all alert status*/ - ret = dm_i2c_write(i2c_dev, TCPC_ALERT_MASK, buffer_0, 2); - if (ret) { - printf("%s dm_i2c_write failed: %d\n", __func__, ret); - return ret; - } - - ret = dm_i2c_write(i2c_dev, TCPC_FAULT_STATUS_MASK, buffer_0, 2); - if (ret) { - printf("%s dm_i2c_write failed: %d\n", __func__, ret); - return ret; - } - - /* Clear active alerts */ - ret = dm_i2c_write(i2c_dev, TCPC_ALERT, buffer_1, 2); - if (ret) { - printf("%s dm_i2c_write failed: %d\n", __func__, ret); - return ret; - } - - return 0; -} - -int board_early_init_f(void) -{ - return 0; -} - -int board_init(void) -{ - return 0; -} - -int board_late_init(void) -{ - if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC) || IS_ENABLED(CONFIG_ENV_IS_IN_NOWHERE)) - board_late_mmc_env_init(); - - if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { - env_set("board_name", "11X11_FRDM"); - env_set("board_rev", "iMX93"); - } - - if (get_boot_device() == USB_BOOT) { - printf("USB boot detected. Will enter fasboot mode\n"); - env_set_ulong("dofastboot", 1); - } - - clear_pd_alert(); - - return 0; -} diff --git a/board/freescale/imx93_frdm/imx93_frdm.env b/board/freescale/imx93_frdm/imx93_frdm.env deleted file mode 100644 index 111f38ed72a..00000000000 --- a/board/freescale/imx93_frdm/imx93_frdm.env +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ - -boot_targets=mmc0 mmc1 -boot_fit=no -bootm_size=0x10000000 -cntr_addr=0x98000000 -cntr_file=os_cntr_signed.bin -console=ttyLP0,115200 -fdt_addr_r=0x83000000 -fdt_addr=0x83000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE -image=Image -mmcdev=1 -mmcpart=1 -mmcroot=/dev/mmcblk${mmcdev}p2 rootwait rw -mmcautodetect=yes -mmcargs=setenv bootargs console=${console} root=${mmcroot} -kernel_addr_r=CONFIG_SYS_LOAD_ADDR -loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} -loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -boot_os=booti ${loadaddr} - ${fdt_addr_r} -fastboot_partition_alias_all=0:0 -fastboot_partition_alias_bootloader=0.1 -emmc_dev=0 -sd_dev=1 -dofastboot=0 - -bsp_bootcmd= - if test ${dofastboot} = 1; then - fastboot 0; - fi; - echo Running BSP bootcmd ...; - mmc dev ${mmcdev}; - run mmcargs; - run loadimage; - run loadfdt; - run boot_os; - -scriptaddr=0x83500000 diff --git a/board/freescale/imx93_frdm/lpddr4_timing.h b/board/freescale/imx93_frdm/lpddr4_timing.h deleted file mode 100644 index 192bc9e1519..00000000000 --- a/board/freescale/imx93_frdm/lpddr4_timing.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2022 Marek Vasut - */ - -#ifndef __LPDDR4_TIMING_H__ -#define __LPDDR4_TIMING_H__ - -extern struct dram_timing_info dram_timing_1GB; -extern struct dram_timing_info dram_timing_2GB; - -#endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/freescale/imx93_frdm/lpddr4x_1gb_timing.c b/board/freescale/imx93_frdm/lpddr4x_1gb_timing.c deleted file mode 100644 index 17549206ee4..00000000000 --- a/board/freescale/imx93_frdm/lpddr4x_1gb_timing.c +++ /dev/null @@ -1,1996 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright 2025 NXP - * - * Code generated with DDR Tool v3.3.0_7.8-d1cdb7d3. - * DDR PHY FW2022.01 - */ - -#include -#include - -/* Initialize DDRC registers */ -static struct dram_cfg_param ddr_ddrc_cfg[] = { - {0x4e300110, 0x44100001}, - {0x4e300000, 0x8000bf}, - {0x4e300008, 0x0}, - {0x4e300080, 0x80000412}, - {0x4e300084, 0x0}, - {0x4e300114, 0x1002}, - {0x4e300260, 0x80}, - {0x4e300f04, 0x80}, - {0x4e300800, 0x43b30002}, - {0x4e300804, 0x1f1f1f1f}, - {0x4e301000, 0x0}, - {0x4e301240, 0x0}, - {0x4e301244, 0x0}, - {0x4e301248, 0x0}, - {0x4e30124c, 0x0}, - {0x4e301250, 0x0}, - {0x4e301254, 0x0}, - {0x4e301258, 0x0}, - {0x4e30125c, 0x0}, -}; - -/* dram fsp cfg */ -static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { - { - { - {0x4e300100, 0x24A0321B}, - {0x4e300104, 0xF8EE001B}, - {0x4e300108, 0x2F2E3233}, - {0x4e30010C, 0x0005C18B}, - {0x4e300124, 0x1C790000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x35F00000}, - {0x4e300170, 0x8B0B0608}, - {0x4e300250, 0x00000028}, - {0x4e300254, 0x00FE00FE}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - {0x4e300300, 0x224F2213}, - {0x4e300304, 0x00FE2213}, - {0x4e300308, 0x0A380E3D}, - }, - { - {0x01, 0xE4}, - {0x02, 0x36}, - {0x03, 0x32}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x11}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x124F2100}, - {0x4e300104, 0xF877000E}, - {0x4e300108, 0x1816E4AA}, - {0x4e30010C, 0x005101E6}, - {0x4e300124, 0x0E3C0000}, - {0x4e300160, 0x00009101}, - {0x4e30016C, 0x30900000}, - {0x4e300170, 0x8A0A0508}, - {0x4e300250, 0x00000014}, - {0x4e300254, 0x007B007B}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0xB4}, - {0x02, 0x1B}, - {0x03, 0x32}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x11}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x00051000}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0x6E620A48}, - {0x4e30010C, 0x0031010D}, - {0x4e300124, 0x04C50000}, - {0x4e300160, 0x00009100}, - {0x4e30016C, 0x30000000}, - {0x4e300170, 0x89090408}, - {0x4e300250, 0x00000007}, - {0x4e300254, 0x00240024}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0x94}, - {0x02, 0x9}, - {0x03, 0x32}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x11}, - {0x16, 0x04}, - }, - 1, - }, - -}; - -/* PHY Initialize Configuration */ -static struct dram_cfg_param ddr_ddrphy_cfg[] = { - {0x100a0, 0x4}, - {0x100a1, 0x5}, - {0x100a2, 0x6}, - {0x100a3, 0x7}, - {0x100a4, 0x0}, - {0x100a5, 0x1}, - {0x100a6, 0x2}, - {0x100a7, 0x3}, - {0x110a0, 0x3}, - {0x110a1, 0x2}, - {0x110a2, 0x0}, - {0x110a3, 0x1}, - {0x110a4, 0x7}, - {0x110a5, 0x6}, - {0x110a6, 0x4}, - {0x110a7, 0x5}, - {0x1005f, 0x5ff}, - {0x1015f, 0x5ff}, - {0x1105f, 0x5ff}, - {0x1115f, 0x5ff}, - {0x11005f, 0x5ff}, - {0x11015f, 0x5ff}, - {0x11105f, 0x5ff}, - {0x11115f, 0x5ff}, - {0x21005f, 0x5ff}, - {0x21015f, 0x5ff}, - {0x21105f, 0x5ff}, - {0x21115f, 0x5ff}, - {0x55, 0x1ff}, - {0x1055, 0x1ff}, - {0x2055, 0x1ff}, - {0x200c5, 0x19}, - {0x1200c5, 0xb}, - {0x2200c5, 0x7}, - {0x2002e, 0x2}, - {0x12002e, 0x2}, - {0x22002e, 0x2}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x1e3}, - {0x2003a, 0x2}, - {0x2007d, 0x212}, - {0x2007c, 0x61}, - {0x120024, 0x1e3}, - {0x2003a, 0x2}, - {0x12007d, 0x212}, - {0x12007c, 0x61}, - {0x220024, 0x1e3}, - {0x2003a, 0x2}, - {0x22007d, 0x212}, - {0x22007c, 0x61}, - {0x20056, 0x3}, - {0x120056, 0x3}, - {0x220056, 0x3}, - {0x1004d, 0x600}, - {0x1014d, 0x600}, - {0x1104d, 0x600}, - {0x1114d, 0x600}, - {0x11004d, 0x600}, - {0x11014d, 0x600}, - {0x11104d, 0x600}, - {0x11114d, 0x600}, - {0x21004d, 0x600}, - {0x21014d, 0x600}, - {0x21104d, 0x600}, - {0x21114d, 0x600}, - {0x10049, 0xe00}, - {0x10149, 0xe00}, - {0x11049, 0xe00}, - {0x11149, 0xe00}, - {0x110049, 0xe00}, - {0x110149, 0xe00}, - {0x111049, 0xe00}, - {0x111149, 0xe00}, - {0x210049, 0xe00}, - {0x210149, 0xe00}, - {0x211049, 0xe00}, - {0x211149, 0xe00}, - {0x43, 0x60}, - {0x1043, 0x60}, - {0x2043, 0x60}, - {0x20018, 0x1}, - {0x20075, 0x4}, - {0x20050, 0x0}, - {0x2009b, 0x2}, - {0x20008, 0x3a5}, - {0x120008, 0x1d3}, - {0x220008, 0x9c}, - {0x20088, 0x9}, - {0x200b2, 0x10c}, - {0x10043, 0x5a1}, - {0x10143, 0x5a1}, - {0x11043, 0x5a1}, - {0x11143, 0x5a1}, - {0x1200b2, 0x10c}, - {0x110043, 0x5a1}, - {0x110143, 0x5a1}, - {0x111043, 0x5a1}, - {0x111143, 0x5a1}, - {0x2200b2, 0x10c}, - {0x210043, 0x5a1}, - {0x210143, 0x5a1}, - {0x211043, 0x5a1}, - {0x211143, 0x5a1}, - {0x200fa, 0x2}, - {0x1200fa, 0x2}, - {0x2200fa, 0x2}, - {0x20019, 0x1}, - {0x120019, 0x1}, - {0x220019, 0x1}, - {0x200f0, 0x600}, - {0x200f1, 0x0}, - {0x200f2, 0x4444}, - {0x200f3, 0x8888}, - {0x200f4, 0x5655}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0xf000}, - {0x1004a, 0x500}, - {0x1104a, 0x500}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0x20021, 0x0}, - {0x200c7, 0x21}, - {0x1200c7, 0x21}, - {0x200ca, 0x24}, - {0x1200ca, 0x24}, -}; - -/* PHY trained csr */ -static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - {0x1005f, 0x0}, - {0x1015f, 0x0}, - {0x1105f, 0x0}, - {0x1115f, 0x0}, - {0x11005f, 0x0}, - {0x11015f, 0x0}, - {0x11105f, 0x0}, - {0x11115f, 0x0}, - {0x21005f, 0x0}, - {0x21015f, 0x0}, - {0x21105f, 0x0}, - {0x21115f, 0x0}, - {0x55, 0x0}, - {0x1055, 0x0}, - {0x2055, 0x0}, - {0x200c5, 0x0}, - {0x1200c5, 0x0}, - {0x2200c5, 0x0}, - {0x2002e, 0x0}, - {0x12002e, 0x0}, - {0x22002e, 0x0}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x0}, - {0x2003a, 0x0}, - {0x2007d, 0x0}, - {0x2007c, 0x0}, - {0x120024, 0x0}, - {0x12007d, 0x0}, - {0x12007c, 0x0}, - {0x220024, 0x0}, - {0x22007d, 0x0}, - {0x22007c, 0x0}, - {0x20056, 0x0}, - {0x120056, 0x0}, - {0x220056, 0x0}, - {0x1004d, 0x0}, - {0x1014d, 0x0}, - {0x1104d, 0x0}, - {0x1114d, 0x0}, - {0x11004d, 0x0}, - {0x11014d, 0x0}, - {0x11104d, 0x0}, - {0x11114d, 0x0}, - {0x21004d, 0x0}, - {0x21014d, 0x0}, - {0x21104d, 0x0}, - {0x21114d, 0x0}, - {0x10049, 0x0}, - {0x10149, 0x0}, - {0x11049, 0x0}, - {0x11149, 0x0}, - {0x110049, 0x0}, - {0x110149, 0x0}, - {0x111049, 0x0}, - {0x111149, 0x0}, - {0x210049, 0x0}, - {0x210149, 0x0}, - {0x211049, 0x0}, - {0x211149, 0x0}, - {0x43, 0x0}, - {0x1043, 0x0}, - {0x2043, 0x0}, - {0x20018, 0x0}, - {0x20075, 0x0}, - {0x20050, 0x0}, - {0x2009b, 0x0}, - {0x20008, 0x0}, - {0x120008, 0x0}, - {0x220008, 0x0}, - {0x20088, 0x0}, - {0x200b2, 0x0}, - {0x10043, 0x0}, - {0x10143, 0x0}, - {0x11043, 0x0}, - {0x11143, 0x0}, - {0x1200b2, 0x0}, - {0x110043, 0x0}, - {0x110143, 0x0}, - {0x111043, 0x0}, - {0x111143, 0x0}, - {0x2200b2, 0x0}, - {0x210043, 0x0}, - {0x210143, 0x0}, - {0x211043, 0x0}, - {0x211143, 0x0}, - {0x200fa, 0x0}, - {0x1200fa, 0x0}, - {0x2200fa, 0x0}, - {0x20019, 0x0}, - {0x120019, 0x0}, - {0x220019, 0x0}, - {0x200f0, 0x0}, - {0x200f1, 0x0}, - {0x200f2, 0x0}, - {0x200f3, 0x0}, - {0x200f4, 0x0}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0x0}, - {0x1004a, 0x0}, - {0x1104a, 0x0}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0xd0000, 0x0}, - {0x90000, 0x0}, - {0x90001, 0x0}, - {0x90002, 0x0}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x0}, - {0x90029, 0x0}, - {0x9002a, 0x0}, - {0x9002b, 0x0}, - {0x9002c, 0x0}, - {0x9002d, 0x0}, - {0x9002e, 0x0}, - {0x9002f, 0x0}, - {0x90030, 0x0}, - {0x90031, 0x0}, - {0x90032, 0x0}, - {0x90033, 0x0}, - {0x90034, 0x0}, - {0x90035, 0x0}, - {0x90036, 0x0}, - {0x90037, 0x0}, - {0x90038, 0x0}, - {0x90039, 0x0}, - {0x9003a, 0x0}, - {0x9003b, 0x0}, - {0x9003c, 0x0}, - {0x9003d, 0x0}, - {0x9003e, 0x0}, - {0x9003f, 0x0}, - {0x90040, 0x0}, - {0x90041, 0x0}, - {0x90042, 0x0}, - {0x90043, 0x0}, - {0x90044, 0x0}, - {0x90045, 0x0}, - {0x90046, 0x0}, - {0x90047, 0x0}, - {0x90048, 0x0}, - {0x90049, 0x0}, - {0x9004a, 0x0}, - {0x9004b, 0x0}, - {0x9004c, 0x0}, - {0x9004d, 0x0}, - {0x9004e, 0x0}, - {0x9004f, 0x0}, - {0x90050, 0x0}, - {0x90051, 0x0}, - {0x90052, 0x0}, - {0x90053, 0x0}, - {0x90054, 0x0}, - {0x90055, 0x0}, - {0x90056, 0x0}, - {0x90057, 0x0}, - {0x90058, 0x0}, - {0x90059, 0x0}, - {0x9005a, 0x0}, - {0x9005b, 0x0}, - {0x9005c, 0x0}, - {0x9005d, 0x0}, - {0x9005e, 0x0}, - {0x9005f, 0x0}, - {0x90060, 0x0}, - {0x90061, 0x0}, - {0x90062, 0x0}, - {0x90063, 0x0}, - {0x90064, 0x0}, - {0x90065, 0x0}, - {0x90066, 0x0}, - {0x90067, 0x0}, - {0x90068, 0x0}, - {0x90069, 0x0}, - {0x9006a, 0x0}, - {0x9006b, 0x0}, - {0x9006c, 0x0}, - {0x9006d, 0x0}, - {0x9006e, 0x0}, - {0x9006f, 0x0}, - {0x90070, 0x0}, - {0x90071, 0x0}, - {0x90072, 0x0}, - {0x90073, 0x0}, - {0x90074, 0x0}, - {0x90075, 0x0}, - {0x90076, 0x0}, - {0x90077, 0x0}, - {0x90078, 0x0}, - {0x90079, 0x0}, - {0x9007a, 0x0}, - {0x9007b, 0x0}, - {0x9007c, 0x0}, - {0x9007d, 0x0}, - {0x9007e, 0x0}, - {0x9007f, 0x0}, - {0x90080, 0x0}, - {0x90081, 0x0}, - {0x90082, 0x0}, - {0x90083, 0x0}, - {0x90084, 0x0}, - {0x90085, 0x0}, - {0x90086, 0x0}, - {0x90087, 0x0}, - {0x90088, 0x0}, - {0x90089, 0x0}, - {0x9008a, 0x0}, - {0x9008b, 0x0}, - {0x9008c, 0x0}, - {0x9008d, 0x0}, - {0x9008e, 0x0}, - {0x9008f, 0x0}, - {0x90090, 0x0}, - {0x90091, 0x0}, - {0x90092, 0x0}, - {0x90093, 0x0}, - {0x90094, 0x0}, - {0x90095, 0x0}, - {0x90096, 0x0}, - {0x90097, 0x0}, - {0x90098, 0x0}, - {0x90099, 0x0}, - {0x9009a, 0x0}, - {0x9009b, 0x0}, - {0x9009c, 0x0}, - {0x9009d, 0x0}, - {0x9009e, 0x0}, - {0x9009f, 0x0}, - {0x900a0, 0x0}, - {0x900a1, 0x0}, - {0x900a2, 0x0}, - {0x900a3, 0x0}, - {0x900a4, 0x0}, - {0x900a5, 0x0}, - {0x900a6, 0x0}, - {0x900a7, 0x0}, - {0x900a8, 0x0}, - {0x900a9, 0x0}, - {0x40000, 0x0}, - {0x40020, 0x0}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x0}, - {0x40021, 0x0}, - {0x40041, 0x0}, - {0x40061, 0x0}, - {0x40002, 0x0}, - {0x40022, 0x0}, - {0x40042, 0x0}, - {0x40062, 0x0}, - {0x40003, 0x0}, - {0x40023, 0x0}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x0}, - {0x40024, 0x0}, - {0x40044, 0x0}, - {0x40064, 0x0}, - {0x40005, 0x0}, - {0x40025, 0x0}, - {0x40045, 0x0}, - {0x40065, 0x0}, - {0x40006, 0x0}, - {0x40026, 0x0}, - {0x40046, 0x0}, - {0x40066, 0x0}, - {0x40007, 0x0}, - {0x40027, 0x0}, - {0x40047, 0x0}, - {0x40067, 0x0}, - {0x40008, 0x0}, - {0x40028, 0x0}, - {0x40048, 0x0}, - {0x40068, 0x0}, - {0x40009, 0x0}, - {0x40029, 0x0}, - {0x40049, 0x0}, - {0x40069, 0x0}, - {0x4000a, 0x0}, - {0x4002a, 0x0}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x0}, - {0x4002b, 0x0}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x0}, - {0x4002c, 0x0}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0x0}, - {0x4002d, 0x0}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x0}, - {0x4002e, 0x0}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x0}, - {0x4002f, 0x0}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x0}, - {0x40030, 0x0}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x0}, - {0x40031, 0x0}, - {0x40051, 0x0}, - {0x40071, 0x0}, - {0x40012, 0x0}, - {0x40032, 0x0}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x0}, - {0x40033, 0x0}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x0}, - {0x40034, 0x0}, - {0x40054, 0x0}, - {0x40074, 0x0}, - {0x40015, 0x0}, - {0x40035, 0x0}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x0}, - {0x40036, 0x0}, - {0x40056, 0x0}, - {0x40076, 0x0}, - {0x40017, 0x0}, - {0x40037, 0x0}, - {0x40057, 0x0}, - {0x40077, 0x0}, - {0x40018, 0x0}, - {0x40038, 0x0}, - {0x40058, 0x0}, - {0x40078, 0x0}, - {0x40019, 0x0}, - {0x40039, 0x0}, - {0x40059, 0x0}, - {0x40079, 0x0}, - {0x4001a, 0x0}, - {0x4003a, 0x0}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x0}, - {0x900ac, 0x0}, - {0x900ad, 0x0}, - {0x900ae, 0x0}, - {0x900af, 0x0}, - {0x900b0, 0x0}, - {0x900b1, 0x0}, - {0x900b2, 0x0}, - {0x900b3, 0x0}, - {0x900b4, 0x0}, - {0x900b5, 0x0}, - {0x900b6, 0x0}, - {0x900b7, 0x0}, - {0x900b8, 0x0}, - {0x900b9, 0x0}, - {0x900ba, 0x0}, - {0x900bb, 0x0}, - {0x900bc, 0x0}, - {0x900bd, 0x0}, - {0x900be, 0x0}, - {0x900bf, 0x0}, - {0x900c0, 0x0}, - {0x900c1, 0x0}, - {0x900c2, 0x0}, - {0x900c3, 0x0}, - {0x900c4, 0x0}, - {0x900c5, 0x0}, - {0x900c6, 0x0}, - {0x900c7, 0x0}, - {0x900c8, 0x0}, - {0x900c9, 0x0}, - {0x900ca, 0x0}, - {0x900cb, 0x0}, - {0x900cc, 0x0}, - {0x900cd, 0x0}, - {0x900ce, 0x0}, - {0x900cf, 0x0}, - {0x900d0, 0x0}, - {0x900d1, 0x0}, - {0x900d2, 0x0}, - {0x900d3, 0x0}, - {0x900d4, 0x0}, - {0x900d5, 0x0}, - {0x900d6, 0x0}, - {0x900d7, 0x0}, - {0x900d8, 0x0}, - {0x900d9, 0x0}, - {0x900da, 0x0}, - {0x900db, 0x0}, - {0x900dc, 0x0}, - {0x900dd, 0x0}, - {0x900de, 0x0}, - {0x900df, 0x0}, - {0x900e0, 0x0}, - {0x900e1, 0x0}, - {0x900e2, 0x0}, - {0x900e3, 0x0}, - {0x900e4, 0x0}, - {0x900e5, 0x0}, - {0x900e6, 0x0}, - {0x900e7, 0x0}, - {0x900e8, 0x0}, - {0x900e9, 0x0}, - {0x900ea, 0x0}, - {0x900eb, 0x0}, - {0x900ec, 0x0}, - {0x900ed, 0x0}, - {0x900ee, 0x0}, - {0x900ef, 0x0}, - {0x900f0, 0x0}, - {0x900f1, 0x0}, - {0x900f2, 0x0}, - {0x900f3, 0x0}, - {0x900f4, 0x0}, - {0x900f5, 0x0}, - {0x900f6, 0x0}, - {0x900f7, 0x0}, - {0x900f8, 0x0}, - {0x900f9, 0x0}, - {0x900fa, 0x0}, - {0x900fb, 0x0}, - {0x900fc, 0x0}, - {0x900fd, 0x0}, - {0x900fe, 0x0}, - {0x900ff, 0x0}, - {0x90100, 0x0}, - {0x90101, 0x0}, - {0x90102, 0x0}, - {0x90103, 0x0}, - {0x90104, 0x0}, - {0x90105, 0x0}, - {0x90106, 0x0}, - {0x90107, 0x0}, - {0x90108, 0x0}, - {0x90109, 0x0}, - {0x9010a, 0x0}, - {0x9010b, 0x0}, - {0x9010c, 0x0}, - {0x9010d, 0x0}, - {0x9010e, 0x0}, - {0x9010f, 0x0}, - {0x90110, 0x0}, - {0x90111, 0x0}, - {0x90112, 0x0}, - {0x90113, 0x0}, - {0x90114, 0x0}, - {0x90115, 0x0}, - {0x90116, 0x0}, - {0x90117, 0x0}, - {0x90118, 0x0}, - {0x90119, 0x0}, - {0x9011a, 0x0}, - {0x9011b, 0x0}, - {0x9011c, 0x0}, - {0x9011d, 0x0}, - {0x9011e, 0x0}, - {0x9011f, 0x0}, - {0x90120, 0x0}, - {0x90121, 0x0}, - {0x90122, 0x0}, - {0x90123, 0x0}, - {0x90124, 0x0}, - {0x90125, 0x0}, - {0x90126, 0x0}, - {0x90127, 0x0}, - {0x90128, 0x0}, - {0x90129, 0x0}, - {0x9012a, 0x0}, - {0x9012b, 0x0}, - {0x9012c, 0x0}, - {0x9012d, 0x0}, - {0x9012e, 0x0}, - {0x9012f, 0x0}, - {0x90130, 0x0}, - {0x90131, 0x0}, - {0x90132, 0x0}, - {0x90133, 0x0}, - {0x90134, 0x0}, - {0x90135, 0x0}, - {0x90136, 0x0}, - {0x90137, 0x0}, - {0x90138, 0x0}, - {0x90139, 0x0}, - {0x9013a, 0x0}, - {0x9013b, 0x0}, - {0x9013c, 0x0}, - {0x9013d, 0x0}, - {0x9013e, 0x0}, - {0x9013f, 0x0}, - {0x90140, 0x0}, - {0x90141, 0x0}, - {0x90142, 0x0}, - {0x90143, 0x0}, - {0x90144, 0x0}, - {0x90145, 0x0}, - {0x90146, 0x0}, - {0x90147, 0x0}, - {0x90148, 0x0}, - {0x90149, 0x0}, - {0x9014a, 0x0}, - {0x9014b, 0x0}, - {0x9014c, 0x0}, - {0x9014d, 0x0}, - {0x9014e, 0x0}, - {0x9014f, 0x0}, - {0x90150, 0x0}, - {0x90151, 0x0}, - {0x90152, 0x0}, - {0x90153, 0x0}, - {0x90154, 0x0}, - {0x90155, 0x0}, - {0x90156, 0x0}, - {0x90157, 0x0}, - {0x90158, 0x0}, - {0x90159, 0x0}, - {0x9015a, 0x0}, - {0x9015b, 0x0}, - {0x9015c, 0x0}, - {0x9015d, 0x0}, - {0x9015e, 0x0}, - {0x9015f, 0x0}, - {0x90160, 0x0}, - {0x90161, 0x0}, - {0x90162, 0x0}, - {0x90163, 0x0}, - {0x90164, 0x0}, - {0x90165, 0x0}, - {0x90166, 0x0}, - {0x90167, 0x0}, - {0x90168, 0x0}, - {0x90169, 0x0}, - {0x9016a, 0x0}, - {0x9016b, 0x0}, - {0x9016c, 0x0}, - {0x9016d, 0x0}, - {0x9016e, 0x0}, - {0x9016f, 0x0}, - {0x90170, 0x0}, - {0x90171, 0x0}, - {0x90172, 0x0}, - {0x90173, 0x0}, - {0x90174, 0x0}, - {0x90175, 0x0}, - {0x90176, 0x0}, - {0x90177, 0x0}, - {0x90178, 0x0}, - {0x90179, 0x0}, - {0x9017a, 0x0}, - {0x9017b, 0x0}, - {0x9017c, 0x0}, - {0x9017d, 0x0}, - {0x9017e, 0x0}, - {0x9017f, 0x0}, - {0x90180, 0x0}, - {0x90181, 0x0}, - {0x90182, 0x0}, - {0x90183, 0x0}, - {0x90184, 0x0}, - {0x90006, 0x0}, - {0x90007, 0x0}, - {0x90008, 0x0}, - {0x90009, 0x0}, - {0x9000a, 0x0}, - {0x9000b, 0x0}, - {0xd00e7, 0x0}, - {0x90017, 0x0}, - {0x9001f, 0x0}, - {0x90026, 0x0}, - {0x400d0, 0x0}, - {0x400d1, 0x0}, - {0x400d2, 0x0}, - {0x400d3, 0x0}, - {0x400d4, 0x0}, - {0x400d5, 0x0}, - {0x400d6, 0x0}, - {0x400d7, 0x0}, - {0x200be, 0x0}, - {0x2000b, 0x0}, - {0x2000c, 0x0}, - {0x2000d, 0x0}, - {0x2000e, 0x0}, - {0x12000b, 0x0}, - {0x12000c, 0x0}, - {0x12000d, 0x0}, - {0x12000e, 0x0}, - {0x22000b, 0x0}, - {0x22000c, 0x0}, - {0x22000d, 0x0}, - {0x22000e, 0x0}, - {0x9000c, 0x0}, - {0x9000d, 0x0}, - {0x9000e, 0x0}, - {0x9000f, 0x0}, - {0x90010, 0x0}, - {0x90011, 0x0}, - {0x90012, 0x0}, - {0x90013, 0x0}, - {0x20010, 0x0}, - {0x20011, 0x0}, - {0x120010, 0x0}, - {0x120011, 0x0}, - {0x40080, 0x0}, - {0x40081, 0x0}, - {0x40082, 0x0}, - {0x40083, 0x0}, - {0x40084, 0x0}, - {0x40085, 0x0}, - {0x140080, 0x0}, - {0x140081, 0x0}, - {0x140082, 0x0}, - {0x140083, 0x0}, - {0x140084, 0x0}, - {0x140085, 0x0}, - {0x240080, 0x0}, - {0x240081, 0x0}, - {0x240082, 0x0}, - {0x240083, 0x0}, - {0x240084, 0x0}, - {0x240085, 0x0}, - {0x400fd, 0x0}, - {0x400f1, 0x0}, - {0x10011, 0x0}, - {0x10012, 0x0}, - {0x10013, 0x0}, - {0x10018, 0x0}, - {0x10002, 0x0}, - {0x100b2, 0x0}, - {0x101b4, 0x0}, - {0x102b4, 0x0}, - {0x103b4, 0x0}, - {0x104b4, 0x0}, - {0x105b4, 0x0}, - {0x106b4, 0x0}, - {0x107b4, 0x0}, - {0x108b4, 0x0}, - {0x11011, 0x0}, - {0x11012, 0x0}, - {0x11013, 0x0}, - {0x11018, 0x0}, - {0x11002, 0x0}, - {0x110b2, 0x0}, - {0x111b4, 0x0}, - {0x112b4, 0x0}, - {0x113b4, 0x0}, - {0x114b4, 0x0}, - {0x115b4, 0x0}, - {0x116b4, 0x0}, - {0x117b4, 0x0}, - {0x118b4, 0x0}, - {0x20089, 0x0}, - {0xc0080, 0x0}, - {0x200cb, 0x0}, - {0x10068, 0x0}, - {0x10069, 0x0}, - {0x10168, 0x0}, - {0x10169, 0x0}, - {0x10268, 0x0}, - {0x10269, 0x0}, - {0x10368, 0x0}, - {0x10369, 0x0}, - {0x10468, 0x0}, - {0x10469, 0x0}, - {0x10568, 0x0}, - {0x10569, 0x0}, - {0x10668, 0x0}, - {0x10669, 0x0}, - {0x10768, 0x0}, - {0x10769, 0x0}, - {0x10868, 0x0}, - {0x10869, 0x0}, - {0x100aa, 0x0}, - {0x10062, 0x0}, - {0x10001, 0x0}, - {0x100a0, 0x0}, - {0x100a1, 0x0}, - {0x100a2, 0x0}, - {0x100a3, 0x0}, - {0x100a4, 0x0}, - {0x100a5, 0x0}, - {0x100a6, 0x0}, - {0x100a7, 0x0}, - {0x11068, 0x0}, - {0x11069, 0x0}, - {0x11168, 0x0}, - {0x11169, 0x0}, - {0x11268, 0x0}, - {0x11269, 0x0}, - {0x11368, 0x0}, - {0x11369, 0x0}, - {0x11468, 0x0}, - {0x11469, 0x0}, - {0x11568, 0x0}, - {0x11569, 0x0}, - {0x11668, 0x0}, - {0x11669, 0x0}, - {0x11768, 0x0}, - {0x11769, 0x0}, - {0x11868, 0x0}, - {0x11869, 0x0}, - {0x110aa, 0x0}, - {0x11062, 0x0}, - {0x11001, 0x0}, - {0x110a0, 0x0}, - {0x110a1, 0x0}, - {0x110a2, 0x0}, - {0x110a3, 0x0}, - {0x110a4, 0x0}, - {0x110a5, 0x0}, - {0x110a6, 0x0}, - {0x110a7, 0x0}, - {0x80, 0x0}, - {0x1080, 0x0}, - {0x2080, 0x0}, - {0x10020, 0x0}, - {0x10080, 0x0}, - {0x10081, 0x0}, - {0x100d0, 0x0}, - {0x100d1, 0x0}, - {0x1008c, 0x0}, - {0x1008d, 0x0}, - {0x10180, 0x0}, - {0x10181, 0x0}, - {0x101d0, 0x0}, - {0x101d1, 0x0}, - {0x1018c, 0x0}, - {0x1018d, 0x0}, - {0x100c0, 0x0}, - {0x100c1, 0x0}, - {0x101c0, 0x0}, - {0x101c1, 0x0}, - {0x102c0, 0x0}, - {0x102c1, 0x0}, - {0x103c0, 0x0}, - {0x103c1, 0x0}, - {0x104c0, 0x0}, - {0x104c1, 0x0}, - {0x105c0, 0x0}, - {0x105c1, 0x0}, - {0x106c0, 0x0}, - {0x106c1, 0x0}, - {0x107c0, 0x0}, - {0x107c1, 0x0}, - {0x108c0, 0x0}, - {0x108c1, 0x0}, - {0x100ae, 0x0}, - {0x100af, 0x0}, - {0x11020, 0x0}, - {0x11080, 0x0}, - {0x11081, 0x0}, - {0x110d0, 0x0}, - {0x110d1, 0x0}, - {0x1108c, 0x0}, - {0x1108d, 0x0}, - {0x11180, 0x0}, - {0x11181, 0x0}, - {0x111d0, 0x0}, - {0x111d1, 0x0}, - {0x1118c, 0x0}, - {0x1118d, 0x0}, - {0x110c0, 0x0}, - {0x110c1, 0x0}, - {0x111c0, 0x0}, - {0x111c1, 0x0}, - {0x112c0, 0x0}, - {0x112c1, 0x0}, - {0x113c0, 0x0}, - {0x113c1, 0x0}, - {0x114c0, 0x0}, - {0x114c1, 0x0}, - {0x115c0, 0x0}, - {0x115c1, 0x0}, - {0x116c0, 0x0}, - {0x116c1, 0x0}, - {0x117c0, 0x0}, - {0x117c1, 0x0}, - {0x118c0, 0x0}, - {0x118c1, 0x0}, - {0x110ae, 0x0}, - {0x110af, 0x0}, - {0x90201, 0x0}, - {0x90202, 0x0}, - {0x90203, 0x0}, - {0x90205, 0x0}, - {0x90206, 0x0}, - {0x90207, 0x0}, - {0x90208, 0x0}, - {0x20020, 0x0}, - {0x100080, 0x0}, - {0x101080, 0x0}, - {0x102080, 0x0}, - {0x110020, 0x0}, - {0x110080, 0x0}, - {0x110081, 0x0}, - {0x1100d0, 0x0}, - {0x1100d1, 0x0}, - {0x11008c, 0x0}, - {0x11008d, 0x0}, - {0x110180, 0x0}, - {0x110181, 0x0}, - {0x1101d0, 0x0}, - {0x1101d1, 0x0}, - {0x11018c, 0x0}, - {0x11018d, 0x0}, - {0x1100c0, 0x0}, - {0x1100c1, 0x0}, - {0x1101c0, 0x0}, - {0x1101c1, 0x0}, - {0x1102c0, 0x0}, - {0x1102c1, 0x0}, - {0x1103c0, 0x0}, - {0x1103c1, 0x0}, - {0x1104c0, 0x0}, - {0x1104c1, 0x0}, - {0x1105c0, 0x0}, - {0x1105c1, 0x0}, - {0x1106c0, 0x0}, - {0x1106c1, 0x0}, - {0x1107c0, 0x0}, - {0x1107c1, 0x0}, - {0x1108c0, 0x0}, - {0x1108c1, 0x0}, - {0x1100ae, 0x0}, - {0x1100af, 0x0}, - {0x111020, 0x0}, - {0x111080, 0x0}, - {0x111081, 0x0}, - {0x1110d0, 0x0}, - {0x1110d1, 0x0}, - {0x11108c, 0x0}, - {0x11108d, 0x0}, - {0x111180, 0x0}, - {0x111181, 0x0}, - {0x1111d0, 0x0}, - {0x1111d1, 0x0}, - {0x11118c, 0x0}, - {0x11118d, 0x0}, - {0x1110c0, 0x0}, - {0x1110c1, 0x0}, - {0x1111c0, 0x0}, - {0x1111c1, 0x0}, - {0x1112c0, 0x0}, - {0x1112c1, 0x0}, - {0x1113c0, 0x0}, - {0x1113c1, 0x0}, - {0x1114c0, 0x0}, - {0x1114c1, 0x0}, - {0x1115c0, 0x0}, - {0x1115c1, 0x0}, - {0x1116c0, 0x0}, - {0x1116c1, 0x0}, - {0x1117c0, 0x0}, - {0x1117c1, 0x0}, - {0x1118c0, 0x0}, - {0x1118c1, 0x0}, - {0x1110ae, 0x0}, - {0x1110af, 0x0}, - {0x190201, 0x0}, - {0x190202, 0x0}, - {0x190203, 0x0}, - {0x190205, 0x0}, - {0x190206, 0x0}, - {0x190207, 0x0}, - {0x190208, 0x0}, - {0x120020, 0x0}, - {0x200080, 0x0}, - {0x201080, 0x0}, - {0x202080, 0x0}, - {0x210020, 0x0}, - {0x210080, 0x0}, - {0x210081, 0x0}, - {0x2100d0, 0x0}, - {0x2100d1, 0x0}, - {0x21008c, 0x0}, - {0x21008d, 0x0}, - {0x210180, 0x0}, - {0x210181, 0x0}, - {0x2101d0, 0x0}, - {0x2101d1, 0x0}, - {0x21018c, 0x0}, - {0x21018d, 0x0}, - {0x2100c0, 0x0}, - {0x2100c1, 0x0}, - {0x2101c0, 0x0}, - {0x2101c1, 0x0}, - {0x2102c0, 0x0}, - {0x2102c1, 0x0}, - {0x2103c0, 0x0}, - {0x2103c1, 0x0}, - {0x2104c0, 0x0}, - {0x2104c1, 0x0}, - {0x2105c0, 0x0}, - {0x2105c1, 0x0}, - {0x2106c0, 0x0}, - {0x2106c1, 0x0}, - {0x2107c0, 0x0}, - {0x2107c1, 0x0}, - {0x2108c0, 0x0}, - {0x2108c1, 0x0}, - {0x2100ae, 0x0}, - {0x2100af, 0x0}, - {0x211020, 0x0}, - {0x211080, 0x0}, - {0x211081, 0x0}, - {0x2110d0, 0x0}, - {0x2110d1, 0x0}, - {0x21108c, 0x0}, - {0x21108d, 0x0}, - {0x211180, 0x0}, - {0x211181, 0x0}, - {0x2111d0, 0x0}, - {0x2111d1, 0x0}, - {0x21118c, 0x0}, - {0x21118d, 0x0}, - {0x2110c0, 0x0}, - {0x2110c1, 0x0}, - {0x2111c0, 0x0}, - {0x2111c1, 0x0}, - {0x2112c0, 0x0}, - {0x2112c1, 0x0}, - {0x2113c0, 0x0}, - {0x2113c1, 0x0}, - {0x2114c0, 0x0}, - {0x2114c1, 0x0}, - {0x2115c0, 0x0}, - {0x2115c1, 0x0}, - {0x2116c0, 0x0}, - {0x2116c1, 0x0}, - {0x2117c0, 0x0}, - {0x2117c1, 0x0}, - {0x2118c0, 0x0}, - {0x2118c1, 0x0}, - {0x2110ae, 0x0}, - {0x2110af, 0x0}, - {0x290201, 0x0}, - {0x290202, 0x0}, - {0x290203, 0x0}, - {0x290205, 0x0}, - {0x290206, 0x0}, - {0x290207, 0x0}, - {0x290208, 0x0}, - {0x220020, 0x0}, - {0x20077, 0x0}, - {0x20072, 0x0}, - {0x20073, 0x0}, - {0x400c0, 0x0}, - {0x10040, 0x0}, - {0x10140, 0x0}, - {0x10240, 0x0}, - {0x10340, 0x0}, - {0x10440, 0x0}, - {0x10540, 0x0}, - {0x10640, 0x0}, - {0x10740, 0x0}, - {0x10840, 0x0}, - {0x11040, 0x0}, - {0x11140, 0x0}, - {0x11240, 0x0}, - {0x11340, 0x0}, - {0x11440, 0x0}, - {0x11540, 0x0}, - {0x11640, 0x0}, - {0x11740, 0x0}, - {0x11840, 0x0}, -}; - -/* P0 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0xe94}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x131f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x36e4}, - {0x5401a, 0x32}, - {0x5401b, 0x1146}, - {0x5401c, 0x1108}, - {0x5401e, 0x4}, - {0x5401f, 0x36e4}, - {0x54020, 0x32}, - {0x54021, 0x1146}, - {0x54022, 0x1108}, - {0x54024, 0x4}, - {0x54032, 0xe400}, - {0x54033, 0x3236}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x11}, - {0x54037, 0x400}, - {0x54038, 0xe400}, - {0x54039, 0x3236}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x11}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P1 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp1_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x1}, - {0x54003, 0x74a}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x1bb4}, - {0x5401a, 0x32}, - {0x5401b, 0x1146}, - {0x5401c, 0x1108}, - {0x5401e, 0x4}, - {0x5401f, 0x1bb4}, - {0x54020, 0x32}, - {0x54021, 0x1146}, - {0x54022, 0x1108}, - {0x54024, 0x4}, - {0x54032, 0xb400}, - {0x54033, 0x321b}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x11}, - {0x54037, 0x400}, - {0x54038, 0xb400}, - {0x54039, 0x321b}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x11}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P2 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp2_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x102}, - {0x54003, 0x270}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x994}, - {0x5401a, 0x32}, - {0x5401b, 0x1146}, - {0x5401c, 0x1100}, - {0x5401e, 0x4}, - {0x5401f, 0x994}, - {0x54020, 0x32}, - {0x54021, 0x1146}, - {0x54022, 0x1100}, - {0x54024, 0x4}, - {0x54032, 0x9400}, - {0x54033, 0x3209}, - {0x54034, 0x4600}, - {0x54035, 0x11}, - {0x54036, 0x11}, - {0x54037, 0x400}, - {0x54038, 0x9400}, - {0x54039, 0x3209}, - {0x5403a, 0x4600}, - {0x5403b, 0x11}, - {0x5403c, 0x11}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P0 2D message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0xe94}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x61}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54010, 0x2080}, - {0x54012, 0x110}, - {0x54019, 0x36e4}, - {0x5401a, 0x32}, - {0x5401b, 0x1146}, - {0x5401c, 0x1108}, - {0x5401e, 0x4}, - {0x5401f, 0x36e4}, - {0x54020, 0x32}, - {0x54021, 0x1146}, - {0x54022, 0x1108}, - {0x54024, 0x4}, - {0x54032, 0xe400}, - {0x54033, 0x3236}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x11}, - {0x54037, 0x400}, - {0x54038, 0xe400}, - {0x54039, 0x3236}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x11}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* DRAM PHY init engine image */ -static struct dram_cfg_param ddr_phy_pie[] = { - {0xd0000, 0x0}, - {0x90000, 0x10}, - {0x90001, 0x400}, - {0x90002, 0x10e}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x8}, - {0x90029, 0xb}, - {0x9002a, 0x480}, - {0x9002b, 0x109}, - {0x9002c, 0x8}, - {0x9002d, 0x448}, - {0x9002e, 0x139}, - {0x9002f, 0x8}, - {0x90030, 0x478}, - {0x90031, 0x109}, - {0x90032, 0x0}, - {0x90033, 0xe8}, - {0x90034, 0x109}, - {0x90035, 0x2}, - {0x90036, 0x10}, - {0x90037, 0x139}, - {0x90038, 0xb}, - {0x90039, 0x7c0}, - {0x9003a, 0x139}, - {0x9003b, 0x44}, - {0x9003c, 0x633}, - {0x9003d, 0x159}, - {0x9003e, 0x14f}, - {0x9003f, 0x630}, - {0x90040, 0x159}, - {0x90041, 0x47}, - {0x90042, 0x633}, - {0x90043, 0x149}, - {0x90044, 0x4f}, - {0x90045, 0x633}, - {0x90046, 0x179}, - {0x90047, 0x8}, - {0x90048, 0xe0}, - {0x90049, 0x109}, - {0x9004a, 0x0}, - {0x9004b, 0x7c8}, - {0x9004c, 0x109}, - {0x9004d, 0x0}, - {0x9004e, 0x1}, - {0x9004f, 0x8}, - {0x90050, 0x30}, - {0x90051, 0x65a}, - {0x90052, 0x9}, - {0x90053, 0x0}, - {0x90054, 0x45a}, - {0x90055, 0x9}, - {0x90056, 0x0}, - {0x90057, 0x448}, - {0x90058, 0x109}, - {0x90059, 0x40}, - {0x9005a, 0x633}, - {0x9005b, 0x179}, - {0x9005c, 0x1}, - {0x9005d, 0x618}, - {0x9005e, 0x109}, - {0x9005f, 0x40c0}, - {0x90060, 0x633}, - {0x90061, 0x149}, - {0x90062, 0x8}, - {0x90063, 0x4}, - {0x90064, 0x48}, - {0x90065, 0x4040}, - {0x90066, 0x633}, - {0x90067, 0x149}, - {0x90068, 0x0}, - {0x90069, 0x4}, - {0x9006a, 0x48}, - {0x9006b, 0x40}, - {0x9006c, 0x633}, - {0x9006d, 0x149}, - {0x9006e, 0x0}, - {0x9006f, 0x658}, - {0x90070, 0x109}, - {0x90071, 0x10}, - {0x90072, 0x4}, - {0x90073, 0x18}, - {0x90074, 0x0}, - {0x90075, 0x4}, - {0x90076, 0x78}, - {0x90077, 0x549}, - {0x90078, 0x633}, - {0x90079, 0x159}, - {0x9007a, 0xd49}, - {0x9007b, 0x633}, - {0x9007c, 0x159}, - {0x9007d, 0x94a}, - {0x9007e, 0x633}, - {0x9007f, 0x159}, - {0x90080, 0x441}, - {0x90081, 0x633}, - {0x90082, 0x149}, - {0x90083, 0x42}, - {0x90084, 0x633}, - {0x90085, 0x149}, - {0x90086, 0x1}, - {0x90087, 0x633}, - {0x90088, 0x149}, - {0x90089, 0x0}, - {0x9008a, 0xe0}, - {0x9008b, 0x109}, - {0x9008c, 0xa}, - {0x9008d, 0x10}, - {0x9008e, 0x109}, - {0x9008f, 0x9}, - {0x90090, 0x3c0}, - {0x90091, 0x149}, - {0x90092, 0x9}, - {0x90093, 0x3c0}, - {0x90094, 0x159}, - {0x90095, 0x18}, - {0x90096, 0x10}, - {0x90097, 0x109}, - {0x90098, 0x0}, - {0x90099, 0x3c0}, - {0x9009a, 0x109}, - {0x9009b, 0x18}, - {0x9009c, 0x4}, - {0x9009d, 0x48}, - {0x9009e, 0x18}, - {0x9009f, 0x4}, - {0x900a0, 0x58}, - {0x900a1, 0xb}, - {0x900a2, 0x10}, - {0x900a3, 0x109}, - {0x900a4, 0x1}, - {0x900a5, 0x10}, - {0x900a6, 0x109}, - {0x900a7, 0x5}, - {0x900a8, 0x7c0}, - {0x900a9, 0x109}, - {0x40000, 0x811}, - {0x40020, 0x880}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x4008}, - {0x40021, 0x83}, - {0x40041, 0x4f}, - {0x40061, 0x0}, - {0x40002, 0x4040}, - {0x40022, 0x83}, - {0x40042, 0x51}, - {0x40062, 0x0}, - {0x40003, 0x811}, - {0x40023, 0x880}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x720}, - {0x40024, 0xf}, - {0x40044, 0x1740}, - {0x40064, 0x0}, - {0x40005, 0x16}, - {0x40025, 0x83}, - {0x40045, 0x4b}, - {0x40065, 0x0}, - {0x40006, 0x716}, - {0x40026, 0xf}, - {0x40046, 0x2001}, - {0x40066, 0x0}, - {0x40007, 0x716}, - {0x40027, 0xf}, - {0x40047, 0x2800}, - {0x40067, 0x0}, - {0x40008, 0x716}, - {0x40028, 0xf}, - {0x40048, 0xf00}, - {0x40068, 0x0}, - {0x40009, 0x720}, - {0x40029, 0xf}, - {0x40049, 0x1400}, - {0x40069, 0x0}, - {0x4000a, 0xe08}, - {0x4002a, 0xc15}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x625}, - {0x4002b, 0x15}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x4028}, - {0x4002c, 0x80}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0xe08}, - {0x4002d, 0xc1a}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x625}, - {0x4002e, 0x1a}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x4040}, - {0x4002f, 0x80}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x2604}, - {0x40030, 0x15}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x708}, - {0x40031, 0x5}, - {0x40051, 0x0}, - {0x40071, 0x2002}, - {0x40012, 0x8}, - {0x40032, 0x80}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x2604}, - {0x40033, 0x1a}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x708}, - {0x40034, 0xa}, - {0x40054, 0x0}, - {0x40074, 0x2002}, - {0x40015, 0x4040}, - {0x40035, 0x80}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x60a}, - {0x40036, 0x15}, - {0x40056, 0x1200}, - {0x40076, 0x0}, - {0x40017, 0x61a}, - {0x40037, 0x15}, - {0x40057, 0x1300}, - {0x40077, 0x0}, - {0x40018, 0x60a}, - {0x40038, 0x1a}, - {0x40058, 0x1200}, - {0x40078, 0x0}, - {0x40019, 0x642}, - {0x40039, 0x1a}, - {0x40059, 0x1300}, - {0x40079, 0x0}, - {0x4001a, 0x4808}, - {0x4003a, 0x880}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x790}, - {0x900ac, 0x11a}, - {0x900ad, 0x8}, - {0x900ae, 0x7aa}, - {0x900af, 0x2a}, - {0x900b0, 0x10}, - {0x900b1, 0x7b2}, - {0x900b2, 0x2a}, - {0x900b3, 0x0}, - {0x900b4, 0x7c8}, - {0x900b5, 0x109}, - {0x900b6, 0x10}, - {0x900b7, 0x10}, - {0x900b8, 0x109}, - {0x900b9, 0x10}, - {0x900ba, 0x2a8}, - {0x900bb, 0x129}, - {0x900bc, 0x8}, - {0x900bd, 0x370}, - {0x900be, 0x129}, - {0x900bf, 0xa}, - {0x900c0, 0x3c8}, - {0x900c1, 0x1a9}, - {0x900c2, 0xc}, - {0x900c3, 0x408}, - {0x900c4, 0x199}, - {0x900c5, 0x14}, - {0x900c6, 0x790}, - {0x900c7, 0x11a}, - {0x900c8, 0x8}, - {0x900c9, 0x4}, - {0x900ca, 0x18}, - {0x900cb, 0xe}, - {0x900cc, 0x408}, - {0x900cd, 0x199}, - {0x900ce, 0x8}, - {0x900cf, 0x8568}, - {0x900d0, 0x108}, - {0x900d1, 0x18}, - {0x900d2, 0x790}, - {0x900d3, 0x16a}, - {0x900d4, 0x8}, - {0x900d5, 0x1d8}, - {0x900d6, 0x169}, - {0x900d7, 0x10}, - {0x900d8, 0x8558}, - {0x900d9, 0x168}, - {0x900da, 0x1ff8}, - {0x900db, 0x85a8}, - {0x900dc, 0x1e8}, - {0x900dd, 0x50}, - {0x900de, 0x798}, - {0x900df, 0x16a}, - {0x900e0, 0x60}, - {0x900e1, 0x7a0}, - {0x900e2, 0x16a}, - {0x900e3, 0x8}, - {0x900e4, 0x8310}, - {0x900e5, 0x168}, - {0x900e6, 0x8}, - {0x900e7, 0xa310}, - {0x900e8, 0x168}, - {0x900e9, 0xa}, - {0x900ea, 0x408}, - {0x900eb, 0x169}, - {0x900ec, 0x6e}, - {0x900ed, 0x0}, - {0x900ee, 0x68}, - {0x900ef, 0x0}, - {0x900f0, 0x408}, - {0x900f1, 0x169}, - {0x900f2, 0x0}, - {0x900f3, 0x8310}, - {0x900f4, 0x168}, - {0x900f5, 0x0}, - {0x900f6, 0xa310}, - {0x900f7, 0x168}, - {0x900f8, 0x1ff8}, - {0x900f9, 0x85a8}, - {0x900fa, 0x1e8}, - {0x900fb, 0x68}, - {0x900fc, 0x798}, - {0x900fd, 0x16a}, - {0x900fe, 0x78}, - {0x900ff, 0x7a0}, - {0x90100, 0x16a}, - {0x90101, 0x68}, - {0x90102, 0x790}, - {0x90103, 0x16a}, - {0x90104, 0x8}, - {0x90105, 0x8b10}, - {0x90106, 0x168}, - {0x90107, 0x8}, - {0x90108, 0xab10}, - {0x90109, 0x168}, - {0x9010a, 0xa}, - {0x9010b, 0x408}, - {0x9010c, 0x169}, - {0x9010d, 0x58}, - {0x9010e, 0x0}, - {0x9010f, 0x68}, - {0x90110, 0x0}, - {0x90111, 0x408}, - {0x90112, 0x169}, - {0x90113, 0x0}, - {0x90114, 0x8b10}, - {0x90115, 0x168}, - {0x90116, 0x1}, - {0x90117, 0xab10}, - {0x90118, 0x168}, - {0x90119, 0x0}, - {0x9011a, 0x1d8}, - {0x9011b, 0x169}, - {0x9011c, 0x80}, - {0x9011d, 0x790}, - {0x9011e, 0x16a}, - {0x9011f, 0x18}, - {0x90120, 0x7aa}, - {0x90121, 0x6a}, - {0x90122, 0xa}, - {0x90123, 0x0}, - {0x90124, 0x1e9}, - {0x90125, 0x8}, - {0x90126, 0x8080}, - {0x90127, 0x108}, - {0x90128, 0xf}, - {0x90129, 0x408}, - {0x9012a, 0x169}, - {0x9012b, 0xc}, - {0x9012c, 0x0}, - {0x9012d, 0x68}, - {0x9012e, 0x9}, - {0x9012f, 0x0}, - {0x90130, 0x1a9}, - {0x90131, 0x0}, - {0x90132, 0x408}, - {0x90133, 0x169}, - {0x90134, 0x0}, - {0x90135, 0x8080}, - {0x90136, 0x108}, - {0x90137, 0x8}, - {0x90138, 0x7aa}, - {0x90139, 0x6a}, - {0x9013a, 0x0}, - {0x9013b, 0x8568}, - {0x9013c, 0x108}, - {0x9013d, 0xb7}, - {0x9013e, 0x790}, - {0x9013f, 0x16a}, - {0x90140, 0x1f}, - {0x90141, 0x0}, - {0x90142, 0x68}, - {0x90143, 0x8}, - {0x90144, 0x8558}, - {0x90145, 0x168}, - {0x90146, 0xf}, - {0x90147, 0x408}, - {0x90148, 0x169}, - {0x90149, 0xd}, - {0x9014a, 0x0}, - {0x9014b, 0x68}, - {0x9014c, 0x0}, - {0x9014d, 0x408}, - {0x9014e, 0x169}, - {0x9014f, 0x0}, - {0x90150, 0x8558}, - {0x90151, 0x168}, - {0x90152, 0x8}, - {0x90153, 0x3c8}, - {0x90154, 0x1a9}, - {0x90155, 0x3}, - {0x90156, 0x370}, - {0x90157, 0x129}, - {0x90158, 0x20}, - {0x90159, 0x2aa}, - {0x9015a, 0x9}, - {0x9015b, 0x8}, - {0x9015c, 0xe8}, - {0x9015d, 0x109}, - {0x9015e, 0x0}, - {0x9015f, 0x8140}, - {0x90160, 0x10c}, - {0x90161, 0x10}, - {0x90162, 0x8138}, - {0x90163, 0x104}, - {0x90164, 0x8}, - {0x90165, 0x448}, - {0x90166, 0x109}, - {0x90167, 0xf}, - {0x90168, 0x7c0}, - {0x90169, 0x109}, - {0x9016a, 0x0}, - {0x9016b, 0xe8}, - {0x9016c, 0x109}, - {0x9016d, 0x47}, - {0x9016e, 0x630}, - {0x9016f, 0x109}, - {0x90170, 0x8}, - {0x90171, 0x618}, - {0x90172, 0x109}, - {0x90173, 0x8}, - {0x90174, 0xe0}, - {0x90175, 0x109}, - {0x90176, 0x0}, - {0x90177, 0x7c8}, - {0x90178, 0x109}, - {0x90179, 0x8}, - {0x9017a, 0x8140}, - {0x9017b, 0x10c}, - {0x9017c, 0x0}, - {0x9017d, 0x478}, - {0x9017e, 0x109}, - {0x9017f, 0x0}, - {0x90180, 0x1}, - {0x90181, 0x8}, - {0x90182, 0x8}, - {0x90183, 0x4}, - {0x90184, 0x0}, - {0x90006, 0x8}, - {0x90007, 0x7c8}, - {0x90008, 0x109}, - {0x90009, 0x0}, - {0x9000a, 0x400}, - {0x9000b, 0x106}, - {0xd00e7, 0x400}, - {0x90017, 0x0}, - {0x9001f, 0x2b}, - {0x90026, 0x69}, - {0x400d0, 0x0}, - {0x400d1, 0x101}, - {0x400d2, 0x105}, - {0x400d3, 0x107}, - {0x400d4, 0x10f}, - {0x400d5, 0x202}, - {0x400d6, 0x20a}, - {0x400d7, 0x20b}, - {0x2003a, 0x2}, - {0x200be, 0x3}, - {0x2000b, 0x41a}, - {0x2000c, 0xe9}, - {0x2000d, 0x91c}, - {0x2000e, 0x2c}, - {0x12000b, 0x20d}, - {0x12000c, 0x74}, - {0x12000d, 0x48e}, - {0x12000e, 0x2c}, - {0x22000b, 0xb0}, - {0x22000c, 0x27}, - {0x22000d, 0x186}, - {0x22000e, 0x10}, - {0x9000c, 0x0}, - {0x9000d, 0x173}, - {0x9000e, 0x60}, - {0x9000f, 0x6110}, - {0x90010, 0x2152}, - {0x90011, 0xdfbd}, - {0x90012, 0x2060}, - {0x90013, 0x6152}, - {0x20010, 0x5a}, - {0x20011, 0x3}, - {0x120010, 0x5a}, - {0x120011, 0x3}, - {0x40080, 0xe0}, - {0x40081, 0x12}, - {0x40082, 0xe0}, - {0x40083, 0x12}, - {0x40084, 0xe0}, - {0x40085, 0x12}, - {0x140080, 0xe0}, - {0x140081, 0x12}, - {0x140082, 0xe0}, - {0x140083, 0x12}, - {0x140084, 0xe0}, - {0x140085, 0x12}, - {0x240080, 0xe0}, - {0x240081, 0x12}, - {0x240082, 0xe0}, - {0x240083, 0x12}, - {0x240084, 0xe0}, - {0x240085, 0x12}, - {0x400fd, 0xf}, - {0x400f1, 0xe}, - {0x10011, 0x1}, - {0x10012, 0x1}, - {0x10013, 0x180}, - {0x10018, 0x1}, - {0x10002, 0x6209}, - {0x100b2, 0x1}, - {0x101b4, 0x1}, - {0x102b4, 0x1}, - {0x103b4, 0x1}, - {0x104b4, 0x1}, - {0x105b4, 0x1}, - {0x106b4, 0x1}, - {0x107b4, 0x1}, - {0x108b4, 0x1}, - {0x11011, 0x1}, - {0x11012, 0x1}, - {0x11013, 0x180}, - {0x11018, 0x1}, - {0x11002, 0x6209}, - {0x110b2, 0x1}, - {0x111b4, 0x1}, - {0x112b4, 0x1}, - {0x113b4, 0x1}, - {0x114b4, 0x1}, - {0x115b4, 0x1}, - {0x116b4, 0x1}, - {0x117b4, 0x1}, - {0x118b4, 0x1}, - {0x20089, 0x1}, - {0x20088, 0x19}, - {0xc0080, 0x0}, - {0xd0000, 0x1}, -}; - -static struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 3733mts 1D */ - .drate = 3733, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 1866mts 1D */ - .drate = 1866, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 625mts 1D */ - .drate = 625, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 3733mts 2D */ - .drate = 3733, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing_1GB = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3733, 1866, 625, }, - .fsp_cfg = ddr_dram_fsp_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), -}; diff --git a/board/freescale/imx93_frdm/lpddr4x_2gb_timing.c b/board/freescale/imx93_frdm/lpddr4x_2gb_timing.c deleted file mode 100644 index cd129e12959..00000000000 --- a/board/freescale/imx93_frdm/lpddr4x_2gb_timing.c +++ /dev/null @@ -1,1995 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright 2025 NXP - * - * Code generated with DDR Tool v3.4.0_8.3-4e2b550a. - * DDR PHY FW2022.01 - */ - -#include -#include - -/* Initialize DDRC registers */ -static struct dram_cfg_param ddr_ddrc_cfg[] = { - {0x4e300110, 0x44100001}, - {0x4e300000, 0x8000ff}, - {0x4e300008, 0x0}, - {0x4e300080, 0x80000512}, - {0x4e300084, 0x0}, - {0x4e300114, 0x1002}, - {0x4e300260, 0x80}, - {0x4e300f04, 0x80}, - {0x4e300800, 0x43b30002}, - {0x4e300804, 0x1f1f1f1f}, - {0x4e301000, 0x0}, - {0x4e301240, 0x0}, - {0x4e301244, 0x0}, - {0x4e301248, 0x0}, - {0x4e30124c, 0x0}, - {0x4e301250, 0x0}, - {0x4e301254, 0x0}, - {0x4e301258, 0x0}, - {0x4e30125c, 0x0}, -}; - -/* dram fsp cfg */ -static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { - { - { - {0x4e300100, 0x24AB321B}, - {0x4e300104, 0xF8EE001B}, - {0x4e300108, 0x2F2EE233}, - {0x4e30010C, 0x0005E18B}, - {0x4e300124, 0x1C760000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x35F00000}, - {0x4e300170, 0x8B0B0608}, - {0x4e300250, 0x00000028}, - {0x4e300254, 0x015B015B}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - {0x4e300300, 0x224F2213}, - {0x4e300304, 0x015B2213}, - {0x4e300308, 0x0A3C0E3D}, - }, - { - {0x01, 0xE4}, - {0x02, 0x36}, - {0x03, 0x32}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x11}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x12552100}, - {0x4e300104, 0xF877000E}, - {0x4e300108, 0x1816B4AA}, - {0x4e30010C, 0x005101E6}, - {0x4e300124, 0x0E3C0000}, - {0x4e300160, 0x00009101}, - {0x4e30016C, 0x30900000}, - {0x4e300170, 0x8A0A0508}, - {0x4e300250, 0x00000014}, - {0x4e300254, 0x00AA00AA}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0xB4}, - {0x02, 0x1B}, - {0x03, 0x32}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x11}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x00061000}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0x6E62FA48}, - {0x4e30010C, 0x0031010D}, - {0x4e300124, 0x04C50000}, - {0x4e300160, 0x00009100}, - {0x4e30016C, 0x30000000}, - {0x4e300170, 0x89090408}, - {0x4e300250, 0x00000007}, - {0x4e300254, 0x00340034}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0x94}, - {0x02, 0x9}, - {0x03, 0x32}, - {0x0b, 0x46}, - {0x0c, 0x11}, - {0x0e, 0x11}, - {0x16, 0x04}, - }, - 1, - }, -}; - -/* PHY Initialize Configuration */ -static struct dram_cfg_param ddr_ddrphy_cfg[] = { - {0x100a0, 0x4}, - {0x100a1, 0x5}, - {0x100a2, 0x6}, - {0x100a3, 0x7}, - {0x100a4, 0x0}, - {0x100a5, 0x1}, - {0x100a6, 0x2}, - {0x100a7, 0x3}, - {0x110a0, 0x3}, - {0x110a1, 0x2}, - {0x110a2, 0x0}, - {0x110a3, 0x1}, - {0x110a4, 0x7}, - {0x110a5, 0x6}, - {0x110a6, 0x4}, - {0x110a7, 0x5}, - {0x1005f, 0x5ff}, - {0x1015f, 0x5ff}, - {0x1105f, 0x5ff}, - {0x1115f, 0x5ff}, - {0x11005f, 0x5ff}, - {0x11015f, 0x5ff}, - {0x11105f, 0x5ff}, - {0x11115f, 0x5ff}, - {0x21005f, 0x5ff}, - {0x21015f, 0x5ff}, - {0x21105f, 0x5ff}, - {0x21115f, 0x5ff}, - {0x55, 0x1ff}, - {0x1055, 0x1ff}, - {0x2055, 0x1ff}, - {0x200c5, 0x19}, - {0x1200c5, 0xb}, - {0x2200c5, 0x7}, - {0x2002e, 0x2}, - {0x12002e, 0x2}, - {0x22002e, 0x2}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x1e3}, - {0x2003a, 0x2}, - {0x2007d, 0x212}, - {0x2007c, 0x61}, - {0x120024, 0x1e3}, - {0x2003a, 0x2}, - {0x12007d, 0x212}, - {0x12007c, 0x61}, - {0x220024, 0x1e3}, - {0x2003a, 0x2}, - {0x22007d, 0x212}, - {0x22007c, 0x61}, - {0x20056, 0x3}, - {0x120056, 0x3}, - {0x220056, 0x3}, - {0x1004d, 0x600}, - {0x1014d, 0x600}, - {0x1104d, 0x600}, - {0x1114d, 0x600}, - {0x11004d, 0x600}, - {0x11014d, 0x600}, - {0x11104d, 0x600}, - {0x11114d, 0x600}, - {0x21004d, 0x600}, - {0x21014d, 0x600}, - {0x21104d, 0x600}, - {0x21114d, 0x600}, - {0x10049, 0xe00}, - {0x10149, 0xe00}, - {0x11049, 0xe00}, - {0x11149, 0xe00}, - {0x110049, 0xe00}, - {0x110149, 0xe00}, - {0x111049, 0xe00}, - {0x111149, 0xe00}, - {0x210049, 0xe00}, - {0x210149, 0xe00}, - {0x211049, 0xe00}, - {0x211149, 0xe00}, - {0x43, 0x60}, - {0x1043, 0x60}, - {0x2043, 0x60}, - {0x20018, 0x1}, - {0x20075, 0x4}, - {0x20050, 0x0}, - {0x2009b, 0x2}, - {0x20008, 0x3a5}, - {0x120008, 0x1d3}, - {0x220008, 0x9c}, - {0x20088, 0x9}, - {0x200b2, 0x10c}, - {0x10043, 0x5a1}, - {0x10143, 0x5a1}, - {0x11043, 0x5a1}, - {0x11143, 0x5a1}, - {0x1200b2, 0x10c}, - {0x110043, 0x5a1}, - {0x110143, 0x5a1}, - {0x111043, 0x5a1}, - {0x111143, 0x5a1}, - {0x2200b2, 0x10c}, - {0x210043, 0x5a1}, - {0x210143, 0x5a1}, - {0x211043, 0x5a1}, - {0x211143, 0x5a1}, - {0x200fa, 0x2}, - {0x1200fa, 0x2}, - {0x2200fa, 0x2}, - {0x20019, 0x1}, - {0x120019, 0x1}, - {0x220019, 0x1}, - {0x200f0, 0x600}, - {0x200f1, 0x0}, - {0x200f2, 0x4444}, - {0x200f3, 0x8888}, - {0x200f4, 0x5655}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0xf000}, - {0x1004a, 0x500}, - {0x1104a, 0x500}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0x20021, 0x0}, - {0x200c7, 0x21}, - {0x1200c7, 0x21}, - {0x200ca, 0x24}, - {0x1200ca, 0x24}, -}; - -/* ddr phy trained csr */ -static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - {0x1005f, 0x0}, - {0x1015f, 0x0}, - {0x1105f, 0x0}, - {0x1115f, 0x0}, - {0x11005f, 0x0}, - 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{0x10369, 0x0}, - {0x10468, 0x0}, - {0x10469, 0x0}, - {0x10568, 0x0}, - {0x10569, 0x0}, - {0x10668, 0x0}, - {0x10669, 0x0}, - {0x10768, 0x0}, - {0x10769, 0x0}, - {0x10868, 0x0}, - {0x10869, 0x0}, - {0x100aa, 0x0}, - {0x10062, 0x0}, - {0x10001, 0x0}, - {0x100a0, 0x0}, - {0x100a1, 0x0}, - {0x100a2, 0x0}, - {0x100a3, 0x0}, - {0x100a4, 0x0}, - {0x100a5, 0x0}, - {0x100a6, 0x0}, - {0x100a7, 0x0}, - {0x11068, 0x0}, - {0x11069, 0x0}, - {0x11168, 0x0}, - {0x11169, 0x0}, - {0x11268, 0x0}, - {0x11269, 0x0}, - {0x11368, 0x0}, - {0x11369, 0x0}, - {0x11468, 0x0}, - {0x11469, 0x0}, - {0x11568, 0x0}, - {0x11569, 0x0}, - {0x11668, 0x0}, - {0x11669, 0x0}, - {0x11768, 0x0}, - {0x11769, 0x0}, - {0x11868, 0x0}, - {0x11869, 0x0}, - {0x110aa, 0x0}, - {0x11062, 0x0}, - {0x11001, 0x0}, - {0x110a0, 0x0}, - {0x110a1, 0x0}, - {0x110a2, 0x0}, - {0x110a3, 0x0}, - {0x110a4, 0x0}, - {0x110a5, 0x0}, - {0x110a6, 0x0}, - {0x110a7, 0x0}, - {0x80, 0x0}, - {0x1080, 0x0}, - {0x2080, 0x0}, - {0x10020, 0x0}, - {0x10080, 0x0}, - {0x10081, 0x0}, - {0x100d0, 0x0}, - {0x100d1, 0x0}, - {0x1008c, 0x0}, - {0x1008d, 0x0}, - {0x10180, 0x0}, - {0x10181, 0x0}, - {0x101d0, 0x0}, - {0x101d1, 0x0}, - {0x1018c, 0x0}, - {0x1018d, 0x0}, - {0x100c0, 0x0}, - {0x100c1, 0x0}, - {0x101c0, 0x0}, - {0x101c1, 0x0}, - {0x102c0, 0x0}, - {0x102c1, 0x0}, - {0x103c0, 0x0}, - {0x103c1, 0x0}, - {0x104c0, 0x0}, - {0x104c1, 0x0}, - {0x105c0, 0x0}, - {0x105c1, 0x0}, - {0x106c0, 0x0}, - {0x106c1, 0x0}, - {0x107c0, 0x0}, - {0x107c1, 0x0}, - {0x108c0, 0x0}, - {0x108c1, 0x0}, - {0x100ae, 0x0}, - {0x100af, 0x0}, - {0x11020, 0x0}, - {0x11080, 0x0}, - {0x11081, 0x0}, - {0x110d0, 0x0}, - {0x110d1, 0x0}, - {0x1108c, 0x0}, - {0x1108d, 0x0}, - {0x11180, 0x0}, - {0x11181, 0x0}, - {0x111d0, 0x0}, - {0x111d1, 0x0}, - {0x1118c, 0x0}, - {0x1118d, 0x0}, - {0x110c0, 0x0}, - {0x110c1, 0x0}, - {0x111c0, 0x0}, - {0x111c1, 0x0}, - {0x112c0, 0x0}, - {0x112c1, 0x0}, - {0x113c0, 0x0}, - {0x113c1, 0x0}, - {0x114c0, 0x0}, - {0x114c1, 0x0}, - {0x115c0, 0x0}, - {0x115c1, 0x0}, - {0x116c0, 0x0}, - {0x116c1, 0x0}, - {0x117c0, 0x0}, - {0x117c1, 0x0}, - {0x118c0, 0x0}, - {0x118c1, 0x0}, - {0x110ae, 0x0}, - {0x110af, 0x0}, - {0x90201, 0x0}, - {0x90202, 0x0}, - {0x90203, 0x0}, - {0x90205, 0x0}, - {0x90206, 0x0}, - {0x90207, 0x0}, - {0x90208, 0x0}, - {0x20020, 0x0}, - {0x100080, 0x0}, - {0x101080, 0x0}, - {0x102080, 0x0}, - {0x110020, 0x0}, - {0x110080, 0x0}, - {0x110081, 0x0}, - {0x1100d0, 0x0}, - {0x1100d1, 0x0}, - {0x11008c, 0x0}, - {0x11008d, 0x0}, - {0x110180, 0x0}, - {0x110181, 0x0}, - {0x1101d0, 0x0}, - {0x1101d1, 0x0}, - {0x11018c, 0x0}, - {0x11018d, 0x0}, - {0x1100c0, 0x0}, - {0x1100c1, 0x0}, - {0x1101c0, 0x0}, - {0x1101c1, 0x0}, - {0x1102c0, 0x0}, - {0x1102c1, 0x0}, - {0x1103c0, 0x0}, - {0x1103c1, 0x0}, - {0x1104c0, 0x0}, - {0x1104c1, 0x0}, - {0x1105c0, 0x0}, - {0x1105c1, 0x0}, - {0x1106c0, 0x0}, - {0x1106c1, 0x0}, - {0x1107c0, 0x0}, - {0x1107c1, 0x0}, - {0x1108c0, 0x0}, - {0x1108c1, 0x0}, - {0x1100ae, 0x0}, - {0x1100af, 0x0}, - {0x111020, 0x0}, - {0x111080, 0x0}, - {0x111081, 0x0}, - {0x1110d0, 0x0}, - {0x1110d1, 0x0}, - {0x11108c, 0x0}, - {0x11108d, 0x0}, - {0x111180, 0x0}, - {0x111181, 0x0}, - {0x1111d0, 0x0}, - {0x1111d1, 0x0}, - {0x11118c, 0x0}, - {0x11118d, 0x0}, - {0x1110c0, 0x0}, - {0x1110c1, 0x0}, - {0x1111c0, 0x0}, - {0x1111c1, 0x0}, - {0x1112c0, 0x0}, - {0x1112c1, 0x0}, - {0x1113c0, 0x0}, - {0x1113c1, 0x0}, - {0x1114c0, 0x0}, - {0x1114c1, 0x0}, - {0x1115c0, 0x0}, - {0x1115c1, 0x0}, - {0x1116c0, 0x0}, - {0x1116c1, 0x0}, - {0x1117c0, 0x0}, - {0x1117c1, 0x0}, - {0x1118c0, 0x0}, - {0x1118c1, 0x0}, - {0x1110ae, 0x0}, - {0x1110af, 0x0}, - {0x190201, 0x0}, - {0x190202, 0x0}, - {0x190203, 0x0}, - {0x190205, 0x0}, - {0x190206, 0x0}, - {0x190207, 0x0}, - {0x190208, 0x0}, - {0x120020, 0x0}, - {0x200080, 0x0}, - {0x201080, 0x0}, - {0x202080, 0x0}, - {0x210020, 0x0}, - {0x210080, 0x0}, - {0x210081, 0x0}, - {0x2100d0, 0x0}, - {0x2100d1, 0x0}, - {0x21008c, 0x0}, - {0x21008d, 0x0}, - {0x210180, 0x0}, - {0x210181, 0x0}, - {0x2101d0, 0x0}, - {0x2101d1, 0x0}, - {0x21018c, 0x0}, - {0x21018d, 0x0}, - {0x2100c0, 0x0}, - {0x2100c1, 0x0}, - {0x2101c0, 0x0}, - {0x2101c1, 0x0}, - {0x2102c0, 0x0}, - {0x2102c1, 0x0}, - {0x2103c0, 0x0}, - {0x2103c1, 0x0}, - {0x2104c0, 0x0}, - {0x2104c1, 0x0}, - {0x2105c0, 0x0}, - {0x2105c1, 0x0}, - {0x2106c0, 0x0}, - {0x2106c1, 0x0}, - {0x2107c0, 0x0}, - {0x2107c1, 0x0}, - {0x2108c0, 0x0}, - {0x2108c1, 0x0}, - {0x2100ae, 0x0}, - {0x2100af, 0x0}, - {0x211020, 0x0}, - {0x211080, 0x0}, - {0x211081, 0x0}, - {0x2110d0, 0x0}, - {0x2110d1, 0x0}, - {0x21108c, 0x0}, - {0x21108d, 0x0}, - {0x211180, 0x0}, - {0x211181, 0x0}, - {0x2111d0, 0x0}, - {0x2111d1, 0x0}, - {0x21118c, 0x0}, - {0x21118d, 0x0}, - {0x2110c0, 0x0}, - {0x2110c1, 0x0}, - {0x2111c0, 0x0}, - {0x2111c1, 0x0}, - {0x2112c0, 0x0}, - {0x2112c1, 0x0}, - {0x2113c0, 0x0}, - {0x2113c1, 0x0}, - {0x2114c0, 0x0}, - {0x2114c1, 0x0}, - {0x2115c0, 0x0}, - {0x2115c1, 0x0}, - {0x2116c0, 0x0}, - {0x2116c1, 0x0}, - {0x2117c0, 0x0}, - {0x2117c1, 0x0}, - {0x2118c0, 0x0}, - {0x2118c1, 0x0}, - {0x2110ae, 0x0}, - {0x2110af, 0x0}, - {0x290201, 0x0}, - {0x290202, 0x0}, - {0x290203, 0x0}, - {0x290205, 0x0}, - {0x290206, 0x0}, - {0x290207, 0x0}, - {0x290208, 0x0}, - {0x220020, 0x0}, - {0x20077, 0x0}, - {0x20072, 0x0}, - {0x20073, 0x0}, - {0x400c0, 0x0}, - {0x10040, 0x0}, - {0x10140, 0x0}, - {0x10240, 0x0}, - {0x10340, 0x0}, - {0x10440, 0x0}, - {0x10540, 0x0}, - {0x10640, 0x0}, - {0x10740, 0x0}, - {0x10840, 0x0}, - {0x11040, 0x0}, - {0x11140, 0x0}, - {0x11240, 0x0}, - {0x11340, 0x0}, - {0x11440, 0x0}, - {0x11540, 0x0}, - {0x11640, 0x0}, - {0x11740, 0x0}, - {0x11840, 0x0}, -}; - -/* P0 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0xe94}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x131f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x36e4}, - {0x5401a, 0x32}, - {0x5401b, 0x1146}, - {0x5401c, 0x1108}, - {0x5401e, 0x4}, - {0x5401f, 0x36e4}, - {0x54020, 0x32}, - {0x54021, 0x1146}, - {0x54022, 0x1108}, - {0x54024, 0x4}, - {0x54032, 0xe400}, - {0x54033, 0x3236}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x11}, - {0x54037, 0x400}, - {0x54038, 0xe400}, - {0x54039, 0x3236}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x11}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P1 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp1_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x1}, - {0x54003, 0x74a}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x1bb4}, - {0x5401a, 0x32}, - {0x5401b, 0x1146}, - {0x5401c, 0x1108}, - {0x5401e, 0x4}, - {0x5401f, 0x1bb4}, - {0x54020, 0x32}, - {0x54021, 0x1146}, - {0x54022, 0x1108}, - {0x54024, 0x4}, - {0x54032, 0xb400}, - {0x54033, 0x321b}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x11}, - {0x54037, 0x400}, - {0x54038, 0xb400}, - {0x54039, 0x321b}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x11}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P2 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp2_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x102}, - {0x54003, 0x270}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x994}, - {0x5401a, 0x32}, - {0x5401b, 0x1146}, - {0x5401c, 0x1100}, - {0x5401e, 0x4}, - {0x5401f, 0x994}, - {0x54020, 0x32}, - {0x54021, 0x1146}, - {0x54022, 0x1100}, - {0x54024, 0x4}, - {0x54032, 0x9400}, - {0x54033, 0x3209}, - {0x54034, 0x4600}, - {0x54035, 0x11}, - {0x54036, 0x11}, - {0x54037, 0x400}, - {0x54038, 0x9400}, - {0x54039, 0x3209}, - {0x5403a, 0x4600}, - {0x5403b, 0x11}, - {0x5403c, 0x11}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P0 2D message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0xe94}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x61}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54010, 0x2080}, - {0x54012, 0x110}, - {0x54019, 0x36e4}, - {0x5401a, 0x32}, - {0x5401b, 0x1146}, - {0x5401c, 0x1108}, - {0x5401e, 0x4}, - {0x5401f, 0x36e4}, - {0x54020, 0x32}, - {0x54021, 0x1146}, - {0x54022, 0x1108}, - {0x54024, 0x4}, - {0x54032, 0xe400}, - {0x54033, 0x3236}, - {0x54034, 0x4600}, - {0x54035, 0x811}, - {0x54036, 0x11}, - {0x54037, 0x400}, - {0x54038, 0xe400}, - {0x54039, 0x3236}, - {0x5403a, 0x4600}, - {0x5403b, 0x811}, - {0x5403c, 0x11}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* DRAM PHY init engine image */ -static struct dram_cfg_param ddr_phy_pie[] = { - {0xd0000, 0x0}, - {0x90000, 0x10}, - {0x90001, 0x400}, - {0x90002, 0x10e}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x8}, - {0x90029, 0xb}, - {0x9002a, 0x480}, - {0x9002b, 0x109}, - {0x9002c, 0x8}, - {0x9002d, 0x448}, - {0x9002e, 0x139}, - {0x9002f, 0x8}, - {0x90030, 0x478}, - {0x90031, 0x109}, - {0x90032, 0x0}, - {0x90033, 0xe8}, - {0x90034, 0x109}, - {0x90035, 0x2}, - {0x90036, 0x10}, - {0x90037, 0x139}, - {0x90038, 0xb}, - {0x90039, 0x7c0}, - {0x9003a, 0x139}, - {0x9003b, 0x44}, - {0x9003c, 0x633}, - {0x9003d, 0x159}, - {0x9003e, 0x14f}, - {0x9003f, 0x630}, - {0x90040, 0x159}, - {0x90041, 0x47}, - {0x90042, 0x633}, - {0x90043, 0x149}, - {0x90044, 0x4f}, - {0x90045, 0x633}, - {0x90046, 0x179}, - {0x90047, 0x8}, - {0x90048, 0xe0}, - {0x90049, 0x109}, - {0x9004a, 0x0}, - {0x9004b, 0x7c8}, - {0x9004c, 0x109}, - {0x9004d, 0x0}, - {0x9004e, 0x1}, - {0x9004f, 0x8}, - {0x90050, 0x30}, - {0x90051, 0x65a}, - {0x90052, 0x9}, - {0x90053, 0x0}, - {0x90054, 0x45a}, - {0x90055, 0x9}, - {0x90056, 0x0}, - {0x90057, 0x448}, - {0x90058, 0x109}, - {0x90059, 0x40}, - {0x9005a, 0x633}, - {0x9005b, 0x179}, - {0x9005c, 0x1}, - {0x9005d, 0x618}, - {0x9005e, 0x109}, - {0x9005f, 0x40c0}, - {0x90060, 0x633}, - {0x90061, 0x149}, - {0x90062, 0x8}, - {0x90063, 0x4}, - {0x90064, 0x48}, - {0x90065, 0x4040}, - {0x90066, 0x633}, - {0x90067, 0x149}, - {0x90068, 0x0}, - {0x90069, 0x4}, - {0x9006a, 0x48}, - {0x9006b, 0x40}, - {0x9006c, 0x633}, - {0x9006d, 0x149}, - {0x9006e, 0x0}, - {0x9006f, 0x658}, - {0x90070, 0x109}, - {0x90071, 0x10}, - {0x90072, 0x4}, - {0x90073, 0x18}, - {0x90074, 0x0}, - {0x90075, 0x4}, - {0x90076, 0x78}, - {0x90077, 0x549}, - {0x90078, 0x633}, - {0x90079, 0x159}, - {0x9007a, 0xd49}, - {0x9007b, 0x633}, - {0x9007c, 0x159}, - {0x9007d, 0x94a}, - {0x9007e, 0x633}, - {0x9007f, 0x159}, - {0x90080, 0x441}, - {0x90081, 0x633}, - {0x90082, 0x149}, - {0x90083, 0x42}, - {0x90084, 0x633}, - {0x90085, 0x149}, - {0x90086, 0x1}, - {0x90087, 0x633}, - {0x90088, 0x149}, - {0x90089, 0x0}, - {0x9008a, 0xe0}, - {0x9008b, 0x109}, - {0x9008c, 0xa}, - {0x9008d, 0x10}, - {0x9008e, 0x109}, - {0x9008f, 0x9}, - {0x90090, 0x3c0}, - {0x90091, 0x149}, - {0x90092, 0x9}, - {0x90093, 0x3c0}, - {0x90094, 0x159}, - {0x90095, 0x18}, - {0x90096, 0x10}, - {0x90097, 0x109}, - {0x90098, 0x0}, - {0x90099, 0x3c0}, - {0x9009a, 0x109}, - {0x9009b, 0x18}, - {0x9009c, 0x4}, - {0x9009d, 0x48}, - {0x9009e, 0x18}, - {0x9009f, 0x4}, - {0x900a0, 0x58}, - {0x900a1, 0xb}, - {0x900a2, 0x10}, - {0x900a3, 0x109}, - {0x900a4, 0x1}, - {0x900a5, 0x10}, - {0x900a6, 0x109}, - {0x900a7, 0x5}, - {0x900a8, 0x7c0}, - {0x900a9, 0x109}, - {0x40000, 0x811}, - {0x40020, 0x880}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x4008}, - {0x40021, 0x83}, - {0x40041, 0x4f}, - {0x40061, 0x0}, - {0x40002, 0x4040}, - {0x40022, 0x83}, - {0x40042, 0x51}, - {0x40062, 0x0}, - {0x40003, 0x811}, - {0x40023, 0x880}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x720}, - {0x40024, 0xf}, - {0x40044, 0x1740}, - {0x40064, 0x0}, - {0x40005, 0x16}, - {0x40025, 0x83}, - {0x40045, 0x4b}, - {0x40065, 0x0}, - {0x40006, 0x716}, - {0x40026, 0xf}, - {0x40046, 0x2001}, - {0x40066, 0x0}, - {0x40007, 0x716}, - {0x40027, 0xf}, - {0x40047, 0x2800}, - {0x40067, 0x0}, - {0x40008, 0x716}, - {0x40028, 0xf}, - {0x40048, 0xf00}, - {0x40068, 0x0}, - {0x40009, 0x720}, - {0x40029, 0xf}, - {0x40049, 0x1400}, - {0x40069, 0x0}, - {0x4000a, 0xe08}, - {0x4002a, 0xc15}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x625}, - {0x4002b, 0x15}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x4028}, - {0x4002c, 0x80}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0xe08}, - {0x4002d, 0xc1a}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x625}, - {0x4002e, 0x1a}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x4040}, - {0x4002f, 0x80}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x2604}, - {0x40030, 0x15}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x708}, - {0x40031, 0x5}, - {0x40051, 0x0}, - {0x40071, 0x2002}, - {0x40012, 0x8}, - {0x40032, 0x80}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x2604}, - {0x40033, 0x1a}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x708}, - {0x40034, 0xa}, - {0x40054, 0x0}, - {0x40074, 0x2002}, - {0x40015, 0x4040}, - {0x40035, 0x80}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x60a}, - {0x40036, 0x15}, - {0x40056, 0x1200}, - {0x40076, 0x0}, - {0x40017, 0x61a}, - {0x40037, 0x15}, - {0x40057, 0x1300}, - {0x40077, 0x0}, - {0x40018, 0x60a}, - {0x40038, 0x1a}, - {0x40058, 0x1200}, - {0x40078, 0x0}, - {0x40019, 0x642}, - {0x40039, 0x1a}, - {0x40059, 0x1300}, - {0x40079, 0x0}, - {0x4001a, 0x4808}, - {0x4003a, 0x880}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x790}, - {0x900ac, 0x11a}, - {0x900ad, 0x8}, - {0x900ae, 0x7aa}, - {0x900af, 0x2a}, - {0x900b0, 0x10}, - {0x900b1, 0x7b2}, - {0x900b2, 0x2a}, - {0x900b3, 0x0}, - {0x900b4, 0x7c8}, - {0x900b5, 0x109}, - {0x900b6, 0x10}, - {0x900b7, 0x10}, - {0x900b8, 0x109}, - {0x900b9, 0x10}, - {0x900ba, 0x2a8}, - {0x900bb, 0x129}, - {0x900bc, 0x8}, - {0x900bd, 0x370}, - {0x900be, 0x129}, - {0x900bf, 0xa}, - {0x900c0, 0x3c8}, - {0x900c1, 0x1a9}, - {0x900c2, 0xc}, - {0x900c3, 0x408}, - {0x900c4, 0x199}, - {0x900c5, 0x14}, - {0x900c6, 0x790}, - {0x900c7, 0x11a}, - {0x900c8, 0x8}, - {0x900c9, 0x4}, - {0x900ca, 0x18}, - {0x900cb, 0xe}, - {0x900cc, 0x408}, - {0x900cd, 0x199}, - {0x900ce, 0x8}, - {0x900cf, 0x8568}, - {0x900d0, 0x108}, - {0x900d1, 0x18}, - {0x900d2, 0x790}, - {0x900d3, 0x16a}, - {0x900d4, 0x8}, - {0x900d5, 0x1d8}, - {0x900d6, 0x169}, - {0x900d7, 0x10}, - {0x900d8, 0x8558}, - {0x900d9, 0x168}, - {0x900da, 0x1ff8}, - {0x900db, 0x85a8}, - {0x900dc, 0x1e8}, - {0x900dd, 0x50}, - {0x900de, 0x798}, - {0x900df, 0x16a}, - {0x900e0, 0x60}, - {0x900e1, 0x7a0}, - {0x900e2, 0x16a}, - {0x900e3, 0x8}, - {0x900e4, 0x8310}, - {0x900e5, 0x168}, - {0x900e6, 0x8}, - {0x900e7, 0xa310}, - {0x900e8, 0x168}, - {0x900e9, 0xa}, - {0x900ea, 0x408}, - {0x900eb, 0x169}, - {0x900ec, 0x6e}, - {0x900ed, 0x0}, - {0x900ee, 0x68}, - {0x900ef, 0x0}, - {0x900f0, 0x408}, - {0x900f1, 0x169}, - {0x900f2, 0x0}, - {0x900f3, 0x8310}, - {0x900f4, 0x168}, - {0x900f5, 0x0}, - {0x900f6, 0xa310}, - {0x900f7, 0x168}, - {0x900f8, 0x1ff8}, - {0x900f9, 0x85a8}, - {0x900fa, 0x1e8}, - {0x900fb, 0x68}, - {0x900fc, 0x798}, - {0x900fd, 0x16a}, - {0x900fe, 0x78}, - {0x900ff, 0x7a0}, - {0x90100, 0x16a}, - {0x90101, 0x68}, - {0x90102, 0x790}, - {0x90103, 0x16a}, - {0x90104, 0x8}, - {0x90105, 0x8b10}, - {0x90106, 0x168}, - {0x90107, 0x8}, - {0x90108, 0xab10}, - {0x90109, 0x168}, - {0x9010a, 0xa}, - {0x9010b, 0x408}, - {0x9010c, 0x169}, - {0x9010d, 0x58}, - {0x9010e, 0x0}, - {0x9010f, 0x68}, - {0x90110, 0x0}, - {0x90111, 0x408}, - {0x90112, 0x169}, - {0x90113, 0x0}, - {0x90114, 0x8b10}, - {0x90115, 0x168}, - {0x90116, 0x1}, - {0x90117, 0xab10}, - {0x90118, 0x168}, - {0x90119, 0x0}, - {0x9011a, 0x1d8}, - {0x9011b, 0x169}, - {0x9011c, 0x80}, - {0x9011d, 0x790}, - {0x9011e, 0x16a}, - {0x9011f, 0x18}, - {0x90120, 0x7aa}, - {0x90121, 0x6a}, - {0x90122, 0xa}, - {0x90123, 0x0}, - {0x90124, 0x1e9}, - {0x90125, 0x8}, - {0x90126, 0x8080}, - {0x90127, 0x108}, - {0x90128, 0xf}, - {0x90129, 0x408}, - {0x9012a, 0x169}, - {0x9012b, 0xc}, - {0x9012c, 0x0}, - {0x9012d, 0x68}, - {0x9012e, 0x9}, - {0x9012f, 0x0}, - {0x90130, 0x1a9}, - {0x90131, 0x0}, - {0x90132, 0x408}, - {0x90133, 0x169}, - {0x90134, 0x0}, - {0x90135, 0x8080}, - {0x90136, 0x108}, - {0x90137, 0x8}, - {0x90138, 0x7aa}, - {0x90139, 0x6a}, - {0x9013a, 0x0}, - {0x9013b, 0x8568}, - {0x9013c, 0x108}, - {0x9013d, 0xb7}, - {0x9013e, 0x790}, - {0x9013f, 0x16a}, - {0x90140, 0x1f}, - {0x90141, 0x0}, - {0x90142, 0x68}, - {0x90143, 0x8}, - {0x90144, 0x8558}, - {0x90145, 0x168}, - {0x90146, 0xf}, - {0x90147, 0x408}, - {0x90148, 0x169}, - {0x90149, 0xd}, - {0x9014a, 0x0}, - {0x9014b, 0x68}, - {0x9014c, 0x0}, - {0x9014d, 0x408}, - {0x9014e, 0x169}, - {0x9014f, 0x0}, - {0x90150, 0x8558}, - {0x90151, 0x168}, - {0x90152, 0x8}, - {0x90153, 0x3c8}, - {0x90154, 0x1a9}, - {0x90155, 0x3}, - {0x90156, 0x370}, - {0x90157, 0x129}, - {0x90158, 0x20}, - {0x90159, 0x2aa}, - {0x9015a, 0x9}, - {0x9015b, 0x8}, - {0x9015c, 0xe8}, - {0x9015d, 0x109}, - {0x9015e, 0x0}, - {0x9015f, 0x8140}, - {0x90160, 0x10c}, - {0x90161, 0x10}, - {0x90162, 0x8138}, - {0x90163, 0x104}, - {0x90164, 0x8}, - {0x90165, 0x448}, - {0x90166, 0x109}, - {0x90167, 0xf}, - {0x90168, 0x7c0}, - {0x90169, 0x109}, - {0x9016a, 0x0}, - {0x9016b, 0xe8}, - {0x9016c, 0x109}, - {0x9016d, 0x47}, - {0x9016e, 0x630}, - {0x9016f, 0x109}, - {0x90170, 0x8}, - {0x90171, 0x618}, - {0x90172, 0x109}, - {0x90173, 0x8}, - {0x90174, 0xe0}, - {0x90175, 0x109}, - {0x90176, 0x0}, - {0x90177, 0x7c8}, - {0x90178, 0x109}, - {0x90179, 0x8}, - {0x9017a, 0x8140}, - {0x9017b, 0x10c}, - {0x9017c, 0x0}, - {0x9017d, 0x478}, - {0x9017e, 0x109}, - {0x9017f, 0x0}, - {0x90180, 0x1}, - {0x90181, 0x8}, - {0x90182, 0x8}, - {0x90183, 0x4}, - {0x90184, 0x0}, - {0x90006, 0x8}, - {0x90007, 0x7c8}, - {0x90008, 0x109}, - {0x90009, 0x0}, - {0x9000a, 0x400}, - {0x9000b, 0x106}, - {0xd00e7, 0x400}, - {0x90017, 0x0}, - {0x9001f, 0x2b}, - {0x90026, 0x69}, - {0x400d0, 0x0}, - {0x400d1, 0x101}, - {0x400d2, 0x105}, - {0x400d3, 0x107}, - {0x400d4, 0x10f}, - {0x400d5, 0x202}, - {0x400d6, 0x20a}, - {0x400d7, 0x20b}, - {0x2003a, 0x2}, - {0x200be, 0x3}, - {0x2000b, 0x41a}, - {0x2000c, 0xe9}, - {0x2000d, 0x91c}, - {0x2000e, 0x2c}, - {0x12000b, 0x20d}, - {0x12000c, 0x74}, - {0x12000d, 0x48e}, - {0x12000e, 0x2c}, - {0x22000b, 0xb0}, - {0x22000c, 0x27}, - {0x22000d, 0x186}, - {0x22000e, 0x10}, - {0x9000c, 0x0}, - {0x9000d, 0x173}, - {0x9000e, 0x60}, - {0x9000f, 0x6110}, - {0x90010, 0x2152}, - {0x90011, 0xdfbd}, - {0x90012, 0x2060}, - {0x90013, 0x6152}, - {0x20010, 0x5a}, - {0x20011, 0x3}, - {0x120010, 0x5a}, - {0x120011, 0x3}, - {0x40080, 0xe0}, - {0x40081, 0x12}, - {0x40082, 0xe0}, - {0x40083, 0x12}, - {0x40084, 0xe0}, - {0x40085, 0x12}, - {0x140080, 0xe0}, - {0x140081, 0x12}, - {0x140082, 0xe0}, - {0x140083, 0x12}, - {0x140084, 0xe0}, - {0x140085, 0x12}, - {0x240080, 0xe0}, - {0x240081, 0x12}, - {0x240082, 0xe0}, - {0x240083, 0x12}, - {0x240084, 0xe0}, - {0x240085, 0x12}, - {0x400fd, 0xf}, - {0x400f1, 0xe}, - {0x10011, 0x1}, - {0x10012, 0x1}, - {0x10013, 0x180}, - {0x10018, 0x1}, - {0x10002, 0x6209}, - {0x100b2, 0x1}, - {0x101b4, 0x1}, - {0x102b4, 0x1}, - {0x103b4, 0x1}, - {0x104b4, 0x1}, - {0x105b4, 0x1}, - {0x106b4, 0x1}, - {0x107b4, 0x1}, - {0x108b4, 0x1}, - {0x11011, 0x1}, - {0x11012, 0x1}, - {0x11013, 0x180}, - {0x11018, 0x1}, - {0x11002, 0x6209}, - {0x110b2, 0x1}, - {0x111b4, 0x1}, - {0x112b4, 0x1}, - {0x113b4, 0x1}, - {0x114b4, 0x1}, - {0x115b4, 0x1}, - {0x116b4, 0x1}, - {0x117b4, 0x1}, - {0x118b4, 0x1}, - {0x20089, 0x1}, - {0x20088, 0x19}, - {0xc0080, 0x0}, - {0xd0000, 0x1}, -}; - -static struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 3733mts 1D */ - .drate = 3733, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 1866mts 1D */ - .drate = 1866, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 625mts 1D */ - .drate = 625, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 3733mts 2D */ - .drate = 3733, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing_2GB = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3733, 1866, 625, }, - .fsp_cfg = ddr_dram_fsp_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), -}; diff --git a/board/freescale/imx93_frdm/spl.c b/board/freescale/imx93_frdm/spl.c deleted file mode 100644 index 006c752d071..00000000000 --- a/board/freescale/imx93_frdm/spl.c +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2025 NXP - */ - -#include "lpddr4_timing.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define SRC_DDRC_SW_CTRL (0x44461020) -#define SRC_DDRPHY_SINGLE_RESET_SW_CTRL (0x44461424) - -static struct _drams { - u8 mr8; - struct dram_timing_info *pdram_timing; - char *name; -} frdm_drams[2] = { - {0x10, &dram_timing_1GB, "1GB DRAM" }, - {0x18, &dram_timing_2GB, "2GB DRAM" }, -}; - -int spl_board_boot_device(enum boot_device boot_dev_spl) -{ - return BOOT_DEVICE_BOOTROM; -} - -void spl_board_init(void) -{ - int ret; - - ret = ele_start_rng(); - if (ret) - printf("Fail to start RNG: %d\n", ret); - - puts("Normal Boot\n"); -} - -void spl_dram_init(void) -{ - int i; - int ret; - - for (i = 0; i < ARRAY_SIZE(frdm_drams); i++) { - struct dram_timing_info *ptiming = frdm_drams[i].pdram_timing; - - printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate); - ret = ddr_init(ptiming); - if (ret == 0) { - if (lpddr4_mr_read(1, 8) == frdm_drams[i].mr8) { - printf("found DRAM %s matched\n", frdm_drams[i].name); - break; - } - - /* Power down and Power up DDR Mixer */ - - /* Clear PwrOkIn via DDRMIX register */ - setbits_32(SRC_DDRPHY_SINGLE_RESET_SW_CTRL, BIT(0)); - /* Power off the DDRMIX */ - setbits_32(SRC_DDRC_SW_CTRL, BIT(31)); - - udelay(50); - - /* Power up the DDRMIX */ - clrbits_32(SRC_DDRC_SW_CTRL, BIT(31)); - setbits_32(SRC_DDRC_SW_CTRL, BIT(0)); - udelay(10); - clrbits_32(SRC_DDRC_SW_CTRL, BIT(0)); - udelay(10); - } - } -} - -int power_init_board(void) -{ - struct udevice *dev; - int ret; - unsigned int val = 0, buck_val; - - ret = pmic_get("pmic@25", &dev); - if (ret == -ENODEV) { - puts("No pca9450@25\n"); - return 0; - } - if (ret != 0) - return ret; - - /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); - - /* Enable DVS control through PMIC_STBY_REQ */ - pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); - - ret = pmic_reg_read(dev, PCA9450_PWR_CTRL); - if (ret < 0) - return ret; - - val = ret; - - if (is_voltage_mode(VOLT_LOW_DRIVE)) { - buck_val = 0x0c; /* 0.8V for Low drive mode */ - printf("PMIC: Low Drive Voltage Mode\n"); - } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) { - buck_val = 0x10; /* 0.85V for Nominal drive mode */ - printf("PMIC: Nominal Voltage Mode\n"); - } else { - buck_val = 0x14; /* 0.9V for Over drive mode */ - printf("PMIC: Over Drive Voltage Mode\n"); - } - - if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val); - } else { - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4); - } - - /* Set standby voltage to 0.65V */ - if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0); - else - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); - - /* I2C_LT_EN*/ - pmic_reg_write(dev, 0xa, 0x3); - return 0; -} - -void board_init_f(ulong dummy) -{ - int ret; - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - timer_init(); - - arch_cpu_init(); - - board_early_init_f(); - - spl_early_init(); - - preloader_console_init(); - - ret = imx9_probe_mu(); - if (ret) { - printf("Fail to init Sentinel API\n"); - } else { - debug("SOC: 0x%x\n", gd->arch.soc_rev); - debug("LC: 0x%x\n", gd->arch.lifecycle); - } - - clock_init_late(); - - power_init_board(); - - if (!is_voltage_mode(VOLT_LOW_DRIVE)) - set_arm_clk(get_cpu_speed_grade_hz()); - - /* Init power of mix */ - soc_power_init(); - - /* Setup TRDC for DDR access */ - trdc_init(); - - /* DDR initialization */ - spl_dram_init(); - - /* Put M33 into CPUWAIT for following kick */ - ret = m33_prepare(); - if (!ret) - printf("M33 prepare ok\n"); - - board_init_r(NULL, 0); -} diff --git a/board/freescale/imx93_qsb/Kconfig b/board/freescale/imx93_qsb/Kconfig deleted file mode 100644 index fea69c85870..00000000000 --- a/board/freescale/imx93_qsb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_IMX93_9X9_QSB - -config SYS_BOARD - default "imx93_qsb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "imx93_qsb" - -endif diff --git a/board/freescale/imx93_qsb/MAINTAINERS b/board/freescale/imx93_qsb/MAINTAINERS deleted file mode 100644 index a3247d17e7c..00000000000 --- a/board/freescale/imx93_qsb/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -i.MX93 QSB BOARD -M: Peng Fan -S: Maintained -F: board/freescale/imx93_qsb/ -F: include/configs/imx93_qsb.h -F: configs/imx93_9x9_qsb_defconfig -F: configs/imx93_9x9_qsb_inline_ecc_defconfig diff --git a/board/freescale/imx93_qsb/Makefile b/board/freescale/imx93_qsb/Makefile deleted file mode 100644 index c94a6b2279d..00000000000 --- a/board/freescale/imx93_qsb/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright 2024 NXP -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += imx93_qsb.o - -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -ifdef CONFIG_IMX9_DRAM_INLINE_ECC -obj-$(CONFIG_TARGET_IMX93_9X9_QSB) += lpddr4_timing_ecc.o -else -obj-$(CONFIG_TARGET_IMX93_9X9_QSB) += lpddr4_timing.o -endif -endif diff --git a/board/freescale/imx93_qsb/imx93_qsb.c b/board/freescale/imx93_qsb/imx93_qsb.c deleted file mode 100644 index 9de91758aa7..00000000000 --- a/board/freescale/imx93_qsb/imx93_qsb.c +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2024 NXP - */ - -#include -#include -#include - -int board_late_init(void) -{ -#ifdef CONFIG_ENV_IS_IN_MMC - board_late_mmc_env_init(); -#endif - - env_set("sec_boot", "no"); -#ifdef CONFIG_AHAB_BOOT - env_set("sec_boot", "yes"); -#endif - -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - env_set("board_name", "9X9_QSB"); - env_set("board_rev", "iMX93"); -#endif - return 0; -} diff --git a/board/freescale/imx93_qsb/imx93_qsb.env b/board/freescale/imx93_qsb/imx93_qsb.env deleted file mode 100644 index 6c10784cf61..00000000000 --- a/board/freescale/imx93_qsb/imx93_qsb.env +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ - -boot_targets=mmc0 mmc1 -boot_fit=no -bootm_size=0x10000000 -cntr_addr=0x98000000 -cntr_file=os_cntr_signed.bin -console=ttyLP0,115200 earlycon -fdt_addr_r=0x83000000 -fdt_addr=0x83000000 -fdtfile=CONFIG_DEFAULT_FDT_FILE -image=Image -mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX -mmcpart=1 -mmcroot=/dev/mmcblk1p2 rootwait rw -mmcautodetect=yes -mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} -prepare_mcore=setenv mcore_clk clk-imx93.mcore_booted -loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} -loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} -auth_os=auth_cntr ${cntr_addr} -sec_boot=no -boot_os=booti ${loadaddr} - ${fdt_addr_r} -mmcboot= - echo Booting from mmc ...; - run mmcargs; - if test ${sec_boot} = yes; then - if run true; then - run boot_os; - else - echo ERR: failed to authenticate; - fi; - else - if run loadfdt; then - run boot_os; - else - echo WARN: Cannot load the DT; - fi; - fi; -netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs - ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp -netboot= - echo Booting from net ...; - run netargs; - if test ${ip_dyn} = yes; then - setenv get_cmd dhcp; - else - setenv get_cmd tftp; - fi; - if test ${sec_boot} = yes; then - ${get_cmd} ${cntr_addr} ${cntr_file}; - if true; then - run boot_os; - else - echo ERR: failed to authenticate; - fi; - else - ${get_cmd} ${loadaddr} ${image}; - if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then - run boot_os; - else - echo WARN: Cannot load the DT; - fi; - fi; -bsp_bootcmd= - echo Running BSP bootcmd ...; - mmc dev ${mmcdev}; - if mmc rescan; then - if run loadbootscript; then - run bootscript; - else - if test ${sec_boot} = yes; then - if run loadcntr; then - run mmcboot; - else - run netboot; - fi; - else - if run loadimage; then - run mmcboot; - else - run netboot; - fi; - fi; - fi; - fi; -scriptaddr=0x83500000 diff --git a/board/freescale/imx93_qsb/lpddr4_timing.c b/board/freescale/imx93_qsb/lpddr4_timing.c deleted file mode 100644 index c589c165720..00000000000 --- a/board/freescale/imx93_qsb/lpddr4_timing.c +++ /dev/null @@ -1,1995 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright 2024 NXP - * - * Code generated with DDR Tool v3.4.0_8.3-4e2b550a. - * DDR PHY FW2022.01 - */ - -#include -#include - -struct dram_cfg_param ddr_ddrc_cfg[] = { - /** Initialize DDRC registers **/ - {0x4e300110, 0x44100001}, - {0x4e300000, 0x8000ff}, - {0x4e300008, 0x0}, - {0x4e300080, 0x80000512}, - {0x4e300084, 0x0}, - {0x4e300114, 0x1002}, - {0x4e300260, 0x80}, - {0x4e300f04, 0x80}, - {0x4e300800, 0x43b30002}, - {0x4e300804, 0x1f1f1f1f}, - {0x4e301000, 0x0}, - {0x4e301240, 0x0}, - {0x4e301244, 0x0}, - {0x4e301248, 0x0}, - {0x4e30124c, 0x0}, - {0x4e301250, 0x0}, - {0x4e301254, 0x0}, - {0x4e301258, 0x0}, - {0x4e30125c, 0x0}, -}; - -/* dram fsp cfg */ -static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { - { - { - {0x4e300100, 0x1465311B}, - {0x4e300104, 0xF8CC0017}, - {0x4e300108, 0xD4D68E00}, - {0x4e30010C, 0x0071E100}, - {0x4e300124, 0x18660000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x33F00000}, - {0x4e300170, 0x8B0B0608}, - {0x4e300250, 0x00000022}, - {0x4e300254, 0x01280128}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - {0x4e300300, 0x1D441D0D}, - {0x4e300304, 0x01281E10}, - {0x4e300308, 0x0C3C0C34}, - }, - { - {0x01, 0xD4}, - {0x02, 0x2D}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x48}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x02121100}, - {0x4e300104, 0xF866000C}, - {0x4e300108, 0xF2FA8088}, - {0x4e30010C, 0x006101A0}, - {0x4e300124, 0x0C340000}, - {0x4e300160, 0x00009101}, - {0x4e30016C, 0x30700000}, - {0x4e300170, 0x8A0A0508}, - {0x4e300250, 0x00000011}, - {0x4e300254, 0x00900090}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0xA4}, - {0x02, 0x52}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x48}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x00061000}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0x6E62FA48}, - {0x4e30010C, 0x0031010D}, - {0x4e300124, 0x04C50000}, - {0x4e300160, 0x00009100}, - {0x4e30016C, 0x30000000}, - {0x4e300170, 0x89090408}, - {0x4e300250, 0x00000007}, - {0x4e300254, 0x00340034}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0x94}, - {0x02, 0x9}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x48}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 1, - } -}; - -/* PHY Initialize Configuration */ -struct dram_cfg_param ddr_ddrphy_cfg[] = { - {0x100a0, 0x4}, - {0x100a1, 0x5}, - {0x100a2, 0x6}, - {0x100a3, 0x7}, - {0x100a4, 0x0}, - {0x100a5, 0x1}, - {0x100a6, 0x2}, - {0x100a7, 0x3}, - {0x110a0, 0x3}, - {0x110a1, 0x2}, - {0x110a2, 0x0}, - {0x110a3, 0x1}, - {0x110a4, 0x7}, - {0x110a5, 0x6}, - {0x110a6, 0x4}, - {0x110a7, 0x5}, - {0x1005f, 0x1ff}, - {0x1015f, 0x1ff}, - {0x1105f, 0x1ff}, - {0x1115f, 0x1ff}, - {0x11005f, 0x1ff}, - {0x11015f, 0x1ff}, - {0x11105f, 0x1ff}, - {0x11115f, 0x1ff}, - {0x21005f, 0x1ff}, - {0x21015f, 0x1ff}, - {0x21105f, 0x1ff}, - {0x21115f, 0x1ff}, - {0x55, 0x1ff}, - {0x1055, 0x1ff}, - {0x2055, 0x1ff}, - {0x200c5, 0x19}, - {0x1200c5, 0xb}, - {0x2200c5, 0x7}, - {0x2002e, 0x2}, - {0x12002e, 0x1}, - {0x22002e, 0x2}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x1e3}, - {0x2003a, 0x2}, - {0x2007d, 0x212}, - {0x2007c, 0x61}, - {0x120024, 0x1e3}, - {0x2003a, 0x2}, - {0x12007d, 0x212}, - {0x12007c, 0x61}, - {0x220024, 0x1e3}, - {0x2003a, 0x2}, - {0x22007d, 0x212}, - {0x22007c, 0x61}, - {0x20056, 0x3}, - {0x120056, 0x3}, - {0x220056, 0x3}, - {0x1004d, 0x600}, - {0x1014d, 0x600}, - {0x1104d, 0x600}, - {0x1114d, 0x600}, - {0x11004d, 0x600}, - {0x11014d, 0x600}, - {0x11104d, 0x600}, - {0x11114d, 0x600}, - {0x21004d, 0x600}, - {0x21014d, 0x600}, - {0x21104d, 0x600}, - {0x21114d, 0x600}, - {0x10049, 0xe3f}, - {0x10149, 0xe3f}, - {0x11049, 0xe3f}, - {0x11149, 0xe3f}, - {0x110049, 0xe3f}, - {0x110149, 0xe3f}, - {0x111049, 0xe3f}, - {0x111149, 0xe3f}, - {0x210049, 0xe3f}, - {0x210149, 0xe3f}, - {0x211049, 0xe3f}, - {0x211149, 0xe3f}, - {0x43, 0x7f}, - {0x1043, 0x7f}, - {0x2043, 0x7f}, - {0x20018, 0x1}, - {0x20075, 0x4}, - {0x20050, 0x11}, - {0x2009b, 0x2}, - {0x20008, 0x320}, - {0x120008, 0x190}, - {0x220008, 0x9c}, - {0x20088, 0x9}, - {0x200b2, 0x10c}, - {0x10043, 0x5a1}, - {0x10143, 0x5a1}, - {0x11043, 0x5a1}, - {0x11143, 0x5a1}, - {0x1200b2, 0x10c}, - {0x110043, 0x5a1}, - {0x110143, 0x5a1}, - {0x111043, 0x5a1}, - {0x111143, 0x5a1}, - {0x2200b2, 0x10c}, - {0x210043, 0x5a1}, - {0x210143, 0x5a1}, - {0x211043, 0x5a1}, - {0x211143, 0x5a1}, - {0x200fa, 0x2}, - {0x1200fa, 0x2}, - {0x2200fa, 0x2}, - {0x20019, 0x1}, - {0x120019, 0x1}, - {0x220019, 0x1}, - {0x200f0, 0x600}, - {0x200f1, 0x0}, - {0x200f2, 0x4444}, - {0x200f3, 0x8888}, - {0x200f4, 0x5655}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0xf000}, - {0x1004a, 0x500}, - {0x1104a, 0x500}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0x20021, 0x0}, - {0x200c7, 0x21}, - {0x1200c7, 0x21}, - {0x200ca, 0x24}, - {0x1200ca, 0x24}, -}; - -/* PHY trained csr */ -struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - {0x1005f, 0x0}, - {0x1015f, 0x0}, - {0x1105f, 0x0}, - {0x1115f, 0x0}, - {0x11005f, 0x0}, - {0x11015f, 0x0}, - {0x11105f, 0x0}, - {0x11115f, 0x0}, - {0x21005f, 0x0}, - {0x21015f, 0x0}, - {0x21105f, 0x0}, - {0x21115f, 0x0}, - {0x55, 0x0}, - {0x1055, 0x0}, - {0x2055, 0x0}, - {0x200c5, 0x0}, - {0x1200c5, 0x0}, - {0x2200c5, 0x0}, - {0x2002e, 0x0}, - {0x12002e, 0x0}, - {0x22002e, 0x0}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x0}, - {0x2003a, 0x0}, - {0x2007d, 0x0}, - {0x2007c, 0x0}, - {0x120024, 0x0}, - {0x12007d, 0x0}, - {0x12007c, 0x0}, - {0x220024, 0x0}, - {0x22007d, 0x0}, - {0x22007c, 0x0}, - {0x20056, 0x0}, - {0x120056, 0x0}, - {0x220056, 0x0}, - {0x1004d, 0x0}, - {0x1014d, 0x0}, - {0x1104d, 0x0}, - {0x1114d, 0x0}, - {0x11004d, 0x0}, - {0x11014d, 0x0}, - {0x11104d, 0x0}, - {0x11114d, 0x0}, - {0x21004d, 0x0}, - {0x21014d, 0x0}, - {0x21104d, 0x0}, - {0x21114d, 0x0}, - {0x10049, 0x0}, - {0x10149, 0x0}, - {0x11049, 0x0}, - {0x11149, 0x0}, - {0x110049, 0x0}, - {0x110149, 0x0}, - {0x111049, 0x0}, - {0x111149, 0x0}, - {0x210049, 0x0}, - {0x210149, 0x0}, - {0x211049, 0x0}, - {0x211149, 0x0}, - {0x43, 0x0}, - {0x1043, 0x0}, - {0x2043, 0x0}, - {0x20018, 0x0}, - {0x20075, 0x0}, - {0x20050, 0x0}, - {0x2009b, 0x0}, - {0x20008, 0x0}, - {0x120008, 0x0}, - {0x220008, 0x0}, - {0x20088, 0x0}, - {0x200b2, 0x0}, - {0x10043, 0x0}, - {0x10143, 0x0}, - {0x11043, 0x0}, - {0x11143, 0x0}, - {0x1200b2, 0x0}, - {0x110043, 0x0}, - {0x110143, 0x0}, - {0x111043, 0x0}, - {0x111143, 0x0}, - {0x2200b2, 0x0}, - {0x210043, 0x0}, - {0x210143, 0x0}, - {0x211043, 0x0}, - {0x211143, 0x0}, - {0x200fa, 0x0}, - {0x1200fa, 0x0}, - {0x2200fa, 0x0}, - {0x20019, 0x0}, - {0x120019, 0x0}, - {0x220019, 0x0}, - {0x200f0, 0x0}, - {0x200f1, 0x0}, - {0x200f2, 0x0}, - {0x200f3, 0x0}, - {0x200f4, 0x0}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0x0}, - {0x1004a, 0x0}, - {0x1104a, 0x0}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0xd0000, 0x0}, - {0x90000, 0x0}, - {0x90001, 0x0}, - {0x90002, 0x0}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x0}, - {0x90029, 0x0}, - {0x9002a, 0x0}, - {0x9002b, 0x0}, - {0x9002c, 0x0}, - {0x9002d, 0x0}, - {0x9002e, 0x0}, - {0x9002f, 0x0}, - {0x90030, 0x0}, - {0x90031, 0x0}, - {0x90032, 0x0}, - {0x90033, 0x0}, - {0x90034, 0x0}, - {0x90035, 0x0}, - {0x90036, 0x0}, - {0x90037, 0x0}, - {0x90038, 0x0}, - {0x90039, 0x0}, - {0x9003a, 0x0}, - {0x9003b, 0x0}, - {0x9003c, 0x0}, - {0x9003d, 0x0}, - {0x9003e, 0x0}, - {0x9003f, 0x0}, - {0x90040, 0x0}, - {0x90041, 0x0}, - {0x90042, 0x0}, - {0x90043, 0x0}, - {0x90044, 0x0}, - {0x90045, 0x0}, - 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{0x11469, 0x0}, - {0x11568, 0x0}, - {0x11569, 0x0}, - {0x11668, 0x0}, - {0x11669, 0x0}, - {0x11768, 0x0}, - {0x11769, 0x0}, - {0x11868, 0x0}, - {0x11869, 0x0}, - {0x110aa, 0x0}, - {0x11062, 0x0}, - {0x11001, 0x0}, - {0x110a0, 0x0}, - {0x110a1, 0x0}, - {0x110a2, 0x0}, - {0x110a3, 0x0}, - {0x110a4, 0x0}, - {0x110a5, 0x0}, - {0x110a6, 0x0}, - {0x110a7, 0x0}, - {0x80, 0x0}, - {0x1080, 0x0}, - {0x2080, 0x0}, - {0x10020, 0x0}, - {0x10080, 0x0}, - {0x10081, 0x0}, - {0x100d0, 0x0}, - {0x100d1, 0x0}, - {0x1008c, 0x0}, - {0x1008d, 0x0}, - {0x10180, 0x0}, - {0x10181, 0x0}, - {0x101d0, 0x0}, - {0x101d1, 0x0}, - {0x1018c, 0x0}, - {0x1018d, 0x0}, - {0x100c0, 0x0}, - {0x100c1, 0x0}, - {0x101c0, 0x0}, - {0x101c1, 0x0}, - {0x102c0, 0x0}, - {0x102c1, 0x0}, - {0x103c0, 0x0}, - {0x103c1, 0x0}, - {0x104c0, 0x0}, - {0x104c1, 0x0}, - {0x105c0, 0x0}, - {0x105c1, 0x0}, - {0x106c0, 0x0}, - {0x106c1, 0x0}, - {0x107c0, 0x0}, - {0x107c1, 0x0}, - {0x108c0, 0x0}, - {0x108c1, 0x0}, - {0x100ae, 0x0}, - {0x100af, 0x0}, - {0x11020, 0x0}, - {0x11080, 0x0}, - {0x11081, 0x0}, - {0x110d0, 0x0}, - {0x110d1, 0x0}, - {0x1108c, 0x0}, - {0x1108d, 0x0}, - {0x11180, 0x0}, - {0x11181, 0x0}, - {0x111d0, 0x0}, - {0x111d1, 0x0}, - {0x1118c, 0x0}, - {0x1118d, 0x0}, - {0x110c0, 0x0}, - {0x110c1, 0x0}, - {0x111c0, 0x0}, - {0x111c1, 0x0}, - {0x112c0, 0x0}, - {0x112c1, 0x0}, - {0x113c0, 0x0}, - {0x113c1, 0x0}, - {0x114c0, 0x0}, - {0x114c1, 0x0}, - {0x115c0, 0x0}, - {0x115c1, 0x0}, - {0x116c0, 0x0}, - {0x116c1, 0x0}, - {0x117c0, 0x0}, - {0x117c1, 0x0}, - {0x118c0, 0x0}, - {0x118c1, 0x0}, - {0x110ae, 0x0}, - {0x110af, 0x0}, - {0x90201, 0x0}, - {0x90202, 0x0}, - {0x90203, 0x0}, - {0x90205, 0x0}, - {0x90206, 0x0}, - {0x90207, 0x0}, - {0x90208, 0x0}, - {0x20020, 0x0}, - {0x100080, 0x0}, - {0x101080, 0x0}, - {0x102080, 0x0}, - {0x110020, 0x0}, - {0x110080, 0x0}, - {0x110081, 0x0}, - {0x1100d0, 0x0}, - {0x1100d1, 0x0}, - {0x11008c, 0x0}, - {0x11008d, 0x0}, - {0x110180, 0x0}, - {0x110181, 0x0}, - {0x1101d0, 0x0}, - {0x1101d1, 0x0}, - {0x11018c, 0x0}, - {0x11018d, 0x0}, - {0x1100c0, 0x0}, - {0x1100c1, 0x0}, - {0x1101c0, 0x0}, - {0x1101c1, 0x0}, - {0x1102c0, 0x0}, - {0x1102c1, 0x0}, - {0x1103c0, 0x0}, - {0x1103c1, 0x0}, - {0x1104c0, 0x0}, - {0x1104c1, 0x0}, - {0x1105c0, 0x0}, - {0x1105c1, 0x0}, - {0x1106c0, 0x0}, - {0x1106c1, 0x0}, - {0x1107c0, 0x0}, - {0x1107c1, 0x0}, - {0x1108c0, 0x0}, - {0x1108c1, 0x0}, - {0x1100ae, 0x0}, - {0x1100af, 0x0}, - {0x111020, 0x0}, - {0x111080, 0x0}, - {0x111081, 0x0}, - {0x1110d0, 0x0}, - {0x1110d1, 0x0}, - {0x11108c, 0x0}, - {0x11108d, 0x0}, - {0x111180, 0x0}, - {0x111181, 0x0}, - {0x1111d0, 0x0}, - {0x1111d1, 0x0}, - {0x11118c, 0x0}, - {0x11118d, 0x0}, - {0x1110c0, 0x0}, - {0x1110c1, 0x0}, - {0x1111c0, 0x0}, - {0x1111c1, 0x0}, - {0x1112c0, 0x0}, - {0x1112c1, 0x0}, - {0x1113c0, 0x0}, - {0x1113c1, 0x0}, - {0x1114c0, 0x0}, - {0x1114c1, 0x0}, - {0x1115c0, 0x0}, - {0x1115c1, 0x0}, - {0x1116c0, 0x0}, - {0x1116c1, 0x0}, - {0x1117c0, 0x0}, - {0x1117c1, 0x0}, - {0x1118c0, 0x0}, - {0x1118c1, 0x0}, - {0x1110ae, 0x0}, - {0x1110af, 0x0}, - {0x190201, 0x0}, - {0x190202, 0x0}, - {0x190203, 0x0}, - {0x190205, 0x0}, - {0x190206, 0x0}, - {0x190207, 0x0}, - {0x190208, 0x0}, - {0x120020, 0x0}, - {0x200080, 0x0}, - {0x201080, 0x0}, - {0x202080, 0x0}, - {0x210020, 0x0}, - {0x210080, 0x0}, - {0x210081, 0x0}, - {0x2100d0, 0x0}, - {0x2100d1, 0x0}, - {0x21008c, 0x0}, - {0x21008d, 0x0}, - {0x210180, 0x0}, - {0x210181, 0x0}, - {0x2101d0, 0x0}, - {0x2101d1, 0x0}, - {0x21018c, 0x0}, - {0x21018d, 0x0}, - {0x2100c0, 0x0}, - {0x2100c1, 0x0}, - {0x2101c0, 0x0}, - {0x2101c1, 0x0}, - {0x2102c0, 0x0}, - {0x2102c1, 0x0}, - {0x2103c0, 0x0}, - {0x2103c1, 0x0}, - {0x2104c0, 0x0}, - {0x2104c1, 0x0}, - {0x2105c0, 0x0}, - {0x2105c1, 0x0}, - {0x2106c0, 0x0}, - {0x2106c1, 0x0}, - {0x2107c0, 0x0}, - {0x2107c1, 0x0}, - {0x2108c0, 0x0}, - {0x2108c1, 0x0}, - {0x2100ae, 0x0}, - {0x2100af, 0x0}, - {0x211020, 0x0}, - {0x211080, 0x0}, - {0x211081, 0x0}, - {0x2110d0, 0x0}, - {0x2110d1, 0x0}, - {0x21108c, 0x0}, - {0x21108d, 0x0}, - {0x211180, 0x0}, - {0x211181, 0x0}, - {0x2111d0, 0x0}, - {0x2111d1, 0x0}, - {0x21118c, 0x0}, - {0x21118d, 0x0}, - {0x2110c0, 0x0}, - {0x2110c1, 0x0}, - {0x2111c0, 0x0}, - {0x2111c1, 0x0}, - {0x2112c0, 0x0}, - {0x2112c1, 0x0}, - {0x2113c0, 0x0}, - {0x2113c1, 0x0}, - {0x2114c0, 0x0}, - {0x2114c1, 0x0}, - {0x2115c0, 0x0}, - {0x2115c1, 0x0}, - {0x2116c0, 0x0}, - {0x2116c1, 0x0}, - {0x2117c0, 0x0}, - {0x2117c1, 0x0}, - {0x2118c0, 0x0}, - {0x2118c1, 0x0}, - {0x2110ae, 0x0}, - {0x2110af, 0x0}, - {0x290201, 0x0}, - {0x290202, 0x0}, - {0x290203, 0x0}, - {0x290205, 0x0}, - {0x290206, 0x0}, - {0x290207, 0x0}, - {0x290208, 0x0}, - {0x220020, 0x0}, - {0x20077, 0x0}, - {0x20072, 0x0}, - {0x20073, 0x0}, - {0x400c0, 0x0}, - {0x10040, 0x0}, - {0x10140, 0x0}, - {0x10240, 0x0}, - {0x10340, 0x0}, - {0x10440, 0x0}, - {0x10540, 0x0}, - {0x10640, 0x0}, - {0x10740, 0x0}, - {0x10840, 0x0}, - {0x11040, 0x0}, - {0x11140, 0x0}, - {0x11240, 0x0}, - {0x11340, 0x0}, - {0x11440, 0x0}, - {0x11540, 0x0}, - {0x11640, 0x0}, - {0x11740, 0x0}, - {0x11840, 0x0}, -}; - -/* P0 message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp0_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0xc80}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x131f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x2dd4}, - {0x5401a, 0x33}, - {0x5401b, 0x4846}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x2dd4}, - {0x54020, 0x33}, - {0x54021, 0x4846}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xd400}, - {0x54033, 0x332d}, - {0x54034, 0x4600}, - {0x54035, 0x848}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xd400}, - {0x54039, 0x332d}, - {0x5403a, 0x4600}, - {0x5403b, 0x848}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P1 message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp1_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x1}, - {0x54003, 0x640}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x52a4}, - {0x5401a, 0x33}, - {0x5401b, 0x4846}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x52a4}, - {0x54020, 0x33}, - {0x54021, 0x4846}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xa400}, - {0x54033, 0x3352}, - {0x54034, 0x4600}, - {0x54035, 0x848}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xa400}, - {0x54039, 0x3352}, - {0x5403a, 0x4600}, - {0x5403b, 0x848}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P2 message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp2_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x102}, - {0x54003, 0x270}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x994}, - {0x5401a, 0x33}, - {0x5401b, 0x4846}, - {0x5401c, 0x4800}, - {0x5401e, 0x4}, - {0x5401f, 0x994}, - {0x54020, 0x33}, - {0x54021, 0x4846}, - {0x54022, 0x4800}, - {0x54024, 0x4}, - {0x54032, 0x9400}, - {0x54033, 0x3309}, - {0x54034, 0x4600}, - {0x54035, 0x48}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0x9400}, - {0x54039, 0x3309}, - {0x5403a, 0x4600}, - {0x5403b, 0x48}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P0 2D message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0xc80}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x61}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54010, 0x2080}, - {0x54012, 0x110}, - {0x54019, 0x2dd4}, - {0x5401a, 0x33}, - {0x5401b, 0x4846}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x2dd4}, - {0x54020, 0x33}, - {0x54021, 0x4846}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xd400}, - {0x54033, 0x332d}, - {0x54034, 0x4600}, - {0x54035, 0x848}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xd400}, - {0x54039, 0x332d}, - {0x5403a, 0x4600}, - {0x5403b, 0x848}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* DRAM PHY init engine image */ -struct dram_cfg_param ddr_phy_pie[] = { - {0xd0000, 0x0}, - {0x90000, 0x10}, - {0x90001, 0x400}, - {0x90002, 0x10e}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x8}, - {0x90029, 0xb}, - {0x9002a, 0x480}, - {0x9002b, 0x109}, - {0x9002c, 0x8}, - {0x9002d, 0x448}, - {0x9002e, 0x139}, - {0x9002f, 0x8}, - {0x90030, 0x478}, - {0x90031, 0x109}, - {0x90032, 0x0}, - {0x90033, 0xe8}, - {0x90034, 0x109}, - {0x90035, 0x2}, - {0x90036, 0x10}, - {0x90037, 0x139}, - {0x90038, 0xb}, - {0x90039, 0x7c0}, - {0x9003a, 0x139}, - {0x9003b, 0x44}, - {0x9003c, 0x633}, - {0x9003d, 0x159}, - {0x9003e, 0x14f}, - {0x9003f, 0x630}, - {0x90040, 0x159}, - {0x90041, 0x47}, - {0x90042, 0x633}, - {0x90043, 0x149}, - {0x90044, 0x4f}, - {0x90045, 0x633}, - {0x90046, 0x179}, - {0x90047, 0x8}, - {0x90048, 0xe0}, - {0x90049, 0x109}, - {0x9004a, 0x0}, - {0x9004b, 0x7c8}, - {0x9004c, 0x109}, - {0x9004d, 0x0}, - {0x9004e, 0x1}, - {0x9004f, 0x8}, - {0x90050, 0x30}, - {0x90051, 0x65a}, - {0x90052, 0x9}, - {0x90053, 0x0}, - {0x90054, 0x45a}, - {0x90055, 0x9}, - {0x90056, 0x0}, - {0x90057, 0x448}, - {0x90058, 0x109}, - {0x90059, 0x40}, - {0x9005a, 0x633}, - {0x9005b, 0x179}, - {0x9005c, 0x1}, - {0x9005d, 0x618}, - {0x9005e, 0x109}, - {0x9005f, 0x40c0}, - {0x90060, 0x633}, - {0x90061, 0x149}, - {0x90062, 0x8}, - {0x90063, 0x4}, - {0x90064, 0x48}, - {0x90065, 0x4040}, - {0x90066, 0x633}, - {0x90067, 0x149}, - {0x90068, 0x0}, - {0x90069, 0x4}, - {0x9006a, 0x48}, - {0x9006b, 0x40}, - {0x9006c, 0x633}, - {0x9006d, 0x149}, - {0x9006e, 0x0}, - {0x9006f, 0x658}, - {0x90070, 0x109}, - {0x90071, 0x10}, - {0x90072, 0x4}, - {0x90073, 0x18}, - {0x90074, 0x0}, - {0x90075, 0x4}, - {0x90076, 0x78}, - {0x90077, 0x549}, - {0x90078, 0x633}, - {0x90079, 0x159}, - {0x9007a, 0xd49}, - {0x9007b, 0x633}, - {0x9007c, 0x159}, - {0x9007d, 0x94a}, - {0x9007e, 0x633}, - {0x9007f, 0x159}, - {0x90080, 0x441}, - {0x90081, 0x633}, - {0x90082, 0x149}, - {0x90083, 0x42}, - {0x90084, 0x633}, - {0x90085, 0x149}, - {0x90086, 0x1}, - {0x90087, 0x633}, - {0x90088, 0x149}, - {0x90089, 0x0}, - {0x9008a, 0xe0}, - {0x9008b, 0x109}, - {0x9008c, 0xa}, - {0x9008d, 0x10}, - {0x9008e, 0x109}, - {0x9008f, 0x9}, - {0x90090, 0x3c0}, - {0x90091, 0x149}, - {0x90092, 0x9}, - {0x90093, 0x3c0}, - {0x90094, 0x159}, - {0x90095, 0x18}, - {0x90096, 0x10}, - {0x90097, 0x109}, - {0x90098, 0x0}, - {0x90099, 0x3c0}, - {0x9009a, 0x109}, - {0x9009b, 0x18}, - {0x9009c, 0x4}, - {0x9009d, 0x48}, - {0x9009e, 0x18}, - {0x9009f, 0x4}, - {0x900a0, 0x58}, - {0x900a1, 0xb}, - {0x900a2, 0x10}, - {0x900a3, 0x109}, - {0x900a4, 0x1}, - {0x900a5, 0x10}, - {0x900a6, 0x109}, - {0x900a7, 0x5}, - {0x900a8, 0x7c0}, - {0x900a9, 0x109}, - {0x40000, 0x811}, - {0x40020, 0x880}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x4008}, - {0x40021, 0x83}, - {0x40041, 0x4f}, - {0x40061, 0x0}, - {0x40002, 0x4040}, - {0x40022, 0x83}, - {0x40042, 0x51}, - {0x40062, 0x0}, - {0x40003, 0x811}, - {0x40023, 0x880}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x720}, - {0x40024, 0xf}, - {0x40044, 0x1740}, - {0x40064, 0x0}, - {0x40005, 0x16}, - {0x40025, 0x83}, - {0x40045, 0x4b}, - {0x40065, 0x0}, - {0x40006, 0x716}, - {0x40026, 0xf}, - {0x40046, 0x2001}, - {0x40066, 0x0}, - {0x40007, 0x716}, - {0x40027, 0xf}, - {0x40047, 0x2800}, - {0x40067, 0x0}, - {0x40008, 0x716}, - {0x40028, 0xf}, - {0x40048, 0xf00}, - {0x40068, 0x0}, - {0x40009, 0x720}, - {0x40029, 0xf}, - {0x40049, 0x1400}, - {0x40069, 0x0}, - {0x4000a, 0xe08}, - {0x4002a, 0xc15}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x625}, - {0x4002b, 0x15}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x4028}, - {0x4002c, 0x80}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0xe08}, - {0x4002d, 0xc1a}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x625}, - {0x4002e, 0x1a}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x4040}, - {0x4002f, 0x80}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x2604}, - {0x40030, 0x15}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x708}, - {0x40031, 0x5}, - {0x40051, 0x0}, - {0x40071, 0x2002}, - {0x40012, 0x8}, - {0x40032, 0x80}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x2604}, - {0x40033, 0x1a}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x708}, - {0x40034, 0xa}, - {0x40054, 0x0}, - {0x40074, 0x2002}, - {0x40015, 0x4040}, - {0x40035, 0x80}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x60a}, - {0x40036, 0x15}, - {0x40056, 0x1200}, - {0x40076, 0x0}, - {0x40017, 0x61a}, - {0x40037, 0x15}, - {0x40057, 0x1300}, - {0x40077, 0x0}, - {0x40018, 0x60a}, - {0x40038, 0x1a}, - {0x40058, 0x1200}, - {0x40078, 0x0}, - {0x40019, 0x642}, - {0x40039, 0x1a}, - {0x40059, 0x1300}, - {0x40079, 0x0}, - {0x4001a, 0x4808}, - {0x4003a, 0x880}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x790}, - {0x900ac, 0x11a}, - {0x900ad, 0x8}, - {0x900ae, 0x7aa}, - {0x900af, 0x2a}, - {0x900b0, 0x10}, - {0x900b1, 0x7b2}, - {0x900b2, 0x2a}, - {0x900b3, 0x0}, - {0x900b4, 0x7c8}, - {0x900b5, 0x109}, - {0x900b6, 0x10}, - {0x900b7, 0x10}, - {0x900b8, 0x109}, - {0x900b9, 0x10}, - {0x900ba, 0x2a8}, - {0x900bb, 0x129}, - {0x900bc, 0x8}, - {0x900bd, 0x370}, - {0x900be, 0x129}, - {0x900bf, 0xa}, - {0x900c0, 0x3c8}, - {0x900c1, 0x1a9}, - {0x900c2, 0xc}, - {0x900c3, 0x408}, - {0x900c4, 0x199}, - {0x900c5, 0x14}, - {0x900c6, 0x790}, - {0x900c7, 0x11a}, - {0x900c8, 0x8}, - {0x900c9, 0x4}, - {0x900ca, 0x18}, - {0x900cb, 0xe}, - {0x900cc, 0x408}, - {0x900cd, 0x199}, - {0x900ce, 0x8}, - {0x900cf, 0x8568}, - {0x900d0, 0x108}, - {0x900d1, 0x18}, - {0x900d2, 0x790}, - {0x900d3, 0x16a}, - {0x900d4, 0x8}, - {0x900d5, 0x1d8}, - {0x900d6, 0x169}, - {0x900d7, 0x10}, - {0x900d8, 0x8558}, - {0x900d9, 0x168}, - {0x900da, 0x1ff8}, - {0x900db, 0x85a8}, - {0x900dc, 0x1e8}, - {0x900dd, 0x50}, - {0x900de, 0x798}, - {0x900df, 0x16a}, - {0x900e0, 0x60}, - {0x900e1, 0x7a0}, - {0x900e2, 0x16a}, - {0x900e3, 0x8}, - {0x900e4, 0x8310}, - {0x900e5, 0x168}, - {0x900e6, 0x8}, - {0x900e7, 0xa310}, - {0x900e8, 0x168}, - {0x900e9, 0xa}, - {0x900ea, 0x408}, - {0x900eb, 0x169}, - {0x900ec, 0x6e}, - {0x900ed, 0x0}, - {0x900ee, 0x68}, - {0x900ef, 0x0}, - {0x900f0, 0x408}, - {0x900f1, 0x169}, - {0x900f2, 0x0}, - {0x900f3, 0x8310}, - {0x900f4, 0x168}, - {0x900f5, 0x0}, - {0x900f6, 0xa310}, - {0x900f7, 0x168}, - {0x900f8, 0x1ff8}, - {0x900f9, 0x85a8}, - {0x900fa, 0x1e8}, - {0x900fb, 0x68}, - {0x900fc, 0x798}, - {0x900fd, 0x16a}, - {0x900fe, 0x78}, - {0x900ff, 0x7a0}, - {0x90100, 0x16a}, - {0x90101, 0x68}, - {0x90102, 0x790}, - {0x90103, 0x16a}, - {0x90104, 0x8}, - {0x90105, 0x8b10}, - {0x90106, 0x168}, - {0x90107, 0x8}, - {0x90108, 0xab10}, - {0x90109, 0x168}, - {0x9010a, 0xa}, - {0x9010b, 0x408}, - {0x9010c, 0x169}, - {0x9010d, 0x58}, - {0x9010e, 0x0}, - {0x9010f, 0x68}, - {0x90110, 0x0}, - {0x90111, 0x408}, - {0x90112, 0x169}, - {0x90113, 0x0}, - {0x90114, 0x8b10}, - {0x90115, 0x168}, - {0x90116, 0x1}, - {0x90117, 0xab10}, - {0x90118, 0x168}, - {0x90119, 0x0}, - {0x9011a, 0x1d8}, - {0x9011b, 0x169}, - {0x9011c, 0x80}, - {0x9011d, 0x790}, - {0x9011e, 0x16a}, - {0x9011f, 0x18}, - {0x90120, 0x7aa}, - {0x90121, 0x6a}, - {0x90122, 0xa}, - {0x90123, 0x0}, - {0x90124, 0x1e9}, - {0x90125, 0x8}, - {0x90126, 0x8080}, - {0x90127, 0x108}, - {0x90128, 0xf}, - {0x90129, 0x408}, - {0x9012a, 0x169}, - {0x9012b, 0xc}, - {0x9012c, 0x0}, - {0x9012d, 0x68}, - {0x9012e, 0x9}, - {0x9012f, 0x0}, - {0x90130, 0x1a9}, - {0x90131, 0x0}, - {0x90132, 0x408}, - {0x90133, 0x169}, - {0x90134, 0x0}, - {0x90135, 0x8080}, - {0x90136, 0x108}, - {0x90137, 0x8}, - {0x90138, 0x7aa}, - {0x90139, 0x6a}, - {0x9013a, 0x0}, - {0x9013b, 0x8568}, - {0x9013c, 0x108}, - {0x9013d, 0xb7}, - {0x9013e, 0x790}, - {0x9013f, 0x16a}, - {0x90140, 0x1f}, - {0x90141, 0x0}, - {0x90142, 0x68}, - {0x90143, 0x8}, - {0x90144, 0x8558}, - {0x90145, 0x168}, - {0x90146, 0xf}, - {0x90147, 0x408}, - {0x90148, 0x169}, - {0x90149, 0xd}, - {0x9014a, 0x0}, - {0x9014b, 0x68}, - {0x9014c, 0x0}, - {0x9014d, 0x408}, - {0x9014e, 0x169}, - {0x9014f, 0x0}, - {0x90150, 0x8558}, - {0x90151, 0x168}, - {0x90152, 0x8}, - {0x90153, 0x3c8}, - {0x90154, 0x1a9}, - {0x90155, 0x3}, - {0x90156, 0x370}, - {0x90157, 0x129}, - {0x90158, 0x20}, - {0x90159, 0x2aa}, - {0x9015a, 0x9}, - {0x9015b, 0x8}, - {0x9015c, 0xe8}, - {0x9015d, 0x109}, - {0x9015e, 0x0}, - {0x9015f, 0x8140}, - {0x90160, 0x10c}, - {0x90161, 0x10}, - {0x90162, 0x8138}, - {0x90163, 0x104}, - {0x90164, 0x8}, - {0x90165, 0x448}, - {0x90166, 0x109}, - {0x90167, 0xf}, - {0x90168, 0x7c0}, - {0x90169, 0x109}, - {0x9016a, 0x0}, - {0x9016b, 0xe8}, - {0x9016c, 0x109}, - {0x9016d, 0x47}, - {0x9016e, 0x630}, - {0x9016f, 0x109}, - {0x90170, 0x8}, - {0x90171, 0x618}, - {0x90172, 0x109}, - {0x90173, 0x8}, - {0x90174, 0xe0}, - {0x90175, 0x109}, - {0x90176, 0x0}, - {0x90177, 0x7c8}, - {0x90178, 0x109}, - {0x90179, 0x8}, - {0x9017a, 0x8140}, - {0x9017b, 0x10c}, - {0x9017c, 0x0}, - {0x9017d, 0x478}, - {0x9017e, 0x109}, - {0x9017f, 0x0}, - {0x90180, 0x1}, - {0x90181, 0x8}, - {0x90182, 0x8}, - {0x90183, 0x4}, - {0x90184, 0x0}, - {0x90006, 0x8}, - {0x90007, 0x7c8}, - {0x90008, 0x109}, - {0x90009, 0x0}, - {0x9000a, 0x400}, - {0x9000b, 0x106}, - {0xd00e7, 0x400}, - {0x90017, 0x0}, - {0x9001f, 0x2b}, - {0x90026, 0x69}, - {0x400d0, 0x0}, - {0x400d1, 0x101}, - {0x400d2, 0x105}, - {0x400d3, 0x107}, - {0x400d4, 0x10f}, - {0x400d5, 0x202}, - {0x400d6, 0x20a}, - {0x400d7, 0x20b}, - {0x2003a, 0x2}, - {0x200be, 0x3}, - {0x2000b, 0x384}, - {0x2000c, 0xc8}, - {0x2000d, 0x7d0}, - {0x2000e, 0x2c}, - {0x12000b, 0x1c2}, - {0x12000c, 0x64}, - {0x12000d, 0x3e8}, - {0x12000e, 0x2c}, - {0x22000b, 0xb0}, - {0x22000c, 0x27}, - {0x22000d, 0x186}, - {0x22000e, 0x10}, - {0x9000c, 0x0}, - {0x9000d, 0x173}, - {0x9000e, 0x60}, - {0x9000f, 0x6110}, - {0x90010, 0x2152}, - {0x90011, 0xdfbd}, - {0x90012, 0x2060}, - {0x90013, 0x6152}, - {0x20010, 0x5a}, - {0x20011, 0x3}, - {0x120010, 0x5a}, - {0x120011, 0x3}, - {0x40080, 0xe0}, - {0x40081, 0x12}, - {0x40082, 0xe0}, - {0x40083, 0x12}, - {0x40084, 0xe0}, - {0x40085, 0x12}, - {0x140080, 0xe0}, - {0x140081, 0x12}, - {0x140082, 0xe0}, - {0x140083, 0x12}, - {0x140084, 0xe0}, - {0x140085, 0x12}, - {0x240080, 0xe0}, - {0x240081, 0x12}, - {0x240082, 0xe0}, - {0x240083, 0x12}, - {0x240084, 0xe0}, - {0x240085, 0x12}, - {0x400fd, 0xf}, - {0x400f1, 0xe}, - {0x10011, 0x1}, - {0x10012, 0x1}, - {0x10013, 0x180}, - {0x10018, 0x1}, - {0x10002, 0x6209}, - {0x100b2, 0x1}, - {0x101b4, 0x1}, - {0x102b4, 0x1}, - {0x103b4, 0x1}, - {0x104b4, 0x1}, - {0x105b4, 0x1}, - {0x106b4, 0x1}, - {0x107b4, 0x1}, - {0x108b4, 0x1}, - {0x11011, 0x1}, - {0x11012, 0x1}, - {0x11013, 0x180}, - {0x11018, 0x1}, - {0x11002, 0x6209}, - {0x110b2, 0x1}, - {0x111b4, 0x1}, - {0x112b4, 0x1}, - {0x113b4, 0x1}, - {0x114b4, 0x1}, - {0x115b4, 0x1}, - {0x116b4, 0x1}, - {0x117b4, 0x1}, - {0x118b4, 0x1}, - {0x20089, 0x1}, - {0x20088, 0x19}, - {0xc0080, 0x0}, - {0xd0000, 0x1}, -}; - -struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 3200mts 1D */ - .drate = 3200, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 1600mts 1D */ - .drate = 1600, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 625mts 1D */ - .drate = 625, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 3200mts 2D */ - .drate = 3200, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3200, 1600, 625, }, - .fsp_cfg = ddr_dram_fsp_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), -}; diff --git a/board/freescale/imx93_qsb/lpddr4_timing_ecc.c b/board/freescale/imx93_qsb/lpddr4_timing_ecc.c deleted file mode 100644 index 60cd4908f4a..00000000000 --- a/board/freescale/imx93_qsb/lpddr4_timing_ecc.c +++ /dev/null @@ -1,1995 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright 2024 NXP - * - * Code generated with DDR Tool v3.4.0_8.3-4e2b550a. - * DDR PHY FW2022.01 - */ - -#include -#include - -struct dram_cfg_param ddr_ddrc_cfg[] = { - /* Initialize DDRC registers */ - {0x4e300110, 0x44100001}, - {0x4e300000, 0x8000ef}, - {0x4e300008, 0x0}, - {0x4e300080, 0x80000512}, - {0x4e300084, 0x0}, - {0x4e300114, 0x1012}, - {0x4e300260, 0x80}, - {0x4e300f04, 0x80}, - {0x4e300800, 0x43b30d00}, - {0x4e300804, 0x1f1f1f1f}, - {0x4e301000, 0xc0000000}, - {0x4e301240, 0x0}, - {0x4e301244, 0x0}, - {0x4e301248, 0x0}, - {0x4e30124c, 0x0}, - {0x4e301250, 0x0}, - {0x4e301254, 0x0}, - {0x4e301258, 0x0}, - {0x4e30125c, 0x0}, -}; - -/* dram fsp cfg */ -static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { - { - { - {0x4e300100, 0x1465311B}, - {0x4e300104, 0xF8CC0017}, - {0x4e300108, 0xD4D68E00}, - {0x4e30010C, 0x0071E100}, - {0x4e300124, 0x18660000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x33F00000}, - {0x4e300170, 0x8B0B0608}, - {0x4e300250, 0x00000022}, - {0x4e300254, 0x01280128}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - {0x4e300300, 0x1D441D0D}, - {0x4e300304, 0x01281E10}, - {0x4e300308, 0x0C3C0C34}, - }, - { - {0x01, 0xD4}, - {0x02, 0x2D}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x48}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x02121100}, - {0x4e300104, 0xF866000C}, - {0x4e300108, 0xF2FA8088}, - {0x4e30010C, 0x006101A0}, - {0x4e300124, 0x0C340000}, - {0x4e300160, 0x00009101}, - {0x4e30016C, 0x30700000}, - {0x4e300170, 0x8A0A0508}, - {0x4e300250, 0x00000011}, - {0x4e300254, 0x00900090}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0xA4}, - {0x02, 0x52}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x48}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x00061000}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0x6E62FA48}, - {0x4e30010C, 0x0031010D}, - {0x4e300124, 0x04C50000}, - {0x4e300160, 0x00009100}, - {0x4e30016C, 0x30000000}, - {0x4e300170, 0x89090408}, - {0x4e300250, 0x00000007}, - {0x4e300254, 0x00340034}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0x94}, - {0x02, 0x9}, - {0x03, 0x33}, - {0x0b, 0x46}, - {0x0c, 0x48}, - {0x0e, 0x48}, - {0x16, 0x04}, - }, - 1, - } -}; - -/* PHY Initialize Configuration */ -struct dram_cfg_param ddr_ddrphy_cfg[] = { - {0x100a0, 0x4}, - {0x100a1, 0x5}, - {0x100a2, 0x6}, - {0x100a3, 0x7}, - {0x100a4, 0x0}, - {0x100a5, 0x1}, - {0x100a6, 0x2}, - {0x100a7, 0x3}, - {0x110a0, 0x3}, - {0x110a1, 0x2}, - {0x110a2, 0x0}, - {0x110a3, 0x1}, - {0x110a4, 0x7}, - {0x110a5, 0x6}, - {0x110a6, 0x4}, - {0x110a7, 0x5}, - {0x1005f, 0x1ff}, - {0x1015f, 0x1ff}, - {0x1105f, 0x1ff}, - {0x1115f, 0x1ff}, - {0x11005f, 0x1ff}, - {0x11015f, 0x1ff}, - {0x11105f, 0x1ff}, - {0x11115f, 0x1ff}, - {0x21005f, 0x1ff}, - {0x21015f, 0x1ff}, - {0x21105f, 0x1ff}, - {0x21115f, 0x1ff}, - {0x55, 0x1ff}, - {0x1055, 0x1ff}, - {0x2055, 0x1ff}, - {0x200c5, 0x19}, - {0x1200c5, 0xb}, - {0x2200c5, 0x7}, - {0x2002e, 0x2}, - {0x12002e, 0x1}, - {0x22002e, 0x2}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x1e3}, - {0x2003a, 0x2}, - {0x2007d, 0x212}, - {0x2007c, 0x61}, - {0x120024, 0x1e3}, - {0x2003a, 0x2}, - {0x12007d, 0x212}, - {0x12007c, 0x61}, - {0x220024, 0x1e3}, - {0x2003a, 0x2}, - {0x22007d, 0x212}, - {0x22007c, 0x61}, - {0x20056, 0x3}, - {0x120056, 0x3}, - {0x220056, 0x3}, - {0x1004d, 0x600}, - {0x1014d, 0x600}, - {0x1104d, 0x600}, - {0x1114d, 0x600}, - {0x11004d, 0x600}, - {0x11014d, 0x600}, - {0x11104d, 0x600}, - {0x11114d, 0x600}, - {0x21004d, 0x600}, - {0x21014d, 0x600}, - {0x21104d, 0x600}, - {0x21114d, 0x600}, - {0x10049, 0xe3f}, - {0x10149, 0xe3f}, - {0x11049, 0xe3f}, - {0x11149, 0xe3f}, - {0x110049, 0xe3f}, - {0x110149, 0xe3f}, - {0x111049, 0xe3f}, - {0x111149, 0xe3f}, - {0x210049, 0xe3f}, - {0x210149, 0xe3f}, - {0x211049, 0xe3f}, - {0x211149, 0xe3f}, - {0x43, 0x7f}, - {0x1043, 0x7f}, - {0x2043, 0x7f}, - {0x20018, 0x1}, - {0x20075, 0x4}, - {0x20050, 0x11}, - {0x2009b, 0x2}, - {0x20008, 0x320}, - {0x120008, 0x190}, - {0x220008, 0x9c}, - {0x20088, 0x9}, - {0x200b2, 0x10c}, - {0x10043, 0x5a1}, - {0x10143, 0x5a1}, - {0x11043, 0x5a1}, - {0x11143, 0x5a1}, - {0x1200b2, 0x10c}, - {0x110043, 0x5a1}, - {0x110143, 0x5a1}, - {0x111043, 0x5a1}, - {0x111143, 0x5a1}, - {0x2200b2, 0x10c}, - {0x210043, 0x5a1}, - {0x210143, 0x5a1}, - {0x211043, 0x5a1}, - {0x211143, 0x5a1}, - {0x200fa, 0x2}, - {0x1200fa, 0x2}, - {0x2200fa, 0x2}, - {0x20019, 0x1}, - {0x120019, 0x1}, - {0x220019, 0x1}, - {0x200f0, 0x600}, - {0x200f1, 0x0}, - {0x200f2, 0x4444}, - {0x200f3, 0x8888}, - {0x200f4, 0x5655}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0xf000}, - {0x1004a, 0x500}, - {0x1104a, 0x500}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0x20021, 0x0}, - {0x200c7, 0x21}, - {0x1200c7, 0x21}, - {0x200ca, 0x24}, - {0x1200ca, 0x24}, -}; - -/* PHY trained csr */ -struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - {0x1005f, 0x0}, - {0x1015f, 0x0}, - {0x1105f, 0x0}, - {0x1115f, 0x0}, - {0x11005f, 0x0}, - {0x11015f, 0x0}, - {0x11105f, 0x0}, - {0x11115f, 0x0}, - {0x21005f, 0x0}, - {0x21015f, 0x0}, - {0x21105f, 0x0}, - {0x21115f, 0x0}, - {0x55, 0x0}, - {0x1055, 0x0}, - {0x2055, 0x0}, - {0x200c5, 0x0}, - {0x1200c5, 0x0}, - {0x2200c5, 0x0}, - {0x2002e, 0x0}, - {0x12002e, 0x0}, - {0x22002e, 0x0}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x0}, - {0x2003a, 0x0}, - {0x2007d, 0x0}, - {0x2007c, 0x0}, - {0x120024, 0x0}, - {0x12007d, 0x0}, - {0x12007c, 0x0}, - {0x220024, 0x0}, - {0x22007d, 0x0}, - {0x22007c, 0x0}, - {0x20056, 0x0}, - {0x120056, 0x0}, - {0x220056, 0x0}, - {0x1004d, 0x0}, - {0x1014d, 0x0}, - {0x1104d, 0x0}, - {0x1114d, 0x0}, - {0x11004d, 0x0}, - {0x11014d, 0x0}, - {0x11104d, 0x0}, - {0x11114d, 0x0}, - {0x21004d, 0x0}, - {0x21014d, 0x0}, - {0x21104d, 0x0}, - {0x21114d, 0x0}, - {0x10049, 0x0}, - {0x10149, 0x0}, - {0x11049, 0x0}, - {0x11149, 0x0}, - {0x110049, 0x0}, - {0x110149, 0x0}, - {0x111049, 0x0}, - {0x111149, 0x0}, - {0x210049, 0x0}, - {0x210149, 0x0}, - {0x211049, 0x0}, - {0x211149, 0x0}, - {0x43, 0x0}, - {0x1043, 0x0}, - {0x2043, 0x0}, - {0x20018, 0x0}, - {0x20075, 0x0}, - {0x20050, 0x0}, - {0x2009b, 0x0}, - {0x20008, 0x0}, - {0x120008, 0x0}, - {0x220008, 0x0}, - {0x20088, 0x0}, - {0x200b2, 0x0}, - {0x10043, 0x0}, - {0x10143, 0x0}, - {0x11043, 0x0}, - {0x11143, 0x0}, - {0x1200b2, 0x0}, - {0x110043, 0x0}, - {0x110143, 0x0}, - {0x111043, 0x0}, - {0x111143, 0x0}, - {0x2200b2, 0x0}, - {0x210043, 0x0}, - {0x210143, 0x0}, - {0x211043, 0x0}, - {0x211143, 0x0}, - {0x200fa, 0x0}, - {0x1200fa, 0x0}, - {0x2200fa, 0x0}, - {0x20019, 0x0}, - {0x120019, 0x0}, - {0x220019, 0x0}, - {0x200f0, 0x0}, - {0x200f1, 0x0}, - {0x200f2, 0x0}, - {0x200f3, 0x0}, - {0x200f4, 0x0}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0x0}, - {0x1004a, 0x0}, - {0x1104a, 0x0}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0xd0000, 0x0}, - {0x90000, 0x0}, - {0x90001, 0x0}, - {0x90002, 0x0}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x0}, - {0x90029, 0x0}, - {0x9002a, 0x0}, - {0x9002b, 0x0}, - {0x9002c, 0x0}, - {0x9002d, 0x0}, - {0x9002e, 0x0}, - {0x9002f, 0x0}, - {0x90030, 0x0}, - {0x90031, 0x0}, - {0x90032, 0x0}, - {0x90033, 0x0}, - {0x90034, 0x0}, - {0x90035, 0x0}, - {0x90036, 0x0}, - {0x90037, 0x0}, - {0x90038, 0x0}, - {0x90039, 0x0}, - {0x9003a, 0x0}, - {0x9003b, 0x0}, - {0x9003c, 0x0}, - {0x9003d, 0x0}, - {0x9003e, 0x0}, - {0x9003f, 0x0}, - {0x90040, 0x0}, - {0x90041, 0x0}, - {0x90042, 0x0}, - {0x90043, 0x0}, - {0x90044, 0x0}, - {0x90045, 0x0}, - {0x90046, 0x0}, - {0x90047, 0x0}, - {0x90048, 0x0}, - {0x90049, 0x0}, - {0x9004a, 0x0}, - {0x9004b, 0x0}, - {0x9004c, 0x0}, - {0x9004d, 0x0}, - {0x9004e, 0x0}, - {0x9004f, 0x0}, - {0x90050, 0x0}, - {0x90051, 0x0}, - {0x90052, 0x0}, - {0x90053, 0x0}, - {0x90054, 0x0}, - {0x90055, 0x0}, - {0x90056, 0x0}, - {0x90057, 0x0}, - {0x90058, 0x0}, - {0x90059, 0x0}, - {0x9005a, 0x0}, - {0x9005b, 0x0}, - {0x9005c, 0x0}, - {0x9005d, 0x0}, - {0x9005e, 0x0}, - {0x9005f, 0x0}, - {0x90060, 0x0}, - {0x90061, 0x0}, - {0x90062, 0x0}, - {0x90063, 0x0}, - {0x90064, 0x0}, - {0x90065, 0x0}, - {0x90066, 0x0}, - {0x90067, 0x0}, - {0x90068, 0x0}, - {0x90069, 0x0}, - {0x9006a, 0x0}, - {0x9006b, 0x0}, - {0x9006c, 0x0}, - {0x9006d, 0x0}, - {0x9006e, 0x0}, - {0x9006f, 0x0}, - {0x90070, 0x0}, - {0x90071, 0x0}, - {0x90072, 0x0}, - {0x90073, 0x0}, - {0x90074, 0x0}, - {0x90075, 0x0}, - {0x90076, 0x0}, - {0x90077, 0x0}, - {0x90078, 0x0}, - {0x90079, 0x0}, - {0x9007a, 0x0}, - {0x9007b, 0x0}, - {0x9007c, 0x0}, - {0x9007d, 0x0}, - {0x9007e, 0x0}, - {0x9007f, 0x0}, - {0x90080, 0x0}, - {0x90081, 0x0}, - {0x90082, 0x0}, - {0x90083, 0x0}, - {0x90084, 0x0}, - {0x90085, 0x0}, - {0x90086, 0x0}, - {0x90087, 0x0}, - {0x90088, 0x0}, - {0x90089, 0x0}, - {0x9008a, 0x0}, - {0x9008b, 0x0}, - {0x9008c, 0x0}, - {0x9008d, 0x0}, - {0x9008e, 0x0}, - {0x9008f, 0x0}, - {0x90090, 0x0}, - {0x90091, 0x0}, - {0x90092, 0x0}, - {0x90093, 0x0}, - {0x90094, 0x0}, - {0x90095, 0x0}, - {0x90096, 0x0}, - {0x90097, 0x0}, - {0x90098, 0x0}, - {0x90099, 0x0}, - {0x9009a, 0x0}, - {0x9009b, 0x0}, - {0x9009c, 0x0}, - {0x9009d, 0x0}, - {0x9009e, 0x0}, - {0x9009f, 0x0}, - {0x900a0, 0x0}, - {0x900a1, 0x0}, - {0x900a2, 0x0}, - {0x900a3, 0x0}, - {0x900a4, 0x0}, - {0x900a5, 0x0}, - {0x900a6, 0x0}, - {0x900a7, 0x0}, - {0x900a8, 0x0}, - {0x900a9, 0x0}, - {0x40000, 0x0}, - {0x40020, 0x0}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x0}, - {0x40021, 0x0}, - {0x40041, 0x0}, - {0x40061, 0x0}, - {0x40002, 0x0}, - {0x40022, 0x0}, - {0x40042, 0x0}, - {0x40062, 0x0}, - {0x40003, 0x0}, - {0x40023, 0x0}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x0}, - {0x40024, 0x0}, - {0x40044, 0x0}, - {0x40064, 0x0}, - {0x40005, 0x0}, - {0x40025, 0x0}, - {0x40045, 0x0}, - {0x40065, 0x0}, - {0x40006, 0x0}, - {0x40026, 0x0}, - {0x40046, 0x0}, - {0x40066, 0x0}, - {0x40007, 0x0}, - {0x40027, 0x0}, - {0x40047, 0x0}, - {0x40067, 0x0}, - {0x40008, 0x0}, - {0x40028, 0x0}, - {0x40048, 0x0}, - {0x40068, 0x0}, - {0x40009, 0x0}, - {0x40029, 0x0}, - {0x40049, 0x0}, - {0x40069, 0x0}, - {0x4000a, 0x0}, - {0x4002a, 0x0}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x0}, - {0x4002b, 0x0}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x0}, - {0x4002c, 0x0}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0x0}, - {0x4002d, 0x0}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x0}, - {0x4002e, 0x0}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x0}, - {0x4002f, 0x0}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x0}, - {0x40030, 0x0}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x0}, - {0x40031, 0x0}, - {0x40051, 0x0}, - {0x40071, 0x0}, - {0x40012, 0x0}, - {0x40032, 0x0}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x0}, - {0x40033, 0x0}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x0}, - {0x40034, 0x0}, - {0x40054, 0x0}, - {0x40074, 0x0}, - {0x40015, 0x0}, - {0x40035, 0x0}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x0}, - {0x40036, 0x0}, - {0x40056, 0x0}, - {0x40076, 0x0}, - {0x40017, 0x0}, - {0x40037, 0x0}, - {0x40057, 0x0}, - {0x40077, 0x0}, - {0x40018, 0x0}, - {0x40038, 0x0}, - {0x40058, 0x0}, - {0x40078, 0x0}, - {0x40019, 0x0}, - {0x40039, 0x0}, - {0x40059, 0x0}, - {0x40079, 0x0}, - {0x4001a, 0x0}, - {0x4003a, 0x0}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x0}, - {0x900ac, 0x0}, - {0x900ad, 0x0}, - {0x900ae, 0x0}, - {0x900af, 0x0}, - {0x900b0, 0x0}, - {0x900b1, 0x0}, - {0x900b2, 0x0}, - {0x900b3, 0x0}, - {0x900b4, 0x0}, - {0x900b5, 0x0}, - {0x900b6, 0x0}, - {0x900b7, 0x0}, - {0x900b8, 0x0}, - {0x900b9, 0x0}, - {0x900ba, 0x0}, - {0x900bb, 0x0}, - {0x900bc, 0x0}, - {0x900bd, 0x0}, - {0x900be, 0x0}, - {0x900bf, 0x0}, - {0x900c0, 0x0}, - {0x900c1, 0x0}, - {0x900c2, 0x0}, - {0x900c3, 0x0}, - {0x900c4, 0x0}, - {0x900c5, 0x0}, - {0x900c6, 0x0}, - {0x900c7, 0x0}, - {0x900c8, 0x0}, - {0x900c9, 0x0}, - {0x900ca, 0x0}, - {0x900cb, 0x0}, - {0x900cc, 0x0}, - {0x900cd, 0x0}, - {0x900ce, 0x0}, - {0x900cf, 0x0}, - {0x900d0, 0x0}, - {0x900d1, 0x0}, - {0x900d2, 0x0}, - {0x900d3, 0x0}, - {0x900d4, 0x0}, - {0x900d5, 0x0}, - {0x900d6, 0x0}, - {0x900d7, 0x0}, - {0x900d8, 0x0}, - {0x900d9, 0x0}, - {0x900da, 0x0}, - {0x900db, 0x0}, - {0x900dc, 0x0}, - {0x900dd, 0x0}, - {0x900de, 0x0}, - {0x900df, 0x0}, - {0x900e0, 0x0}, - {0x900e1, 0x0}, - {0x900e2, 0x0}, - {0x900e3, 0x0}, - {0x900e4, 0x0}, - {0x900e5, 0x0}, - {0x900e6, 0x0}, - {0x900e7, 0x0}, - {0x900e8, 0x0}, - {0x900e9, 0x0}, - {0x900ea, 0x0}, - {0x900eb, 0x0}, - {0x900ec, 0x0}, - {0x900ed, 0x0}, - {0x900ee, 0x0}, - {0x900ef, 0x0}, - {0x900f0, 0x0}, - {0x900f1, 0x0}, - {0x900f2, 0x0}, - {0x900f3, 0x0}, - {0x900f4, 0x0}, - {0x900f5, 0x0}, - {0x900f6, 0x0}, - {0x900f7, 0x0}, - {0x900f8, 0x0}, - {0x900f9, 0x0}, - {0x900fa, 0x0}, - {0x900fb, 0x0}, - {0x900fc, 0x0}, - {0x900fd, 0x0}, - {0x900fe, 0x0}, - {0x900ff, 0x0}, - {0x90100, 0x0}, - {0x90101, 0x0}, - {0x90102, 0x0}, - {0x90103, 0x0}, - {0x90104, 0x0}, - {0x90105, 0x0}, - {0x90106, 0x0}, - {0x90107, 0x0}, - {0x90108, 0x0}, - {0x90109, 0x0}, - {0x9010a, 0x0}, - {0x9010b, 0x0}, - {0x9010c, 0x0}, - {0x9010d, 0x0}, - {0x9010e, 0x0}, - {0x9010f, 0x0}, - {0x90110, 0x0}, - {0x90111, 0x0}, - {0x90112, 0x0}, - {0x90113, 0x0}, - {0x90114, 0x0}, - {0x90115, 0x0}, - {0x90116, 0x0}, - {0x90117, 0x0}, - {0x90118, 0x0}, - {0x90119, 0x0}, - {0x9011a, 0x0}, - {0x9011b, 0x0}, - {0x9011c, 0x0}, - {0x9011d, 0x0}, - {0x9011e, 0x0}, - {0x9011f, 0x0}, - {0x90120, 0x0}, - {0x90121, 0x0}, - {0x90122, 0x0}, - {0x90123, 0x0}, - {0x90124, 0x0}, - {0x90125, 0x0}, - {0x90126, 0x0}, - {0x90127, 0x0}, - {0x90128, 0x0}, - {0x90129, 0x0}, - {0x9012a, 0x0}, - {0x9012b, 0x0}, - {0x9012c, 0x0}, - {0x9012d, 0x0}, - {0x9012e, 0x0}, - {0x9012f, 0x0}, - {0x90130, 0x0}, - {0x90131, 0x0}, - {0x90132, 0x0}, - {0x90133, 0x0}, - {0x90134, 0x0}, - {0x90135, 0x0}, - {0x90136, 0x0}, - {0x90137, 0x0}, - {0x90138, 0x0}, - {0x90139, 0x0}, - {0x9013a, 0x0}, - {0x9013b, 0x0}, - {0x9013c, 0x0}, - {0x9013d, 0x0}, - {0x9013e, 0x0}, - {0x9013f, 0x0}, - {0x90140, 0x0}, - {0x90141, 0x0}, - {0x90142, 0x0}, - {0x90143, 0x0}, - {0x90144, 0x0}, - {0x90145, 0x0}, - {0x90146, 0x0}, - {0x90147, 0x0}, - {0x90148, 0x0}, - {0x90149, 0x0}, - {0x9014a, 0x0}, - {0x9014b, 0x0}, - {0x9014c, 0x0}, - {0x9014d, 0x0}, - {0x9014e, 0x0}, - {0x9014f, 0x0}, - {0x90150, 0x0}, - {0x90151, 0x0}, - {0x90152, 0x0}, - {0x90153, 0x0}, - {0x90154, 0x0}, - {0x90155, 0x0}, - {0x90156, 0x0}, - {0x90157, 0x0}, - {0x90158, 0x0}, - {0x90159, 0x0}, - {0x9015a, 0x0}, - {0x9015b, 0x0}, - {0x9015c, 0x0}, - {0x9015d, 0x0}, - {0x9015e, 0x0}, - {0x9015f, 0x0}, - {0x90160, 0x0}, - {0x90161, 0x0}, - {0x90162, 0x0}, - {0x90163, 0x0}, - {0x90164, 0x0}, - {0x90165, 0x0}, - {0x90166, 0x0}, - {0x90167, 0x0}, - {0x90168, 0x0}, - {0x90169, 0x0}, - {0x9016a, 0x0}, - {0x9016b, 0x0}, - {0x9016c, 0x0}, - {0x9016d, 0x0}, - {0x9016e, 0x0}, - {0x9016f, 0x0}, - {0x90170, 0x0}, - {0x90171, 0x0}, - {0x90172, 0x0}, - {0x90173, 0x0}, - {0x90174, 0x0}, - {0x90175, 0x0}, - {0x90176, 0x0}, - {0x90177, 0x0}, - {0x90178, 0x0}, - {0x90179, 0x0}, - {0x9017a, 0x0}, - {0x9017b, 0x0}, - {0x9017c, 0x0}, - {0x9017d, 0x0}, - {0x9017e, 0x0}, - {0x9017f, 0x0}, - {0x90180, 0x0}, - {0x90181, 0x0}, - {0x90182, 0x0}, - {0x90183, 0x0}, - {0x90184, 0x0}, - {0x90006, 0x0}, - {0x90007, 0x0}, - {0x90008, 0x0}, - {0x90009, 0x0}, - {0x9000a, 0x0}, - {0x9000b, 0x0}, - {0xd00e7, 0x0}, - {0x90017, 0x0}, - {0x9001f, 0x0}, - {0x90026, 0x0}, - {0x400d0, 0x0}, - {0x400d1, 0x0}, - {0x400d2, 0x0}, - {0x400d3, 0x0}, - {0x400d4, 0x0}, - {0x400d5, 0x0}, - {0x400d6, 0x0}, - {0x400d7, 0x0}, - {0x200be, 0x0}, - {0x2000b, 0x0}, - {0x2000c, 0x0}, - {0x2000d, 0x0}, - {0x2000e, 0x0}, - {0x12000b, 0x0}, - {0x12000c, 0x0}, - {0x12000d, 0x0}, - {0x12000e, 0x0}, - {0x22000b, 0x0}, - {0x22000c, 0x0}, - {0x22000d, 0x0}, - {0x22000e, 0x0}, - {0x9000c, 0x0}, - {0x9000d, 0x0}, - {0x9000e, 0x0}, - {0x9000f, 0x0}, - {0x90010, 0x0}, - {0x90011, 0x0}, - {0x90012, 0x0}, - {0x90013, 0x0}, - {0x20010, 0x0}, - {0x20011, 0x0}, - {0x120010, 0x0}, - {0x120011, 0x0}, - {0x40080, 0x0}, - {0x40081, 0x0}, - {0x40082, 0x0}, - {0x40083, 0x0}, - {0x40084, 0x0}, - {0x40085, 0x0}, - {0x140080, 0x0}, - {0x140081, 0x0}, - {0x140082, 0x0}, - {0x140083, 0x0}, - {0x140084, 0x0}, - {0x140085, 0x0}, - {0x240080, 0x0}, - {0x240081, 0x0}, - {0x240082, 0x0}, - {0x240083, 0x0}, - {0x240084, 0x0}, - {0x240085, 0x0}, - {0x400fd, 0x0}, - {0x400f1, 0x0}, - {0x10011, 0x0}, - {0x10012, 0x0}, - {0x10013, 0x0}, - {0x10018, 0x0}, - {0x10002, 0x0}, - {0x100b2, 0x0}, - {0x101b4, 0x0}, - {0x102b4, 0x0}, - {0x103b4, 0x0}, - {0x104b4, 0x0}, - {0x105b4, 0x0}, - {0x106b4, 0x0}, - {0x107b4, 0x0}, - {0x108b4, 0x0}, - {0x11011, 0x0}, - {0x11012, 0x0}, - {0x11013, 0x0}, - {0x11018, 0x0}, - {0x11002, 0x0}, - {0x110b2, 0x0}, - {0x111b4, 0x0}, - {0x112b4, 0x0}, - {0x113b4, 0x0}, - {0x114b4, 0x0}, - {0x115b4, 0x0}, - {0x116b4, 0x0}, - {0x117b4, 0x0}, - {0x118b4, 0x0}, - {0x20089, 0x0}, - {0xc0080, 0x0}, - {0x200cb, 0x0}, - {0x10068, 0x0}, - {0x10069, 0x0}, - {0x10168, 0x0}, - {0x10169, 0x0}, - {0x10268, 0x0}, - {0x10269, 0x0}, - {0x10368, 0x0}, - {0x10369, 0x0}, - {0x10468, 0x0}, - {0x10469, 0x0}, - {0x10568, 0x0}, - {0x10569, 0x0}, - {0x10668, 0x0}, - {0x10669, 0x0}, - {0x10768, 0x0}, - {0x10769, 0x0}, - {0x10868, 0x0}, - {0x10869, 0x0}, - {0x100aa, 0x0}, - {0x10062, 0x0}, - {0x10001, 0x0}, - {0x100a0, 0x0}, - {0x100a1, 0x0}, - {0x100a2, 0x0}, - {0x100a3, 0x0}, - {0x100a4, 0x0}, - {0x100a5, 0x0}, - {0x100a6, 0x0}, - {0x100a7, 0x0}, - {0x11068, 0x0}, - {0x11069, 0x0}, - {0x11168, 0x0}, - {0x11169, 0x0}, - {0x11268, 0x0}, - {0x11269, 0x0}, - {0x11368, 0x0}, - {0x11369, 0x0}, - {0x11468, 0x0}, - {0x11469, 0x0}, - {0x11568, 0x0}, - {0x11569, 0x0}, - {0x11668, 0x0}, - {0x11669, 0x0}, - {0x11768, 0x0}, - {0x11769, 0x0}, - {0x11868, 0x0}, - {0x11869, 0x0}, - {0x110aa, 0x0}, - {0x11062, 0x0}, - {0x11001, 0x0}, - {0x110a0, 0x0}, - {0x110a1, 0x0}, - {0x110a2, 0x0}, - {0x110a3, 0x0}, - {0x110a4, 0x0}, - {0x110a5, 0x0}, - {0x110a6, 0x0}, - {0x110a7, 0x0}, - {0x80, 0x0}, - {0x1080, 0x0}, - {0x2080, 0x0}, - {0x10020, 0x0}, - {0x10080, 0x0}, - {0x10081, 0x0}, - {0x100d0, 0x0}, - {0x100d1, 0x0}, - {0x1008c, 0x0}, - {0x1008d, 0x0}, - {0x10180, 0x0}, - {0x10181, 0x0}, - {0x101d0, 0x0}, - {0x101d1, 0x0}, - {0x1018c, 0x0}, - {0x1018d, 0x0}, - {0x100c0, 0x0}, - {0x100c1, 0x0}, - {0x101c0, 0x0}, - {0x101c1, 0x0}, - {0x102c0, 0x0}, - {0x102c1, 0x0}, - {0x103c0, 0x0}, - {0x103c1, 0x0}, - {0x104c0, 0x0}, - {0x104c1, 0x0}, - {0x105c0, 0x0}, - {0x105c1, 0x0}, - {0x106c0, 0x0}, - {0x106c1, 0x0}, - {0x107c0, 0x0}, - {0x107c1, 0x0}, - {0x108c0, 0x0}, - {0x108c1, 0x0}, - {0x100ae, 0x0}, - {0x100af, 0x0}, - {0x11020, 0x0}, - {0x11080, 0x0}, - {0x11081, 0x0}, - {0x110d0, 0x0}, - {0x110d1, 0x0}, - {0x1108c, 0x0}, - {0x1108d, 0x0}, - {0x11180, 0x0}, - {0x11181, 0x0}, - {0x111d0, 0x0}, - {0x111d1, 0x0}, - {0x1118c, 0x0}, - {0x1118d, 0x0}, - {0x110c0, 0x0}, - {0x110c1, 0x0}, - {0x111c0, 0x0}, - {0x111c1, 0x0}, - {0x112c0, 0x0}, - {0x112c1, 0x0}, - {0x113c0, 0x0}, - {0x113c1, 0x0}, - {0x114c0, 0x0}, - {0x114c1, 0x0}, - {0x115c0, 0x0}, - {0x115c1, 0x0}, - {0x116c0, 0x0}, - {0x116c1, 0x0}, - {0x117c0, 0x0}, - {0x117c1, 0x0}, - {0x118c0, 0x0}, - {0x118c1, 0x0}, - {0x110ae, 0x0}, - {0x110af, 0x0}, - {0x90201, 0x0}, - {0x90202, 0x0}, - {0x90203, 0x0}, - {0x90205, 0x0}, - {0x90206, 0x0}, - {0x90207, 0x0}, - {0x90208, 0x0}, - {0x20020, 0x0}, - {0x100080, 0x0}, - {0x101080, 0x0}, - {0x102080, 0x0}, - {0x110020, 0x0}, - {0x110080, 0x0}, - {0x110081, 0x0}, - {0x1100d0, 0x0}, - {0x1100d1, 0x0}, - {0x11008c, 0x0}, - {0x11008d, 0x0}, - {0x110180, 0x0}, - {0x110181, 0x0}, - {0x1101d0, 0x0}, - {0x1101d1, 0x0}, - {0x11018c, 0x0}, - {0x11018d, 0x0}, - {0x1100c0, 0x0}, - {0x1100c1, 0x0}, - {0x1101c0, 0x0}, - {0x1101c1, 0x0}, - {0x1102c0, 0x0}, - {0x1102c1, 0x0}, - {0x1103c0, 0x0}, - {0x1103c1, 0x0}, - {0x1104c0, 0x0}, - {0x1104c1, 0x0}, - {0x1105c0, 0x0}, - {0x1105c1, 0x0}, - {0x1106c0, 0x0}, - {0x1106c1, 0x0}, - {0x1107c0, 0x0}, - {0x1107c1, 0x0}, - {0x1108c0, 0x0}, - {0x1108c1, 0x0}, - {0x1100ae, 0x0}, - {0x1100af, 0x0}, - {0x111020, 0x0}, - {0x111080, 0x0}, - {0x111081, 0x0}, - {0x1110d0, 0x0}, - {0x1110d1, 0x0}, - {0x11108c, 0x0}, - {0x11108d, 0x0}, - {0x111180, 0x0}, - {0x111181, 0x0}, - {0x1111d0, 0x0}, - {0x1111d1, 0x0}, - {0x11118c, 0x0}, - {0x11118d, 0x0}, - {0x1110c0, 0x0}, - {0x1110c1, 0x0}, - {0x1111c0, 0x0}, - {0x1111c1, 0x0}, - {0x1112c0, 0x0}, - {0x1112c1, 0x0}, - {0x1113c0, 0x0}, - {0x1113c1, 0x0}, - {0x1114c0, 0x0}, - {0x1114c1, 0x0}, - {0x1115c0, 0x0}, - {0x1115c1, 0x0}, - {0x1116c0, 0x0}, - {0x1116c1, 0x0}, - {0x1117c0, 0x0}, - {0x1117c1, 0x0}, - {0x1118c0, 0x0}, - {0x1118c1, 0x0}, - {0x1110ae, 0x0}, - {0x1110af, 0x0}, - {0x190201, 0x0}, - {0x190202, 0x0}, - {0x190203, 0x0}, - {0x190205, 0x0}, - {0x190206, 0x0}, - {0x190207, 0x0}, - {0x190208, 0x0}, - {0x120020, 0x0}, - {0x200080, 0x0}, - {0x201080, 0x0}, - {0x202080, 0x0}, - {0x210020, 0x0}, - {0x210080, 0x0}, - {0x210081, 0x0}, - {0x2100d0, 0x0}, - {0x2100d1, 0x0}, - {0x21008c, 0x0}, - {0x21008d, 0x0}, - {0x210180, 0x0}, - {0x210181, 0x0}, - {0x2101d0, 0x0}, - {0x2101d1, 0x0}, - {0x21018c, 0x0}, - {0x21018d, 0x0}, - {0x2100c0, 0x0}, - {0x2100c1, 0x0}, - {0x2101c0, 0x0}, - {0x2101c1, 0x0}, - {0x2102c0, 0x0}, - {0x2102c1, 0x0}, - {0x2103c0, 0x0}, - {0x2103c1, 0x0}, - {0x2104c0, 0x0}, - {0x2104c1, 0x0}, - {0x2105c0, 0x0}, - {0x2105c1, 0x0}, - {0x2106c0, 0x0}, - {0x2106c1, 0x0}, - {0x2107c0, 0x0}, - {0x2107c1, 0x0}, - {0x2108c0, 0x0}, - {0x2108c1, 0x0}, - {0x2100ae, 0x0}, - {0x2100af, 0x0}, - {0x211020, 0x0}, - {0x211080, 0x0}, - {0x211081, 0x0}, - {0x2110d0, 0x0}, - {0x2110d1, 0x0}, - {0x21108c, 0x0}, - {0x21108d, 0x0}, - {0x211180, 0x0}, - {0x211181, 0x0}, - {0x2111d0, 0x0}, - {0x2111d1, 0x0}, - {0x21118c, 0x0}, - {0x21118d, 0x0}, - {0x2110c0, 0x0}, - {0x2110c1, 0x0}, - {0x2111c0, 0x0}, - {0x2111c1, 0x0}, - {0x2112c0, 0x0}, - {0x2112c1, 0x0}, - {0x2113c0, 0x0}, - {0x2113c1, 0x0}, - {0x2114c0, 0x0}, - {0x2114c1, 0x0}, - {0x2115c0, 0x0}, - {0x2115c1, 0x0}, - {0x2116c0, 0x0}, - {0x2116c1, 0x0}, - {0x2117c0, 0x0}, - {0x2117c1, 0x0}, - {0x2118c0, 0x0}, - {0x2118c1, 0x0}, - {0x2110ae, 0x0}, - {0x2110af, 0x0}, - {0x290201, 0x0}, - {0x290202, 0x0}, - {0x290203, 0x0}, - {0x290205, 0x0}, - {0x290206, 0x0}, - {0x290207, 0x0}, - {0x290208, 0x0}, - {0x220020, 0x0}, - {0x20077, 0x0}, - {0x20072, 0x0}, - {0x20073, 0x0}, - {0x400c0, 0x0}, - {0x10040, 0x0}, - {0x10140, 0x0}, - {0x10240, 0x0}, - {0x10340, 0x0}, - {0x10440, 0x0}, - {0x10540, 0x0}, - {0x10640, 0x0}, - {0x10740, 0x0}, - {0x10840, 0x0}, - {0x11040, 0x0}, - {0x11140, 0x0}, - {0x11240, 0x0}, - {0x11340, 0x0}, - {0x11440, 0x0}, - {0x11540, 0x0}, - {0x11640, 0x0}, - {0x11740, 0x0}, - {0x11840, 0x0}, -}; - -/* P0 message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp0_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0xc80}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x131f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x2dd4}, - {0x5401a, 0x33}, - {0x5401b, 0x4846}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x2dd4}, - {0x54020, 0x33}, - {0x54021, 0x4846}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xd400}, - {0x54033, 0x332d}, - {0x54034, 0x4600}, - {0x54035, 0x848}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xd400}, - {0x54039, 0x332d}, - {0x5403a, 0x4600}, - {0x5403b, 0x848}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P1 message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp1_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x1}, - {0x54003, 0x640}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x52a4}, - {0x5401a, 0x33}, - {0x5401b, 0x4846}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x52a4}, - {0x54020, 0x33}, - {0x54021, 0x4846}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xa400}, - {0x54033, 0x3352}, - {0x54034, 0x4600}, - {0x54035, 0x848}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xa400}, - {0x54039, 0x3352}, - {0x5403a, 0x4600}, - {0x5403b, 0x848}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P2 message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp2_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x102}, - {0x54003, 0x270}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x994}, - {0x5401a, 0x33}, - {0x5401b, 0x4846}, - {0x5401c, 0x4800}, - {0x5401e, 0x4}, - {0x5401f, 0x994}, - {0x54020, 0x33}, - {0x54021, 0x4846}, - {0x54022, 0x4800}, - {0x54024, 0x4}, - {0x54032, 0x9400}, - {0x54033, 0x3309}, - {0x54034, 0x4600}, - {0x54035, 0x48}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0x9400}, - {0x54039, 0x3309}, - {0x5403a, 0x4600}, - {0x5403b, 0x48}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P0 2D message block parameter for training firmware */ -struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0xc80}, - {0x54004, 0x4}, - {0x54006, 0x15}, - {0x54008, 0x61}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54010, 0x2080}, - {0x54012, 0x110}, - {0x54019, 0x2dd4}, - {0x5401a, 0x33}, - {0x5401b, 0x4846}, - {0x5401c, 0x4808}, - {0x5401e, 0x4}, - {0x5401f, 0x2dd4}, - {0x54020, 0x33}, - {0x54021, 0x4846}, - {0x54022, 0x4808}, - {0x54024, 0x4}, - {0x54032, 0xd400}, - {0x54033, 0x332d}, - {0x54034, 0x4600}, - {0x54035, 0x848}, - {0x54036, 0x48}, - {0x54037, 0x400}, - {0x54038, 0xd400}, - {0x54039, 0x332d}, - {0x5403a, 0x4600}, - {0x5403b, 0x848}, - {0x5403c, 0x48}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* DRAM PHY init engine image */ -struct dram_cfg_param ddr_phy_pie[] = { - {0xd0000, 0x0}, - {0x90000, 0x10}, - {0x90001, 0x400}, - {0x90002, 0x10e}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x8}, - {0x90029, 0xb}, - {0x9002a, 0x480}, - {0x9002b, 0x109}, - {0x9002c, 0x8}, - {0x9002d, 0x448}, - {0x9002e, 0x139}, - {0x9002f, 0x8}, - {0x90030, 0x478}, - {0x90031, 0x109}, - {0x90032, 0x0}, - {0x90033, 0xe8}, - {0x90034, 0x109}, - {0x90035, 0x2}, - {0x90036, 0x10}, - {0x90037, 0x139}, - {0x90038, 0xb}, - {0x90039, 0x7c0}, - {0x9003a, 0x139}, - {0x9003b, 0x44}, - {0x9003c, 0x633}, - {0x9003d, 0x159}, - {0x9003e, 0x14f}, - {0x9003f, 0x630}, - {0x90040, 0x159}, - {0x90041, 0x47}, - {0x90042, 0x633}, - {0x90043, 0x149}, - {0x90044, 0x4f}, - {0x90045, 0x633}, - {0x90046, 0x179}, - {0x90047, 0x8}, - {0x90048, 0xe0}, - {0x90049, 0x109}, - {0x9004a, 0x0}, - {0x9004b, 0x7c8}, - {0x9004c, 0x109}, - {0x9004d, 0x0}, - {0x9004e, 0x1}, - {0x9004f, 0x8}, - {0x90050, 0x30}, - {0x90051, 0x65a}, - {0x90052, 0x9}, - {0x90053, 0x0}, - {0x90054, 0x45a}, - {0x90055, 0x9}, - {0x90056, 0x0}, - {0x90057, 0x448}, - {0x90058, 0x109}, - {0x90059, 0x40}, - {0x9005a, 0x633}, - {0x9005b, 0x179}, - {0x9005c, 0x1}, - {0x9005d, 0x618}, - {0x9005e, 0x109}, - {0x9005f, 0x40c0}, - {0x90060, 0x633}, - {0x90061, 0x149}, - {0x90062, 0x8}, - {0x90063, 0x4}, - {0x90064, 0x48}, - {0x90065, 0x4040}, - {0x90066, 0x633}, - {0x90067, 0x149}, - {0x90068, 0x0}, - {0x90069, 0x4}, - {0x9006a, 0x48}, - {0x9006b, 0x40}, - {0x9006c, 0x633}, - {0x9006d, 0x149}, - {0x9006e, 0x0}, - {0x9006f, 0x658}, - {0x90070, 0x109}, - {0x90071, 0x10}, - {0x90072, 0x4}, - {0x90073, 0x18}, - {0x90074, 0x0}, - {0x90075, 0x4}, - {0x90076, 0x78}, - {0x90077, 0x549}, - {0x90078, 0x633}, - {0x90079, 0x159}, - {0x9007a, 0xd49}, - {0x9007b, 0x633}, - {0x9007c, 0x159}, - {0x9007d, 0x94a}, - {0x9007e, 0x633}, - {0x9007f, 0x159}, - {0x90080, 0x441}, - {0x90081, 0x633}, - {0x90082, 0x149}, - {0x90083, 0x42}, - {0x90084, 0x633}, - {0x90085, 0x149}, - {0x90086, 0x1}, - {0x90087, 0x633}, - {0x90088, 0x149}, - {0x90089, 0x0}, - {0x9008a, 0xe0}, - {0x9008b, 0x109}, - {0x9008c, 0xa}, - {0x9008d, 0x10}, - {0x9008e, 0x109}, - {0x9008f, 0x9}, - {0x90090, 0x3c0}, - {0x90091, 0x149}, - {0x90092, 0x9}, - {0x90093, 0x3c0}, - {0x90094, 0x159}, - {0x90095, 0x18}, - {0x90096, 0x10}, - {0x90097, 0x109}, - {0x90098, 0x0}, - {0x90099, 0x3c0}, - {0x9009a, 0x109}, - {0x9009b, 0x18}, - {0x9009c, 0x4}, - {0x9009d, 0x48}, - {0x9009e, 0x18}, - {0x9009f, 0x4}, - {0x900a0, 0x58}, - {0x900a1, 0xb}, - {0x900a2, 0x10}, - {0x900a3, 0x109}, - {0x900a4, 0x1}, - {0x900a5, 0x10}, - {0x900a6, 0x109}, - {0x900a7, 0x5}, - {0x900a8, 0x7c0}, - {0x900a9, 0x109}, - {0x40000, 0x811}, - {0x40020, 0x880}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x4008}, - {0x40021, 0x83}, - {0x40041, 0x4f}, - {0x40061, 0x0}, - {0x40002, 0x4040}, - {0x40022, 0x83}, - {0x40042, 0x51}, - {0x40062, 0x0}, - {0x40003, 0x811}, - {0x40023, 0x880}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x720}, - {0x40024, 0xf}, - {0x40044, 0x1740}, - {0x40064, 0x0}, - {0x40005, 0x16}, - {0x40025, 0x83}, - {0x40045, 0x4b}, - {0x40065, 0x0}, - {0x40006, 0x716}, - {0x40026, 0xf}, - {0x40046, 0x2001}, - {0x40066, 0x0}, - {0x40007, 0x716}, - {0x40027, 0xf}, - {0x40047, 0x2800}, - {0x40067, 0x0}, - {0x40008, 0x716}, - {0x40028, 0xf}, - {0x40048, 0xf00}, - {0x40068, 0x0}, - {0x40009, 0x720}, - {0x40029, 0xf}, - {0x40049, 0x1400}, - {0x40069, 0x0}, - {0x4000a, 0xe08}, - {0x4002a, 0xc15}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x625}, - {0x4002b, 0x15}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x4028}, - {0x4002c, 0x80}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0xe08}, - {0x4002d, 0xc1a}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x625}, - {0x4002e, 0x1a}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x4040}, - {0x4002f, 0x80}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x2604}, - {0x40030, 0x15}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x708}, - {0x40031, 0x5}, - {0x40051, 0x0}, - {0x40071, 0x2002}, - {0x40012, 0x8}, - {0x40032, 0x80}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x2604}, - {0x40033, 0x1a}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x708}, - {0x40034, 0xa}, - {0x40054, 0x0}, - {0x40074, 0x2002}, - {0x40015, 0x4040}, - {0x40035, 0x80}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x60a}, - {0x40036, 0x15}, - {0x40056, 0x1200}, - {0x40076, 0x0}, - {0x40017, 0x61a}, - {0x40037, 0x15}, - {0x40057, 0x1300}, - {0x40077, 0x0}, - {0x40018, 0x60a}, - {0x40038, 0x1a}, - {0x40058, 0x1200}, - {0x40078, 0x0}, - {0x40019, 0x642}, - {0x40039, 0x1a}, - {0x40059, 0x1300}, - {0x40079, 0x0}, - {0x4001a, 0x4808}, - {0x4003a, 0x880}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x790}, - {0x900ac, 0x11a}, - {0x900ad, 0x8}, - {0x900ae, 0x7aa}, - {0x900af, 0x2a}, - {0x900b0, 0x10}, - {0x900b1, 0x7b2}, - {0x900b2, 0x2a}, - {0x900b3, 0x0}, - {0x900b4, 0x7c8}, - {0x900b5, 0x109}, - {0x900b6, 0x10}, - {0x900b7, 0x10}, - {0x900b8, 0x109}, - {0x900b9, 0x10}, - {0x900ba, 0x2a8}, - {0x900bb, 0x129}, - {0x900bc, 0x8}, - {0x900bd, 0x370}, - {0x900be, 0x129}, - {0x900bf, 0xa}, - {0x900c0, 0x3c8}, - {0x900c1, 0x1a9}, - {0x900c2, 0xc}, - {0x900c3, 0x408}, - {0x900c4, 0x199}, - {0x900c5, 0x14}, - {0x900c6, 0x790}, - {0x900c7, 0x11a}, - {0x900c8, 0x8}, - {0x900c9, 0x4}, - {0x900ca, 0x18}, - {0x900cb, 0xe}, - {0x900cc, 0x408}, - {0x900cd, 0x199}, - {0x900ce, 0x8}, - {0x900cf, 0x8568}, - {0x900d0, 0x108}, - {0x900d1, 0x18}, - {0x900d2, 0x790}, - {0x900d3, 0x16a}, - {0x900d4, 0x8}, - {0x900d5, 0x1d8}, - {0x900d6, 0x169}, - {0x900d7, 0x10}, - {0x900d8, 0x8558}, - {0x900d9, 0x168}, - {0x900da, 0x1ff8}, - {0x900db, 0x85a8}, - {0x900dc, 0x1e8}, - {0x900dd, 0x50}, - {0x900de, 0x798}, - {0x900df, 0x16a}, - {0x900e0, 0x60}, - {0x900e1, 0x7a0}, - {0x900e2, 0x16a}, - {0x900e3, 0x8}, - {0x900e4, 0x8310}, - {0x900e5, 0x168}, - {0x900e6, 0x8}, - {0x900e7, 0xa310}, - {0x900e8, 0x168}, - {0x900e9, 0xa}, - {0x900ea, 0x408}, - {0x900eb, 0x169}, - {0x900ec, 0x6e}, - {0x900ed, 0x0}, - {0x900ee, 0x68}, - {0x900ef, 0x0}, - {0x900f0, 0x408}, - {0x900f1, 0x169}, - {0x900f2, 0x0}, - {0x900f3, 0x8310}, - {0x900f4, 0x168}, - {0x900f5, 0x0}, - {0x900f6, 0xa310}, - {0x900f7, 0x168}, - {0x900f8, 0x1ff8}, - {0x900f9, 0x85a8}, - {0x900fa, 0x1e8}, - {0x900fb, 0x68}, - {0x900fc, 0x798}, - {0x900fd, 0x16a}, - {0x900fe, 0x78}, - {0x900ff, 0x7a0}, - {0x90100, 0x16a}, - {0x90101, 0x68}, - {0x90102, 0x790}, - {0x90103, 0x16a}, - {0x90104, 0x8}, - {0x90105, 0x8b10}, - {0x90106, 0x168}, - {0x90107, 0x8}, - {0x90108, 0xab10}, - {0x90109, 0x168}, - {0x9010a, 0xa}, - {0x9010b, 0x408}, - {0x9010c, 0x169}, - {0x9010d, 0x58}, - {0x9010e, 0x0}, - {0x9010f, 0x68}, - {0x90110, 0x0}, - {0x90111, 0x408}, - {0x90112, 0x169}, - {0x90113, 0x0}, - {0x90114, 0x8b10}, - {0x90115, 0x168}, - {0x90116, 0x1}, - {0x90117, 0xab10}, - {0x90118, 0x168}, - {0x90119, 0x0}, - {0x9011a, 0x1d8}, - {0x9011b, 0x169}, - {0x9011c, 0x80}, - {0x9011d, 0x790}, - {0x9011e, 0x16a}, - {0x9011f, 0x18}, - {0x90120, 0x7aa}, - {0x90121, 0x6a}, - {0x90122, 0xa}, - {0x90123, 0x0}, - {0x90124, 0x1e9}, - {0x90125, 0x8}, - {0x90126, 0x8080}, - {0x90127, 0x108}, - {0x90128, 0xf}, - {0x90129, 0x408}, - {0x9012a, 0x169}, - {0x9012b, 0xc}, - {0x9012c, 0x0}, - {0x9012d, 0x68}, - {0x9012e, 0x9}, - {0x9012f, 0x0}, - {0x90130, 0x1a9}, - {0x90131, 0x0}, - {0x90132, 0x408}, - {0x90133, 0x169}, - {0x90134, 0x0}, - {0x90135, 0x8080}, - {0x90136, 0x108}, - {0x90137, 0x8}, - {0x90138, 0x7aa}, - {0x90139, 0x6a}, - {0x9013a, 0x0}, - {0x9013b, 0x8568}, - {0x9013c, 0x108}, - {0x9013d, 0xb7}, - {0x9013e, 0x790}, - {0x9013f, 0x16a}, - {0x90140, 0x1f}, - {0x90141, 0x0}, - {0x90142, 0x68}, - {0x90143, 0x8}, - {0x90144, 0x8558}, - {0x90145, 0x168}, - {0x90146, 0xf}, - {0x90147, 0x408}, - {0x90148, 0x169}, - {0x90149, 0xd}, - {0x9014a, 0x0}, - {0x9014b, 0x68}, - {0x9014c, 0x0}, - {0x9014d, 0x408}, - {0x9014e, 0x169}, - {0x9014f, 0x0}, - {0x90150, 0x8558}, - {0x90151, 0x168}, - {0x90152, 0x8}, - {0x90153, 0x3c8}, - {0x90154, 0x1a9}, - {0x90155, 0x3}, - {0x90156, 0x370}, - {0x90157, 0x129}, - {0x90158, 0x20}, - {0x90159, 0x2aa}, - {0x9015a, 0x9}, - {0x9015b, 0x8}, - {0x9015c, 0xe8}, - {0x9015d, 0x109}, - {0x9015e, 0x0}, - {0x9015f, 0x8140}, - {0x90160, 0x10c}, - {0x90161, 0x10}, - {0x90162, 0x8138}, - {0x90163, 0x104}, - {0x90164, 0x8}, - {0x90165, 0x448}, - {0x90166, 0x109}, - {0x90167, 0xf}, - {0x90168, 0x7c0}, - {0x90169, 0x109}, - {0x9016a, 0x0}, - {0x9016b, 0xe8}, - {0x9016c, 0x109}, - {0x9016d, 0x47}, - {0x9016e, 0x630}, - {0x9016f, 0x109}, - {0x90170, 0x8}, - {0x90171, 0x618}, - {0x90172, 0x109}, - {0x90173, 0x8}, - {0x90174, 0xe0}, - {0x90175, 0x109}, - {0x90176, 0x0}, - {0x90177, 0x7c8}, - {0x90178, 0x109}, - {0x90179, 0x8}, - {0x9017a, 0x8140}, - {0x9017b, 0x10c}, - {0x9017c, 0x0}, - {0x9017d, 0x478}, - {0x9017e, 0x109}, - {0x9017f, 0x0}, - {0x90180, 0x1}, - {0x90181, 0x8}, - {0x90182, 0x8}, - {0x90183, 0x4}, - {0x90184, 0x0}, - {0x90006, 0x8}, - {0x90007, 0x7c8}, - {0x90008, 0x109}, - {0x90009, 0x0}, - {0x9000a, 0x400}, - {0x9000b, 0x106}, - {0xd00e7, 0x400}, - {0x90017, 0x0}, - {0x9001f, 0x2b}, - {0x90026, 0x69}, - {0x400d0, 0x0}, - {0x400d1, 0x101}, - {0x400d2, 0x105}, - {0x400d3, 0x107}, - {0x400d4, 0x10f}, - {0x400d5, 0x202}, - {0x400d6, 0x20a}, - {0x400d7, 0x20b}, - {0x2003a, 0x2}, - {0x200be, 0x3}, - {0x2000b, 0x384}, - {0x2000c, 0xc8}, - {0x2000d, 0x7d0}, - {0x2000e, 0x2c}, - {0x12000b, 0x1c2}, - {0x12000c, 0x64}, - {0x12000d, 0x3e8}, - {0x12000e, 0x2c}, - {0x22000b, 0xb0}, - {0x22000c, 0x27}, - {0x22000d, 0x186}, - {0x22000e, 0x10}, - {0x9000c, 0x0}, - {0x9000d, 0x173}, - {0x9000e, 0x60}, - {0x9000f, 0x6110}, - {0x90010, 0x2152}, - {0x90011, 0xdfbd}, - {0x90012, 0x2060}, - {0x90013, 0x6152}, - {0x20010, 0x5a}, - {0x20011, 0x3}, - {0x120010, 0x5a}, - {0x120011, 0x3}, - {0x40080, 0xe0}, - {0x40081, 0x12}, - {0x40082, 0xe0}, - {0x40083, 0x12}, - {0x40084, 0xe0}, - {0x40085, 0x12}, - {0x140080, 0xe0}, - {0x140081, 0x12}, - {0x140082, 0xe0}, - {0x140083, 0x12}, - {0x140084, 0xe0}, - {0x140085, 0x12}, - {0x240080, 0xe0}, - {0x240081, 0x12}, - {0x240082, 0xe0}, - {0x240083, 0x12}, - {0x240084, 0xe0}, - {0x240085, 0x12}, - {0x400fd, 0xf}, - {0x400f1, 0xe}, - {0x10011, 0x1}, - {0x10012, 0x1}, - {0x10013, 0x180}, - {0x10018, 0x1}, - {0x10002, 0x6209}, - {0x100b2, 0x1}, - {0x101b4, 0x1}, - {0x102b4, 0x1}, - {0x103b4, 0x1}, - {0x104b4, 0x1}, - {0x105b4, 0x1}, - {0x106b4, 0x1}, - {0x107b4, 0x1}, - {0x108b4, 0x1}, - {0x11011, 0x1}, - {0x11012, 0x1}, - {0x11013, 0x180}, - {0x11018, 0x1}, - {0x11002, 0x6209}, - {0x110b2, 0x1}, - {0x111b4, 0x1}, - {0x112b4, 0x1}, - {0x113b4, 0x1}, - {0x114b4, 0x1}, - {0x115b4, 0x1}, - {0x116b4, 0x1}, - {0x117b4, 0x1}, - {0x118b4, 0x1}, - {0x20089, 0x1}, - {0x20088, 0x19}, - {0xc0080, 0x0}, - {0xd0000, 0x1}, -}; - -struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 3200mts 1D */ - .drate = 3200, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 1600mts 1D */ - .drate = 1600, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 625mts 1D */ - .drate = 625, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 3200mts 2D */ - .drate = 3200, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3200, 1600, 625, }, - .fsp_cfg = ddr_dram_fsp_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), -}; diff --git a/board/freescale/imx93_qsb/spl.c b/board/freescale/imx93_qsb/spl.c deleted file mode 100644 index 9e64714521b..00000000000 --- a/board/freescale/imx93_qsb/spl.c +++ /dev/null @@ -1,159 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2024 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int spl_board_boot_device(enum boot_device boot_dev_spl) -{ - return BOOT_DEVICE_BOOTROM; -} - -void spl_board_init(void) -{ - int ret; - - ret = ele_start_rng(); - if (ret) - printf("Fail to start RNG: %d\n", ret); - - puts("Normal Boot\n"); -} - -void spl_dram_init(void) -{ - struct dram_timing_info *ptiming = &dram_timing; - - printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate); - ddr_init(ptiming); -} - -#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) -int power_init_board(void) -{ - struct udevice *dev; - int ret; - unsigned int val = 0, buck_val; - - ret = pmic_get("pmic@25", &dev); - if (ret == -ENODEV) { - puts("No pca9450@25\n"); - return 0; - } - if (ret != 0) - return ret; - - /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); - - /* enable DVS control through PMIC_STBY_REQ */ - pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); - - ret = pmic_reg_read(dev, PCA9450_PWR_CTRL); - if (ret < 0) - return ret; - - val = ret; - - if (is_voltage_mode(VOLT_LOW_DRIVE)) { - buck_val = 0x0c; /* 0.8V for Low drive mode */ - printf("PMIC: Low Drive Voltage Mode\n"); - } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) { - buck_val = 0x10; /* 0.85V for Nominal drive mode */ - printf("PMIC: Nominal Voltage Mode\n"); - } else { - buck_val = 0x14; /* 0.9V for Over drive mode */ - printf("PMIC: Over Drive Voltage Mode\n"); - } - - ele_volt_change_start_req(); - - if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val); - } else { - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4); - } - - ele_volt_change_finish_req(); - - /* set standby voltage to 0.65v */ - if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0); - else - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); - - /* 1.1v for LPDDR4 */ - pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28); - - /* I2C_LT_EN*/ - pmic_reg_write(dev, 0xa, 0x3); - - /* set WDOG_B_CFG to cold reset */ - pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); - return 0; -} -#endif - -void board_init_f(ulong dummy) -{ - int ret; - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - timer_init(); - - arch_cpu_init(); - - spl_early_init(); - - preloader_console_init(); - - ret = imx9_probe_mu(); - if (ret) { - printf("Fail to init ELE API\n"); - } else { - debug("SOC: 0x%x\n", gd->arch.soc_rev); - debug("LC: 0x%x\n", gd->arch.lifecycle); - } - - clock_init_late(); - - power_init_board(); - - if (!is_voltage_mode(VOLT_LOW_DRIVE)) - set_arm_clk(get_cpu_speed_grade_hz()); - - /* Init power of mix */ - soc_power_init(); - - /* Setup TRDC for DDR access */ - trdc_init(); - - /* DDR initialization */ - spl_dram_init(); - - /* Put M33 into CPUWAIT for following kick */ - ret = m33_prepare(); - if (!ret) - printf("M33 prepare ok\n"); - - board_init_r(NULL, 0); -} diff --git a/board/freescale/imx94_evk/Kconfig b/board/freescale/imx94_evk/Kconfig deleted file mode 100644 index a4237244ace..00000000000 --- a/board/freescale/imx94_evk/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_IMX943_EVK - -config SYS_BOARD - default "imx94_evk" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "imx94_evk" - -endif diff --git a/board/freescale/imx94_evk/MAINTAINERS b/board/freescale/imx94_evk/MAINTAINERS deleted file mode 100644 index 95309430734..00000000000 --- a/board/freescale/imx94_evk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -i.MX94 EVK BOARD -M: Alice Guo -S: Maintained -F: board/freescale/imx94_evk/ -F: include/configs/imx94_evk.h -F: configs/imx943_evk_defconfig diff --git a/board/freescale/imx94_evk/Makefile b/board/freescale/imx94_evk/Makefile deleted file mode 100644 index ca31602f6ba..00000000000 --- a/board/freescale/imx94_evk/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright 2025 NXP -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += imx94_evk.o - -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -endif diff --git a/board/freescale/imx94_evk/imx94_evk.c b/board/freescale/imx94_evk/imx94_evk.c deleted file mode 100644 index 588aa7548d4..00000000000 --- a/board/freescale/imx94_evk/imx94_evk.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2025 NXP - */ - -#include -#include -#include -#include -#include - -int board_early_init_f(void) -{ - init_uart_clk(0); - return 0; -} - -int board_init(void) -{ - return 0; -} - -int board_late_init(void) -{ - if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) - board_late_mmc_env_init(); - - env_set("sec_boot", "no"); - - if (IS_ENABLED(CONFIG_AHAB_BOOT)) - env_set("sec_boot", "yes"); - - return 0; -} - -int board_phys_sdram_size(phys_size_t *size) -{ - *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE; - - return 0; -} diff --git a/board/freescale/imx94_evk/imx94_evk.env b/board/freescale/imx94_evk/imx94_evk.env deleted file mode 100644 index 2baf1bbadcb..00000000000 --- a/board/freescale/imx94_evk/imx94_evk.env +++ /dev/null @@ -1,100 +0,0 @@ -#ifdef CONFIG_AHAB_BOOT -sec_boot=yes -#else -sec_boot=no -#endif - -jh_root_dtb=imx943-evk-root.dtb -jh_mmcboot=setenv fdtfile ${jh_root_dtb}; - setenv jh_clk kvm.enable_virt_at_load=false cpuidle.off=1 clk_ignore_unused kvm-arm.mode=nvhe; - setenv jh_root_mem 0x60000000@0x90000000,0x100000000@0x100000000; - if run loadimage; then - run mmcboot; - else run jh_netboot; fi; -jh_netboot=setenv fdtfile ${jh_root_dtb}; - setenv jh_root_mem 0x60000000@0x90000000,0x100000000@0x100000000; - setenv jh_clk kvm.enable_virt_at_load=false cpuidle.off=1 clk_ignore_unused kvm-arm.mode=nvhe; run netboot; - -initrd_addr=0x93800000 -emmc_dev=0 -sd_dev=1 -scriptaddr=0x93500000 -kernel_addr_r=CONFIG_SYS_LOAD_ADDR -image=Image -splashimage=0xA0000000 -console=ttyLP0,115200 earlycon -fdt_addr_r=0x93000000 -fdt_addr=0x93000000 -cntr_addr=0xA8000000 -cntr_file=os_cntr_signed.bin -boot_fit=no -fdtfile=CONFIG_DEFAULT_FDT_FILE -bootm_size=0x10000000 -mmcdev=CONFIG_SYS_MMC_ENV_DEV -mmcautodetect=yes -mmcargs=setenv bootargs ${jh_clk} ${mcore_args} console=${console} root=${mmcroot} -prepare_mcore=setenv mcore_args pd_ignore_unused; -loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; -bootscript=echo Running bootscript from mmc ...; source -loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} -loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} -auth_os=booti ${cntr_addr} -boot_os=booti ${loadaddr} - ${fdt_addr_r}; -mmcboot=echo Booting from mmc ...; - run mmcargs; - if test ${sec_boot} = yes; then - run auth_os; - else - if test ${boot_fit} = yes || test ${boot_fit} = try; then - bootm ${loadaddr}; - else - if run loadfdt; then - run boot_os; - else - echo WARN: Cannot load the DT; - fi; - fi; - fi; -netargs=setenv bootargs ${jh_clk} ${mcore_args} console=${console} root=/dev/nfs - ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp -netboot=echo Booting from net ...; - run netargs; - if test ${ip_dyn} = yes; then - setenv get_cmd dhcp; - else - setenv get_cmd tftp; - fi; - if test ${sec_boot} = yes; then - ${get_cmd} ${cntr_addr} ${cntr_file}; - run auth_os; - else - ${get_cmd} ${loadaddr} ${image}; - if test ${boot_fit} = yes || test ${boot_fit} = try; then - bootm ${loadaddr}; - else - if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then - run boot_os; - else - echo WARN: Cannot load the DT; - fi; - fi; - fi; -bsp_bootcmd=echo Running BSP bootcmd ...; - mmc dev ${mmcdev}; if mmc rescan; then - if run loadbootscript; then - run bootscript; - else - if test ${sec_boot} = yes; then - if run loadcntr; then - run mmcboot; - else run netboot; - fi; - else - if run loadimage; then - run mmcboot; - else run netboot; - fi; - fi; - fi; - fi; diff --git a/board/freescale/imx94_evk/spl.c b/board/freescale/imx94_evk/spl.c deleted file mode 100644 index 797806a8d4d..00000000000 --- a/board/freescale/imx94_evk/spl.c +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2025 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int spl_board_boot_device(enum boot_device boot_dev_spl) -{ - switch (boot_dev_spl) { - case SD1_BOOT: - case MMC1_BOOT: - return BOOT_DEVICE_MMC1; - case SD2_BOOT: - case MMC2_BOOT: - return BOOT_DEVICE_MMC2; - case USB_BOOT: - return BOOT_DEVICE_BOARD; - case QSPI_BOOT: - return BOOT_DEVICE_SPI; - default: - return BOOT_DEVICE_NONE; - } -} - -void spl_board_init(void) -{ - int ret; - - puts("Normal Boot\n"); - - ret = ele_start_rng(); - if (ret) - printf("Fail to start RNG: %d\n", ret); -} - -/* SCMI support by default */ -void board_init_f(ulong dummy) -{ - int ret; - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - if (IS_ENABLED(CONFIG_SPL_RECOVER_DATA_SECTION) && - IS_ENABLED(CONFIG_SPL_BUILD)) - spl_save_restore_data(); - - timer_init(); - - spl_early_init(); - - /* Need enable SCMI drivers and ELE driver before enabling console */ - ret = imx9_probe_mu(); - if (ret) - hang(); /* if MU not probed, nothing can output, just hang here */ - - arch_cpu_init(); - - board_early_init_f(); - - preloader_console_init(); - - debug("SOC: 0x%x\n", gd->arch.soc_rev); - debug("LC: 0x%x\n", gd->arch.lifecycle); - - get_reset_reason(true, false); - - board_init_r(NULL, 0); -} diff --git a/board/freescale/imx95_evk/Kconfig b/board/freescale/imx95_evk/Kconfig deleted file mode 100644 index bf746e091de..00000000000 --- a/board/freescale/imx95_evk/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_IMX95_19X19_EVK || TARGET_IMX95_15X15_EVK - -config SYS_BOARD - default "imx95_evk" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "imx95_evk" - -endif diff --git a/board/freescale/imx95_evk/MAINTAINERS b/board/freescale/imx95_evk/MAINTAINERS deleted file mode 100644 index bc27786f70d..00000000000 --- a/board/freescale/imx95_evk/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -i.MX95 EVK BOARD -M: Alice Guo -S: Maintained -F: board/freescale/imx95_evk/ -F: include/configs/imx95_evk.h -F: configs/imx95_a0_19x19_evk_defconfig -F: configs/imx95_19x19_evk_defconfig -F: configs/imx95_15x15_evk_defconfig diff --git a/board/freescale/imx95_evk/Makefile b/board/freescale/imx95_evk/Makefile deleted file mode 100644 index 0f5cec385c3..00000000000 --- a/board/freescale/imx95_evk/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright 2025 NXP -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += imx95_evk.o - -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -endif diff --git a/board/freescale/imx95_evk/imx95_evk.c b/board/freescale/imx95_evk/imx95_evk.c deleted file mode 100644 index ca1d916deab..00000000000 --- a/board/freescale/imx95_evk/imx95_evk.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2025 NXP - */ - -#include -#include -#include - -int board_early_init_f(void) -{ - /* UART1: A55, UART2: M33, UART3: M7 */ - init_uart_clk(0); - - return 0; -} - -int board_late_init(void) -{ - if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) - board_late_mmc_env_init(); - - return 0; -} - -int board_phys_sdram_size(phys_size_t *size) -{ - *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE; - - return 0; -} diff --git a/board/freescale/imx95_evk/imx95_evk.env b/board/freescale/imx95_evk/imx95_evk.env deleted file mode 100644 index a7309d734b0..00000000000 --- a/board/freescale/imx95_evk/imx95_evk.env +++ /dev/null @@ -1,91 +0,0 @@ -sec_boot=no -initrd_addr=0x93800000 -emmc_dev=0 -sd_dev=1 -scriptaddr=0x93500000 -kernel_addr_r=CONFIG_SYS_LOAD_ADDR -image=Image -splashimage=0xA0000000 -console=ttyLP0,115200 earlycon -fdt_addr_r=0x93000000 -fdt_addr=0x93000000 -cntr_addr=0xA8000000 -cntr_file=os_cntr_signed.bin -boot_fit=no -fdtfile=CONFIG_DEFAULT_FDT_FILE -bootm_size=0x10000000 -mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX -mmcautodetect=yes -mmcargs=setenv bootargs console=${console} root=${mmcroot} -loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; -bootscript=echo Running bootscript from mmc ...; source -loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} -loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} -auth_os=auth_cntr ${cntr_addr} -boot_os=booti ${loadaddr} - ${fdt_addr_r}; -mmcboot=echo Booting from mmc ...; - run mmcargs; - if test ${sec_boot} = yes; then - if run auth_os; then - run boot_os; - else - echo ERR: failed to authenticate; - fi; - else - if test ${boot_fit} = yes || test ${boot_fit} = try; then - bootm ${loadaddr}; - else - if run loadfdt; then - run boot_os; - else - echo WARN: Cannot load the DT; - fi; - fi; - fi; -netargs=setenv bootargs console=${console} root=/dev/nfs - ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp -netboot=echo Booting from net ...; - run netargs; - if test ${ip_dyn} = yes; then - setenv get_cmd dhcp; - else - setenv get_cmd tftp; - fi; - if test ${sec_boot} = yes; then - ${get_cmd} ${cntr_addr} ${cntr_file}; - if run auth_os; then - run boot_os; - else - echo ERR: failed to authenticate; - fi; - else - ${get_cmd} ${loadaddr} ${image}; - if test ${boot_fit} = yes || test ${boot_fit} = try; then - bootm ${loadaddr}; - else - if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then - run boot_os; - else - echo WARN: Cannot load the DT; - fi; - fi; - fi; -bsp_bootcmd=echo Running BSP bootcmd ...; - mmc dev ${mmcdev}; if mmc rescan; then - if run loadbootscript; then - run bootscript; - else - if test ${sec_boot} = yes; then - if run loadcntr; then - run mmcboot; - else run netboot; - fi; - else - if run loadimage; then - run mmcboot; - else run netboot; - fi; - fi; - fi; - fi; diff --git a/board/freescale/imx95_evk/spl.c b/board/freescale/imx95_evk/spl.c deleted file mode 100644 index 752d7f916b6..00000000000 --- a/board/freescale/imx95_evk/spl.c +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2025 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int spl_board_boot_device(enum boot_device boot_dev_spl) -{ - switch (boot_dev_spl) { - case SD1_BOOT: - case MMC1_BOOT: - return BOOT_DEVICE_MMC1; - case SD2_BOOT: - case MMC2_BOOT: - return BOOT_DEVICE_MMC2; - case USB_BOOT: - return BOOT_DEVICE_BOARD; - default: - return BOOT_DEVICE_NONE; - } -} - -void spl_board_init(void) -{ - int ret; - - puts("Normal Boot\n"); - - ret = ele_start_rng(); - if (ret) - printf("Fail to start RNG: %d\n", ret); -} - -void board_init_f(ulong dummy) -{ - int ret; - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - -#ifdef CONFIG_SPL_RECOVER_DATA_SECTION - if (IS_ENABLED(CONFIG_SPL_BUILD)) - spl_save_restore_data(); -#endif - - timer_init(); - - /* Need dm_init() to run before any SCMI calls can be made. */ - spl_early_init(); - - /* Need enable SCMI drivers and ELE driver before enabling console */ - ret = imx9_probe_mu(); - if (ret) - hang(); /* if MU not probed, nothing can output, just hang here */ - - arch_cpu_init(); - - board_early_init_f(); - - preloader_console_init(); - - debug("SOC: 0x%x\n", gd->arch.soc_rev); - debug("LC: 0x%x\n", gd->arch.lifecycle); - - get_reset_reason(true, false); - - board_init_r(NULL, 0); -} diff --git a/board/freescale/imxrt1020-evk/Kconfig b/board/freescale/imxrt1020-evk/Kconfig deleted file mode 100644 index 6618a9b3b57..00000000000 --- a/board/freescale/imxrt1020-evk/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -if TARGET_IMXRT1020_EVK - -config SYS_BOARD - default "imxrt1020-evk" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "imxrt1020" - -config SYS_CONFIG_NAME - default "imxrt1020-evk" - -config IMX_CONFIG - default "board/freescale/imxrt1020-evk/imximage.cfg" - -endif diff --git a/board/freescale/imxrt1020-evk/MAINTAINERS b/board/freescale/imxrt1020-evk/MAINTAINERS deleted file mode 100644 index 05f017b2bab..00000000000 --- a/board/freescale/imxrt1020-evk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -IMXRT1020 EVALUATION KIT -M: Giulio Benetti -S: Maintained -F: board/freescale/imxrt1020-evk -F: include/configs/imxrt1020-evk.h -F: configs/imxrt1020-evk_defconfig diff --git a/board/freescale/imxrt1020-evk/Makefile b/board/freescale/imxrt1020-evk/Makefile deleted file mode 100644 index 807dc7c35e1..00000000000 --- a/board/freescale/imxrt1020-evk/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2020 -# Author(s): Giulio Benetti - -obj-y := imxrt1020-evk.o diff --git a/board/freescale/imxrt1020-evk/imximage.cfg b/board/freescale/imxrt1020-evk/imximage.cfg deleted file mode 100644 index 0ed71479a60..00000000000 --- a/board/freescale/imxrt1020-evk/imximage.cfg +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2020 - * Author(s): Giulio Benetti - */ - -#include - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi/sd/nand/onenand, qspi/nor - */ - -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* Set all FlexRAM as OCRAM(01b) */ -DATA 4 0x400AC044 0x00005555 -/* Use FLEXRAM_BANK_CFG to config FlexRAM */ -SET_BIT 4 0x400AC040 0x4 diff --git a/board/freescale/imxrt1020-evk/imxrt1020-evk.c b/board/freescale/imxrt1020-evk/imxrt1020-evk.c deleted file mode 100644 index 11dbef84688..00000000000 --- a/board/freescale/imxrt1020-evk/imxrt1020-evk.c +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020 - * Author(s): Giulio Benetti - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ -#ifndef CONFIG_SUPPORT_SPL - int rv; - struct udevice *dev; - - rv = uclass_get_device(UCLASS_RAM, 0, &dev); - if (rv) { - debug("DRAM init failed: %d\n", rv); - return rv; - } - -#endif - return fdtdec_setup_mem_size_base(); -} - -int dram_init_banksize(void) -{ - return fdtdec_setup_memory_banksize(); -} - -#ifdef CONFIG_XPL_BUILD -#ifdef CONFIG_SPL_OS_BOOT -int spl_start_uboot(void) -{ - debug("SPL: booting kernel\n"); - /* break into full u-boot on 'c' */ - return serial_tstc() && serial_getc() == 'c'; -} -#endif - -int spl_dram_init(void) -{ - struct udevice *dev; - int rv; - - rv = uclass_get_device(UCLASS_RAM, 0, &dev); - if (rv) - debug("DRAM init failed: %d\n", rv); - return rv; -} - -void spl_board_init(void) -{ - preloader_console_init(); - spl_dram_init(); - arch_cpu_init(); /* to configure mpu for sdram rw permissions */ -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_MMC1; -} -#endif - -int board_init(void) -{ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; - - return 0; -} diff --git a/board/freescale/imxrt1050-evk/Kconfig b/board/freescale/imxrt1050-evk/Kconfig deleted file mode 100644 index 04ade6ec900..00000000000 --- a/board/freescale/imxrt1050-evk/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -if TARGET_IMXRT1050_EVK - -config SYS_BOARD - default "imxrt1050-evk" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "imxrt1050" - -config SYS_CONFIG_NAME - default "imxrt1050-evk" - -config IMX_CONFIG - default "board/freescale/imxrt1050-evk/imximage.cfg" - -endif diff --git a/board/freescale/imxrt1050-evk/MAINTAINERS b/board/freescale/imxrt1050-evk/MAINTAINERS deleted file mode 100644 index 890825b39ae..00000000000 --- a/board/freescale/imxrt1050-evk/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -IMXRT1050 EVALUATION KIT -M: Giulio Benetti -S: Maintained -F: board/freescale/imxrt1050-evk -F: include/configs/imxrt1050-evk.h -F: configs/imxrt1050-evk_defconfig -F: configs/imxrt1050-evk_fspi_defconfig diff --git a/board/freescale/imxrt1050-evk/Makefile b/board/freescale/imxrt1050-evk/Makefile deleted file mode 100644 index 0e984d1d7a8..00000000000 --- a/board/freescale/imxrt1050-evk/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2019 -# Author(s): Giulio Benetti - -obj-y := imxrt1050-evk.o diff --git a/board/freescale/imxrt1050-evk/imximage-nor.cfg b/board/freescale/imxrt1050-evk/imximage-nor.cfg deleted file mode 100644 index 829be6cbe2b..00000000000 --- a/board/freescale/imxrt1050-evk/imximage-nor.cfg +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2024 - * Author(s): Jesse Taube - */ - -#include - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi/sd/nand/onenand, qspi/nor - */ - -BOOT_FROM nor - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* - * 0x400AC044 is used to configure the flexram. - * Unfortunately setting all to OCRAM only works for MMC - * and setting all to DTCM only works for FLEXSPI NOR. - * This configuration fortunately works for both SPI and MMC. -*/ -/* Set first two banks FlexRAM as OCRAM(01b) and the rest to DTCM(10b) */ -DATA 4 0x400AC044 0x55aaaaaa -/* Use FLEXRAM_BANK_CFG to config FlexRAM */ -SET_BIT 4 0x400AC040 0x4 diff --git a/board/freescale/imxrt1050-evk/imximage.cfg b/board/freescale/imxrt1050-evk/imximage.cfg deleted file mode 100644 index b30d8521947..00000000000 --- a/board/freescale/imxrt1050-evk/imximage.cfg +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2019 - * Author(s): Giulio Benetti - */ - -#include - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi/sd/nand/onenand, qspi/nor - */ - -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* - * 0x400AC044 is used to configure the flexram. - * Unfortunately setting all to OCRAM only works for MMC - * and setting all to DTCM only works for FLEXSPI NOR. - * This configuration fortunately works for both SPI and MMC. -*/ -/* Set first two banks FlexRAM as OCRAM(01b) and the rest to DTCM(10b) */ -DATA 4 0x400AC044 0x55aaaaaa -/* Use FLEXRAM_BANK_CFG to config FlexRAM */ -SET_BIT 4 0x400AC040 0x4 diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk-nor.env b/board/freescale/imxrt1050-evk/imxrt1050-evk-nor.env deleted file mode 100644 index c61e9e3c00a..00000000000 --- a/board/freescale/imxrt1050-evk/imxrt1050-evk-nor.env +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -/* environment for imxrt1050-evk */ - -#ifdef CONFIG_VIDEO -stdin=serial -stdout=serial,vidconsole -stderr=serial,vidconsole -#endif - -fdt_addr_r=0x80800000 -kernel_addr_r=0x80000000 -boot_targets=nor diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.c b/board/freescale/imxrt1050-evk/imxrt1050-evk.c deleted file mode 100644 index 056489932ac..00000000000 --- a/board/freescale/imxrt1050-evk/imxrt1050-evk.c +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2019 - * Author(s): Giulio Benetti - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ -#ifndef CONFIG_SUPPORT_SPL - int rv; - struct udevice *dev; - - rv = uclass_get_device(UCLASS_RAM, 0, &dev); - if (rv) { - debug("DRAM init failed: %d\n", rv); - return rv; - } - -#endif - return fdtdec_setup_mem_size_base(); -} - -int dram_init_banksize(void) -{ - return fdtdec_setup_memory_banksize(); -} - -#ifdef CONFIG_XPL_BUILD -#ifdef CONFIG_SPL_OS_BOOT -int spl_start_uboot(void) -{ - debug("SPL: booting kernel\n"); - /* break into full u-boot on 'c' */ - return serial_tstc() && serial_getc() == 'c'; -} -#endif - -int spl_dram_init(void) -{ - struct udevice *dev; - int rv; - - rv = uclass_get_device(UCLASS_RAM, 0, &dev); - if (rv) - debug("DRAM init failed: %d\n", rv); - return rv; -} - -void spl_board_init(void) -{ - preloader_console_init(); - spl_dram_init(); - arch_cpu_init(); /* to configure mpu for sdram rw permissions */ -} - -u32 spl_boot_device(void) -{ - /* There is no way to find the boot device so look if there is a valid IVT in RAM for MMC */ - u32 nor_ivt = *(u32 *)(CONFIG_SYS_LOAD_ADDR - 0xC00); - - if (nor_ivt == 0x402000d1) - return BOOT_DEVICE_MMC1; - return BOOT_DEVICE_NOR; -} -#endif - -int board_init(void) -{ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; - - return 0; -} diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.env b/board/freescale/imxrt1050-evk/imxrt1050-evk.env deleted file mode 100644 index 1c5cbc29d53..00000000000 --- a/board/freescale/imxrt1050-evk/imxrt1050-evk.env +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -/* environment for imxrt1050-evk */ - -#ifdef CONFIG_VIDEO -stdin=serial -stdout=serial,vidconsole -stderr=serial,vidconsole -#endif - -fdt_addr_r=0x80800000 -kernel_addr_r=0x80000000 -boot_targets=mmc diff --git a/board/freescale/imxrt1170-evk/Kconfig b/board/freescale/imxrt1170-evk/Kconfig deleted file mode 100644 index ad7cd4aeb9c..00000000000 --- a/board/freescale/imxrt1170-evk/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -if TARGET_IMXRT1170_EVK - -config SYS_BOARD - default "imxrt1170-evk" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "imxrt1170" - -config SYS_CONFIG_NAME - default "imxrt1170-evk" - -config IMX_CONFIG - default "board/freescale/imxrt1170-evk/imximage.cfg" - -endif diff --git a/board/freescale/imxrt1170-evk/MAINTAINERS b/board/freescale/imxrt1170-evk/MAINTAINERS deleted file mode 100644 index 1fc3179c005..00000000000 --- a/board/freescale/imxrt1170-evk/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -IMXRT1170 EVALUATION KIT -M: Giulio Benetti -M: Jesse Taube -S: Maintained -F: board/freescale/imxrt1170-evk -F: include/configs/imxrt1170-evk.h -F: configs/imxrt1170-evk_defconfig diff --git a/board/freescale/imxrt1170-evk/Makefile b/board/freescale/imxrt1170-evk/Makefile deleted file mode 100644 index 857a168b09d..00000000000 --- a/board/freescale/imxrt1170-evk/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2019 -# Author(s): Giulio Benetti - -obj-y := imxrt1170-evk.o diff --git a/board/freescale/imxrt1170-evk/imximage.cfg b/board/freescale/imxrt1170-evk/imximage.cfg deleted file mode 100644 index 57583d04ce6..00000000000 --- a/board/freescale/imxrt1170-evk/imximage.cfg +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2022 - * Author(s): Jesse Taube - * Giulio Benetti - */ - -#include - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi/sd/nand/onenand, qspi/nor - */ - -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ diff --git a/board/freescale/imxrt1170-evk/imxrt1170-evk.c b/board/freescale/imxrt1170-evk/imxrt1170-evk.c deleted file mode 100644 index 047aea8181a..00000000000 --- a/board/freescale/imxrt1170-evk/imxrt1170-evk.c +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2019 - * Author(s): Giulio Benetti - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ -#ifndef CONFIG_SUPPORT_SPL - int rv; - struct udevice *dev; - - rv = uclass_get_device(UCLASS_RAM, 0, &dev); - if (rv) { - debug("DRAM init failed: %d\n", rv); - return rv; - } - -#endif - return fdtdec_setup_mem_size_base(); -} - -int dram_init_banksize(void) -{ - return fdtdec_setup_memory_banksize(); -} - -#ifdef CONFIG_XPL_BUILD -#ifdef CONFIG_SPL_OS_BOOT -int spl_start_uboot(void) -{ - debug("SPL: booting kernel\n"); - /* break into full u-boot on 'c' */ - return serial_tstc() && serial_getc() == 'c'; -} -#endif - -int spl_dram_init(void) -{ - struct udevice *dev; - int rv; - - rv = uclass_get_device(UCLASS_RAM, 0, &dev); - if (rv) - debug("DRAM init failed: %d\n", rv); - return rv; -} - -void spl_board_init(void) -{ - preloader_console_init(); - spl_dram_init(); - arch_cpu_init(); /* to configure mpu for sdram rw permissions */ -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_MMC1; -} -#endif - -int board_init(void) -{ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; - - return 0; -} diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig deleted file mode 100644 index a7e59e62656..00000000000 --- a/board/freescale/ls1012afrdm/Kconfig +++ /dev/null @@ -1,80 +0,0 @@ -if TARGET_LS1012AFRDM - -config SYS_BOARD - default "ls1012afrdm" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls1012afrdm" - -config SYS_LS_PFE_FW_ADDR - hex "Flash address of PFE firmware" - default 0x40a00000 - -config SYS_LS_PFE_FW_LENGTH - hex "length of PFE firmware" - default 0x40000 - -endif - -if FSL_PFE - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select PHYLIB - imply PHY_REALTEK - imply PHY_ATHEROS - -config DDR_PFE_PHYS_BASEADDR - hex "PFE DDR physical base address" - default 0x03800000 - -config DDR_PFE_BASEADDR - hex "PFE DDR base address" - default 0x83800000 - -config PFE_EMAC1_PHY_ADDR - hex "PFE DDR base address" - default 0x2 - -config PFE_EMAC2_PHY_ADDR - hex "PFE DDR base address" - default 0x1 - -endif - -if TARGET_LS1012AFRWY - -config SYS_BOARD - default "ls1012afrdm" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls1012afrwy" - -config SYS_LS_PFE_FW_ADDR - hex "Flash address of PFE firmware" - default 0x40020000 - -config SYS_LS_PFE_FW_LENGTH - hex "length of PFE firmware" - default 0x40000 - -config SYS_LS_PFE_ESBC_ADDR - hex "PFE Firmware HDR Addr" - default 0x401f8000 - -config SYS_LS_PFE_ESBC_LENGTH - hex "length of PFE Firmware HDR" - default 0xc00 -endif diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS deleted file mode 100644 index 89d1085b00b..00000000000 --- a/board/freescale/ls1012afrdm/MAINTAINERS +++ /dev/null @@ -1,17 +0,0 @@ -LS1012AFRDM BOARD -M: Pramod Kumar -S: Maintained -F: board/freescale/ls1012afrdm/ -F: include/configs/ls1012afrdm.h -F: configs/ls1012afrdm_qspi_defconfig -F: configs/ls1012afrdm_tfa_defconfig -F: configs/ls1012afrwy_tfa_defconfig -F: configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig - -LS1012AFRWY BOARD -M: Pramod Kumar -S: Maintained -F: board/freescale/ls1012afrwy/ -F: include/configs/ls1012afrwy.h -F: configs/ls1012afrwy_qspi_defconfig -F: configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile deleted file mode 100644 index 1e53c967304..00000000000 --- a/board/freescale/ls1012afrdm/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2016 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += ls1012afrdm.o -obj-$(CONFIG_FSL_PFE) += eth.o diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README deleted file mode 100644 index e60ed606ec1..00000000000 --- a/board/freescale/ls1012afrdm/README +++ /dev/null @@ -1,58 +0,0 @@ -Overview --------- -QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development -platform, with a complete debugging environment. The LS1012AFRDM board -supports the QorIQ LS1012A processor and is optimized to support the -high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. - -LS1012A SoC Overview --------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A -SoC overview. - - LS1012AFRDM board Overview - ----------------------- - - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s - - 2 SGMII 1G PHYs - - DDR Controller - - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s - operating at 1.35 V - - QSPI - - Onboard 512 Mbit QSPI flash memory running at speed up - to 108/54 MHz - - One high-speed USB 2.0/3.0 port, one USB 2.0 port - - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a - Micro-AB connector. - - USB 2.0 port is a debug port (CMSIS DAP) and is configured - as a Micro-AB device. - - I2C controller - - One I2C bus with connectivity to Arduino headers - - UART - - UART (Console): UART1 (Without flow control) for console - - ARM JTAG support - - ARM Cortex® 10-pin JTAG connector for LS1012A - - CMSIS DAP through K20 microcontroller - - SAI Audio interface - - One SAI port, SAI 2 with full duplex support - - Clocks - - 25 MHz crystal for LS1012A - - 8 MHz Crystal for K20 - - 24 MHz for SC16IS740IPW SPI to Dual UART bridge - - Power Supplies - - 5 V input supply from USB - - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and - other board interfaces - -Booting Options ---------------- -QSPI Flash 1 - -QSPI flash map --------------- -Images | Size |QSPI Flash Address ------------------------------------------- -RCW + PBI | 1MB | 0x4000_0000 -U-Boot | 1MB | 0x4010_0000 -U-Boot Env | 1MB | 0x4020_0000 -PPA FIT image | 2MB | 0x4050_0000 -Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c deleted file mode 100644 index c431e5e611b..00000000000 --- a/board/freescale/ls1012afrdm/eth.c +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" -#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1" - -#define MASK_ETH_PHY_RST 0x00000100 - -static inline void ls1012afrdm_reset_phy(void) -{ - unsigned int val; - struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR); - - setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST); - - val = in_be32(&pgpio->gpdat); - setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST); - mdelay(10); - - val = in_be32(&pgpio->gpdat); - setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST); - mdelay(50); -} - -int pfe_eth_board_init(struct udevice *dev) -{ - static int init_done; - struct mii_dev *bus; - struct pfe_mdio_info mac_mdio_info; - struct pfe_eth_dev *priv = dev_get_priv(dev); - - if (!init_done) { - ls1012afrdm_reset_phy(); - - mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; - mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME; - - bus = pfe_mdio_init(&mac_mdio_info); - if (!bus) { - printf("Failed to register mdio\n"); - return -1; - } - - init_done = 1; - } - - if (priv->gemac_port) { - mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR; - mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME; - bus = pfe_mdio_init(&mac_mdio_info); - if (!bus) { - printf("Failed to register mdio\n"); - return -1; - } - } - - pfe_set_mdio(priv->gemac_port, - miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); - if (!priv->gemac_port) - /* MAC1 */ - pfe_set_phy_address_mode(priv->gemac_port, - CONFIG_PFE_EMAC1_PHY_ADDR, - PHY_INTERFACE_MODE_SGMII); - else - /* MAC2 */ - pfe_set_phy_address_mode(priv->gemac_port, - CONFIG_PFE_EMAC2_PHY_ADDR, - PHY_INTERFACE_MODE_SGMII); - return 0; -} - -static struct pfe_eth_pdata pfe_pdata0 = { - .pfe_eth_pdata_mac = { - .iobase = (phys_addr_t)EMAC1_BASE_ADDR, - .phy_interface = 0, - }, - - .pfe_ddr_addr = { - .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, - .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, - }, -}; - -static struct pfe_eth_pdata pfe_pdata1 = { - .pfe_eth_pdata_mac = { - .iobase = (phys_addr_t)EMAC2_BASE_ADDR, - .phy_interface = 1, - }, - - .pfe_ddr_addr = { - .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, - .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, - }, -}; - -U_BOOT_DRVINFO(ls1012a_pfe0) = { - .name = "pfe_eth", - .plat = &pfe_pdata0, -}; - -U_BOOT_DRVINFO(ls1012a_pfe1) = { - .name = "pfe_eth", - .plat = &pfe_pdata1, -}; diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c deleted file mode 100644 index f157e75e385..00000000000 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ /dev/null @@ -1,188 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2017-2018, 2021 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static inline int get_board_version(void) -{ - uint32_t val; -#ifdef CONFIG_TARGET_LS1012AFRDM - val = 0; -#else - struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR); - - val = in_be32(&pgpio->gpdat) & BOARD_REV_MASK;/*Get GPIO2 11,12,14*/ - -#endif - return val; -} - -int checkboard(void) -{ -#ifdef CONFIG_TARGET_LS1012AFRDM - puts("Board: LS1012AFRDM "); -#else - int rev; - - rev = get_board_version(); - - puts("Board: FRWY-LS1012A "); - - puts("Version"); - - switch (rev) { - case BOARD_REV_A_B: - puts(": RevA/B "); - break; - case BOARD_REV_C: - puts(": RevC "); - break; - default: - puts(": unknown"); - break; - } -#endif - - return 0; -} - -#ifdef CONFIG_TARGET_LS1012AFRWY -int esdhc_status_fixup(void *blob, const char *compat) -{ - char esdhc0_path[] = "/soc/esdhc@1560000"; - char esdhc1_path[] = "/soc/esdhc@1580000"; - - do_fixup_by_path(blob, esdhc0_path, "status", "okay", - sizeof("okay"), 1); - - do_fixup_by_path(blob, esdhc1_path, "status", "disabled", - sizeof("disabled"), 1); - return 0; -} -#endif - -#ifdef CONFIG_TFABOOT -int dram_init(void) -{ -#ifdef CONFIG_TARGET_LS1012AFRWY - int board_rev; -#endif - - gd->ram_size = tfa_get_dram_size(); - - if (!gd->ram_size) { -#ifdef CONFIG_TARGET_LS1012AFRWY - board_rev = get_board_version(); - - if (board_rev & BOARD_REV_C) - gd->ram_size = SYS_SDRAM_SIZE_1024; - else - gd->ram_size = SYS_SDRAM_SIZE_512; -#else - gd->ram_size = CFG_SYS_SDRAM_SIZE; -#endif - } - return 0; -} -#else -int dram_init(void) -{ -#ifdef CONFIG_TARGET_LS1012AFRWY - int board_rev; -#endif - struct fsl_mmdc_info mparam = { - 0x04180000, /* mdctl */ - 0x00030035, /* mdpdc */ - 0x12554000, /* mdotc */ - 0xbabf7954, /* mdcfg0 */ - 0xdb328f64, /* mdcfg1 */ - 0x01ff00db, /* mdcfg2 */ - 0x00001680, /* mdmisc */ - 0x0f3c8000, /* mdref */ - 0x00002000, /* mdrwd */ - 0x00bf1023, /* mdor */ - 0x0000003f, /* mdasp */ - 0x0000022a, /* mpodtctrl */ - 0xa1390003, /* mpzqhwctrl */ - }; - -#ifdef CONFIG_TARGET_LS1012AFRWY - board_rev = get_board_version(); - - if (board_rev == BOARD_REV_C) { - mparam.mdctl = 0x05180000; - gd->ram_size = SYS_SDRAM_SIZE_1024; - } else { - gd->ram_size = SYS_SDRAM_SIZE_512; - } -#else - gd->ram_size = CFG_SYS_SDRAM_SIZE; -#endif - mmdc_init(&mparam); - -#if !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD) - /* This will break-before-make MMU for DDR */ - update_early_mmu_table(); -#endif - - return 0; -} -#endif - -int board_early_init_f(void) -{ - fsl_lsch2_early_init_f(); - - return 0; -} - -int board_init(void) -{ - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + - CONFIG_SYS_CCI400_OFFSET); - - /* - * Set CCI-400 control override register to enable barrier - * transaction - */ - if (current_el() == 3) - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); - - return 0; -} - -#ifdef CONFIG_FSL_PFE -void board_quiesce_devices(void) -{ - pfe_command_stop(0, NULL); -} -#endif - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - arch_fixup_fdt(blob); - - ft_cpu_setup(blob, bd); - - return 0; -} diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig deleted file mode 100644 index d333069898f..00000000000 --- a/board/freescale/ls1012aqds/Kconfig +++ /dev/null @@ -1,72 +0,0 @@ -if TARGET_LS1012AQDS - -config SYS_BOARD - default "ls1012aqds" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls1012aqds" - -if CHAIN_OF_TRUST -config SYS_LS_PFE_ESBC_ADDR - hex "PFE Firmware HDR Addr" - default 0x40700000 - -config SYS_LS_PFE_ESBC_LENGTH - hex "length of PFE Firmware HDR" - default 0xc00 -endif - -if FSL_PFE - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select PHYLIB - imply PHY_VITESSE - imply PHY_REALTEK - imply PHY_AQUANTIA - imply PHYLIB_10G - -config PFE_RGMII_RESET_WA - def_bool y - -config SYS_LS_PFE_FW_ADDR - hex "Flash address of PFE firmware" - default 0x40a00000 - -config SYS_LS_PFE_FW_LENGTH - hex "length of PFE firmware" - default 0x300000 - -config DDR_PFE_PHYS_BASEADDR - hex "PFE DDR physical base address" - default 0x03800000 - -config DDR_PFE_BASEADDR - hex "PFE DDR base address" - default 0x83800000 - -config PFE_EMAC1_PHY_ADDR - hex "PFE DDR base address" - default 0x1e - -config PFE_EMAC2_PHY_ADDR - hex "PFE DDR base address" - default 0x1 - -config PFE_SGMII_2500_PHY1_ADDR - hex "PFE DDR base address" - default 0x1 - -config PFE_SGMII_2500_PHY2_ADDR - hex "PFE DDR base address" - default 0x2 - -endif - -endif diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS deleted file mode 100644 index eabf5805765..00000000000 --- a/board/freescale/ls1012aqds/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -LS1012AQDS BOARD -M: Pramod Kumar -S: Maintained -F: board/freescale/ls1012aqds/ -F: include/configs/ls1012aqds.h -F: configs/ls1012aqds_qspi_defconfig -F: configs/ls1012aqds_tfa_defconfig -F: configs/ls1012aqds_tfa_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile deleted file mode 100644 index 5aba9caf927..00000000000 --- a/board/freescale/ls1012aqds/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2016 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += ls1012aqds.o -obj-$(CONFIG_FSL_PFE) += eth.o diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README deleted file mode 100644 index e9b80cad506..00000000000 --- a/board/freescale/ls1012aqds/README +++ /dev/null @@ -1,59 +0,0 @@ -Overview --------- -QorIQ LS1012A Development System (LS1012AQDS) is a high-performance -development platform, with a complete debugging environment. -The LS1012AQDS board supports the QorIQ LS1012A processor and is -optimized to support the high-bandwidth DDR3L memory and -a full complement of high-speed SerDes ports. - -LS1012A SoC Overview --------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A -SoC overview. - -LS1012AQDS board Overview ------------------------ - - SERDES Connections, 4 lanes supporting: - - PCI Express - 3.0 - - SGMII, SGMII 2.5 - - SATA 3.0 - - DDR Controller - - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s - - QSPI Controller - - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select - signals to QSPI NOR flash memory (2 virtual banks) and the QSPI - emulator - - USB 3.0 - - One USB 3.0 controller with integrated PHY - - One high-speed USB 3.0 port - - USB 2.0 - - One USB 2.0 controller with ULPI interface - - Two enhanced secure digital host controllers: - - SDHC1 controller can be connected to onboard SDHC connector - - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices - - 2 I2C controllers - - One SATA onboard connectors - - UART - - 5 SAI - - One SAI port with audio codec SGTL5000: - • Provides MIC bias - • Provides headphone and line output - - One SAI port terminated at 2x6 header - - Three SAI Tx/Rx ports terminated at 2x3 headers - - ARM JTAG support - -Booting Options ---------------- -a) QSPI Flash Emu Boot -b) QSPI Flash 1 -c) QSPI Flash 2 - -QSPI flash map --------------- -Images | Size |QSPI Flash Address ------------------------------------------- -RCW + PBI | 1MB | 0x4000_0000 -U-Boot | 1MB | 0x4010_0000 -U-Boot Env | 1MB | 0x4020_0000 -PPA FIT image | 2MB | 0x4050_0000 -Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c deleted file mode 100644 index d5e87c5393b..00000000000 --- a/board/freescale/ls1012aqds/eth.c +++ /dev/null @@ -1,309 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/qixis.h" -#include -#include -#include "ls1012aqds_qixis.h" - -#define EMI_NONE 0xFF -#define EMI1_RGMII 1 -#define EMI1_SLOT1 2 -#define EMI1_SLOT2 3 - -#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" -#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1" - -static const char * const mdio_names[] = { - "NULL", - "LS1012AQDS_MDIO_RGMII", - "LS1012AQDS_MDIO_SLOT1", - "LS1012AQDS_MDIO_SLOT2", - "NULL", -}; - -static const char *ls1012aqds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct ls1012aqds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void ls1012aqds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - - if (muxval < 7) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int ls1012aqds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct ls1012aqds_mdio *priv = bus->priv; - - ls1012aqds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int ls1012aqds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct ls1012aqds_mdio *priv = bus->priv; - - ls1012aqds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int ls1012aqds_mdio_reset(struct mii_dev *bus) -{ - struct ls1012aqds_mdio *priv = bus->priv; - - if (priv->realbus->reset) - return priv->realbus->reset(priv->realbus); - else - return -1; -} - -static int ls1012aqds_mdio_init(char *realbusname, u8 muxval) -{ - struct ls1012aqds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate ls1012aqds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate ls1012aqds private data\n"); - free(bus); - return -1; - } - - bus->read = ls1012aqds_mdio_read; - bus->write = ls1012aqds_mdio_write; - bus->reset = ls1012aqds_mdio_reset; - sprintf(bus->name, ls1012aqds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - return mdio_register(bus); -} - -int pfe_eth_board_init(struct udevice *dev) -{ - static int init_done; - struct mii_dev *bus; - static const char *mdio_name; - struct pfe_mdio_info mac_mdio_info; - struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; - u8 data8; - struct pfe_eth_dev *priv = dev_get_priv(dev); - - int srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - ls1012aqds_mux_mdio(EMI1_SLOT1); - - if (!init_done) { - mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; - mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME; - - bus = pfe_mdio_init(&mac_mdio_info); - if (!bus) { - printf("Failed to register mdio\n"); - return -1; - } - init_done = 1; - } - - if (priv->gemac_port) { - mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR; - mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME; - - bus = pfe_mdio_init(&mac_mdio_info); - if (!bus) { - printf("Failed to register mdio\n"); - return -1; - } - } - - switch (srds_s1) { - case 0x3508: - printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1); -#ifdef CONFIG_PFE_RGMII_RESET_WA - /* - * Work around for FPGA registers initialization - * This is needed for RGMII to work. - */ - printf("Reset RGMII WA....\n"); - data8 = QIXIS_READ(rst_frc[0]); - data8 |= 0x2; - QIXIS_WRITE(rst_frc[0], data8); - data8 = QIXIS_READ(rst_frc[0]); - - data8 = QIXIS_READ(res8[6]); - data8 |= 0xff; - QIXIS_WRITE(res8[6], data8); - data8 = QIXIS_READ(res8[6]); -#endif - if (priv->gemac_port) { - mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII); - if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_RGMII) - < 0) { - printf("Failed to register mdio for %s\n", mdio_name); - } - - /* MAC2 */ - mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII); - bus = miiphy_get_dev_by_name(mdio_name); - pfe_set_mdio(priv->gemac_port, bus); - pfe_set_phy_address_mode(priv->gemac_port, - CONFIG_PFE_EMAC2_PHY_ADDR, - PHY_INTERFACE_MODE_RGMII); - - } else { - mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1); - if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1) - < 0) { - printf("Failed to register mdio for %s\n", mdio_name); - } - - /* MAC1 */ - mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1); - bus = miiphy_get_dev_by_name(mdio_name); - pfe_set_mdio(priv->gemac_port, bus); - pfe_set_phy_address_mode(priv->gemac_port, - CONFIG_PFE_EMAC1_PHY_ADDR, - PHY_INTERFACE_MODE_SGMII); - } - - break; - - case 0x2205: - printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1); - /* - * Work around for FPGA registers initialization - * This is needed for RGMII to work. - */ - printf("Reset SLOT1 SLOT2....\n"); - data8 = QIXIS_READ(rst_frc[2]); - data8 |= 0xc0; - QIXIS_WRITE(rst_frc[2], data8); - mdelay(100); - data8 = QIXIS_READ(rst_frc[2]); - data8 &= 0x3f; - QIXIS_WRITE(rst_frc[2], data8); - - if (priv->gemac_port) { - mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2); - if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT2) - < 0) { - printf("Failed to register mdio for %s\n", mdio_name); - } - /* MAC2 */ - mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2); - bus = miiphy_get_dev_by_name(mdio_name); - pfe_set_mdio(1, bus); - pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR, - PHY_INTERFACE_MODE_2500BASEX); - - data8 = QIXIS_READ(brdcfg[12]); - data8 |= 0x20; - QIXIS_WRITE(brdcfg[12], data8); - - } else { - mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1); - if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1) - < 0) { - printf("Failed to register mdio for %s\n", mdio_name); - } - - /* MAC1 */ - mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1); - bus = miiphy_get_dev_by_name(mdio_name); - pfe_set_mdio(0, bus); - pfe_set_phy_address_mode(0, - CONFIG_PFE_SGMII_2500_PHY1_ADDR, - PHY_INTERFACE_MODE_2500BASEX); - } - break; - - default: - printf("ls1012aqds:unsupported SerDes PRCTL= %d\n", srds_s1); - break; - } - return 0; -} - -static struct pfe_eth_pdata pfe_pdata0 = { - .pfe_eth_pdata_mac = { - .iobase = (phys_addr_t)EMAC1_BASE_ADDR, - .phy_interface = 0, - }, - - .pfe_ddr_addr = { - .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, - .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, - }, -}; - -static struct pfe_eth_pdata pfe_pdata1 = { - .pfe_eth_pdata_mac = { - .iobase = (phys_addr_t)EMAC2_BASE_ADDR, - .phy_interface = 1, - }, - - .pfe_ddr_addr = { - .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, - .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, - }, -}; - -U_BOOT_DRVINFO(ls1012a_pfe0) = { - .name = "pfe_eth", - .plat = &pfe_pdata0, -}; - -U_BOOT_DRVINFO(ls1012a_pfe1) = { - .name = "pfe_eth", - .plat = &pfe_pdata1, -}; diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c deleted file mode 100644 index b21c4d917d0..00000000000 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ /dev/null @@ -1,287 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2021 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/qixis.h" -#include "ls1012aqds_qixis.h" -#include "ls1012aqds_pfe.h" -#include - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - char buf[64]; - u8 sw; - - sw = QIXIS_READ(arch); - printf("Board Arch: V%d, ", sw >> 4); - printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); - - sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); - - if (sw & QIXIS_LBMAP_ALTBANK) - printf("flash: 2\n"); - else - printf("flash: 1\n"); - - printf("FPGA: v%d (%s), build %d", - (int)QIXIS_READ(scver), qixis_read_tag(buf), - (int)qixis_read_minor()); - - /* the timestamp string contains "\n" at the end */ - printf(" on %s", qixis_read_time(buf)); - return 0; -} - -#ifdef CONFIG_TFABOOT -int dram_init(void) -{ - gd->ram_size = tfa_get_dram_size(); - if (!gd->ram_size) - gd->ram_size = CFG_SYS_SDRAM_SIZE; - - return 0; -} -#else -int dram_init(void) -{ - static const struct fsl_mmdc_info mparam = { - 0x05180000, /* mdctl */ - 0x00030035, /* mdpdc */ - 0x12554000, /* mdotc */ - 0xbabf7954, /* mdcfg0 */ - 0xdb328f64, /* mdcfg1 */ - 0x01ff00db, /* mdcfg2 */ - 0x00001680, /* mdmisc */ - 0x0f3c8000, /* mdref */ - 0x00002000, /* mdrwd */ - 0x00bf1023, /* mdor */ - 0x0000003f, /* mdasp */ - 0x0000022a, /* mpodtctrl */ - 0xa1390003, /* mpzqhwctrl */ - }; - - mmdc_init(&mparam); - gd->ram_size = CFG_SYS_SDRAM_SIZE; -#if !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD) - /* This will break-before-make MMU for DDR */ - update_early_mmu_table(); -#endif - - return 0; -} -#endif - -int board_early_init_f(void) -{ - fsl_lsch2_early_init_f(); - - return 0; -} - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ - u8 mux_sdhc_cd = 0x80; - int bus_num = 0; - -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_FPGA_ADDR, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1); -#else - i2c_set_bus_num(bus_num); - - i2c_write(CFG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); -#endif - - return 0; -} -#endif - -int board_init(void) -{ - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + - CONFIG_SYS_CCI400_OFFSET); - - /* Set CCI-400 control override register to enable barrier - * transaction */ - if (current_el() == 3) - out_le32(&cci->ctrl_ord, - CCI400_CTRLORD_EN_BARRIER); - -#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 - erratum_a010315(); -#endif - - return 0; -} - -#ifdef CONFIG_FSL_PFE -void board_quiesce_devices(void) -{ - pfe_command_stop(0, NULL); -} -#endif - -int esdhc_status_fixup(void *blob, const char *compat) -{ - char esdhc0_path[] = "/soc/esdhc@1560000"; - char esdhc1_path[] = "/soc/esdhc@1580000"; - u8 card_id; - - do_fixup_by_path(blob, esdhc0_path, "status", "okay", - sizeof("okay"), 1); - - /* - * The Presence Detect 2 register detects the installation - * of cards in various PCI Express or SGMII slots. - * - * STAT_PRS2[7:5]: Specifies the type of card installed in the - * SDHC2 Adapter slot. 0b111 indicates no adapter is installed. - */ - card_id = (QIXIS_READ(present2) & 0xe0) >> 5; - - /* If no adapter is installed in SDHC2, disable SDHC2 */ - if (card_id == 0x7) - do_fixup_by_path(blob, esdhc1_path, "status", "disabled", - sizeof("disabled"), 1); - else - do_fixup_by_path(blob, esdhc1_path, "status", "okay", - sizeof("okay"), 1); - return 0; -} - -static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val, - char *enet_path, char *mdio_path) -{ - do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id", - &prop_val.busid, PFE_PROP_LEN, 1); - do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id", - &prop_val.phyid, PFE_PROP_LEN, 1); - do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val", - &prop_val.mux_val, PFE_PROP_LEN, 1); - do_fixup_by_path(set_blob, enet_path, "phy-mode", - prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1); - do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask", - &prop_val.phy_mask, PFE_PROP_LEN, 1); - return 0; -} - -static void fdt_fsl_fixup_of_pfe(void *blob) -{ - int i = 0; - struct pfe_prop_val prop_val; - void *l_blob = blob; - - struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; - unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - for (i = 0; i < NUM_ETH_NODE; i++) { - switch (srds_s1) { - case SERDES_1_G_PROTOCOL: - if (i == 0) { - prop_val.busid = cpu_to_fdt32( - ETH_1_1G_BUS_ID); - prop_val.phyid = cpu_to_fdt32( - ETH_1_1G_PHY_ID); - prop_val.mux_val = cpu_to_fdt32( - ETH_1_1G_MDIO_MUX); - prop_val.phy_mask = cpu_to_fdt32( - ETH_1G_MDIO_PHY_MASK); - prop_val.phy_mode = "sgmii"; - pfe_set_properties(l_blob, prop_val, ETH_1_PATH, - ETH_1_MDIO); - } else { - prop_val.busid = cpu_to_fdt32( - ETH_2_1G_BUS_ID); - prop_val.phyid = cpu_to_fdt32( - ETH_2_1G_PHY_ID); - prop_val.mux_val = cpu_to_fdt32( - ETH_2_1G_MDIO_MUX); - prop_val.phy_mask = cpu_to_fdt32( - ETH_1G_MDIO_PHY_MASK); - prop_val.phy_mode = "rgmii"; - pfe_set_properties(l_blob, prop_val, ETH_2_PATH, - ETH_2_MDIO); - } - break; - case SERDES_2_5_G_PROTOCOL: - if (i == 0) { - prop_val.busid = cpu_to_fdt32( - ETH_1_2_5G_BUS_ID); - prop_val.phyid = cpu_to_fdt32( - ETH_1_2_5G_PHY_ID); - prop_val.mux_val = cpu_to_fdt32( - ETH_1_2_5G_MDIO_MUX); - prop_val.phy_mask = cpu_to_fdt32( - ETH_2_5G_MDIO_PHY_MASK); - prop_val.phy_mode = "2500base-x"; - pfe_set_properties(l_blob, prop_val, ETH_1_PATH, - ETH_1_MDIO); - } else { - prop_val.busid = cpu_to_fdt32( - ETH_2_2_5G_BUS_ID); - prop_val.phyid = cpu_to_fdt32( - ETH_2_2_5G_PHY_ID); - prop_val.mux_val = cpu_to_fdt32( - ETH_2_2_5G_MDIO_MUX); - prop_val.phy_mask = cpu_to_fdt32( - ETH_2_5G_MDIO_PHY_MASK); - prop_val.phy_mode = "2500base-x"; - pfe_set_properties(l_blob, prop_val, ETH_2_PATH, - ETH_2_MDIO); - } - break; - default: - printf("serdes:[%d]\n", srds_s1); - } - } -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - arch_fixup_fdt(blob); - - ft_cpu_setup(blob, bd); - fdt_fsl_fixup_of_pfe(blob); - - return 0; -} -#endif diff --git a/board/freescale/ls1012aqds/ls1012aqds_pfe.h b/board/freescale/ls1012aqds/ls1012aqds_pfe.h deleted file mode 100644 index 5ab283ce8d5..00000000000 --- a/board/freescale/ls1012aqds/ls1012aqds_pfe.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017 NXP - */ - -#define ETH_1_1G_BUS_ID 0x1 -#define ETH_1_1G_PHY_ID 0x1e -#define ETH_1_1G_MDIO_MUX 0x2 -#define ETH_1G_MDIO_PHY_MASK 0xBFFFFFFD -#define ETH_1_1G_PHY_MODE "sgmii" -#define ETH_2_1G_BUS_ID 0x1 -#define ETH_2_1G_PHY_ID 0x1 -#define ETH_2_1G_MDIO_MUX 0x1 -#define ETH_2_1G_PHY_MODE "rgmii" - -#define ETH_1_2_5G_BUS_ID 0x0 -#define ETH_1_2_5G_PHY_ID 0x1 -#define ETH_1_2_5G_MDIO_MUX 0x2 -#define ETH_2_5G_MDIO_PHY_MASK 0xFFFFFFF9 -#define ETH_2_5G_PHY_MODE "2500base-x" -#define ETH_2_2_5G_BUS_ID 0x1 -#define ETH_2_2_5G_PHY_ID 0x2 -#define ETH_2_2_5G_MDIO_MUX 0x3 - -#define SERDES_1_G_PROTOCOL 0x3508 -#define SERDES_2_5_G_PROTOCOL 0x2205 - -#define PFE_PROP_LEN 4 - -#define ETH_1_PATH "/pfe@04000000/ethernet@0" -#define ETH_1_MDIO ETH_1_PATH "/mdio@0" - -#define ETH_2_PATH "/pfe@04000000/ethernet@1" -#define ETH_2_MDIO ETH_2_PATH "/mdio@0" - -#define NUM_ETH_NODE 2 - -struct pfe_prop_val { - int busid; - int phyid; - int mux_val; - int phy_mask; - char *phy_mode; -}; diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h deleted file mode 100644 index 19f522d9eaa..00000000000 --- a/board/freescale/ls1012aqds/ls1012aqds_qixis.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __LS1043AQDS_QIXIS_H__ -#define __LS1043AQDS_QIXIS_H__ - -/* Definitions of QIXIS Registers for LS1043AQDS */ - -/* BRDCFG4[4:7] select EC1 and EC2 as a pair */ -#define BRDCFG4_EMISEL_MASK 0xe0 -#define BRDCFG4_EMISEL_SHIFT 6 - -/* SYSCLK */ -#define QIXIS_SYSCLK_66 0x0 -#define QIXIS_SYSCLK_83 0x1 -#define QIXIS_SYSCLK_100 0x2 -#define QIXIS_SYSCLK_125 0x3 -#define QIXIS_SYSCLK_133 0x4 - -/* DDRCLK */ -#define QIXIS_DDRCLK_66 0x0 -#define QIXIS_DDRCLK_100 0x1 -#define QIXIS_DDRCLK_125 0x2 -#define QIXIS_DDRCLK_133 0x3 - -/* BRDCFG2 - SD clock*/ -#define QIXIS_SDCLK1_100 0x0 -#define QIXIS_SDCLK1_125 0x1 -#define QIXIS_SDCLK1_165 0x2 -#define QIXIS_SDCLK1_100_SP 0x3 - -#endif diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig deleted file mode 100644 index b55660d485f..00000000000 --- a/board/freescale/ls1012ardb/Kconfig +++ /dev/null @@ -1,108 +0,0 @@ -if TARGET_LS1012ARDB - -config SYS_BOARD - default "ls1012ardb" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls1012ardb" - -if CHAIN_OF_TRUST -config SYS_LS_PFE_ESBC_ADDR - hex "PFE Firmware HDR Addr" - default 0x40640000 - -config SYS_LS_PFE_ESBC_LENGTH - hex "length of PFE Firmware HDR" - default 0xc00 -endif - -if FSL_PFE - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select PHYLIB - imply PHY_REALTEK - -config SYS_LS_PFE_FW_ADDR - hex "Flash address of PFE firmware" - default 0x40a00000 - -config SYS_LS_PFE_FW_LENGTH - hex "length of PFE firmware" - default 0x300000 - -config DDR_PFE_PHYS_BASEADDR - hex "PFE DDR physical base address" - default 0x03800000 - -config DDR_PFE_BASEADDR - hex "PFE DDR base address" - default 0x83800000 - -config PFE_EMAC1_PHY_ADDR - hex "PFE DDR base address" - default 0x2 - -config PFE_EMAC2_PHY_ADDR - hex "PFE DDR base address" - default 0x1 - -endif - -endif - -if TARGET_LS1012A2G5RDB - -config SYS_BOARD - default "ls1012ardb" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls1012a2g5rdb" - -if FSL_PFE - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select PHYLIB - imply PHYLIB_10G - imply PHY_AQUANTIA - -config SYS_LS_PFE_FW_ADDR - hex "Flash address of PFE firmware" - default 0x40a00000 - -config SYS_LS_PFE_FW_LENGTH - hex "length of PFE firmware" - default 0x300000 - -config DDR_PFE_PHYS_BASEADDR - hex "PFE DDR physical base address" - default 0x03800000 - -config DDR_PFE_BASEADDR - hex "PFE DDR base address" - default 0x83800000 - -config PFE_EMAC1_PHY_ADDR - hex "PFE DDR base address" - default 0x2 - -config PFE_EMAC2_PHY_ADDR - hex "PFE DDR base address" - default 0x1 - -endif - -endif diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS deleted file mode 100644 index ce2f9a16cc7..00000000000 --- a/board/freescale/ls1012ardb/MAINTAINERS +++ /dev/null @@ -1,17 +0,0 @@ -LS1012ARDB BOARD -M: Pramod Kumar -S: Maintained -F: board/freescale/ls1012ardb/ -F: include/configs/ls1012ardb.h -F: configs/ls1012ardb_qspi_defconfig -F: configs/ls1012ardb_tfa_defconfig -F: configs/ls1012ardb_tfa_SECURE_BOOT_defconfig -F: configs/ls1012a2g5rdb_tfa_defconfig -F: configs/ls1012ardb_qspi_SECURE_BOOT_defconfig - -LS1012A2G5RDB BOARD -M: Pramod Kumar -S: Maintained -F: board/freescale/ls1012ardb/ -F: include/configs/ls1012a2g5rdb.h -F: configs/ls1012a2g5rdb_qspi_defconfig diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile deleted file mode 100644 index 70c7b33273d..00000000000 --- a/board/freescale/ls1012ardb/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2016 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += ls1012ardb.o -obj-$(CONFIG_FSL_PFE) += eth.o diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README deleted file mode 100644 index 26b0485a7f8..00000000000 --- a/board/freescale/ls1012ardb/README +++ /dev/null @@ -1,97 +0,0 @@ -Overview --------- -QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance -development platform, with a complete debugging environment. -The LS1012ARDB board supports the QorIQ LS1012A processor and is -optimized to support the high-bandwidth DDR3L memory and -a full complement of high-speed SerDes ports. - -LS1012A SoC Overview --------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A -SoC overview. - -LS1012ARDB board Overview ------------------------ - - SERDES Connections, 4 lanes supporting: - - PCI Express - 3.0 - - SGMII, SGMII 2.5 - - SATA 3.0 - - DDR Controller - - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s - -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select - signals to - - QSPI NOR flash memory (2 virtual banks) - - the QSPI emulator.s - - USB 3.0 - - one high-speed USB 2.0/3.0 port. - - Two enhanced secure digital host controllers: - - SDHC1 controller can be connected to onboard SDHC connector - - SDHC2 controller: Three dual 1:4 mux/demux devices, - 74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC, - SDIO WiFi, SPI, and Ardiuno shield - - 2 I2C controllers - - One SATA onboard connectors - - UART - - The LS1012A processor consists of two UART controllers, - out of which only UART1 is used on RDB. - - ARM JTAG support - -Booting Options ---------------- -a) QSPI Flash Emu Boot -b) QSPI Flash 1 -c) QSPI Flash 2 - -QSPI flash map --------------- -Images | Size |QSPI Flash Address ------------------------------------------- -RCW + PBI | 1MB | 0x4000_0000 -U-Boot | 1MB | 0x4010_0000 -U-Boot Env | 1MB | 0x4020_0000 -PPA FIT image | 2MB | 0x4050_0000 -Linux ITB | ~53MB | 0x40A0_0000 - -LS1012A2G5RDB board Overview ------------------------ - - SERDES Connections, 3 lanes supporting: - - SGMII, SGMII 2.5 - - SATA 3.0 - - DDR Controller - - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s - -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select - signals to - - QSPI NOR flash memory - - USB 3.0 - - one high-speed USB 2.0/3.0 port. - - SDIO WiFi, SPI - - 2 I2C controllers - - One SATA onboard connectors - - UART - - The LS1012A processor consists of two UART controllers, - out of which only UART1 is used on 2G5RDB. - - ARM JTAG support - -Major Difference between LS1012ARDB and LS1012A-2G5RDB ------------------------------------------------------- -1. LS1012A-2G5RDB has Type C USB connector unlike USB Type A/B of LS1012ARDB -2. LS1012A-2G5RDB has 2 2.5G AQR PHY unlike 2 1G Realtek RTL8211FS PHYs - of LS1012ARDB -3. LS1012A-2G5RDB is not having Arduino header -4. LS1012A-2G5RDB doesn't have PCI slot - -Booting Options ---------------- -QSPI Flash - -QSPI flash map --------------- -Images | Size |QSPI Flash Address ------------------------------------------- -RCW + PBI | 1MB | 0x4000_0000 -U-Boot | 1MB | 0x4010_0000 -U-Boot Env | 1MB | 0x4030_0000 -PPA FIT image | 2MB | 0x4040_0000 -PFE firmware | 20K | 0x00a0_0000 -Linux ITB | ~53MB | 0x4100_0000 diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c deleted file mode 100644 index 71cb2988a56..00000000000 --- a/board/freescale/ls1012ardb/eth.c +++ /dev/null @@ -1,171 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" - -static inline void ls1012ardb_reset_phy(void) -{ -#ifdef CONFIG_TARGET_LS1012ARDB - /* Through reset IO expander reset both RGMII and SGMII PHYs */ -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - int ret; - - /* - * The I2C IO-expander PCAL9555A is mouted on I2C1 bus(bus number is 0). - */ - ret = i2c_get_chip_for_busnum(0, I2C_MUX_IO2_ADDR, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - 0); - return; - } - /* Config port 0 - * - config pin IOXP_RST_ETH1_B and IOXP_RST_ETH2_B - * are enabled as an output. - */ - dm_i2c_reg_write(dev, 6, __PHY_MASK); - - /* - * Set port 0 output a value to reset ETH2 interface - * - pin IOXP_RST_ETH2_B output 0b0 - */ - dm_i2c_reg_write(dev, 2, __PHY_ETH2_MASK); - mdelay(10); - dm_i2c_reg_write(dev, 2, __PHY_ETH1_MASK); - /* - * Set port 0 output a value to reset ETH1 interface - * - pin IOXP_RST_ETH1_B output 0b0 - */ - mdelay(10); - dm_i2c_reg_write(dev, 2, 0xFF); -#else - i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK); - i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK); - mdelay(10); - i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK); - mdelay(10); - i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF); -#endif - mdelay(50); -#endif -} - -int pfe_eth_board_init(struct udevice *dev) -{ - static int init_done; - struct mii_dev *bus; - struct pfe_mdio_info mac_mdio_info; - struct pfe_eth_dev *priv = dev_get_priv(dev); - struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; - - int srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - if (!init_done) { - ls1012ardb_reset_phy(); - mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; - mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME; - - bus = pfe_mdio_init(&mac_mdio_info); - if (!bus) { - printf("Failed to register mdio\n"); - return -1; - } - init_done = 1; - } - - pfe_set_mdio(priv->gemac_port, - miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); - - switch (srds_s1) { - case 0x3508: - if (!priv->gemac_port) { - /* MAC1 */ - pfe_set_phy_address_mode(priv->gemac_port, - CONFIG_PFE_EMAC1_PHY_ADDR, - PHY_INTERFACE_MODE_SGMII); - } else { - /* MAC2 */ - pfe_set_phy_address_mode(priv->gemac_port, - CONFIG_PFE_EMAC2_PHY_ADDR, - PHY_INTERFACE_MODE_RGMII_ID); - } - break; - case 0x2208: - if (!priv->gemac_port) { - /* MAC1 */ - pfe_set_phy_address_mode(priv->gemac_port, - CONFIG_PFE_EMAC1_PHY_ADDR, - PHY_INTERFACE_MODE_2500BASEX); - } else { - /* MAC2 */ - pfe_set_phy_address_mode(priv->gemac_port, - CONFIG_PFE_EMAC2_PHY_ADDR, - PHY_INTERFACE_MODE_2500BASEX); - } - break; - default: - printf("unsupported SerDes PRCTL= %d\n", srds_s1); - break; - } - return 0; -} - -static struct pfe_eth_pdata pfe_pdata0 = { - .pfe_eth_pdata_mac = { - .iobase = (phys_addr_t)EMAC1_BASE_ADDR, - .phy_interface = 0, - }, - - .pfe_ddr_addr = { - .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, - .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, - }, -}; - -static struct pfe_eth_pdata pfe_pdata1 = { - .pfe_eth_pdata_mac = { - .iobase = (phys_addr_t)EMAC2_BASE_ADDR, - .phy_interface = 1, - }, - - .pfe_ddr_addr = { - .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, - .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, - }, -}; - -U_BOOT_DRVINFO(ls1012a_pfe0) = { - .name = "pfe_eth", - .plat = &pfe_pdata0, -}; - -U_BOOT_DRVINFO(ls1012a_pfe1) = { - .name = "pfe_eth", - .plat = &pfe_pdata1, -}; diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c deleted file mode 100644 index ab69eab8408..00000000000 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ /dev/null @@ -1,411 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2021 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define BOOT_FROM_UPPER_BANK 0x2 -#define BOOT_FROM_LOWER_BANK 0x1 - -int checkboard(void) -{ -#ifdef CONFIG_TARGET_LS1012ARDB - u8 in1; - int ret, bus_num = 0; - - puts("Board: LS1012ARDB "); - - /* Initialize i2c early for Serial flash bank information */ -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return -ENXIO; - } - ret = dm_i2c_read(dev, I2C_MUX_IO_1, &in1, 1); -#else /* Non DM I2C support - will be removed */ - i2c_set_bus_num(bus_num); - ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1); -#endif - if (ret < 0) { - printf("Error reading i2c boot information!\n"); - return 0; /* Don't want to hang() on this error */ - } - - puts("Version"); - switch (in1 & SW_REV_MASK) { - case SW_REV_A: - puts(": RevA"); - break; - case SW_REV_B: - puts(": RevB"); - break; - case SW_REV_C: - puts(": RevC"); - break; - case SW_REV_C1: - puts(": RevC1"); - break; - case SW_REV_C2: - puts(": RevC2"); - break; - case SW_REV_D: - puts(": RevD"); - break; - case SW_REV_E: - puts(": RevE"); - break; - default: - puts(": unknown"); - break; - } - - printf(", boot from QSPI"); - if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU) - puts(": emu\n"); - else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1) - puts(": bank1\n"); - else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2) - puts(": bank2\n"); - else - puts("unknown\n"); -#else - - puts("Board: LS1012A2G5RDB "); -#endif - return 0; -} - -#ifdef CONFIG_TFABOOT -int dram_init(void) -{ - gd->ram_size = tfa_get_dram_size(); - if (!gd->ram_size) - gd->ram_size = CFG_SYS_SDRAM_SIZE; - - return 0; -} -#else -int dram_init(void) -{ -#ifndef CONFIG_TFABOOT - static const struct fsl_mmdc_info mparam = { - 0x05180000, /* mdctl */ - 0x00030035, /* mdpdc */ - 0x12554000, /* mdotc */ - 0xbabf7954, /* mdcfg0 */ - 0xdb328f64, /* mdcfg1 */ - 0x01ff00db, /* mdcfg2 */ - 0x00001680, /* mdmisc */ - 0x0f3c8000, /* mdref */ - 0x00002000, /* mdrwd */ - 0x00bf1023, /* mdor */ - 0x0000003f, /* mdasp */ - 0x0000022a, /* mpodtctrl */ - 0xa1390003, /* mpzqhwctrl */ - }; - - mmdc_init(&mparam); -#endif - - gd->ram_size = CFG_SYS_SDRAM_SIZE; -#if !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD) - /* This will break-before-make MMU for DDR */ - update_early_mmu_table(); -#endif - - return 0; -} -#endif - -int board_early_init_f(void) -{ - fsl_lsch2_early_init_f(); - - return 0; -} - -int board_init(void) -{ - struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + - CONFIG_SYS_CCI400_OFFSET); - /* - * Set CCI-400 control override register to enable barrier - * transaction - */ - if (current_el() == 3) - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); - -#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 - erratum_a010315(); -#endif - - return 0; -} - -#ifdef CONFIG_FSL_PFE -void board_quiesce_devices(void) -{ - pfe_command_stop(0, NULL); -} -#endif - -#ifdef CONFIG_TARGET_LS1012ARDB -int esdhc_status_fixup(void *blob, const char *compat) -{ - char esdhc1_path[] = "/soc/esdhc@1580000"; - bool sdhc2_en = false; - u8 mux_sdhc2; - u8 io = 0; - int ret, bus_num = 0; - -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return -ENXIO; - } - ret = dm_i2c_read(dev, I2C_MUX_IO_1, &io, 1); -#else - i2c_set_bus_num(bus_num); - /* IO1[7:3] is the field of board revision info. */ - ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1); -#endif - if (ret < 0) { - printf("Error reading i2c boot information!\n"); - return 0; - } - - /* hwconfig method is used for RevD and later versions. */ - if ((io & SW_REV_MASK) <= SW_REV_D) { -#ifdef CONFIG_HWCONFIG - if (hwconfig("esdhc1")) - sdhc2_en = true; -#endif - } else { - /* - * The I2C IO-expander for mux select is used to control - * the muxing of various onboard interfaces. - * - * IO0[3:2] indicates SDHC2 interface demultiplexer - * select lines. - * 00 - SDIO wifi - * 01 - GPIO (to Arduino) - * 10 - eMMC Memory - * 11 - SPI - */ -#if CONFIG_IS_ENABLED(DM_I2C) - ret = dm_i2c_read(dev, I2C_MUX_IO_0, &io, 1); -#else - ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1); -#endif - if (ret < 0) { - printf("Error reading i2c boot information!\n"); - return 0; - } - - mux_sdhc2 = (io & 0x0c) >> 2; - /* Enable SDHC2 only when use SDIO wifi and eMMC */ - if (mux_sdhc2 == 2 || mux_sdhc2 == 0) - sdhc2_en = true; - } - if (sdhc2_en) - do_fixup_by_path(blob, esdhc1_path, "status", "okay", - sizeof("okay"), 1); - else - do_fixup_by_path(blob, esdhc1_path, "status", "disabled", - sizeof("disabled"), 1); - return 0; -} -#endif - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - arch_fixup_fdt(blob); - - ft_cpu_setup(blob, bd); - - return 0; -} - -static int switch_to_bank1(void) -{ - u8 data = 0xf4, chip_addr = 0x24, offset_addr = 0x03; - int ret, bus_num = 0; - -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, chip_addr, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return -ENXIO; - } - /* - * -------------------------------------------------------------------- - * |bus |I2C address| Device | Notes | - * -------------------------------------------------------------------- - * |I2C1|0x24, 0x25,| IO expander (CFG,| Provides 16bits of General | - * | |0x26 | RESET, and INT/ | Purpose parallel Input/Output| - * | | | KW41GPIO) - NXP | (GPIO) expansion for the | - * | | | PCAL9555AHF | I2C bus | - * ----- -------------------------------------------------------------- - * - mount three IO expander(PCAL9555AHF) on I2C1 - * - * PCAL9555A device address - * slave address - * -------------------------------------- - * | 0 | 1 | 0 | 0 | A2 | A1 | A0 | R/W | - * -------------------------------------- - * | fixed | hardware selectable| - * - * Output port 1(Pinter register bits = 0x03) - * - * P1_[7~0] = 0xf4 - * P1_0 <---> CFG_MUX_QSPI_S0 - * P1_1 <---> CFG_MUX_QSPI_S1 - * CFG_MUX_QSPI_S[1:0] = 0b00 - * - * QSPI chip-select demultiplexer select - * --------------------------------------------------------------------- - * CFG_MUX_QSPI_S1|CFG_MUX_QSPI_S0| Values - * --------------------------------------------------------------------- - * 0 | 0 |CS routed to SPI memory bank1(default) - * --------------------------------------------------------------------- - * 0 | 1 |CS routed to SPI memory bank2 - * --------------------------------------------------------------------- - * - */ - ret = dm_i2c_write(dev, offset_addr, &data, 1); -#else /* Non DM I2C support - will be removed */ - i2c_set_bus_num(bus_num); - ret = i2c_write(chip_addr, offset_addr, 1, &data, 1); -#endif - - if (ret) { - printf("i2c write error to chip : %u, addr : %u, data : %u\n", - chip_addr, offset_addr, data); - } - - return ret; -} - -static int switch_to_bank2(void) -{ - u8 data[2] = {0xfc, 0xf5}, offset_addr[2] = {0x7, 0x3}; - u8 chip_addr = 0x24; - int ret, i, bus_num = 0; - -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, chip_addr, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return -ENXIO; - } -#else /* Non DM I2C support - will be removed */ - i2c_set_bus_num(bus_num); -#endif - - /* - * 1th step: config port 1 - * - the port 1 pin is enabled as an output - * 2th step: output port 1 - * - P1_[7:0] output 0xf5, - * then CFG_MUX_QSPI_S[1:0] equal to 0b01, - * CS routed to SPI memory bank2 - */ - for (i = 0; i < sizeof(data); i++) { -#if CONFIG_IS_ENABLED(DM_I2C) - ret = dm_i2c_write(dev, offset_addr[i], &data[i], 1); -#else /* Non DM I2C support - will be removed */ - ret = i2c_write(chip_addr, offset_addr[i], 1, &data[i], 1); -#endif - if (ret) { - printf("i2c write error to chip : %u, addr : %u, data : %u\n", - chip_addr, offset_addr[i], data[i]); - goto err; - } - } - -err: - return ret; -} - -static int convert_flash_bank(int bank) -{ - int ret = 0; - - switch (bank) { - case BOOT_FROM_UPPER_BANK: - ret = switch_to_bank2(); - break; - case BOOT_FROM_LOWER_BANK: - ret = switch_to_bank1(); - break; - default: - ret = CMD_RET_USAGE; - break; - }; - - return ret; -} - -static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - if (argc != 2) - return CMD_RET_USAGE; - if (strcmp(argv[1], "1") == 0) - convert_flash_bank(BOOT_FROM_LOWER_BANK); - else if (strcmp(argv[1], "2") == 0) - convert_flash_bank(BOOT_FROM_UPPER_BANK); - else - return CMD_RET_USAGE; - - return 0; -} - -U_BOOT_CMD( - boot_bank, 2, 0, flash_bank_cmd, - "Flash bank Selection Control", - "bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)" -); diff --git a/board/freescale/ls1021aiot/Kconfig b/board/freescale/ls1021aiot/Kconfig deleted file mode 100644 index 4a12c1687fc..00000000000 --- a/board/freescale/ls1021aiot/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_LS1021AIOT - -config SYS_BOARD - default "ls1021aiot" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "ls102xa" - -config SYS_CONFIG_NAME - default "ls1021aiot" - -endif diff --git a/board/freescale/ls1021aiot/MAINTAINERS b/board/freescale/ls1021aiot/MAINTAINERS deleted file mode 100644 index 65f21bee344..00000000000 --- a/board/freescale/ls1021aiot/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -LS1021AIOT BOARD -M: Alison Wang -S: Maintained -F: board/freescale/ls1021aiot/ -F: include/configs/ls1021aiot.h -F: configs/ls1021aiot_sdcard_defconfig -F: configs/ls1021aiot_qspi_defconfig diff --git a/board/freescale/ls1021aiot/Makefile b/board/freescale/ls1021aiot/Makefile deleted file mode 100644 index 587bbd79ddf..00000000000 --- a/board/freescale/ls1021aiot/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2016 Freescale Semiconductor, Inc. - -obj-y += ls1021aiot.o -obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021aiot/README b/board/freescale/ls1021aiot/README deleted file mode 100644 index 08b0268b9bd..00000000000 --- a/board/freescale/ls1021aiot/README +++ /dev/null @@ -1,58 +0,0 @@ -Overview --------- -The LS1021A-IOT is a Freescale reference board that hosts -the LS1021A SoC. - -LS1021AIOT board Overview -------------------------- - - DDR Controller - - Supports 1GB un-buffered DDR3L SDRAM discrete - devices(32-bit bus) with 4 bit ECC - - DDR power supplies 1.35V to all devices with - automatic tracking of VTT - - Soldered DDR chip - - Supprot one fixed speed - - Ethernet - - Two on-board SGMII 10/100/1G ethernet ports - - One Gbit Etherent RGMII interface to 4-ports switch - with 4x 10/100/1000 RJ145 ports - - CPLD - - 8-bit registers in CPLD for system configuration - - connected to IFC_AD[0:7] - - Power Supplies - - 12V@5A DC - - SDHC - - SDHC port connects directly to a full 8-bit SD/MMC slot - - Support for SDIO devices - - USB - - Two on-board USB 3.0 - - One on-board USB k22 - - PCIe - - Two MiniPCIe Solts - - SATA - - Support SATA Connector - - AUDIO - - AUDIO in and out - - I/O Expansion - - Arduino Shield Connector - - Port0 - CAN/GPIO/Flextimer - - Port1 - GPIO/CPLD Expansion - - Port2 - SPI/I2C/UART - -Memory map ------------ -The addresses in brackets are physical addresses. - -Start Address End Address Description Size -0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB -0x00_4000_0000 0x00_43FF_FFFF QSPI(Chip select 0) 64MB -0x00_4400_0000 0x00_47FF_FFFF QSPI(Chip select 1) 64MB -0x00_6000_0000 0x00_6000_FFFF CPLD 64K -0x00_8000_0000 0x00_BFFF_FFFF DDR 1GB - -Boot description ------------------ -LS1021A-IOT support two ways of boot: -Qspi boot and SD boot -The board doesn't support boot from another -source without changing any switch/jumper. diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c deleted file mode 100644 index 52a3c3abdb4..00000000000 --- a/board/freescale/ls1021aiot/ls1021aiot.c +++ /dev/null @@ -1,207 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2021 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include "../common/sleep.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define DDR_SIZE 0x40000000 - -int checkboard(void) -{ - puts("Board: LS1021AIOT\n"); - -#ifndef CONFIG_QSPI_BOOT - struct ccsr_gur *dcfg = (struct ccsr_gur *)CFG_SYS_FSL_GUTS_ADDR; - u32 cpldrev; - - cpldrev = in_be32(&dcfg->gpporcr1); - - printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) & - 0xf)); -#endif - return 0; -} - -void ddrmc_init(void) -{ - struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR; - u32 temp_sdram_cfg, tmp; - - out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); - - out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); - out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); - - out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); - out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); - out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); - out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); - out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); - out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); - - out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); - out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); - - out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); - out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); - - out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); - - out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); - - out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); - out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); - - out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); - - out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); - out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); - - out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); - - /* DDR erratum A-009942 */ - tmp = in_be32(&ddr->debug[28]); - out_be32(&ddr->debug[28], tmp | 0x0070006f); - - udelay(500); - - temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); - - out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); -} - -int dram_init(void) -{ -#if (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)) - ddrmc_init(); -#endif - - erratum_a008850_post(); - - gd->ram_size = DDR_SIZE; - return 0; -} - -int board_early_init_f(void) -{ - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; - -#ifdef CONFIG_TSEC_ENET - /* clear BD & FR bits for BE BD's and frame data */ - clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); - out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); - -#endif - -#ifdef CONFIG_FSL_IFC - init_early_memctl_regs(); -#endif - - arch_soc_init(); - - return 0; -} - -#ifdef CONFIG_XPL_BUILD -void board_init_f(ulong dummy) -{ - /* Clear the BSS */ - memset(__bss_start, 0, __bss_end - __bss_start); - - get_clocks(); - - preloader_console_init(); - - dram_init(); - - /* Allow OCRAM access permission as R/W */ - -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - - board_init_r(NULL, 0); -} -#endif - -int board_init(void) -{ -#ifndef CONFIG_SYS_FSL_NO_SERDES - fsl_serdes_init(); -#endif - - ls102xa_smmu_stream_id_init(); - - return 0; -} - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ - return 0; -} -#endif - -#if defined(CONFIG_MISC_INIT_R) -int misc_init_r(void) -{ -#ifdef CONFIG_FSL_DEVICE_DISABLE - device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); - -#endif - return 0; -} -#endif - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - - return 0; -} - -void flash_write16(u16 val, void *addr) -{ - u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); - - __raw_writew(shftval, addr); -} - -u16 flash_read16(void *addr) -{ - u16 val = __raw_readw(addr); - - return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); -} diff --git a/board/freescale/ls1021aiot/ls102xa_pbi.cfg b/board/freescale/ls1021aiot/ls102xa_pbi.cfg deleted file mode 100644 index b5ac5e27e9d..00000000000 --- a/board/freescale/ls1021aiot/ls102xa_pbi.cfg +++ /dev/null @@ -1,14 +0,0 @@ -#PBI commands - -09570200 ffffffff -09570158 00000300 -8940007c 21f47300 - -#Configure Scratch register -09ee0200 10000000 -#Configure alternate space -09570158 00001000 -#Flush PBL data -096100c0 000FFFFF - -09ea085c 00502880 diff --git a/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg b/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg deleted file mode 100644 index a1984c713d5..00000000000 --- a/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg +++ /dev/null @@ -1,27 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 -# serdes protocol - -#Default with 2 x SGMII (no SATA) -0608000a 00000000 00000000 00000000 -20000000 08407900 60025a00 21046000 -00000000 00000000 00000000 20038000 -20024800 881b1340 00000000 00000000 - -#SATA set-up -#0608000a 00000000 00000000 00000000 -#70000000 08007900 60025a00 21046000 -#00000000 00000000 00000000 20038000 -#20024800 881b1340 00000000 00000000 - -#HDMI set-up -#0608000a 00000000 00000000 00000000 -#20000000 08407900 60025a00 21046000 -#00000000 00000000 00000000 20038000 -#00000000 881b1340 00000000 00000000 - -#QE testing -#0608000a 00000000 00000000 00000000 -#20000000 08407900 60025a00 21046000 -#00000000 00000000 00000000 00038000 -#20094800 881b1340 00000000 00000000 diff --git a/board/freescale/ls1021aiot/psci.S b/board/freescale/ls1021aiot/psci.S deleted file mode 100644 index d0106ba3905..00000000000 --- a/board/freescale/ls1021aiot/psci.S +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 NXP Semiconductor. - * Author: Feng Li - */ - -#include -#include - -#include -#include - - .pushsection ._secure.text, "ax" - - .arch_extension sec - - .align 5 - -.globl psci_system_off -psci_system_off: -1: wfi - b 1b - -.globl psci_text_end -psci_text_end: - nop - .popsection diff --git a/board/freescale/ls1021aqds/Kconfig b/board/freescale/ls1021aqds/Kconfig deleted file mode 100644 index 119b9550410..00000000000 --- a/board/freescale/ls1021aqds/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_LS1021AQDS - -config SYS_BOARD - default "ls1021aqds" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "ls102xa" - -config SYS_CONFIG_NAME - default "ls1021aqds" - -endif diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS deleted file mode 100644 index 913d251eeb7..00000000000 --- a/board/freescale/ls1021aqds/MAINTAINERS +++ /dev/null @@ -1,14 +0,0 @@ -LS1021AQDS BOARD -M: Alison Wang -S: Maintained -F: board/freescale/ls1021aqds/ -F: include/configs/ls1021aqds.h -F: configs/ls1021aqds_nor_defconfig -F: configs/ls1021aqds_ddr4_nor_defconfig -F: configs/ls1021aqds_ddr4_nor_lpuart_defconfig -F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig -F: configs/ls1021aqds_nor_lpuart_defconfig -F: configs/ls1021aqds_sdcard_ifc_defconfig -F: configs/ls1021aqds_sdcard_qspi_defconfig -F: configs/ls1021aqds_qspi_defconfig -F: configs/ls1021aqds_nand_defconfig diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile deleted file mode 100644 index 8cbf33fa0ce..00000000000 --- a/board/freescale/ls1021aqds/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright 2014 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += ls1021aqds.o -obj-y += ddr.o -obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021aqds/README b/board/freescale/ls1021aqds/README deleted file mode 100644 index e2ce00165bd..00000000000 --- a/board/freescale/ls1021aqds/README +++ /dev/null @@ -1,117 +0,0 @@ -Overview --------- -The LS1021AQDS is a Freescale reference board that hosts the LS1021A SoC. - -LS1021A SoC Overview ------------------- -The QorIQ LS1 family, which includes the LS1021A communications processor, -is built on Layerscape architecture, the industry's first software-aware, -core-agnostic networking architecture to offer unprecedented efficiency -and scale. - -A member of the value-performance tier, the QorIQ LS1021A processor provides -extensive integration and power efficiency for fanless, small form factor -enterprise networking applications. Incorporating dual ARM Cortex-A7 cores -running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark -performance of over 6,000, as well as virtualization support, advanced -security features and the broadest array of high-speed interconnects and -optimized peripheral features ever offered in a sub-3 W processor. - -The QorIQ LS1021A processor features an integrated LCD controller, -CAN controller for implementing industrial protocols, DDR3L/4 running -up to 1600 MHz, integrated security engine and QUICC Engine, and ECC -protection on both L1 and L2 caches. The LS1021A processor is pin- and -software-compatible with the QorIQ LS1020A and LS1022A processors. - -The LS1021A SoC includes the following function and features: - - - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture - - Dual high-preformance ARM Cortex-A7 cores, each core includes: - - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection) - - 512 Kbyte shared coherent L2 Cache (with ECC protection) - - NEON Co-processor (per core) - - 40-bit physical addressing - - Vector floating-point support - - ARM Core-Link CCI-400 Cache Coherent Interconnect - - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration - supporting speeds up to 1600Mtps - - ECC and interleaving support - - VeTSEC Ethernet complex - - Up to 3x virtualized 10/100/1000 Ethernet controllers - - MII, RMII, RGMII, and SGMII support - - QoS, lossless flow control, and IEEE 1588 support - - 4-lane 6GHz SerDes - - High speed interconnect (4 SerDes lanes with are muxed for these protocol) - - Two PCI Express Gen2 controllers running at up to 5 GHz - - One Serial ATA 3.0 supporting 6 GT/s operation - - Two SGMII interfaces supporting 1000 Mbps - - Additional peripheral interfaces - - One high-speed USB 3.0 controller with integrated PHY and one high-speed - USB 2.00 controller with ULPI - - Integrated flash controller (IFC) with 16-bit interface - - Quad SPI NOR Flash - - One enhanced Secure digital host controller - - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface) - - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power - UARTs - - Three I2C controllers - - Eight FlexTimers four supporting PWM and four FlexCAN ports - - Four GPIO controllers supporting up to 109 general purpose I/O signals - - Integrated advanced audio block: - - Four synchronous audio interfaces (SAI) - - Sony/Philips Digital Interconnect Format (SPDIF) - - Asynchronous Sample Rate Converter (ASRC) - - Hardware based crypto offload engine - - IPSec forwarding at up to 1Gbps - - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported - - Public key hardware accelerator - - True Random Number Generator (NIST Certified) - - Advanced Encryption Standard Accelerators (AESA) - - Data Encryption Standard Accelerators - - QUICC Engine ULite block - - Two universal communication controllers (TDM and HDLC) supporting 64 - multichannels, each running at 64 Kbps - - Support for 256 channels of HDLC - - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported - -LS1021AQDS board Overview -------------------------- - - DDR Controller - - Supports rates of up to 1600 MHz data-rate - - Supports one DDR3LP UDIMM, of single-, dual- types. - - IFC/Local Bus - - NAND flash: 512M 8-bit NAND flash - - NOR: 128MB 16-bit NOR Flash - - Ethernet - - Three on-board RGMII 10/100/1G ethernet ports. - - FPGA - - Clocks - - System and DDR clock (SYSCLK, DDRCLK) - - SERDES clocks - - Power Supplies - - SDHC - - SDHC/SDXC connector - - Other IO - - Two Serial ports - - Three I2C ports - -Memory map ------------ -The addresses in brackets are physical addresses. - -Start Address End Address Description Size -0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB -0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB -0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB -0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB -0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB -0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB -0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB -0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB -0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB -0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB - -LS1021a rev1.0 Soc specific Options/Settings --------------------------------------------- -If the LS1021a Soc is rev1.0, you need modify the configuration and enable -CONFIG_SPL_SKIP_LOWLEVEL_INIT in menuconfig or similar. diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c deleted file mode 100644 index fd897e832c8..00000000000 --- a/board/freescale/ls1021aqds/ddr.c +++ /dev/null @@ -1,199 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 3) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - pbsp = udimms[0]; - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->cpo_override = pbsp->cpo_override; - popts->write_data_delay = - pbsp->write_data_delay; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for %lu MT/s\n", - ddr_freq); - printf("Trying to use the highest speed (%u) parameters\n", - pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); - - /* force DDR bus width to 32 bits */ - popts->data_bus_width = 1; - popts->otf_burst_chop_en = 0; - popts->burst_length = DDR_BL8; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 1; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - -#ifdef CONFIG_SYS_FSL_DDR4 - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | - DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ -#else - popts->cswl_override = DDR_CSWL_CS0; - - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x58; - - /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); -#endif -} - -#ifdef CONFIG_SYS_DDR_RAW_TIMING -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 1073741824u, - .capacity = 1073741824u, - .primary_sdram_width = 32, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 15, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 1071, - .caslat_x = 0xfe << 4, /* 5,6,7,8 */ - .taa_ps = 13125, - .twr_ps = 15000, - .trcd_ps = 13125, - .trrd_ps = 7500, - .trp_ps = 13125, - .tras_ps = 37500, - .trc_ps = 50625, - .trfc_ps = 160000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 37500, -}; - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - static const char dimm_model[] = "Fixed DDR on board"; - - if (((controller_number == 0) && (dimm_number == 0)) || - ((controller_number == 1) && (dimm_number == 0))) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} -#endif - -#if defined(CONFIG_DEEP_SLEEP) -void board_mem_sleep_setup(void) -{ - void __iomem *qixis_base = (void *)QIXIS_BASE; - - /* does not provide HW signals for power management */ - clrbits_8(qixis_base + 0x21, 0x2); - udelay(1); -} -#endif - -int fsl_initdram(void) -{ - phys_size_t dram_size; - -#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_SPL) - puts("Initializing DDR....using SPD\n"); - dram_size = fsl_ddr_sdram(); -#else - dram_size = fsl_ddr_sdram_size(); -#endif - -#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD) - fsl_dp_resume(); -#endif - - erratum_a008850_post(); - - gd->ram_size = dram_size; - - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; - - return 0; -} diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h deleted file mode 100644 index 58a88384367..00000000000 --- a/board/freescale/ls1021aqds/ddr.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ - -void erratum_a008850_post(void); - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; - u32 cpo_override; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | - */ -#ifdef CONFIG_SYS_FSL_DDR4 - {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, - {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 1666, 0, 8, 8, 0x090A0B0B, 0x0C0D0E0C,}, - {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, - {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,}, -#elif defined(CONFIG_SYS_FSL_DDR3) - {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, - {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, -#else -#error DDR type not defined -#endif - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -#endif diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c deleted file mode 100644 index 0bdd468d9a7..00000000000 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ /dev/null @@ -1,456 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2019, 2021 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/i2c_mux.h" -#include "../common/sleep.h" -#include "../common/qixis.h" -#include "ls1021aqds_qixis.h" -#ifdef CONFIG_U_QE -#include -#endif - -#define PIN_MUX_SEL_CAN 0x03 -#define PIN_MUX_SEL_IIC2 0xa0 -#define PIN_MUX_SEL_RGMII 0x00 -#define PIN_MUX_SEL_SAI 0x0c -#define PIN_MUX_SEL_SDHC 0x00 - -#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value) -#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value) -enum { - MUX_TYPE_CAN, - MUX_TYPE_IIC2, - MUX_TYPE_RGMII, - MUX_TYPE_SAI, - MUX_TYPE_SDHC, - MUX_TYPE_SD_PCI4, - MUX_TYPE_SD_PC_SA_SG_SG, - MUX_TYPE_SD_PC_SA_PC_SG, - MUX_TYPE_SD_PC_SG_SG, -}; - -enum { - GE0_CLK125, - GE2_CLK125, - GE1_CLK125, -}; - -int checkboard(void) -{ -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) - char buf[64]; -#endif -#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) - u8 sw; -#endif - - puts("Board: LS1021AQDS\n"); - -#ifdef CONFIG_SD_BOOT - puts("SD\n"); -#elif CONFIG_QSPI_BOOT - puts("QSPI\n"); -#else - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank: %d\n", sw); - else if (sw == 0x8) - puts("PromJet\n"); - else if (sw == 0x9) - puts("NAND\n"); - else if (sw == 0x15) - printf("IFCCard\n"); - else - printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); -#endif - -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) - printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", - QIXIS_READ(id), QIXIS_READ(arch)); - - printf("FPGA: v%d (%s), build %d\n", - (int)QIXIS_READ(scver), qixis_read_tag(buf), - (int)qixis_read_minor()); -#endif - - return 0; -} - -#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); - - switch (sysclk_conf & 0x0f) { - case QIXIS_SYSCLK_64: - return 64000000; - case QIXIS_SYSCLK_83: - return 83333333; - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - case QIXIS_SYSCLK_150: - return 150000000; - case QIXIS_SYSCLK_160: - return 160000000; - case QIXIS_SYSCLK_166: - return 166666666; - } - return 66666666; -} -#endif - -#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ -unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); - - switch ((ddrclk_conf & 0x30) >> 4) { - case QIXIS_DDRCLK_100: - return 100000000; - case QIXIS_DDRCLK_125: - return 125000000; - case QIXIS_DDRCLK_133: - return 133333333; - } - return 66666666; -} -#endif - -int dram_init(void) -{ - /* - * When resuming from deep sleep, the I2C channel may not be - * in the default channel. So, switch to the default channel - * before accessing DDR SPD. - * - * PCA9547(0x77) mount on I2C1 bus - */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - return fsl_initdram(); -} - -int board_early_init_f(void) -{ - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; - -#ifdef CONFIG_TSEC_ENET - /* clear BD & FR bits for BE BD's and frame data */ - clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); -#endif - -#ifdef CONFIG_FSL_IFC - init_early_memctl_regs(); -#endif - - arch_soc_init(); - -#if defined(CONFIG_DEEP_SLEEP) - if (is_warm_boot()) - fsl_dp_disable_console(); -#endif - - return 0; -} - -#ifdef CONFIG_XPL_BUILD -void board_init_f(ulong dummy) -{ -#ifdef CONFIG_NAND_BOOT - struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; - u32 porsr1, pinctl; - - /* - * There is LS1 SoC issue where NOR, FPGA are inaccessible during - * NAND boot because IFC signals > IFC_AD7 are not enabled. - * This workaround changes RCW source to make all signals enabled. - */ - porsr1 = in_be32(&gur->porsr1); - pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | - DCFG_CCSR_PORSR1_RCW_SRC_I2C); - out_be32((unsigned int *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), - pinctl); -#endif - - /* Clear the BSS */ - memset(__bss_start, 0, __bss_end - __bss_start); - -#ifdef CONFIG_FSL_IFC - init_early_memctl_regs(); -#endif - - get_clocks(); - -#if defined(CONFIG_DEEP_SLEEP) - if (is_warm_boot()) - fsl_dp_disable_console(); -#endif - - preloader_console_init(); - -#ifdef CONFIG_SPL_I2C - i2c_init_all(); -#endif - - timer_init(); - dram_init(); - - /* Allow OCRAM access permission as R/W */ -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - - board_init_r(NULL, 0); -} -#endif - -void config_etseccm_source(int etsec_gtx_125_mux) -{ - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; - - switch (etsec_gtx_125_mux) { - case GE0_CLK125: - out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125); - debug("etseccm set to GE0_CLK125\n"); - break; - - case GE2_CLK125: - out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); - debug("etseccm set to GE2_CLK125\n"); - break; - - case GE1_CLK125: - out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125); - debug("etseccm set to GE1_CLK125\n"); - break; - - default: - printf("Error! trying to set etseccm to invalid value\n"); - break; - } -} - -int config_board_mux(int ctrl_type) -{ - u8 reg12, reg14; - - reg12 = QIXIS_READ(brdcfg[12]); - reg14 = QIXIS_READ(brdcfg[14]); - - switch (ctrl_type) { - case MUX_TYPE_CAN: - config_etseccm_source(GE2_CLK125); - reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN); - break; - case MUX_TYPE_IIC2: - reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2); - break; - case MUX_TYPE_RGMII: - reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII); - break; - case MUX_TYPE_SAI: - config_etseccm_source(GE2_CLK125); - reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI); - break; - case MUX_TYPE_SDHC: - reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC); - break; - case MUX_TYPE_SD_PCI4: - reg12 = 0x38; - break; - case MUX_TYPE_SD_PC_SA_SG_SG: - reg12 = 0x01; - break; - case MUX_TYPE_SD_PC_SA_PC_SG: - reg12 = 0x01; - break; - case MUX_TYPE_SD_PC_SG_SG: - reg12 = 0x21; - break; - default: - printf("Wrong mux interface type\n"); - return -1; - } - - QIXIS_WRITE(brdcfg[12], reg12); - QIXIS_WRITE(brdcfg[14], reg14); - - return 0; -} - -int config_serdes_mux(void) -{ - struct ccsr_gur *gur = (struct ccsr_gur *)CFG_SYS_FSL_GUTS_ADDR; - u32 cfg; - - cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; - cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; - - switch (cfg) { - case 0x0: - config_board_mux(MUX_TYPE_SD_PCI4); - break; - case 0x30: - config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG); - break; - case 0x60: - config_board_mux(MUX_TYPE_SD_PC_SG_SG); - break; - case 0x70: - config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG); - break; - default: - printf("SRDS1 prtcl:0x%x\n", cfg); - break; - } - - return 0; -} - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ -#ifdef CONFIG_CHAIN_OF_TRUST - fsl_setenv_chain_of_trust(); -#endif - - return 0; -} -#endif - -int misc_init_r(void) -{ - int conflict_flag; - - /* some signals can not enable simultaneous*/ - conflict_flag = 0; - if (hwconfig("sdhc")) - conflict_flag++; - if (hwconfig("iic2")) - conflict_flag++; - if (conflict_flag > 1) { - printf("WARNING: pin conflict !\n"); - return 0; - } - - conflict_flag = 0; - if (hwconfig("rgmii")) - conflict_flag++; - if (hwconfig("can")) - conflict_flag++; - if (hwconfig("sai")) - conflict_flag++; - if (conflict_flag > 1) { - printf("WARNING: pin conflict !\n"); - return 0; - } - - if (hwconfig("can")) - config_board_mux(MUX_TYPE_CAN); - else if (hwconfig("rgmii")) - config_board_mux(MUX_TYPE_RGMII); - else if (hwconfig("sai")) - config_board_mux(MUX_TYPE_SAI); - - if (hwconfig("iic2")) - config_board_mux(MUX_TYPE_IIC2); - else if (hwconfig("sdhc")) - config_board_mux(MUX_TYPE_SDHC); - -#ifdef CONFIG_FSL_DEVICE_DISABLE - device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); -#endif - return 0; -} - -int board_init(void) -{ -#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 - erratum_a010315(); -#endif -#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 - erratum_a009942_check_cpo(); -#endif - - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - -#ifndef CONFIG_SYS_FSL_NO_SERDES - fsl_serdes_init(); - config_serdes_mux(); -#endif - - ls102xa_smmu_stream_id_init(); - -#ifdef CONFIG_U_QE - u_qe_init(); -#endif - - return 0; -} - -#if defined(CONFIG_DEEP_SLEEP) -void board_sleep_prepare(void) -{ -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif -} -#endif - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - - return 0; -} - -u8 flash_read8(void *addr) -{ - return __raw_readb(addr + 1); -} - -void flash_write16(u16 val, void *addr) -{ - u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); - - __raw_writew(shftval, addr); -} - -u16 flash_read16(void *addr) -{ - u16 val = __raw_readw(addr); - - return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); -} diff --git a/board/freescale/ls1021aqds/ls1021aqds_qixis.h b/board/freescale/ls1021aqds/ls1021aqds_qixis.h deleted file mode 100644 index 7ad08a54ea6..00000000000 --- a/board/freescale/ls1021aqds/ls1021aqds_qixis.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __LS1021AQDS_QIXIS_H__ -#define __LS1021AQDS_QIXIS_H__ - -/* Definitions of QIXIS Registers for LS1021AQDS */ - -/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ -#define BRDCFG4_EMISEL_MASK 0xe0 -#define BRDCFG4_EMISEL_SHIFT 5 - -/* SYSCLK */ -#define QIXIS_SYSCLK_66 0x0 -#define QIXIS_SYSCLK_83 0x1 -#define QIXIS_SYSCLK_100 0x2 -#define QIXIS_SYSCLK_125 0x3 -#define QIXIS_SYSCLK_133 0x4 -#define QIXIS_SYSCLK_150 0x5 -#define QIXIS_SYSCLK_160 0x6 -#define QIXIS_SYSCLK_166 0x7 -#define QIXIS_SYSCLK_64 0x8 - -/* DDRCLK */ -#define QIXIS_DDRCLK_66 0x0 -#define QIXIS_DDRCLK_100 0x1 -#define QIXIS_DDRCLK_125 0x2 -#define QIXIS_DDRCLK_133 0x3 - -#define QIXIS_SRDS1CLK_100 0x0 - -#define QIXIS_DCU_BRDCFG5 0x55 - -#endif diff --git a/board/freescale/ls1021aqds/ls102xa_pbi.cfg b/board/freescale/ls1021aqds/ls102xa_pbi.cfg deleted file mode 100644 index f1a1b63ab77..00000000000 --- a/board/freescale/ls1021aqds/ls102xa_pbi.cfg +++ /dev/null @@ -1,12 +0,0 @@ -#PBI commands - -09570200 ffffffff -09570158 00000300 -8940007c 21f47300 - -#Configure Scratch register -09ee0200 10000000 -#Configure alternate space -09570158 00001000 -#Flush PBL data -096100c0 000FFFFF diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg deleted file mode 100644 index d76e9132e35..00000000000 --- a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 -# serdes protocol -0608000c 00000000 00000000 00000000 -60000000 00407900 e0106a00 21046000 -00000000 00000000 00000000 00038000 -00000000 001b7200 00000000 00000000 diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg deleted file mode 100644 index f0cf9c2b38d..00000000000 --- a/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg +++ /dev/null @@ -1,14 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 - -#enable IFC, disable QSPI and DSPI -0608000c 00000000 00000000 00000000 -60000000 00407900 60040a00 21046000 -00000000 00000000 00000000 00038000 -00000000 001b7200 00000000 00000000 - -#disable IFC, enable QSPI and DSPI -#0608000c 00000000 00000000 00000000 -#60000000 00407900 60040a00 21046000 -#00000000 00000000 00000000 00038000 -#20024800 001b7200 00000000 00000000 diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg deleted file mode 100644 index 10cc4a9ab0b..00000000000 --- a/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg +++ /dev/null @@ -1,14 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 - -#enable IFC, disable QSPI and DSPI -#0608000c 00000000 00000000 00000000 -#60000000 00407900 60040a00 21046000 -#00000000 00000000 00000000 00038000 -#00000000 001b7200 00000000 00000000 - -#disable IFC, enable QSPI and DSPI -0608000c 00000000 00000000 00000000 -60000000 00407900 60040a00 21046000 -00000000 00000000 00000000 00038000 -20024800 001b7200 00000000 00000000 diff --git a/board/freescale/ls1021aqds/psci.S b/board/freescale/ls1021aqds/psci.S deleted file mode 100644 index 0f38c934ddf..00000000000 --- a/board/freescale/ls1021aqds/psci.S +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 NXP Semiconductor. - * Author: Wang Dongsheng - */ - -#include -#include - -#include -#include - - .pushsection ._secure.text, "ax" - - .arch_extension sec - - .align 5 - -.globl psci_system_off -psci_system_off: - @ Get QIXIS base address - movw r1, #(QIXIS_BASE & 0xffff) - movt r1, #(QIXIS_BASE >> 16) - - ldrb r2, [r1, #QIXIS_PWR_CTL] - orr r2, r2, #QIXIS_PWR_CTL_POWEROFF - strb r2, [r1, #QIXIS_PWR_CTL] - -1: wfi - b 1b - - .popsection diff --git a/board/freescale/ls1021atsn/Kconfig b/board/freescale/ls1021atsn/Kconfig deleted file mode 100644 index aa42a06c663..00000000000 --- a/board/freescale/ls1021atsn/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -if TARGET_LS1021ATSN - -config SYS_BOARD - default "ls1021atsn" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "ls102xa" - -config SYS_CONFIG_NAME - default "ls1021atsn" - -endif diff --git a/board/freescale/ls1021atsn/MAINTAINERS b/board/freescale/ls1021atsn/MAINTAINERS deleted file mode 100644 index 560bb615d2f..00000000000 --- a/board/freescale/ls1021atsn/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -NXP LS1021A-TSN Board -M: Vladimir Oltean -S: Maintained -F: arch/arm/dts/ls1021a-tsn.dts -F: board/freescale/ls1021atsn/ -F: include/configs/ls1021atsn.h -F: configs/ls1021atsn_qspi_defconfig -F: configs/ls1021atsn_sdcard_defconfig diff --git a/board/freescale/ls1021atsn/Makefile b/board/freescale/ls1021atsn/Makefile deleted file mode 100644 index b4808f05e8e..00000000000 --- a/board/freescale/ls1021atsn/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-y += ls1021atsn.o -obj-$(CONFIG_ARMV7_PSCI) += ../ls1021atwr/psci.o diff --git a/board/freescale/ls1021atsn/README.rst b/board/freescale/ls1021atsn/README.rst deleted file mode 100644 index cd12291d8aa..00000000000 --- a/board/freescale/ls1021atsn/README.rst +++ /dev/null @@ -1,97 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -LS1021A-TSN Board Overview -========================== - - - 1GB DDR3 at 800 MHz - - Spansion/Cypress 64 MB (Rev. A) / 32 MB (Rev. B and C) QSPI NOR flash - - Ethernet - - 2 SGMII 10/100/1G Ethernet ports (Atheros AR8031) - - One SJA1105T switch with 4 Ethernet ports (Broadcom BCM5464R) - - One internal RGMII port connected to the switch - - SDHC - - microSDHC/SDXC connector - - Other I/O - - One Serial port - - Arduino and expansion headers - - mPCIE slot - - SATA port - - USB3.0 port - -LS1021A Memory map -================== - -The addresses in brackets are physical addresses. - -============== ============== ============================== ======= -Start Address End Address Description Size -============== ============== ============================== ======= -0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB -0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB -0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB -0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB -0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB -0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB -0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB -0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB -============== ============== ============================== ======= - -Compiling and flashing -====================== - -The LS1021A-TSN board comes along with a microSD card with OpenIL U-Boot that -can be used to update its internal QSPI flash (which is empty out of the -factory). - -To compile and flash an SD card image:: - - make ls1021atsn_sdcard_defconfig && make -j 8 && sudo cp u-boot-with-spl-pbl.bin /srv/tftpboot/ - => tftp 0x82000000 u-boot-with-spl-pbl.bin && mmc rescan && mmc erase 8 0x1100 && mmc write 0x82000000 8 0x1100 - -For the QSPI flash, first obtain the Reset Configuration Word binary for -bootimg from the QSPI flash from the rcw project -(https://github.com/nxp-qoriq/rcw):: - - make -j 8 && sudo cp ls1021atsn/SSR_PNS_30/rcw_1200_qspiboot.bin.swapped /srv/tftpboot/ - -The above RCW binary takes care of swapping the QSPI AMBA memory, so that the -U-Boot binary does not need to be swapped when flashing it. - -To compile and flash a U-Boot image for QSPI:: - - make ls1021atsn_qspi_defconfig && make -j 8 && sudo cp u-boot.bin /srv/tftpboot/ - -Then optionally create a custom uboot-env.txt file (although the default -environment already supports distro boot) and convert it to binary format:: - - mkenvimage -s 2M -o /srv/tftpboot/uboot-env.bin uboot-env.txt - -To program the QSPI flash with the images:: - - => tftp 0x82000000 rcw_1200_qspiboot.bin.swapped && sf probe && sf erase 0x0 +${filesize} && sf write 0x82000000 0x0 ${filesize} - => tftp 0x82000000 u-boot.bin && sf probe && sf erase 0x100000 +${filesize} && sf write 0x82000000 0x100000 ${filesize} - => tftp 0x82000000 uboot-env.bin && sf probe && sf erase 0x400000 +${filesize} && sf write 0x82000000 0x400000 ${filesize} - -The boards contain an AT24 I2C EEPROM that is supposed to hold the MAC -addresses of the Ethernet interfaces, however the EEPROM comes blank out of -the factory, and the MAC addresses are printed on a label on the bottom of -the boards. - -To write the MAC addresses to the EEPROM, the following needs to be done once:: - - => mac id - => mac 0 00:1F:7B:xx:xx:xx - => mac 1 00:1F:7B:xx:xx:xx - => mac 2 00:1F:7B:xx:xx:xx - => mac save - -The switch ports do not have their own MAC address - they inherit it from the -master enet2 port. - -Known issues and limitations -============================ - -- The 4 SJA1105 switch ports are not functional in U-Boot for now. -- Since the IFC pins are multiplexed with QSPI on LS1021A, currently there is - no way to talk to the CPLD for e.g. running the "qixis_reset" command, or - turning the fan on, etc. diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c deleted file mode 100644 index c92430c0896..00000000000 --- a/board/freescale/ls1021atsn/ls1021atsn.c +++ /dev/null @@ -1,264 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright 2016-2019, 2021 NXP - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/sleep.h" -#include -#include -#include -#include -#include -#ifdef CONFIG_U_QE -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -static void ddrmc_init(void) -{ -#if (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)) - struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR; - u32 temp_sdram_cfg, tmp; - - out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); - - out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); - out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); - - out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); - out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); - out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); - out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); - out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); - out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); - -#ifdef CONFIG_DEEP_SLEEP - if (is_warm_boot()) { - out_be32(&ddr->sdram_cfg_2, - DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT); - out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); - out_be32(&ddr->init_ext_addr, (1 << 31)); - - /* DRAM VRef will not be trained */ - out_be32(&ddr->ddr_cdr2, - DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN); - } else -#endif - { - out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); - out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); - } - - out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); - out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); - - out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); - - out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); - - out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); - out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); - - out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); - - out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); - out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); - - out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); - - /* DDR erratum A-009942 */ - tmp = in_be32(&ddr->debug[28]); - out_be32(&ddr->debug[28], tmp | 0x0070006f); - - udelay(1); - -#ifdef CONFIG_DEEP_SLEEP - if (is_warm_boot()) { - /* enter self-refresh */ - temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); - temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; - out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); - - temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI); - } else -#endif - temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); - - out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); - -#ifdef CONFIG_DEEP_SLEEP - if (is_warm_boot()) { - /* exit self-refresh */ - temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); - temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; - out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); - } -#endif -#endif /* !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD) */ -} - -int dram_init(void) -{ - ddrmc_init(); - - erratum_a008850_post(); - - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - -#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD) - fsl_dp_resume(); -#endif - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - return pci_eth_init(bis); -} - -int board_early_init_f(void) -{ - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; - -#ifdef CONFIG_TSEC_ENET - /* - * Clear BD & FR bits for big endian BD's and frame data (aka set - * correct eTSEC endianness). This is crucial in ensuring that it does - * not report Data Parity Errors in its RX/TX FIFOs when attempting to - * send traffic. - */ - clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); - /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */ - out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); -#endif - - arch_soc_init(); - -#if defined(CONFIG_DEEP_SLEEP) - if (is_warm_boot()) { - timer_init(); - dram_init(); - } -#endif - - return 0; -} - -#ifdef CONFIG_XPL_BUILD -void board_init_f(ulong dummy) -{ - void (*second_uboot)(void); - - /* Clear the BSS */ - memset(__bss_start, 0, __bss_end - __bss_start); - - get_clocks(); - - if (CONFIG_IS_ENABLED(DEEP_SLEEP)) - if (is_warm_boot()) - fsl_dp_disable_console(); - - preloader_console_init(); - - dram_init(); - - /* Allow OCRAM access permission as R/W */ -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); - enable_layerscape_ns_access(); -#endif - - /* - * if it is woken up from deep sleep, then jump to second - * stage U-Boot and continue executing without recopying - * it from SD since it has already been reserved in memory - * in last boot. - */ - if (CONFIG_IS_ENABLED(DEEP_SLEEP)) { - if (is_warm_boot()) { - second_uboot = (void (*)(void))CONFIG_TEXT_BASE; - second_uboot(); - } - } - - board_init_r(NULL, 0); -} -#endif - -int board_init(void) -{ -#ifndef CONFIG_SYS_FSL_NO_SERDES - fsl_serdes_init(); -#endif - ls102xa_smmu_stream_id_init(); - -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - -#ifdef CONFIG_U_QE - u_qe_init(); -#endif - - return 0; -} - -#if defined(CONFIG_XPL_BUILD) -void spl_board_init(void) -{ - ls102xa_smmu_stream_id_init(); -} -#endif - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ -#ifdef CONFIG_CHAIN_OF_TRUST - fsl_setenv_chain_of_trust(); -#endif - - return 0; -} -#endif - -#if defined(CONFIG_MISC_INIT_R) -int misc_init_r(void) -{ -#ifdef CONFIG_FSL_DEVICE_DISABLE - device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); -#endif - return 0; -} -#endif - -#if defined(CONFIG_DEEP_SLEEP) -void board_sleep_prepare(void) -{ -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif -} -#endif - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - - return 0; -} diff --git a/board/freescale/ls1021atsn/ls102xa_pbi.cfg b/board/freescale/ls1021atsn/ls102xa_pbi.cfg deleted file mode 100644 index ba1499b2644..00000000000 --- a/board/freescale/ls1021atsn/ls102xa_pbi.cfg +++ /dev/null @@ -1,15 +0,0 @@ -# PBI commands - -09570200 ffffffff -09570158 00000300 -8940007c 21f47300 - -# Configure Scratch register -09ee0200 10000000 -# Configure alternate space -09570158 00001000 -# Flush PBL data -096100c0 000FFFFF - -09ea085c 00502880 -09ea0560 80800000 diff --git a/board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg b/board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg deleted file mode 100644 index a6fc91436f2..00000000000 --- a/board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg +++ /dev/null @@ -1,8 +0,0 @@ -# PBL preamble and RCW header -aa55aa55 01ee0100 - -# Disable IFC, enable QSPI and DSPI -0608000c 00000000 00000000 00000000 -30000000 08007900 40105a00 21046000 -00000000 00000000 00000000 10002000 -20124801 8804b340 00000000 00000000 diff --git a/board/freescale/ls1021atwr/Kconfig b/board/freescale/ls1021atwr/Kconfig deleted file mode 100644 index bc50b8d9668..00000000000 --- a/board/freescale/ls1021atwr/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_LS1021ATWR - -config SYS_BOARD - default "ls1021atwr" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "ls102xa" - -config SYS_CONFIG_NAME - default "ls1021atwr" - -endif diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS deleted file mode 100644 index 7ab8347e9ed..00000000000 --- a/board/freescale/ls1021atwr/MAINTAINERS +++ /dev/null @@ -1,12 +0,0 @@ -LS1021ATWR BOARD -M: Alison Wang -S: Maintained -F: board/freescale/ls1021atwr/ -F: include/configs/ls1021atwr.h -F: configs/ls1021atwr_nor_defconfig -F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig -F: configs/ls1021atwr_nor_lpuart_defconfig -F: configs/ls1021atwr_sdcard_ifc_defconfig -F: configs/ls1021atwr_sdcard_qspi_defconfig -F: configs/ls1021atwr_qspi_defconfig -F: configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile deleted file mode 100644 index cfa6c0c8540..00000000000 --- a/board/freescale/ls1021atwr/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2014 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += ls1021atwr.o -obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021atwr/README b/board/freescale/ls1021atwr/README deleted file mode 100644 index a4639cd7476..00000000000 --- a/board/freescale/ls1021atwr/README +++ /dev/null @@ -1,114 +0,0 @@ -Overview --------- -The LS1021ATWR is a Freescale reference board that hosts the LS1021A SoC. - -LS1021A SoC Overview ------------------- -The QorIQ LS1 family, which includes the LS1021A communications processor, -is built on Layerscape architecture, the industry's first software-aware, -core-agnostic networking architecture to offer unprecedented efficiency -and scale. - -A member of the value-performance tier, the QorIQ LS1021A processor provides -extensive integration and power efficiency for fanless, small form factor -enterprise networking applications. Incorporating dual ARM Cortex-A7 cores -running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark -performance of over 6,000, as well as virtualization support, advanced -security features and the broadest array of high-speed interconnects and -optimized peripheral features ever offered in a sub-3 W processor. - -The QorIQ LS1021A processor features an integrated LCD controller, -CAN controller for implementing industrial protocols, DDR3L/4 running -up to 1600 MHz, integrated security engine and QUICC Engine, and ECC -protection on both L1 and L2 caches. The LS1021A processor is pin- and -software-compatible with the QorIQ LS1020A and LS1022A processors. - -The LS1021A SoC includes the following function and features: - - - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture - - Dual high-preformance ARM Cortex-A7 cores, each core includes: - - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection) - - 512 Kbyte shared coherent L2 Cache (with ECC protection) - - NEON Co-processor (per core) - - 40-bit physical addressing - - Vector floating-point support - - ARM Core-Link CCI-400 Cache Coherent Interconnect - - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration - supporting speeds up to 1600Mtps - - ECC and interleaving support - - VeTSEC Ethernet complex - - Up to 3x virtualized 10/100/1000 Ethernet controllers - - MII, RMII, RGMII, and SGMII support - - QoS, lossless flow control, and IEEE 1588 support - - 4-lane 6GHz SerDes - - High speed interconnect (4 SerDes lanes with are muxed for these protocol) - - Two PCI Express Gen2 controllers running at up to 5 GHz - - One Serial ATA 3.0 supporting 6 GT/s operation - - Two SGMII interfaces supporting 1000 Mbps - - Additional peripheral interfaces - - One high-speed USB 3.0 controller with integrated PHY and one high-speed - USB 2.00 controller with ULPI - - Integrated flash controller (IFC) with 16-bit interface - - Quad SPI NOR Flash - - One enhanced Secure digital host controller - - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface) - - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power - UARTs - - Three I2C controllers - - Eight FlexTimers four supporting PWM and four FlexCAN ports - - Four GPIO controllers supporting up to 109 general purpose I/O signals - - Integrated advanced audio block: - - Four synchronous audio interfaces (SAI) - - Sony/Philips Digital Interconnect Format (SPDIF) - - Asynchronous Sample Rate Converter (ASRC) - - Hardware based crypto offload engine - - IPSec forwarding at up to 1Gbps - - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported - - Public key hardware accelerator - - True Random Number Generator (NIST Certified) - - Advanced Encryption Standard Accelerators (AESA) - - Data Encryption Standard Accelerators - - QUICC Engine ULite block - - Two universal communication controllers (TDM and HDLC) supporting 64 - multichannels, each running at 64 Kbps - - Support for 256 channels of HDLC - - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported - -LS1021ATWR board Overview -------------------------- - - DDR Controller - - Supports rates of up to 1600 MHz data-rate - - Supports one DDR3LP SDRAM. - - IFC/Local Bus - - NOR: 128MB 16-bit NOR Flash - - Ethernet - - Three on-board RGMII 10/100/1G ethernet ports. - - CPLD - - Clocks - - System and DDR clock (SYSCLK, DDRCLK) - - SERDES clocks - - Power Supplies - - SDHC - - SDHC/SDXC connector - - Other IO - - One Serial port - - Three I2C ports - -Memory map ------------ -The addresses in brackets are physical addresses. - -Start Address End Address Description Size -0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB -0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB -0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB -0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB -0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB -0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB -0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB -0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB - -LS1021a rev1.0 Soc specific Options/Settings --------------------------------------------- -If the LS1021a Soc is rev1.0, you need modify the configuration and enable -CONFIG_SPL_SKIP_LOWLEVEL_INIT in menuconfig or similar. diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c deleted file mode 100644 index 0758e5eae25..00000000000 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ /dev/null @@ -1,753 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2019, 2021-2022 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/sleep.h" -#ifdef CONFIG_U_QE -#include -#endif -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define VERSION_MASK 0x00FF -#define BANK_MASK 0x0001 -#define CFG_RESET 0x1 -#define INIT_RESET 0x1 - -#define CPLD_SET_MUX_SERDES 0x20 -#define CPLD_SET_BOOT_BANK 0x40 - -#define BOOT_FROM_UPPER_BANK 0x0 -#define BOOT_FROM_LOWER_BANK 0x1 - -#define LANEB_SATA (0x01) -#define LANEB_SGMII1 (0x02) -#define LANEC_SGMII1 (0x04) -#define LANEC_PCIEX1 (0x08) -#define LANED_PCIEX2 (0x10) -#define LANED_SGMII2 (0x20) - -#define MASK_LANE_B 0x1 -#define MASK_LANE_C 0x2 -#define MASK_LANE_D 0x4 -#define MASK_SGMII 0x8 - -#define KEEP_STATUS 0x0 -#define NEED_RESET 0x1 - -#define SOFT_MUX_ON_I2C3_IFC 0x2 -#define SOFT_MUX_ON_CAN3_USB2 0x8 -#define SOFT_MUX_ON_QE_LCD 0x10 - -#define PIN_I2C3_IFC_MUX_I2C3 0x0 -#define PIN_I2C3_IFC_MUX_IFC 0x1 -#define PIN_CAN3_USB2_MUX_USB2 0x0 -#define PIN_CAN3_USB2_MUX_CAN3 0x1 -#define PIN_QE_LCD_MUX_LCD 0x0 -#define PIN_QE_LCD_MUX_QE 0x1 - -struct cpld_data { - u8 cpld_ver; /* cpld revision */ - u8 cpld_ver_sub; /* cpld sub revision */ - u8 pcba_ver; /* pcb revision number */ - u8 system_rst; /* reset system by cpld */ - u8 soft_mux_on; /* CPLD override physical switches Enable */ - u8 cfg_rcw_src1; /* Reset config word 1 */ - u8 cfg_rcw_src2; /* Reset config word 2 */ - u8 vbank; /* Flash bank selection Control */ - u8 gpio; /* GPIO for TWR-ELEV */ - u8 i2c3_ifc_mux; - u8 mux_spi2; - u8 can3_usb2_mux; /* CAN3 and USB2 Selection */ - u8 qe_lcd_mux; /* QE and LCD Selection */ - u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */ - u8 global_rst; /* reset with init CPLD reg to default */ - u8 rev1; /* Reserved */ - u8 rev2; /* Reserved */ -}; - -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -static void cpld_show(void) -{ - struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); - - printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n", - in_8(&cpld_data->cpld_ver) & VERSION_MASK, - in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK, - in_8(&cpld_data->pcba_ver) & VERSION_MASK, - in_8(&cpld_data->vbank) & BANK_MASK); - -#ifdef DEBUG - printf("soft_mux_on =%x\n", - in_8(&cpld_data->soft_mux_on)); - printf("cfg_rcw_src1 =%x\n", - in_8(&cpld_data->cfg_rcw_src1)); - printf("cfg_rcw_src2 =%x\n", - in_8(&cpld_data->cfg_rcw_src2)); - printf("vbank =%x\n", - in_8(&cpld_data->vbank)); - printf("gpio =%x\n", - in_8(&cpld_data->gpio)); - printf("i2c3_ifc_mux =%x\n", - in_8(&cpld_data->i2c3_ifc_mux)); - printf("mux_spi2 =%x\n", - in_8(&cpld_data->mux_spi2)); - printf("can3_usb2_mux =%x\n", - in_8(&cpld_data->can3_usb2_mux)); - printf("qe_lcd_mux =%x\n", - in_8(&cpld_data->qe_lcd_mux)); - printf("serdes_mux =%x\n", - in_8(&cpld_data->serdes_mux)); -#endif -} -#endif - -int checkboard(void) -{ - puts("Board: LS1021ATWR\n"); -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) - cpld_show(); -#endif - - return 0; -} - -void ddrmc_init(void) -{ - struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR; - u32 temp_sdram_cfg, tmp; - - out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); - - out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); - out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); - - out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); - out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); - out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); - out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); - out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); - out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); - -#ifdef CONFIG_DEEP_SLEEP - if (is_warm_boot()) { - out_be32(&ddr->sdram_cfg_2, - DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT); - out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); - out_be32(&ddr->init_ext_addr, (1 << 31)); - - /* DRAM VRef will not be trained */ - out_be32(&ddr->ddr_cdr2, - DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN); - } else -#endif - { - out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); - out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); - } - - out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); - out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); - - out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); - - out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); - - out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); - out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); - - out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); - - out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); - out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); - - out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); - - /* DDR erratum A-009942 */ - tmp = in_be32(&ddr->debug[28]); - out_be32(&ddr->debug[28], tmp | 0x0070006f); - - udelay(1); - -#ifdef CONFIG_DEEP_SLEEP - if (is_warm_boot()) { - /* enter self-refresh */ - temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); - temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; - out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); - - temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI); - } else -#endif - temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); - - out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); - -#ifdef CONFIG_DEEP_SLEEP - if (is_warm_boot()) { - /* exit self-refresh */ - temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); - temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; - out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); - } -#endif -} - -int dram_init(void) -{ -#if (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)) - ddrmc_init(); -#endif - - erratum_a008850_post(); - - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - -#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD) - fsl_dp_resume(); -#endif - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - return pci_eth_init(bis); -} - -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -static void convert_serdes_mux(int type, int need_reset) -{ - char current_serdes; - struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); - - current_serdes = cpld_data->serdes_mux; - - switch (type) { - case LANEB_SATA: - current_serdes &= ~MASK_LANE_B; - break; - case LANEB_SGMII1: - current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C); - break; - case LANEC_SGMII1: - current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C); - break; - case LANED_SGMII2: - current_serdes |= MASK_LANE_D; - break; - case LANEC_PCIEX1: - current_serdes |= MASK_LANE_C; - break; - case (LANED_PCIEX2 | LANEC_PCIEX1): - current_serdes |= MASK_LANE_C; - current_serdes &= ~MASK_LANE_D; - break; - default: - printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type); - return; - } - - cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES; - cpld_data->serdes_mux = current_serdes; - - if (need_reset == 1) { - printf("Reset board to enable configuration\n"); - cpld_data->system_rst = CFG_RESET; - } -} - -int config_serdes_mux(void) -{ - struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; - - protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT; - switch (protocol) { - case 0x10: - convert_serdes_mux(LANEB_SATA, KEEP_STATUS); - convert_serdes_mux(LANED_PCIEX2 | - LANEC_PCIEX1, KEEP_STATUS); - break; - case 0x20: - convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS); - convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); - convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); - break; - case 0x30: - convert_serdes_mux(LANEB_SATA, KEEP_STATUS); - convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS); - convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); - break; - case 0x70: - convert_serdes_mux(LANEB_SATA, KEEP_STATUS); - convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); - convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); - break; - } - - return 0; -} -#endif - -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -int config_board_mux(void) -{ - struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); - int conflict_flag; - - conflict_flag = 0; - if (hwconfig("i2c3")) { - conflict_flag++; - cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC; - cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3; - } - - if (hwconfig("ifc")) { - conflict_flag++; - /* some signals can not enable simultaneous*/ - if (conflict_flag > 1) - goto conflict; - cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC; - cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC; - } - - conflict_flag = 0; - if (hwconfig("usb2")) { - conflict_flag++; - cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2; - cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2; - } - - if (hwconfig("can3")) { - conflict_flag++; - /* some signals can not enable simultaneous*/ - if (conflict_flag > 1) - goto conflict; - cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2; - cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3; - } - - conflict_flag = 0; - if (hwconfig("lcd")) { - conflict_flag++; - cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD; - cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD; - } - - if (hwconfig("qe")) { - conflict_flag++; - /* some signals can not enable simultaneous*/ - if (conflict_flag > 1) - goto conflict; - cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD; - cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE; - } - - return 0; - -conflict: - printf("WARNING: pin conflict! MUX setting may failed!\n"); - return 0; -} -#endif - -int board_early_init_f(void) -{ - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; - -#ifdef CONFIG_TSEC_ENET - /* clear BD & FR bits for BE BD's and frame data */ - clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); - out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); -#endif - -#ifdef CONFIG_FSL_IFC - init_early_memctl_regs(); -#endif - - arch_soc_init(); - -#if defined(CONFIG_DEEP_SLEEP) - if (is_warm_boot()) { - timer_init(); - dram_init(); - } -#endif - - return 0; -} - -#ifdef CONFIG_XPL_BUILD -void board_init_f(ulong dummy) -{ - void (*second_uboot)(void); - - /* Clear the BSS */ - memset(__bss_start, 0, __bss_end - __bss_start); - - get_clocks(); - - if (CONFIG_IS_ENABLED(DEEP_SLEEP)) - if (is_warm_boot()) - fsl_dp_disable_console(); - - preloader_console_init(); - - timer_init(); - dram_init(); - - /* Allow OCRAM access permission as R/W */ -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif - - /* - * if it is woken up from deep sleep, then jump to second - * stage uboot and continue executing without recopying - * it from SD since it has already been reserved in memeory - * in last boot. - */ - if (CONFIG_IS_ENABLED(DEEP_SLEEP)) { - if (is_warm_boot()) { - second_uboot = (void (*)(void))CONFIG_TEXT_BASE; - second_uboot(); - } - } - - board_init_r(NULL, 0); -} -#endif - -#ifdef CONFIG_DEEP_SLEEP -/* program the regulator (MC34VR500) to support deep sleep */ -void ls1twr_program_regulator(void) -{ - u8 i2c_device_id; - -#define LS1TWR_I2C_BUS_MC34VR500 1 -#define MC34VR500_ADDR 0x8 -#define MC34VR500_DEVICEID 0x4 -#define MC34VR500_DEVICEID_MASK 0x0f -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(LS1TWR_I2C_BUS_MC34VR500, MC34VR500_ADDR, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - LS1TWR_I2C_BUS_MC34VR500); - return; - } - i2c_device_id = dm_i2c_reg_read(dev, 0x0) & - MC34VR500_DEVICEID_MASK; - if (i2c_device_id != MC34VR500_DEVICEID) { - printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n"); - return; - } - - dm_i2c_reg_write(dev, 0x31, 0x4); - dm_i2c_reg_write(dev, 0x4d, 0x4); - dm_i2c_reg_write(dev, 0x6d, 0x38); - dm_i2c_reg_write(dev, 0x6f, 0x37); - dm_i2c_reg_write(dev, 0x71, 0x30); -#else - unsigned int i2c_bus; - i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500); - i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) & - MC34VR500_DEVICEID_MASK; - if (i2c_device_id != MC34VR500_DEVICEID) { - printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n"); - return; - } - - i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4); - i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4); - i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38); - i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37); - i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30); - - i2c_set_bus_num(i2c_bus); -#endif -} -#endif - -int board_init(void) -{ -#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 - erratum_a010315(); -#endif - -#ifndef CONFIG_SYS_FSL_NO_SERDES - fsl_serdes_init(); -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) - config_serdes_mux(); -#endif -#endif - - ls102xa_smmu_stream_id_init(); - -#ifdef CONFIG_U_QE - u_qe_init(); -#endif - -#ifdef CONFIG_DEEP_SLEEP - ls1twr_program_regulator(); -#endif - return 0; -} - -#if defined(CONFIG_XPL_BUILD) -void spl_board_init(void) -{ - if (IS_ENABLED(CONFIG_FSL_CAAM)) { - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); - if (ret) - printf("Failed to initialize caam_jr: %d\n", ret); - } - - ls102xa_smmu_stream_id_init(); -} -#endif - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ -#ifdef CONFIG_CHAIN_OF_TRUST - fsl_setenv_chain_of_trust(); -#endif - - return 0; -} -#endif - -#if defined(CONFIG_MISC_INIT_R) -int misc_init_r(void) -{ -#ifdef CONFIG_FSL_DEVICE_DISABLE - device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); -#endif -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) - config_board_mux(); -#endif - return 0; -} -#endif - -#if defined(CONFIG_DEEP_SLEEP) -void board_sleep_prepare(void) -{ -#ifdef CONFIG_LAYERSCAPE_NS_ACCESS - enable_layerscape_ns_access(); -#endif -} -#endif - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - - return 0; -} - -u8 flash_read8(void *addr) -{ - return __raw_readb(addr + 1); -} - -void flash_write16(u16 val, void *addr) -{ - u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); - - __raw_writew(shftval, addr); -} - -u16 flash_read16(void *addr) -{ - u16 val = __raw_readw(addr); - - return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); -} - -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \ - && !defined(CONFIG_XPL_BUILD) -static void convert_flash_bank(char bank) -{ - struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); - - printf("Now switch to boot from flash bank %d.\n", bank); - cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK; - cpld_data->vbank = bank; - - printf("Reset board to enable configuration.\n"); - cpld_data->system_rst = CFG_RESET; -} - -static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - if (argc != 2) - return CMD_RET_USAGE; - if (strcmp(argv[1], "0") == 0) - convert_flash_bank(BOOT_FROM_UPPER_BANK); - else if (strcmp(argv[1], "1") == 0) - convert_flash_bank(BOOT_FROM_LOWER_BANK); - else - return CMD_RET_USAGE; - - return 0; -} - -U_BOOT_CMD( - boot_bank, 2, 0, flash_bank_cmd, - "Flash bank Selection Control", - "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)" -); - -static int cpld_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); - - if (argc > 2) - return CMD_RET_USAGE; - if ((argc == 1) || (strcmp(argv[1], "conf") == 0)) - cpld_data->system_rst = CFG_RESET; - else if (strcmp(argv[1], "init") == 0) - cpld_data->global_rst = INIT_RESET; - else - return CMD_RET_USAGE; - - return 0; -} - -U_BOOT_CMD( - cpld_reset, 2, 0, cpld_reset_cmd, - "Reset via CPLD", - "conf\n" - " -reset with current CPLD configuration\n" - "init\n" - " -reset and initial CPLD configuration with default value" - -); - -static void print_serdes_mux(void) -{ - char current_serdes; - struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); - - current_serdes = cpld_data->serdes_mux; - - printf("Serdes Lane B: "); - if ((current_serdes & MASK_LANE_B) == 0) - printf("SATA,\n"); - else - printf("SGMII 1,\n"); - - printf("Serdes Lane C: "); - if ((current_serdes & MASK_LANE_C) == 0) - printf("SGMII 1,\n"); - else - printf("PCIe,\n"); - - printf("Serdes Lane D: "); - if ((current_serdes & MASK_LANE_D) == 0) - printf("PCIe,\n"); - else - printf("SGMII 2,\n"); - - printf("SGMII 1 is on lane "); - if ((current_serdes & MASK_SGMII) == 0) - printf("C.\n"); - else - printf("B.\n"); -} - -static int serdes_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - if (argc != 2) - return CMD_RET_USAGE; - if (strcmp(argv[1], "sata") == 0) { - printf("Set serdes lane B to SATA.\n"); - convert_serdes_mux(LANEB_SATA, NEED_RESET); - } else if (strcmp(argv[1], "sgmii1b") == 0) { - printf("Set serdes lane B to SGMII 1.\n"); - convert_serdes_mux(LANEB_SGMII1, NEED_RESET); - } else if (strcmp(argv[1], "sgmii1c") == 0) { - printf("Set serdes lane C to SGMII 1.\n"); - convert_serdes_mux(LANEC_SGMII1, NEED_RESET); - } else if (strcmp(argv[1], "sgmii2") == 0) { - printf("Set serdes lane D to SGMII 2.\n"); - convert_serdes_mux(LANED_SGMII2, NEED_RESET); - } else if (strcmp(argv[1], "pciex1") == 0) { - printf("Set serdes lane C to PCIe X1.\n"); - convert_serdes_mux(LANEC_PCIEX1, NEED_RESET); - } else if (strcmp(argv[1], "pciex2") == 0) { - printf("Set serdes lane C & lane D to PCIe X2.\n"); - convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET); - } else if (strcmp(argv[1], "show") == 0) { - print_serdes_mux(); - } else { - return CMD_RET_USAGE; - } - - return 0; -} - -U_BOOT_CMD( - lane_bank, 2, 0, serdes_mux_cmd, - "Multiplexed function setting for SerDes Lanes", - "sata\n" - " -change lane B to sata\n" - "lane_bank sgmii1b\n" - " -change lane B to SGMII1\n" - "lane_bank sgmii1c\n" - " -change lane C to SGMII1\n" - "lane_bank sgmii2\n" - " -change lane D to SGMII2\n" - "lane_bank pciex1\n" - " -change lane C to PCIeX1\n" - "lane_bank pciex2\n" - " -change lane C & lane D to PCIeX2\n" - "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n" -); -#endif diff --git a/board/freescale/ls1021atwr/ls102xa_pbi.cfg b/board/freescale/ls1021atwr/ls102xa_pbi.cfg deleted file mode 100644 index f1a1b63ab77..00000000000 --- a/board/freescale/ls1021atwr/ls102xa_pbi.cfg +++ /dev/null @@ -1,12 +0,0 @@ -#PBI commands - -09570200 ffffffff -09570158 00000300 -8940007c 21f47300 - -#Configure Scratch register -09ee0200 10000000 -#Configure alternate space -09570158 00001000 -#Flush PBL data -096100c0 000FFFFF diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg deleted file mode 100644 index f94997d5384..00000000000 --- a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 - -#enable IFC, disable QSPI and DSPI -0608000c 00000000 00000000 00000000 -30000000 00007900 60040a00 21046000 -00000000 00000000 00000000 20000000 -00080000 881b7340 00000000 00000000 diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg deleted file mode 100644 index 541b604cffc..00000000000 --- a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 - -#disable IFC, enable QSPI and DSPI -0608000c 00000000 00000000 00000000 -30000000 00007900 60040a00 21046000 -00000000 00000000 00000000 20000000 -20024800 881b7340 00000000 00000000 diff --git a/board/freescale/ls1021atwr/psci.S b/board/freescale/ls1021atwr/psci.S deleted file mode 100644 index 3c093aa33cb..00000000000 --- a/board/freescale/ls1021atwr/psci.S +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 NXP Semiconductor. - * Author: Wang Dongsheng - */ - -#include -#include - -#include -#include - - .pushsection ._secure.text, "ax" - - .arch_extension sec - - .align 5 - -.globl psci_system_off -psci_system_off: -1: wfi - b 1b - - .popsection diff --git a/board/freescale/ls1028a/Kconfig b/board/freescale/ls1028a/Kconfig deleted file mode 100644 index fb6ee17ce89..00000000000 --- a/board/freescale/ls1028a/Kconfig +++ /dev/null @@ -1,47 +0,0 @@ -if TARGET_LS1028AQDS - -config SYS_BOARD - default "ls1028a" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls1028aqds" - -config EMMC_BOOT - bool "Support for booting from EMMC" - -config TEXT_BASE - default 0x96000000 if SD_BOOT || EMMC_BOOT - default 0x82000000 if TFABOOT - default 0x20100000 - -endif - -if TARGET_LS1028ARDB - -config SYS_BOARD - default "ls1028a" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls1028ardb" - -config EMMC_BOOT - bool "Support for booting from EMMC" - -config TEXT_BASE - default 0x96000000 if SD_BOOT || EMMC_BOOT - default 0x82000000 if TFABOOT - default 0x20100000 - -endif diff --git a/board/freescale/ls1028a/MAINTAINERS b/board/freescale/ls1028a/MAINTAINERS deleted file mode 100644 index 551f6a08651..00000000000 --- a/board/freescale/ls1028a/MAINTAINERS +++ /dev/null @@ -1,26 +0,0 @@ -LS1028AQDS BOARD -M: Tang Yuantian -S: Maintained -F: board/freescale/ls1028a/ -F: include/configs/ls1028a_common.h -F: include/configs/ls1028aqds.h -F: configs/ls1028aqds_tfa_defconfig -F: configs/ls1028aqds_tfa_lpuart_defconfig - -LS1028ARDB BOARD -M: Tang Yuantian -S: Maintained -F: board/freescale/ls1028a/ -F: include/configs/ls1028a_common.h -F: include/configs/ls1028ardb.h -F: configs/ls1028ardb_tfa_defconfig - -LS1028AQDS_SECURE_BOOT BOARD -M: Tang Yuantian -S: Maintained -F: configs/ls1028aqds_tfa_SECURE_BOOT_defconfig - -LS1028ARDB_SECURE_BOOT BOARD -M: Tang Yuantian -S: Maintained -F: configs/ls1028ardb_tfa_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1028a/Makefile b/board/freescale/ls1028a/Makefile deleted file mode 100644 index 9bc144cbfea..00000000000 --- a/board/freescale/ls1028a/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2019 NXP -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += ls1028a.o -obj-y += ddr.o diff --git a/board/freescale/ls1028a/README b/board/freescale/ls1028a/README deleted file mode 100644 index 323881faa50..00000000000 --- a/board/freescale/ls1028a/README +++ /dev/null @@ -1,164 +0,0 @@ -Overview --------- -The LS1028A Reference Design (RDB) is a high-performance computing, -evaluation, and development platform that supports ARM SoC LS1028A and its -derivatives. - -LS1028A SoC Overview --------------------------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc - -RDB Default Switch Settings (1: ON; 0: OFF) -------------------------------------------- -For XSPI NOR boot (default) -SW2: 1111_1000 -SW3: 1111_0000 -SW5: 0011_1001 - -For SD Boot -SW2: 1000_1000 -SW3: 1111_0000 -SW5: 0011_1001 - -For eMMC Boot -SW2: 1001_1000 -SW3: 1111_0000 -SW5: 0011_1001 - -LS1028ARDB board Overview -------------------------- -Processor - Two Arm Cortex- A72 processor cores: - - Based on 64-bit ARMv8 architecture - - Up to 1.3 GHz operation - - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1 - data cache - - Arranged as a single cluster of two cores sharing a single 1 MB L2 - cache -DDR memory - - Five onboard 1G x8 discrete memory modules (Four data byte lanes - ECC) - - 32-bit data and 4-bit ECC - - One chip select - - Data transfer rates of up to 1.6 GT/s - - Single-bit error correction and double-bit error detection ECC (4-bit - check word across 32-bit data) -High-speed serial ports(SerDes) - - Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the - Qualcomm AR8033 PHY - - Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected - through the NXP F104S8A PHY - - Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3 - (8 Gbit/s) cards - - Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2 Key-B - slot through a register mux to support either PCIe Gen 3 (8 Gbit/s) or - SATA Gen 3 cards (6 Gbit/s) at a time -eSDHC - - eSDHC1, eSDHC2 -SPI - - Connects to two mikroBUS sockets to support mikro-click modules, - such as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near - field communications (NFC) controller -Octal SPI (XSPI) - - One 256 MB onboard XSPI serial NOR flash memory - - One 512 MB onboard XSPI serial NAND flash memory - - Supports a QSPI emulator for offboard QSPI emulation -I2C - - All system devices are accessed via I2C1, which is multiplexed on - I2C multiplexer PCA9848 to isolate address conflicts and reduce - capacitive load - - I2C1 is used for EEPROMs, RTC, INA220 current-power sensor, - thermal monitor, PCIe/SATA M.2 connectors and mikro-click modules - 1 and 2 -CAN - - The two CAN DB9 ports can support CAN FD fast phase at data rates of - up to 5 Mbit/s -Serial audio interface(SAI) - - Audio codec SGTL5000 provides headphone and audio LINEOUT for - stereo speakers - - IEEE1588 interface to support audio on SAI4 - -QDS Default Switch Settings (1: ON; 0: OFF) -------------------------------------------- -For SD Boot -SW1 : 1000_0000 -SW2 : 1110_0110 -SW3 : 0000_0010 -SW4 : 0000_0000 -SW5 : 0000_0000 -SW6 : 0000_0000 -SW7 : 1111_0011 -SW8 : 1110_0000 -SW9 : 1000_0001 -SW10: 1110_0000 - -For XSPI Boot -SW1 : 1111_0000 -SW2 : 0000_0110 -SW3 : 0000_0010 -SW4 : 0000_0000 -SW5 : 0110_0000 -SW6 : 0101_0000 -SW7 : 1111_0011 -SW8 : 1110_0000 -SW9 : 1000_0000 -SW10: 1110_0000 - -LS1028AQDS board Overview -------------------------- -Processor - Two Arm Cortex- A72 processor cores: - - Based on 64-bit ARMv8 architecture - - Up to 1.3 GHz operation - - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1 - data cache - - Arranged as a single cluster of two cores sharing a single 1 MB L2 - cache -DDR memory - - Supports data rates of up to 1.6 GT/s for both, DDR4 and DDR3L - - Supports a single- or dual-ranked SODIMM or UDIMM connector - - 32-bit data and 4-bit ECC - - Supports x8/x16 devices - - Supports ECC error detection and correction - - 1.35 V or 1.2 V DDR power supply, with automatic tracking of VTT, to - all devices in case of DDR3L or DDR4, respectively. Power can - switch to 1.35 V or 1.2 V, based on the switch settings for DDR3L or - DDR4 devices, respectively -SerDes (Serializer/Deserializer) - - Four-lane (0-3) SerDes: - - Lane 0: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 10 - Gbit SXGMII, 1 Gbit SGMII - - Lane 1: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit - SGMII, 10 Gbit QXGMII, 5 Gbit QSGMII, 1 Gbit SGMII - - Lane 2: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit - SGMII - - Lane 3: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit - SGMII, SATA 2.0/3.0 - - Four slots on SerDes lanes support PCIe Gen1/2/3, 1 Gbit SGMII - add-in cards - - Lane 1 connects to a 2x10 connector with SFP+ through a retimer; - lane 2 (TX lines) connects to an SMA connector - Lane 3 connects to 1x7 header to support SATA devices -eSDHC - - eSDHC1, eSDHC2 -SPI - - SPI1 and SPI2 support three onboard SPI flash memory devices: - 512 Mbit high-speed flash (with speed of up to 108/54 MHz) - memory for storage - 4 Mbit low-speed flash memory (with speed of up to 40 MHz) - 64 Mbit high-speed flash memory (with speed of up to 104/80 - MHz) - - SPI3 supports one onboard 64 Mbit SPI flash memory (with speed of - up to 104/80 MHz) - - All memories operate at 1.8 V - - A header is provided on SPI1 to test SPI slave mode -I2C - - LS1028A supports eight I2C controllers -Serial audio interface(SAI) - Two SAI ports with audio codec SGTL5000: - - Include stereo LINEIN with support for external analog input - - Provide headphone and line output -Display - - DisplayPort connector to connect the DP data to a 4K display device - (computer monitor) - - eDP connector to connect the DP data to a 4K display panel diff --git a/board/freescale/ls1028a/ddr.c b/board/freescale/ls1028a/ddr.c deleted file mode 100644 index c406f2436d1..00000000000 --- a/board/freescale/ls1028a/ddr.c +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 NXP - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int fsl_initdram(void) -{ - gd->ram_size = tfa_get_dram_size(); - - if (!gd->ram_size) - gd->ram_size = fsl_ddr_sdram_size(); - - return 0; -} diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c deleted file mode 100644 index db94d9c1fa8..00000000000 --- a/board/freescale/ls1028a/ls1028a.c +++ /dev/null @@ -1,329 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019-2022 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include "../common/qixis.h" -#include "../drivers/net/fsl_enetc.h" - -DECLARE_GLOBAL_DATA_PTR; - -int config_board_mux(void) -{ -#ifndef CONFIG_LPUART -#if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS) - u8 reg; - - reg = QIXIS_READ(brdcfg[13]); - /* Field| Function - * 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3): - * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}. - * 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4): - * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}. - */ - reg &= ~(0xf0); - reg |= 0xb0; - QIXIS_WRITE(brdcfg[13], reg); - - reg = QIXIS_READ(brdcfg[15]); - /* Field| Function - * 7 | Controls the CAN1 transceiver (net CFG_CAN1_STBY): - * CAN1 | 0= CAN #1 transceiver enabled - * 6 | Controls the CAN2 transceiver (net CFG_CAN2_STBY): - * CAN2 | 0= CAN #2 transceiver enabled - */ - reg &= ~(0xc0); - QIXIS_WRITE(brdcfg[15], reg); -#endif -#endif - - return 0; -} - -#ifdef CONFIG_LPUART -u32 get_lpuart_clk(void) -{ - return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV; -} -#endif - -int board_init(void) -{ -#ifndef CONFIG_SYS_EARLY_PCI_INIT - pci_init(); -#endif - -#if defined(CONFIG_TARGET_LS1028ARDB) - u8 val = I2C_MUX_CH_DEFAULT; - -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1); -#else - struct udevice *dev; - - if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev)) - dm_i2c_write(dev, 0x0b, &val, 1); -#endif -#endif - -#if defined(CONFIG_TARGET_LS1028ARDB) - u8 reg; - - reg = QIXIS_READ(brdcfg[4]); - /* - * Field | Function - * 3 | DisplayPort Power Enable (net DP_PWR_EN): - * DPPWR | 0= DP_PWR is enabled. - */ - reg &= ~(DP_PWD_EN_DEFAULT_MASK); - QIXIS_WRITE(brdcfg[4], reg); -#endif - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - return pci_eth_init(bis); -} - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ - config_board_mux(); - - return 0; -} -#endif - -int board_early_init_f(void) -{ -#ifdef CONFIG_LPUART - u8 uart; -#endif - -#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_XPL_BUILD) - i2c_early_init_f(); -#endif - - fsl_lsch3_early_init_f(); - -#ifdef CONFIG_LPUART - /* - * Field| Function - * -------------------------------------------------------------- - * 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3): - * I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}. - * -------------------------------------------------------------- - * 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4): - * I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}. - */ - /* use lpuart0 as system console */ - uart = QIXIS_READ(brdcfg[13]); - uart &= ~CFG_LPUART_MUX_MASK; - uart |= CFG_LPUART_EN; - QIXIS_WRITE(brdcfg[13], uart); -#endif - - return 0; -} - -void detail_board_ddr_info(void) -{ - puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); - print_ddr_info(0); -} - -int esdhc_status_fixup(void *blob, const char *compat) -{ - void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE; - char esdhc1_path[] = "/soc/mmc@2140000"; - char esdhc2_path[] = "/soc/mmc@2150000"; - char dspi1_path[] = "/soc/spi@2100000"; - char dspi2_path[] = "/soc/spi@2110000"; - u32 mux_sdhc1, mux_sdhc2; - u32 io = 0; - - /* - * The PMUX IO-expander for mux select is used to control - * the muxing of various onboard interfaces. - */ - - io = in_le32(dcfg_ccsr + DCFG_RCWSR12); - mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK; - - /* Disable esdhc1/dspi1 if not selected. */ - if (mux_sdhc1 != 0) - do_fixup_by_path(blob, esdhc1_path, "status", "disabled", - sizeof("disabled"), 1); - if (mux_sdhc1 != 2) - do_fixup_by_path(blob, dspi1_path, "status", "disabled", - sizeof("disabled"), 1); - - io = in_le32(dcfg_ccsr + DCFG_RCWSR13); - mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK; - - /* Disable esdhc2/dspi2 if not selected. */ - if (mux_sdhc2 != 0) - do_fixup_by_path(blob, esdhc2_path, "status", "disabled", - sizeof("disabled"), 1); - if (mux_sdhc2 != 2) - do_fixup_by_path(blob, dspi2_path, "status", "disabled", - sizeof("disabled"), 1); - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; - - ft_cpu_setup(blob, bd); - - /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; - -#ifdef CONFIG_RESV_RAM - /* reduce size if reserved memory is within this bank */ - if (gd->arch.resv_ram >= base[0] && - gd->arch.resv_ram < base[0] + size[0]) - size[0] = gd->arch.resv_ram - base[0]; - else if (gd->arch.resv_ram >= base[1] && - gd->arch.resv_ram < base[1] + size[1]) - size[1] = gd->arch.resv_ram - base[1]; -#endif - - fdt_fixup_memory_banks(blob, base, size, 2); - - fdt_fixup_icid(blob); - -#ifdef CONFIG_FSL_ENETC - fdt_fixup_enetc_mac(blob); -#endif - - return 0; -} -#endif - -#ifdef CONFIG_FSL_QIXIS -int checkboard(void) -{ -#ifdef CONFIG_TFABOOT - enum boot_src src = get_boot_src(); -#endif - u8 sw; - - int clock; - char *board; - char buf[64] = {0}; - static const char *freq[6] = {"100.00", "125.00", "156.25", - "161.13", "322.26", "100.00 SS"}; - - cpu_name(buf); - /* find the board details */ - sw = QIXIS_READ(id); - - switch (sw) { - case 0x46: - board = "QDS"; - break; - case 0x47: - board = "RDB"; - break; - case 0x49: - board = "HSSI"; - break; - default: - board = "unknown"; - break; - } - - sw = QIXIS_READ(arch); - printf("Board: %s-%s, Version: %c, boot from ", - buf, board, (sw & 0xf) + 'A' - 1); - - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - -#ifdef CONFIG_TFABOOT - if (src == BOOT_SOURCE_SD_MMC) { - puts("SD\n"); - } else if (src == BOOT_SOURCE_SD_MMC2) { - puts("eMMC\n"); - } else { -#endif -#ifdef CONFIG_SD_BOOT - puts("SD\n"); -#elif defined(CONFIG_EMMC_BOOT) - puts("eMMC\n"); -#else - switch (sw) { - case 0: - case 4: - printf("NOR\n"); - break; - case 1: - printf("NAND\n"); - break; - default: - printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); - break; - } -#endif -#ifdef CONFIG_TFABOOT - } -#endif - - printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board); - puts("SERDES1 Reference : "); - - sw = QIXIS_READ(brdcfg[2]); -#ifdef CONFIG_TARGET_LS1028ARDB - clock = (sw >> 6) & 3; -#else - clock = (sw >> 4) & 0xf; -#endif - - printf("Clock1 = %sMHz ", freq[clock]); -#ifdef CONFIG_TARGET_LS1028ARDB - clock = (sw >> 4) & 3; -#else - clock = sw & 0xf; -#endif - printf("Clock2 = %sMHz\n", freq[clock]); - - return 0; -} -#endif - -void *video_hw_init(void) -{ - return NULL; -} diff --git a/board/freescale/ls1043aqds/Kconfig b/board/freescale/ls1043aqds/Kconfig deleted file mode 100644 index 7e27f8f5b13..00000000000 --- a/board/freescale/ls1043aqds/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_LS1043AQDS - -config SYS_BOARD - default "ls1043aqds" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls1043aqds" - -endif diff --git a/board/freescale/ls1043aqds/MAINTAINERS b/board/freescale/ls1043aqds/MAINTAINERS deleted file mode 100644 index f7420ecd303..00000000000 --- a/board/freescale/ls1043aqds/MAINTAINERS +++ /dev/null @@ -1,14 +0,0 @@ -LS1043AQDS BOARD -M: Mingkai Hu -S: Maintained -F: board/freescale/ls1043aqds/ -F: include/configs/ls1043aqds.h -F: configs/ls1043aqds_defconfig -F: configs/ls1043aqds_nor_ddr3_defconfig -F: configs/ls1043aqds_nand_defconfig -F: configs/ls1043aqds_sdcard_ifc_defconfig -F: configs/ls1043aqds_sdcard_qspi_defconfig -F: configs/ls1043aqds_qspi_defconfig -F: configs/ls1043aqds_lpuart_defconfig -F: configs/ls1043aqds_tfa_defconfig -F: configs/ls1043aqds_tfa_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1043aqds/Makefile b/board/freescale/ls1043aqds/Makefile deleted file mode 100644 index ff830788fd7..00000000000 --- a/board/freescale/ls1043aqds/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright 2015 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += ddr.o -ifndef CONFIG_XPL_BUILD -obj-y += eth.o -endif -obj-y += ls1043aqds.o diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README deleted file mode 100644 index f5aa51da87e..00000000000 --- a/board/freescale/ls1043aqds/README +++ /dev/null @@ -1,64 +0,0 @@ -Overview --------- -The LS1043A Development System (QDS) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS1043A -LayerScape Architecture processor. The LS1043AQDS provides SW development -platform for the Freescale LS1043A processor series, with a complete -debugging environment. - -LS1043A SoC Overview --------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A -SoC overview. - - LS1043AQDS board Overview - ----------------------- - - SERDES Connections, 4 lanes supporting: - - PCI Express - 3.0 - - SGMII, SGMII 2.5 - - QSGMII - - SATA 3.0 - - 10GBase-R - - DDR Controller - - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s - -IFC/Local Bus - - One in-socket 128 MB NOR flash 16-bit data bus - - One 512 MB NAND flash with ECC support - - PromJet Port - - FPGA connection - - USB 3.0 - - Three high speed USB 3.0 ports - - First USB 3.0 port configured as Host with Type-A connector - - The other two USB 3.0 ports configured as OTG with micro-AB connector - - SDHC port connects directly to an adapter card slot, featuring: - - Optional clock feedback paths, and optional high-speed voltage translation assistance - - SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC - - eMMC memory devices - - DSPI: Onboard support for three SPI flash memory devices - - 4 I2C controllers - - One SATA onboard connectors - - UART - - Two 4-pin serial ports at up to 115.2 Kbit/s - - Two DB9 D-Type connectors supporting one Serial port each - - ARM JTAG support - -Memory map from core's view ----------------------------- -Start Address End Address Description Size -0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB -0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB -0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB -0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB -0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB -0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB -0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB -0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB -0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB - -Booting Options ---------------- -a) Promjet Boot -b) NOR boot -c) NAND boot -d) SD boot -e) QSPI boot diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c deleted file mode 100644 index 137ad7395ad..00000000000 --- a/board/freescale/ls1043aqds/ddr.c +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#include -#include -#ifdef CONFIG_FSL_DEEP_SLEEP -#include -#endif -#include -#include -#include -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 3) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - pbsp = udimms[0]; - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->cpo_override = pbsp->cpo_override; - popts->write_data_delay = - pbsp->write_data_delay; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for %lu MT/s\n", - ddr_freq); - printf("Trying to use the highest speed (%u) parameters\n", - pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); - - /* force DDR bus width to 32 bits */ - popts->data_bus_width = 1; - popts->otf_burst_chop_en = 0; - popts->burst_length = DDR_BL8; - popts->bstopre = 0; /* enable auto precharge */ - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 1; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - -#ifdef CONFIG_SYS_FSL_DDR4 - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | - DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ - - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x59; -#else - popts->cswl_override = DDR_CSWL_CS0; - - /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); -#endif -} - -#ifdef CONFIG_TFABOOT -int fsl_initdram(void) -{ - gd->ram_size = tfa_get_dram_size(); - if (!gd->ram_size) - gd->ram_size = fsl_ddr_sdram_size(); - - return 0; -} -#else -int fsl_initdram(void) -{ - phys_size_t dram_size; - -#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) - gd->ram_size = fsl_ddr_sdram_size(); - - return 0; -#else - puts("Initializing DDR....using SPD\n"); - - dram_size = fsl_ddr_sdram(); -#endif - erratum_a008850_post(); - -#ifdef CONFIG_FSL_DEEP_SLEEP - fsl_dp_ddr_restore(); -#endif - - gd->ram_size = dram_size; - - return 0; -} -#endif diff --git a/board/freescale/ls1043aqds/ddr.h b/board/freescale/ls1043aqds/ddr.h deleted file mode 100644 index 65b0250d370..00000000000 --- a/board/freescale/ls1043aqds/ddr.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ - -extern void erratum_a008850_post(void); - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; - u32 cpo_override; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | - */ -#ifdef CONFIG_SYS_FSL_DDR4 - {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, - {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E0A,}, - {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, - {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,}, -#elif defined(CONFIG_SYS_FSL_DDR3) - {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, - {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, -#else -#error DDR type not defined -#endif - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -#endif diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c deleted file mode 100644 index 5a8ca27b327..00000000000 --- a/board/freescale/ls1043aqds/eth.c +++ /dev/null @@ -1,501 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * Copyright 2019 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/qixis.h" -#include "../common/fman.h" -#include "ls1043aqds_qixis.h" - -#define EMI_NONE 0xFF -#define EMI1_RGMII1 0 -#define EMI1_RGMII2 1 -#define EMI1_SLOT1 2 -#define EMI1_SLOT2 3 -#define EMI1_SLOT3 4 -#define EMI1_SLOT4 5 -#define EMI2 6 - -static const char * const mdio_names[] = { - "LS1043AQDS_MDIO_RGMII1", - "LS1043AQDS_MDIO_RGMII2", - "LS1043AQDS_MDIO_SLOT1", - "LS1043AQDS_MDIO_SLOT2", - "LS1043AQDS_MDIO_SLOT3", - "LS1043AQDS_MDIO_SLOT4", - "NULL", -}; - -/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */ -#ifdef CONFIG_FMAN_ENET -static int mdio_mux[NUM_FM_PORTS]; - -static u8 lane_to_slot[] = {1, 2, 3, 4}; -#endif - -static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name; - - if (muxval > EMI2) - return NULL; - - name = ls1043aqds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -#ifdef CONFIG_FMAN_ENET -struct ls1043aqds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void ls1043aqds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - - if (muxval < 7) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct ls1043aqds_mdio *priv = bus->priv; - - ls1043aqds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct ls1043aqds_mdio *priv = bus->priv; - - ls1043aqds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, - regnum, value); -} - -static int ls1043aqds_mdio_reset(struct mii_dev *bus) -{ - struct ls1043aqds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int ls1043aqds_mdio_init(char *realbusname, u8 muxval) -{ - struct ls1043aqds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate ls1043aqds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate ls1043aqds private data\n"); - free(bus); - return -1; - } - - bus->read = ls1043aqds_mdio_read; - bus->write = ls1043aqds_mdio_write; - bus->reset = ls1043aqds_mdio_reset; - strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - struct fixed_link f_link; - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - if (port == FM1_DTSEC9) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s1-p1"); - } else if (port == FM1_DTSEC2) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s2-p1"); - } else if (port == FM1_DTSEC5) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s3-p1"); - } else if (port == FM1_DTSEC6) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s4-p1"); - } - } else if (fm_info_get_enet_if(port) == - PHY_INTERFACE_MODE_2500BASEX) { - /* 2.5G SGMII interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(1000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 2.5G SGMII */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "2500base-x"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { - switch (mdio_mux[port]) { - case EMI1_SLOT1: - switch (port) { - case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p1"); - break; - case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p2"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p3"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p4"); - break; - default: - break; - } - break; - case EMI1_SLOT2: - switch (port) { - case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p1"); - break; - case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p2"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p3"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p4"); - break; - default: - break; - } - break; - default: - break; - } - fdt_delprop(fdt, offset, "phy-connection-type"); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "qsgmii"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && - port == FM1_10GEC1) { - /* 10GBase-R interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(10000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 10GBase-R */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - int i; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - switch (mdio_mux[i]) { - case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1-slot1"); - break; - case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1-slot2"); - break; - case EMI1_SLOT3: - fdt_status_okay_by_alias(fdt, "emi1-slot3"); - break; - case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1-slot4"); - break; - default: - break; - } - break; - case PHY_INTERFACE_MODE_XGMII: - break; - default: - break; - } - } -} - -int board_eth_init(struct bd_info *bis) -{ - int i, idx, lane, slot, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x2555: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - break; - case 0x4555: - case 0x4558: - /* QSGMII on lane A, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT1_PHY_ADDR_S1); - fm_info_set_phy_address(FM1_DTSEC2, - QSGMII_CARD_PORT2_PHY_ADDR_S1); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT3_PHY_ADDR_S1); - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT4_PHY_ADDR_S1); - break; - case 0x1355: - /* SGMII on lane B, MAC 2*/ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x2355: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - /* SGMII on lane B, MAC 2*/ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x3335: - /* SGMII on lane C, MAC 5 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); - case 0x3355: - case 0x3358: - /* SGMII on lane B, MAC 2 */ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - case 0x3555: - case 0x3558: - /* SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x1455: - /* QSGMII on lane B, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT1_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC2, - QSGMII_CARD_PORT2_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT3_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT4_PHY_ADDR_S2); - break; - case 0x2455: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - /* QSGMII on lane B, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT1_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC2, - QSGMII_CARD_PORT2_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT3_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT4_PHY_ADDR_S2); - break; - case 0x2255: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - /* 2.5G SGMII on lane B, MAC 2 */ - fm_info_set_phy_address(FM1_DTSEC2, 2); - break; - case 0x3333: - /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC9, - SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, - SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, - SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, - SGMII_CARD_PORT1_PHY_ADDR); - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n", - srds_s1); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_2500BASEX: - case PHY_INTERFACE_MODE_QSGMII: - if (interface == PHY_INTERFACE_MODE_SGMII) { - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - } else if (interface == PHY_INTERFACE_MODE_2500BASEX) { - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_2500_FM1_DTSEC1 + idx); - } else { - lane = serdes_get_first_lane(FSL_SRDS_1, - QSGMII_FM1_A); - } - - if (lane < 0) - break; - - slot = lane_to_slot[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - default: - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (i == FM1_DTSEC3) - mdio_mux[i] = EMI1_RGMII1; - else if (i == FM1_DTSEC4) - mdio_mux[i] = EMI1_RGMII2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - cpu_eth_init(bis); - - return pci_eth_init(bis); -} -#endif /* CONFIG_FMAN_ENET */ diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c deleted file mode 100644 index f043599fbb8..00000000000 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ /dev/null @@ -1,595 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * Copyright 2019-2020 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/i2c_mux.h" - -#include "../common/qixis.h" -#include "ls1043aqds_qixis.h" - -DECLARE_GLOBAL_DATA_PTR; - -enum { - MUX_TYPE_GPIO, -}; - -/* LS1043AQDS serdes mux */ -#define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */ -#define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */ -#define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */ -#define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */ -#define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */ -#define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */ -#define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */ -#define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */ -#define CFG_UART_MUX_MASK 0x6 -#define CFG_UART_MUX_SHIFT 1 -#define CFG_LPUART_EN 0x1 - -#ifdef CONFIG_TFABOOT -struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { - { - "nor0", - CFG_SYS_NOR0_CSPR, - CFG_SYS_NOR0_CSPR_EXT, - CFG_SYS_NOR_AMASK, - CFG_SYS_NOR_CSOR, - { - CFG_SYS_NOR_FTIM0, - CFG_SYS_NOR_FTIM1, - CFG_SYS_NOR_FTIM2, - CFG_SYS_NOR_FTIM3 - }, - - }, - { - "nor1", - CFG_SYS_NOR1_CSPR, - CFG_SYS_NOR1_CSPR_EXT, - CFG_SYS_NOR_AMASK, - CFG_SYS_NOR_CSOR, - { - CFG_SYS_NOR_FTIM0, - CFG_SYS_NOR_FTIM1, - CFG_SYS_NOR_FTIM2, - CFG_SYS_NOR_FTIM3 - }, - }, - { - "nand", - CFG_SYS_NAND_CSPR, - CFG_SYS_NAND_CSPR_EXT, - CFG_SYS_NAND_AMASK, - CFG_SYS_NAND_CSOR, - { - CFG_SYS_NAND_FTIM0, - CFG_SYS_NAND_FTIM1, - CFG_SYS_NAND_FTIM2, - CFG_SYS_NAND_FTIM3 - }, - }, - { - "fpga", - CFG_SYS_FPGA_CSPR, - CFG_SYS_FPGA_CSPR_EXT, - CFG_SYS_FPGA_AMASK, - CFG_SYS_FPGA_CSOR, - { - CFG_SYS_FPGA_FTIM0, - CFG_SYS_FPGA_FTIM1, - CFG_SYS_FPGA_FTIM2, - CFG_SYS_FPGA_FTIM3 - }, - } -}; - -struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { - { - "nand", - CFG_SYS_NAND_CSPR, - CFG_SYS_NAND_CSPR_EXT, - CFG_SYS_NAND_AMASK, - CFG_SYS_NAND_CSOR, - { - CFG_SYS_NAND_FTIM0, - CFG_SYS_NAND_FTIM1, - CFG_SYS_NAND_FTIM2, - CFG_SYS_NAND_FTIM3 - }, - }, - { - "nor0", - CFG_SYS_NOR0_CSPR, - CFG_SYS_NOR0_CSPR_EXT, - CFG_SYS_NOR_AMASK, - CFG_SYS_NOR_CSOR, - { - CFG_SYS_NOR_FTIM0, - CFG_SYS_NOR_FTIM1, - CFG_SYS_NOR_FTIM2, - CFG_SYS_NOR_FTIM3 - }, - }, - { - "nor1", - CFG_SYS_NOR1_CSPR, - CFG_SYS_NOR1_CSPR_EXT, - CFG_SYS_NOR_AMASK, - CFG_SYS_NOR_CSOR, - { - CFG_SYS_NOR_FTIM0, - CFG_SYS_NOR_FTIM1, - CFG_SYS_NOR_FTIM2, - CFG_SYS_NOR_FTIM3 - }, - }, - { - "fpga", - CFG_SYS_FPGA_CSPR, - CFG_SYS_FPGA_CSPR_EXT, - CFG_SYS_FPGA_AMASK, - CFG_SYS_FPGA_CSOR, - { - CFG_SYS_FPGA_FTIM0, - CFG_SYS_FPGA_FTIM1, - CFG_SYS_FPGA_FTIM2, - CFG_SYS_FPGA_FTIM3 - }, - } -}; - -void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) -{ - enum boot_src src = get_boot_src(); - - if (src == BOOT_SOURCE_IFC_NAND) - regs_info->regs = ifc_cfg_nand_boot; - else - regs_info->regs = ifc_cfg_nor_boot; - regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; -} -#endif - -int checkboard(void) -{ -#ifdef CONFIG_TFABOOT - enum boot_src src = get_boot_src(); -#endif - char buf[64]; -#ifndef CONFIG_SD_BOOT - u8 sw; -#endif - - puts("Board: LS1043AQDS, boot from "); - -#ifdef CONFIG_TFABOOT - if (src == BOOT_SOURCE_SD_MMC) - puts("SD\n"); - else { -#endif - -#ifdef CONFIG_SD_BOOT - puts("SD\n"); -#else - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank: %d\n", sw); - else if (sw == 0x8) - puts("PromJet\n"); - else if (sw == 0x9) - puts("NAND\n"); - else if (sw == 0xF) - printf("QSPI\n"); - else - printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); -#endif - -#ifdef CONFIG_TFABOOT - } -#endif - printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", - QIXIS_READ(id), QIXIS_READ(arch)); - - printf("FPGA: v%d (%s), build %d\n", - (int)QIXIS_READ(scver), qixis_read_tag(buf), - (int)qixis_read_minor()); - - return 0; -} - -bool if_board_diff_clk(void) -{ - u8 diff_conf = QIXIS_READ(brdcfg[11]); - - return diff_conf & 0x40; -} - -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); - - switch (sysclk_conf & 0x0f) { - case QIXIS_SYSCLK_64: - return 64000000; - case QIXIS_SYSCLK_83: - return 83333333; - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - case QIXIS_SYSCLK_150: - return 150000000; - case QIXIS_SYSCLK_160: - return 160000000; - case QIXIS_SYSCLK_166: - return 166666666; - } - - return 66666666; -} - -unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); - - if (if_board_diff_clk()) - return get_board_sys_clk(); - switch ((ddrclk_conf & 0x30) >> 4) { - case QIXIS_DDRCLK_100: - return 100000000; - case QIXIS_DDRCLK_125: - return 125000000; - case QIXIS_DDRCLK_133: - return 133333333; - } - - return 66666666; -} - -int dram_init(void) -{ - /* - * When resuming from deep sleep, the I2C channel may not be - * in the default channel. So, switch to the default channel - * before accessing DDR SPD. - * - * PCA9547 mount on I2C1 bus - */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - fsl_initdram(); -#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ - defined(CONFIG_XPL_BUILD) - /* This will break-before-make MMU for DDR */ - update_early_mmu_table(); -#endif - - return 0; -} - -int i2c_multiplexer_select_vid_channel(u8 channel) -{ - return select_i2c_ch_pca9547(channel, 0); -} - -void board_retimer_init(void) -{ - u8 reg; - int bus_num = 0; - - /* Retimer is connected to I2C1_CH7_CH5 */ - select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num); - reg = I2C_MUX_CH5; -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return; - } - dm_i2c_write(dev, 0, ®, 1); - - /* Access to Control/Shared register */ - ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return; - } - - reg = 0x0; - dm_i2c_write(dev, 0xff, ®, 1); - - /* Read device revision and ID */ - dm_i2c_read(dev, 1, ®, 1); - debug("Retimer version id = 0x%x\n", reg); - - /* Enable Broadcast. All writes target all channel register sets */ - reg = 0x0c; - dm_i2c_write(dev, 0xff, ®, 1); - - /* Reset Channel Registers */ - dm_i2c_read(dev, 0, ®, 1); - reg |= 0x4; - dm_i2c_write(dev, 0, ®, 1); - - /* Enable override divider select and Enable Override Output Mux */ - dm_i2c_read(dev, 9, ®, 1); - reg |= 0x24; - dm_i2c_write(dev, 9, ®, 1); - - /* Select VCO Divider to full rate (000) */ - dm_i2c_read(dev, 0x18, ®, 1); - reg &= 0x8f; - dm_i2c_write(dev, 0x18, ®, 1); - - /* Selects active PFD MUX Input as Re-timed Data (001) */ - dm_i2c_read(dev, 0x1e, ®, 1); - reg &= 0x3f; - reg |= 0x20; - dm_i2c_write(dev, 0x1e, ®, 1); - - /* Set data rate as 10.3125 Gbps */ - reg = 0x0; - dm_i2c_write(dev, 0x60, ®, 1); - reg = 0xb2; - dm_i2c_write(dev, 0x61, ®, 1); - reg = 0x90; - dm_i2c_write(dev, 0x62, ®, 1); - reg = 0xb3; - dm_i2c_write(dev, 0x63, ®, 1); - reg = 0xcd; - dm_i2c_write(dev, 0x64, ®, 1); -#else - i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); - - /* Access to Control/Shared register */ - reg = 0x0; - i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); - - /* Read device revision and ID */ - i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); - debug("Retimer version id = 0x%x\n", reg); - - /* Enable Broadcast. All writes target all channel register sets */ - reg = 0x0c; - i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); - - /* Reset Channel Registers */ - i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); - reg |= 0x4; - i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); - - /* Enable override divider select and Enable Override Output Mux */ - i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1); - reg |= 0x24; - i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1); - - /* Select VCO Divider to full rate (000) */ - i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); - reg &= 0x8f; - i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); - - /* Selects active PFD MUX Input as Re-timed Data (001) */ - i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); - reg &= 0x3f; - reg |= 0x20; - i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); - - /* Set data rate as 10.3125 Gbps */ - reg = 0x0; - i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); - reg = 0xb2; - i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); - reg = 0x90; - i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); - reg = 0xb3; - i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); - reg = 0xcd; - i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); -#endif - - /* Return the default channel */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num); -} - -int board_early_init_f(void) -{ - u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR; -#ifdef CONFIG_HAS_FSL_XHCI_USB - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; - u32 usb_pwrfault; -#endif -#ifdef CONFIG_LPUART - u8 uart; -#endif - - /* - * Enable secure system counter for timer - */ - out_le32(cntcr, 0x1); - -#if defined(CONFIG_SYS_I2C_EARLY_INIT) - i2c_early_init_f(); -#endif - fsl_lsch2_early_init_f(); - -#ifdef CONFIG_HAS_FSL_XHCI_USB - out_be32(&scfg->rcwpmuxcr0, 0x3333); - out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); - usb_pwrfault = - (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) | - (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) | - (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT); - out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); -#endif - -#ifdef CONFIG_LPUART - /* We use lpuart0 as system console */ - uart = QIXIS_READ(brdcfg[14]); - uart &= ~CFG_UART_MUX_MASK; - uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; - QIXIS_WRITE(brdcfg[14], uart); -#endif - - return 0; -} - -#ifdef CONFIG_FSL_DEEP_SLEEP -/* determine if it is a warm boot */ -bool is_warm_boot(void) -{ -#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) - struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; - - if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) - return 1; - - return 0; -} -#endif - -int config_board_mux(int ctrl_type) -{ - u8 reg14; - - reg14 = QIXIS_READ(brdcfg[14]); - - switch (ctrl_type) { - case MUX_TYPE_GPIO: - reg14 = (reg14 & (~0x30)) | 0x20; - break; - default: - puts("Unsupported mux interface type\n"); - return -1; - } - - QIXIS_WRITE(brdcfg[14], reg14); - - return 0; -} - -int config_serdes_mux(void) -{ - return 0; -} - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ - if (hwconfig("gpio")) - config_board_mux(MUX_TYPE_GPIO); - - return 0; -} -#endif - -int board_init(void) -{ -#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 - erratum_a010315(); -#endif - - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - board_retimer_init(); - -#ifdef CFG_SYS_FSL_SERDES - config_serdes_mux(); -#endif - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; - u8 reg; - - /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; - - fdt_fixup_memory_banks(blob, base, size, 2); - ft_cpu_setup(blob, bd); - -#ifdef CONFIG_FMAN_ENET - fdt_fixup_board_enet(blob); -#endif - - fdt_fixup_icid(blob); - - reg = QIXIS_READ(brdcfg[0]); - reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - /* Disable IFC if QSPI is enabled */ - if (reg == 0xF) - do_fixup_by_compat(blob, "fsl,ifc", - "status", "disabled", 8 + 1, 1); - - return 0; -} -#endif - -u8 flash_read8(void *addr) -{ - return __raw_readb(addr + 1); -} - -void flash_write16(u16 val, void *addr) -{ - u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); - - __raw_writew(shftval, addr); -} - -u16 flash_read16(void *addr) -{ - u16 val = __raw_readw(addr); - - return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); -} - -#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) -void *env_sf_get_env_addr(void) -{ - return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); -} -#endif diff --git a/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg b/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg deleted file mode 100644 index f072274f474..00000000000 --- a/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg +++ /dev/null @@ -1,14 +0,0 @@ -#Configure Scratch register -09570600 00000000 -09570604 10000000 -#Alt base register -09570158 00001000 -#Disable CCI barrier tranaction -09570178 0000e010 -09180000 00000008 -#USB PHY frequency sel -09570418 0000009e -0957041c 0000009e -09570420 0000009e -#flush PBI data -096100c0 000fffff diff --git a/board/freescale/ls1043aqds/ls1043aqds_qixis.h b/board/freescale/ls1043aqds/ls1043aqds_qixis.h deleted file mode 100644 index bba494ae413..00000000000 --- a/board/freescale/ls1043aqds/ls1043aqds_qixis.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __LS1043AQDS_QIXIS_H__ -#define __LS1043AQDS_QIXIS_H__ - -/* Definitions of QIXIS Registers for LS1043AQDS */ - -/* BRDCFG4[4:7] select EC1 and EC2 as a pair */ -#define BRDCFG4_EMISEL_MASK 0xe0 -#define BRDCFG4_EMISEL_SHIFT 5 - -/* SYSCLK */ -#define QIXIS_SYSCLK_66 0x0 -#define QIXIS_SYSCLK_83 0x1 -#define QIXIS_SYSCLK_100 0x2 -#define QIXIS_SYSCLK_125 0x3 -#define QIXIS_SYSCLK_133 0x4 -#define QIXIS_SYSCLK_150 0x5 -#define QIXIS_SYSCLK_160 0x6 -#define QIXIS_SYSCLK_166 0x7 -#define QIXIS_SYSCLK_64 0x8 - -/* DDRCLK */ -#define QIXIS_DDRCLK_66 0x0 -#define QIXIS_DDRCLK_100 0x1 -#define QIXIS_DDRCLK_125 0x2 -#define QIXIS_DDRCLK_133 0x3 - -/* BRDCFG2 - SD clock*/ -#define QIXIS_SDCLK1_100 0x0 -#define QIXIS_SDCLK1_125 0x1 -#define QIXIS_SDCLK1_165 0x2 -#define QIXIS_SDCLK1_100_SP 0x3 - -#endif diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg deleted file mode 100644 index d87058b7efe..00000000000 --- a/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 -# serdes protocol -08100010 0a000000 00000000 00000000 -14550002 80004012 e0106000 c1002000 -00000000 00000000 00000000 00038800 -00000000 00001100 00000096 00000001 diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg deleted file mode 100644 index b6b5e0b1018..00000000000 --- a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 -# RCW -# Enable IFC; disable QSPI -08100010 0a000000 00000000 00000000 -14550002 80004012 60040000 c1002000 -00000000 00000000 00000000 00038800 -00000000 00001100 00000096 00000001 diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg deleted file mode 100644 index 7783521b95b..00000000000 --- a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 -# RCW -# Enable QSPI; disable IFC -08100010 0a000000 00000000 00000000 -14550002 80004012 60040000 c1002000 -00000000 00000000 00000000 00038800 -20124000 00001100 00000096 00000001 diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig deleted file mode 100644 index 51818ec5801..00000000000 --- a/board/freescale/ls1043ardb/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ - -if TARGET_LS1043ARDB - -config SYS_BOARD - default "ls1043ardb" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls1043ardb" - -endif diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS deleted file mode 100644 index 06b23889f6d..00000000000 --- a/board/freescale/ls1043ardb/MAINTAINERS +++ /dev/null @@ -1,13 +0,0 @@ -LS1043A BOARD -M: Mingkai Hu -S: Maintained -F: board/freescale/ls1043ardb/ -F: include/configs/ls1043ardb.h -F: configs/ls1043ardb_defconfig -F: configs/ls1043ardb_nand_defconfig -F: configs/ls1043ardb_sdcard_defconfig -F: configs/ls1043ardb_tfa_defconfig -F: configs/ls1043ardb_tfa_SECURE_BOOT_defconfig -F: configs/ls1043ardb_SECURE_BOOT_defconfig -F: configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig -F: configs/ls1043ardb_nand_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1043ardb/Makefile b/board/freescale/ls1043ardb/Makefile deleted file mode 100644 index 95745bf3a9c..00000000000 --- a/board/freescale/ls1043ardb/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2015 Freescale Semiconductor - -obj-y += ddr.o -obj-y += ls1043ardb.o -ifndef CONFIG_XPL_BUILD -obj-$(CONFIG_NET) += eth.o -obj-y += cpld.o -endif diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README deleted file mode 100644 index 66ee578e99d..00000000000 --- a/board/freescale/ls1043ardb/README +++ /dev/null @@ -1,54 +0,0 @@ -Overview --------- -The LS1043A Reference Design Board (RDB) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS1043A -LayerScape Architecture processor. The LS1043ARDB provides SW development -platform for the Freescale LS1043A processor series, with a complete -debugging environment. The LS1043A RDB is lead-free and RoHS-compliant. - -LS1043A SoC Overview --------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A -SoC overview. - - LS1043ARDB board Overview - ----------------------- - - SERDES Connections, 4 lanes supporting: - - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and - standard PCIe card - - QSGMII with x4 RJ45 connector - - 10GBase-R with x1 RJ45 connector - - DDR Controller - - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s - -IFC/Local Bus - - One 128MB NOR flash 16-bit data bus - - One 512 MB NAND flash with ECC support - - CPLD connection - - USB 3.0 - - Two super speed USB 3.0 Type A ports - - SDHC: connects directly to a full SD/MMC slot - - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz) - - 4 I2C controllers - - UART - - Two 4-pin serial ports at up to 115.2 Kbit/s - - Two DB9 D-Type connectors supporting one Serial port each - - ARM JTAG support - -Memory map from core's view ----------------------------- -Start Address End Address Description Size -0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB -0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB -0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB -0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB -0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB -0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB -0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB -0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB -0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB - -Booting Options ---------------- -a) NOR boot -b) NAND boot -c) SD boot diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c deleted file mode 100644 index 39b6c6449cf..00000000000 --- a/board/freescale/ls1043ardb/cpld.c +++ /dev/null @@ -1,178 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor - * - * Freescale LS1043ARDB board-specific CPLD controlling supports. - */ - -#include -#include -#include -#include -#include "cpld.h" - -u8 cpld_read(unsigned int reg) -{ - void *p = (void *)CFG_SYS_CPLD_BASE; - - return in_8(p + reg); -} - -void cpld_write(unsigned int reg, u8 value) -{ - void *p = (void *)CFG_SYS_CPLD_BASE; - - out_8(p + reg, value); -} - -/* Set the boot bank to the alternate bank */ -void cpld_set_altbank(void) -{ - u16 reg = CPLD_CFG_RCW_SRC_NOR; - u8 reg4 = CPLD_READ(soft_mux_on); - u8 reg5 = (u8)(reg >> 1); - u8 reg6 = (u8)(reg & 1); - u8 reg7 = CPLD_READ(vbank); - - cpld_rev_bit(®5); - - CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); - - CPLD_WRITE(cfg_rcw_src1, reg5); - CPLD_WRITE(cfg_rcw_src2, reg6); - - reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; - CPLD_WRITE(vbank, reg7); - - CPLD_WRITE(system_rst, 1); -} - -/* Set the boot bank to the default bank */ -void cpld_set_defbank(void) -{ - u16 reg = CPLD_CFG_RCW_SRC_NOR; - u8 reg4 = CPLD_READ(soft_mux_on); - u8 reg5 = (u8)(reg >> 1); - u8 reg6 = (u8)(reg & 1); - - cpld_rev_bit(®5); - - CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); - - CPLD_WRITE(cfg_rcw_src1, reg5); - CPLD_WRITE(cfg_rcw_src2, reg6); - - CPLD_WRITE(vbank, 0); - - CPLD_WRITE(system_rst, 1); -} - -void cpld_set_nand(void) -{ - u16 reg = CPLD_CFG_RCW_SRC_NAND; - - if (CPLD_READ(cpld_ver) > 0x2) - reg = CPLD_CFG_RCW_SRC_NAND_4K; - - u8 reg5 = (u8)(reg >> 1); - u8 reg6 = (u8)(reg & 1); - - cpld_rev_bit(®5); - - CPLD_WRITE(soft_mux_on, 1); - - CPLD_WRITE(cfg_rcw_src1, reg5); - CPLD_WRITE(cfg_rcw_src2, reg6); - - CPLD_WRITE(system_rst, 1); -} - -void cpld_set_sd(void) -{ - u16 reg = CPLD_CFG_RCW_SRC_SD; - u8 reg5 = (u8)(reg >> 1); - u8 reg6 = (u8)(reg & 1); - - cpld_rev_bit(®5); - - CPLD_WRITE(soft_mux_on, 1); - - CPLD_WRITE(cfg_rcw_src1, reg5); - CPLD_WRITE(cfg_rcw_src2, reg6); - - CPLD_WRITE(system_rst, 1); -} -#ifdef DEBUG -static void cpld_dump_regs(void) -{ - printf("cpld_ver = %x\n", CPLD_READ(cpld_ver)); - printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub)); - printf("pcba_ver = %x\n", CPLD_READ(pcba_ver)); - printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on)); - printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1)); - printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2)); - printf("vbank = %x\n", CPLD_READ(vbank)); - printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel)); - printf("uart_sel = %x\n", CPLD_READ(uart_sel)); - printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel)); - printf("tdmclk_mux_sel = %x\n", CPLD_READ(tdmclk_mux_sel)); - printf("sdhc_spics_sel = %x\n", CPLD_READ(sdhc_spics_sel)); - printf("status_led = %x\n", CPLD_READ(status_led)); - putc('\n'); -} -#endif - -void cpld_rev_bit(unsigned char *value) -{ - u8 rev_val, val; - int i; - - val = *value; - rev_val = val & 1; - for (i = 1; i <= 7; i++) { - val >>= 1; - rev_val <<= 1; - rev_val |= val & 1; - } - - *value = rev_val; -} - -int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - int rc = 0; - - if (argc <= 1) - return cmd_usage(cmdtp); - - if (strcmp(argv[1], "reset") == 0) { - if (strcmp(argv[2], "altbank") == 0) - cpld_set_altbank(); - else if (strcmp(argv[2], "nand") == 0) - cpld_set_nand(); - else if (strcmp(argv[2], "sd") == 0) - cpld_set_sd(); - else - cpld_set_defbank(); -#ifdef DEBUG - } else if (strcmp(argv[1], "dump") == 0) { - cpld_dump_regs(); -#endif - } else { - rc = cmd_usage(cmdtp); - } - - return rc; -} - -U_BOOT_CMD( - cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, - "Reset the board or alternate bank", - "reset: reset to default bank\n" - "cpld reset altbank: reset to alternate bank\n" - "cpld reset nand: reset to boot from NAND flash\n" - "cpld reset sd: reset to boot from SD card\n" -#ifdef DEBUG - "cpld dump - display the CPLD registers\n" -#endif -); diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h deleted file mode 100644 index eed34d63546..00000000000 --- a/board/freescale/ls1043ardb/cpld.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor - */ - -#ifndef __CPLD_H__ -#define __CPLD_H__ - -/* - * CPLD register set of LS1043ARDB board-specific. - */ -struct cpld_data { - u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ - u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ - u8 pcba_ver; /* 0x2 - PCBA Revision Register */ - u8 system_rst; /* 0x3 - system reset register */ - u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */ - u8 cfg_rcw_src1; /* 0x5 - Reset config word 1 */ - u8 cfg_rcw_src2; /* 0x6 - Reset config word 1 */ - u8 vbank; /* 0x7 - Flash bank selection Control */ - u8 sysclk_sel; /* 0x8 - */ - u8 uart_sel; /* 0x9 - */ - u8 sd1refclk_sel; /* 0xA - */ - u8 tdmclk_mux_sel; /* 0xB - */ - u8 sdhc_spics_sel; /* 0xC - */ - u8 status_led; /* 0xD - */ - u8 global_rst; /* 0xE - */ -}; - -u8 cpld_read(unsigned int reg); -void cpld_write(unsigned int reg, u8 value); -void cpld_rev_bit(unsigned char *value); - -#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) -#define CPLD_WRITE(reg, value) \ - cpld_write(offsetof(struct cpld_data, reg), value) - -/* CPLD on IFC */ -#define CPLD_SW_MUX_BANK_SEL 0x40 -#define CPLD_BANK_SEL_MASK 0x07 -#define CPLD_BANK_SEL_ALTBANK 0x04 -#define CPLD_CFG_RCW_SRC_NOR 0x025 -#define CPLD_CFG_RCW_SRC_NAND 0x106 -#define CPLD_CFG_RCW_SRC_NAND_4K 0x118 -#define CPLD_CFG_RCW_SRC_SD 0x040 -#endif diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c deleted file mode 100644 index 231b60d1b3d..00000000000 --- a/board/freescale/ls1043ardb/ddr.c +++ /dev/null @@ -1,254 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include "ddr.h" -#include -#include -#ifdef CONFIG_FSL_DEEP_SLEEP -#include -#endif -#include - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 1) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - pbsp = udimms[0]; - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->cpo_override = pbsp->cpo_override; - popts->write_data_delay = - pbsp->write_data_delay; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for %lu MT/s\n", - ddr_freq); - printf("Trying to use the highest speed (%u) parameters\n", - pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); - - /* force DDR bus width to 32 bits */ - popts->data_bus_width = 1; - popts->otf_burst_chop_en = 0; - popts->burst_length = DDR_BL8; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 1; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x46; - - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | - DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ -} - -/* DDR model number: MT40A512M8HX-093E */ -#ifdef CONFIG_SYS_DDR_RAW_TIMING -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 2147483648u, - .capacity = 2147483648u, - .primary_sdram_width = 32, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 15, - .n_col_addr = 10, - .bank_addr_bits = 2, - .bank_group_bits = 2, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 938, - .tckmax_ps = 1500, - .caslat_x = 0x000DFA00, - .taa_ps = 13500, - .trcd_ps = 13500, - .trp_ps = 13500, - .tras_ps = 33000, - .trc_ps = 46500, - .trfc1_ps = 260000, - .trfc2_ps = 160000, - .trfc4_ps = 110000, - .tfaw_ps = 21000, - .trrds_ps = 3700, - .trrdl_ps = 5300, - .tccdl_ps = 5355, - .refresh_rate_ps = 7800000, - .dq_mapping[0] = 0x0, - .dq_mapping[1] = 0x0, - .dq_mapping[2] = 0x0, - .dq_mapping[3] = 0x0, - .dq_mapping[4] = 0x0, - .dq_mapping[5] = 0x0, - .dq_mapping[6] = 0x0, - .dq_mapping[7] = 0x0, - .dq_mapping[8] = 0x0, - .dq_mapping[9] = 0x0, - .dq_mapping[10] = 0x0, - .dq_mapping[11] = 0x0, - .dq_mapping[12] = 0x0, - .dq_mapping[13] = 0x0, - .dq_mapping[14] = 0x0, - .dq_mapping[15] = 0x0, - .dq_mapping[16] = 0x0, - .dq_mapping[17] = 0x0, - .dq_mapping_ors = 0, -}; - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - static const char dimm_model[] = "Fixed DDR on board"; - - if (((controller_number == 0) && (dimm_number == 0)) || - ((controller_number == 1) && (dimm_number == 0))) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} -#else - -phys_size_t fixed_sdram(void) -{ - int i; - char buf[32]; - fsl_ddr_cfg_regs_t ddr_cfg_regs; - phys_size_t ddr_size; - ulong ddr_freq, ddr_freq_mhz; - - ddr_freq = get_ddr_freq(0); - ddr_freq_mhz = ddr_freq / 1000000; - - printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { - if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && - (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { - memcpy(&ddr_cfg_regs, - fixed_ddr_parm_0[i].ddr_settings, - sizeof(ddr_cfg_regs)); - break; - } - } - - if (fixed_ddr_parm_0[i].max_freq == 0) - panic("Unsupported DDR data rate %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - ddr_size = (phys_size_t)2048 * 1024 * 1024; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); - - return ddr_size; -} -#endif - -#ifdef CONFIG_TFABOOT -int fsl_initdram(void) -{ - gd->ram_size = tfa_get_dram_size(); - if (!gd->ram_size) -#ifdef CONFIG_SYS_DDR_RAW_TIMING - gd->ram_size = fsl_ddr_sdram_size(); -#else - gd->ram_size = 0x80000000; -#endif - return 0; -} -#else -int fsl_initdram(void) -{ - phys_size_t dram_size; - -#ifdef CONFIG_SYS_DDR_RAW_TIMING -#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_SPL) - puts("Initializing DDR....\n"); - dram_size = fsl_ddr_sdram(); -#else - dram_size = fsl_ddr_sdram_size(); -#endif -#else -#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_SPL) - puts("Initialzing DDR using fixed setting\n"); - dram_size = fixed_sdram(); -#else - gd->ram_size = 0x80000000; - - return 0; -#endif -#endif - erratum_a008850_post(); - -#ifdef CONFIG_FSL_DEEP_SLEEP - fsl_dp_ddr_restore(); -#endif - - gd->ram_size = dram_size; - - return 0; -} -#endif diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h deleted file mode 100644 index 85ed920ca6d..00000000000 --- a/board/freescale/ls1043ardb/ddr.h +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ - -extern void erratum_a008850_post(void); - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; - u32 cpo_override; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | - */ -#ifdef CONFIG_SYS_FSL_DDR4 - {1, 1666, 0, 12, 7, 0x07090800, 0x00000000,}, - {1, 1900, 0, 12, 7, 0x07090800, 0x00000000,}, - {1, 2200, 0, 12, 7, 0x07090800, 0x00000000,}, -#endif - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -#ifndef CONFIG_SYS_DDR_RAW_TIMING -fsl_ddr_cfg_regs_t ddr_cfg_regs_1600 = { - .cs[0].bnds = 0x0000007F, - .cs[1].bnds = 0, - .cs[2].bnds = 0, - .cs[3].bnds = 0, - .cs[0].config = 0x80040322, - .cs[0].config_2 = 0, - .cs[1].config = 0, - .cs[1].config_2 = 0, - .cs[2].config = 0, - .cs[3].config = 0, - .timing_cfg_3 = 0x010C1000, - .timing_cfg_0 = 0x91550018, - .timing_cfg_1 = 0xBBB48C42, - .timing_cfg_2 = 0x0048C111, - .ddr_sdram_cfg = 0xC50C0008, - .ddr_sdram_cfg_2 = 0x00401100, - .ddr_sdram_cfg_3 = 0, - .ddr_sdram_mode = 0x03010210, - .ddr_sdram_mode_2 = 0, - .ddr_sdram_mode_3 = 0x00010210, - .ddr_sdram_mode_4 = 0, - .ddr_sdram_mode_5 = 0x00010210, - .ddr_sdram_mode_6 = 0, - .ddr_sdram_mode_7 = 0x00010210, - .ddr_sdram_mode_8 = 0, - .ddr_sdram_mode_9 = 0x00000500, - .ddr_sdram_mode_10 = 0x04000000, - .ddr_sdram_mode_11 = 0x00000400, - .ddr_sdram_mode_12 = 0x04000000, - .ddr_sdram_mode_13 = 0x00000400, - .ddr_sdram_mode_14 = 0x04000000, - .ddr_sdram_mode_15 = 0x00000400, - .ddr_sdram_mode_16 = 0x04000000, - .ddr_sdram_interval = 0x18600618, - .ddr_data_init = 0xDEADBEEF, - .ddr_sdram_clk_cntl = 0x03000000, - .ddr_init_addr = 0, - .ddr_init_ext_addr = 0, - .timing_cfg_4 = 0x00000002, - .timing_cfg_5 = 0x03401400, - .timing_cfg_6 = 0, - .timing_cfg_7 = 0x13300000, - .timing_cfg_8 = 0x02115600, - .timing_cfg_9 = 0, - .ddr_zq_cntl = 0x8A090705, - .ddr_wrlvl_cntl = 0x8675F607, - .ddr_wrlvl_cntl_2 = 0x07090800, - .ddr_wrlvl_cntl_3 = 0, - .ddr_sr_cntr = 0, - .ddr_sdram_rcw_1 = 0, - .ddr_sdram_rcw_2 = 0, - .ddr_cdr1 = 0x80040000, - .ddr_cdr2 = 0x0000A181, - .dq_map_0 = 0, - .dq_map_1 = 0, - .dq_map_2 = 0, - .dq_map_3 = 0, - .debug[28] = 0x00700046, - -}; - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {1550, 1650, &ddr_cfg_regs_1600}, - {0, 0, NULL} -}; - -#endif -#endif diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c deleted file mode 100644 index cacc49c0584..00000000000 --- a/board/freescale/ls1043ardb/eth.c +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - int i; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - u32 srds_s1; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - /* QSGMII on lane B, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR); - - switch (srds_s1) { - case 0x1455: - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1043ARDB\n", - srds_s1); - break; - } - - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) - fm_info_set_mdio(i, dev); - - /* 10GBase-R on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(FM1_10GEC1, dev); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c deleted file mode 100644 index bba041065b5..00000000000 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ /dev/null @@ -1,415 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * Copyright 2021-2022 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "cpld.h" -#ifdef CONFIG_U_QE -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_TFABOOT -struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { - { - "nor", - CFG_SYS_NOR_CSPR, - CFG_SYS_NOR_CSPR_EXT, - CFG_SYS_NOR_AMASK, - CFG_SYS_NOR_CSOR, - { - CFG_SYS_NOR_FTIM0, - CFG_SYS_NOR_FTIM1, - CFG_SYS_NOR_FTIM2, - CFG_SYS_NOR_FTIM3 - }, - - }, - { - "nand", - CFG_SYS_NAND_CSPR, - CFG_SYS_NAND_CSPR_EXT, - CFG_SYS_NAND_AMASK, - CFG_SYS_NAND_CSOR, - { - CFG_SYS_NAND_FTIM0, - CFG_SYS_NAND_FTIM1, - CFG_SYS_NAND_FTIM2, - CFG_SYS_NAND_FTIM3 - }, - }, - { - "cpld", - CFG_SYS_CPLD_CSPR, - CFG_SYS_CPLD_CSPR_EXT, - CFG_SYS_CPLD_AMASK, - CFG_SYS_CPLD_CSOR, - { - CFG_SYS_CPLD_FTIM0, - CFG_SYS_CPLD_FTIM1, - CFG_SYS_CPLD_FTIM2, - CFG_SYS_CPLD_FTIM3 - }, - } -}; - -struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { - { - "nand", - CFG_SYS_NAND_CSPR, - CFG_SYS_NAND_CSPR_EXT, - CFG_SYS_NAND_AMASK, - CFG_SYS_NAND_CSOR, - { - CFG_SYS_NAND_FTIM0, - CFG_SYS_NAND_FTIM1, - CFG_SYS_NAND_FTIM2, - CFG_SYS_NAND_FTIM3 - }, - }, - { - "nor", - CFG_SYS_NOR_CSPR, - CFG_SYS_NOR_CSPR_EXT, - CFG_SYS_NOR_AMASK, - CFG_SYS_NOR_CSOR, - { - CFG_SYS_NOR_FTIM0, - CFG_SYS_NOR_FTIM1, - CFG_SYS_NOR_FTIM2, - CFG_SYS_NOR_FTIM3 - }, - }, - { - "cpld", - CFG_SYS_CPLD_CSPR, - CFG_SYS_CPLD_CSPR_EXT, - CFG_SYS_CPLD_AMASK, - CFG_SYS_CPLD_CSOR, - { - CFG_SYS_CPLD_FTIM0, - CFG_SYS_CPLD_FTIM1, - CFG_SYS_CPLD_FTIM2, - CFG_SYS_CPLD_FTIM3 - }, - } -}; - -void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) -{ - enum boot_src src = get_boot_src(); - - if (src == BOOT_SOURCE_IFC_NAND) - regs_info->regs = ifc_cfg_nand_boot; - else - regs_info->regs = ifc_cfg_nor_boot; - regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; -} - -#endif -int board_early_init_f(void) -{ - fsl_lsch2_early_init_f(); - - return 0; -} - -#ifndef CONFIG_XPL_BUILD - -int checkboard(void) -{ -#ifdef CONFIG_TFABOOT - enum boot_src src = get_boot_src(); -#endif - static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; -#ifndef CONFIG_SD_BOOT - u8 cfg_rcw_src1, cfg_rcw_src2; - u16 cfg_rcw_src; -#endif - u8 sd1refclk_sel; - - printf("Board: LS1043ARDB, boot from "); - -#ifdef CONFIG_TFABOOT - if (src == BOOT_SOURCE_SD_MMC) - puts("SD\n"); - else { -#endif - -#ifdef CONFIG_SD_BOOT - puts("SD\n"); -#else - cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); - cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); - cpld_rev_bit(&cfg_rcw_src1); - cfg_rcw_src = cfg_rcw_src1; - cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; - - if (cfg_rcw_src == 0x25) - printf("vBank %d\n", CPLD_READ(vbank)); - else if ((cfg_rcw_src == 0x106) || (cfg_rcw_src == 0x118)) - puts("NAND\n"); - else - printf("Invalid setting of SW4\n"); -#endif - -#ifdef CONFIG_TFABOOT - } -#endif - printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), - CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); - - puts("SERDES Reference Clocks:\n"); - sd1refclk_sel = CPLD_READ(sd1refclk_sel); - printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); - - return 0; -} - -int board_init(void) -{ - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; - -#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 - erratum_a010315(); -#endif - -#ifdef CONFIG_FSL_IFC - init_final_memctl_regs(); -#endif - -#ifdef CONFIG_NXP_ESBC - /* In case of Secure Boot, the IBR configures the SMMU - * to allow only Secure transactions. - * SMMU must be reset in bypass mode. - * Set the ClientPD bit and Clear the USFCFG Bit - */ - u32 val; - val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); - out_le32(SMMU_SCR0, val); - val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); - out_le32(SMMU_NSCR0, val); -#endif - -#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) - pci_init(); -#endif - -#ifdef CONFIG_U_QE - u_qe_init(); -#endif - /* invert AQR105 IRQ pins polarity */ - out_be32(&scfg->intpcr, AQR105_IRQ_MASK); - - return 0; -} - -int config_board_mux(void) -{ - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; - u32 usb_pwrfault; - - if (hwconfig("qe-hdlc")) { - out_be32(&scfg->rcwpmuxcr0, - (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600); - printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n", - in_be32(&scfg->rcwpmuxcr0)); - } else { -#ifdef CONFIG_HAS_FSL_XHCI_USB - out_be32(&scfg->rcwpmuxcr0, 0x3333); - out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); - usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << - SCFG_USBPWRFAULT_USB3_SHIFT) | - (SCFG_USBPWRFAULT_DEDICATED << - SCFG_USBPWRFAULT_USB2_SHIFT) | - (SCFG_USBPWRFAULT_SHARED << - SCFG_USBPWRFAULT_USB1_SHIFT); - out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); -#endif - } - return 0; -} - -#if defined(CONFIG_MISC_INIT_R) -int misc_init_r(void) -{ - config_board_mux(); - return 0; -} -#endif - -void fdt_del_qe(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "fsl,qe")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -/* Update the address of the Aquantia PHY on the MDIO bus for boards revision - * v7.0 and up. Also rename the PHY node to align with the address change. - */ -void fdt_fixup_phy_addr(void *blob) -{ - const char phy_path[] = - "/soc/fman@1a00000/mdio@fd000/ethernet-phy@1"; - int ret, offset, new_addr = AQR113C_PHY_ADDR; - char new_name[] = "ethernet-phy@00"; - - if (CPLD_READ(pcba_ver) < 0x7) - return; - - offset = fdt_path_offset(blob, phy_path); - if (offset < 0) { - printf("ethernet-phy@1 node not found in the dts\n"); - return; - } - - ret = fdt_setprop_u32(blob, offset, "reg", new_addr); - if (ret < 0) { - printf("Unable to set 'reg' for node ethernet-phy@1: %s\n", - fdt_strerror(ret)); - return; - } - - sprintf(new_name, "ethernet-phy@%x", new_addr); - ret = fdt_set_name(blob, offset, new_name); - if (ret < 0) - printf("Unable to rename node ethernet-phy@1: %s\n", - fdt_strerror(ret)); -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; - - /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; - - fdt_fixup_memory_banks(blob, base, size, 2); - ft_cpu_setup(blob, bd); - -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif - fdt_fixup_phy_addr(blob); -#endif - - fdt_fixup_icid(blob); - - /* - * qe-hdlc and usb multi-use the pins, - * when set hwconfig to qe-hdlc, delete usb node. - */ - if (hwconfig("qe-hdlc")) -#ifdef CONFIG_HAS_FSL_XHCI_USB - fdt_del_node_and_alias(blob, "usb1"); -#endif - /* - * qe just support qe-uart and qe-hdlc, - * if qe-uart and qe-hdlc are not set in hwconfig, - * delete qe node. - */ - if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc")) - fdt_del_qe(blob); - - return 0; -} - -void nand_fixup(void) -{ - u32 csor = 0; - - if (CPLD_READ(pcba_ver) < 0x7) - return; - - /* Change NAND Flash PGS/SPRZ configuration */ - csor = CFG_SYS_NAND_CSOR; - if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) - csor = (csor & ~(CSOR_NAND_PGS_MASK)) | CSOR_NAND_PGS_4K; - - if ((csor & CSOR_NAND_SPRZ_MASK) == CSOR_NAND_SPRZ_64) - csor = (csor & ~(CSOR_NAND_SPRZ_MASK)) | CSOR_NAND_SPRZ_224; - - if (IS_ENABLED(CONFIG_TFABOOT)) { - u8 cfg_rcw_src1, cfg_rcw_src2; - u16 cfg_rcw_src; - - cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); - cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); - cpld_rev_bit(&cfg_rcw_src1); - cfg_rcw_src = cfg_rcw_src1; - cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; - - if (cfg_rcw_src == 0x25) - set_ifc_csor(IFC_CS1, csor); - else if (cfg_rcw_src == 0x118) - set_ifc_csor(IFC_CS0, csor); - else - printf("Invalid setting\n"); - } else { - if (IS_ENABLED(CONFIG_NAND_BOOT)) - set_ifc_csor(IFC_CS0, csor); - else - set_ifc_csor(IFC_CS1, csor); - } -} - -#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) -int board_fix_fdt(void *blob) -{ - /* nand driver fix up */ - nand_fixup(); - - /* fdt fix up */ - fdt_fixup_phy_addr(blob); - - return 0; -} -#endif - -u8 flash_read8(void *addr) -{ - return __raw_readb(addr + 1); -} - -void flash_write16(u16 val, void *addr) -{ - u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); - - __raw_writew(shftval, addr); -} - -u16 flash_read16(void *addr) -{ - u16 val = __raw_readw(addr); - - return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); -} - -#endif diff --git a/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg deleted file mode 100644 index f072274f474..00000000000 --- a/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg +++ /dev/null @@ -1,14 +0,0 @@ -#Configure Scratch register -09570600 00000000 -09570604 10000000 -#Alt base register -09570158 00001000 -#Disable CCI barrier tranaction -09570178 0000e010 -09180000 00000008 -#USB PHY frequency sel -09570418 0000009e -0957041c 0000009e -09570420 0000009e -#flush PBI data -096100c0 000fffff diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg deleted file mode 100644 index d87058b7efe..00000000000 --- a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 -# serdes protocol -08100010 0a000000 00000000 00000000 -14550002 80004012 e0106000 c1002000 -00000000 00000000 00000000 00038800 -00000000 00001100 00000096 00000001 diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg deleted file mode 100644 index e2ee34b7dfc..00000000000 --- a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 -# RCW -08100010 0a000000 00000000 00000000 -14550002 80004012 60040000 c1002000 -00000000 00000000 00000000 00038800 -00000000 00001100 00000096 00000001 diff --git a/board/freescale/ls1046afrwy/Kconfig b/board/freescale/ls1046afrwy/Kconfig deleted file mode 100644 index 68329d78caf..00000000000 --- a/board/freescale/ls1046afrwy/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ - -if TARGET_LS1046AFRWY - -config SYS_BOARD - default "ls1046afrwy" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls1046afrwy" - -endif diff --git a/board/freescale/ls1046afrwy/MAINTAINERS b/board/freescale/ls1046afrwy/MAINTAINERS deleted file mode 100644 index 8f360e1820f..00000000000 --- a/board/freescale/ls1046afrwy/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -LS1046AFRWY BOARD -M: Pramod Kumar -S: Maintained -F: board/freescale/ls1046afrwy/ -F: board/freescale/ls1046afrwy/ls1046afrwy.c -F: include/configs/ls1046afrwy.h -F: configs/ls1046afrwy_tfa_defconfig -F: configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1046afrwy/Makefile b/board/freescale/ls1046afrwy/Makefile deleted file mode 100644 index c70f5cda797..00000000000 --- a/board/freescale/ls1046afrwy/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2019 NXP - -obj-y += ddr.o -obj-y += ls1046afrwy.o -obj-$(CONFIG_NET) += eth.o diff --git a/board/freescale/ls1046afrwy/README b/board/freescale/ls1046afrwy/README deleted file mode 100644 index 2c7c797a879..00000000000 --- a/board/freescale/ls1046afrwy/README +++ /dev/null @@ -1,76 +0,0 @@ -Overview --------- -The LS1046A Freeway Board (iFRWY) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS1046A -LayerScape Architecture processor. The FRWY-LS1046A provides SW development -platform for the Freescale LS1046A processor series, with a complete -debugging environment. The FRWY-LS1046A is lead-free and RoHS-compliant. - -LS1046A SoC Overview --------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A -SoC overview. - - FRWY-LS1046A board Overview - ----------------------- - - SERDES1 Connections, 4 lanes supporting: - - Lane0: Unused - - Lane1: Unused - - Lane2: QSGMII - - Lane3: Unused - - SERDES2 Connections, 4 lanes supporting: - - Lane0: Unused - - Lane1: PCIe3 with PCIe x1 slot - - Lane2: Unused - - Lane3: PCIe3 with PCIe x1 slot - - DDR Controller - - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s - -IFC/Local Bus - - One 512 MB NAND flash with ECC support - - USB 3.0 - - Two Type A port - - SDHC: connects directly to a full microSD slot - - QSPI: 64 MB high-speed flash Memory for boot code and storage - - 4 I2C controllers - - UART - - Two 4-pin serial ports at up to 115.2 Kbit/s - - Two DB9 D-Type connectors supporting one Serial port each - - ARM JTAG support - -Memory map from core's view ----------------------------- -Start Address End Address Description Size -0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB -0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB -0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB -0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB -0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB -0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB -0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB -0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB -0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M -0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M -0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB -0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G -0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G -0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G - -QSPI flash map: -Start Address End Address Description Size -0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI + BL2 1MB -0x00_4010_0000 - 0x00_404F_FFFF FIP Image - (Bl31 + BL32(optee. - bin) + Bl33(uboot) - + headers for secure - boot) 4MB -0x00_4050_0000 - 0x00_405F_FFFF Boot Firmware Env 1MB -0x00_4060_0000 - 0x00_408F_FFFF Secure boot headers 3MB -0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB -0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB -0x00_409C_0000 - 0x00_409F_FFFF Reserved 256KB -0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB - -Booting Options ---------------- -a) QSPI boot -b) microSD boot diff --git a/board/freescale/ls1046afrwy/ddr.c b/board/freescale/ls1046afrwy/ddr.c deleted file mode 100644 index b08caee1d97..00000000000 --- a/board/freescale/ls1046afrwy/ddr.c +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 NXP - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int fsl_initdram(void) -{ - gd->ram_size = tfa_get_dram_size(); - - if (!gd->ram_size) - gd->ram_size = fsl_ddr_sdram_size(); - - return 0; -} diff --git a/board/freescale/ls1046afrwy/eth.c b/board/freescale/ls1046afrwy/eth.c deleted file mode 100644 index 8efc7f68424..00000000000 --- a/board/freescale/ls1046afrwy/eth.c +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 NXP - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct memac_mdio_info dtsec_mdio_info; - struct mii_dev *dev; - u32 srds_s1; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - /* QSGMII on lane B, MAC 6/5/10/1 */ - fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR); - - switch (srds_s1) { - case 0x3040: - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n", - srds_s1); - break; - } - - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(FM1_DTSEC6, dev); - fm_info_set_mdio(FM1_DTSEC5, dev); - fm_info_set_mdio(FM1_DTSEC10, dev); - fm_info_set_mdio(FM1_DTSEC1, dev); - - fm_disable_port(FM1_DTSEC9); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} - -#ifdef CONFIG_FMAN_ENET -int fdt_update_ethernet_dt(void *blob) -{ - u32 srds_s1; - int i, prop; - int offset, nodeoff; - const char *path; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - /* Cycle through all aliases */ - for (prop = 0; ; prop++) { - const char *name; - - /* FDT might have been edited, recompute the offset */ - offset = fdt_first_property_offset(blob, - fdt_path_offset(blob, - "/aliases") - ); - /* Select property number 'prop' */ - for (i = 0; i < prop; i++) - offset = fdt_next_property_offset(blob, offset); - - if (offset < 0) - break; - - path = fdt_getprop_by_offset(blob, offset, &name, NULL); - nodeoff = fdt_path_offset(blob, path); - - switch (srds_s1) { - case 0x3040: - if (!strcmp(name, "ethernet1")) - fdt_status_disabled(blob, nodeoff); - if (!strcmp(name, "ethernet2")) - fdt_status_disabled(blob, nodeoff); - if (!strcmp(name, "ethernet3")) - fdt_status_disabled(blob, nodeoff); - if (!strcmp(name, "ethernet6")) - fdt_status_disabled(blob, nodeoff); - break; - default: - printf("%s:Invalid SerDes prtcl 0x%x for LS1046AFRWY\n", - __func__, srds_s1); - break; - } - } - - return 0; -} -#endif diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c deleted file mode 100644 index 8889c24f1f0..00000000000 --- a/board/freescale/ls1046afrwy/ls1046afrwy.c +++ /dev/null @@ -1,218 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019, 2021 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/i2c_mux.h" - -#define LS1046A_PORSR1_REG 0x1EE0000 -#define BOOT_SRC_SD 0x20000000 -#define BOOT_SRC_MASK 0xFF800000 -#define BOARD_REV_GPIO_SHIFT 17 -#define BOARD_REV_MASK 0x03 -#define USB2_SEL_MASK 0x00000100 - -#define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \ -(((word) & 0x00ff0000) >> 8) | \ -(((word) & 0x0000ff00) << 8) | \ -(((word) & 0x000000ff) << 24)) -#define SPI_MCR_REG 0x2100000 - -DECLARE_GLOBAL_DATA_PTR; - -static inline void demux_select_usb2(void) -{ - u32 val; - struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR); - - val = in_be32(&pgpio->gpdir); - val |= USB2_SEL_MASK; - out_be32(&pgpio->gpdir, val); - - val = in_be32(&pgpio->gpdat); - val |= USB2_SEL_MASK; - out_be32(&pgpio->gpdat, val); -} - -static inline void set_spi_cs_signal_inactive(void) -{ - /* default: all CS signals inactive state is high */ - uint mcr_val; - uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK | - DSPI_MCR_CRXF | DSPI_MCR_CTXF; - - mcr_val = in_be32(SPI_MCR_REG); - mcr_val |= DSPI_MCR_HALT; - out_be32(SPI_MCR_REG, mcr_val); - out_be32(SPI_MCR_REG, mcr_cfg_val); - mcr_val = in_be32(SPI_MCR_REG); - mcr_val &= ~DSPI_MCR_HALT; - out_be32(SPI_MCR_REG, mcr_val); -} - -int board_early_init_f(void) -{ - fsl_lsch2_early_init_f(); - - return 0; -} - -static inline uint8_t get_board_version(void) -{ - struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR); - - /* GPIO 13 and GPIO 14 are used for Board Rev */ - u32 gpio_val = ((in_be32(&pgpio->gpdat) >> BOARD_REV_GPIO_SHIFT)) - & BOARD_REV_MASK; - - /* GPIOs' are 0..31 in Big Endiness, swap GPIO 13 and GPIO 14 */ - u8 val = ((gpio_val >> 1) | (gpio_val << 1)) & BOARD_REV_MASK; - - return val; -} - -int checkboard(void) -{ - static const char *freq[2] = {"100.00MHZ", "100.00MHZ"}; - u32 boot_src; - u8 rev; - - rev = get_board_version(); - switch (rev) { - case 0x00: - puts("Board: LS1046AFRWY, Rev: A, boot from "); - break; - case 0x01: - puts("Board: LS1046AFRWY, Rev: B, boot from "); - break; - default: - puts("Board: LS1046AFRWY, Rev: Unknown, boot from "); - break; - } - boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG)); - - if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD) - puts("SD\n"); - else - puts("QSPI\n"); - printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]); - - return 0; -} - -int board_init(void) -{ -#ifdef CONFIG_NXP_ESBC - /* - * In case of Secure Boot, the IBR configures the SMMU - * to allow only Secure transactions. - * SMMU must be reset in bypass mode. - * Set the ClientPD bit and Clear the USFCFG Bit - */ - u32 val; -val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); - out_le32(SMMU_SCR0, val); - val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); - out_le32(SMMU_NSCR0, val); -#endif - - if (!IS_ENABLED(CONFIG_SYS_EARLY_PCI_INIT)) - pci_init(); - - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - return 0; -} - -int board_setup_core_volt(u32 vdd) -{ - return 0; -} - -void config_board_mux(void) -{ -#ifdef CONFIG_HAS_FSL_XHCI_USB - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; - u32 usb_pwrfault; - /* - * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT - * USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA - */ - out_be32(&scfg->rcwpmuxcr0, 0x3300); -#ifdef CONFIG_HAS_FSL_IIC3 - /* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */ - out_be32(&scfg->rcwpmuxcr0, 0x0000); -#endif - out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); - usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << - SCFG_USBPWRFAULT_USB3_SHIFT) | - (SCFG_USBPWRFAULT_DEDICATED << - SCFG_USBPWRFAULT_USB2_SHIFT) | - (SCFG_USBPWRFAULT_SHARED << - SCFG_USBPWRFAULT_USB1_SHIFT); - out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); -#ifndef CONFIG_HAS_FSL_IIC3 - /* - * LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input - * to select I2C3_USB2_SEL_IO - * I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to - * I2C3 header (default) - * I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to - * USB2 port - * programmed to select USB2 by setting GPIO3_23 output to one - */ - demux_select_usb2(); -#endif -#endif - set_spi_cs_signal_inactive(); -} - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ - config_board_mux(); - return 0; -} -#endif - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; - - /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; - - fdt_fixup_memory_banks(blob, base, size, 2); - ft_cpu_setup(blob, bd); - -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif -#endif - - fdt_fixup_icid(blob); - - return 0; -} diff --git a/board/freescale/ls1046aqds/Kconfig b/board/freescale/ls1046aqds/Kconfig deleted file mode 100644 index 723f4ba90a0..00000000000 --- a/board/freescale/ls1046aqds/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_LS1046AQDS - -config SYS_BOARD - default "ls1046aqds" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls1046aqds" - -endif diff --git a/board/freescale/ls1046aqds/MAINTAINERS b/board/freescale/ls1046aqds/MAINTAINERS deleted file mode 100644 index e1db2aaa8e4..00000000000 --- a/board/freescale/ls1046aqds/MAINTAINERS +++ /dev/null @@ -1,14 +0,0 @@ -LS1046AQDS BOARD -M: Mingkai Hu -S: Maintained -F: board/freescale/ls1046aqds/ -F: include/configs/ls1046aqds.h -F: configs/ls1046aqds_defconfig -F: configs/ls1046aqds_nand_defconfig -F: configs/ls1046aqds_sdcard_ifc_defconfig -F: configs/ls1046aqds_sdcard_qspi_defconfig -F: configs/ls1046aqds_qspi_defconfig -F: configs/ls1046aqds_lpuart_defconfig -F: configs/ls1046aqds_tfa_defconfig -F: configs/ls1046aqds_tfa_SECURE_BOOT_defconfig -F: configs/ls1046aqds_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1046aqds/Makefile b/board/freescale/ls1046aqds/Makefile deleted file mode 100644 index 365247d92bc..00000000000 --- a/board/freescale/ls1046aqds/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright 2016 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += ddr.o -ifndef CONFIG_XPL_BUILD -obj-y += eth.o -endif -obj-y += ls1046aqds.o diff --git a/board/freescale/ls1046aqds/README b/board/freescale/ls1046aqds/README deleted file mode 100644 index cb694735a46..00000000000 --- a/board/freescale/ls1046aqds/README +++ /dev/null @@ -1,70 +0,0 @@ -Overview --------- -The LS1046A Development System (QDS) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS1046A -LayerScape Architecture processor. The LS1046AQDS provides SW development -platform for the Freescale LS1046A processor series, with a complete -debugging environment. - -LS1046A SoC Overview --------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A -SoC overview. - - LS1046AQDS board Overview - ----------------------- - - SERDES Connections, 8 lanes supporting: - - PCI Express - 3.0 - - SGMII, SGMII 2.5 - - QSGMII - - SATA 3.0 - - 10GBase-R - - DDR Controller - - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s - -IFC/Local Bus - - One in-socket 128 MB NOR flash 16-bit data bus - - One 512 MB NAND flash with ECC support - - PromJet Port - - FPGA connection - - USB 3.0 - - Three high speed USB 3.0 ports - - First USB 3.0 port configured as Host with Type-A connector - - The other two USB 3.0 ports configured as OTG with micro-AB connector - - SDHC port connects directly to an adapter card slot, featuring: - - Optional clock feedback paths, and optional high-speed voltage translation assistance - - SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC - - eMMC memory devices - - DSPI: Onboard support for three SPI flash memory devices - - 4 I2C controllers - - One SATA onboard connectors - - UART - - Two 4-pin serial ports at up to 115.2 Kbit/s - - Two DB9 D-Type connectors supporting one Serial port each - - ARM JTAG support - -Memory map from core's view ----------------------------- -Start Address End Address Description Size -0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB -0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB -0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB -0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB -0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB -0x00_6000_0000 - 0x00_67FF_FFFF IFC - NOR Flash 128MB -0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB -0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - FPGA 4KB -0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB -0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M -0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M -0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB -0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G -0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G -0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G - -Booting Options ---------------- -a) Promjet Boot -b) NOR boot -c) NAND boot -d) SD boot -e) QSPI boot diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c deleted file mode 100644 index 57790335f0a..00000000000 --- a/board/freescale/ls1046aqds/ddr.c +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -#include -#include -#ifdef CONFIG_FSL_DEEP_SLEEP -#include -#endif -#include -#include -#include -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 3) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - pbsp = udimms[0]; - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for %lu MT/s\n", - ddr_freq); - printf("Trying to use the highest speed (%u) parameters\n", - pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); - - popts->data_bus_width = 0; /* 64b data bus */ - popts->otf_burst_chop_en = 0; - popts->burst_length = DDR_BL8; - popts->bstopre = 0; /* enable auto precharge */ - - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | - DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; - - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x70; -} - -#ifdef CONFIG_TFABOOT -int fsl_initdram(void) -{ - gd->ram_size = tfa_get_dram_size(); - if (!gd->ram_size) - gd->ram_size = fsl_ddr_sdram_size(); - - return 0; -} -#else -int fsl_initdram(void) -{ - phys_size_t dram_size; - -#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) - gd->ram_size = fsl_ddr_sdram_size(); - - return 0; -#else - puts("Initializing DDR....using SPD\n"); - - dram_size = fsl_ddr_sdram(); -#endif - -#ifdef CONFIG_FSL_DEEP_SLEEP - fsl_dp_ddr_restore(); -#endif - - erratum_a008850_post(); - - gd->ram_size = dram_size; - - return 0; -} -#endif diff --git a/board/freescale/ls1046aqds/ddr.h b/board/freescale/ls1046aqds/ddr.h deleted file mode 100644 index e55446f2b29..00000000000 --- a/board/freescale/ls1046aqds/ddr.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ - -void erratum_a008850_post(void); - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | - */ - {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, - {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2300, 0, 8, 9, 0x0A0C0D11, 0x1214150E,}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -#endif diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c deleted file mode 100644 index cd3500c2e96..00000000000 --- a/board/freescale/ls1046aqds/eth.c +++ /dev/null @@ -1,431 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2018-2020 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/qixis.h" -#include "../common/fman.h" -#include "ls1046aqds_qixis.h" - -#define EMI_NONE 0xFF -#define EMI1_RGMII1 0 -#define EMI1_RGMII2 1 -#define EMI1_SLOT1 2 -#define EMI1_SLOT2 3 -#define EMI1_SLOT4 4 - -static const char * const mdio_names[] = { - "LS1046AQDS_MDIO_RGMII1", - "LS1046AQDS_MDIO_RGMII2", - "LS1046AQDS_MDIO_SLOT1", - "LS1046AQDS_MDIO_SLOT2", - "LS1046AQDS_MDIO_SLOT4", - "NULL", -}; - -/* Map SerDes 1 & 2 lanes to default slot. */ -#ifdef CONFIG_FMAN_ENET -static int mdio_mux[NUM_FM_PORTS]; - -static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0}; -#endif - -static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name; - - if (muxval > EMI1_SLOT4) - return NULL; - - name = ls1046aqds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -#ifdef CONFIG_FMAN_ENET -struct ls1046aqds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void ls1046aqds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - - if (muxval < 7) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct ls1046aqds_mdio *priv = bus->priv; - - ls1046aqds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct ls1046aqds_mdio *priv = bus->priv; - - ls1046aqds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, - regnum, value); -} - -static int ls1046aqds_mdio_reset(struct mii_dev *bus) -{ - struct ls1046aqds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int ls1046aqds_mdio_init(char *realbusname, u8 muxval) -{ - struct ls1046aqds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate ls1046aqds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate ls1046aqds private data\n"); - free(bus); - return -1; - } - - bus->read = ls1046aqds_mdio_read; - bus->write = ls1046aqds_mdio_write; - bus->reset = ls1046aqds_mdio_reset; - sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - struct fixed_link f_link; - const char *phyconn; - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - switch (port) { - case FM1_DTSEC9: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p1"); - break; - case FM1_DTSEC10: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p2"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p3"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p4"); - break; - case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s4-p1"); - break; - default: - break; - } - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) { - /* 2.5G SGMII interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(1000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 2.5G SGMII on QDS */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "2500base-x"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { - switch (port) { - case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p4"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p2"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p1"); - break; - case FM1_DTSEC10: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p3"); - break; - default: - break; - } - fdt_delprop(fdt, offset, "phy-connection-type"); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "qsgmii"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && - (port == FM1_10GEC1 || port == FM1_10GEC2)) { - phyconn = fdt_getprop(fdt, offset, "phy-connection-type", NULL); - if (is_backplane_mode(phyconn)) { - /* Backplane KR mode: skip fixups */ - printf("Interface %d in backplane KR mode\n", port); - } else { - /* 10GBase-R interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(10000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 10GBase-R */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, - sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "xgmii"); - } - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - int i; - - for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - switch (mdio_mux[i]) { - case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1-slot1"); - break; - case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1-slot2"); - break; - case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1-slot4"); - break; - default: - break; - } - break; - default: - break; - } - } -} - -int board_eth_init(struct bd_info *bis) -{ - int i, idx, lane, slot, interface; - struct memac_mdio_info dtsec_mdio_info; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 srds_s1, srds_s2; - u8 brdcfg12; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - srds_s2 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; - srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT; - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x3333: - /* SGMII on slot 1, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - case 0x1333: - case 0x2333: - /* SGMII on slot 1, MAC 10 */ - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - case 0x1133: - case 0x2233: - /* SGMII on slot 1, MAC 5/6 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x1040: - case 0x2040: - /* QSGMII on lane B, MAC 6/5/10/1 */ - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT1_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT2_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC10, - QSGMII_CARD_PORT3_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT4_PHY_ADDR_S2); - break; - case 0x3363: - /* SGMII on slot 1, MAC 9/10 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - case 0x1163: - case 0x2263: - case 0x2223: - /* SGMII on slot 1, MAC 6 */ - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n", - srds_s1); - break; - } - - if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06) - /* SGMII on slot 4, MAC 2 */ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - if (interface == PHY_INTERFACE_MODE_SGMII) { - if (i == FM1_DTSEC5) { - /* route lane 2 to slot1 so to have - * one sgmii riser card supports - * MAC5 and MAC6. - */ - brdcfg12 = QIXIS_READ(brdcfg[12]); - QIXIS_WRITE(brdcfg[12], - brdcfg12 | 0x80); - } - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - } else { - /* clear the bit 7 to route lane B on slot2. */ - brdcfg12 = QIXIS_READ(brdcfg[12]); - QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f); - - lane = serdes_get_first_lane(FSL_SRDS_1, - QSGMII_FM1_A); - lane_to_slot[lane] = 2; - } - - if (i == FM1_DTSEC2) - lane = 5; - - if (lane < 0) - break; - - slot = lane_to_slot[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - default: - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (i == FM1_DTSEC3) - mdio_mux[i] = EMI1_RGMII1; - else if (i == FM1_DTSEC4) - mdio_mux[i] = EMI1_RGMII2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - cpu_eth_init(bis); - - return pci_eth_init(bis); -} -#endif /* CONFIG_FMAN_ENET */ diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c deleted file mode 100644 index 7df12550868..00000000000 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ /dev/null @@ -1,479 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2019-2021 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/i2c_mux.h" - -#include "../common/vid.h" -#include "../common/qixis.h" -#include "ls1046aqds_qixis.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_TFABOOT -struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { - { - "nor0", - CFG_SYS_NOR0_CSPR, - CFG_SYS_NOR0_CSPR_EXT, - CFG_SYS_NOR_AMASK, - CFG_SYS_NOR_CSOR, - { - CFG_SYS_NOR_FTIM0, - CFG_SYS_NOR_FTIM1, - CFG_SYS_NOR_FTIM2, - CFG_SYS_NOR_FTIM3 - }, - - }, - { - "nor1", - CFG_SYS_NOR1_CSPR, - CFG_SYS_NOR1_CSPR_EXT, - CFG_SYS_NOR_AMASK, - CFG_SYS_NOR_CSOR, - { - CFG_SYS_NOR_FTIM0, - CFG_SYS_NOR_FTIM1, - CFG_SYS_NOR_FTIM2, - CFG_SYS_NOR_FTIM3 - }, - }, - { - "nand", - CFG_SYS_NAND_CSPR, - CFG_SYS_NAND_CSPR_EXT, - CFG_SYS_NAND_AMASK, - CFG_SYS_NAND_CSOR, - { - CFG_SYS_NAND_FTIM0, - CFG_SYS_NAND_FTIM1, - CFG_SYS_NAND_FTIM2, - CFG_SYS_NAND_FTIM3 - }, - }, - { - "fpga", - CFG_SYS_FPGA_CSPR, - CFG_SYS_FPGA_CSPR_EXT, - CFG_SYS_FPGA_AMASK, - CFG_SYS_FPGA_CSOR, - { - CFG_SYS_FPGA_FTIM0, - CFG_SYS_FPGA_FTIM1, - CFG_SYS_FPGA_FTIM2, - CFG_SYS_FPGA_FTIM3 - }, - } -}; - -struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { - { - "nand", - CFG_SYS_NAND_CSPR, - CFG_SYS_NAND_CSPR_EXT, - CFG_SYS_NAND_AMASK, - CFG_SYS_NAND_CSOR, - { - CFG_SYS_NAND_FTIM0, - CFG_SYS_NAND_FTIM1, - CFG_SYS_NAND_FTIM2, - CFG_SYS_NAND_FTIM3 - }, - }, - { - "nor0", - CFG_SYS_NOR0_CSPR, - CFG_SYS_NOR0_CSPR_EXT, - CFG_SYS_NOR_AMASK, - CFG_SYS_NOR_CSOR, - { - CFG_SYS_NOR_FTIM0, - CFG_SYS_NOR_FTIM1, - CFG_SYS_NOR_FTIM2, - CFG_SYS_NOR_FTIM3 - }, - }, - { - "nor1", - CFG_SYS_NOR1_CSPR, - CFG_SYS_NOR1_CSPR_EXT, - CFG_SYS_NOR_AMASK, - CFG_SYS_NOR_CSOR, - { - CFG_SYS_NOR_FTIM0, - CFG_SYS_NOR_FTIM1, - CFG_SYS_NOR_FTIM2, - CFG_SYS_NOR_FTIM3 - }, - }, - { - "fpga", - CFG_SYS_FPGA_CSPR, - CFG_SYS_FPGA_CSPR_EXT, - CFG_SYS_FPGA_AMASK, - CFG_SYS_FPGA_CSOR, - { - CFG_SYS_FPGA_FTIM0, - CFG_SYS_FPGA_FTIM1, - CFG_SYS_FPGA_FTIM2, - CFG_SYS_FPGA_FTIM3 - }, - } -}; - -void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) -{ - enum boot_src src = get_boot_src(); - - if (src == BOOT_SOURCE_IFC_NAND) - regs_info->regs = ifc_cfg_nand_boot; - else - regs_info->regs = ifc_cfg_nor_boot; - regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; -} - -#endif - -enum { - MUX_TYPE_GPIO, -}; - -int checkboard(void) -{ -#ifdef CONFIG_TFABOOT - enum boot_src src = get_boot_src(); -#endif - char buf[64]; -#ifndef CONFIG_SD_BOOT - u8 sw; -#endif - - puts("Board: LS1046AQDS, boot from "); - -#ifdef CONFIG_TFABOOT - if (src == BOOT_SOURCE_SD_MMC) - puts("SD\n"); - else { -#endif - -#ifdef CONFIG_SD_BOOT - puts("SD\n"); -#else - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank: %d\n", sw); - else if (sw == 0x8) - puts("PromJet\n"); - else if (sw == 0x9) - puts("NAND\n"); - else if (sw == 0xF) - printf("QSPI\n"); - else - printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); -#endif - -#ifdef CONFIG_TFABOOT - } -#endif - printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", - QIXIS_READ(id), QIXIS_READ(arch)); - - printf("FPGA: v%d (%s), build %d\n", - (int)QIXIS_READ(scver), qixis_read_tag(buf), - (int)qixis_read_minor()); - - return 0; -} - -bool if_board_diff_clk(void) -{ - u8 diff_conf = QIXIS_READ(brdcfg[11]); - - return diff_conf & 0x40; -} - -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); - - switch (sysclk_conf & 0x0f) { - case QIXIS_SYSCLK_64: - return 64000000; - case QIXIS_SYSCLK_83: - return 83333333; - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - case QIXIS_SYSCLK_150: - return 150000000; - case QIXIS_SYSCLK_160: - return 160000000; - case QIXIS_SYSCLK_166: - return 166666666; - } - - return 66666666; -} - -unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); - - if (if_board_diff_clk()) - return get_board_sys_clk(); - switch ((ddrclk_conf & 0x30) >> 4) { - case QIXIS_DDRCLK_100: - return 100000000; - case QIXIS_DDRCLK_125: - return 125000000; - case QIXIS_DDRCLK_133: - return 133333333; - } - - return 66666666; -} - -#ifdef CONFIG_LPUART -u32 get_lpuart_clk(void) -{ - return gd->bus_clk; -} -#endif - -int dram_init(void) -{ - /* - * When resuming from deep sleep, the I2C channel may not be - * in the default channel. So, switch to the default channel - * before accessing DDR SPD. - * - * PCA9547 mount on I2C1 bus - */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - fsl_initdram(); -#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ - defined(CONFIG_XPL_BUILD) - /* This will break-before-make MMU for DDR */ - update_early_mmu_table(); -#endif - - return 0; -} - -int i2c_multiplexer_select_vid_channel(u8 channel) -{ - return select_i2c_ch_pca9547(channel, 0); -} - -int board_early_init_f(void) -{ - u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR; -#ifdef CONFIG_HAS_FSL_XHCI_USB - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; - u32 usb_pwrfault; -#endif -#ifdef CONFIG_LPUART - u8 uart; -#endif - - /* - * Enable secure system counter for timer - */ - out_le32(cntcr, 0x1); - -#if defined(CONFIG_SYS_I2C_EARLY_INIT) - i2c_early_init_f(); -#endif - fsl_lsch2_early_init_f(); - -#ifdef CONFIG_HAS_FSL_XHCI_USB - out_be32(&scfg->rcwpmuxcr0, 0x3333); - out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); - usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << - SCFG_USBPWRFAULT_USB3_SHIFT) | - (SCFG_USBPWRFAULT_DEDICATED << - SCFG_USBPWRFAULT_USB2_SHIFT) | - (SCFG_USBPWRFAULT_SHARED << - SCFG_USBPWRFAULT_USB1_SHIFT); - out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); -#endif - -#ifdef CONFIG_LPUART - /* We use lpuart0 as system console */ - uart = QIXIS_READ(brdcfg[14]); - uart &= ~CFG_UART_MUX_MASK; - uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; - QIXIS_WRITE(brdcfg[14], uart); -#endif - - return 0; -} - -#ifdef CONFIG_FSL_DEEP_SLEEP -/* determine if it is a warm boot */ -bool is_warm_boot(void) -{ -#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) - struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; - - if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) - return 1; - - return 0; -} -#endif - -int config_board_mux(int ctrl_type) -{ - u8 reg14; - - reg14 = QIXIS_READ(brdcfg[14]); - - switch (ctrl_type) { - case MUX_TYPE_GPIO: - reg14 = (reg14 & (~0x6)) | 0x2; - break; - default: - puts("Unsupported mux interface type\n"); - return -1; - } - - QIXIS_WRITE(brdcfg[14], reg14); - - return 0; -} - -int config_serdes_mux(void) -{ - return 0; -} - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ - if (hwconfig("gpio")) - config_board_mux(MUX_TYPE_GPIO); - - return 0; -} -#endif - -int board_init(void) -{ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - -#ifdef CFG_SYS_FSL_SERDES - config_serdes_mux(); -#endif - - if (adjust_vdd(0)) - printf("Warning: Adjusting core voltage failed.\n"); - -#ifdef CONFIG_NXP_ESBC - /* - * In case of Secure Boot, the IBR configures the SMMU - * to allow only Secure transactions. - * SMMU must be reset in bypass mode. - * Set the ClientPD bit and Clear the USFCFG Bit - */ - u32 val; - val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); - out_le32(SMMU_SCR0, val); - val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); - out_le32(SMMU_NSCR0, val); -#endif - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; - u8 reg; - - /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; - - fdt_fixup_memory_banks(blob, base, size, 2); - ft_cpu_setup(blob, bd); - -#ifdef CONFIG_FMAN_ENET - fdt_fixup_board_enet(blob); -#endif - - fdt_fixup_icid(blob); - - reg = QIXIS_READ(brdcfg[0]); - reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - /* Disable IFC if QSPI is enabled */ - if (reg == 0xF) - do_fixup_by_compat(blob, "fsl,ifc", - "status", "disabled", 8 + 1, 1); - - return 0; -} -#endif - -u8 flash_read8(void *addr) -{ - return __raw_readb(addr + 1); -} - -void flash_write16(u16 val, void *addr) -{ - u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); - - __raw_writew(shftval, addr); -} - -u16 flash_read16(void *addr) -{ - u16 val = __raw_readw(addr); - - return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); -} - -#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) -void *env_sf_get_env_addr(void) -{ - return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); -} -#endif diff --git a/board/freescale/ls1046aqds/ls1046aqds_pbi.cfg b/board/freescale/ls1046aqds/ls1046aqds_pbi.cfg deleted file mode 100644 index 5a6b7b84a4c..00000000000 --- a/board/freescale/ls1046aqds/ls1046aqds_pbi.cfg +++ /dev/null @@ -1,17 +0,0 @@ -#Configure Scratch register -09570600 00000000 -09570604 10000000 -#Alt base register -09570158 00001000 -#Disable CCI barrier tranaction -09570178 0000e010 -09180000 00000008 -#USB PHY frequency sel -09570418 0000009e -0957041c 0000009e -09570420 0000009e -#Serdes SATA -09eb1300 80104e20 -09eb08dc 00502880 -#flush PBI data -096100c0 000fffff diff --git a/board/freescale/ls1046aqds/ls1046aqds_qixis.h b/board/freescale/ls1046aqds/ls1046aqds_qixis.h deleted file mode 100644 index f371056e37a..00000000000 --- a/board/freescale/ls1046aqds/ls1046aqds_qixis.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __LS1046AQDS_QIXIS_H__ -#define __LS1046AQDS_QIXIS_H__ - -/* Definitions of QIXIS Registers for LS1046AQDS */ - -/* BRDCFG4[4:7] select EC1 and EC2 as a pair */ -#define BRDCFG4_EMISEL_MASK 0xe0 -#define BRDCFG4_EMISEL_SHIFT 5 - -/* SYSCLK */ -#define QIXIS_SYSCLK_66 0x0 -#define QIXIS_SYSCLK_83 0x1 -#define QIXIS_SYSCLK_100 0x2 -#define QIXIS_SYSCLK_125 0x3 -#define QIXIS_SYSCLK_133 0x4 -#define QIXIS_SYSCLK_150 0x5 -#define QIXIS_SYSCLK_160 0x6 -#define QIXIS_SYSCLK_166 0x7 -#define QIXIS_SYSCLK_64 0x8 - -/* DDRCLK */ -#define QIXIS_DDRCLK_66 0x0 -#define QIXIS_DDRCLK_100 0x1 -#define QIXIS_DDRCLK_125 0x2 -#define QIXIS_DDRCLK_133 0x3 - -/* BRDCFG2 - SD clock*/ -#define QIXIS_SDCLK1_100 0x0 -#define QIXIS_SDCLK1_125 0x1 -#define QIXIS_SDCLK1_165 0x2 -#define QIXIS_SDCLK1_100_SP 0x3 - -#endif diff --git a/board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg b/board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg deleted file mode 100644 index b5fc08ce2ab..00000000000 --- a/board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 -# serdes protocol -0c150010 0e000000 00000000 00000000 -11335559 40005012 e0116000 c1000000 -00000000 00000000 00000000 00038800 -00000000 01001101 00000096 00000001 diff --git a/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg b/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg deleted file mode 100644 index 59d24d67908..00000000000 --- a/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 -# RCW -# Enable IFC; disable QSPI -0c150010 0e000000 00000000 00000000 -11335559 40005012 60040000 c1000000 -00000000 00000000 00000000 00038800 -00000000 01001101 00000096 00000001 diff --git a/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg b/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg deleted file mode 100644 index 9401a6f0f4f..00000000000 --- a/board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 -# RCW -# Enable QSPI; disable IFC -0c150010 0e000000 00000000 00000000 -11335559 40005012 60040000 c1000000 -00000000 00000000 00000000 00038800 -20124000 01001101 00000096 00000001 diff --git a/board/freescale/ls1046ardb/Kconfig b/board/freescale/ls1046ardb/Kconfig deleted file mode 100644 index a62255c78db..00000000000 --- a/board/freescale/ls1046ardb/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ - -if TARGET_LS1046ARDB - -config SYS_BOARD - default "ls1046ardb" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls1046ardb" - -endif diff --git a/board/freescale/ls1046ardb/MAINTAINERS b/board/freescale/ls1046ardb/MAINTAINERS deleted file mode 100644 index d5a6b261519..00000000000 --- a/board/freescale/ls1046ardb/MAINTAINERS +++ /dev/null @@ -1,16 +0,0 @@ -LS1046A BOARD -M: Mingkai Hu -S: Maintained -F: board/freescale/ls1046ardb/ -F: board/freescale/ls1046ardb/ls1046ardb.c -F: include/configs/ls1046ardb.h -F: configs/ls1046ardb_qspi_defconfig -F: configs/ls1046ardb_qspi_spl_defconfig -F: configs/ls1046ardb_sdcard_defconfig -F: configs/ls1046ardb_emmc_defconfig -F: configs/ls1046ardb_tfa_defconfig -F: configs/ls1046ardb_tfa_SECURE_BOOT_defconfig -F: configs/ls1046ardb_SECURE_BOOT_defconfig -F: configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig -F: configs/ls1046ardb_qspi_SECURE_BOOT_defconfig -F: doc/board/nxp/ls1046ardb.rst diff --git a/board/freescale/ls1046ardb/Makefile b/board/freescale/ls1046ardb/Makefile deleted file mode 100644 index 9e5d24f53c8..00000000000 --- a/board/freescale/ls1046ardb/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2016 Freescale Semiconductor - -obj-y += ddr.o -obj-y += ls1046ardb.o -ifndef CONFIG_XPL_BUILD -obj-$(CONFIG_NET) += eth.o -obj-y += cpld.o -endif diff --git a/board/freescale/ls1046ardb/cpld.c b/board/freescale/ls1046ardb/cpld.c deleted file mode 100644 index 26a5962bd6e..00000000000 --- a/board/freescale/ls1046ardb/cpld.c +++ /dev/null @@ -1,167 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor - * - * Freescale LS1046ARDB board-specific CPLD controlling supports. - */ - -#include -#include -#include -#include -#include "cpld.h" - -u8 cpld_read(unsigned int reg) -{ - void *p = (void *)CFG_SYS_CPLD_BASE; - - return in_8(p + reg); -} - -void cpld_write(unsigned int reg, u8 value) -{ - void *p = (void *)CFG_SYS_CPLD_BASE; - - out_8(p + reg, value); -} - -/* Set the boot bank to the alternate bank */ -void cpld_set_altbank(void) -{ - u16 reg = CPLD_CFG_RCW_SRC_QSPI; - u8 reg4 = CPLD_READ(soft_mux_on); - u8 reg5 = (u8)(reg >> 1); - u8 reg6 = (u8)(reg & 1); - u8 reg7 = CPLD_READ(vbank); - - cpld_rev_bit(®5); - - CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); - - CPLD_WRITE(cfg_rcw_src1, reg5); - CPLD_WRITE(cfg_rcw_src2, reg6); - - reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; - CPLD_WRITE(vbank, reg7); - - CPLD_WRITE(system_rst, 1); -} - -/* Set the boot bank to the default bank */ -void cpld_set_defbank(void) -{ - u16 reg = CPLD_CFG_RCW_SRC_QSPI; - u8 reg4 = CPLD_READ(soft_mux_on); - u8 reg5 = (u8)(reg >> 1); - u8 reg6 = (u8)(reg & 1); - - cpld_rev_bit(®5); - - CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); - - CPLD_WRITE(cfg_rcw_src1, reg5); - CPLD_WRITE(cfg_rcw_src2, reg6); - - CPLD_WRITE(vbank, 0); - - CPLD_WRITE(system_rst, 1); -} - -void cpld_set_sd(void) -{ - u16 reg = CPLD_CFG_RCW_SRC_SD; - u8 reg5 = (u8)(reg >> 1); - u8 reg6 = (u8)(reg & 1); - - cpld_rev_bit(®5); - - CPLD_WRITE(soft_mux_on, 1); - - CPLD_WRITE(cfg_rcw_src1, reg5); - CPLD_WRITE(cfg_rcw_src2, reg6); - - CPLD_WRITE(system_rst, 1); -} - -void cpld_select_core_volt(bool en_0v9) -{ - u8 reg17 = en_0v9; - - CPLD_WRITE(vdd_en, 1); - CPLD_WRITE(vdd_sel, reg17); -} - -#ifdef DEBUG -static void cpld_dump_regs(void) -{ - printf("cpld_ver = %x\n", CPLD_READ(cpld_ver)); - printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub)); - printf("pcba_ver = %x\n", CPLD_READ(pcba_ver)); - printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on)); - printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1)); - printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2)); - printf("vbank = %x\n", CPLD_READ(vbank)); - printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel)); - printf("uart_sel = %x\n", CPLD_READ(uart_sel)); - printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel)); - printf("rgmii_1588_sel = %x\n", CPLD_READ(rgmii_1588_sel)); - printf("1588_clk_sel = %x\n", CPLD_READ(reg_1588_clk_sel)); - printf("status_led = %x\n", CPLD_READ(status_led)); - printf("sd_emmc = %x\n", CPLD_READ(sd_emmc)); - printf("vdd_en = %x\n", CPLD_READ(vdd_en)); - printf("vdd_sel = %x\n", CPLD_READ(vdd_sel)); - putc('\n'); -} -#endif - -void cpld_rev_bit(unsigned char *value) -{ - u8 rev_val, val; - int i; - - val = *value; - rev_val = val & 1; - for (i = 1; i <= 7; i++) { - val >>= 1; - rev_val <<= 1; - rev_val |= val & 1; - } - - *value = rev_val; -} - -int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - int rc = 0; - - if (argc <= 1) - return cmd_usage(cmdtp); - - if (strcmp(argv[1], "reset") == 0) { - if (strcmp(argv[2], "altbank") == 0) - cpld_set_altbank(); - else if (strcmp(argv[2], "sd") == 0) - cpld_set_sd(); - else - cpld_set_defbank(); -#ifdef DEBUG - } else if (strcmp(argv[1], "dump") == 0) { - cpld_dump_regs(); -#endif - } else { - rc = cmd_usage(cmdtp); - } - - return rc; -} - -U_BOOT_CMD( - cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, - "Reset the board or alternate bank", - "reset: reset to default bank\n" - "cpld reset altbank: reset to alternate bank\n" - "cpld reset sd: reset to boot from SD card\n" -#ifdef DEBUG - "cpld dump - display the CPLD registers\n" -#endif -); diff --git a/board/freescale/ls1046ardb/cpld.h b/board/freescale/ls1046ardb/cpld.h deleted file mode 100644 index e87044f5c0d..00000000000 --- a/board/freescale/ls1046ardb/cpld.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Freescale Semiconductor - */ - -#ifndef __CPLD_H__ -#define __CPLD_H__ - -/* - * CPLD register set of LS1046ARDB board-specific. - * CPLD Revision: V2.1 - */ -struct cpld_data { - u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ - u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ - u8 pcba_ver; /* 0x2 - PCBA Revision Register */ - u8 system_rst; /* 0x3 - system reset register */ - u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */ - u8 cfg_rcw_src1; /* 0x5 - RCW Source Location POR Regsiter 1 */ - u8 cfg_rcw_src2; /* 0x6 - RCW Source Location POR Regsiter 2 */ - u8 vbank; /* 0x7 - QSPI Flash Bank Setting Register */ - u8 sysclk_sel; /* 0x8 - System clock POR Register */ - u8 uart_sel; /* 0x9 - UART1 Connection Control Register */ - u8 sd1refclk_sel; /* 0xA - */ - u8 rgmii_1588_sel; /* 0xB - */ - u8 reg_1588_clk_sel; /* 0xC - */ - u8 status_led; /* 0xD - */ - u8 global_rst; /* 0xE - */ - u8 sd_emmc; /* 0xF - SD/EMMC Interface Control Regsiter */ - u8 vdd_en; /* 0x10 - VDD Voltage Control Enable Register */ - u8 vdd_sel; /* 0x11 - VDD Voltage Control Register */ -}; - -u8 cpld_read(unsigned int reg); -void cpld_write(unsigned int reg, u8 value); -void cpld_rev_bit(unsigned char *value); -void cpld_select_core_volt(bool en_0v9); - -#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) -#define CPLD_WRITE(reg, value) \ - cpld_write(offsetof(struct cpld_data, reg), value) - -/* CPLD on IFC */ -#define CPLD_SW_MUX_BANK_SEL 0x40 -#define CPLD_BANK_SEL_MASK 0x07 -#define CPLD_BANK_SEL_ALTBANK 0x04 -#define CPLD_CFG_RCW_SRC_QSPI 0x044 -#define CPLD_CFG_RCW_SRC_SD 0x040 -#endif diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c deleted file mode 100644 index 4170666c420..00000000000 --- a/board/freescale/ls1046ardb/ddr.c +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include "ddr.h" -#ifdef CONFIG_FSL_DEEP_SLEEP -#include -#endif -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 1) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - if (popts->registered_dimm_en) - pbsp = rdimms[0]; - else - pbsp = udimms[0]; - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for %lu MT/s\n", - ddr_freq); - printf("Trying to use the highest speed (%u) parameters\n", - pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); - - popts->data_bus_width = 0; /* 64-bit data bus */ - popts->bstopre = 0; /* enable auto precharge */ - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | - DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; - - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x61; -} - -#ifdef CONFIG_TFABOOT -int fsl_initdram(void) -{ - gd->ram_size = tfa_get_dram_size(); - - if (!gd->ram_size) - gd->ram_size = fsl_ddr_sdram_size(); - - return 0; -} -#else -int fsl_initdram(void) -{ - phys_size_t dram_size; - -#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) - gd->ram_size = fsl_ddr_sdram_size(); - - return 0; -#else - puts("Initializing DDR....using SPD\n"); - - dram_size = fsl_ddr_sdram(); -#endif - - erratum_a008850_post(); - - gd->ram_size = dram_size; - - return 0; -} -#endif diff --git a/board/freescale/ls1046ardb/ddr.h b/board/freescale/ls1046ardb/ddr.h deleted file mode 100644 index 05baef232ab..00000000000 --- a/board/freescale/ls1046ardb/ddr.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ - -void erratum_a008850_post(void); - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, - {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2300, 0, 8, 7, 0x08090A0E, 0x1011120C,}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 1666, 0, 0x8, 0x0D, 0x0C0B0A08, 0x0A0B0C08,}, - {2, 1900, 0, 0x8, 0x0E, 0x0D0C0B09, 0x0B0C0D09,}, - {2, 2300, 0, 0xa, 0x12, 0x100F0D0C, 0x0E0F100C,}, - {1, 1666, 0, 0x8, 0x0D, 0x0C0B0A08, 0x0A0B0C08,}, - {1, 1900, 0, 0x8, 0x0E, 0x0D0C0B09, 0x0B0C0D09,}, - {1, 2300, 0, 0xa, 0x12, 0x100F0D0C, 0x0E0F100C,}, - {} -}; - -static const struct board_specific_parameters *rdimms[] = { - rdimm0, -}; - -#endif diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c deleted file mode 100644 index fee8e0e21d4..00000000000 --- a/board/freescale/ls1046ardb/eth.c +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - int i; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - u32 srds_s1; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - /* Set the two on-board SGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR); - - /* Set the on-board AQ PHY address */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - - switch (srds_s1) { - case 0x1133: - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n", - srds_s1); - break; - } - - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) - fm_info_set_mdio(i, dev); - - /* 10GBase-R on lane A, MAC 9 */ - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(FM1_10GEC1, dev); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} - -#ifdef CONFIG_FMAN_ENET -int fdt_update_ethernet_dt(void *blob) -{ - u32 srds_s1; - int i, prop; - int offset, nodeoff; - const char *path; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - /* Cycle through all aliases */ - for (prop = 0; ; prop++) { - const char *name; - - /* FDT might have been edited, recompute the offset */ - offset = fdt_first_property_offset(blob, - fdt_path_offset(blob, - "/aliases") - ); - /* Select property number 'prop' */ - for (i = 0; i < prop; i++) - offset = fdt_next_property_offset(blob, offset); - - if (offset < 0) - break; - - path = fdt_getprop_by_offset(blob, offset, &name, NULL); - nodeoff = fdt_path_offset(blob, path); - - switch (srds_s1) { - case 0x1133: - if (!strcmp(name, "ethernet0")) - fdt_status_disabled(blob, nodeoff); - - if (!strcmp(name, "ethernet1")) - fdt_status_disabled(blob, nodeoff); - break; - default: - printf("%s: Invalid SerDes prtcl 0x%x for LS1046ARDB\n", - __func__, srds_s1); - break; - } - } - - return 0; -} -#endif diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c deleted file mode 100644 index 83b280f7646..00000000000 --- a/board/freescale/ls1046ardb/ls1046ardb.c +++ /dev/null @@ -1,192 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2021 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "cpld.h" - -DECLARE_GLOBAL_DATA_PTR; - -struct serial_device *default_serial_console(void) -{ -#if IS_ENABLED(CONFIG_SEMIHOSTING_SERIAL) - if (semihosting_enabled()) - return &serial_smh_device; -#endif - return &eserial1_device; -} - -int board_early_init_f(void) -{ - fsl_lsch2_early_init_f(); - - return 0; -} - -#ifndef CONFIG_XPL_BUILD -int checkboard(void) -{ - static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; - u8 cfg_rcw_src1, cfg_rcw_src2; - u16 cfg_rcw_src; - u8 sd1refclk_sel; - - puts("Board: LS1046ARDB, boot from "); - - cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); - cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); - cpld_rev_bit(&cfg_rcw_src1); - cfg_rcw_src = cfg_rcw_src1; - cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; - - if (cfg_rcw_src == 0x44) - printf("QSPI vBank %d\n", CPLD_READ(vbank)); - else if (cfg_rcw_src == 0x40) - puts("SD\n"); - else - puts("Invalid setting of SW5\n"); - - printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), - CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); - - puts("SERDES Reference Clocks:\n"); - sd1refclk_sel = CPLD_READ(sd1refclk_sel); - printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); - - return 0; -} - -int board_init(void) -{ - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; - -#ifdef CONFIG_NXP_ESBC - /* - * In case of Secure Boot, the IBR configures the SMMU - * to allow only Secure transactions. - * SMMU must be reset in bypass mode. - * Set the ClientPD bit and Clear the USFCFG Bit - */ - u32 val; - val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); - out_le32(SMMU_SCR0, val); - val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); - out_le32(SMMU_NSCR0, val); -#endif - -#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) - pci_init(); -#endif - - /* invert AQR105 IRQ pins polarity */ - out_be32(&scfg->intpcr, AQR105_IRQ_MASK); - - return 0; -} - -int board_setup_core_volt(u32 vdd) -{ - bool en_0v9; - - en_0v9 = (vdd == 900) ? true : false; - cpld_select_core_volt(en_0v9); - - return 0; -} - -int get_serdes_volt(void) -{ - return mc34vr500_get_sw_volt(SW4); -} - -int set_serdes_volt(int svdd) -{ - return mc34vr500_set_sw_volt(SW4, svdd); -} - -int power_init_board(void) -{ - int ret; - - ret = power_mc34vr500_init(0); - if (ret) - return ret; - - setup_chip_volt(); - - return 0; -} - -void config_board_mux(void) -{ -#ifdef CONFIG_HAS_FSL_XHCI_USB - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; - u32 usb_pwrfault; - - /* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */ - out_be32(&scfg->rcwpmuxcr0, 0x3300); - out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); - usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << - SCFG_USBPWRFAULT_USB3_SHIFT) | - (SCFG_USBPWRFAULT_DEDICATED << - SCFG_USBPWRFAULT_USB2_SHIFT) | - (SCFG_USBPWRFAULT_SHARED << - SCFG_USBPWRFAULT_USB1_SHIFT); - out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); -#endif -} - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ - config_board_mux(); - return 0; -} -#endif - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; - - /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; - - fdt_fixup_memory_banks(blob, base, size, 2); - ft_cpu_setup(blob, bd); - -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif -#endif - - fdt_fixup_icid(blob); - - return 0; -} -#endif diff --git a/board/freescale/ls1046ardb/ls1046ardb_pbi.cfg b/board/freescale/ls1046ardb/ls1046ardb_pbi.cfg deleted file mode 100644 index 5478217524d..00000000000 --- a/board/freescale/ls1046ardb/ls1046ardb_pbi.cfg +++ /dev/null @@ -1,22 +0,0 @@ -#Configure Scratch register -09570600 00000000 -09570604 10000000 -#Disable CCI barrier tranaction -09570178 0000e010 -09180000 00000008 -#USB PHY frequency sel -09570418 0000009e -0957041c 0000009e -09570420 0000009e -#Serdes SATA -09eb1300 80104e20 -09eb08dc 00502880 -#PEX gen3 link -09570158 00000300 -89400890 01048000 -89500890 01048000 -89600890 01048000 -#Alt base register -09570158 00001000 -#flush PBI data -096100c0 000fffff diff --git a/board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg b/board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg deleted file mode 100644 index 735d46c9f9b..00000000000 --- a/board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg +++ /dev/null @@ -1,26 +0,0 @@ -#QSPI clk -0957015c 40100000 -#Configure Scratch register -09570600 00000000 -09570604 10000000 -#Disable CCI barrier tranaction -09570178 0000e010 -09180000 00000008 -#USB PHY frequency sel -09570418 0000009e -0957041c 0000009e -09570420 0000009e -#Serdes SATA -09eb1300 80104e20 -09eb08dc 00502880 -#PEX gen3 link -09570158 00000300 -89400890 01048000 -89500890 01048000 -89600890 01048000 -#Alt base register -09570158 00001000 -#flush PBI data -096100c0 000fffff -#Change endianness -09550000 000f400c diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg b/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg deleted file mode 100644 index ccedf87e849..00000000000 --- a/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 -# RCW -0c150012 0e000000 00000000 00000000 -11335559 40000012 60040000 c1000000 -00000000 00000000 00000000 00238800 -20124000 00003000 00000096 00000001 diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg b/board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg deleted file mode 100644 index 7b9be0ad3f8..00000000000 --- a/board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 -# RCW -0c150010 0e000000 00000000 00000000 -11335559 40005012 40025000 c1000000 -00000000 00000000 00000000 00238800 -20124000 00003101 00000096 00000001 diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg b/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg deleted file mode 100644 index d3b152282f2..00000000000 --- a/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 -# RCW -0c150012 0e000000 00000000 00000000 -11335559 40005012 60040000 c1000000 -00000000 00000000 00000000 00238800 -20124000 00003101 00000096 00000001 diff --git a/board/freescale/ls1088a/Kconfig b/board/freescale/ls1088a/Kconfig deleted file mode 100644 index 1ada661743e..00000000000 --- a/board/freescale/ls1088a/Kconfig +++ /dev/null @@ -1,31 +0,0 @@ -if TARGET_LS1088AQDS - -config SYS_BOARD - default "ls1088a" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls1088aqds" - -endif - -if TARGET_LS1088ARDB - -config SYS_BOARD - default "ls1088a" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls1088ardb" - -endif diff --git a/board/freescale/ls1088a/MAINTAINERS b/board/freescale/ls1088a/MAINTAINERS deleted file mode 100644 index 95a14149e4f..00000000000 --- a/board/freescale/ls1088a/MAINTAINERS +++ /dev/null @@ -1,35 +0,0 @@ -LS1088ARDB BOARD -M: Ashish Kumar -S: Maintained -F: board/freescale/ls1088a/ -F: include/configs/ls1088ardb.h -F: configs/ls1088ardb_qspi_defconfig -F: configs/ls1088ardb_sdcard_qspi_defconfig -F: configs/ls1088ardb_tfa_defconfig -F: configs/ls1088ardb_tfa_SECURE_BOOT_defconfig - -LS1088AQDS BOARD -M: Ashish Kumar -S: Maintained -F: board/freescale/ls1088a/ -F: include/configs/ls1088aqds.h -F: configs/ls1088aqds_qspi_defconfig -F: configs/ls1088aqds_sdcard_qspi_defconfig -F: configs/ls1088aqds_defconfig -F: configs/ls1088aqds_sdcard_ifc_defconfig -F: configs/ls1088aqds_tfa_defconfig - -LS1088AQDS_QSPI_SECURE_BOOT BOARD -M: Udit Agarwal -S: Maintained -F: configs/ls1088aqds_qspi_SECURE_BOOT_defconfig - -LS1088ARDB_QSPI_SECURE_BOOT BOARD -M: Udit Agarwal -S: Maintained -F: configs/ls1088ardb_qspi_SECURE_BOOT_defconfig - -LS1088ARDB_SD_SECURE_BOOT BOARD -M: Udit Agarwal -S: Maintained -F: configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1088a/Makefile b/board/freescale/ls1088a/Makefile deleted file mode 100644 index e54d6cad9e1..00000000000 --- a/board/freescale/ls1088a/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2017 NXP - -obj-y += ls1088a.o -obj-y += ddr.o -ifndef CONFIG_XPL_BUILD -obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o -obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o -endif diff --git a/board/freescale/ls1088a/README b/board/freescale/ls1088a/README deleted file mode 100644 index 5315909defc..00000000000 --- a/board/freescale/ls1088a/README +++ /dev/null @@ -1,145 +0,0 @@ -Overview --------- -The LS1088A Reference Design (RDB) is a high-performance computing, -evaluation, and development platform that supports ARM SoC LS1088A and its -derivatives. - - -LS1088A SoC Overview --------------------------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc - -RDB Default Switch Settings (1: ON; 0: OFF) -------------------------------------------- - -For QSPI Boot -SW1 0011 0001 -SW2 x100 0000 -SW3 1111 0010 -SW4 1001 0011 -SW5 1111 0000 - -For SD Boot -SW1 0010 0000 -SW2 0100 0000 -SW3 1111 0010 -SW4 1001 0011 -SW5 1111 0000 - -For eMMC Boot -SW1 0010 0000 -SW2 1100 0000 -SW3 1111 0010 -SW4 1001 0011 -SW5 1111 0000 - -Alternately you can use this command to switch from QSPI to SD - -=> i2c mw 66 0x60 0x20; i2c mw 66 10 10;i2c mw 66 10 21 - - LS1088ARDB board Overview - ------------------------- - - SERDES Connections, 16 lanes supporting: - - PCI Express - 3.0 - - SATA 3.0 - - 10GBase-R - - QSGMII - - DDR Controller - - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four - chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default - with FSL refernce software is 2100MT/s - - 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB - - IFC/Local Bus - - One 2 GB NAND flash with ECC support, not as boot source - - CPLD of size 2K - - USB 3.0 - - Two high speed USB 3.0 ports - - First USB 3.0 port configured as Host with Type-A connector - - Second USB 3.0 port configured as OTG with micro-AB connector - - SDHC/eMMC - - SDHC slot and onboard eMMC are muxed together - - 4 I2C controllers - - Two SATA onboard connectors - - 2 UART - - JTAG support - - QSPI emulator support - - TDM riser support - -QDS Default Switch Settings (1: ON; 0: OFF) -------------------------------------------- - -For 16b IFC-NOR -SW1 0001 0010 -SW2 x110 1111 - -For QSPI Boot -SW1 0011 0001 -SW2 0110 1111 - -For SD Boot -SW1 0010 0000 -SW2 0110 1111 - -For eMMC Boot -SW1 0010 0000 -SW2 1110 1111 - -For I2C (ext. addr.) -SW1 0010 0100 -SW2 1110 1111 - -SW3 to SW12 are identical for all boot source - -SW3 0010 0100 -SW4 0010 0000 -SW5 1110 0111 -SW6 1110 1000 -SW7 0001 1101 -SW8 0000 1101 -SW9 1100 1010 -SW10 1110 1000 -SW11 1111 0100 -SW12 1111 1111 - - LS1088AQDS board Overview - ------------------------- - - SERDES Connections, 16 lanes supporting: - - PCI Express - 3.0 - - SATA 3.0 - - 2 10GBase-R - - QSGMII, SGMII with help for Riser card - - 2 RGMII - - 5 slot for Riser card or PCIe NIC - - DDR Controller - - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four - chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default - with FSL refernce software is 2100MT/s - - 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB - - IFC/Local Bus - - One 2 GB NAND flash with ECC support, not as boot source - - CPLD of size 2K - - USB 3.0 - - Two high speed USB 3.0 ports - - First USB 3.0 port configured as Host with Type-A connector - - Second USB 3.0 port configured as OTG with micro-AB connector - - SDHC/eMMC - - SDHC/eMMC slot via adaptor - - 4 I2C controllers - - Two SATA onboard connectors - - 2 UART - - JTAG support - - DSPI - - PROMJET support - - QSPI emulator support - - TDM riser support - -QSPI flash memory map valid for both QDS and RDB - Image Flash Offset - RCW+PBI 0x00000000 - Boot firmware (U-Boot) 0x00100000 - Boot firmware Environment 0x00300000 - PPA firmware 0x00400000 - DPAA2 MC 0x00A00000 - DPAA2 DPL 0x00D00000 - DPAA2 DPC 0x00E00000 - Kernel.itb 0x01000000 diff --git a/board/freescale/ls1088a/ddr.c b/board/freescale/ls1088a/ddr.c deleted file mode 100644 index cd590af9534..00000000000 --- a/board/freescale/ls1088a/ddr.c +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2017 NXP - */ - -#include -#include -#include -#include -#include -#include -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)) -static void fsl_ddr_setup_0v9_volt(memctl_options_t *popts) -{ - int vdd; - - vdd = get_core_volt_from_fuse(); - /* Nothing to do for silicons doesn't support VID */ - if (vdd < 0) - return; - - if (vdd == 900) { - popts->ddr_cdr1 |= DDR_CDR1_V0PT9_EN; - debug("VID: configure DDR to support 900 mV\n"); - } -} -#endif - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 1) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - /* - * we use identical timing for all slots. If needed, change the code - * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; - */ - pbsp = udimms[0]; - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for %lu MT/s\n", - ddr_freq); - printf("Trying to use the highest speed (%u) parameters\n", - pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" - "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, - pbsp->wrlvl_ctl_3); - - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* Enable DDR hashing */ - popts->addr_hash = 1; - - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); -#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)) - fsl_ddr_setup_0v9_volt(popts); -#endif - - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | - DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; -} - -#ifdef CONFIG_TFABOOT -int fsl_initdram(void) -{ - gd->ram_size = tfa_get_dram_size(); - - if (!gd->ram_size) - gd->ram_size = fsl_ddr_sdram_size(); - - return 0; -} -#else -int fsl_initdram(void) -{ - puts("Initializing DDR....using SPD\n"); - -#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) - gd->ram_size = fsl_ddr_sdram_size(); -#else - gd->ram_size = fsl_ddr_sdram(); -#endif - return 0; -} -#endif /* CONFIG_TFABOOT */ diff --git a/board/freescale/ls1088a/ddr.h b/board/freescale/ls1088a/ddr.h deleted file mode 100644 index b35c4ae2dad..00000000000 --- a/board/freescale/ls1088a/ddr.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017 NXP - */ - -#ifndef __LS1088A_DDR_H__ -#define __LS1088A_DDR_H__ -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ - -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ -#if defined(CONFIG_TARGET_LS1088ARDB) - - {2, 1666, 0, 8, 8, 0x090A0B0E, 0x0F10110D,}, - {2, 1900, 0, 8, 9, 0x0A0B0C10, 0x1112140E,}, - {2, 2300, 0, 8, 9, 0x0A0C0E11, 0x1214160F,}, - {} -#elif defined(CONFIG_TARGET_LS1088AQDS) - {2, 1666, 0, 8, 8, 0x0A0A0C0E, 0x0F10110C,}, - {2, 1900, 0, 8, 9, 0x0A0B0C10, 0x1112140E,}, - {2, 2300, 0, 4, 9, 0x0A0C0D11, 0x1214150E,}, - {} - -#endif -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; -#endif diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c deleted file mode 100644 index e6033d251c5..00000000000 --- a/board/freescale/ls1088a/eth_ls1088aqds.c +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2017 NXP - */ - -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_RESET_PHY_R) -void reset_phy(void) -{ - mc_env_boot(); -} -#endif /* CONFIG_RESET_PHY_R */ - -#if defined(CONFIG_MULTI_DTB_FIT) - -/* Structure to hold SERDES protocols supported (network interfaces are - * described in the DTS). - * - * @serdes_block: the index of the SERDES block - * @serdes_protocol: the decimal value of the protocol supported - * @dts_needed: DTS notes describing the current configuration are needed - * - * When dts_needed is true, the board_fit_config_name_match() function - * will try to exactly match the current configuration of the block with a DTS - * name provided. - */ -static struct serdes_configuration { - u8 serdes_block; - u32 serdes_protocol; - bool dts_needed; -} supported_protocols[] = { - /* Serdes block #1 */ - {1, 21, true}, - {1, 29, true}, -}; - -#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) - -static bool protocol_supported(u8 serdes_block, u32 protocol) -{ - struct serdes_configuration serdes_conf; - int i; - - for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { - serdes_conf = supported_protocols[i]; - if (serdes_conf.serdes_block == serdes_block && - serdes_conf.serdes_protocol == protocol) - return true; - } - - return false; -} - -static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) -{ - struct serdes_configuration serdes_conf; - int i; - - for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { - serdes_conf = supported_protocols[i]; - if (serdes_conf.serdes_block == serdes_block && - serdes_conf.serdes_protocol == protocol) { - if (serdes_conf.dts_needed == true) - sprintf(str, "%u", protocol); - else - sprintf(str, "x"); - return; - } - } -} - -int board_fit_config_name_match(const char *name) -{ - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - char expected_dts[100]; - char srds_s1_str[2]; - u32 srds_s1, cfg; - - cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & - FSL_CHASSIS3_SRDS1_PRTCL_MASK; - cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; - srds_s1 = serdes_get_number(FSL_SRDS_1, cfg); - - /* Check for supported protocols. The default DTS will be used - * in this case - */ - if (!protocol_supported(1, srds_s1)) - return -1; - - get_str_protocol(1, srds_s1, srds_s1_str); - - sprintf(expected_dts, "fsl-ls1088a-qds-%s-x", srds_s1_str); - - if (!strcmp(name, expected_dts)) - return 0; - - return -1; -} -#endif diff --git a/board/freescale/ls1088a/eth_ls1088ardb.c b/board/freescale/ls1088a/eth_ls1088ardb.c deleted file mode 100644 index fb6f9c1a813..00000000000 --- a/board/freescale/ls1088a/eth_ls1088ardb.c +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2017 NXP - */ - -#include - -#if defined(CONFIG_RESET_PHY_R) -void reset_phy(void) -{ - mc_env_boot(); -} -#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c deleted file mode 100644 index 51ec055be63..00000000000 --- a/board/freescale/ls1088a/ls1088a.c +++ /dev/null @@ -1,1041 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2017-2022 NXP - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/i2c_mux.h" - -#include "../common/qixis.h" -#include "ls1088a_qixis.h" -#include "../common/vid.h" -#include - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_TARGET_LS1088AQDS -#ifdef CONFIG_TFABOOT -struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { - { - "nor0", - CFG_SYS_NOR0_CSPR_EARLY, - CFG_SYS_NOR0_CSPR_EXT, - CFG_SYS_NOR_AMASK, - CFG_SYS_NOR_CSOR, - { - CFG_SYS_NOR_FTIM0, - CFG_SYS_NOR_FTIM1, - CFG_SYS_NOR_FTIM2, - CFG_SYS_NOR_FTIM3 - }, - 0, - CFG_SYS_NOR0_CSPR, - 0, - }, - { - "nor1", - CFG_SYS_NOR1_CSPR_EARLY, - CFG_SYS_NOR0_CSPR_EXT, - CFG_SYS_NOR_AMASK_EARLY, - CFG_SYS_NOR_CSOR, - { - CFG_SYS_NOR_FTIM0, - CFG_SYS_NOR_FTIM1, - CFG_SYS_NOR_FTIM2, - CFG_SYS_NOR_FTIM3 - }, - 0, - CFG_SYS_NOR1_CSPR, - CFG_SYS_NOR_AMASK, - }, - { - "nand", - CFG_SYS_NAND_CSPR, - CFG_SYS_NAND_CSPR_EXT, - CFG_SYS_NAND_AMASK, - CFG_SYS_NAND_CSOR, - { - CFG_SYS_NAND_FTIM0, - CFG_SYS_NAND_FTIM1, - CFG_SYS_NAND_FTIM2, - CFG_SYS_NAND_FTIM3 - }, - }, - { - "fpga", - CFG_SYS_FPGA_CSPR, - CFG_SYS_FPGA_CSPR_EXT, - SYS_FPGA_AMASK, - CFG_SYS_FPGA_CSOR, - { - SYS_FPGA_CS_FTIM0, - SYS_FPGA_CS_FTIM1, - SYS_FPGA_CS_FTIM2, - SYS_FPGA_CS_FTIM3 - }, - 0, - SYS_FPGA_CSPR_FINAL, - 0, - } -}; - -struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { - { - "nand", - CFG_SYS_NAND_CSPR, - CFG_SYS_NAND_CSPR_EXT, - CFG_SYS_NAND_AMASK, - CFG_SYS_NAND_CSOR, - { - CFG_SYS_NAND_FTIM0, - CFG_SYS_NAND_FTIM1, - CFG_SYS_NAND_FTIM2, - CFG_SYS_NAND_FTIM3 - }, - }, - { - "reserved", - }, - { - "fpga", - CFG_SYS_FPGA_CSPR, - CFG_SYS_FPGA_CSPR_EXT, - SYS_FPGA_AMASK, - CFG_SYS_FPGA_CSOR, - { - SYS_FPGA_CS_FTIM0, - SYS_FPGA_CS_FTIM1, - SYS_FPGA_CS_FTIM2, - SYS_FPGA_CS_FTIM3 - }, - 0, - SYS_FPGA_CSPR_FINAL, - 0, - } -}; - -void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) -{ - enum boot_src src = get_boot_src(); - - if (src == BOOT_SOURCE_QSPI_NOR) - regs_info->regs = ifc_cfg_qspi_nor_boot; - else - regs_info->regs = ifc_cfg_ifc_nor_boot; - - regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; -} -#endif /* CONFIG_TFABOOT */ -#endif /* CONFIG_TARGET_LS1088AQDS */ - -int board_early_init_f(void) -{ -#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS) - i2c_early_init_f(); -#endif - fsl_lsch3_early_init_f(); - return 0; -} - -#ifdef CONFIG_FSL_QIXIS -unsigned long long get_qixis_addr(void) -{ - unsigned long long addr; - - if (gd->flags & GD_FLG_RELOC) - addr = QIXIS_BASE_PHYS; - else - addr = QIXIS_BASE_PHYS_EARLY; - - /* - * IFC address under 256MB is mapped to 0x30000000, any address above - * is mapped to 0x5_10000000 up to 4GB. - */ - addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; - - return addr; -} -#endif - -#if defined(CONFIG_VID) -static int setup_core_voltage(void) -{ - if (adjust_vdd(0) < 0) - printf("core voltage not adjusted\n"); - - return 0; -} -EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, setup_core_voltage); - -u16 soc_get_fuse_vid(int vid_index) -{ - static const u16 vdd[32] = { - 10250, - 9875, - 9750, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 9000, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 10000, /* 1.0000V */ - 10125, - 10250, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - }; - - return vdd[vid_index]; -}; -#endif - -int is_pb_board(void) -{ - u8 board_id; - - board_id = QIXIS_READ(id); - if (board_id == LS1088ARDB_PB_BOARD) - return 1; - else - return 0; -} - -int fixup_ls1088ardb_pb_banner(void *fdt) -{ - fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board"); - - return 0; -} - -#if !defined(CONFIG_XPL_BUILD) -int checkboard(void) -{ -#ifdef CONFIG_TFABOOT - enum boot_src src = get_boot_src(); -#endif - char buf[64]; - u8 sw; - static const char *const freq[] = {"100", "125", "156.25", - "100 separate SSCG"}; - int clock; - -#ifdef CONFIG_TARGET_LS1088AQDS - printf("Board: LS1088A-QDS, "); -#else - if (is_pb_board()) - printf("Board: LS1088ARDB-PB, "); - else - printf("Board: LS1088A-RDB, "); -#endif - - sw = QIXIS_READ(arch); - printf("Board Arch: V%d, ", sw >> 4); - -#ifdef CONFIG_TARGET_LS1088AQDS - printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); -#else - printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); -#endif - - memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); - - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - -#ifdef CONFIG_TFABOOT - if (src == BOOT_SOURCE_SD_MMC) - puts("SD card\n"); -#else -#ifdef CONFIG_SD_BOOT - puts("SD card\n"); -#endif -#endif /* CONFIG_TFABOOT */ - switch (sw) { -#ifdef CONFIG_TARGET_LS1088AQDS - case 0: - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: - printf("vBank: %d\n", sw); - break; - case 8: - puts("PromJet\n"); - break; - case 15: - puts("IFCCard\n"); - break; - case 14: -#else - case 0: -#endif - puts("QSPI:"); - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT; - if (sw == 0 || sw == 4) - puts("0\n"); - else if (sw == 1) - puts("1\n"); - else - puts("EMU\n"); - break; - - default: - printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); - break; - } - -#ifdef CONFIG_TARGET_LS1088AQDS - printf("FPGA: v%d (%s), build %d", - (int)QIXIS_READ(scver), qixis_read_tag(buf), - (int)qixis_read_minor()); - /* the timestamp string contains "\n" at the end */ - printf(" on %s", qixis_read_time(buf)); -#else - printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); -#endif - - /* - * Display the actual SERDES reference clocks as configured by the - * dip switches on the board. Note that the SWx registers could - * technically be set to force the reference clocks to match the - * values that the SERDES expects (or vice versa). For now, however, - * we just display both values and hope the user notices when they - * don't match. - */ - puts("SERDES1 Reference : "); - sw = QIXIS_READ(brdcfg[2]); - clock = (sw >> 6) & 3; - printf("Clock1 = %sMHz ", freq[clock]); - clock = (sw >> 4) & 3; - printf("Clock2 = %sMHz", freq[clock]); - - puts("\nSERDES2 Reference : "); - clock = (sw >> 2) & 3; - printf("Clock1 = %sMHz ", freq[clock]); - clock = (sw >> 0) & 3; - printf("Clock2 = %sMHz\n", freq[clock]); - - return 0; -} -#endif - -bool if_board_diff_clk(void) -{ -#ifdef CONFIG_TARGET_LS1088AQDS - u8 diff_conf = QIXIS_READ(brdcfg[11]); - return diff_conf & 0x40; -#else - u8 diff_conf = QIXIS_READ(dutcfg[11]); - return diff_conf & 0x80; -#endif -} - -#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); - - switch (sysclk_conf & 0x0f) { - case QIXIS_SYSCLK_83: - return 83333333; - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - case QIXIS_SYSCLK_150: - return 150000000; - case QIXIS_SYSCLK_160: - return 160000000; - case QIXIS_SYSCLK_166: - return 166666666; - } - - return 66666666; -} -#endif - -#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ -unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); - - if (if_board_diff_clk()) - return get_board_sys_clk(); - switch ((ddrclk_conf & 0x30) >> 4) { - case QIXIS_DDRCLK_100: - return 100000000; - case QIXIS_DDRCLK_125: - return 125000000; - case QIXIS_DDRCLK_133: - return 133333333; - } - - return 66666666; -} -#endif - -#if !defined(CONFIG_XPL_BUILD) -void board_retimer_init(void) -{ - u8 reg; - - /* Retimer is connected to I2C1_CH5 */ - select_i2c_ch_pca9547(I2C_MUX_CH5, 0); - - /* Access to Control/Shared register */ - reg = 0x0; -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); -#else - struct udevice *dev; - - i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev); - dm_i2c_write(dev, 0xff, ®, 1); -#endif - - /* Read device revision and ID */ -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); -#else - dm_i2c_read(dev, 1, ®, 1); -#endif - debug("Retimer version id = 0x%x\n", reg); - - /* Enable Broadcast. All writes target all channel register sets */ - reg = 0x0c; -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); -#else - dm_i2c_write(dev, 0xff, ®, 1); -#endif - - /* Reset Channel Registers */ -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); -#else - dm_i2c_read(dev, 0, ®, 1); -#endif - reg |= 0x4; -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); -#else - dm_i2c_write(dev, 0, ®, 1); -#endif - - /* Set data rate as 10.3125 Gbps */ - reg = 0x90; -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); -#else - dm_i2c_write(dev, 0x60, ®, 1); -#endif - reg = 0xb3; -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); -#else - dm_i2c_write(dev, 0x61, ®, 1); -#endif - reg = 0x90; -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); -#else - dm_i2c_write(dev, 0x62, ®, 1); -#endif - reg = 0xb3; -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); -#else - dm_i2c_write(dev, 0x63, ®, 1); -#endif - reg = 0xcd; -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); -#else - dm_i2c_write(dev, 0x64, ®, 1); -#endif - - /* Select VCO Divider to full rate (000) */ -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); -#else - dm_i2c_read(dev, 0x2F, ®, 1); -#endif - reg &= 0x0f; - reg |= 0x70; -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); -#else - dm_i2c_write(dev, 0x2F, ®, 1); -#endif - -#ifdef CONFIG_TARGET_LS1088AQDS - /* Retimer is connected to I2C1_CH5 */ - select_i2c_ch_pca9547(I2C_MUX_CH5, 0); - - /* Access to Control/Shared register */ - reg = 0x0; -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); -#else - i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev); - dm_i2c_write(dev, 0xff, ®, 1); -#endif - - /* Read device revision and ID */ -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1); -#else - dm_i2c_read(dev, 1, ®, 1); -#endif - debug("Retimer version id = 0x%x\n", reg); - - /* Enable Broadcast. All writes target all channel register sets */ - reg = 0x0c; -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); -#else - dm_i2c_write(dev, 0xff, ®, 1); -#endif - - /* Reset Channel Registers */ -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1); -#else - dm_i2c_read(dev, 0, ®, 1); -#endif - reg |= 0x4; -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1); -#else - dm_i2c_write(dev, 0, ®, 1); -#endif - - /* Set data rate as 10.3125 Gbps */ - reg = 0x90; -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1); -#else - dm_i2c_write(dev, 0x60, ®, 1); -#endif - reg = 0xb3; -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1); -#else - dm_i2c_write(dev, 0x61, ®, 1); -#endif - reg = 0x90; -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1); -#else - dm_i2c_write(dev, 0x62, ®, 1); -#endif - reg = 0xb3; -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1); -#else - dm_i2c_write(dev, 0x63, ®, 1); -#endif - reg = 0xcd; -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1); -#else - dm_i2c_write(dev, 0x64, ®, 1); -#endif - - /* Select VCO Divider to full rate (000) */ -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); -#else - dm_i2c_read(dev, 0x2F, ®, 1); -#endif - reg &= 0x0f; - reg |= 0x70; -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); -#else - dm_i2c_write(dev, 0x2F, ®, 1); -#endif - -#endif - /*return the default channel*/ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); -} - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ -#ifdef CONFIG_TARGET_LS1088ARDB - u8 brdcfg5; - - if (hwconfig("esdhc-force-sd")) { - brdcfg5 = QIXIS_READ(brdcfg[5]); - brdcfg5 &= ~BRDCFG5_SPISDHC_MASK; - brdcfg5 |= BRDCFG5_FORCE_SD; - QIXIS_WRITE(brdcfg[5], brdcfg5); - } -#endif - -#ifdef CONFIG_TARGET_LS1088AQDS - u8 brdcfg4, brdcfg5; - - if (hwconfig("dspi-on-board")) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_USBOSC_MASK; - brdcfg4 |= BRDCFG4_SPI; - QIXIS_WRITE(brdcfg[4], brdcfg4); - - brdcfg5 = QIXIS_READ(brdcfg[5]); - brdcfg5 &= ~BRDCFG5_SPR_MASK; - brdcfg5 |= BRDCFG5_SPI_ON_BOARD; - QIXIS_WRITE(brdcfg[5], brdcfg5); - } else if (hwconfig("dspi-off-board")) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_USBOSC_MASK; - brdcfg4 |= BRDCFG4_SPI; - QIXIS_WRITE(brdcfg[4], brdcfg4); - - brdcfg5 = QIXIS_READ(brdcfg[5]); - brdcfg5 &= ~BRDCFG5_SPR_MASK; - brdcfg5 |= BRDCFG5_SPI_OFF_BOARD; - QIXIS_WRITE(brdcfg[5], brdcfg5); - } -#endif - return 0; -} -#endif -#endif - -int i2c_multiplexer_select_vid_channel(u8 channel) -{ - return select_i2c_ch_pca9547(channel, 0); -} - -#ifdef CONFIG_TARGET_LS1088AQDS -/* read the current value(SVDD) of the LTM Regulator Voltage */ -int get_serdes_volt(void) -{ - int ret, vcode = 0; - u8 chan = PWM_CHANNEL0; - - /* Select the PAGE 0 using PMBus commands PAGE for VDD */ -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_write(I2C_SVDD_MONITOR_ADDR, - PMBUS_CMD_PAGE, 1, &chan, 1); -#else - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev); - if (!ret) - ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, - &chan, 1); -#endif - - if (ret) { - printf("VID: failed to select VDD Page 0\n"); - return ret; - } - - /* Read the output voltage using PMBus command READ_VOUT */ -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_read(I2C_SVDD_MONITOR_ADDR, - PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); -#else - dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2); -#endif - if (ret) { - printf("VID: failed to read the voltage\n"); - return ret; - } - - return vcode; -} - -int set_serdes_volt(int svdd) -{ - int ret, vdd_last; - u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, - svdd & 0xFF, (svdd & 0xFF00) >> 8}; - - /* Write the desired voltage code to the SVDD regulator */ -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_write(I2C_SVDD_MONITOR_ADDR, - PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); -#else - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev); - if (!ret) - ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE, - (void *)&buff, 5); -#endif - if (ret) { - printf("VID: I2C failed to write to the voltage regulator\n"); - return -1; - } - - /* Wait for the voltage to get to the desired value */ - do { - vdd_last = get_serdes_volt(); - if (vdd_last < 0) { - printf("VID: Couldn't read sensor abort VID adjust\n"); - return -1; - } - } while (vdd_last != svdd); - - return 1; -} -#else -int get_serdes_volt(void) -{ - return 0; -} - -int set_serdes_volt(int svdd) -{ - int ret; - u8 brdcfg4; - - printf("SVDD changing of RDB\n"); - - /* Read the BRDCFG54 via CLPD */ -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_read(CFG_SYS_I2C_FPGA_ADDR, - QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); -#else - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev); - if (!ret) - ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET, - (void *)&brdcfg4, 1); -#endif - - if (ret) { - printf("VID: I2C failed to read the CPLD BRDCFG4\n"); - return -1; - } - - brdcfg4 = brdcfg4 | 0x08; - - /* Write to the BRDCFG4 */ -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_write(CFG_SYS_I2C_FPGA_ADDR, - QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); -#else - ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET, - (void *)&brdcfg4, 1); -#endif - - if (ret) { - debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n"); - return -1; - } - - /* Wait for the voltage to get to the desired value */ - udelay(10000); - - return 1; -} -#endif - -/* this function disables the SERDES, changes the SVDD Voltage and enables it*/ -int board_adjust_vdd(int vdd) -{ - int ret = 0; - - debug("%s: vdd = %d\n", __func__, vdd); - - /* Special settings to be performed when voltage is 900mV */ - if (vdd == 900) { - ret = setup_serdes_volt(vdd); - if (ret < 0) { - ret = -1; - goto exit; - } - } -exit: - return ret; -} - -#if !defined(CONFIG_XPL_BUILD) -int board_init(void) -{ - init_final_memctl_regs(); -#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) - u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; -#endif - - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - board_retimer_init(); - -#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) - /* invert AQR105 IRQ pins polarity */ - out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK); -#endif - -#if !defined(CONFIG_SYS_EARLY_PCI_INIT) - pci_init(); -#endif - - return 0; -} - -void detail_board_ddr_info(void) -{ - puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); - print_ddr_info(0); -} - -#ifdef CONFIG_FSL_MC_ENET -void board_quiesce_devices(void) -{ - fsl_mc_ldpaa_exit(gd->bd); -} - -void fdt_fixup_board_enet(void *fdt) -{ - int offset; - - offset = fdt_path_offset(fdt, "/fsl-mc"); - - if (offset < 0) - offset = fdt_path_offset(fdt, "/soc/fsl-mc"); - - if (offset < 0) { - printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", - __func__, offset); - return; - } - - if (get_mc_boot_status() == 0 && - (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) - fdt_status_okay(fdt, offset); - else - fdt_status_fail(fdt, offset); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -void fsl_fdt_fixup_flash(void *fdt) -{ - int offset; -#ifdef CONFIG_TFABOOT - u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; - u32 val; -#endif - -/* - * IFC-NOR and QSPI are muxed on SoC. - * So disable IFC node in dts if QSPI is enabled or - * disable QSPI node in dts in case QSPI is not enabled. - */ - -#ifdef CONFIG_TFABOOT - enum boot_src src = get_boot_src(); - bool disable_ifc = false; - - switch (src) { - case BOOT_SOURCE_IFC_NOR: - disable_ifc = false; - break; - case BOOT_SOURCE_QSPI_NOR: - disable_ifc = true; - break; - default: - val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4); - if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3)) - disable_ifc = true; - break; - } - - if (disable_ifc) { - offset = fdt_path_offset(fdt, "/soc/memory-controller/nor"); - - if (offset < 0) - offset = fdt_path_offset(fdt, "/memory-controller/nor"); - } else { - offset = fdt_path_offset(fdt, "/soc/quadspi"); - - if (offset < 0) - offset = fdt_path_offset(fdt, "/quadspi"); - } - -#else -#ifdef CONFIG_FSL_QSPI - offset = fdt_path_offset(fdt, "/soc/memory-controller/nor"); - - if (offset < 0) - offset = fdt_path_offset(fdt, "/memory-controller/nor"); -#else - offset = fdt_path_offset(fdt, "/soc/quadspi"); - - if (offset < 0) - offset = fdt_path_offset(fdt, "/quadspi"); -#endif -#endif - if (offset < 0) - return; - - fdt_status_disabled(fdt, offset); -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - int i; - u16 mc_memory_bank = 0; - - u64 *base; - u64 *size; - u64 mc_memory_base = 0; - u64 mc_memory_size = 0; - u16 total_memory_banks; - - ft_cpu_setup(blob, bd); - - fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); - - if (mc_memory_base != 0) - mc_memory_bank++; - - total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; - - base = calloc(total_memory_banks, sizeof(u64)); - if (!base) - return -ENOMEM; - - size = calloc(total_memory_banks, sizeof(u64)); - if (!size) { - free(base); - return -ENOMEM; - } - - /* fixup DT for the two GPP DDR banks */ - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; - } - -#ifdef CONFIG_RESV_RAM - /* reduce size if reserved memory is within this bank */ - if (gd->arch.resv_ram >= base[0] && - gd->arch.resv_ram < base[0] + size[0]) - size[0] = gd->arch.resv_ram - base[0]; - else if (gd->arch.resv_ram >= base[1] && - gd->arch.resv_ram < base[1] + size[1]) - size[1] = gd->arch.resv_ram - base[1]; -#endif - - if (mc_memory_base != 0) { - for (i = 0; i <= total_memory_banks; i++) { - if (base[i] == 0 && size[i] == 0) { - base[i] = mc_memory_base; - size[i] = mc_memory_size; - break; - } - } - } - - fdt_fixup_memory_banks(blob, base, size, total_memory_banks); - - fdt_fsl_mc_fixup_iommu_map_entry(blob); - - fsl_fdt_fixup_flash(blob); - -#ifdef CONFIG_FSL_MC_ENET - fdt_fixup_board_enet(blob); - fdt_reserve_mc_mem(blob, 0x300); -#endif - - fdt_fixup_icid(blob); - - if (is_pb_board()) - fixup_ls1088ardb_pb_banner(blob); - - return 0; -} -#endif -#endif /* defined(CONFIG_XPL_BUILD) */ - -#ifdef CONFIG_TFABOOT -#ifdef CONFIG_MTD_NOR_FLASH -int is_flash_available(void) -{ - char *env_hwconfig = env_get("hwconfig"); - enum boot_src src = get_boot_src(); - int is_nor_flash_available = 1; - - switch (src) { - case BOOT_SOURCE_IFC_NOR: - is_nor_flash_available = 1; - break; - case BOOT_SOURCE_QSPI_NOR: - is_nor_flash_available = 0; - break; - /* - * In Case of SD boot,if qspi is defined in env_hwconfig - * disable nor flash probe. - */ - default: - if (hwconfig_f("qspi", env_hwconfig)) - is_nor_flash_available = 0; - break; - } - return is_nor_flash_available; -} -#endif - -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH -void *env_sf_get_env_addr(void) -{ - return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); -} -#endif -#endif diff --git a/board/freescale/ls1088a/ls1088a_qixis.h b/board/freescale/ls1088a/ls1088a_qixis.h deleted file mode 100644 index e3502eb1d19..00000000000 --- a/board/freescale/ls1088a/ls1088a_qixis.h +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017 NXP - */ - -#ifndef __LS1088AQDS_QIXIS_H__ -#define __LS1088AQDS_QIXIS_H__ - -/* Definitions of QIXIS Registers for LS1088AQDS */ - -/* SYSCLK */ -#define QIXIS_SYSCLK_66 0x0 -#define QIXIS_SYSCLK_83 0x1 -#define QIXIS_SYSCLK_100 0x2 -#define QIXIS_SYSCLK_125 0x3 -#define QIXIS_SYSCLK_133 0x4 -#define QIXIS_SYSCLK_150 0x5 -#define QIXIS_SYSCLK_160 0x6 -#define QIXIS_SYSCLK_166 0x7 - -/* DDRCLK */ -#define QIXIS_DDRCLK_66 0x0 -#define QIXIS_DDRCLK_100 0x1 -#define QIXIS_DDRCLK_125 0x2 -#define QIXIS_DDRCLK_133 0x3 - -/* BRDCFG2 - SD clock*/ -#define QIXIS_SDCLK1_100 0x0 -#define QIXIS_SDCLK1_125 0x1 -#define QIXIS_SDCLK1_165 0x2 -#define QIXIS_SDCLK1_100_SP 0x3 - -#define BRDCFG4_EMISEL_MASK 0xE0 -#define BRDCFG4_EMISEL_SHIFT 5 -#define BRDCFG9_SFPTX_MASK 0x10 -#define BRDCFG9_SFPTX_SHIFT 4 - -/* Definitions of QIXIS Registers for LS1088ARDB */ - -/* BRDCFG5 */ -#define BRDCFG5_SPISDHC_MASK 0x0C -#define BRDCFG5_FORCE_SD 0x08 - -/* Definitions of QIXIS Registers for LS1088AQDS */ - -/* BRDCFG4 */ -#define BRDCFG4_USBOSC_MASK 0x01 -#define BRDCFG4_SPI 0x01 - -/* BRDCFG5 */ -#define BRDCFG5_SPR_MASK 0x0f -#define BRDCFG5_SPI_ON_BOARD 0x0a -#define BRDCFG5_SPI_OFF_BOARD 0x0f - -#endif diff --git a/board/freescale/ls2080aqds/Kconfig b/board/freescale/ls2080aqds/Kconfig deleted file mode 100644 index 2f997e9de1a..00000000000 --- a/board/freescale/ls2080aqds/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ - -if TARGET_LS2080AQDS - -config SYS_BOARD - default "ls2080aqds" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls2080aqds" - -endif diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS deleted file mode 100644 index fdad199ec25..00000000000 --- a/board/freescale/ls2080aqds/MAINTAINERS +++ /dev/null @@ -1,13 +0,0 @@ -LS2080A BOARD -M: Priyanka Jain -M: Wasim Khan -S: Maintained -F: board/freescale/ls2080aqds/ -F: board/freescale/ls2080a/ls2080aqds.c -F: include/configs/ls2080aqds.h -F: configs/ls2080aqds_defconfig -F: configs/ls2080aqds_nand_defconfig -F: configs/ls2080aqds_qspi_defconfig -F: configs/ls2080aqds_sdcard_defconfig -F: configs/ls2088aqds_tfa_defconfig -F: configs/ls2080aqds_SECURE_BOOT_defconfig diff --git a/board/freescale/ls2080aqds/Makefile b/board/freescale/ls2080aqds/Makefile deleted file mode 100644 index efc51b4a34d..00000000000 --- a/board/freescale/ls2080aqds/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2015 Freescale Semiconductor - -obj-y += ls2080aqds.o -obj-y += ddr.o -obj-y += eth.o diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README deleted file mode 100644 index a4cb1a6cac4..00000000000 --- a/board/freescale/ls2080aqds/README +++ /dev/null @@ -1,215 +0,0 @@ -Overview --------- -The LS2080A Development System (QDS) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS2080A -and LS2088A Layerscape Architecture processor. The LS2080AQDS provides -validation and SW development platform for the Freescale LS2080A, LS2088A -processor series, with a complete debugging environment. - -LS2080A, LS2088A SoC Overview --------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A, -LS2088A SoC overview. - - LS2080AQDS board Overview - ----------------------- - - SERDES Connections, 16 lanes supporting: - - PCI Express - 3.0 - - SGMII, SGMII 2.5 - - QSGMII - - SATA 3.0 - - XAUI - - 10GBase-R - - DDR Controller - - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four - chip-selects and two DIMM connectors. Support is up to 2133MT/s. - - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects - and two DIMM connectors. Support is up to 1600MT/s. - -IFC/Local Bus - - IFC rev. 2.0 implementation supporting Little Endian connection scheme. - - One in-socket 128 MB NOR flash 16-bit data bus - - One 512 MB NAND flash with ECC support - - IFC Test Port - - PromJet Port - - FPGA connection - - USB 3.0 - - Two high speed USB 3.0 ports - - First USB 3.0 port configured as Host with Type-A connector - - Second USB 3.0 port configured as OTG with micro-AB connector - - SDHC: PCIe x1 Right Angle connector for supporting following cards - - 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only - - 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only - - 4-bit eMMC Card Rev 4.4 (1.8V only) - - 8-bit eMMC Card Rev 4.5 (1.8V only) - - SD Card Rev 2.0 and Rev 3.0 - - DSPI: 3 high-speed flash Memory for storage - - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz) - - 8 MB high-speed flash Memory (up to 104 MHz) - - 512 MB low-speed flash Memory (up to 40 MHz) - - QSPI: via NAND/QSPI Card - - 4 I2C controllers - - Two SATA onboard connectors - - UART - - Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s - - Two DB9 D-Type connectors supporting one Serial port each - - ARM JTAG support - -Memory map from core's view ----------------------------- -0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom -0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR -0x00_1800_0000 .. 0x00_181F_FFFF OCRAM -0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1 -0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1 -0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 -0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 - -Other addresses are either reserved, or not used directly by U-Boot. -This list should be updated when more addresses are used. - -IFC region map from core's view -------------------------------- -During boot i.e. IFC Region #1:- - 0x30000000 - 0x37ffffff : 128MB : NOR flash - 0x38000000 - 0x3BFFFFFF : 64MB : Promjet - 0x3C000000 - 0x40000000 : 64MB : FPGA etc - -After relocate to DDR i.e. IFC Region #2:- - 0x5_1000_0000..0x5_1fff_ffff Memory Hole - 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) - 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB - 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) - 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) - -Booting Options ---------------- -a) Promjet Boot -b) NOR boot -c) NAND boot -d) SD boot -e) QSPI boot - -Memory map for NOR boot -------------------------- -Image Flash Offset -RCW+PBI 0x00000000 -Boot firmware (U-Boot) 0x00100000 -Boot firmware Environment 0x00300000 -PPA firmware 0x00400000 -Secure Headers 0x00600000 -DPAA2 MC 0x00A00000 -DPAA2 DPL 0x00D00000 -DPAA2 DPC 0x00E00000 -Kernel.itb 0x01000000 - -Memory map for SD boot -------------------------- -Image Flash Offset SD Card - Start Block No. -RCW+PBI 0x00000000 0x00008 -Boot firmware (U-Boot) 0x00100000 0x00800 -Boot firmware Environment 0x00300000 0x01800 -PPA firmware 0x00400000 0x02000 -DPAA2 MC 0x00A00000 0x05000 -DPAA2 DPL 0x00D00000 0x06800 -DPAA2 DPC 0x00E00000 0x07000 -Kernel.itb 0x01000000 0x08000 - -Environment Variables ---------------------- -- mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined - the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. - -- mcmemsize: MC DRAM block size. If this variable is not defined - the value CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. - -Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) -------------------------------------------------------------------- -One needs to use appropriate bootargs to boot Linux flavors which do -not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown -below: - -=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram - earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m - hugepages=16 mem=2048M' - - -X-QSGMII-16PORT riser card ----------------------------- -The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes -interfaces implemented in PCIe form factor board. -It supports following: - - Card can operate with up to 4 QSGMII lane simultaneously - - Card can operate with up to 8 SGMII lane simultaneously - -Supported card configuration - - CSEL : ON ON ON ON - - MSEL1 : ON ON ON ON OFF OFF OFF OFF - - MSEL2 : OFF OFF OFF OFF ON ON ON ON - -To enable this card: modify hwconfig to add "xqsgmii" variable. - -Supported PHY addresses during SGMII: -#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 -#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 -#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 -#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 -#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 -#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa -#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc -#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe - -Mapping DPMACx to PHY during SGMII -DPMAC1 -> PHY1-P0 -DPMAC2 -> PHY2-P0 -DPMAC3 -> PHY3-P0 -DPMAC4 -> PHY4-P0 -DPMAC5 -> PHY3-P2 -DPMAC6 -> PHY1-P2 -DPMAC7 -> PHY4-P1 -DPMAC8 -> PHY2-P2 -DPMAC9 -> PHY1-P0 -DPMAC10 -> PHY2-P0 -DPMAC11 -> PHY3-P0 -DPMAC12 -> PHY4-P0 -DPMAC13 -> PHY3-P2 -DPMAC14 -> PHY1-P2 -DPMAC15 -> PHY4-P1 -DPMAC16 -> PHY2-P2 - - -Supported PHY address during QSGMII -#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 -#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 -#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 -#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 -#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 -#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 -#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 -#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 -#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 -#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 -#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa -#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb -#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc -#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd -#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe -#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf - -Mapping DPMACx to PHY during QSGMII -DPMAC1 -> PHY1-P3 -DPMAC2 -> PHY1-P2 -DPMAC3 -> PHY1-P1 -DPMAC4 -> PHY1-P0 -DPMAC5 -> PHY2-P3 -DPMAC6 -> PHY2-P2 -DPMAC7 -> PHY2-P1 -DPMAC8 -> PHY2-P0 -DPMAC9 -> PHY3-P0 -DPMAC10 -> PHY3-P1 -DPMAC11 -> PHY3-P2 -DPMAC12 -> PHY3-P3 -DPMAC13 -> PHY4-P0 -DPMAC14 -> PHY4-P1 -DPMAC15 -> PHY4-P2 -DPMAC16 -> PHY4-P3 diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c deleted file mode 100644 index 31ed72c949b..00000000000 --- a/board/freescale/ls2080aqds/ddr.c +++ /dev/null @@ -1,181 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR - u8 dq_mapping_0, dq_mapping_2, dq_mapping_3; -#endif - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - int slot; - - if (ctrl_num > 2) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - - for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) { - if (pdimm[slot].n_ranks) - break; - } - - if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR) - return; - - /* - * we use identical timing for all slots. If needed, change the code - * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; - */ - if (popts->registered_dimm_en) - pbsp = rdimms[ctrl_num]; - else - pbsp = udimms[ctrl_num]; - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(ctrl_num) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm[slot].n_ranks && - (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for data rate %lu MT/s\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" - "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, - pbsp->wrlvl_ctl_3); -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (ctrl_num == CONFIG_DP_DDR_CTRL) { - /* force DDR bus width to 32 bits */ - popts->data_bus_width = 1; - popts->otf_burst_chop_en = 0; - popts->burst_length = DDR_BL8; - popts->bstopre = 0; /* enable auto precharge */ - /* - * Layout optimization results byte mapping - * Byte 0 -> Byte ECC - * Byte 1 -> Byte 3 - * Byte 2 -> Byte 2 - * Byte 3 -> Byte 1 - * Byte ECC -> Byte 0 - */ - dq_mapping_0 = pdimm[slot].dq_mapping[0]; - dq_mapping_2 = pdimm[slot].dq_mapping[2]; - dq_mapping_3 = pdimm[slot].dq_mapping[3]; - pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8]; - pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9]; - pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6]; - pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7]; - pdimm[slot].dq_mapping[6] = dq_mapping_2; - pdimm[slot].dq_mapping[7] = dq_mapping_3; - pdimm[slot].dq_mapping[8] = dq_mapping_0; - pdimm[slot].dq_mapping[9] = 0; - pdimm[slot].dq_mapping[10] = 0; - pdimm[slot].dq_mapping[11] = 0; - pdimm[slot].dq_mapping[12] = 0; - pdimm[slot].dq_mapping[13] = 0; - pdimm[slot].dq_mapping[14] = 0; - pdimm[slot].dq_mapping[15] = 0; - pdimm[slot].dq_mapping[16] = 0; - pdimm[slot].dq_mapping[17] = 0; - } -#endif - /* To work at higher than 1333MT/s */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0x0; /* 32 clocks */ - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - if (ddr_freq < 2350) { - if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) { - /* four chip-selects */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | - DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm); - popts->twot_en = 1; /* enable 2T timing */ - } else { - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | - DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | - DDR_CDR2_VREF_RANGE_2; - } - } else { - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | - DDR_CDR1_ODT(DDR_CDR_ODT_100ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) | - DDR_CDR2_VREF_RANGE_2; - } -} - -#ifdef CONFIG_TFABOOT -int fsl_initdram(void) -{ - gd->ram_size = tfa_get_dram_size(); - - if (!gd->ram_size) - gd->ram_size = fsl_ddr_sdram_size(); - - return 0; -} -#else -int fsl_initdram(void) -{ -#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) - gd->ram_size = fsl_ddr_sdram_size(); -#else - puts("Initializing DDR....using SPD\n"); - - gd->ram_size = fsl_ddr_sdram(); -#endif - - return 0; -} -#endif /* CONFIG_TFABOOT */ diff --git a/board/freescale/ls2080aqds/ddr.h b/board/freescale/ls2080aqds/ddr.h deleted file mode 100644 index 465155e56bf..00000000000 --- a/board/freescale/ls2080aqds/ddr.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ - -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, - {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2300, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, - {} -}; - -/* DP-DDR DIMM */ -static const struct board_specific_parameters udimm2[] = { - /* - * memory controller 2 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, - {2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, - {2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, - {2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, - {} -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, - {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, - {} -}; - -/* DP-DDR DIMM */ -static const struct board_specific_parameters rdimm2[] = { - /* - * memory controller 2 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,}, - {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, - udimm0, - udimm2, -}; - -static const struct board_specific_parameters *rdimms[] = { - rdimm0, - rdimm0, - rdimm2, -}; - -#endif diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c deleted file mode 100644 index b47e2ec5a79..00000000000 --- a/board/freescale/ls2080aqds/eth.c +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include - -#define MC_BOOT_ENV_VAR "mcinitcmd" - -#if defined(CONFIG_RESET_PHY_R) -void reset_phy(void) -{ - mc_env_boot(); -} -#endif /* CONFIG_RESET_PHY_R */ - -#if defined(CONFIG_MULTI_DTB_FIT) - -/* Structure to hold SERDES protocols supported (network interfaces are - * described in the DTS). - * - * @serdes_block: the index of the SERDES block - * @serdes_protocol: the decimal value of the protocol supported - * @dts_needed: DTS notes describing the current configuration are needed - * - * When dts_needed is true, the board_fit_config_name_match() function - * will try to exactly match the current configuration of the block with a DTS - * name provided. - */ -static struct serdes_configuration { - u8 serdes_block; - u32 serdes_protocol; - bool dts_needed; -} supported_protocols[] = { - /* Serdes block #1 */ - {1, 42, true}, - - /* Serdes block #2 */ - {2, 65, false}, -}; - -#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) - -static bool protocol_supported(u8 serdes_block, u32 protocol) -{ - struct serdes_configuration serdes_conf; - int i; - - for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { - serdes_conf = supported_protocols[i]; - if (serdes_conf.serdes_block == serdes_block && - serdes_conf.serdes_protocol == protocol) - return true; - } - - return false; -} - -static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) -{ - struct serdes_configuration serdes_conf; - int i; - - for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { - serdes_conf = supported_protocols[i]; - if (serdes_conf.serdes_block == serdes_block && - serdes_conf.serdes_protocol == protocol) { - if (serdes_conf.dts_needed == true) - sprintf(str, "%u", protocol); - else - sprintf(str, "x"); - return; - } - } -} - -int board_fit_config_name_match(const char *name) -{ - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 rcw_status = in_le32(&gur->rcwsr[28]); - char srds_s1_str[2], srds_s2_str[2]; - u32 srds_s1, srds_s2; - char expected_dts[100]; - - srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; - - srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; - srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; - - /* Check for supported protocols. The default DTS will be used - * in this case - */ - if (!protocol_supported(1, srds_s1) || - !protocol_supported(2, srds_s2)) - return -1; - - get_str_protocol(1, srds_s1, srds_s1_str); - get_str_protocol(2, srds_s2, srds_s2_str); - - printf("expected_dts %s\n", expected_dts); - sprintf(expected_dts, "fsl-ls2080a-qds-%s-%s", - srds_s1_str, srds_s2_str); - - if (!strcmp(name, expected_dts)) - return 0; - - printf("this is not!\n"); - return -1; -} - -#endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c deleted file mode 100644 index aba0560181a..00000000000 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ /dev/null @@ -1,349 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor - * Copyright 2021 NXP - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/i2c_mux.h" - -#include "../common/qixis.h" -#include "ls2080aqds_qixis.h" -#include "../common/vid.h" - -#define PIN_MUX_SEL_SDHC 0x00 -#define PIN_MUX_SEL_DSPI 0x0a -#define SCFG_QSPICLKCTRL_DIV_20 (5 << 27) - -#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) - -DECLARE_GLOBAL_DATA_PTR; - -enum { - MUX_TYPE_SDHC, - MUX_TYPE_DSPI, -}; - -unsigned long long get_qixis_addr(void) -{ - unsigned long long addr; - - if (gd->flags & GD_FLG_RELOC) - addr = QIXIS_BASE_PHYS; - else - addr = QIXIS_BASE_PHYS_EARLY; - - /* - * IFC address under 256MB is mapped to 0x30000000, any address above - * is mapped to 0x5_10000000 up to 4GB. - */ - addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; - - return addr; -} - -int checkboard(void) -{ - char buf[64]; - u8 sw; - static const char *const freq[] = {"100", "125", "156.25", - "100 separate SSCG"}; - int clock; - - cpu_name(buf); - printf("Board: %s-QDS, ", buf); - - sw = QIXIS_READ(arch); - printf("Board Arch: V%d, ", sw >> 4); - printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); - - memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); - - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank: %d\n", sw); - else if (sw == 0x8) - puts("PromJet\n"); - else if (sw == 0x9) - puts("NAND\n"); - else if (sw == 0xf) - puts("QSPI\n"); - else if (sw == 0x15) - printf("IFCCard\n"); - else - printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); - - printf("FPGA: v%d (%s), build %d", - (int)QIXIS_READ(scver), qixis_read_tag(buf), - (int)qixis_read_minor()); - /* the timestamp string contains "\n" at the end */ - printf(" on %s", qixis_read_time(buf)); - - /* - * Display the actual SERDES reference clocks as configured by the - * dip switches on the board. Note that the SWx registers could - * technically be set to force the reference clocks to match the - * values that the SERDES expects (or vice versa). For now, however, - * we just display both values and hope the user notices when they - * don't match. - */ - puts("SERDES1 Reference : "); - sw = QIXIS_READ(brdcfg[2]); - clock = (sw >> 6) & 3; - printf("Clock1 = %sMHz ", freq[clock]); - clock = (sw >> 4) & 3; - printf("Clock2 = %sMHz", freq[clock]); - - puts("\nSERDES2 Reference : "); - clock = (sw >> 2) & 3; - printf("Clock1 = %sMHz ", freq[clock]); - clock = (sw >> 0) & 3; - printf("Clock2 = %sMHz\n", freq[clock]); - - return 0; -} - -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); - - switch (sysclk_conf & 0x0F) { - case QIXIS_SYSCLK_83: - return 83333333; - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - case QIXIS_SYSCLK_150: - return 150000000; - case QIXIS_SYSCLK_160: - return 160000000; - case QIXIS_SYSCLK_166: - return 166666666; - } - return 66666666; -} - -unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); - - switch ((ddrclk_conf & 0x30) >> 4) { - case QIXIS_DDRCLK_100: - return 100000000; - case QIXIS_DDRCLK_125: - return 125000000; - case QIXIS_DDRCLK_133: - return 133333333; - } - return 66666666; -} - -int config_board_mux(int ctrl_type) -{ - u8 reg5; - - reg5 = QIXIS_READ(brdcfg[5]); - - switch (ctrl_type) { - case MUX_TYPE_SDHC: - reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); - break; - case MUX_TYPE_DSPI: - reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); - break; - default: - printf("Wrong mux interface type\n"); - return -1; - } - - QIXIS_WRITE(brdcfg[5], reg5); - - return 0; -} - -int board_init(void) -{ - char *env_hwconfig; - u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; - u32 val; - - init_final_memctl_regs(); - - val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); - - env_hwconfig = env_get("hwconfig"); - - if (hwconfig_f("dspi", env_hwconfig) && - DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) - config_board_mux(MUX_TYPE_DSPI); - else - config_board_mux(MUX_TYPE_SDHC); - -#if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_FSL_QSPI) - val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4); - - if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3)) - QIXIS_WRITE(brdcfg[9], - (QIXIS_READ(brdcfg[9]) & 0xf8) | - FSL_QIXIS_BRDCFG9_QSPI); -#endif - - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - -#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT -#if CONFIG_IS_ENABLED(DM_I2C) - rtc_enable_32khz_output(0, CFG_SYS_I2C_RTC_ADDR); -#else - rtc_enable_32khz_output(); -#endif -#endif - -#if !defined(CONFIG_SYS_EARLY_PCI_INIT) - pci_init(); -#endif - - return 0; -} - -int board_early_init_f(void) -{ -#if defined(CONFIG_SYS_I2C_EARLY_INIT) - i2c_early_init_f(); -#endif - fsl_lsch3_early_init_f(); -#ifdef CONFIG_FSL_QSPI - /* input clk: 1/2 platform clk, output: input/20 */ - out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20); -#endif - return 0; -} - -int misc_init_r(void) -{ - if (adjust_vdd(0)) - printf("Warning: Adjusting core voltage failed.\n"); - - return 0; -} - -void detail_board_ddr_info(void) -{ - puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); - print_ddr_info(0); -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { - puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); - print_ddr_info(CONFIG_DP_DDR_CTRL); - } -#endif -} - -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) -void fdt_fixup_board_enet(void *fdt) -{ - int offset; - - offset = fdt_path_offset(fdt, "/soc/fsl-mc"); - - if (offset < 0) - offset = fdt_path_offset(fdt, "/fsl-mc"); - - if (offset < 0) { - printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", - __func__, offset); - return; - } - - if (get_mc_boot_status() == 0 && - (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) - fdt_status_okay(fdt, offset); - else - fdt_status_fail(fdt, offset); -} - -void board_quiesce_devices(void) -{ - fsl_mc_ldpaa_exit(gd->bd); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - u64 base[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; - - ft_cpu_setup(blob, bd); - - /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; - -#ifdef CONFIG_RESV_RAM - /* reduce size if reserved memory is within this bank */ - if (gd->arch.resv_ram >= base[0] && - gd->arch.resv_ram < base[0] + size[0]) - size[0] = gd->arch.resv_ram - base[0]; - else if (gd->arch.resv_ram >= base[1] && - gd->arch.resv_ram < base[1] + size[1]) - size[1] = gd->arch.resv_ram - base[1]; -#endif - - fdt_fixup_memory_banks(blob, base, size, 2); - - fdt_fsl_mc_fixup_iommu_map_entry(blob); - - fsl_fdt_fixup_dr_usb(blob, bd); - -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) - fdt_fixup_board_enet(blob); - fdt_reserve_mc_mem(blob, 0x300); -#endif - - fdt_fixup_icid(blob); - - return 0; -} -#endif - -void qixis_dump_switch(void) -{ - int i, nr_of_cfgsw; - - QIXIS_WRITE(cms[0], 0x00); - nr_of_cfgsw = QIXIS_READ(cms[1]); - - puts("DIP switch settings dump:\n"); - for (i = 1; i <= nr_of_cfgsw; i++) { - QIXIS_WRITE(cms[0], i); - printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); - } -} diff --git a/board/freescale/ls2080aqds/ls2080aqds_qixis.h b/board/freescale/ls2080aqds/ls2080aqds_qixis.h deleted file mode 100644 index 7b2607b8daa..00000000000 --- a/board/freescale/ls2080aqds/ls2080aqds_qixis.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __LS2_QDS_QIXIS_H__ -#define __LS2_QDS_QIXIS_H__ - -/* SYSCLK */ -#define QIXIS_SYSCLK_66 0x0 -#define QIXIS_SYSCLK_83 0x1 -#define QIXIS_SYSCLK_100 0x2 -#define QIXIS_SYSCLK_125 0x3 -#define QIXIS_SYSCLK_133 0x4 -#define QIXIS_SYSCLK_150 0x5 -#define QIXIS_SYSCLK_160 0x6 -#define QIXIS_SYSCLK_166 0x7 - -/* DDRCLK */ -#define QIXIS_DDRCLK_66 0x0 -#define QIXIS_DDRCLK_100 0x1 -#define QIXIS_DDRCLK_125 0x2 -#define QIXIS_DDRCLK_133 0x3 - -#define BRDCFG4_EMISEL_MASK 0xE0 -#define BRDCFG4_EMISEL_SHIFT 5 -#define BRDCFG9_SFPTX_MASK 0x10 -#define BRDCFG9_SFPTX_SHIFT 4 -#endif /*__LS2_QDS_QIXIS_H__*/ diff --git a/board/freescale/ls2080ardb/Kconfig b/board/freescale/ls2080ardb/Kconfig deleted file mode 100644 index 671eead5f7f..00000000000 --- a/board/freescale/ls2080ardb/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_LS2080ARDB || TARGET_LS2081ARDB - -config SYS_BOARD - default "ls2080ardb" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls2080ardb" - -endif diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS deleted file mode 100644 index f2f834ffbd9..00000000000 --- a/board/freescale/ls2080ardb/MAINTAINERS +++ /dev/null @@ -1,32 +0,0 @@ -LS2080A BOARD -M: Priyanka Jain -M: Wasim Khan -S: Maintained -F: board/freescale/ls2080ardb/ -F: board/freescale/ls2080a/ls2080ardb.c -F: include/configs/ls2080ardb.h -F: configs/ls2080ardb_defconfig -F: configs/ls2080ardb_nand_defconfig - -LS2088A_QSPI-boot BOARD -M: Priyanka Jain -M: Wasim Khan -S: Maintained -F: configs/ls2088ardb_qspi_defconfig -F: configs/ls2088ardb_tfa_defconfig -F: configs/ls2088ardb_tfa_SECURE_BOOT_defconfig - -LS2081ARDB BOARD -M: Priyanka Jain -S: Maintained -F: configs/ls2081ardb_defconfig - -LS2080A_SECURE_BOOT BOARD -M: Udit Agarwal -S: Maintained -F: configs/ls2080ardb_SECURE_BOOT_defconfig - -LS2088A_QSPI_SECURE_BOOT BOARD -M: Udit Agarwal -S: Maintained -F: configs/ls2088ardb_qspi_SECURE_BOOT_defconfig diff --git a/board/freescale/ls2080ardb/Makefile b/board/freescale/ls2080ardb/Makefile deleted file mode 100644 index ed44d459f01..00000000000 --- a/board/freescale/ls2080ardb/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2015 Freescale Semiconductor - -obj-y += ls2080ardb.o eth_ls2080rdb.o -obj-y += ddr.o diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README deleted file mode 100644 index 4c1c36ea3a5..00000000000 --- a/board/freescale/ls2080ardb/README +++ /dev/null @@ -1,134 +0,0 @@ -Overview --------- -The LS2080A Reference Design (RDB) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS2080A, LS2088A -Layerscape Architecture processor. - -The LS2081A Reference Design (RDB) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS2081A -Layerscape Architecture processor.More details in below sections - -LS2080A, LS2088A, LS2081A SoC Overview --------------------------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A, -LS2081A, LS2088A SoC overview. - - LS2080ARDB board Overview - ----------------------- - - SERDES Connections, 16 lanes supporting: - - PCI Express - 3.0 - - SATA 3.0 - - 10GBase-R - - DDR Controller - - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four - chip-selects and two DIMM connectors. Support is up to 2133MT/s. - - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects - and two DIMM connectors. Support is up to 1600MT/s. - -IFC/Local Bus - - IFC rev. 2.0 implementation supporting Little Endian connection scheme. - - 128 MB NOR flash 16-bit data bus - - One 2 GB NAND flash with ECC support - - CPLD connection - - USB 3.0 - - Two high speed USB 3.0 ports - - First USB 3.0 port configured as Host with Type-A connector - - Second USB 3.0 port configured as OTG with micro-AB connector - - SDHC adapter - - SD Card Rev 2.0 and Rev 3.0 - - DSPI - - 128 MB high-speed flash Memory for boot code and storage (up to 108MHz) - - 4 I2C controllers - - Two SATA onboard connectors - - UART - - ARM JTAG support - - LS2081ARDB board Overview - ------------------------- - LS2081ARDB board is similar to LS2080ARDB board - with few differences like - - Hosts LS2081A SoC - - Default boot source is QSPI-boot - - Does not have IFC interface - - RTC and QSPI flash devices are different - - Provides QIXIS access via I2C - -Memory map from core's view ----------------------------- -0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom -0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR -0x00_1800_0000 .. 0x00_181F_FFFF OCRAM -0x00_2000_0000 .. 0x00_2FFF_FFFF QSPI region #1 -0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1 -0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1 -0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 -0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 - -Other addresses are either reserved, or not used directly by U-Boot. -This list should be updated when more addresses are used. - -IFC region map from core's view -------------------------------- -During boot i.e. IFC Region #1:- - 0x30000000 - 0x37ffffff : 128MB : NOR flash - 0x3C000000 - 0x40000000 : 64MB : CPLD - -After relocate to DDR i.e. IFC Region #2:- - 0x5_1000_0000..0x5_1fff_ffff Memory Hole - 0x5_2000_0000..0x5_3fff_ffff IFC CSx (CPLD, NAND and others 512MB) - 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB - 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) - 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) - -Booting Options ---------------- -a) NOR boot -b) NAND boot -c) QSPI boot - -Memory map for NOR boot -------------------------- -Image Flash Offset -RCW+PBI 0x00000000 -Boot firmware (U-Boot) 0x00100000 -Boot firmware Environment 0x00300000 -PPA firmware 0x00400000 -Secure Headers 0x00600000 -Cortina PHY firmware 0x00980000 -DPAA2 MC 0x00A00000 -DPAA2 DPL 0x00D00000 -DPAA2 DPC 0x00E00000 -Kernel.itb 0x01000000 - -cfg_rcw_src switches needs to be changed for booting from different option. -Refer to board documentation for correct switch setting. - -QSPI boot details -=================== -Supported only for - LS2088ARDB RevF board with LS2088A SoC. - -Images needs to be copied to QSPI flash -as per memory map given below. - -Memory map for QSPI flash -------------------------- -Image Flash Offset -RCW+PBI 0x00000000 -Boot firmware (U-Boot) 0x00100000 -Boot firmware Environment 0x00300000 -PPA firmware 0x00400000 -Cortina PHY firmware 0x00980000 -DPAA2 MC 0x00A00000 -DPAA2 DPL 0x00D00000 -DPAA2 DPC 0x00E00000 -Kernel.itb 0x01000000 - -Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) -------------------------------------------------------------------- -One needs to use appropriate bootargs to boot Linux flavors which do -not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown -below: - -=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram - earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m - hugepages=16 mem=2048M' diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c deleted file mode 100644 index e56667c846f..00000000000 --- a/board/freescale/ls2080ardb/ddr.c +++ /dev/null @@ -1,186 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR - u8 dq_mapping_0, dq_mapping_2, dq_mapping_3; -#endif - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - int slot; - - if (ctrl_num > 2) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - - for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) { - if (pdimm[slot].n_ranks) - break; - } - - if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR) - return; - - /* - * we use identical timing for all slots. If needed, change the code - * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; - */ - if (popts->registered_dimm_en) - pbsp = rdimms[ctrl_num]; - else - pbsp = udimms[ctrl_num]; - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(ctrl_num) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm[slot].n_ranks && - (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for data rate %lu MT/s\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" - "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, - pbsp->wrlvl_ctl_3); -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (ctrl_num == CONFIG_DP_DDR_CTRL) { - if (popts->registered_dimm_en) - printf("WARN: RDIMM not supported.\n"); - /* force DDR bus width to 32 bits */ - popts->data_bus_width = 1; - popts->otf_burst_chop_en = 0; - popts->burst_length = DDR_BL8; - popts->bstopre = 0; /* enable auto precharge */ - /* - * Layout optimization results byte mapping - * Byte 0 -> Byte ECC - * Byte 1 -> Byte 3 - * Byte 2 -> Byte 2 - * Byte 3 -> Byte 1 - * Byte ECC -> Byte 0 - */ - dq_mapping_0 = pdimm[slot].dq_mapping[0]; - dq_mapping_2 = pdimm[slot].dq_mapping[2]; - dq_mapping_3 = pdimm[slot].dq_mapping[3]; - pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8]; - pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9]; - pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6]; - pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7]; - pdimm[slot].dq_mapping[6] = dq_mapping_2; - pdimm[slot].dq_mapping[7] = dq_mapping_3; - pdimm[slot].dq_mapping[8] = dq_mapping_0; - pdimm[slot].dq_mapping[9] = 0; - pdimm[slot].dq_mapping[10] = 0; - pdimm[slot].dq_mapping[11] = 0; - pdimm[slot].dq_mapping[12] = 0; - pdimm[slot].dq_mapping[13] = 0; - pdimm[slot].dq_mapping[14] = 0; - pdimm[slot].dq_mapping[15] = 0; - pdimm[slot].dq_mapping[16] = 0; - pdimm[slot].dq_mapping[17] = 0; - } -#endif - /* To work at higher than 1333MT/s */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0x0; /* 32 clocks */ - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x6e; - - if (ddr_freq < 2350) { - if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) { - /* four chip-selects */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | - DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm); - popts->twot_en = 1; /* enable 2T timing */ - } else { - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | - DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | - DDR_CDR2_VREF_RANGE_2; - } - } else { - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | - DDR_CDR1_ODT(DDR_CDR_ODT_100ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) | - DDR_CDR2_VREF_RANGE_2; - } -} - -#ifdef CONFIG_TFABOOT -int fsl_initdram(void) -{ - gd->ram_size = tfa_get_dram_size(); - - if (!gd->ram_size) - gd->ram_size = fsl_ddr_sdram_size(); - - return 0; -} -#else -int fsl_initdram(void) -{ -#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) - gd->ram_size = fsl_ddr_sdram_size(); -#else - puts("Initializing DDR....using SPD\n"); - - gd->ram_size = fsl_ddr_sdram(); -#endif - - return 0; -} -#endif /* CONFIG_TFABOOT */ diff --git a/board/freescale/ls2080ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h deleted file mode 100644 index 43301dc72a3..00000000000 --- a/board/freescale/ls2080ardb/ddr.h +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ - -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 10, 9, 0x090A0B0E, 0x0F11110C,}, - {2, 1900, 0, 12, 0xA, 0x0B0C0E11, 0x1214140F,}, - {2, 2300, 0, 12, 0xB, 0x0C0D0F12, 0x14161610,}, - {} -}; - -/* DP-DDR DIMM */ -static const struct board_specific_parameters udimm2[] = { - /* - * memory controller 2 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, - {2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, - {2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, - {2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, - {} -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 1666, 0, 8, 0x0F, 0x0D0C0A09, 0x0B0C0E08,}, - {2, 1900, 0, 8, 0x10, 0x0F0D0B0A, 0x0B0E0F09,}, - {2, 2200, 0, 8, 0x13, 0x120F0E0B, 0x0D10110B,}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, - udimm0, - udimm2, -}; - -static const struct board_specific_parameters *rdimms[] = { - rdimm0, - rdimm0, - udimm2, /* DP-DDR doesn't support RDIMM */ -}; - -#endif diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c deleted file mode 100644 index 7d5beb32417..00000000000 --- a/board/freescale/ls2080ardb/eth_ls2080rdb.c +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_eth_init(struct bd_info *bis) -{ - -#if defined(CONFIG_PHY_AQUANTIA) && !defined(CONFIG_XPL_BUILD) - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - - return 0; -} - -#if defined(CONFIG_RESET_PHY_R) -void reset_phy(void) -{ - mc_env_boot(); -} -#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c deleted file mode 100644 index 6f824f57c47..00000000000 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ /dev/null @@ -1,571 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor - * Copyright 2017, 2021 NXP - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/i2c_mux.h" - -#ifdef CONFIG_FSL_QIXIS -#include "../common/qixis.h" -#include "ls2080ardb_qixis.h" -#endif -#include "../common/vid.h" - -#define CORTINA_FW_ADDR_IFCNOR 0x580980000 -#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0x584980000 -#define CORTINA_FW_ADDR_QSPI 0x980000 -#define PIN_MUX_SEL_SDHC 0x00 -#define PIN_MUX_SEL_DSPI 0x0a - -#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) -DECLARE_GLOBAL_DATA_PTR; - -enum { - MUX_TYPE_SDHC, - MUX_TYPE_DSPI, -}; - -#ifdef CONFIG_VID -u16 soc_get_fuse_vid(int vid_index) -{ - static const u16 vdd[32] = { - 10500, - 0, /* reserved */ - 9750, - 0, /* reserved */ - 9500, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 9000, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 10000, /* 1.0000V */ - 0, /* reserved */ - 10250, - 0, /* reserved */ - 10500, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - }; - - return vdd[vid_index]; -}; -#endif - -unsigned long long get_qixis_addr(void) -{ - unsigned long long addr; - - if (gd->flags & GD_FLG_RELOC) - addr = QIXIS_BASE_PHYS; - else - addr = QIXIS_BASE_PHYS_EARLY; - - /* - * IFC address under 256MB is mapped to 0x30000000, any address above - * is mapped to 0x5_10000000 up to 4GB. - */ - addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; - - return addr; -} - -int checkboard(void) -{ -#ifdef CONFIG_FSL_QIXIS - u8 sw; -#endif - char buf[15]; - - cpu_name(buf); - printf("Board: %s-RDB, ", buf); - -#ifdef CONFIG_TARGET_LS2081ARDB -#ifdef CONFIG_FSL_QIXIS - sw = QIXIS_READ(arch); - printf("Board version: %c, ", (sw & 0xf) + 'A'); - - sw = QIXIS_READ(brdcfg[0]); - sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK; - switch (sw) { - case 0: - puts("boot from QSPI DEV#0\n"); - puts("QSPI_CSA_1 mapped to QSPI DEV#1\n"); - break; - case 1: - puts("boot from QSPI DEV#1\n"); - puts("QSPI_CSA_1 mapped to QSPI DEV#0\n"); - break; - case 2: - puts("boot from QSPI EMU\n"); - puts("QSPI_CSA_1 mapped to QSPI DEV#0\n"); - break; - case 3: - puts("boot from QSPI EMU\n"); - puts("QSPI_CSA_1 mapped to QSPI DEV#1\n"); - break; - case 4: - puts("boot from QSPI DEV#0\n"); - puts("QSPI_CSA_1 mapped to QSPI EMU\n"); - break; - default: - printf("invalid setting of SW%u\n", sw); - break; - } - printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); -#endif - puts("SERDES1 Reference : "); - printf("Clock1 = 100MHz "); - printf("Clock2 = 161.13MHz"); -#else -#ifdef CONFIG_FSL_QIXIS - sw = QIXIS_READ(arch); - printf("Board Arch: V%d, ", sw >> 4); - printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); - - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank: %d\n", sw); - else if (sw == 0x9) - puts("NAND\n"); - else - printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); - - printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); -#endif - puts("SERDES1 Reference : "); - printf("Clock1 = 156.25MHz "); - printf("Clock2 = 156.25MHz"); -#endif - - puts("\nSERDES2 Reference : "); - printf("Clock1 = 100MHz "); - printf("Clock2 = 100MHz\n"); - - return 0; -} - -unsigned long get_board_sys_clk(void) -{ -#ifdef CONFIG_FSL_QIXIS - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); - - switch (sysclk_conf & 0x0F) { - case QIXIS_SYSCLK_83: - return 83333333; - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - case QIXIS_SYSCLK_150: - return 150000000; - case QIXIS_SYSCLK_160: - return 160000000; - case QIXIS_SYSCLK_166: - return 166666666; - } -#endif - return 100000000; -} - -int i2c_multiplexer_select_vid_channel(u8 channel) -{ - return select_i2c_ch_pca9547(channel, 0); -} - -int config_board_mux(int ctrl_type) -{ -#ifdef CONFIG_FSL_QIXIS - u8 reg5; - - reg5 = QIXIS_READ(brdcfg[5]); - - switch (ctrl_type) { - case MUX_TYPE_SDHC: - reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); - break; - case MUX_TYPE_DSPI: - reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); - break; - default: - printf("Wrong mux interface type\n"); - return -1; - } - - QIXIS_WRITE(brdcfg[5], reg5); -#endif - return 0; -} - -ulong *cs4340_get_fw_addr(void) -{ -#ifdef CONFIG_TFABOOT - struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 svr = gur_in32(&gur->svr); -#endif - ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR; - -#ifdef CONFIG_TFABOOT - /* LS2088A TFA boot */ - if (SVR_SOC_VER(svr) == SVR_LS2088A) { - enum boot_src src = get_boot_src(); - u8 sw; - - switch (src) { - case BOOT_SOURCE_IFC_NOR: - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & 0x0f); - if (sw == 0) - cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR; - else if (sw == 4) - cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK; - break; - case BOOT_SOURCE_QSPI_NOR: - /* Only one bank in QSPI */ - cortina_fw_addr = CORTINA_FW_ADDR_QSPI; - break; - default: - printf("WARNING: Boot source not found\n"); - } - } -#endif - return (ulong *)cortina_fw_addr; -} - -int board_init(void) -{ -#ifdef CONFIG_FSL_MC_ENET - u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; -#endif - - init_final_memctl_regs(); - - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - -#ifdef CONFIG_FSL_QIXIS - QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); -#endif - -#ifdef CONFIG_FSL_MC_ENET - /* invert AQR405 IRQ pins polarity */ - out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); -#endif - -#if !defined(CONFIG_SYS_EARLY_PCI_INIT) - pci_init(); -#endif - - return 0; -} - -int board_early_init_f(void) -{ -#if defined(CONFIG_SYS_I2C_EARLY_INIT) - i2c_early_init_f(); -#endif - fsl_lsch3_early_init_f(); - return 0; -} - -int misc_init_r(void) -{ - char *env_hwconfig; - u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; - u32 val; - struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 svr = gur_in32(&gur->svr); - - val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); - - env_hwconfig = env_get("hwconfig"); - - if (hwconfig_f("dspi", env_hwconfig) && - DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) - config_board_mux(MUX_TYPE_DSPI); - else - config_board_mux(MUX_TYPE_SDHC); - - /* - * LS2081ARDB RevF board has smart voltage translator - * which needs to be programmed to enable high speed SD interface - * by setting GPIO4_10 output to zero - */ -#ifdef CONFIG_TARGET_LS2081ARDB - out_le32(GPIO4_GPDIR_ADDR, (1 << 21 | - in_le32(GPIO4_GPDIR_ADDR))); - out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) & - in_le32(GPIO4_GPDAT_ADDR))); -#endif - if (hwconfig("sdhc")) - config_board_mux(MUX_TYPE_SDHC); - - if (adjust_vdd(0)) - printf("Warning: Adjusting core voltage failed.\n"); - /* - * Default value of board env is based on filename which is - * ls2080ardb. Modify board env for other supported SoCs - */ - if ((SVR_SOC_VER(svr) == SVR_LS2088A) || - (SVR_SOC_VER(svr) == SVR_LS2048A)) - env_set("board", "ls2088ardb"); - else if ((SVR_SOC_VER(svr) == SVR_LS2081A) || - (SVR_SOC_VER(svr) == SVR_LS2041A)) - env_set("board", "ls2081ardb"); - - return 0; -} - -void detail_board_ddr_info(void) -{ - puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); - print_ddr_info(0); -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { - puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); - print_ddr_info(CONFIG_DP_DDR_CTRL); - } -#endif -} - -#ifdef CONFIG_FSL_MC_ENET -void fdt_fixup_board_enet(void *fdt) -{ - int offset; - - offset = fdt_path_offset(fdt, "/soc/fsl-mc"); - - if (offset < 0) - offset = fdt_path_offset(fdt, "/fsl-mc"); - - if (offset < 0) { - printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", - __func__, offset); - return; - } - - if (get_mc_boot_status() == 0 && - (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) - fdt_status_okay(fdt, offset); - else - fdt_status_fail(fdt, offset); -} - -void board_quiesce_devices(void) -{ - fsl_mc_ldpaa_exit(gd->bd); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -void fsl_fdt_fixup_flash(void *fdt) -{ - int offset; -#ifdef CONFIG_TFABOOT - u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; - u32 val; -#endif - -/* - * IFC and QSPI are muxed on board. - * So disable IFC node in dts if QSPI is enabled or - * disable QSPI node in dts in case QSPI is not enabled. - */ -#ifdef CONFIG_TFABOOT - enum boot_src src = get_boot_src(); - bool disable_ifc = false; - - switch (src) { - case BOOT_SOURCE_IFC_NOR: - disable_ifc = false; - break; - case BOOT_SOURCE_QSPI_NOR: - disable_ifc = true; - break; - default: - val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4); - if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3)) - disable_ifc = true; - break; - } - - if (disable_ifc) { - offset = fdt_path_offset(fdt, "/soc/ifc"); - - if (offset < 0) - offset = fdt_path_offset(fdt, "/ifc"); - } else { - offset = fdt_path_offset(fdt, "/soc/quadspi"); - - if (offset < 0) - offset = fdt_path_offset(fdt, "/quadspi"); - } - -#else -#ifdef CONFIG_FSL_QSPI - offset = fdt_path_offset(fdt, "/soc/ifc"); - - if (offset < 0) - offset = fdt_path_offset(fdt, "/ifc"); -#else - offset = fdt_path_offset(fdt, "/soc/quadspi"); - - if (offset < 0) - offset = fdt_path_offset(fdt, "/quadspi"); -#endif -#endif - - if (offset < 0) - return; - - fdt_status_disabled(fdt, offset); -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - int i; - u16 mc_memory_bank = 0; - - u64 *base; - u64 *size; - u64 mc_memory_base = 0; - u64 mc_memory_size = 0; - u16 total_memory_banks; - - ft_cpu_setup(blob, bd); - - fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); - - if (mc_memory_base != 0) - mc_memory_bank++; - - total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; - - base = calloc(total_memory_banks, sizeof(u64)); - size = calloc(total_memory_banks, sizeof(u64)); - - /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; - -#ifdef CONFIG_RESV_RAM - /* reduce size if reserved memory is within this bank */ - if (gd->arch.resv_ram >= base[0] && - gd->arch.resv_ram < base[0] + size[0]) - size[0] = gd->arch.resv_ram - base[0]; - else if (gd->arch.resv_ram >= base[1] && - gd->arch.resv_ram < base[1] + size[1]) - size[1] = gd->arch.resv_ram - base[1]; -#endif - - if (mc_memory_base != 0) { - for (i = 0; i <= total_memory_banks; i++) { - if (base[i] == 0 && size[i] == 0) { - base[i] = mc_memory_base; - size[i] = mc_memory_size; - break; - } - } - } - - fdt_fixup_memory_banks(blob, base, size, total_memory_banks); - - fdt_fsl_mc_fixup_iommu_map_entry(blob); - - fsl_fdt_fixup_dr_usb(blob, bd); - - fsl_fdt_fixup_flash(blob); - -#ifdef CONFIG_FSL_MC_ENET - fdt_fixup_board_enet(blob); - fdt_reserve_mc_mem(blob, 0x300); -#endif - - fdt_fixup_icid(blob); - - return 0; -} -#endif - -void qixis_dump_switch(void) -{ -#ifdef CONFIG_FSL_QIXIS - int i, nr_of_cfgsw; - - QIXIS_WRITE(cms[0], 0x00); - nr_of_cfgsw = QIXIS_READ(cms[1]); - - puts("DIP switch settings dump:\n"); - for (i = 1; i <= nr_of_cfgsw; i++) { - QIXIS_WRITE(cms[0], i); - printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); - } -#endif -} - -/* - * Board rev C and earlier has duplicated I2C addresses for 2nd controller. - * Both slots has 0x54, resulting 2nd slot unusable. - */ -void update_spd_address(unsigned int ctrl_num, - unsigned int slot, - unsigned int *addr) -{ -#ifndef CONFIG_TARGET_LS2081ARDB -#ifdef CONFIG_FSL_QIXIS - u8 sw; - - sw = QIXIS_READ(arch); - if ((sw & 0xf) < 0x3) { - if (ctrl_num == 1 && slot == 0) - *addr = SPD_EEPROM_ADDRESS4; - else if (ctrl_num == 1 && slot == 1) - *addr = SPD_EEPROM_ADDRESS3; - } -#endif -#endif -} diff --git a/board/freescale/ls2080ardb/ls2080ardb_qixis.h b/board/freescale/ls2080ardb/ls2080ardb_qixis.h deleted file mode 100644 index db3c6dc2a2a..00000000000 --- a/board/freescale/ls2080ardb/ls2080ardb_qixis.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __LS2_RDB_QIXIS_H__ -#define __LS2_RDB_QIXIS_H__ - -/* SYSCLK */ -#define QIXIS_SYSCLK_66 0x0 -#define QIXIS_SYSCLK_83 0x1 -#define QIXIS_SYSCLK_100 0x2 -#define QIXIS_SYSCLK_125 0x3 -#define QIXIS_SYSCLK_133 0x4 -#define QIXIS_SYSCLK_150 0x5 -#define QIXIS_SYSCLK_160 0x6 -#define QIXIS_SYSCLK_166 0x7 - -#endif /*__LS2_RDB_QIXIS_H__*/ diff --git a/board/freescale/lx2160a/Kconfig b/board/freescale/lx2160a/Kconfig deleted file mode 100644 index 0e4b4158a7f..00000000000 --- a/board/freescale/lx2160a/Kconfig +++ /dev/null @@ -1,47 +0,0 @@ -if TARGET_LX2160ARDB - -config SYS_BOARD - default "lx2160a" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "lx2160ardb" - -endif - -if TARGET_LX2160AQDS - -config SYS_BOARD - default "lx2160a" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "lx2160aqds" - -endif - -if TARGET_LX2162AQDS - -config SYS_BOARD - default "lx2160a" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "lx2162aqds" - -endif diff --git a/board/freescale/lx2160a/MAINTAINERS b/board/freescale/lx2160a/MAINTAINERS deleted file mode 100644 index c60b2af6e42..00000000000 --- a/board/freescale/lx2160a/MAINTAINERS +++ /dev/null @@ -1,55 +0,0 @@ -LX2160ARDB BOARD -M: Meenakshi Aggarwal -M: Priyanka Jain -M: Wasim Khan -S: Maintained -F: board/freescale/lx2160a/ -F: include/configs/lx2160a_common.h -F: include/configs/lx2160ardb.h -F: configs/lx2160ardb_tfa_defconfig -F: configs/lx2160ardb_tfa_stmm_defconfig -F: arch/arm/dts/fsl-lx2160a-rdb.dts - -LX2160ARDB_SECURE_BOOT BOARD -M: Udit Agarwal -S: Maintained -F: configs/lx2160ardb_tfa_SECURE_BOOT_defconfig - -LX2160AQDS BOARD -M: Meenakshi Aggarwal -M: Wasim Khan -S: Maintained -F: board/freescale/lx2160a/eth_lx2160aqds.h -F: include/configs/lx2160aqds.h -F: configs/lx2160aqds_tfa_defconfig -F: arch/arm/dts/fsl-lx2160a-qds.dts - -LX2160AQDS_SECURE_BOOT BOARD -M: Udit Agarwal -S: Maintained -F: configs/lx2160aqds_tfa_SECURE_BOOT_defconfig - -LX2162AQDS BOARD -M: Meenakshi Aggarwal -M: Wasim Khan -S: Maintained -F: board/freescale/lx2160a/eth_lx2162aqds.h -F: include/configs/lx2162aqds.h -F: configs/lx2162aqds_tfa_defconfig -F: arch/arm/dts/fsl-lx2162a-qds.dts -F: arch/arm/dts/fsl-lx2162a-qds-17-x.dts -F: arch/arm/dts/fsl-lx2162a-qds-18-x.dts -F: arch/arm/dts/fsl-lx2162a-qds-20-x.dts -F: arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi -F: arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi -F: arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi - -LX2162AQDS_SECURE_BOOT BOARD -M: Manish Tomar -S: Maintained -F: configs/lx2162aqds_tfa_SECURE_BOOT_defconfig - -LX2162AQDS_VERIFIED_BOOT BOARD -M: Manish Tomar -S: Maintained -F: configs/lx2162aqds_tfa_verified_boot_defconfig diff --git a/board/freescale/lx2160a/Makefile b/board/freescale/lx2160a/Makefile deleted file mode 100644 index c9561bfadea..00000000000 --- a/board/freescale/lx2160a/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright 2018 Freescale Semiconductor -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += lx2160a.o -obj-y += ddr.o -obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o -obj-$(CONFIG_TARGET_LX2160AQDS) += eth_lx2160aqds.o -obj-$(CONFIG_TARGET_LX2162AQDS) += eth_lx2162aqds.o diff --git a/board/freescale/lx2160a/README b/board/freescale/lx2160a/README deleted file mode 100644 index 7bca98dd3d7..00000000000 --- a/board/freescale/lx2160a/README +++ /dev/null @@ -1,329 +0,0 @@ -Overview --------- -The LX2160A Reference Design (RDB) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LX2160A -Layerscape Architecture processor and its personalities. - -LX2160A SoC Overview --------------------------------------- -For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc - -LX2160ARDB board Overview ----------------------- -DDR Memory - Two ports of 72-bits (8-bits ECC) DDR4. - Each port supports four chip-selects and two DIMM - connectors. Data rate upto 3.2 GT/s. - -SERDES ports - Thress serdes controllers (24 lanes) - Serdes1: Supports two USXGMII connectors, each connected through - Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi - IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi - CS4223 phy. - - Serdes2: Supports one PCIe x4 (Gen1/2/3/4) connector, four SATA 3.0 - connectors - - Serdes3: Supports one PCIe x8 (Gen1/2/3/4) connector - -eSDHC - eSDHC1: Supports a SD connector for connecting SD cards - eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC - -Octal SPI (XSPI) - Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator - for off-board emulation - -I2C All system devices on I2C1 multiplexed using PCA9547 multiplexer - Serial Ports - -USB 3.0 - Two high speed USB 3.0 ports. First USB 3.0 port configured as - Host with Type-A connector, second USB 3.0 port configured as OTG - with micro-AB connector - -Serial Ports Two UART ports -Ethernet Two RGMII interfaces -Debug ARM JTAG support - -Booting Options ---------------- -a) Flexspi boot -b) SD boot - -Memory map for Flexspi flash ----------------------------- -Image Flash Offset -bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl) 0x00000000 -fip.bin (bl31 + bl33(u-boot) + - header for Secure-boot(secure-boot only)) 0x00100000 -Boot firmware Environment 0x00500000 -DDR PHY Firmware (fip_ddr_all.bin) 0x00800000 -DPAA2 MC Firmware 0x00A00000 -DPAA2 DPL 0x00D00000 -DPAA2 DPC 0x00E00000 -Kernel.itb 0x01000000 - -Memory map for sd card ----------------------------- -Image SD card Offset -bl2_sd.pbl (RCW+PBI+bl2.pbl) 0x00008 -fip.bin (bl31 + bl33(u-boot) + - header for Secure-boot(secure-boot only)) 0x00800 -Boot firmware Environment 0x02800 -DDR PHY Firmware (fip_ddr_all.bin) 0x04000 -DPAA2 MC Firmware 0x05000 -DPAA2 DPL 0x06800 -DPAA2 DPC 0x07000 -Kernel.itb 0x08000 - -LX2160AQDS board Overview ----------------------- -Various Mezzanine cards and their connection for different SERDES protocols is -as below: - -SERDES1 |CARDS ------------------------------------------------------------------------ -1 |Mezzanine:X-M4-PCIE-SGMII (29733) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) - |Connect I/O cable to IO_SLOT1(J110) - |Mezzanine:X-M4-PCIE-SGMII (29733) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111) - |Connect I/O cable to IO_SLOT2(J113) ------------------------------------------------------------------------- -3 |Mezzanine:X-M11-USXGMII (29828) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) - |Connect I/O cable to IO_SLOT1(J110) - |Mezzanine:X-M4-PCIE-SGMII (29733) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111) - |Connect I/O cable to IO_SLOT2(J113) ------------------------------------------------------------------------- -7 |Mezzanine:X-M11-USXGMII (29828) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) - |Connect I/O cable to IO_SLOT1(J110) - |Mezzanine:X-M4-PCIE-SGMII (29733) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111) - |Connect I/O cable to IO_SLOT2(J113) ------------------------------------------------------------------------- -8 |Mezzanine:X-M12-XFI (29829) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) - |Connect I/O cable to IO_SLOT1(J110) - |Mezzanine:X-M12-XFI (29829) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111) - |Connect I/O cable to IO_SLOT2(J113) ------------------------------------------------------------------------- -13 |Mezzanine:X-M8-100G (29734) - |Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) - |Connect I/O cable to IO_SLOT1(J110) - |Mezzanine:X-M8-100G (29734) - |Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT2(J111) - |Connect I/O cable to IO_SLOT2(J113) ------------------------------------------------------------------------- -15 |Mezzanine:X-M8-100G (29734) - |Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) - |Connect I/O cable to IO_SLOT1(J110) - |Mezzanine:X-M4-PCIE-SGMII (29733) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111) - |Connect I/O cable to IO_SLOT2(J113) ------------------------------------------------------------------------- -17 |Mezzanine:X-M13-25G (32133) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) - |Connect I/O cable to IO_SLOT1(J110) - |Mezzanine:X-M4-PCIE-SGMII (29733) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111) - |Connect I/O cable to IO_SLOT2(J113) ------------------------------------------------------------------------- -19 |Mezzanine:X-M11-USXGMII (29828), X-M13-25G (32133) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) - |Connect M11 I/O cable to IO_SLOT1(J110), M13 I/O cable to IO_SLOT6(J125) - |Mezzanine:X-M7-40G (29738) - |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT2 (J111) - |Connect I/O cable to IO_SLOT2(J113) ------------------------------------------------------------------------- -20 |Mezzanine:X-M7-40G (29738) - |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) - |Connect I/O cable to IO_SLOT1(J108) - |Mezzanine:X-M7-40G (29738) - |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT2 (J111) - |Connect I/O cable to IO_SLOT2(J113) ------------------------------------------------------------------------- - - -SERDES2 |CARDS ------------------------------------------------------------------------ -2 |Mezzanine:X-M6-PCIE-X8 (29737) * - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) - |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT4 (J117) - |Connect I/O cable to IO_SLOT3(J116) ------------------------------------------------------------------------- -3 |Mezzanine:X-M4-PCIE-SGMII (29733) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) - |Connect I/O cable to IO_SLOT3(J116) - |Mezzanine:X-M4-PCIE-SGMII (29733) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) - |Connect I/O cable to IO_SLOT4(J119) ------------------------------------------------------------------------- -5 |Mezzanine:X-M4-PCIE-SGMII (29733) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) - |Connect I/O cable to IO_SLOT3(J116) - |Mezzanine:X-M5-SATA (29687) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) - |Connect I/O cable to IO_SLOT4(J119) ------------------------------------------------------------------------- -11 |Mezzanine:X-M4-PCIE-SGMII (29733) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) - |Connect I/O cable to IO_SLOT7(J127) - |Mezzanine:X-M4-PCIE-SGMII (29733) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) - |Connect I/O cable to IO_SLOT8(J131) ------------------------------------------------------------------------- - - -SERDES3 |CARDS ------------------------------------------------------------------------ -2 |Mezzanine:X-M6-PCIE-X8 (29737) * - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT5 (J120) - |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT6 (J123) - |Connect I/O cable to IO_SLOT5(J122) -------------------------------------------------------------------------- -3 |Mezzanine:X-M4-PCIE-SGMII (29733) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT5 (J120) - |Connect I/O cable to IO_SLOT5(J122) - |Mezzanine:X-M4-PCIE-SGMII (29733) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT6 (J123) - |Connect I/O cable to IO_SLOT6(J125) -------------------------------------------------------------------------- - -LX2162A SoC Overview --------------------------------------- -For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc - -LX2162AQDS board Overview ----------------------- -DDR Memory - One ports of 72-bits (8-bits ECC) DDR4. - Each port supports four chip-selects and two DIMM - connectors. Data rate upto 2.9 GT/s. - -SERDES ports - Two serdes controllers (12 lanes) - Serdes1: Supports two USXGMII connectors, each connected through - Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi - IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi - CS4223 phy. - - Serdes2: Supports two PCIe x4 (Gen3) and one PCIe x8 (Gen3) connector, - four SATA 3.0 connectors - -eSDHC - eSDHC1: Supports a SD connector for connecting SD cards - eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC - -Octal SPI (XSPI) - Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator - for off-board emulation - -I2C All system devices on I2C1 multiplexed using PCA9547 multiplexer - Serial Ports - -USB 3.0 - One high speed USB 3.0 ports. First USB 3.0 port configured as Host - with Type-A connector, second USB 3.0 port configured as OTG with - micro-AB connector - -Serial Ports Two UART ports -Ethernet Two RGMII interfaces -Debug ARM JTAG support - -Booting Options ---------------- -a) Flexspi boot -b) SD boot -c) eMMC boot - -Memory map for Flexspi flash ----------------------------- -Image Flash Offset -bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl) 0x00000000 -fip.bin (bl31 + bl33(u-boot) + - header for Secure-boot(secure-boot only)) 0x00100000 -Boot firmware Environment 0x00500000 -DDR PHY Firmware (fip_ddr_all.bin) 0x00800000 -DPAA2 MC Firmware 0x00A00000 -DPAA2 DPL 0x00D00000 -DPAA2 DPC 0x00E00000 -Kernel.itb 0x01000000 - -Memory map for sd/eMMC card ----------------------------- -Image SD/eMMC card Offset -bl2_sd.pbl (RCW+PBI+bl2.pbl) 0x00008 -fip.bin (bl31 + bl33(u-boot) + - header for Secure-boot(secure-boot only)) 0x00800 -Boot firmware Environment 0x02800 -DDR PHY Firmware (fip_ddr_all.bin) 0x04000 -DPAA2 MC Firmware 0x05000 -DPAA2 DPL 0x06800 -DPAA2 DPC 0x07000 -Kernel.itb 0x08000 - -Various Mezzanine cards and their connection for different SERDES protocols is -as below: - -SERDES1 |CARDS ------------------------------------------------------------------------ -1 |Mezzanine:X-M4-PCIE-SGMII (29733) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) - |Connect I/O cable to IO_SLOT1(J110) ------------------------------------------------------------------------- -3 |Mezzanine:X-M11-USXGMII (29828) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) - |Connect I/O cable to IO_SLOT1(J110) ------------------------------------------------------------------------- -15 |Mezzanine:X-M8-50G (29734) - |Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) - |Connect I/O cable to IO_SLOT1(J110) ------------------------------------------------------------------------- -17 |Mezzanine:X-M13-25G (32133) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) - |Connect I/O cable to IO_SLOT1(J110) ------------------------------------------------------------------------- -18 |Mezzanine:X-M11-USXGMII (29828), X-M13-25G (32133) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) - |Connect M11 I/O cable to IO_SLOT1(J110), M13 I/O cable to IO_SLOT6(J125) ------------------------------------------------------------------------- -20 |Mezzanine:X-M7-40G (29738) - |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) - |Connect I/O cable to IO_SLOT1(J108) ------------------------------------------------------------------------- - - -SERDES2 |CARDS ------------------------------------------------------------------------ -2 |Mezzanine:X-M6-PCIE-X8 (29737) * - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) - |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT4 (J117) - |Connect I/O cable to IO_SLOT3(J116) ------------------------------------------------------------------------- -3 |Mezzanine:X-M4-PCIE-SGMII (29733) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) - |Connect I/O cable to IO_SLOT3(J116) - |Mezzanine:X-M4-PCIE-SGMII (29733) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) - |Connect I/O cable to IO_SLOT4(J119) ------------------------------------------------------------------------- -5 |Mezzanine:X-M4-PCIE-SGMII (29733) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) - |Connect I/O cable to IO_SLOT3(J116) - |Mezzanine:X-M5-SATA (29687) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) - |Connect I/O cable to IO_SLOT4(J119) ------------------------------------------------------------------------- -11 |Mezzanine:X-M4-PCIE-SGMII (29733) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) - |Connect I/O cable to IO_SLOT7(J127) - |Mezzanine:X-M4-PCIE-SGMII (29733) - |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) - |Connect I/O cable to IO_SLOT8(J131) ------------------------------------------------------------------------- diff --git a/board/freescale/lx2160a/ddr.c b/board/freescale/lx2160a/ddr.c deleted file mode 100644 index 637e43a22be..00000000000 --- a/board/freescale/lx2160a/ddr.c +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 NXP - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int fsl_initdram(void) -{ - gd->ram_size = tfa_get_dram_size(); - - if (!gd->ram_size) - gd->ram_size = fsl_ddr_sdram_size(); - - return 0; -} diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c deleted file mode 100644 index 9939bb6f89e..00000000000 --- a/board/freescale/lx2160a/eth_lx2160aqds.c +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018-2020 NXP - * - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_PHY_AQUANTIA - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - - return 0; -} - -#if defined(CONFIG_RESET_PHY_R) -void reset_phy(void) -{ -#if defined(CONFIG_FSL_MC_ENET) - mc_env_boot(); -#endif -} -#endif /* CONFIG_RESET_PHY_R */ - -#if defined(CONFIG_MULTI_DTB_FIT) - -/* Structure to hold SERDES protocols supported (network interfaces are - * described in the DTS). - * - * @serdes_block: the index of the SERDES block - * @serdes_protocol: the decimal value of the protocol supported - * @dts_needed: DTS notes describing the current configuration are needed - * - * When dts_needed is true, the board_fit_config_name_match() function - * will try to exactly match the current configuration of the block with a DTS - * name provided. - */ -static struct serdes_configuration { - u8 serdes_block; - u32 serdes_protocol; - bool dts_needed; -} supported_protocols[] = { - /* Serdes block #1 */ - {1, 3, true}, - {1, 7, true}, - {1, 19, true}, - {1, 20, true}, - - /* Serdes block #2 */ - {2, 2, false}, - {2, 3, false}, - {2, 5, false}, - {2, 11, true}, - - /* Serdes block #3 */ - {3, 2, false}, - {3, 3, false}, -}; - -#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) - -static bool protocol_supported(u8 serdes_block, u32 protocol) -{ - struct serdes_configuration serdes_conf; - int i; - - for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { - serdes_conf = supported_protocols[i]; - if (serdes_conf.serdes_block == serdes_block && - serdes_conf.serdes_protocol == protocol) - return true; - } - - return false; -} - -static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) -{ - struct serdes_configuration serdes_conf; - int i; - - for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { - serdes_conf = supported_protocols[i]; - if (serdes_conf.serdes_block == serdes_block && - serdes_conf.serdes_protocol == protocol) { - if (serdes_conf.dts_needed == true) - sprintf(str, "%u", protocol); - else - sprintf(str, "x"); - return; - } - } -} - -int board_fit_config_name_match(const char *name) -{ - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 rcw_status = in_le32(&gur->rcwsr[28]); - char srds_s1_str[2], srds_s2_str[2], srds_s3_str[2]; - u32 srds_s1, srds_s2, srds_s3; - char expected_dts[100]; - - srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; - - srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; - srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; - - srds_s3 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK; - srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT; - - /* Check for supported protocols. The default DTS will be used - * in this case - */ - if (!protocol_supported(1, srds_s1) || - !protocol_supported(2, srds_s2) || - !protocol_supported(3, srds_s3)) - return -1; - - get_str_protocol(1, srds_s1, srds_s1_str); - get_str_protocol(2, srds_s2, srds_s2_str); - get_str_protocol(3, srds_s3, srds_s3_str); - - sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s-%s", - srds_s1_str, srds_s2_str, srds_s3_str); - - if (!strcmp(name, expected_dts)) - return 0; - - return -1; -} -#endif diff --git a/board/freescale/lx2160a/eth_lx2160ardb.c b/board/freescale/lx2160a/eth_lx2160ardb.c deleted file mode 100644 index 90e7c9100e1..00000000000 --- a/board/freescale/lx2160a/eth_lx2160ardb.c +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018, 2020 NXP - * - */ - -#include -#include -#include -#include "lx2160a.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_PHY_AQUANTIA - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - return pci_eth_init(bis); -} - -#if defined(CONFIG_RESET_PHY_R) -void reset_phy(void) -{ -#if defined(CONFIG_FSL_MC_ENET) - mc_env_boot(); -#endif -} -#endif /* CONFIG_RESET_PHY_R */ - -static int fdt_get_dpmac_node(void *fdt, int dpmac_id) -{ - char dpmac_str[11] = "dpmacs@00"; - int offset, dpmacs_offset; - - /* get the dpmac offset */ - dpmacs_offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs"); - if (dpmacs_offset < 0) - dpmacs_offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs"); - - if (dpmacs_offset < 0) { - printf("dpmacs node not found in device tree\n"); - return dpmacs_offset; - } - - sprintf(dpmac_str, "dpmac@%x", dpmac_id); - offset = fdt_subnode_offset(fdt, dpmacs_offset, dpmac_str); - if (offset < 0) { - sprintf(dpmac_str, "ethernet@%x", dpmac_id); - offset = fdt_subnode_offset(fdt, dpmacs_offset, dpmac_str); - if (offset < 0) { - printf("dpmac@%x/ethernet@%x node not found in device tree\n", - dpmac_id, dpmac_id); - return offset; - } - } - - return offset; -} - -static int fdt_update_phy_addr(void *fdt, int dpmac_id, int phy_addr) -{ - char dpmac_str[] = "dpmacs@00"; - const u32 *phyhandle; - int offset; - int err; - - /* get the dpmac offset */ - offset = fdt_get_dpmac_node(fdt, dpmac_id); - if (offset < 0) - return offset; - - /* get dpmac phy-handle */ - sprintf(dpmac_str, "dpmac@%x", dpmac_id); - phyhandle = (u32 *)fdt_getprop(fdt, offset, "phy-handle", NULL); - if (!phyhandle) { - printf("%s node not found in device tree\n", dpmac_str); - return offset; - } - - offset = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*phyhandle)); - if (offset < 0) { - printf("Could not get the ph node offset for dpmac %d\n", - dpmac_id); - return offset; - } - - phy_addr = cpu_to_fdt32(phy_addr); - err = fdt_setprop(fdt, offset, "reg", &phy_addr, sizeof(phy_addr)); - if (err < 0) { - printf("Could not set phy node's reg for dpmac %d: %s.\n", - dpmac_id, fdt_strerror(err)); - return err; - } - - return 0; -} - -static int fdt_delete_phy_handle(void *fdt, int dpmac_id) -{ - const u32 *phyhandle; - int offset; - - /* get the dpmac offset */ - offset = fdt_get_dpmac_node(fdt, dpmac_id); - if (offset < 0) - return offset; - - /* verify if the node has a phy-handle */ - phyhandle = (u32 *)fdt_getprop(fdt, offset, "phy-handle", NULL); - if (!phyhandle) - return 0; - - return fdt_delprop(fdt, offset, "phy-handle"); -} - -int fdt_fixup_board_phy_revc(void *fdt) -{ - int ret; - - if (get_board_rev() < 'C') - return 0; - - /* DPMACs 3,4 have their Aquantia PHYs at new addresses */ - ret = fdt_update_phy_addr(fdt, 3, AQR113C_PHY_ADDR1); - if (ret) - return ret; - - ret = fdt_update_phy_addr(fdt, 4, AQR113C_PHY_ADDR2); - if (ret) - return ret; - - /* There is no PHY for the DPMAC2, so remove the phy-handle */ - return fdt_delete_phy_handle(fdt, 2); -} diff --git a/board/freescale/lx2160a/eth_lx2162aqds.c b/board/freescale/lx2160a/eth_lx2162aqds.c deleted file mode 100644 index 805aa705be9..00000000000 --- a/board/freescale/lx2160a/eth_lx2162aqds.c +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2020 NXP - * - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_PHY_AQUANTIA - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - - return 0; -} - -#if defined(CONFIG_RESET_PHY_R) -void reset_phy(void) -{ -#if defined(CONFIG_FSL_MC_ENET) - mc_env_boot(); -#endif -} -#endif /* CONFIG_RESET_PHY_R */ - -#if defined(CONFIG_MULTI_DTB_FIT) - -/* Structure to hold SERDES protocols supported (network interfaces are - * described in the DTS). - * - * @serdes_block: the index of the SERDES block - * @serdes_protocol: the decimal value of the protocol supported - * @dts_needed: DTS notes describing the current configuration are needed - * - * When dts_needed is true, the board_fit_config_name_match() function - * will try to exactly match the current configuration of the block with a DTS - * name provided. - */ -static struct serdes_configuration { - u8 serdes_block; - u32 serdes_protocol; - bool dts_needed; -} supported_protocols[] = { - /* Serdes block #1 */ - {1, 2, true}, - {1, 3, true}, - {1, 15, true}, - {1, 17, true}, - {1, 18, true}, - {1, 20, true}, - - /* Serdes block #2 */ - {2, 2, false}, - {2, 3, false}, - {2, 5, false}, - {2, 10, false}, - {2, 11, true}, - {2, 12, true}, -}; - -#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) - -static bool protocol_supported(u8 serdes_block, u32 protocol) -{ - struct serdes_configuration serdes_conf; - int i; - - for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { - serdes_conf = supported_protocols[i]; - if (serdes_conf.serdes_block == serdes_block && - serdes_conf.serdes_protocol == protocol) - return true; - } - - return false; -} - -static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) -{ - struct serdes_configuration serdes_conf; - int i; - - for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { - serdes_conf = supported_protocols[i]; - if (serdes_conf.serdes_block == serdes_block && - serdes_conf.serdes_protocol == protocol) { - if (serdes_conf.dts_needed == true) - sprintf(str, "%u", protocol); - else - sprintf(str, "x"); - return; - } - } -} - -int board_fit_config_name_match(const char *name) -{ - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 rcw_status = in_le32(&gur->rcwsr[28]); - char srds_s1_str[2], srds_s2_str[2]; - u32 srds_s1, srds_s2; - char expected_dts[100]; - - srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; - - srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; - srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; - - /* Check for supported protocols. The default DTS will be used - * in this case - */ - if (!protocol_supported(1, srds_s1) || - !protocol_supported(2, srds_s2)) - return -1; - - get_str_protocol(1, srds_s1, srds_s1_str); - get_str_protocol(2, srds_s2, srds_s2_str); - - sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s", - srds_s1_str, srds_s2_str); - - if (!strcmp(name, expected_dts)) - return 0; - - return -1; -} -#endif diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c deleted file mode 100644 index 341f82ce724..00000000000 --- a/board/freescale/lx2160a/lx2160a.c +++ /dev/null @@ -1,864 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018-2021 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/i2c_mux.h" - -#include "../common/qixis.h" -#include "../common/vid.h" -#include -#include -#include "lx2160a.h" - -#ifdef CONFIG_EMC2305 -#include "../common/emc2305.h" -#endif - -#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) -#define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value) -#define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f) -#define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value) -#define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value) -#define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value) -#define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value) -#define SDHC1_BASE_PMUX_DSPI 2 -#define SDHC2_BASE_PMUX_DSPI 2 -#define IIC5_PMUX_SPI3 3 -#endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */ - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ -#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_XPL_BUILD) - i2c_early_init_f(); -#endif - -#ifdef CONFIG_EMC2305 - select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305, 0); - emc2305_init(I2C_EMC2305_ADDR); - set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); -#endif - - fsl_lsch3_early_init_f(); - return 0; -} - -#ifdef CONFIG_OF_BOARD_FIXUP -int board_fix_fdt(void *fdt) -{ - char *reg_names, *reg_name; - int names_len, old_name_len, new_name_len, remaining_names_len; - struct str_map { - char *old_str; - char *new_str; - } reg_names_map[] = { - { "ccsr", "dbi" }, - { "pf_ctrl", "ctrl" } - }; - int off = -1, i = 0; - - if (IS_SVR_REV(get_svr(), 1, 0)) - return 0; - - fdt_for_each_node_by_compatible(off, fdt, -1, "fsl,lx2160a-pcie") { - fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie", - strlen("fsl,ls-pcie") + 1); - - reg_names = (char *)fdt_getprop(fdt, off, "reg-names", - &names_len); - if (!reg_names) - continue; - - reg_name = reg_names; - remaining_names_len = names_len - (reg_name - reg_names); - i = 0; - while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) { - old_name_len = strlen(reg_names_map[i].old_str); - new_name_len = strlen(reg_names_map[i].new_str); - if (memcmp(reg_name, reg_names_map[i].old_str, - old_name_len) == 0) { - /* first only leave required bytes for new_str - * and copy rest of the string after it - */ - memcpy(reg_name + new_name_len, - reg_name + old_name_len, - remaining_names_len - old_name_len); - /* Now copy new_str */ - memcpy(reg_name, reg_names_map[i].new_str, - new_name_len); - names_len -= old_name_len; - names_len += new_name_len; - i++; - } - - reg_name = memchr(reg_name, '\0', remaining_names_len); - if (!reg_name) - break; - - reg_name += 1; - - remaining_names_len = names_len - - (reg_name - reg_names); - } - - fdt_setprop(fdt, off, "reg-names", reg_names, names_len); - } - - /* Fixup u-boot's DTS in case this is a revC board and - * we're using DM_ETH. - */ - if (IS_ENABLED(CONFIG_TARGET_LX2160ARDB) && IS_ENABLED(CONFIG_DM_ETH)) - fdt_fixup_board_phy_revc(fdt); - return 0; -} -#endif - -#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) -void esdhc_dspi_status_fixup(void *blob) -{ - const char esdhc0_path[] = "/soc/esdhc@2140000"; - const char esdhc1_path[] = "/soc/esdhc@2150000"; - const char dspi0_path[] = "/soc/spi@2100000"; - const char dspi1_path[] = "/soc/spi@2110000"; - const char dspi2_path[] = "/soc/spi@2120000"; - - struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 sdhc1_base_pmux; - u32 sdhc2_base_pmux; - u32 iic5_pmux; - - /* Check RCW field sdhc1_base_pmux to enable/disable - * esdhc0/dspi0 DT node - */ - sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) - & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK; - sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT; - - if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) { - do_fixup_by_path(blob, dspi0_path, "status", "okay", - sizeof("okay"), 1); - do_fixup_by_path(blob, esdhc0_path, "status", "disabled", - sizeof("disabled"), 1); - } else { - do_fixup_by_path(blob, esdhc0_path, "status", "okay", - sizeof("okay"), 1); - do_fixup_by_path(blob, dspi0_path, "status", "disabled", - sizeof("disabled"), 1); - } - - /* Check RCW field sdhc2_base_pmux to enable/disable - * esdhc1/dspi1 DT node - */ - sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1]) - & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK; - sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT; - - if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) { - do_fixup_by_path(blob, dspi1_path, "status", "okay", - sizeof("okay"), 1); - do_fixup_by_path(blob, esdhc1_path, "status", "disabled", - sizeof("disabled"), 1); - } else { - do_fixup_by_path(blob, esdhc1_path, "status", "okay", - sizeof("okay"), 1); - do_fixup_by_path(blob, dspi1_path, "status", "disabled", - sizeof("disabled"), 1); - } - - /* Check RCW field IIC5 to enable dspi2 DT node */ - iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) - & FSL_CHASSIS3_IIC5_PMUX_MASK; - iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT; - - if (iic5_pmux == IIC5_PMUX_SPI3) - do_fixup_by_path(blob, dspi2_path, "status", "okay", - sizeof("okay"), 1); - else - do_fixup_by_path(blob, dspi2_path, "status", "disabled", - sizeof("disabled"), 1); -} -#endif - -int esdhc_status_fixup(void *blob, const char *compat) -{ -#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) - /* Enable esdhc and dspi DT nodes based on RCW fields */ - esdhc_dspi_status_fixup(blob); -#else - /* Enable both esdhc DT nodes for LX2160ARDB */ - do_fixup_by_compat(blob, compat, "status", "okay", - sizeof("okay"), 1); -#endif - return 0; -} - -#if defined(CONFIG_VID) -int i2c_multiplexer_select_vid_channel(u8 channel) -{ - return select_i2c_ch_pca9547(channel, 0); -} - -int init_func_vid(void) -{ - int set_vid; - - if (IS_SVR_REV(get_svr(), 1, 0)) - set_vid = adjust_vdd(800); - else - set_vid = adjust_vdd(0); - - if (set_vid < 0) - printf("core voltage not adjusted\n"); - - return 0; -} -#endif -EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, init_func_vid); - -int checkboard(void) -{ - enum boot_src src = get_boot_src(); - char buf[64]; - u8 sw; -#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) - int clock; - static const char *const freq[] = {"100", "125", "156.25", - "161.13", "322.26", "", "", "", - "", "", "", "", "", "", "", - "100 separate SSCG"}; -#endif - - cpu_name(buf); -#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) - printf("Board: %s-QDS, ", buf); -#else - printf("Board: %s-RDB, ", buf); -#endif - - sw = QIXIS_READ(arch); - printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A'); - - if (src == BOOT_SOURCE_SD_MMC) { - puts("SD\n"); - } else if (src == BOOT_SOURCE_SD_MMC2) { - puts("eMMC\n"); - } else { - sw = QIXIS_READ(brdcfg[0]); - sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK; - switch (sw) { - case 0: - case 4: - puts("FlexSPI DEV#0\n"); - break; - case 1: - puts("FlexSPI DEV#1\n"); - break; - case 2: - case 3: - puts("FlexSPI EMU\n"); - break; - default: - printf("invalid setting, xmap: %d\n", sw); - break; - } - } -#if defined(CONFIG_TARGET_LX2160ARDB) - printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); - - puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n"); - puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); - puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); -#else - printf("FPGA: v%d (%s), build %d", - (int)QIXIS_READ(scver), qixis_read_tag(buf), - (int)qixis_read_minor()); - /* the timestamp string contains "\n" at the end */ - printf(" on %s", qixis_read_time(buf)); - - puts("SERDES1 Reference : "); - sw = QIXIS_READ(brdcfg[2]); - clock = sw >> 4; - printf("Clock1 = %sMHz ", freq[clock]); -#if defined(CONFIG_TARGET_LX2160AQDS) - clock = sw & 0x0f; - printf("Clock2 = %sMHz", freq[clock]); -#endif - sw = QIXIS_READ(brdcfg[3]); - puts("\nSERDES2 Reference : "); - clock = sw >> 4; - printf("Clock1 = %sMHz ", freq[clock]); - clock = sw & 0x0f; - printf("Clock2 = %sMHz\n", freq[clock]); -#if defined(CONFIG_TARGET_LX2160AQDS) - sw = QIXIS_READ(brdcfg[12]); - puts("SERDES3 Reference : "); - clock = sw >> 4; - printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]); -#endif -#endif - return 0; -} - -#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) -static void esdhc_adapter_card_ident(void) -{ - u8 card_id, val; - - val = QIXIS_READ(sdhc1); - card_id = val & QIXIS_SDID_MASK; - - switch (card_id) { - case QIXIS_ESDHC_ADAPTER_TYPE_SD: - /* Power cycle to card */ - val &= ~QIXIS_SDHC1_S1V3; - QIXIS_WRITE(sdhc1, val); - mdelay(1); - val |= QIXIS_SDHC1_S1V3; - QIXIS_WRITE(sdhc1, val); - /* Route to SDHC1_VS */ - val = QIXIS_READ(brdcfg[11]); - val |= QIXIS_SDHC1_VS; - QIXIS_WRITE(brdcfg[11], val); - break; - default: - break; - } -} - -int config_board_mux(void) -{ - u8 reg11, reg5, reg13; - struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 sdhc1_base_pmux; - u32 sdhc2_base_pmux; - u32 iic5_pmux; - - /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}. - * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}. - * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}. - * Qixis and remote systems are isolated from the I2C1 bus. - * Processor connections are still available. - * SPI2 CS2_B controls EN25S64 SPI memory device. - * SPI3 CS2_B controls EN25S64 SPI memory device. - * EC2 connects to PHY #2 using RGMII protocol. - * CLK_OUT connects to FPGA for clock measurement. - */ - - reg5 = QIXIS_READ(brdcfg[5]); - reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40); - QIXIS_WRITE(brdcfg[5], reg5); - - /* Check RCW field sdhc1_base_pmux - * esdhc0 : sdhc1_base_pmux = 0 - * dspi0 : sdhc1_base_pmux = 2 - */ - sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) - & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK; - sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT; - - if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) { - reg11 = QIXIS_READ(brdcfg[11]); - reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40); - QIXIS_WRITE(brdcfg[11], reg11); - } else { - /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot. - * {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot. - * {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot. - */ - reg11 = QIXIS_READ(brdcfg[11]); - reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11); - QIXIS_WRITE(brdcfg[11], reg11); - } - - /* Check RCW field sdhc2_base_pmux - * esdhc1 : sdhc2_base_pmux = 0 (default) - * dspi1 : sdhc2_base_pmux = 2 - */ - sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1]) - & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK; - sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT; - - if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) { - reg13 = QIXIS_READ(brdcfg[13]); - reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01); - QIXIS_WRITE(brdcfg[13], reg13); - } else { - reg13 = QIXIS_READ(brdcfg[13]); - reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00); - QIXIS_WRITE(brdcfg[13], reg13); - } - - /* Check RCW field IIC5 to enable dspi2 DT nodei - * dspi2: IIC5 = 3 - */ - iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) - & FSL_CHASSIS3_IIC5_PMUX_MASK; - iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT; - - if (iic5_pmux == IIC5_PMUX_SPI3) { - /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */ - reg11 = QIXIS_READ(brdcfg[11]); - reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10); - QIXIS_WRITE(brdcfg[11], reg11); - - /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere. - * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }. - * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}. - */ - reg11 = QIXIS_READ(brdcfg[11]); - reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01); - QIXIS_WRITE(brdcfg[11], reg11); - } else { - /* - * If {SDHC1_DAT4} has been configured to route to SDHC1_VS, - * do not change it. - * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot. - */ - reg11 = QIXIS_READ(brdcfg[11]); - if ((reg11 & 0x30) != 0x30) { - reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00); - QIXIS_WRITE(brdcfg[11], reg11); - } - - /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot. - * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot. - * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot. - */ - reg11 = QIXIS_READ(brdcfg[11]); - reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00); - QIXIS_WRITE(brdcfg[11], reg11); - } - - return 0; -} - -int board_early_init_r(void) -{ - esdhc_adapter_card_ident(); - return 0; -} -#elif defined(CONFIG_TARGET_LX2160ARDB) -int config_board_mux(void) -{ - u8 brdcfg; - - brdcfg = QIXIS_READ(brdcfg[4]); - /* The BRDCFG4 register controls general board configuration. - *|-------------------------------------------| - *|Field | Function | - *|-------------------------------------------| - *|5 | CAN I/O Enable (net CFG_CAN_EN_B):| - *|CAN_EN | 0= CAN transceivers are disabled. | - *| | 1= CAN transceivers are enabled. | - *|-------------------------------------------| - */ - brdcfg |= BIT_MASK(5); - QIXIS_WRITE(brdcfg[4], brdcfg); - - return 0; -} -#else -int config_board_mux(void) -{ - return 0; -} -#endif - -#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB) -u8 get_board_rev(void) -{ - u8 board_rev = (QIXIS_READ(arch) & 0xf) - 1 + 'A'; - - return board_rev; -} -#endif - -unsigned long get_board_sys_clk(void) -{ -#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); - - switch (sysclk_conf & 0x03) { - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - } - return 100000000; -#else - return 100000000; -#endif -} - -unsigned long get_board_ddr_clk(void) -{ -#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); - - switch ((ddrclk_conf & 0x30) >> 4) { - case QIXIS_DDRCLK_100: - return 100000000; - case QIXIS_DDRCLK_125: - return 125000000; - case QIXIS_DDRCLK_133: - return 133333333; - } - return 100000000; -#else - return 100000000; -#endif -} - -int board_init(void) -{ -#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB) - u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; -#endif - - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - -#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB) - /* invert AQR107 IRQ pins polarity */ - out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK); -#endif - -#if !defined(CONFIG_SYS_EARLY_PCI_INIT) - pci_init(); -#endif - return 0; -} - -void detail_board_ddr_info(void) -{ - int i; - u64 ddr_size = 0; - - puts("\nDDR "); - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - ddr_size += gd->bd->bi_dram[i].size; - print_size(ddr_size, ""); - print_ddr_info(0); -} - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ - config_board_mux(); - - return 0; -} -#endif - -#ifdef CONFIG_VID -u16 soc_get_fuse_vid(int vid_index) -{ - static const u16 vdd[32] = { - 8250, - 7875, - 7750, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 8000, - 8125, - 8250, - 0, /* reserved */ - 8500, - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - 0, /* reserved */ - }; - - return vdd[vid_index]; -}; -#endif - -#ifdef CONFIG_FSL_MC_ENET - -void fdt_fixup_board_enet(void *fdt) -{ - int offset; - - offset = fdt_path_offset(fdt, "/soc/fsl-mc"); - - if (offset < 0) - offset = fdt_path_offset(fdt, "/fsl-mc"); - - if (offset < 0) { - printf("%s: fsl-mc node not found in device tree (error %d)\n", - __func__, offset); - return; - } - - if (get_mc_boot_status() == 0 && - (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) { - fdt_status_okay(fdt, offset); - if (IS_ENABLED(CONFIG_TARGET_LX2160ARDB)) - fdt_fixup_board_phy_revc(fdt); - } else { - fdt_status_fail(fdt, offset); - } -} - -void board_quiesce_devices(void) -{ - fsl_mc_ldpaa_exit(gd->bd); -} -#endif - -#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB) -int fdt_fixup_add_thermal(void *blob, int mux_node, int channel, int reg) -{ - int err; - int noff; - int offset; - char channel_node_name[50]; - char thermal_node_name[50]; - u32 phandle; - - snprintf(channel_node_name, sizeof(channel_node_name), - "i2c@%x", channel); - debug("channel_node_name = %s\n", channel_node_name); - - snprintf(thermal_node_name, sizeof(thermal_node_name), - "temperature-sensor@%x", reg); - debug("thermal_node_name = %s\n", thermal_node_name); - - err = fdt_increase_size(blob, 200); - if (err) { - printf("fdt_increase_size: err=%s\n", fdt_strerror(err)); - return err; - } - - noff = fdt_subnode_offset(blob, mux_node, (const char *) - channel_node_name); - if (noff < 0) { - /* channel node not found - create it */ - noff = fdt_add_subnode(blob, mux_node, channel_node_name); - if (noff < 0) { - printf("fdt_add_subnode: err=%s\n", fdt_strerror(err)); - return err; - } - fdt_setprop_u32 (blob, noff, "#address-cells", 1); - fdt_setprop_u32 (blob, noff, "#size-cells", 0); - fdt_setprop_u32 (blob, noff, "reg", channel); - } - - /* Create thermal node*/ - offset = fdt_add_subnode(blob, noff, thermal_node_name); - fdt_setprop(blob, offset, "compatible", "nxp,sa56004", - strlen("nxp,sa56004") + 1); - fdt_setprop_u32 (blob, offset, "reg", reg); - - /* fixup phandle*/ - noff = fdt_node_offset_by_compatible(blob, -1, "regulator-fixed"); - if (noff < 0) { - printf("%s : failed to get phandle\n", __func__); - return noff; - } - phandle = fdt_get_phandle(blob, noff); - fdt_setprop_u32 (blob, offset, "vcc-supply", phandle); - - return 0; -} - -void fdt_fixup_delete_thermal(void *blob, int mux_node, int channel, int reg) -{ - int node; - int value; - int err; - int subnode; - - fdt_for_each_subnode(subnode, blob, mux_node) { - value = fdtdec_get_uint(blob, subnode, "reg", -1); - if (value == channel) { - /* delete thermal node */ - fdt_for_each_subnode(node, blob, subnode) { - value = fdtdec_get_uint(blob, node, "reg", -1); - err = fdt_node_check_compatible(blob, node, - "nxp,sa56004"); - if (!err && value == reg) { - fdt_del_node(blob, node); - break; - } - } - } - } -} - -void fdt_fixup_i2c_thermal_node(void *blob) -{ - int i2coffset; - int mux_node; - int reg; - int err; - - i2coffset = fdt_node_offset_by_compat_reg(blob, "fsl,vf610-i2c", - 0x2000000); - if (i2coffset != -FDT_ERR_NOTFOUND) { - fdt_for_each_subnode(mux_node, blob, i2coffset) { - reg = fdtdec_get_uint(blob, mux_node, "reg", -1); - err = fdt_node_check_compatible(blob, mux_node, - "nxp,pca9547"); - if (!err && reg == 0x77) { - fdt_fixup_delete_thermal(blob, mux_node, - 0x3, 0x4d); - err = fdt_fixup_add_thermal(blob, mux_node, - 0x3, 0x48); - if (err) - printf("%s: Add thermal node failed\n", - __func__); - } - } - } else { - printf("%s: i2c node not found\n", __func__); - } -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - int i; - u16 mc_memory_bank = 0; - - u64 *base; - u64 *size; - u64 mc_memory_base = 0; - u64 mc_memory_size = 0; - u16 total_memory_banks; - int err; - - err = fdt_increase_size(blob, 512); - if (err) { - printf("%s fdt_increase_size: err=%s\n", __func__, - fdt_strerror(err)); - return err; - } - - ft_cpu_setup(blob, bd); - - fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); - - if (mc_memory_base != 0) - mc_memory_bank++; - - total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; - - base = calloc(total_memory_banks, sizeof(u64)); - size = calloc(total_memory_banks, sizeof(u64)); - - /* fixup DT for the three GPP DDR banks */ - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; - } - -#ifdef CONFIG_RESV_RAM - /* reduce size if reserved memory is within this bank */ - if (gd->arch.resv_ram >= base[0] && - gd->arch.resv_ram < base[0] + size[0]) - size[0] = gd->arch.resv_ram - base[0]; - else if (gd->arch.resv_ram >= base[1] && - gd->arch.resv_ram < base[1] + size[1]) - size[1] = gd->arch.resv_ram - base[1]; - else if (gd->arch.resv_ram >= base[2] && - gd->arch.resv_ram < base[2] + size[2]) - size[2] = gd->arch.resv_ram - base[2]; -#endif - - if (mc_memory_base != 0) { - for (i = 0; i <= total_memory_banks; i++) { - if (base[i] == 0 && size[i] == 0) { - base[i] = mc_memory_base; - size[i] = mc_memory_size; - break; - } - } - } - - fdt_fixup_memory_banks(blob, base, size, total_memory_banks); - -#ifdef CONFIG_USB_HOST - fsl_fdt_fixup_dr_usb(blob, bd); -#endif - -#ifdef CONFIG_FSL_MC_ENET - fdt_fsl_mc_fixup_iommu_map_entry(blob); - fdt_fixup_board_enet(blob); - fdt_reserve_mc_mem(blob, 0x4000); -#endif - fdt_fixup_icid(blob); - -#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB) - if (get_board_rev() == 'C') - fdt_fixup_i2c_thermal_node(blob); -#endif - - return 0; -} -#endif - -void qixis_dump_switch(void) -{ - int i, nr_of_cfgsw; - - QIXIS_WRITE(cms[0], 0x00); - nr_of_cfgsw = QIXIS_READ(cms[1]); - - puts("DIP switch settings dump:\n"); - for (i = 1; i <= nr_of_cfgsw; i++) { - QIXIS_WRITE(cms[0], i); - printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); - } -} diff --git a/board/freescale/lx2160a/lx2160a.h b/board/freescale/lx2160a/lx2160a.h deleted file mode 100644 index 61a8bb95906..00000000000 --- a/board/freescale/lx2160a/lx2160a.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2020 NXP - */ - -#ifndef __LX2160_H -#define __LX2160_H - -#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) -/* SYSCLK */ -#define QIXIS_SYSCLK_100 0x0 -#define QIXIS_SYSCLK_125 0x1 -#define QIXIS_SYSCLK_133 0x2 - -/* DDRCLK */ -#define QIXIS_DDRCLK_100 0x0 -#define QIXIS_DDRCLK_125 0x1 -#define QIXIS_DDRCLK_133 0x2 - -#define BRDCFG4_EMI1SEL_MASK 0xF8 -#define BRDCFG4_EMI1SEL_SHIFT 3 -#define BRDCFG4_EMI2SEL_MASK 0x07 -#define BRDCFG4_EMI2SEL_SHIFT 0 -#endif - -#define QIXIS_XMAP_SHIFT 5 - -/* RTC */ -#define I2C_MUX_CH_RTC 0xB - -/* MAC/PHY configuration */ -#if defined(CONFIG_FSL_MC_ENET) -#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) -#define AQ_PHY_ADDR1 0x00 -#define AQ_PHY_ADDR2 0x01 -#define AQ_PHY_ADDR3 0x02 -#define AQ_PHY_ADDR4 0x03 -#endif - -#ifdef CONFIG_TARGET_LX2160ARDB -#define AQR107_PHY_ADDR1 0x04 -#define AQR107_PHY_ADDR2 0x05 -#define AQR107_IRQ_MASK 0x0C -#endif - -#define CORTINA_PHY_ADDR1 0x0 -#define INPHI_PHY_ADDR1 0x0 - -#define RGMII_PHY_ADDR1 0x01 -#define RGMII_PHY_ADDR2 0x02 - -#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) -#define INPHI_PHY_ADDR2 0x1 -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F -#endif -#endif - -#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB) -u8 get_board_rev(void); -int fdt_fixup_board_phy_revc(void *fdt); -#else -static inline u8 get_board_rev(void) -{ - return 0; -} - -static inline int fdt_fixup_board_phy_revc(void *fdt) -{ - return 0; -} -#endif - -#endif /* __LX2160_H */ diff --git a/board/freescale/m5208evbe/Kconfig b/board/freescale/m5208evbe/Kconfig deleted file mode 100644 index 9b416afbdc7..00000000000 --- a/board/freescale/m5208evbe/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M5208EVBE - -config SYS_CPU - default "mcf52x2" - -config SYS_BOARD - default "m5208evbe" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "M5208EVBE" - -endif diff --git a/board/freescale/m5208evbe/MAINTAINERS b/board/freescale/m5208evbe/MAINTAINERS deleted file mode 100644 index ff153034a4f..00000000000 --- a/board/freescale/m5208evbe/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -M5208EVBE BOARD -M: Angelo Dureghello -S: Maintained -F: board/freescale/m5208evbe/ -F: include/configs/M5208EVBE.h -F: configs/M5208EVBE_defconfig diff --git a/board/freescale/m5208evbe/Makefile b/board/freescale/m5208evbe/Makefile deleted file mode 100644 index b7a7c3e6471..00000000000 --- a/board/freescale/m5208evbe/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = m5208evbe.o diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c deleted file mode 100644 index b202b8094d9..00000000000 --- a/board/freescale/m5208evbe/m5208evbe.c +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("Board: "); - puts("Freescale M5208EVBe\n"); - return 0; -}; - -int dram_init(void) -{ - sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); - u32 dramsize, i; - - dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; - - for (i = 0x13; i < 0x20; i++) { - if (dramsize == (1 << i)) - break; - } - i--; - - out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); -#ifdef CFG_SYS_SDRAM_BASE1 - out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i); -#endif - out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); - out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2); - - udelay(500); - - /* Issue PALL */ - out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); - asm("nop"); - - /* Perform two refresh cycles */ - out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); - asm("nop"); - - /* Issue LEMR */ - out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE); - asm("nop"); - out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); - asm("nop"); - - out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); - asm("nop"); - - out_be32(&sdram->ctrl, - (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00); - asm("nop"); - - udelay(100); - - gd->ram_size = dramsize; - - return 0; -}; - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/freescale/m5235evb/Kconfig b/board/freescale/m5235evb/Kconfig deleted file mode 100644 index f0d4c8c7964..00000000000 --- a/board/freescale/m5235evb/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -if TARGET_M5235EVB - -config SYS_CPU - default "mcf523x" - -config SYS_BOARD - default "m5235evb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "M5235EVB" - -config NORFLASH_PS32BIT - bool "Board has 32bit CFI flash" - -endif diff --git a/board/freescale/m5235evb/MAINTAINERS b/board/freescale/m5235evb/MAINTAINERS deleted file mode 100644 index b15ac5f14ab..00000000000 --- a/board/freescale/m5235evb/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -M5235EVB BOARD -M: TsiChung Liew -S: Maintained -F: board/freescale/m5235evb/ -F: include/configs/M5235EVB.h -F: configs/M5235EVB_defconfig -F: configs/M5235EVB_Flash32_defconfig diff --git a/board/freescale/m5235evb/Makefile b/board/freescale/m5235evb/Makefile deleted file mode 100644 index b7067e4581b..00000000000 --- a/board/freescale/m5235evb/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = m5235evb.o diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c deleted file mode 100644 index 65cde56fb2d..00000000000 --- a/board/freescale/m5235evb/m5235evb.c +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("Board: "); - puts("Freescale M5235 EVB\n"); - return 0; -}; - -int dram_init(void) -{ - sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); - gpio_t *gpio = (gpio_t *)(MMAP_GPIO); - u32 dramsize, i, dramclk; - - /* - * When booting from external Flash, the port-size is less than - * the port-size of SDRAM. In this case it is necessary to enable - * Data[15:0] on Port Address/Data. - */ - out_8(&gpio->par_ad, - GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 | - GPIO_PAR_AD_DATAL); - - /* Initialize PAR to enable SDRAM signals */ - out_8(&gpio->par_sdram, - GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | - GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE | - GPIO_PAR_SDRAM_SDCS(3)); - - dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; - for (i = 0x13; i < 0x20; i++) { - if (dramsize == (1 << i)) - break; - } - i--; - - if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) { - dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ); - - /* Initialize DRAM Control Register: DCR */ - out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS | - SDRAMC_DCR_RTIM_6CLKS | - SDRAMC_DCR_RC((15 * dramclk) >> 4)); - - /* Initialize DACR0 */ - out_be32(&sdram->dacr0, - SDRAMC_DARCn_BA(CFG_SYS_SDRAM_BASE) | - SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 | - SDRAMC_DARCn_PS_32); - asm("nop"); - - /* Initialize DMR0 */ - out_be32(&sdram->dmr0, - ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V); - asm("nop"); - - /* Set IP (bit 3) in DACR */ - setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP); - - /* Wait 30ns to allow banks to precharge */ - for (i = 0; i < 5; i++) { - asm("nop"); - } - - /* Write to this block to initiate precharge */ - *(u32 *) (CFG_SYS_SDRAM_BASE) = 0xA5A59696; - - /* Set RE (bit 15) in DACR */ - setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE); - - /* Wait for at least 8 auto refresh cycles to occur */ - for (i = 0; i < 0x2000; i++) { - asm("nop"); - } - - /* Finish the configuration by issuing the MRS. */ - setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS); - asm("nop"); - - /* Write to the SDRAM Mode Register */ - *(u32 *) (CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; - } - - gd->ram_size = dramsize; - - return 0; -}; - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/freescale/m5249evb/Kconfig b/board/freescale/m5249evb/Kconfig deleted file mode 100644 index 0f624776b55..00000000000 --- a/board/freescale/m5249evb/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M5249EVB - -config SYS_CPU - default "mcf52x2" - -config SYS_BOARD - default "m5249evb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "M5249EVB" - -endif diff --git a/board/freescale/m5249evb/MAINTAINERS b/board/freescale/m5249evb/MAINTAINERS deleted file mode 100644 index 619e0cd20da..00000000000 --- a/board/freescale/m5249evb/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -M5249EVB BOARD -M: Angelo Dureghello -S: Maintained -F: board/freescale/m5249evb/ -F: include/configs/M5249EVB.h -F: configs/M5249EVB_defconfig diff --git a/board/freescale/m5249evb/Makefile b/board/freescale/m5249evb/Makefile deleted file mode 100644 index 497bc722908..00000000000 --- a/board/freescale/m5249evb/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = m5249evb.o diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c deleted file mode 100644 index 68524e5e682..00000000000 --- a/board/freescale/m5249evb/m5249evb.c +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard (void) { - ulong val; - uchar val8; - - puts ("Board: "); - puts("Freescale M5249EVB"); - val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf; - printf(" (Switch=%1X)\n", val8); - - /* - * Set LED on - */ - val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_SYS_GPIO1_LED; - mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */ - - return 0; -}; - -int dram_init(void) -{ - unsigned long junk = 0xa5a59696; - - /* - * Note: - * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1 - */ - -#ifdef CFG_SYS_FAST_CLK - /* - * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K) - * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39 - */ - mbar_writeShort(MCFSIM_DCR, 0x8239); -#elif CFG_SYS_PLL_BYPASS - /* - * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K) - * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02 - */ - mbar_writeShort(MCFSIM_DCR, 0x8202); -#else - /* - * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K) - * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles) - */ - mbar_writeShort(MCFSIM_DCR, 0x8222); -#endif - - /* - * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port), - * PM=1 (continuous page mode) - */ - - /* RE=0 (keep auto-refresh disabled while setting up registers) */ - mbar_writeLong(MCFSIM_DACR0, 0x00003324); - - /* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */ - mbar_writeLong(MCFSIM_DMR0, 0x01fc0001); - - /** Precharge sequence **/ - mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */ - *((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */ - udelay(0x10); /* Allow several Precharge cycles */ - - /** Refresh Sequence **/ - mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */ - udelay(0x7d0); /* Allow gobs of refresh cycles */ - - /** Mode Register initialization **/ - mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ - *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */ - - gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; - - return 0; -}; - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf ("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/freescale/m5253demo/Kconfig b/board/freescale/m5253demo/Kconfig deleted file mode 100644 index 0ecce875d14..00000000000 --- a/board/freescale/m5253demo/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -if TARGET_M5253DEMO - -config FLASH_CFI_LEGACY - depends on SYS_FLASH_CFI - def_bool y - -config SYS_CPU - default "mcf52x2" - -config SYS_BOARD - default "m5253demo" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "M5253DEMO" - -endif diff --git a/board/freescale/m5253demo/MAINTAINERS b/board/freescale/m5253demo/MAINTAINERS deleted file mode 100644 index 9b27f4382ea..00000000000 --- a/board/freescale/m5253demo/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -M5253DEMO BOARD -M: TsiChung Liew -S: Maintained -F: board/freescale/m5253demo/ -F: include/configs/M5253DEMO.h -F: configs/M5253DEMO_defconfig diff --git a/board/freescale/m5253demo/Makefile b/board/freescale/m5253demo/Makefile deleted file mode 100644 index 00d395d1a3c..00000000000 --- a/board/freescale/m5253demo/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = m5253demo.o flash.o diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c deleted file mode 100644 index ab5d2ebff64..00000000000 --- a/board/freescale/m5253demo/flash.c +++ /dev/null @@ -1,440 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include -#include -#include -#include -#include - -#include - -#ifndef CONFIG_SYS_FLASH_CFI -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define FLASH_CYCLE1 0x5555 -#define FLASH_CYCLE2 0x2aaa - -#define SYNC __asm__("nop") - -/*----------------------------------------------------------------------- - * Functions - */ - -ulong flash_get_size(FPWV * addr, flash_info_t * info); -int flash_get_offsets(ulong base, flash_info_t * info); -int write_word(flash_info_t * info, FPWV * dest, u16 data); -static inline void spin_wheel(void); - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -ulong flash_init(void) -{ - ulong size = 0; - ulong fbase = 0; - - fbase = (ulong) CFG_SYS_FLASH_BASE; - flash_get_size((FPWV *) fbase, &flash_info[0]); - flash_get_offsets((ulong) fbase, &flash_info[0]); - fbase += flash_info[0].size; - size += flash_info[0].size; - - /* Protect monitor and environment sectors */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); - - return size; -} - -int flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - - info->start[0] = base; - info->protect[0] = 0; - for (i = 1; i < CFG_SYS_SST_SECT; i++) { - info->start[i] = info->start[i - 1] - + CFG_SYS_SST_SECTSZ; - info->protect[i] = 0; - } - } - - return FL_ERR_OK; -} - -void flash_print_info(flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_SST: - printf("SST "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_SST6401B: - printf("SST39VF6401B\n"); - break; - default: - printf("Unknown Chip Type\n"); - return; - } - - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf("\n"); -} - -/* - * The following code cannot be run from FLASH! - */ -ulong flash_get_size(FPWV * addr, flash_info_t * info) -{ - u16 value; - - addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */ - addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */ - addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */ - - switch (addr[0] & 0xffff) { - case (u8) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - value = addr[1]; - break; - default: - printf("Unknown Flash\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - - *addr = (FPW) 0x00F000F0; - return (0); /* no or unknown flash */ - } - - switch (value) { - case (u16) SST_ID_xF6401B: - info->flash_id += FLASH_SST6401B; - break; - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - info->sector_count = 0; - info->size = 0; - info->sector_count = CFG_SYS_SST_SECT; - info->size = CFG_SYS_SST_SECT * CFG_SYS_SST_SECTSZ; - - /* reset ID mode */ - *addr = (FPWV) 0x00F000F0; - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - return (info->size); -} - -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect, count; - ulong type, start; - int rcode = 0, flashtype = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - - switch (type) { - case FLASH_MAN_SST: - flashtype = 1; - break; - default: - type = (info->flash_id & FLASH_VENDMASK); - printf("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - else - printf("\n"); - - flag = disable_interrupts(); - - start = get_timer(0); - - if ((s_last - s_first) == (CFG_SYS_SST_SECT - 1)) { - if (prot == 0) { - addr = (FPWV *) info->start[0]; - - addr[FLASH_CYCLE1] = 0x00AA; /* unlock */ - addr[FLASH_CYCLE2] = 0x0055; /* unlock */ - addr[FLASH_CYCLE1] = 0x0080; /* erase mode */ - addr[FLASH_CYCLE1] = 0x00AA; /* unlock */ - addr[FLASH_CYCLE2] = 0x0055; /* unlock */ - *addr = 0x0030; /* erase chip */ - - count = 0; - start = get_timer(0); - - while ((*addr & 0x0080) != 0x0080) { - if (count++ > 0x10000) { - spin_wheel(); - count = 0; - } - - /* check timeout, 1000ms */ - if (get_timer(start) > 1000) { - printf("Timeout\n"); - *addr = 0x00F0; /* reset to read mode */ - - return 1; - } - } - - *addr = 0x00F0; /* reset to read mode */ - - printf("\b. done\n"); - - if (flag) - enable_interrupts(); - - return 0; - } else if (prot == CFG_SYS_SST_SECT) { - return 1; - } - } - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - - addr = (FPWV *) (info->start[sect]); - - printf("."); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - switch (flashtype) { - case 1: - { - FPWV *base; /* first address in bank */ - - flag = disable_interrupts(); - - base = (FPWV *) (CFG_SYS_FLASH_BASE); /* First sector */ - - base[FLASH_CYCLE1] = 0x00AA; /* unlock */ - base[FLASH_CYCLE2] = 0x0055; /* unlock */ - base[FLASH_CYCLE1] = 0x0080; /* erase mode */ - base[FLASH_CYCLE1] = 0x00AA; /* unlock */ - base[FLASH_CYCLE2] = 0x0055; /* unlock */ - *addr = 0x0050; /* erase sector */ - - if (flag) - enable_interrupts(); - - while ((*addr & 0x0080) != 0x0080) { - /* check timeout, 1000ms */ - if (get_timer(start) > 1000) { - printf("Timeout\n"); - *addr = 0x00F0; /* reset to read mode */ - - rcode = 1; - break; - } - } - - *addr = 0x00F0; /* reset to read mode */ - break; - } - } /* switch (flashtype) */ - } - } - printf(" done\n"); - - if (flag) - enable_interrupts(); - - return rcode; -} - -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, count; - u16 data; - int rc; - - if (info->flash_id == FLASH_UNKNOWN) - return 4; - - /* get lower word aligned address */ - wp = addr; - - /* handle unaligned start bytes */ - if (wp & 1) { - data = *((FPWV *) wp); - data = (data << 8) | *src; - - if ((rc = write_word(info, (FPWV *) wp, data)) != 0) - return (rc); - - wp++; - cnt -= 1; - src++; - } - - while (cnt >= 2) { - /* - * handle word aligned part - */ - count = 0; - data = *((FPWV *) src); - - if ((rc = write_word(info, (FPWV *) wp, data)) != 0) - return (rc); - - wp += 2; - src += 2; - cnt -= 2; - - if (count++ > 0x800) { - spin_wheel(); - count = 0; - } - } - /* handle word aligned part */ - if (cnt) { - /* handle word aligned part */ - count = 0; - data = *((FPWV *) wp); - - data = (data & 0x00FF) | (*src << 8); - - if ((rc = write_word(info, (FPWV *) wp, data)) != 0) - return (rc); - - wp++; - src++; - cnt -= 1; - if (count++ > 0x800) { - spin_wheel(); - count = 0; - } - } - - if (cnt == 0) - return FL_ERR_OK; - - return FL_ERR_OK; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash - * A word is 16 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_word(flash_info_t * info, FPWV * dest, u16 data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & (u8) data) != (u8) data) { - return (2); - } - - base = (FPWV *) (CFG_SYS_FLASH_BASE); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (u8) 0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* data polling for D7 */ - while (res == 0 - && (*dest & (u8) 0x00800080) != (data & (u8) 0x00800080)) { - /* check timeout, 500ms */ - if (get_timer(start) > 500) { - *dest = (u8) 0x00F000F0; /* reset bank */ - res = 1; - } - } - - *dest++ = (u8) 0x00F000F0; /* reset bank */ - - return (res); -} - -static inline void spin_wheel(void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} - -#endif diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c deleted file mode 100644 index 50c5320b55c..00000000000 --- a/board/freescale/m5253demo/m5253demo.c +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * Hayden Fraser (Hayden.Fraser@freescale.com) - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("Board: "); - puts("Freescale MCF5253 DEMO\n"); - return 0; -}; - -int dram_init(void) -{ - u32 dramsize = 0; - - /* - * Check to see if the SDRAM has already been initialized - * by a run control tool - */ - if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { - u32 RC, temp; - - RC = (CFG_SYS_CLK / 1000000) >> 1; - RC = (RC * 15) >> 4; - - /* Initialize DRAM Control Register: DCR */ - mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); - __asm__("nop"); - - mbar_writeLong(MCFSIM_DACR0, 0x00003224); - __asm__("nop"); - - /* Initialize DMR0 */ - dramsize = (CFG_SYS_SDRAM_SIZE << 20); - temp = (dramsize - 1) & 0xFFFC0000; - mbar_writeLong(MCFSIM_DMR0, temp | 1); - __asm__("nop"); - - mbar_writeLong(MCFSIM_DACR0, 0x0000322c); - mb(); - __asm__("nop"); - - /* Write to this block to initiate precharge */ - *(u32 *) (CFG_SYS_SDRAM_BASE) = 0xa5a5a5a5; - mb(); - __asm__("nop"); - - /* Set RE bit in DACR */ - mbar_writeLong(MCFSIM_DACR0, - mbar_readLong(MCFSIM_DACR0) | 0x8000); - __asm__("nop"); - - /* Wait for at least 8 auto refresh cycles to occur */ - udelay(500); - - /* Finish the configuration by issuing the MRS */ - mbar_writeLong(MCFSIM_DACR0, - mbar_readLong(MCFSIM_DACR0) | 0x0040); - __asm__("nop"); - - *(u32 *) (CFG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; - mb(); - } - - gd->ram_size = dramsize; - - return 0; -} - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("DRAM test not implemented!\n"); - - return (0); -} - -#ifdef CONFIG_IDE -#include -#include -void ide_set_reset(int idereset) -{ - atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; - long period; - /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ - int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ - {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ - {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ - {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ - {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */ - }; - - if (idereset) { - /* control reset */ - out_8(&ata->cr, 0); - udelay(100); - } else { - mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); - -#define CALC_TIMING(t) (t + period - 1) / period - period = 1000000000 / (CFG_SYS_CLK / 2); /* period in ns */ - - /*ata->ton = CALC_TIMING (180); */ - out_8(&ata->t1, CALC_TIMING(piotms[2][0])); - out_8(&ata->t2w, CALC_TIMING(piotms[2][1])); - out_8(&ata->t2r, CALC_TIMING(piotms[2][1])); - out_8(&ata->ta, CALC_TIMING(piotms[2][8])); - out_8(&ata->trd, CALC_TIMING(piotms[2][7])); - out_8(&ata->t4, CALC_TIMING(piotms[2][3])); - out_8(&ata->t9, CALC_TIMING(piotms[2][6])); - - /* IORDY enable */ - out_8(&ata->cr, 0x40); - udelay(2000); - /* IORDY enable */ - setbits_8(&ata->cr, 0x01); - } -} -#endif /* CONFIG_IDE */ - -#ifdef CONFIG_DRIVER_DM9000 -int board_eth_init(struct bd_info *bis) -{ - return dm9000_initialize(bis); -} -#endif diff --git a/board/freescale/m5272c3/Kconfig b/board/freescale/m5272c3/Kconfig deleted file mode 100644 index aee0b239b3b..00000000000 --- a/board/freescale/m5272c3/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M5272C3 - -config SYS_CPU - default "mcf52x2" - -config SYS_BOARD - default "m5272c3" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "M5272C3" - -endif diff --git a/board/freescale/m5272c3/MAINTAINERS b/board/freescale/m5272c3/MAINTAINERS deleted file mode 100644 index 692ab5b5829..00000000000 --- a/board/freescale/m5272c3/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -M5272C3 BOARD -M: Angelo Dureghello -S: Maintained -F: board/freescale/m5272c3/ -F: include/configs/M5272C3.h -F: configs/M5272C3_defconfig diff --git a/board/freescale/m5272c3/Makefile b/board/freescale/m5272c3/Makefile deleted file mode 100644 index 1df8f7003e4..00000000000 --- a/board/freescale/m5272c3/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = m5272c3.o diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c deleted file mode 100644 index d1286badc61..00000000000 --- a/board/freescale/m5272c3/m5272c3.c +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard (void) { - puts ("Board: "); - puts ("Freescale MCF5272C3 EVB\n"); - return 0; - }; - -int dram_init(void) -{ - sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM); - - out_be16(&sdp->sdram_sdtr, 0xf539); - out_be16(&sdp->sdram_sdcr, 0x4211); - - /* Dummy write to start SDRAM */ - *((volatile unsigned long *)0) = 0; - - gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; - - return 0; - }; - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf ("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/freescale/m5275evb/Kconfig b/board/freescale/m5275evb/Kconfig deleted file mode 100644 index 5a6de9c1c9e..00000000000 --- a/board/freescale/m5275evb/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M5275EVB - -config SYS_CPU - default "mcf52x2" - -config SYS_BOARD - default "m5275evb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "M5275EVB" - -endif diff --git a/board/freescale/m5275evb/MAINTAINERS b/board/freescale/m5275evb/MAINTAINERS deleted file mode 100644 index 065ae7bb1df..00000000000 --- a/board/freescale/m5275evb/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -M5275EVB BOARD -M: Angelo Dureghello -S: Maintained -F: board/freescale/m5275evb/ -F: include/configs/M5275EVB.h -F: configs/M5275EVB_defconfig diff --git a/board/freescale/m5275evb/Makefile b/board/freescale/m5275evb/Makefile deleted file mode 100644 index 83e3b10f0ed..00000000000 --- a/board/freescale/m5275evb/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = m5275evb.o diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c deleted file mode 100644 index 8b986d42425..00000000000 --- a/board/freescale/m5275evb/m5275evb.c +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com) - * - * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define PERIOD 13 /* system bus period in ns */ -#define SDRAM_TREFI 7800 /* in ns */ - -int checkboard(void) -{ - puts("Board: "); - puts("Freescale MCF5275 EVB\n"); - return 0; -}; - -int dram_init(void) -{ - sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM); - gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO); - - /* Enable SDRAM */ - out_be16(&gpio_reg->par_sdram, 0x3FF); - - /* Set up chip select */ - out_be32(&sdp->sdbar0, CFG_SYS_SDRAM_BASE); - out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V); - - /* Set up timing */ - out_be32(&sdp->sdcfg1, 0x83711630); - out_be32(&sdp->sdcfg2, 0x46770000); - - /* Enable clock */ - out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE); - - /* Set precharge */ - setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); - - /* Dummy write to start SDRAM */ - *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; - - /* Send LEMR */ - setbits_be32(&sdp->sdmr, - MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) | - MCF_SDRAMC_SDMR_CMD); - *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; - - /* Send LMR */ - out_be32(&sdp->sdmr, 0x058d0000); - *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; - - /* Stop sending commands */ - clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD); - - /* Set precharge */ - setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); - *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; - - /* Stop manual precharge, send 2 IREF */ - clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); - setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF); - *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; - *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; - - out_be32(&sdp->sdmr, 0x018d0000); - *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; - - /* Stop sending commands */ - clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD); - clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN); - - /* Turn on auto refresh, lock SDMR */ - out_be32(&sdp->sdcr, - MCF_SDRAMC_SDCR_CKE - | MCF_SDRAMC_SDCR_REF - | MCF_SDRAMC_SDCR_MUX(1) - /* 1 added to round up */ - | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1) - | MCF_SDRAMC_SDCR_DQS_OE(0x3)); - - gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; - - return 0; -}; - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/freescale/m5282evb/Kconfig b/board/freescale/m5282evb/Kconfig deleted file mode 100644 index 2ffdd528f63..00000000000 --- a/board/freescale/m5282evb/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M5282EVB - -config SYS_CPU - default "mcf52x2" - -config SYS_BOARD - default "m5282evb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "M5282EVB" - -endif diff --git a/board/freescale/m5282evb/MAINTAINERS b/board/freescale/m5282evb/MAINTAINERS deleted file mode 100644 index f141c89c3a5..00000000000 --- a/board/freescale/m5282evb/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -M5282EVB BOARD -M: Angelo Dureghello -S: Maintained -F: board/freescale/m5282evb/ -F: include/configs/M5282EVB.h -F: configs/M5282EVB_defconfig diff --git a/board/freescale/m5282evb/Makefile b/board/freescale/m5282evb/Makefile deleted file mode 100644 index e898f39330b..00000000000 --- a/board/freescale/m5282evb/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = m5282evb.o diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c deleted file mode 100644 index 81da6e2abd4..00000000000 --- a/board/freescale/m5282evb/m5282evb.c +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard (void) -{ - puts ("Board: Freescale M5282EVB Evaluation Board\n"); - return 0; -} - -int dram_init(void) -{ - u32 dramsize, i, dramclk; - - dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; - for (i = 0x13; i < 0x20; i++) { - if (dramsize == (1 << i)) - break; - } - i--; - - if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE)) - { - dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ); - - /* Initialize DRAM Control Register: DCR */ - MCFSDRAMC_DCR = (0 - | MCFSDRAMC_DCR_RTIM_6 - | MCFSDRAMC_DCR_RC((15 * dramclk)>>4)); - asm("nop"); - - /* Initialize DACR0 */ - MCFSDRAMC_DACR0 = (0 - | MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE) - | MCFSDRAMC_DACR_CASL(1) - | MCFSDRAMC_DACR_CBM(3) - | MCFSDRAMC_DACR_PS_32); - asm("nop"); - - /* Initialize DMR0 */ - MCFSDRAMC_DMR0 = (0 - | ((dramsize - 1) & 0xFFFC0000) - | MCFSDRAMC_DMR_V); - asm("nop"); - - /* Set IP (bit 3) in DACR */ - MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; - asm("nop"); - - /* Wait 30ns to allow banks to precharge */ - for (i = 0; i < 5; i++) { - asm ("nop"); - } - - /* Write to this block to initiate precharge */ - *(u32 *)(CFG_SYS_SDRAM_BASE) = 0xA5A59696; - asm("nop"); - - /* Set RE (bit 15) in DACR */ - MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; - asm("nop"); - - /* Wait for at least 8 auto refresh cycles to occur */ - for (i = 0; i < 2000; i++) { - asm(" nop"); - } - - /* Finish the configuration by issuing the IMRS. */ - MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; - asm("nop"); - - /* Write to the SDRAM Mode Register */ - *(u32 *)(CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; - } - gd->ram_size = dramsize; - - return 0; -} diff --git a/board/freescale/m53017evb/Kconfig b/board/freescale/m53017evb/Kconfig deleted file mode 100644 index 8ab89e52b2e..00000000000 --- a/board/freescale/m53017evb/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M53017EVB - -config SYS_CPU - default "mcf532x" - -config SYS_BOARD - default "m53017evb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "M53017EVB" - -endif diff --git a/board/freescale/m53017evb/MAINTAINERS b/board/freescale/m53017evb/MAINTAINERS deleted file mode 100644 index ad5f0cea664..00000000000 --- a/board/freescale/m53017evb/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -M53017EVB BOARD -M: TsiChung Liew -S: Maintained -F: board/freescale/m53017evb/ -F: include/configs/M53017EVB.h -F: configs/M53017EVB_defconfig diff --git a/board/freescale/m53017evb/Makefile b/board/freescale/m53017evb/Makefile deleted file mode 100644 index 4eeb3a860b9..00000000000 --- a/board/freescale/m53017evb/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = m53017evb.o diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README deleted file mode 100644 index 34f05f3fdc7..00000000000 --- a/board/freescale/m53017evb/README +++ /dev/null @@ -1,178 +0,0 @@ -Freescale MCF53017EVB ColdFire Development Board -================================================ - -TsiChung Liew(Tsi-Chung.Liew@freescale.com) -Created 10/22/08 -=========================================== - - -Changed files: -============== - -- board/freescale/m53017evb/m53017evb.c Dram setup -- board/freescale/m53017evb/mii.c Mii access -- board/freescale/m53017evb/Makefile Makefile -- board/freescale/m53017evb/config.mk config make -- board/freescale/m53017evb/u-boot.lds Linker description - -- arch/m68k/cpu/mcf532x/cpu.c cpu specific code -- arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs -- arch/m68k/cpu/mcf532x/interrupts.c cpu specific interrupt support -- arch/m68k/cpu/mcf532x/speed.c system, flexbus, and cpu clock -- arch/m68k/cpu/mcf532x/Makefile Makefile -- arch/m68k/cpu/mcf532x/config.mk config make -- arch/m68k/cpu/mcf532x/start.S start up assembly code - -- board/freescale/m53017evb/README his readme file - -- drivers/net/mcffec.c ColdFire common FEC driver -- drivers/net/mcfmii.c ColdFire common Mii driver -- drivers/serial/mcfuart.c ColdFire common UART driver -- drivers/rtc/mcfrtc.c Realtime clock Driver - -- include/asm-m68k/bitops.h Bit operation function export -- include/asm-m68k/byteorder.h Byte order functions -- include/asm-m68k/fec.h FEC structure and definition -- include/asm-m68k/fsl_i2c.h I2C structure and definition -- include/asm-m68k/global_data.h Global data structure -- include/asm-m68k/immap.h ColdFire specific header file and driver macros -- include/asm-m68k/immap_5301x.h mcf5301x specific header file -- include/asm-m68k/io.h io functions -- include/asm-m68k/m532x.h mcf5301x specific header file -- include/asm-m68k/posix_types.h Posix -- include/asm-m68k/processor.h header file -- include/asm-m68k/ptrace.h Exception structure -- include/asm-m68k/rtc.h Realtime clock header file -- include/asm-m68k/string.h String function export -- include/asm-m68k/timer.h Timer structure and definition -- include/asm-m68k/types.h Data types definition -- include/asm-m68k/uart.h Uart structure and definition -- include/asm-m68k/u-boot.h U-Boot structure - -- include/configs/M53017EVB.h Board specific configuration file - -- arch/m68k/lib/board.c board init function -- arch/m68k/lib/cache.c -- arch/m68k/lib/interrupts Coldfire common interrupt functions -- arch/m68k/lib/m68k_linux.c -- arch/m68k/lib/time.c Timer functions (Dma timer and PIT) -- arch/m68k/lib/traps.c Exception init code - -1 MCF5301x specific Options/Settings -==================================== -1.1 pre-loader is no longer suppoer in thie coldfire family - -1.2 Configuration settings for M53017EVB Development Board -CONFIG_MCF5301x -- define for all MCF5301x CPUs -CONFIG_M53015 -- define for MCF53015 CPUs -CONFIG_M53017EVB -- define for M53017EVB board - -CONFIG_MCFUART -- define to use common CF Uart driver -CFG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 -CONFIG_BAUDRATE -- define UART baudrate - -CONFIG_MCFRTC -- define to use common CF RTC driver -CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h -CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency -RTC_DEBUG -- define to show RTC debug message -CONFIG_CMD_DATE -- enable to use date feature in U-Boot - -CONFIG_MCFFEC -- define to use common CF FEC driver -CONFIG_MII -- enable to use MII driver -CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c -CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery -CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer -CONFIG_SYS_FAULT_ECHO_LINK_DOWN -- -CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration -CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register -MCFFEC_TOUT_LOOP -- set FEC timeout loop - -CONFIG_MCFTMR -- define to use DMA timer - -CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver -CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged -CONFIG_SYS_I2C_SPEED -- define for I2C speed -CONFIG_SYS_I2C_SLAVE -- define for I2C slave address -CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset -CONFIG_SYS_IMMR -- define for MBAR offset - -CFG_SYS_MBAR -- define MBAR offset - -CONFIG_MONITOR_IS_IN_RAM -- Not support - -CFG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM - -CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register -CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register -CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register - -CFG_SYS_SDRAM_BASE -- defines the DRAM Base - -2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL -=========================================== -2.1. System memory map: - Flash: 0x00000000-0x3FFFFFFF (1024MB) - DDR: 0x40000000-0x7FFFFFFF (1024MB) - SRAM: 0x80000000-0x8FFFFFFF (256MB) - IP: 0xFC000000-0xFFFFFFFF (256MB) - -2.2. For the initial bringup, we adopted a consistent memory scheme between U-Boot and - linux kernel, you can customize it based on your system requirements: - Flash0: 0x00000000-0x00FFFFFF (16MB) - DDR: 0x40000000-0x4FFFFFFF (256MB) - SRAM: 0x80000000-0x80007FFF (32KB) - IP: 0xFC000000-0xFC0FFFFF (64KB) - -3. COMPILATION -============== -3.1 To create U-Boot the gcc-4.x-xx compiler set (ColdFire ELF or -uClinux version) from codesourcery.com was used. Download it from: -http://www.codesourcery.com/gnu_toolchains/coldfire/download.html - -3.2 Compilation - export CROSS_COMPILE=cross-compile-prefix - cd u-boot - make distclean - make M53017EVB_config - make - -4. SCREEN DUMP -============== -4.1 M53017EVB Development board - (NOTE: May not show exactly the same) - -U-Boot 2008.10 (Oct 22 2007 - 11:07:57) - -CPU: Freescale MCF53015 (Mask:76 Version:0) - CPU CLK 240 Mhz BUS CLK 80 Mhz -Board: Freescale M53017EVB -I2C: ready -DRAM: 64 MB -FLASH: 16 MB -In: serial -Out: serial -Err: serial -NAND: 16 MiB -Net: FEC0, FEC1 --> print -bootdelay=1 -baudrate=115200 -ethaddr=00:e0:0c:bc:e5:60 -hostname=M53017EVB -netdev=eth0 -loadaddr=40010000 -u-boot=u-boot.bin -load=tftp ${loadaddr) ${u-boot} -upd=run load; run prog -prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save -gatewayip=192.168.1.1 -netmask=255.255.255.0 -ipaddr=192.168.1.3 -serverip=192.168.1.2 -stdin=serial -stdout=serial -stderr=serial -mem=65024k - -Environment size: 437/4092 bytes --> diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c deleted file mode 100644 index 196d56dc17d..00000000000 --- a/board/freescale/m53017evb/m53017evb.c +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("Board: "); - puts("Freescale M53017EVB\n"); - return 0; -}; - -int dram_init(void) -{ - sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); - u32 dramsize, i; - - dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; - - for (i = 0x13; i < 0x20; i++) { - if (dramsize == (1 << i)) - break; - } - i--; - - out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); -#ifdef CFG_SYS_SDRAM_BASE1 - out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i); -#endif - out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); - out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2); - - udelay(500); - - /* Issue PALL */ - out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); - asm("nop"); - - /* Perform two refresh cycles */ - out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); - asm("nop"); - - /* Issue LEMR */ - out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE); - asm("nop"); - out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); - asm("nop"); - - out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); - asm("nop"); - - out_be32(&sdram->ctrl, - (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); - asm("nop"); - - udelay(100); - - gd->ram_size = dramsize; - - return 0; -}; - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/freescale/m5329evb/Kconfig b/board/freescale/m5329evb/Kconfig deleted file mode 100644 index 930fbba246d..00000000000 --- a/board/freescale/m5329evb/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M5329EVB - -config SYS_CPU - default "mcf532x" - -config SYS_BOARD - default "m5329evb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "M5329EVB" - -endif diff --git a/board/freescale/m5329evb/MAINTAINERS b/board/freescale/m5329evb/MAINTAINERS deleted file mode 100644 index 2f7dd2d4560..00000000000 --- a/board/freescale/m5329evb/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -M5329EVB BOARD -M: TsiChung Liew -S: Maintained -F: board/freescale/m5329evb/ -F: include/configs/M5329EVB.h -F: configs/M5329AFEE_defconfig -F: configs/M5329BFEE_defconfig diff --git a/board/freescale/m5329evb/Makefile b/board/freescale/m5329evb/Makefile deleted file mode 100644 index 19796c213fb..00000000000 --- a/board/freescale/m5329evb/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = m5329evb.o nand.o diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c deleted file mode 100644 index 26d5f3bf58c..00000000000 --- a/board/freescale/m5329evb/m5329evb.c +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("Board: "); - puts("Freescale FireEngine 5329 EVB\n"); - return 0; -}; - -int dram_init(void) -{ - sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); - u32 dramsize, i; - - dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; - - for (i = 0x13; i < 0x20; i++) { - if (dramsize == (1 << i)) - break; - } - i--; - - out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); - out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); - out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2); - - /* Issue PALL */ - out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); - - /* Issue LEMR */ - out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); - out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000); - - udelay(500); - - /* Issue PALL */ - out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); - - /* Perform two refresh cycles */ - out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); - - out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE); - - out_be32(&sdram->ctrl, - (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); - - udelay(100); - - gd->ram_size = dramsize; - - return 0; -}; - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c deleted file mode 100644 index a250d61ef36..00000000000 --- a/board/freescale/m5329evb/nand.c +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include -#include -#include - -#if defined(CONFIG_CMD_NAND) -#include -#include -#include - -#define SET_CLE 0x10 -#define SET_ALE 0x08 - -static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd_to_nand(mtdinfo); - volatile u16 *nCE = (u16 *) CFG_SYS_LATCH_ADDR; - - if (ctrl & NAND_CTRL_CHANGE) { - ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; - - IO_ADDR_W &= ~(SET_ALE | SET_CLE); - - if (ctrl & NAND_NCE) - *nCE &= 0xFFFB; - else - *nCE |= 0x0004; - - if (ctrl & NAND_CLE) - IO_ADDR_W |= SET_CLE; - if (ctrl & NAND_ALE) - IO_ADDR_W |= SET_ALE; - - this->IO_ADDR_W = (void *)IO_ADDR_W; - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -int board_nand_init(struct nand_chip *nand) -{ - gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - /* - * set up pin configuration - enabled 2nd output buffer's signals - * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) - * to use nCE signal - */ - clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3); - setbits_8(&gpio->pddr_timer, 0x08); - setbits_8(&gpio->ppd_timer, 0x08); - out_8(&gpio->pclrr_timer, 0); - out_8(&gpio->podr_timer, 0); - - nand->chip_delay = 60; - nand->ecc.mode = NAND_ECC_SOFT; - nand->cmd_ctrl = nand_hwcontrol; - - return 0; -} -#endif diff --git a/board/freescale/m5373evb/Kconfig b/board/freescale/m5373evb/Kconfig deleted file mode 100644 index 67d049d79eb..00000000000 --- a/board/freescale/m5373evb/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M5373EVB - -config SYS_CPU - default "mcf532x" - -config SYS_BOARD - default "m5373evb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "M5373EVB" - -endif diff --git a/board/freescale/m5373evb/MAINTAINERS b/board/freescale/m5373evb/MAINTAINERS deleted file mode 100644 index acb7a43ed64..00000000000 --- a/board/freescale/m5373evb/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -M5373EVB BOARD -M: TsiChung Liew -S: Maintained -F: board/freescale/m5373evb/ -F: include/configs/M5373EVB.h -F: configs/M5373EVB_defconfig diff --git a/board/freescale/m5373evb/Makefile b/board/freescale/m5373evb/Makefile deleted file mode 100644 index 20efa7b8432..00000000000 --- a/board/freescale/m5373evb/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = m5373evb.o nand.o diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README deleted file mode 100644 index 7240648796b..00000000000 --- a/board/freescale/m5373evb/README +++ /dev/null @@ -1,324 +0,0 @@ -Freescale MCF5373EVB ColdFire Development Board -================================================ - -TsiChung Liew(Tsi-Chung.Liew@freescale.com) -Created 11/08/07 -=========================================== - - -Changed files: -============== - -- board/freescale/m5373evb/m5373evb.c Dram setup -- board/freescale/m5373evb/mii.c Mii access -- board/freescale/m5373evb/Makefile Makefile -- board/freescale/m5373evb/config.mk config make -- board/freescale/m5373evb/u-boot.lds Linker description - -- arch/m68k/cpu/mcf532x/cpu.c cpu specific code -- arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs -- arch/m68k/cpu/mcf532x/interrupts.c cpu specific interrupt support -- arch/m68k/cpu/mcf532x/speed.c system, pci, flexbus, and cpu clock -- arch/m68k/cpu/mcf532x/Makefile Makefile -- arch/m68k/cpu/mcf532x/config.mk config make -- arch/m68k/cpu/mcf532x/start.S start up assembly code - -- board/freescale/m5373evb/README This readme file - -- drivers/net/mcffec.c ColdFire common FEC driver -- drivers/serial/mcfuart.c ColdFire common UART driver -- drivers/rtc/mcfrtc.c Realtime clock Driver - -- include/asm-m68k/bitops.h Bit operation function export -- include/asm-m68k/byteorder.h Byte order functions -- include/asm-m68k/fec.h FEC structure and definition -- include/asm-m68k/fsl_i2c.h I2C structure and definition -- include/asm-m68k/global_data.h Global data structure -- include/asm-m68k/immap.h ColdFire specific header file and driver macros -- include/asm-m68k/immap_532x.h mcf532x specific header file -- include/asm-m68k/io.h io functions -- include/asm-m68k/m532x.h mcf532x specific header file -- include/asm-m68k/posix_types.h Posix -- include/asm-m68k/processor.h header file -- include/asm-m68k/ptrace.h Exception structure -- include/asm-m68k/rtc.h Realtime clock header file -- include/asm-m68k/string.h String function export -- include/asm-m68k/timer.h Timer structure and definition -- include/asm-m68k/types.h Data types definition -- include/asm-m68k/uart.h Uart structure and definition -- include/asm-m68k/u-boot.h U-Boot structure - -- include/configs/M5373EVB.h Board specific configuration file - -- arch/m68k/lib/board.c board init function -- arch/m68k/lib/cache.c -- arch/m68k/lib/interrupts Coldfire common interrupt functions -- arch/m68k/lib/m68k_linux.c -- arch/m68k/lib/time.c Timer functions (Dma timer and PIT) -- arch/m68k/lib/traps.c Exception init code - -1 MCF5373 specific Options/Settings -==================================== -1.1 pre-loader is no longer suppoer in thie coldfire family - -1.2 Configuration settings for M5373EVB Development Board -CONFIG_MCF532x -- define for all MCF532x CPUs -CONFIG_M5373 -- define for all Freescale MCF5373 CPUs -CONFIG_M5373EVB -- define for M5373EVB board - -CONFIG_MCFUART -- define to use common CF Uart driver -CFG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 -CONFIG_BAUDRATE -- define UART baudrate - -CONFIG_MCFRTC -- define to use common CF RTC driver -CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h -CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency -RTC_DEBUG -- define to show RTC debug message -CONFIG_CMD_DATE -- enable to use date feature in U-Boot - -CONFIG_MCFFEC -- define to use common CF FEC driver -CONFIG_MII -- enable to use MII driver -CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c -CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery -CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer -CONFIG_SYS_FAULT_ECHO_LINK_DOWN-- -CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration -CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register -MCFFEC_TOUT_LOOP -- set FEC timeout loop - -CONFIG_MCFTMR -- define to use DMA timer - -CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver -CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged -CONFIG_SYS_I2C_SPEED -- define for I2C speed -CONFIG_SYS_I2C_SLAVE -- define for I2C slave address -CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset -CONFIG_SYS_IMMR -- define for MBAR offset - -CFG_SYS_MBAR -- define MBAR offset - -CONFIG_MONITOR_IS_IN_RAM -- Not support - -CFG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5373 internal SRAM - -CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register -CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register -CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register - -CFG_SYS_SDRAM_BASE -- defines the DRAM Base - -2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL -=========================================== -2.1. System memory map: - Flash: 0x00000000-0x3FFFFFFF (1024MB) - DDR: 0x40000000-0x7FFFFFFF (1024MB) - SRAM: 0x80000000-0x8FFFFFFF (256MB) - IP: 0xF0000000-0xFFFFFFFF (256MB) - -2.2. For the initial bringup, we adopted a consistent memory scheme between U-Boot and - linux kernel, you can customize it based on your system requirements: - Flash0: 0x00000000-0x00FFFFFF (16MB) - - DDR: 0x40000000-0x4FFFFFFF (256MB) - SRAM: 0x80000000-0x80007FFF (32KB) - IP: 0xFC000000-0xFC0FFFFF (64KB) - -3. COMPILATION -============== -3.1 To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or -uClinux version) from codesourcery.com was used. Download it from: -http://www.codesourcery.com/gnu_toolchains/coldfire/download.html - -3.2 Compilation - export CROSS_COMPILE=cross-compile-prefix - cd u-boot-1.x.x - make distclean - make M5373EVB_config - make - -4. SCREEN DUMP -============== -4.1 M5373EVB Development board - (NOTE: May not show exactly the same) - -U-Boot 1.3.0 (Nov 8 2007 - 12:44:08) - -CPU: Freescale MCF5373 (Mask:65 Version:1) - CPU CLK 240 Mhz BUS CLK 80 Mhz -Board: Freescale FireEngine 5373 EVB -I2C: ready -DRAM: 32 MB -FLASH: 2 MB -In: serial -Out: serial -Err: serial -NAND: 16 MiB -Net: FEC0 --> print -bootdelay=1 -baudrate=115200 -ethaddr=00:e0:0c:bc:e5:60 -hostname=M5373EVB -netdev=eth0 -loadaddr=40010000 -load=tftp ${loadaddr) ${u-boot} -upd=run load; run prog -prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save -ethact=FEC0 -u-boot=u-boot.bin -gatewayip=192.168.1.1 -netmask=255.255.255.0 -ipaddr=192.168.1.3 -serverip=192.168.1.2 -stdin=serial -stdout=serial -stderr=serial -mem=261632k - -Environment size: 401/8188 bytes --> bdinfo -memstart = 0x40000000 -memsize = 0x02000000 -flashstart = 0x00000000 -flashsize = 0x00200000 -flashoffset = 0x00000000 -sramstart = 0x80000000 -sramsize = 0x00008000 -mbar = 0xFC000000 -busfreq = 80 MHz -ethaddr = 00:E0:0C:BC:E5:60 -ip_addr = 192.168.1.3 -baudrate = 115200 bps --> --> help -? - alias for 'help' -base - print or set address offset -bdinfo - print Board Info structure -boot - boot default, i.e., run 'bootcmd' -bootd - boot default, i.e., run 'bootcmd' -bootelf - Boot from an ELF image in memory -bootm - boot application image from memory -bootp - boot image via network using BootP/TFTP protocol -bootvx - Boot vxWorks from an ELF image -cmp - memory compare -coninfo - print console devices and information -cp - memory copy -crc32 - checksum calculation -date - get/set/reset date & time -dcache - enable or disable data cache -echo - echo args to console -erase - erase FLASH memory -flinfo - print FLASH memory information -go - start application at address 'addr' -help - print online help -i2c - I2C sub-system -icache - enable or disable instruction cache -iminfo - print header information for application image -imls - list all images found in flash -itest - return true/false on integer compare -loadb - load binary file over serial line (kermit mode) -loads - load S-Record file over serial line -loady - load binary file over serial line (ymodem mode) -loop - infinite loop on address range -ls - list files in a directory (default /) -md - memory display -mii - MII utility commands -mm - memory modify (auto-incrementing) -mtest - simple RAM test -mw - memory write (fill) -nand - NAND sub-system -nboot - boot from NAND device -nfs - boot image via network using NFS protocol -nm - memory modify (constant address) -ping - send ICMP ECHO_REQUEST to network host -printenv- print environment variables -protect - enable or disable FLASH write protection -rarpboot- boot image via network using RARP/TFTP protocol -reset - Perform RESET of the CPU -run - run commands in an environment variable -saveenv - save environment variables to persistent storage -setenv - set environment variables -sleep - delay execution for some time -source - run script from memory -tftpboot- boot image via network using TFTP protocol -version - print monitor version --> tftp 0x40800000 uImage -Using FEC0 device -TFTP from server 192.168.1.3; our IP address is 192.168.1.3 Filename 'uImage'. -Load address: 0x40800000 -Loading: ################################################################# - ################################################################# - ########## -done -Bytes transferred = 2053270 (1f5496 hex) --> bootm 0x40800000 -## Booting image at 40800000 ... - Image Name: Linux Kernel Image - Created: 2007-11-07 20:33:08 UTC - Image Type: M68K Linux Kernel Image (gzip compressed) - Data Size: 2053206 Bytes = 2 MB - Load Address: 40020000 - Entry Point: 40020000 - Verifying Checksum ... OK - Uncompressing Kernel Image ... OK -Linux version 2.6.22-uc1 (mattw@loa) (gcc version 4.2.1 (Sourcery G++ Lite 4.2-7 - - -uClinux/COLDFIRE(m537x) -COLDFIRE port done by Greg Ungerer, gerg@snapgear.com Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne Built 1 zonelists. Total pages: 8128 Kernel command line: rootfstype=romfs PID hash table entries: 128 (order: 7, 512 bytes) Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) Memory available: 28092k/32768k RAM, (1788k kernel code, 244k data) Mount-cache hash table entries: 512 -NET: Registered protocol family 16 -USB-MCF537x: (HOST module) EHCI device is registered -USB-MCF537x: (OTG module) EHCI device is registered -USB-MCF537x: (OTG module) UDC device is registered -usbcore: registered new interface driver usbfs -usbcore: registered new interface driver hub -usbcore: registered new device driver usb -NET: Registered protocol family 2 -IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 1024 (order: 1, 8192 bytes) TCP bind hash table entries: 1024 (order: 0, 4096 bytes) -TCP: Hash tables configured (established 1024 bind 1024) TCP reno registered -JFFS2 version 2.2. (NAND) © 2001-2006 Red Hat, Inc. -io scheduler noop registered -io scheduler cfq registered (default) -ColdFire internal UART serial driver version 1.00 ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART -ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART -ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize -loop: module loaded -nbd: registered device at major 43 -usbcore: registered new interface driver ub FEC ENET Version 0.2 -fec: PHY @ 0x1, ID 0x20005c90 -- DP83848 -eth0: ethernet 00:e0:0c:bc:e5:60 -uclinux[mtd]: RAM probe address=0x4021c22c size=0x22b000 Creating 1 MTD partitions on "RAM": -0x00000000-0x0022b000 : "ROMfs" -uclinux[mtd]: set ROMfs to be root filesystem NAND device: Manufacturer ID: 0x20, Chip ID: 0x73 (ST Micro NAND 16MiB 3,3V 8-b) Scanning device for bad blocks Creating 1 MTD partitions on "NAND 16MiB 3,3V 8-bit": -0x00000000-0x01000000 : "M53xx flash partition 1" -QSPI: spi->max_speed_hz 300000 -QSPI: Baud set to 255 -SPI: Coldfire master initialized -M537x - Disable UART1 when using Audio -udc: Freescale MCF53xx UDC driver version 27 October 2006 init -udc: MCF53xx USB Device is found. ID=0x5 Rev=0x41 i2c /dev entries driver -usbcore: registered new interface driver usbhid -drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver TCP cubic registered -NET: Registered protocol family 1 -NET: Registered protocol family 17 -VFS: Mounted root (romfs filesystem) readonly. -Freeing unused kernel memory: 64k freed (0x401f5000 - 0x40204000) init started: BusyBox v1.00 (2007.11.07-19:57+0000) multi-call binary?Setting e Mounting filesystems -mount: Mounting devpts on /dev/pts failed: No such device -mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory Starting syslogd and klogd Setting up networking on loopback device: -Setting up networking on eth0: -info, udhcpc (v0.9.9-pre) started -eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX. -debug, Sending discover... -debug, Sending discover... -debug, Sending select for 172.27.0.130... -info, Lease of 172.27.0.130 obtained, lease time 43200 deleting routers -route: SIOC[ADD|DEL]RT: No such process -adding dns 172.27.0.1 -Starting the boa webserver: -Setting time from ntp server: ntp.cs.strath.ac.uk -ntp.cs.strath.ac.uk: Unknown host - - -BusyBox v1.00 (2007.11.07-19:57+0000) Built-in shell (msh) Enter 'help' for a list of built-in commands. - -# diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c deleted file mode 100644 index d6fdf41bab4..00000000000 --- a/board/freescale/m5373evb/m5373evb.c +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("Board: "); - puts("Freescale FireEngine 5373 EVB\n"); - return 0; -}; - -int dram_init(void) -{ - sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); - u32 dramsize, i; - - dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; - - for (i = 0x13; i < 0x20; i++) { - if (dramsize == (1 << i)) - break; - } - i--; - - out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); - out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); - out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2); - - /* Issue PALL */ - out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); - - /* Issue LEMR */ - out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); - out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000); - - udelay(500); - - /* Issue PALL */ - out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); - - /* Perform two refresh cycles */ - out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); - - out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE); - - out_be32(&sdram->ctrl, - (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); - - udelay(100); - - gd->ram_size = dramsize; - - return 0; -}; - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("DRAM test not implemented!\n"); - - return (0); -} diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c deleted file mode 100644 index e7c08d22e6b..00000000000 --- a/board/freescale/m5373evb/nand.c +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#include -#include -#include - -#if defined(CONFIG_CMD_NAND) -#include -#include -#include - -#define SET_CLE 0x10 -#define SET_ALE 0x08 - -static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd_to_nand(mtdinfo); - volatile u16 *nCE = (u16 *) CFG_SYS_LATCH_ADDR; - - if (ctrl & NAND_CTRL_CHANGE) { - ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; - - IO_ADDR_W &= ~(SET_ALE | SET_CLE); - - if (ctrl & NAND_NCE) - *nCE &= 0xFFFB; - else - *nCE |= 0x0004; - - if (ctrl & NAND_CLE) - IO_ADDR_W |= SET_CLE; - if (ctrl & NAND_ALE) - IO_ADDR_W |= SET_ALE; - - this->IO_ADDR_W = (void *)IO_ADDR_W; - - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -int board_nand_init(struct nand_chip *nand) -{ - gpio_t *gpio = (gpio_t *) MMAP_GPIO; - fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - - clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP); - - /* - * set up pin configuration - enabled 2nd output buffer's signals - * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) - * to use nCE signal - */ - clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3); - setbits_8(&gpio->pddr_timer, 0x08); - setbits_8(&gpio->ppd_timer, 0x08); - out_8(&gpio->pclrr_timer, 0); - out_8(&gpio->podr_timer, 0); - - nand->chip_delay = 60; - nand->ecc.mode = NAND_ECC_SOFT; - nand->cmd_ctrl = nand_hwcontrol; - - return 0; -} -#endif diff --git a/board/freescale/mpc837xerdb/Kconfig b/board/freescale/mpc837xerdb/Kconfig deleted file mode 100644 index 3779625edd5..00000000000 --- a/board/freescale/mpc837xerdb/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MPC837XERDB - -config PCIE - def_bool y - -config SYS_BOARD - default "mpc837xerdb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC837XERDB" - -endif diff --git a/board/freescale/mpc837xerdb/MAINTAINERS b/board/freescale/mpc837xerdb/MAINTAINERS deleted file mode 100644 index 9f44a37a0d9..00000000000 --- a/board/freescale/mpc837xerdb/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MPC837XERDB BOARD -M: Sinan Akman -S: Maintained -F: board/freescale/mpc837xerdb/ -F: include/configs/MPC837XERDB.h -F: configs/MPC837XERDB_defconfig -F: configs/MPC837XERDB_SLAVE_defconfig diff --git a/board/freescale/mpc837xerdb/Makefile b/board/freescale/mpc837xerdb/Makefile deleted file mode 100644 index 4661e4cf232..00000000000 --- a/board/freescale/mpc837xerdb/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc837xerdb.o diff --git a/board/freescale/mpc837xerdb/README b/board/freescale/mpc837xerdb/README deleted file mode 100644 index 12df2f2e756..00000000000 --- a/board/freescale/mpc837xerdb/README +++ /dev/null @@ -1,97 +0,0 @@ -Freescale MPC837xE-RDB Board ------------------------------------------ - -1. Board Description - - The MPC837xE-RDB are reference boards featuring the Freescale MPC8377E, - MPC8378E, and the MPC8379E processors in a Mini-ITX form factor. - - The MPC837xE-RDB's have the following common features: - - A) 256-MBytes on-board DDR2 unbuffered SDRAM - B) 8-Mbytes NOR Flash - C) 32-MBytes NAND Flash - D) 1 Secure Digital High Speed Card (SDHC) Interface - E) 1 Gigabit Ethernet - F) 5-port Ethernet switch (Vitesse 7385) - G) 1 32-bit, 3.3 V, PCI slot - H) 1 32-bit, 3.3 V, Mini-PCI slot - I) 4-port USB 2.0 Hub - J) 1-port OTG USB - K) 2 serial ports (top main console) - L) on board Oscillator: 66M - - The MPC837xE-RDB's have the following differences: - - MPC8377E-RDB MPC8378E-RDB MPC8379E-RDB - SATA controllers 2 0 4 - PCI-Express (mini) 2 2 0 - SGMII Ports 0 2 0 - - -2. Memory Map - -2.1. The memory map should look pretty much like this: - - Address Range Device Size Port Size - (Bytes) (Bits) - =========================== ================= ======= ========= - 0x0000_0000 0x0fff_ffff DDR 256M 64 - 0x1000_0000 0x7fff_ffff Empty 1.75G - - 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M 32 - 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M 32 - 0xe030_0000 0xe03f_ffff PCI I/O space 1M 32 - 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M - - 0xe060_0000 0xe060_7fff NAND Flash 32K 8 - 0xfe00_0000 0xfe7f_ffff NOR Flash on CS0 8M 16 - - -3. Definitions - -3.1 Explanation of NEW definitions in: - - include/configs/MPC837XERDB.h - - CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360 - CONFIG_MPC837x MPC837x specific - CONFIG_MPC837XERDB MPC837xE-RDB board specific - - -4. Compilation - - Assuming you're using BASH shell: - - export CROSS_COMPILE=your-cross-compile-prefix - cd u-boot - make distclean - make MPC837XERDB_config - make - - -5. Downloading and Flashing Images - -5.0 Download over serial line using Kermit: - - loadb $loadaddr - [Drop to kermit: - ^\c - send - c - ] - - - Or via tftp: - - tftp $loadaddr u-boot.bin - -5.1 Reflash U-Boot Image using U-Boot - - tftp $loadaddr u-boot.bin - protect off fe000000 fe0fffff - erase fe000000 fe0fffff - cp.b $loadaddr fe000000 $filesize - - -6. Additional Notes: - 1) The console is connected to the top RS-232 connector and the - baudrate for MPC837XE-RDB is 115200bps. diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c deleted file mode 100644 index 55299745a3c..00000000000 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ /dev/null @@ -1,242 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * Kevin Lam - * Joe D'Abbraccio - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CFG_SYS_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CONFIG_SYS_MEMTEST_START, - CONFIG_SYS_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -void ddr_enable_ecc(unsigned int dram_size); -#endif -int fixed_sdram(void); - -int dram_init(void) -{ - immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) - return -ENXIO; - -#if defined(CONFIG_SPD_EEPROM) - msize = spd_sdram(); -#else - msize = fixed_sdram(); -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* Initialize DDR ECC byte */ - ddr_enable_ecc(msize * 1024 * 1024); -#endif - /* return total bus DDR size(bytes) */ - gd->ram_size = msize * 1024 * 1024; - - return 0; -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = CFG_SYS_SDRAM_SIZE; - u32 msize_log2 = __ilog2(msize); - - im->sysconf.ddrlaw[0].bar = CFG_SYS_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - - im->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE; - udelay(50000); - - im->ddr.sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL; - udelay(1000); - - im->ddr.csbnds[0].csbnds = CFG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CFG_SYS_DDR_CS0_CONFIG; - udelay(1000); - - im->ddr.timing_cfg_0 = CFG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CFG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CFG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CFG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CFG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CFG_SYS_DDR_INTERVAL; - sync(); - udelay(1000); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - udelay(2000); - return CFG_SYS_SDRAM_SIZE >> 20; -} -#endif /*!CONFIG_SYS_SPD_EEPROM */ - -int checkboard(void) -{ - puts("Board: Freescale MPC837xERDB\n"); - return 0; -} - -int board_early_init_f(void) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; -#ifdef CONFIG_FSL_SERDES - u32 spridr = in_be32(&immr->sysconf.spridr); - - /* we check only part num, and don't look for CPU revisions */ - switch (PARTID_NO_E(spridr)) { - case SPR_8377: - fsl_setup_serdes(CFG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - break; - case SPR_8378: - fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - break; - case SPR_8379: - fsl_setup_serdes(CFG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - break; - default: - printf("serdes not configured: unknown CPU part number: " - "%04x\n", spridr >> 16); - break; - } -#endif /* CONFIG_FSL_SERDES */ - -#ifdef CONFIG_FSL_ESDHC - clrsetbits_be32(&immr->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); - clrsetbits_be32(&immr->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD); -#endif - return 0; -} - -#ifdef CONFIG_FSL_ESDHC -#if !(CONFIG_IS_ENABLED(DM_MMC) || CONFIG_IS_ENABLED(DM_USB)) -int board_mmc_init(struct bd_info *bd) -{ - struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; - char buffer[HWCONFIG_BUFFER_SIZE] = {0}; - int esdhc_hwconfig_enabled = 0; - - if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0) - esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer); - - if (esdhc_hwconfig_enabled == 0) - return 0; - - clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); - clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD); - - return fsl_esdhc_mmc_init(bd); -} -#endif -#endif - -/* - * Miscellaneous late-boot configurations - * - * If a VSC7385 microcode image is present, then upload it. -*/ -int misc_init_r(void) -{ - int rc = 0; - -#ifdef CFG_VSC7385_IMAGE - if (vsc7385_upload_firmware((void *) CFG_VSC7385_IMAGE, - CFG_VSC7385_IMAGE_SIZE)) { - puts("Failure uploading VSC7385 microcode.\n"); - rc = 1; - } -#endif - - return rc; -} - -int board_late_init(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; -#ifdef CONFIG_USB_HOST - clrsetbits_be32(&immap->sysconf.sicrl, SICRL_USB_A, 0x40000000); -#endif - return 0; -} - -#if defined(CONFIG_OF_BOARD_SETUP) - -int ft_board_setup(void *blob, struct bd_info *bd) -{ -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - ft_cpu_setup(blob, bd); - fsl_fdt_fixup_dr_usb(blob, bd); - fdt_fixup_esdhc(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/freescale/mpc8548cds/Kconfig b/board/freescale/mpc8548cds/Kconfig deleted file mode 100644 index bb0a0758964..00000000000 --- a/board/freescale/mpc8548cds/Kconfig +++ /dev/null @@ -1,24 +0,0 @@ -if TARGET_MPC8548CDS - -config PCI1 - def_bool y - -config FSL_CADMUS - def_bool y - -config INTERRUPTS - def_bool y - -config SYS_BOARD - default "mpc8548cds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8548CDS" - -config TARGET_MPC8548CDS_LEGACY - bool "Legacy platform support" - -endif diff --git a/board/freescale/mpc8548cds/MAINTAINERS b/board/freescale/mpc8548cds/MAINTAINERS deleted file mode 100644 index fbbedb1d1d1..00000000000 --- a/board/freescale/mpc8548cds/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -MPC8548CDS BOARD -M: Priyanka Jain -S: Maintained -F: board/freescale/mpc8548cds/ -F: include/configs/MPC8548CDS.h -F: configs/MPC8548CDS_defconfig -F: configs/MPC8548CDS_36BIT_defconfig -F: configs/MPC8548CDS_legacy_defconfig diff --git a/board/freescale/mpc8548cds/Makefile b/board/freescale/mpc8548cds/Makefile deleted file mode 100644 index 5ed40e92eb9..00000000000 --- a/board/freescale/mpc8548cds/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2004 Freescale Semiconductor. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc8548cds.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c deleted file mode 100644 index 4b8ddcc3ae4..00000000000 --- a/board/freescale/mpc8548cds/ddr.c +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2008 Freescale Semiconductor, Inc. - */ - -#include -#include - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 7; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 10; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c deleted file mode 100644 index 2334870fda0..00000000000 --- a/board/freescale/mpc8548cds/law.c +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008,2010-2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include -#include -#include - -struct law_entry law_table[] = { - /* LBC window - maps 256M */ - SET_LAW(CFG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c deleted file mode 100644 index 7810010fd04..00000000000 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2002 Scott McNutt - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/cadmus.h" -#include "../common/eeprom.h" -#include "../common/via.h" - -void local_bus_init(void); - -int checkboard (void) -{ - volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR); - - /* PCI slot in USER bits CSR[6:7] by convention. */ - uint pci_slot = get_pci_slot (); - - uint cpu_board_rev = get_cpu_board_revision (); - - puts("Board: MPC8548CDS"); - printf(" Carrier Rev: 0x%02x, PCI Slot %d\n", - get_board_version(), pci_slot); - printf(" Daughtercard Rev: %d.%d (0x%04x)\n", - MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), - MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); - /* - * Initialize local bus. - */ - local_bus_init (); - - /* - * Hack TSEC 3 and 4 IO voltages. - */ - gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ - - ecm->eedr = 0xffffffff; /* clear ecm errors */ - ecm->eeer = 0xffffffff; /* enable ecm errors */ - return 0; -} - -/* - * Initialize Local Bus - */ -void -local_bus_init(void) -{ - volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - uint clkdiv; - sys_info_t sysinfo; - - get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; - - gur->lbiuiplldcr1 = 0x00078080; - if (clkdiv == 16) { - gur->lbiuiplldcr0 = 0x7c0f1bf0; - } else if (clkdiv == 8) { - gur->lbiuiplldcr0 = 0x6c0f1bf0; - } else if (clkdiv == 4) { - gur->lbiuiplldcr0 = 0x5c0f1bf0; - } - - lbc->lcrr |= 0x00030000; - - asm("sync;isync;msync"); - - lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ - lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ -} - -/* - * Initialize SDRAM memory on the Local Bus. - */ -void lbc_sdram_init(void) -{ -#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) - - uint idx; - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - uint *sdram_addr = (uint *)CFG_SYS_LBC_SDRAM_BASE; - uint lsdmr_common; - - puts("LBC SDRAM: "); - print_size(CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, - "\n"); - - /* - * Setup SDRAM Base and Option Registers - */ - set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); - set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - lbc->lbcr = CFG_SYS_LBC_LBCR; - asm("msync"); - - lbc->lsrt = CFG_SYS_LBC_LSRT; - lbc->mrtpr = CFG_SYS_LBC_MRTPR; - asm("msync"); - - /* - * MPC8548 uses "new" 15-16 style addressing. - */ - lsdmr_common = CFG_SYS_LBC_LSDMR_COMMON; - lsdmr_common |= LSDMR_BSMA1516; - - /* - * Issue PRECHARGE ALL command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue 8 AUTO REFRESH commands. - */ - for (idx = 0; idx < 8; idx++) { - lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - } - - /* - * Issue 8 MODE-set command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - /* - * Issue NORMAL OP command. - */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; - asm("sync;msync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(200); /* Overkill. Must wait > 200 bus cycles */ - -#endif /* enable SDRAM init */ -} diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c deleted file mode 100644 index 0b2afa8054d..00000000000 --- a/board/freescale/mpc8548cds/tlb.c +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008, 2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* - * Entry 0: - * FLASH(cover boot page) 16M Non-cacheable, guarded - */ - SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), - - /* - * Entry 1: - * CCSRBAR 1M Non-cacheable, guarded - */ - SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - - /* - * Entry 2: - * LBC SDRAM 64M Cacheable, non-guarded - */ - SET_TLB_ENTRY(1, CFG_SYS_LBC_SDRAM_BASE, - CFG_SYS_LBC_SDRAM_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 2, BOOKE_PAGESZ_64M, 1), - - /* - * Entry 3: - * CADMUS registers 1M Non-cacheable, guarded - */ - SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1M, 1), - - /* - * Entry 4: - * PCI and PCIe MEM 1G Non-cacheable, guarded - */ - SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_VIRT, CFG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_1G, 1), - - /* - * Entry 5: - * PCI1 IO 1M Non-cacheable, guarded - */ - SET_TLB_ENTRY(1, CFG_SYS_PCI1_IO_VIRT, CFG_SYS_PCI1_IO_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_1M, 1), - - /* - * Entry 6: - * PCIe IO 1M Non-cacheable, guarded - */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_1M, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mx23evk/Kconfig b/board/freescale/mx23evk/Kconfig deleted file mode 100644 index 51a8f9f773c..00000000000 --- a/board/freescale/mx23evk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX23EVK - -config SYS_BOARD - default "mx23evk" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "mx23evk" - -endif diff --git a/board/freescale/mx23evk/MAINTAINERS b/board/freescale/mx23evk/MAINTAINERS deleted file mode 100644 index 122b70cd719..00000000000 --- a/board/freescale/mx23evk/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -MX23EVK BOARD -M: Fabio Estevam -M: Otavio Salvador -S: Maintained -F: board/freescale/mx23evk/ -F: arch/arm/dts/imx23-evk.dts -F: include/configs/mx23evk.h -F: configs/mx23evk_defconfig diff --git a/board/freescale/mx23evk/Makefile b/board/freescale/mx23evk/Makefile deleted file mode 100644 index 5cc99ab1836..00000000000 --- a/board/freescale/mx23evk/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifndef CONFIG_XPL_BUILD -obj-y := mx23evk.o -else -obj-y := spl_boot.o -endif diff --git a/board/freescale/mx23evk/mx23evk.c b/board/freescale/mx23evk/mx23evk.c deleted file mode 100644 index fbc8fbdbf59..00000000000 --- a/board/freescale/mx23evk/mx23evk.c +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Freescale MX23EVK board - * - * (C) Copyright 2013 O.S. Systems Software LTDA. - * - * Author: Otavio Salvador - * - * Based on m28evk.c: - * Copyright (C) 2011 Marek Vasut - * on behalf of DENX Software Engineering GmbH - */ - -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Functions - */ -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - - /* SSP0 clock at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); - - /* Power on LCD */ - gpio_direction_output(MX23_PAD_LCD_RESET__GPIO_1_18, 1); - - /* Set contrast to maximum */ - gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1); - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} diff --git a/board/freescale/mx23evk/spl_boot.c b/board/freescale/mx23evk/spl_boot.c deleted file mode 100644 index a4c39a35221..00000000000 --- a/board/freescale/mx23evk/spl_boot.c +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Freescale MX23EVK Boot setup - * - * Copyright (C) 2011 Marek Vasut - * on behalf of DENX Software Engineering GmbH - */ - -#include -#include -#include -#include -#include - -#define MUX_CONFIG_SSP1 (MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_LCD (MXS_PAD_4MA | MXS_PAD_NOPULL) - -const iomux_cfg_t iomux_setup[] = { - /* DUART */ - MX23_PAD_PWM0__DUART_RX, - MX23_PAD_PWM1__DUART_TX, - - /* EMI */ - MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI, - MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI, - - MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI, - MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI, - MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - - MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, - MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, - MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - - /* MMC 0 */ - MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP1, - MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP1, - MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP1, - MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP1, - MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP1, - MX23_PAD_SSP1_DETECT__SSP1_DETECT | MUX_CONFIG_SSP1, - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX23_PAD_SSP1_SCK__SSP1_SCK | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* Write Protect Pin */ - MX23_PAD_PWM4__GPIO_1_30 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* Slot Power Enable */ - MX23_PAD_PWM3__GPIO_1_29 | - (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* LCD */ - MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, - MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, - MX23_PAD_GPMI_D08__LCD_D18 | MUX_CONFIG_LCD, - MX23_PAD_GPMI_D09__LCD_D19 | MUX_CONFIG_LCD, - MX23_PAD_GPMI_D10__LCD_D20 | MUX_CONFIG_LCD, - MX23_PAD_GPMI_D11__LCD_D21 | MUX_CONFIG_LCD, - MX23_PAD_GPMI_D12__LCD_D22 | MUX_CONFIG_LCD, - MX23_PAD_GPMI_D13__LCD_D23 | MUX_CONFIG_LCD, - MX23_PAD_LCD_DOTCK__LCD_DOTCK | MUX_CONFIG_LCD, - MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, - MX23_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD, - MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, - MX23_PAD_LCD_RESET__GPIO_1_18 | MUX_CONFIG_LCD, /* LCD power */ - MX23_PAD_PWM2__GPIO_1_28 | MUX_CONFIG_LCD, /* LCD contrast */ -}; - -#define HW_DRAM_CTL14 (0x38 >> 2) -#define CS_MAP 0x3 -#define INTAREF 0x2 -#define HW_DRAM_CTL14_CONFIG (INTAREF << 8 | CS_MAP) - -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG; -} - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); -} diff --git a/board/freescale/mx28evk/Kconfig b/board/freescale/mx28evk/Kconfig deleted file mode 100644 index 39777bd70fa..00000000000 --- a/board/freescale/mx28evk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX28EVK - -config SYS_BOARD - default "mx28evk" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mxs" - -config SYS_CONFIG_NAME - default "mx28evk" - -endif diff --git a/board/freescale/mx28evk/MAINTAINERS b/board/freescale/mx28evk/MAINTAINERS deleted file mode 100644 index f20baa91c67..00000000000 --- a/board/freescale/mx28evk/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MX28EVK BOARD -M: Fabio Estevam -S: Maintained -F: board/freescale/mx28evk/ -F: arch/arm/dts/imx28-evk.dts -F: include/configs/mx28evk.h -F: configs/mx28evk_defconfig diff --git a/board/freescale/mx28evk/Makefile b/board/freescale/mx28evk/Makefile deleted file mode 100644 index 1fd2a439f7a..00000000000 --- a/board/freescale/mx28evk/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -ifndef CONFIG_XPL_BUILD -obj-y := mx28evk.o -else -obj-y := iomux.o -endif diff --git a/board/freescale/mx28evk/README b/board/freescale/mx28evk/README deleted file mode 100644 index d32f0efb332..00000000000 --- a/board/freescale/mx28evk/README +++ /dev/null @@ -1,62 +0,0 @@ -FREESCALE MX28EVK -================== - -Supported hardware: MX28EVK rev C and D are supported in U-Boot. - -Files of the MX28EVK port --------------------------- - -arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28 -arch/arm/include/asm/arch-mxs/ - Header files for the Freescale i.MX28 -board/freescale/mx28evk/ - MX28EVK board specific files -include/configs/mx28evk.h - MX28EVK configuration file - -Jumper configuration ---------------------- - -To boot MX28EVK from an SD card, set the boot mode DIP switches as: - - * Boot Mode Select: 1 0 0 1 (Boot from SD card Slot 0 - U42) - * JTAG PSWITCH RESET: To the right (reset disabled) - * Battery Source: Down - * Wall 5V: Up - * VDD 5V: To the left (off) - * Hold Button: Down (off) - -To boot MX28EVK from SPI NOR flash, set the boot mode DIP switches as: - - * Boot Mode Select: 0 0 1 0 (Boot from SSP2) - * JTAG PSWITCH RESET: To the right (reset disabled) - * Battery Source: Down - * Wall 5V: Up - * VDD 5V: To the left (off) - * Hold Button: Down (off) - -Environment Storage -------------------- - -There are three targets for mx28evk: - -"make mx28evk_config" - store environment variables into MMC - -or - -"make mx28evk_nand_config" - store environment variables into NAND flash - -or - -"make mx28evk_spi_config" - store environment variables into SPI NOR flash - -Choose the target accordingly. - -Note: The mx28evk board does not come with a NAND flash populated from the -factory. It comes with an empty slot (U23), which allows the insertion of a -48-pin TSOP flash device. - -mx28evk does not come with SPI NOR flash populated from the factory either. -It is possible to solder a SOIC memory on U49 or use a DIP8 on J89. -To get SPI communication to work R320, R321,R322 and C178 need to be populated. -Look in the schematics for the proper component values. - -Follow the instructions from doc/imx/common/mxs.txt to generate a bootable -SD card or to generate a binary to be flashed into SPI NOR. diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c deleted file mode 100644 index b84b045bd1f..00000000000 --- a/board/freescale/mx28evk/iomux.c +++ /dev/null @@ -1,204 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Freescale MX28EVK IOMUX setup - * - * Copyright (C) 2011 Marek Vasut - * on behalf of DENX Software Engineering GmbH - */ - -#include -#include -#include -#include -#include - -#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) -#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) -#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) - -const iomux_cfg_t iomux_setup[] = { - /* DUART */ - MX28_PAD_PWM0__DUART_RX, - MX28_PAD_PWM1__DUART_TX, - - /* MMC0 */ - MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | - (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - MX28_PAD_SSP0_SCK__SSP0_SCK | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), - /* write protect */ - MX28_PAD_SSP1_SCK__GPIO_2_12, - /* MMC0 slot power enable */ - MX28_PAD_PWM3__GPIO_3_28 | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - -#ifdef CONFIG_NAND_MXS - /* GPMI NAND */ - MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RDN__GPMI_RDN | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), - MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, - MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, -#endif - - /* FEC0 */ - MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, - MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, - /* FEC0 Enable */ - MX28_PAD_SSP1_DATA3__GPIO_2_15 | - (MXS_PAD_12MA | MXS_PAD_3V3), - /* FEC0 Reset */ - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | - (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), - - /* FEC1 */ - MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET, - MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, - - /* EMI */ - MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, - MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, - - MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, - MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, - MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, - MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, - MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, - MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, - - /* SPI2 (for SPI flash) */ - MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, - MX28_PAD_SSP2_SS0__SSP2_D3 | - (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), - /* I2C */ - MX28_PAD_I2C0_SCL__I2C0_SCL, - MX28_PAD_I2C0_SDA__I2C0_SDA, - - /* LCD */ - MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD, - MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD, - MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD, - MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD, - MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD, - MX28_PAD_LCD_CS__LCD_ENABLE | MUX_CONFIG_LCD, - MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD, /* LCD power */ - MX28_PAD_PWM2__GPIO_3_18 | MUX_CONFIG_LCD, /* LCD contrast */ -}; - -#define HW_DRAM_CTL29 (0x74 >> 2) -#define CS_MAP 0xf -#define COLUMN_SIZE 0x2 -#define ADDR_PINS 0x1 -#define APREBIT 0xa - -#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \ - ADDR_PINS << 8 | APREBIT) - -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG; -} - -void board_init_ll(const uint32_t arg, const uint32_t *resptr) -{ - mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); -} diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c deleted file mode 100644 index ada572912da..00000000000 --- a/board/freescale/mx28evk/mx28evk.c +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Freescale MX28EVK board - * - * (C) Copyright 2011 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - * - * Based on m28evk.c: - * Copyright (C) 2011 Marek Vasut - * on behalf of DENX Software Engineering GmbH - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Functions - */ -int board_early_init_f(void) -{ - /* IO0 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK0, 480000); - /* IO1 clock at 480MHz */ - mxs_set_ioclk(MXC_IOCLK1, 480000); - - /* SSP0 clock at 96MHz */ - mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); - /* SSP2 clock at 160MHz */ - mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); - -#ifdef CONFIG_CMD_USB - mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); - mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 | - MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL); - gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1); -#endif - - /* Power on LCD */ - gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 1); - - /* Set contrast to maximum */ - gpio_direction_output(MX28_PAD_PWM2__GPIO_3_18, 1); - - return 0; -} - -int dram_init(void) -{ - return mxs_dram_init(); -} - -int board_init(void) -{ - /* Adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} diff --git a/board/freescale/mx51evk/Kconfig b/board/freescale/mx51evk/Kconfig deleted file mode 100644 index a26b539536e..00000000000 --- a/board/freescale/mx51evk/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -if TARGET_MX51EVK - -config SYS_BOARD - default "mx51evk" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mx5" - -config SYS_CONFIG_NAME - default "mx51evk" - -config IMX_CONFIG - default "board/freescale/mx51evk/imximage.cfg" - -endif diff --git a/board/freescale/mx51evk/MAINTAINERS b/board/freescale/mx51evk/MAINTAINERS deleted file mode 100644 index 025a5f8b582..00000000000 --- a/board/freescale/mx51evk/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX51EVK BOARD -M: Fabio Estevam -S: Maintained -F: board/freescale/mx51evk/ -F: include/configs/mx51evk.h -F: configs/mx51evk_defconfig diff --git a/board/freescale/mx51evk/Makefile b/board/freescale/mx51evk/Makefile deleted file mode 100644 index 808e35015e8..00000000000 --- a/board/freescale/mx51evk/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski -# -# (C) Copyright 2009 Freescale Semiconductor, Inc. - -obj-y += mx51evk.o diff --git a/board/freescale/mx51evk/imximage.cfg b/board/freescale/mx51evk/imximage.cfg deleted file mode 100644 index ff2ec4aa273..00000000000 --- a/board/freescale/mx51evk/imximage.cfg +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C Copyright 2009 - * Stefano Babic DENX Software Engineering sbabic@denx.de. - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM spi - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* Setting IOMUXC */ -DATA 4 0x73FA88a0 0x200 -DATA 4 0x73FA850c 0x20c5 -DATA 4 0x73FA8510 0x20c5 -DATA 4 0x73FA883c 0x2 -DATA 4 0x73FA8848 0x2 -DATA 4 0x73FA84b8 0xe7 -DATA 4 0x73FA84bc 0x45 -DATA 4 0x73FA84c0 0x45 -DATA 4 0x73FA84c4 0x45 -DATA 4 0x73FA84c8 0x45 -DATA 4 0x73FA8820 0x0 -DATA 4 0x73FA84a4 0x3 -DATA 4 0x73FA84a8 0x3 -DATA 4 0x73FA84ac 0xe3 -DATA 4 0x73FA84b0 0xe3 -DATA 4 0x73FA84b4 0xe3 -DATA 4 0x73FA84cc 0xe3 -DATA 4 0x73FA84d0 0xe2 - -DATA 4 0x73FA882c 0x6 -DATA 4 0x73FA88a4 0x6 -DATA 4 0x73FA88ac 0x6 -DATA 4 0x73FA88b8 0x6 - -/* - * Setting DDR for micron - * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model - * CAS=3 BL=4 - */ -/* ESDCTL_ESDCTL0 */ -DATA 4 0x83FD9000 0x82a20000 -/* ESDCTL_ESDCTL1 */ -DATA 4 0x83FD9008 0x82a20000 -/* ESDCTL_ESDMISC */ -DATA 4 0x83FD9010 0x000ad0d0 -/* ESDCTL_ESDCFG0 */ -DATA 4 0x83FD9004 0x333574aa -/* ESDCTL_ESDCFG1 */ -DATA 4 0x83FD900C 0x333574aa - -/* Init DRAM on CS0 */ -/* ESDCTL_ESDSCR */ -DATA 4 0x83FD9014 0x04008008 -DATA 4 0x83FD9014 0x0000801a -DATA 4 0x83FD9014 0x0000801b -DATA 4 0x83FD9014 0x00448019 -DATA 4 0x83FD9014 0x07328018 -DATA 4 0x83FD9014 0x04008008 -DATA 4 0x83FD9014 0x00008010 -DATA 4 0x83FD9014 0x00008010 -DATA 4 0x83FD9014 0x06328018 -DATA 4 0x83FD9014 0x03808019 -DATA 4 0x83FD9014 0x00408019 -DATA 4 0x83FD9014 0x00008000 - -/* Init DRAM on CS1 */ -DATA 4 0x83FD9014 0x0400800c -DATA 4 0x83FD9014 0x0000801e -DATA 4 0x83FD9014 0x0000801f -DATA 4 0x83FD9014 0x0000801d -DATA 4 0x83FD9014 0x0732801c -DATA 4 0x83FD9014 0x0400800c -DATA 4 0x83FD9014 0x00008014 -DATA 4 0x83FD9014 0x00008014 -DATA 4 0x83FD9014 0x0632801c -DATA 4 0x83FD9014 0x0380801d -DATA 4 0x83FD9014 0x0040801d -DATA 4 0x83FD9014 0x00008004 - -/* Write to CTL0 */ -DATA 4 0x83FD9000 0xb2a20000 -/* Write to CTL1 */ -DATA 4 0x83FD9008 0xb2a20000 -/* ESDMISC */ -DATA 4 0x83FD9010 0x000ad6d0 -/* ESDCTL_ESDCDLYGD */ -DATA 4 0x83FD9034 0x90000000 -DATA 4 0x83FD9014 0x00000000 diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c deleted file mode 100644 index 69456842302..00000000000 --- a/board/freescale/mx51evk/mx51evk.c +++ /dev/null @@ -1,220 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); - return 0; -} - -#ifdef CONFIG_REVISION_TAG -u32 get_board_rev(void) -{ - u32 rev = get_cpu_rev(); - if (!gpio_get_value(IMX_GPIO_NR(1, 22))) - rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET; - return rev; -} -#endif - -#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH) - -static void setup_iomux_uart(void) -{ - static const iomux_v3_cfg_t uart_pads[] = { - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL), - NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); -} - -#ifdef CONFIG_MXC_SPI -static void setup_iomux_spi(void) -{ - static const iomux_v3_cfg_t spi_pads[] = { - NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS | - PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS | - PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), - NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, - MX51_GPIO_PAD_CTRL), - MX51_PAD_CSPI1_SS0__ECSPI1_SS0, - NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2), - NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS | - PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), - }; - - imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); -} -#endif - -static void power_init(void) -{ - unsigned int val; - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; - struct pmic *p; - int ret; - - ret = pmic_init(CFG_FSL_PMIC_BUS); - if (ret) - return; - - p = pmic_get("FSL_PMIC"); - if (!p) - return; - - /* Write needed to Power Gate 2 register */ - pmic_reg_read(p, REG_POWER_MISC, &val); - val &= ~PWGT2SPIEN; - pmic_reg_write(p, REG_POWER_MISC, val); - - /* Externally powered */ - pmic_reg_read(p, REG_CHARGE, &val); - val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB; - pmic_reg_write(p, REG_CHARGE, val); - - /* power up the system first */ - pmic_reg_write(p, REG_POWER_MISC, PWUP); - - /* Set core voltage to 1.1V */ - pmic_reg_read(p, REG_SW_0, &val); - val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; - pmic_reg_write(p, REG_SW_0, val); - - /* Setup VCC (SW2) to 1.25 */ - pmic_reg_read(p, REG_SW_1, &val); - val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; - pmic_reg_write(p, REG_SW_1, val); - - /* Setup 1V2_DIG1 (SW3) to 1.25 */ - pmic_reg_read(p, REG_SW_2, &val); - val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; - pmic_reg_write(p, REG_SW_2, val); - udelay(50); - - /* Raise the core frequency to 800MHz */ - writel(0x0, &mxc_ccm->cacrr); - - /* Set switchers in Auto in NORMAL mode & STANDBY mode */ - /* Setup the switcher mode for SW1 & SW2*/ - pmic_reg_read(p, REG_SW_4, &val); - val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | - (SWMODE_MASK << SWMODE2_SHIFT))); - val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | - (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); - pmic_reg_write(p, REG_SW_4, val); - - /* Setup the switcher mode for SW3 & SW4 */ - pmic_reg_read(p, REG_SW_5, &val); - val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) | - (SWMODE_MASK << SWMODE4_SHIFT))); - val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) | - (SWMODE_AUTO_AUTO << SWMODE4_SHIFT); - pmic_reg_write(p, REG_SW_5, val); - - /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */ - pmic_reg_read(p, REG_SETTING_0, &val); - val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); - val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6; - pmic_reg_write(p, REG_SETTING_0, val); - - /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ - pmic_reg_read(p, REG_SETTING_1, &val); - val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); - val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775; - pmic_reg_write(p, REG_SETTING_1, val); - - /* Configure VGEN3 and VCAM regulators to use external PNP */ - val = VGEN3CONFIG | VCAMCONFIG; - pmic_reg_write(p, REG_MODE_1, val); - udelay(200); - - /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ - val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | - VVIDEOEN | VAUDIOEN | VSDEN; - pmic_reg_write(p, REG_MODE_1, val); - - imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14, - NO_PAD_CTRL)); - gpio_request(IMX_GPIO_NR(2, 14), "gpio2_14"); - gpio_direction_output(IMX_GPIO_NR(2, 14), 0); - - udelay(500); - - gpio_set_value(IMX_GPIO_NR(2, 14), 1); -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - setup_iomux_lcd(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ -#ifdef CONFIG_MXC_SPI - setup_iomux_spi(); - power_init(); -#endif - - return 0; -} -#endif - -/* - * Do not overwrite the console - * Use always serial for U-Boot console - */ -int overwrite_console(void) -{ - return 1; -} - -int checkboard(void) -{ - puts("Board: MX51EVK\n"); - - return 0; -} diff --git a/board/freescale/mx53loco/Kconfig b/board/freescale/mx53loco/Kconfig deleted file mode 100644 index 5dcdcd9f725..00000000000 --- a/board/freescale/mx53loco/Kconfig +++ /dev/null @@ -1,21 +0,0 @@ -if TARGET_MX53LOCO - -config DIALOG_POWER - def_bool y - -config SYS_BOARD - default "mx53loco" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mx5" - -config SYS_CONFIG_NAME - default "mx53loco" - -config IMX_CONFIG - default "board/freescale/mx53loco/imximage.cfg" - -endif diff --git a/board/freescale/mx53loco/MAINTAINERS b/board/freescale/mx53loco/MAINTAINERS deleted file mode 100644 index 6c237518773..00000000000 --- a/board/freescale/mx53loco/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MX53LOCO BOARD -M: Fabio Estevam -M: Jason Liu -S: Maintained -F: board/freescale/mx53loco/ -F: include/configs/mx53loco.h -F: configs/mx53loco_defconfig diff --git a/board/freescale/mx53loco/Makefile b/board/freescale/mx53loco/Makefile deleted file mode 100644 index 9befe426957..00000000000 --- a/board/freescale/mx53loco/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. -# Jason Liu - -obj-y += mx53loco.o diff --git a/board/freescale/mx53loco/imximage.cfg b/board/freescale/mx53loco/imximage.cfg deleted file mode 100644 index d12801d19f2..00000000000 --- a/board/freescale/mx53loco/imximage.cfg +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. - * Jason Liu - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -DATA 4 0x53fa8554 0x00300000 -DATA 4 0x53fa8558 0x00300040 -DATA 4 0x53fa8560 0x00300000 -DATA 4 0x53fa8564 0x00300040 -DATA 4 0x53fa8568 0x00300040 -DATA 4 0x53fa8570 0x00300000 -DATA 4 0x53fa8574 0x00300000 -DATA 4 0x53fa8578 0x00300000 -DATA 4 0x53fa857c 0x00300040 -DATA 4 0x53fa8580 0x00300040 -DATA 4 0x53fa8584 0x00300000 -DATA 4 0x53fa8588 0x00300000 -DATA 4 0x53fa8590 0x00300040 -DATA 4 0x53fa8594 0x00300000 -DATA 4 0x53fa86f0 0x00300000 -DATA 4 0x53fa86f4 0x00000000 -DATA 4 0x53fa86fc 0x00000000 -DATA 4 0x53fa8714 0x00000000 -DATA 4 0x53fa8718 0x00300000 -DATA 4 0x53fa871c 0x00300000 -DATA 4 0x53fa8720 0x00300000 -DATA 4 0x53fa8724 0x04000000 -DATA 4 0x53fa8728 0x00300000 -DATA 4 0x53fa872c 0x00300000 -DATA 4 0x63fd9088 0x35343535 -DATA 4 0x63fd9090 0x4d444c44 -DATA 4 0x63fd907c 0x01370138 -DATA 4 0x63fd9080 0x013b013c -DATA 4 0x63fd9018 0x00011740 -DATA 4 0x63fd9000 0x83190000 -DATA 4 0x63fd900c 0x9f5152e3 -DATA 4 0x63fd9010 0xb68e8a63 -DATA 4 0x63fd9014 0x01ff00db -DATA 4 0x63fd902c 0x000026d2 -DATA 4 0x63fd9030 0x009f0e21 -DATA 4 0x63fd9008 0x12273030 -DATA 4 0x63fd9004 0x0002002d -DATA 4 0x63fd901c 0x00008032 -DATA 4 0x63fd901c 0x00008033 -DATA 4 0x63fd901c 0x00028031 -DATA 4 0x63fd901c 0x052080b0 -DATA 4 0x63fd901c 0x04008040 -DATA 4 0x63fd9000 0xc3190000 -DATA 4 0x63fd901c 0x0000803a -DATA 4 0x63fd901c 0x0000803b -DATA 4 0x63fd901c 0x00028039 -DATA 4 0x63fd901c 0x05208138 -DATA 4 0x63fd901c 0x04008048 -DATA 4 0x63fd9020 0x00005800 -DATA 4 0x63fd9040 0x05380003 -DATA 4 0x63fd9058 0x00022227 -DATA 4 0x63fd901c 0x00000000 diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c deleted file mode 100644 index 2d8f5da9906..00000000000 --- a/board/freescale/mx53loco/mx53loco.c +++ /dev/null @@ -1,246 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. - * Jason Liu - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24) - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_REVISION_TAG -u32 get_board_rev(void) -{ - struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; - struct fuse_bank *bank = &iim->bank[0]; - struct fuse_bank0_regs *fuse = - (struct fuse_bank0_regs *)bank->fuse_regs; - struct udevice *bus; - struct udevice *dev; - - int rev = readl(&fuse->gp[6]); - - ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); - if (ret) - return ret; - - if (!dm_i2c_probe(bus, CFG_SYS_DIALOG_PMIC_I2C_ADDR, 0, &dev)) - rev = 0; - - return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; -} -#endif - -#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) - -static void setup_iomux_uart(void) -{ - static const iomux_v3_cfg_t uart_pads[] = { - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); -} - -static int power_init(void) -{ - unsigned int val; - int ret; - struct pmic *p; - struct udevice *bus; - struct udevice *dev; - - ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); - if (ret) - return ret; - - if (!dm_i2c_probe(bus, CFG_SYS_DIALOG_PMIC_I2C_ADDR, 0, &dev)) { - ret = pmic_dialog_init(I2C_PMIC); - if (ret) - return ret; - - p = pmic_get("DIALOG_PMIC"); - if (!p) - return -ENODEV; - - env_set("fdt_file", "imx53-qsb.dtb"); - - /* Set VDDA to 1.25V */ - val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; - ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); - if (ret) { - printf("Writing to BUCKCORE_REG failed: %d\n", ret); - return ret; - } - - pmic_reg_read(p, DA9053_SUPPLY_REG, &val); - val |= DA9052_SUPPLY_VBCOREGO; - ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val); - if (ret) { - printf("Writing to SUPPLY_REG failed: %d\n", ret); - return ret; - } - - /* Set Vcc peripheral to 1.30V */ - ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); - if (ret) { - printf("Writing to BUCKPRO_REG failed: %d\n", ret); - return ret; - } - - ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); - if (ret) { - printf("Writing to SUPPLY_REG failed: %d\n", ret); - return ret; - } - - return ret; - } - - if (!dm_i2c_probe(bus, CFG_SYS_FSL_PMIC_I2C_ADDR, 0, &dev)) { - ret = pmic_init(0); - if (ret) - return ret; - - p = pmic_get("FSL_PMIC"); - if (!p) - return -ENODEV; - - env_set("fdt_file", "imx53-qsrb.dtb"); - - /* Set VDDGP to 1.25V for 1GHz on SW1 */ - pmic_reg_read(p, REG_SW_0, &val); - val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708; - ret = pmic_reg_write(p, REG_SW_0, val); - if (ret) { - printf("Writing to REG_SW_0 failed: %d\n", ret); - return ret; - } - - /* Set VCC as 1.30V on SW2 */ - pmic_reg_read(p, REG_SW_1, &val); - val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708; - ret = pmic_reg_write(p, REG_SW_1, val); - if (ret) { - printf("Writing to REG_SW_1 failed: %d\n", ret); - return ret; - } - - /* Set global reset timer to 4s */ - pmic_reg_read(p, REG_POWER_CTL2, &val); - val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708; - ret = pmic_reg_write(p, REG_POWER_CTL2, val); - if (ret) { - printf("Writing to REG_POWER_CTL2 failed: %d\n", ret); - return ret; - } - - /* Set VUSBSEL and VUSBEN for USB PHY supply*/ - pmic_reg_read(p, REG_MODE_0, &val); - val |= (VUSBSEL_MC34708 | VUSBEN_MC34708); - ret = pmic_reg_write(p, REG_MODE_0, val); - if (ret) { - printf("Writing to REG_MODE_0 failed: %d\n", ret); - return ret; - } - - /* Set SWBST to 5V in auto mode */ - val = SWBST_AUTO; - ret = pmic_reg_write(p, SWBST_CTRL, val); - if (ret) { - printf("Writing to SWBST_CTRL failed: %d\n", ret); - return ret; - } - - return ret; - } - - return -1; -} - -static void clock_1GHz(void) -{ - int ret; - u32 ref_clk = MXC_HCLK; - /* - * After increasing voltage to 1.25V, we can switch - * CPU clock to 1GHz and DDR to 400MHz safely - */ - ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); - if (ret) - printf("CPU: Switch CPU clock to 1GHZ failed\n"); - - ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); - ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); - if (ret) - printf("CPU: Switch DDR clock to 400MHz failed\n"); -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - setup_iomux_lcd(); - - return 0; -} - -/* - * Do not overwrite the console - * Use always serial for U-Boot console - */ -int overwrite_console(void) -{ - return 1; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - mxc_set_sata_internal_clock(); - - return 0; -} - -int board_late_init(void) -{ - if (!power_init()) - clock_1GHz(); - - return 0; -} - -int checkboard(void) -{ - puts("Board: MX53 LOCO\n"); - - return 0; -} diff --git a/board/freescale/mx6memcal/Kconfig b/board/freescale/mx6memcal/Kconfig deleted file mode 100644 index 2d5c206ae45..00000000000 --- a/board/freescale/mx6memcal/Kconfig +++ /dev/null @@ -1,230 +0,0 @@ -if TARGET_MX6MEMCAL - -config SYS_BOARD - default "mx6memcal" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "mx6memcal" - -menu "mx6memcal specifics" -choice - prompt "Serial console" - help - Either UART1 or UART2 will be used as the console for - displaying the calibration values or errors. - -config SERIAL_CONSOLE_UART1 - bool "UART1" - help - Select this if your board uses UART1 for its' console. - -config SERIAL_CONSOLE_UART2 - bool "UART2" - help - Select this if your board uses UART2 for its' console. - -endchoice - -choice - prompt "UART pads" - help - Select the RX and TX pads used for your serial console. - The choices below reflect the most commonly used options - for your UART. - - config UART2_EIM_D26_27 - bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)" - depends on SERIAL_CONSOLE_UART2 - help - Choose this configuration if you're using pads - EIM_D26 and D27 for a console on UART2. - This is typical for designs that are based on the - NXP SABRELite. - - config UART1_CSI0_DAT10_11 - bool "UART1 on CSI0_DAT10/11 (Wand, SabreSD)" - depends on SERIAL_CONSOLE_UART1 - help - Choose this configuration if you're using pads - CSI0_DAT10 and DAT11 for a console on UART1 as - is done on the i.MX6 Wand board and i.MX6 SabreSD. - - config UART1_UART1 - bool "UART1 on UART1 (i.MX6SL EVK, WaRP)" - depends on SERIAL_CONSOLE_UART1 - help - Choose this configuration if you're using pads - UART1_TXD/RXD for a console on UART1 as is done - on most i.MX6SL designs. - -endchoice - -config IMXIMAGE_OUTPUT - bool "Include output for imximage .cfg files" - default y - help - Say "Y" if you want output formatted for use in non-SPL - (DCD-style) configuration files. - -config DDRWIDTH - int "DDR bus width" - default 64 - help - Select either 32 or 64 to reflect the DDR bus width. - -config DDRCS - int "DDR chip selects" - default 2 - range 1 2 - help - Select the number of chip selects used in your board design - -choice - prompt "Memory type" - help - Select the type of DDR (DDR3 or LPDDR2) used on your design - -config DDR3 - bool "DDR3" - help - Select this if your board design uses DDR3. - -config LPDDR2 - bool "LPDDR2" - help - Select this if your board design uses LPDDR2. - -endchoice - -choice - prompt "Memory device" - -config MT41K512M16TNA - bool "Micron MT41K512M16TNA 512Mx16 (1GiB/chip)" - depends on DDR3 - -config MT41K128M16JT - bool "Micron MT41K128M16JT 128Mx16 (256 MiB/chip)" - depends on DDR3 - -config H5TQ4G63AFR - bool "Hynix H5TQ4G63AFR 256Mx16 (512 MiB/chip)" - depends on DDR3 - -config H5TQ2G63DFR - bool "Hynix H5TQ2G63DFR 128Mx16 (256 MiB/chip)" - depends on DDR3 - -config MT42L256M32D2LG - bool "Micron MT42L256M32D2LG LPDDR2 256Mx32 (1GiB/chip)" - depends on LPDDR2 - -config MT29PZZZ4D4BKESK - bool "Micron MT29PZZZ4D4BKESK multi-chip 512MiB LPDDR2/4GiB eMMC" - depends on LPDDR2 - -endchoice - -config DDR_ODT - int "DDR On-die-termination" - default 2 - range 0 7 - help - Enter the on-die termination value as an index defined for - IOMUX settings for PAD_DRAM_SDCLK0_P and others. - 0 == Disabled - 1 == 120 Ohm - 2 == 60 Ohm - 3 == 40 Ohm - 4 == 30 Ohm - 5 == 24 Ohm - 6 == 20 Ohm - 7 == 17 Ohm - Value will be applied to all clock and data lines - - -config DRAM_DRIVE_STRENGTH - int "DRAM Drive strength" - default 6 - range 0 7 - help - Enter drive strength as an index defined for IOMUX settings - for GRP_B1DS and others. - 0 == Hi Z - 6 == 40 Ohm (default) - 7 == 34 Ohm - Value will be applied to all clock and data lines - -config RTT_NOM - int "RTT_NOM" - default 1 - range 1 2 - help - Enter the RTT_NOM selector - 1 == RZQ/4 (60ohm) - 2 == RZQ/2 (120ohm) - -config RTT_WR - int "RTT_WR" - default 1 - range 0 2 - help - Enter the RTT_WR selector for MR2 - 0 == Dynamic ODT disabled - 1 == RZQ/4 (60ohm) - 2 == RZQ/2 (120ohm) - -config RALAT - int "Read additional latency" - default 5 - range 0 7 - help - Enter a latency in number of cycles. This will be added to - CAS and internal delays for which the MMDC will retrieve the - read data from the internal FIFO. - This is used to compensate for board/chip delays. - -config WALAT - int "Write additional latency" - default 0 - range 0 7 - help - Enter a latency in number of cycles. This will be added to - CAS and internal delays for which the MMDC will retrieve the - read data from the internal FIFO - This is used to compensate for board/chip delays. - -config REFSEL - int "Refresh period" - range 0 3 - default 1 - help - Select the DDR refresh period. - See the description of bitfield REF_SEL in the reference manual - for details. - 0 == disabled - 1 == 32 kHz - 2 == 64 kHz - 3 == fast counter - -config REFR - int "Number of refreshes" - range 0 7 - default 7 - help - This selects the number of refreshes (-1) during each period. - i.e.: - 0 == 1 refresh (tRFC) - 7 == 8 refreshes (tRFC*8) - See the description of MDREF[REFR] in the reference manual for - details. - -endmenu - -config IMX_CONFIG - default "arch/arm/mach-imx/spl_sd.cfg" - -endif diff --git a/board/freescale/mx6memcal/MAINTAINERS b/board/freescale/mx6memcal/MAINTAINERS deleted file mode 100644 index 5da38f7109b..00000000000 --- a/board/freescale/mx6memcal/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MX6MEMCAL BOARD -M: Eric Nelson -S: Maintained -F: board/freescale/mx6memcal/ -F: include/configs/mx6memcal.h -F: configs/mx6memcal_defconfig - diff --git a/board/freescale/mx6memcal/Makefile b/board/freescale/mx6memcal/Makefile deleted file mode 100644 index b4088b9f2ec..00000000000 --- a/board/freescale/mx6memcal/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. - -ifdef CONFIG_XPL_BUILD -obj-y := spl.o -else -obj-y := mx6memcal.o -endif diff --git a/board/freescale/mx6memcal/README b/board/freescale/mx6memcal/README deleted file mode 100644 index 9fe2fe2d043..00000000000 --- a/board/freescale/mx6memcal/README +++ /dev/null @@ -1,49 +0,0 @@ -mx6memcal - a tool for calibrating DDR on i.MX6 boards. - -The mx6memcal board isn't a real board, but a tool for use in bring-up of -new i.MX6 board designs. - -It provides a similar function to the tool from NXP([1]) with a number -of advantages: - -1. It's open-source, so it's easier to change if needed. - Typical reasons for needing to change include the use of alternate - UARTs and PMIC initialization. -2. It produces an image that's directly loadable with imx_usb [2] or - SB_LOADER.exe [3]. - The NXP tool requires either a cumbersome JTAG connection that - makes running the DDR very slow or a working U-Boot image that - suffers from a chicken-and-egg problem (i.e. where do you get the - DDR parameters for U-Boot?). -3. It doesn't prompt for parameters, so it's much faster to gather - data from multiple boards. -4. Parameters to the calibration process can be chosen through - 'make menuconfig'. - -When booted, the mx6memcal board will run the DDR calibration -routines and display the result in a form suitable for cut and -paste into struct mx6_mmdc_calibration. It can also optionally -produce output in a form usable in a DCD-style .cfg file. - -Selections in Kconfig allow most system design settings to be chosen: - -1. The UART number and pad configuration for the UART. Options - include support for the most frequent reference designs on - i.MX6DQ/SDL (SABRE Lite and SABRESD designs). -2. The memory bus width (64 and 32-bit) -3. The number of chip-selects in use -4. The type of DDR (DDR3 or LPDDR2). Note that LPDDR2 support - is incomplete as of this writing. -5. The type of DDR chips in use. This selection allows re-use of common - parts and four DDR3 and two LPDDR2 parts are currently defined -6. The On-die termination value for the DRAM lines -7. The DRAM drive strength -8. The RTT_NOM and RTT_WR termination settings -9. RALAT/WALAT latency values - -References: -[1] - NXP DDR Stress Test Tool - https://community.nxp.com/docs/DOC-105652 -[2] - Boundary Devices imx_usb_loader - https://github.com/boundarydevices/imx_usb_loader -[3] - Use of SB_Loader.exe - https://boundarydevices.com/windows-users-and-unbricking diff --git a/board/freescale/mx6memcal/mx6memcal.c b/board/freescale/mx6memcal/mx6memcal.c deleted file mode 100644 index a58ab93f27d..00000000000 --- a/board/freescale/mx6memcal/mx6memcal.c +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * mx6memcal board support - provides a minimal, UART-only - * U-Boot that's capable of running a memory test. - * - * Copyright (C) 2016 Nelson Integration, LLC - * Author: Eric Nelson - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("Board: mx6memcal\n"); - return 0; -} - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - return 0; -} diff --git a/board/freescale/mx6memcal/spl.c b/board/freescale/mx6memcal/spl.c deleted file mode 100644 index bc9c4259f07..00000000000 --- a/board/freescale/mx6memcal/spl.c +++ /dev/null @@ -1,457 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 Nelson Integration, LLC - * Author: Eric Nelson - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -static iomux_v3_cfg_t const uart_pads[] = { -#ifdef CONFIG_UART2_EIM_D26_27 - IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -#elif defined(CONFIG_UART1_CSI0_DAT10_11) - IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -#elif defined(CONFIG_UART1_SD3_DAT6_7) - IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -#elif defined(CONFIG_UART1_UART1) - MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), -#else -#error select UART console pads -#endif -}; - -#ifdef CONFIG_DDR3 -#define GRP_DDRTYPE 0x000C0000 -#else -#define GRP_DDRTYPE 0x00080000 -#endif - -/* all existing designs have this disabled */ -#define DDR_PKE 0 - -/* use Kconfig for ODT and DRIVE_STRENGTH */ -#define DDR_ODT \ - (CONFIG_DDR_ODT << 8) -#define DRAM_DRIVE_STRENGTH \ - (CONFIG_DRAM_DRIVE_STRENGTH << 3) - -/* configure MX6Q/DUAL mmdc DDR io registers */ -static struct mx6dq_iomux_ddr_regs const mx6dq_ddr_ioregs = { - /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ - .dram_sdclk_0 = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_sdclk_1 = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_cas = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_ras = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_reset = DDR_ODT + DRAM_DRIVE_STRENGTH, - /* SDCKE[0:1]: 100k pull-up */ - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - /* SDBA2: pull-up disabled */ - .dram_sdba2 = 0x00000000, - /* SDODT[0:1]: 100k pull-up, 40 ohm */ - .dram_sdodt0 = 0x00003000 + DRAM_DRIVE_STRENGTH, - .dram_sdodt1 = 0x00003000 + DRAM_DRIVE_STRENGTH, - /* SDQS[0:7]: Differential input, 40 ohm */ - .dram_sdqs0 = DRAM_DRIVE_STRENGTH, - .dram_sdqs1 = DRAM_DRIVE_STRENGTH, - .dram_sdqs2 = DRAM_DRIVE_STRENGTH, - .dram_sdqs3 = DRAM_DRIVE_STRENGTH, - .dram_sdqs4 = DRAM_DRIVE_STRENGTH, - .dram_sdqs5 = DRAM_DRIVE_STRENGTH, - .dram_sdqs6 = DRAM_DRIVE_STRENGTH, - .dram_sdqs7 = DRAM_DRIVE_STRENGTH, - - /* DQM[0:7]: Differential input, 40 ohm */ - .dram_dqm0 = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_dqm1 = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_dqm2 = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_dqm3 = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_dqm4 = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_dqm5 = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_dqm6 = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_dqm7 = DDR_ODT + DRAM_DRIVE_STRENGTH, -}; - -/* configure MX6Q/DUAL mmdc GRP io registers */ -static struct mx6dq_iomux_grp_regs const mx6dq_grp_ioregs = { - /* DDR3 */ - .grp_ddr_type = GRP_DDRTYPE, - .grp_ddrmode_ctl = DDR_ODT, - /* disable DDR pullups */ - .grp_ddrpke = DDR_PKE, - /* ADDR[00:16], SDBA[0:1]: 40 ohm */ - .grp_addds = DRAM_DRIVE_STRENGTH, - /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ - .grp_ctlds = DRAM_DRIVE_STRENGTH, - /* DATA[00:63]: Differential input, 40 ohm */ - .grp_ddrmode = DDR_ODT, - .grp_b0ds = DRAM_DRIVE_STRENGTH, - .grp_b1ds = DRAM_DRIVE_STRENGTH, - .grp_b2ds = DRAM_DRIVE_STRENGTH, - .grp_b3ds = DRAM_DRIVE_STRENGTH, - .grp_b4ds = DRAM_DRIVE_STRENGTH, - .grp_b5ds = DRAM_DRIVE_STRENGTH, - .grp_b6ds = DRAM_DRIVE_STRENGTH, - .grp_b7ds = DRAM_DRIVE_STRENGTH, -}; - -static struct mx6sdl_iomux_ddr_regs const mx6sdl_ddr_ioregs = { - /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ - .dram_sdclk_0 = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_sdclk_1 = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_cas = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_ras = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_reset = DDR_ODT + DRAM_DRIVE_STRENGTH, - /* SDCKE[0:1]: 100k pull-up */ - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - /* SDBA2: pull-up disabled */ - .dram_sdba2 = 0x00000000, - /* SDODT[0:1]: 100k pull-up, 40 ohm */ - .dram_sdodt0 = 0x00003000 + DRAM_DRIVE_STRENGTH, - .dram_sdodt1 = 0x00003000 + DRAM_DRIVE_STRENGTH, - /* SDQS[0:7]: Differential input, 40 ohm */ - .dram_sdqs0 = DRAM_DRIVE_STRENGTH, - .dram_sdqs1 = DRAM_DRIVE_STRENGTH, - .dram_sdqs2 = DRAM_DRIVE_STRENGTH, - .dram_sdqs3 = DRAM_DRIVE_STRENGTH, - .dram_sdqs4 = DRAM_DRIVE_STRENGTH, - .dram_sdqs5 = DRAM_DRIVE_STRENGTH, - .dram_sdqs6 = DRAM_DRIVE_STRENGTH, - .dram_sdqs7 = DRAM_DRIVE_STRENGTH, - - /* DQM[0:7]: Differential input, 40 ohm */ - .dram_dqm0 = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_dqm1 = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_dqm2 = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_dqm3 = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_dqm4 = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_dqm5 = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_dqm6 = DDR_ODT + DRAM_DRIVE_STRENGTH, - .dram_dqm7 = DDR_ODT + DRAM_DRIVE_STRENGTH, -}; - -/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ -static struct mx6sdl_iomux_grp_regs const mx6sdl_grp_ioregs = { - /* DDR3 */ - .grp_ddr_type = GRP_DDRTYPE, - /* SDQS[0:7]: Differential input, 40 ohm */ - .grp_ddrmode_ctl = DDR_ODT, - /* disable DDR pullups */ - .grp_ddrpke = DDR_PKE, - /* ADDR[00:16], SDBA[0:1]: 40 ohm */ - .grp_addds = DRAM_DRIVE_STRENGTH, - /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ - .grp_ctlds = DRAM_DRIVE_STRENGTH, - /* DATA[00:63]: Differential input, 40 ohm */ - .grp_ddrmode = DDR_ODT, - .grp_b0ds = DRAM_DRIVE_STRENGTH, - .grp_b1ds = DRAM_DRIVE_STRENGTH, - .grp_b2ds = DRAM_DRIVE_STRENGTH, - .grp_b3ds = DRAM_DRIVE_STRENGTH, - .grp_b4ds = DRAM_DRIVE_STRENGTH, - .grp_b5ds = DRAM_DRIVE_STRENGTH, - .grp_b6ds = DRAM_DRIVE_STRENGTH, - .grp_b7ds = DRAM_DRIVE_STRENGTH, -}; - -const struct mx6sl_iomux_ddr_regs mx6sl_ddr_ioregs = { - .dram_sdqs0 = DRAM_DRIVE_STRENGTH, - .dram_sdqs1 = DRAM_DRIVE_STRENGTH, - .dram_sdqs2 = DRAM_DRIVE_STRENGTH, - .dram_sdqs3 = DRAM_DRIVE_STRENGTH, - .dram_dqm0 = DRAM_DRIVE_STRENGTH, - .dram_dqm1 = DRAM_DRIVE_STRENGTH, - .dram_dqm2 = DRAM_DRIVE_STRENGTH, - .dram_dqm3 = DRAM_DRIVE_STRENGTH, - .dram_cas = DRAM_DRIVE_STRENGTH, - .dram_ras = DRAM_DRIVE_STRENGTH, - .dram_sdclk_0 = DRAM_DRIVE_STRENGTH, - .dram_reset = DRAM_DRIVE_STRENGTH, - .dram_sdba2 = 0x00020000, - .dram_odt0 = 0x00030000 + DRAM_DRIVE_STRENGTH, - .dram_odt1 = 0x00030000 + DRAM_DRIVE_STRENGTH, -}; - -const struct mx6sl_iomux_grp_regs mx6sl_grp_ioregs = { - .grp_b0ds = DRAM_DRIVE_STRENGTH, - .grp_b1ds = DRAM_DRIVE_STRENGTH, - .grp_b2ds = DRAM_DRIVE_STRENGTH, - .grp_b3ds = DRAM_DRIVE_STRENGTH, - .grp_addds = DRAM_DRIVE_STRENGTH, - .grp_ctlds = DRAM_DRIVE_STRENGTH, - .grp_ddrmode_ctl = DDR_ODT, - .grp_ddrpke = DDR_PKE, - .grp_ddrmode = DDR_ODT, - .grp_ddr_type = GRP_DDRTYPE, -}; - -static struct mx6_ddr_sysinfo const sysinfo = { - /* width of data bus:0=16,1=32,2=64 */ -#if CONFIG_DDRWIDTH == 32 - .dsize = 1, -#elif CONFIG_DDRWIDTH == 64 - .dsize = 2, -#else -#error missing CONFIG_DDRWIDTH -#endif - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, /* 32Gb per CS */ - - /* # of chip selects */ - .ncs = CONFIG_DDRCS, - .cs1_mirror = 0, - .bi_on = 1, /* Bank interleaving enabled */ - .rtt_nom = CONFIG_RTT_NOM, - .rtt_wr = CONFIG_RTT_WR, - .ralat = CONFIG_RALAT, /* Read additional latency */ - .walat = CONFIG_WALAT, /* Write additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ -#ifdef CONFIG_DDR3 - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .sde_to_rst = 0x10, /* JEDEC value for LPDDR2 - 200us */ - .pd_fast_exit = 0, /* immaterial for calibration */ - .ddr_type = DDR_TYPE_DDR3, -#else - .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ - .sde_to_rst = 0, /* LPDDR2 does not need this field */ - .pd_fast_exit = 0, /* immaterial for calibration */ - .ddr_type = DDR_TYPE_LPDDR2, -#endif - .refsel = CONFIG_REFSEL, - .refr = CONFIG_REFR, -}; - -#ifdef CONFIG_MT41K512M16TNA -/* Micron MT41K512M16TNA-125 */ -static struct mx6_ddr3_cfg const ddrtype = { - .mem_speed = 1600, - .density = 8, - .width = 16, - .banks = 8, - .rowaddr = 15, - .coladdr = 10, - .pagesz = 1, - .trcd = 1375, - .trcmin = 5062, - .trasmin = 3750, -}; -#elif defined(CONFIG_MT41K128M16JT) -/* Micron MT41K128M16JT-125 */ -static struct mx6_ddr3_cfg const ddrtype = { - .mem_speed = 1600, - .density = 2, - .width = 16, - .banks = 8, - .rowaddr = 14, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; -#elif defined(CONFIG_H5TQ4G63AFR) -/* Hynix H5TQ4G63AFR */ -static struct mx6_ddr3_cfg const ddrtype = { - .mem_speed = 1600, - .density = 4, - .width = 16, - .banks = 8, - .rowaddr = 15, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; -#elif defined CONFIG_H5TQ2G63DFR -/* Hynix H5TQ2G63DFR */ -static struct mx6_ddr3_cfg const ddrtype = { - .mem_speed = 1333, - .density = 2, - .width = 16, - .banks = 8, - .rowaddr = 14, - .coladdr = 10, - .pagesz = 2, - .trcd = 1350, - .trcmin = 4950, - .trasmin = 3600, -}; -#elif defined(CONFIG_MT42L256M32D2LG) -/* Micron MT42L256M32D2LG */ -static struct mx6_lpddr2_cfg ddrtype = { - .mem_speed = 800, - .density = 4, - .width = 32, - .banks = 8, - .rowaddr = 14, - .coladdr = 10, - .trcd_lp = 2000, - .trppb_lp = 2000, - .trpab_lp = 2250, - .trasmin = 4200, -}; -#elif defined(CONFIG_MT29PZZZ4D4BKESK) -/* Micron MT29PZZZ4D4BKESK */ -static struct mx6_lpddr2_cfg ddrtype = { - .mem_speed = 800, - .density = 4, - .width = 32, - .banks = 8, - .rowaddr = 14, - .coladdr = 10, - .trcd_lp = 2000, - .trppb_lp = 2000, - .trpab_lp = 2250, - .trasmin = 4200, -}; -#else -#error please select DDR type using menuconfig -#endif - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - /* FIXME: these should probably be checked, especially - * for i.MX6SL, UL, ULL - */ - writel(0x00C03F3F, &ccm->CCGR0); - writel(0x0030FC03, &ccm->CCGR1); - writel(0x0FFFC000, &ccm->CCGR2); - writel(0x3FF00000, &ccm->CCGR3); - writel(0x00FFF300, &ccm->CCGR4); - writel(0x0F0000C3, &ccm->CCGR5); - writel(0x000003FF, &ccm->CCGR6); -} - -static void display_calibration(struct mx6_mmdc_calibration *calib) -{ - printf(".p0_mpdgctrl0\t= 0x%08X\n", calib->p0_mpdgctrl0); - printf(".p0_mpdgctrl1\t= 0x%08X\n", calib->p0_mpdgctrl1); - printf(".p0_mprddlctl\t= 0x%08X\n", calib->p0_mprddlctl); - printf(".p0_mpwrdlctl\t= 0x%08X\n", calib->p0_mpwrdlctl); - printf(".p0_mpwldectrl0\t= 0x%08X\n", calib->p0_mpwldectrl0); - printf(".p0_mpwldectrl1\t= 0x%08X\n", calib->p0_mpwldectrl1); - if (sysinfo.dsize == 2) { - printf(".p1_mpdgctrl0\t= 0x%08X\n", calib->p1_mpdgctrl0); - printf(".p1_mpdgctrl1\t= 0x%08X\n", calib->p1_mpdgctrl1); - printf(".p1_mprddlctl\t= 0x%08X\n", calib->p1_mprddlctl); - printf(".p1_mpwrdlctl\t= 0x%08X\n", calib->p1_mpwrdlctl); - printf(".p1_mpwldectrl0\t= 0x%08X\n", calib->p1_mpwldectrl0); - printf(".p1_mpwldectrl1\t= 0x%08X\n", calib->p1_mpwldectrl1); - } -#ifdef CONFIG_IMXIMAGE_OUTPUT - printf("DATA 4 MX6_MMDC_P0_MPDGCTRL0\t= 0x%08X\n", calib->p0_mpdgctrl0); - printf("DATA 4 MX6_MMDC_P0_MPDGCTRL1\t= 0x%08X\n", calib->p0_mpdgctrl1); - printf("DATA 4 MX6_MMDC_P0_MPRDDLCTL\t= 0x%08X\n", calib->p0_mprddlctl); - printf("DATA 4 MX6_MMDC_P0_MPWRDLCTL\t= 0x%08X\n", calib->p0_mpwrdlctl); - printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL0\t= 0x%08X\n", - calib->p0_mpwldectrl0); - printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL1\t= 0x%08X\n", - calib->p0_mpwldectrl1); - if (sysinfo.dsize == 2) { - printf("DATA 4 MX6_MMDC_P1_MPDGCTRL0\t= 0x%08X\n", - calib->p1_mpdgctrl0); - printf("DATA 4 MX6_MMDC_P1_MPDGCTRL1\t= 0x%08X\n", - calib->p1_mpdgctrl1); - printf("DATA 4 MX6_MMDC_P1_MPRDDLCTL\t= 0x%08X\n", - calib->p1_mprddlctl); - printf("DATA 4 MX6_MMDC_P1_MPWRDLCTL\t= 0x%08X\n", - calib->p1_mpwrdlctl); - printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL0\t= 0x%08X\n", - calib->p1_mpwldectrl0); - printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL1\t= 0x%08X\n", - calib->p1_mpwldectrl1); - } -#endif -} - -/* - * called from C runtime startup code (arch/arm/lib/crt0.S:_main) - * - we have a stack and a place to store GD, both in SRAM - * - no variable global data is available - */ -void board_init_f(ulong dummy) -{ - int errs; - struct mx6_mmdc_calibration calibration = {0}; - - memset((void *)gd, 0, sizeof(struct global_data)); - - /* write leveling calibration defaults */ - calibration.p0_mpwrdlctl = 0x40404040; - calibration.p1_mpwrdlctl = 0x40404040; - - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - ccgr_init(); - - SETUP_IOMUX_PADS(uart_pads); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - if (sysinfo.dsize != 1) { - if (is_cpu_type(MXC_CPU_MX6SX) || - is_cpu_type(MXC_CPU_MX6UL) || - is_cpu_type(MXC_CPU_MX6ULL) || - is_cpu_type(MXC_CPU_MX6SL)) { - printf("cpu type 0x%x doesn't support 64-bit bus\n", - get_cpu_type()); - reset_cpu(); - } - } -#ifdef CONFIG_MX6SL - mx6sl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sl_ddr_ioregs, - &mx6sl_grp_ioregs); -#else - if (is_cpu_type(MXC_CPU_MX6Q)) { - mx6dq_dram_iocfg(CONFIG_DDRWIDTH, &mx6dq_ddr_ioregs, - &mx6dq_grp_ioregs); - } else { - mx6sdl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sdl_ddr_ioregs, - &mx6sdl_grp_ioregs); - } -#endif - mx6_dram_cfg(&sysinfo, &calibration, &ddrtype); - - errs = mmdc_do_write_level_calibration(&sysinfo); - if (errs) { - printf("error %d from write level calibration\n", errs); - } else { - errs = mmdc_do_dqs_calibration(&sysinfo); - if (errs) { - printf("error %d from dqs calibration\n", errs); - } else { - printf("completed successfully\n"); - mmdc_read_calibration(&sysinfo, &calibration); - display_calibration(&calibration); - } - } -} diff --git a/board/freescale/mx6sabreauto/Kconfig b/board/freescale/mx6sabreauto/Kconfig deleted file mode 100644 index 5b4faf6d5fd..00000000000 --- a/board/freescale/mx6sabreauto/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MX6SABREAUTO - -config SYS_BOARD - default "mx6sabreauto" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "mx6sabreauto" - -endif diff --git a/board/freescale/mx6sabreauto/MAINTAINERS b/board/freescale/mx6sabreauto/MAINTAINERS deleted file mode 100644 index 6179d672c39..00000000000 --- a/board/freescale/mx6sabreauto/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MX6SABREAUTO BOARD -M: Fabio Estevam -M: Peng Fan -S: Maintained -F: board/freescale/mx6sabreauto/ -F: include/configs/mx6sabreauto.h -F: configs/mx6sabreauto_defconfig diff --git a/board/freescale/mx6sabreauto/Makefile b/board/freescale/mx6sabreauto/Makefile deleted file mode 100644 index 7ecdb6b4ad2..00000000000 --- a/board/freescale/mx6sabreauto/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. - -obj-y := mx6sabreauto.o diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c deleted file mode 100644 index 8ca57e0b2ac..00000000000 --- a/board/freescale/mx6sabreauto/mx6sabreauto.c +++ /dev/null @@ -1,931 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/pfuze.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) -#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ - PAD_CTL_SRE_FAST) -#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) - -#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -static iomux_v3_cfg_t const uart4_pads[] = { - IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const port_exp[] = { - IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -#ifdef CONFIG_MTD_NOR_FLASH -static iomux_v3_cfg_t const eimnor_pads[] = { - IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static void eimnor_cs_setup(void) -{ - struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; - - writel(0x00020181, &weim_regs->cs0gcr1); - writel(0x00000001, &weim_regs->cs0gcr2); - writel(0x0a020000, &weim_regs->cs0rcr1); - writel(0x0000c000, &weim_regs->cs0rcr2); - writel(0x0804a240, &weim_regs->cs0wcr1); - writel(0x00000120, &weim_regs->wcr); - - set_chipselect_size(CS0_128); -} - -static void eim_clk_setup(void) -{ - struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - int cscmr1, ccgr6; - - /* Turn off EIM clock */ - ccgr6 = readl(&imx_ccm->CCGR6); - ccgr6 &= ~(0x3 << 10); - writel(ccgr6, &imx_ccm->CCGR6); - - /* - * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root - * and aclk_eim_slow_podf = 01 --> divide by 2 - * so that we can have EIM at the maximum clock of 132MHz - */ - cscmr1 = readl(&imx_ccm->cscmr1); - cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK | - MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK); - cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET); - writel(cscmr1, &imx_ccm->cscmr1); - - /* Turn on EIM clock */ - ccgr6 |= (0x3 << 10); - writel(ccgr6, &imx_ccm->CCGR6); -} - -static void setup_iomux_eimnor(void) -{ - SETUP_IOMUX_PADS(eimnor_pads); - - gpio_direction_output(IMX_GPIO_NR(5, 4), 0); - - eimnor_cs_setup(); -} -#endif - -static iomux_v3_cfg_t const usdhc3_pads[] = { - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static void setup_iomux_uart(void) -{ - SETUP_IOMUX_PADS(uart4_pads); -} - -#ifdef CONFIG_FSL_ESDHC_IMX -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC3_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - gpio_direction_input(IMX_GPIO_NR(6, 15)); - return !gpio_get_value(IMX_GPIO_NR(6, 15)); -} - -int board_mmc_init(struct bd_info *bis) -{ - SETUP_IOMUX_PADS(usdhc3_pads); - - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} -#endif - -#ifdef CONFIG_NAND_MXS -static iomux_v3_cfg_t gpmi_pads[] = { - IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)), - IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), - IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1)), -}; - -static void setup_gpmi_nand(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - /* config gpmi nand iomux */ - SETUP_IOMUX_PADS(gpmi_pads); - - setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | - MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | - MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); - - /* enable apbh clock gating */ - setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); -} -#endif - -#ifdef CONFIG_REVISION_TAG -u32 get_board_rev(void) -{ - int rev = nxp_board_rev(); - - return (get_cpu_rev() & ~(0xF << 8)) | rev; -} -#endif - -static int ar8031_phy_fixup(struct phy_device *phydev) -{ - unsigned short val; - - /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - val &= 0xffe3; - val |= 0x18; - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); - - /* introduce tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - val |= 0x0100; - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - ar8031_phy_fixup(phydev); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -#if defined(CONFIG_VIDEO_IPUV3) -static void disable_lvds(struct display_info_t const *dev) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - clrbits_le32(&iomux->gpr[2], - IOMUXC_GPR2_LVDS_CH0_MODE_MASK | - IOMUXC_GPR2_LVDS_CH1_MODE_MASK); -} - -static void do_enable_hdmi(struct display_info_t const *dev) -{ - disable_lvds(dev); - imx_enable_hdmi_phy(); -} - -struct display_info_t const displays[] = {{ - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB666, - .detect = NULL, - .enable = NULL, - .mode = { - .name = "Hannstar-XGA", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED -} }, { - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, - .enable = do_enable_hdmi, - .mode = { - .name = "HDMI", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED, -} } }; -size_t display_count = ARRAY_SIZE(displays); - -iomux_v3_cfg_t const backlight_pads[] = { - IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL)), -}; - -static void setup_iomux_backlight(void) -{ - gpio_request(IMX_GPIO_NR(2, 9), "backlight"); - gpio_direction_output(IMX_GPIO_NR(2, 9), 1); - SETUP_IOMUX_PADS(backlight_pads); -} - -static void setup_display(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - int reg; - - setup_iomux_backlight(); - enable_ipu_clock(); - imx_setup_hdmi(); - - /* Turn on LDB_DI0 and LDB_DI1 clocks */ - reg = readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; - writel(reg, &mxc_ccm->CCGR3); - - /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */ - reg = readl(&mxc_ccm->cs2cdr); - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | - MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); - reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | - (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); - writel(reg, &mxc_ccm->cs2cdr); - - reg = readl(&mxc_ccm->cscmr2); - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; - writel(reg, &mxc_ccm->cscmr2); - - reg = readl(&mxc_ccm->chsccdr); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << - MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); - writel(reg, &mxc_ccm->chsccdr); - - reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW | - IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | - IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | - IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | - IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | - IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | - IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 | - IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED; - writel(reg, &iomux->gpr[2]); - - reg = readl(&iomux->gpr[3]); - reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | - IOMUXC_GPR3_HDMI_MUX_CTL_MASK); - reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << - IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) | - (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << - IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET); - writel(reg, &iomux->gpr[3]); -} -#endif /* CONFIG_VIDEO_IPUV3 */ - -/* - * Do not overwrite the console - * Use always serial for U-Boot console - */ -int overwrite_console(void) -{ - return 1; -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - -#ifdef CONFIG_NAND_MXS - setup_gpmi_nand(); -#endif - -#ifdef CONFIG_MTD_NOR_FLASH - eim_clk_setup(); -#endif - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - /* I2C 3 Steer */ - gpio_request(IMX_GPIO_NR(5, 4), "steer logic"); - gpio_direction_output(IMX_GPIO_NR(5, 4), 1); - - gpio_request(IMX_GPIO_NR(1, 15), "expander en"); - gpio_direction_output(IMX_GPIO_NR(1, 15), 1); - SETUP_IOMUX_PADS(port_exp); - -#ifdef CONFIG_VIDEO_IPUV3 - setup_display(); -#endif - -#ifdef CONFIG_MTD_NOR_FLASH - setup_iomux_eimnor(); -#endif - return 0; -} - -#ifdef CONFIG_MXC_SPI -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; -} -#endif - -int power_init_board(void) -{ - struct udevice *dev; - unsigned int value; - int ret; - - ret = pmic_get("pfuze100@8", &dev); - if (ret == -ENODEV) - return 0; - - if (ret != 0) - return ret; - - if (is_mx6dqp()) { - /* set SW2 staby volatage 0.975V*/ - value = pmic_reg_read(dev, PFUZE100_SW2STBY); - value &= ~0x3f; - value |= 0x17; - pmic_reg_write(dev, PFUZE100_SW2STBY, value); - } - - return pfuze_mode_init(dev, APS_PFM); -} - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ - {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - -int board_late_init(void) -{ -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - env_set("board_name", "SABREAUTO"); - - if (is_mx6dqp()) - env_set("board_rev", "MX6QP"); - else if (is_mx6dq()) - env_set("board_rev", "MX6Q"); - else if (is_mx6sdl()) - env_set("board_rev", "MX6DL"); -#endif - - return 0; -} - -int checkboard(void) -{ - printf("Board: MX6Q-Sabreauto rev%c\n", nxp_board_rev_string()); - - return 0; -} - -#ifdef CONFIG_USB_EHCI_MX6 -int board_ehci_hcd_init(int port) -{ - switch (port) { - case 0: - /* - * Set daisy chain for otg_pin_id on 6q. - * For 6dl, this bit is reserved. - */ - imx_iomux_set_gpr_register(1, 13, 1, 0); - break; - case 1: - break; - default: - printf("MXC USB port %d not yet supported\n", port); - return -EINVAL; - } - return 0; -} -#endif - -#ifdef CONFIG_XPL_BUILD -#include -#include -#include - -#ifdef CONFIG_SPL_OS_BOOT -int spl_start_uboot(void) -{ - return 0; -} -#endif - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0x00C03F3F, &ccm->CCGR0); - writel(0x0030FC03, &ccm->CCGR1); - writel(0x0FFFC000, &ccm->CCGR2); - writel(0x3FF00000, &ccm->CCGR3); - writel(0x00FFF300, &ccm->CCGR4); - writel(0x0F0000C3, &ccm->CCGR5); - writel(0x000003FF, &ccm->CCGR6); -} - -static int mx6q_dcd_table[] = { - 0x020e0798, 0x000C0000, - 0x020e0758, 0x00000000, - 0x020e0588, 0x00000030, - 0x020e0594, 0x00000030, - 0x020e056c, 0x00000030, - 0x020e0578, 0x00000030, - 0x020e074c, 0x00000030, - 0x020e057c, 0x00000030, - 0x020e058c, 0x00000000, - 0x020e059c, 0x00000030, - 0x020e05a0, 0x00000030, - 0x020e078c, 0x00000030, - 0x020e0750, 0x00020000, - 0x020e05a8, 0x00000028, - 0x020e05b0, 0x00000028, - 0x020e0524, 0x00000028, - 0x020e051c, 0x00000028, - 0x020e0518, 0x00000028, - 0x020e050c, 0x00000028, - 0x020e05b8, 0x00000028, - 0x020e05c0, 0x00000028, - 0x020e0774, 0x00020000, - 0x020e0784, 0x00000028, - 0x020e0788, 0x00000028, - 0x020e0794, 0x00000028, - 0x020e079c, 0x00000028, - 0x020e07a0, 0x00000028, - 0x020e07a4, 0x00000028, - 0x020e07a8, 0x00000028, - 0x020e0748, 0x00000028, - 0x020e05ac, 0x00000028, - 0x020e05b4, 0x00000028, - 0x020e0528, 0x00000028, - 0x020e0520, 0x00000028, - 0x020e0514, 0x00000028, - 0x020e0510, 0x00000028, - 0x020e05bc, 0x00000028, - 0x020e05c4, 0x00000028, - 0x021b0800, 0xa1390003, - 0x021b080c, 0x001F001F, - 0x021b0810, 0x001F001F, - 0x021b480c, 0x001F001F, - 0x021b4810, 0x001F001F, - 0x021b083c, 0x43260335, - 0x021b0840, 0x031A030B, - 0x021b483c, 0x4323033B, - 0x021b4840, 0x0323026F, - 0x021b0848, 0x483D4545, - 0x021b4848, 0x44433E48, - 0x021b0850, 0x41444840, - 0x021b4850, 0x4835483E, - 0x021b081c, 0x33333333, - 0x021b0820, 0x33333333, - 0x021b0824, 0x33333333, - 0x021b0828, 0x33333333, - 0x021b481c, 0x33333333, - 0x021b4820, 0x33333333, - 0x021b4824, 0x33333333, - 0x021b4828, 0x33333333, - 0x021b08b8, 0x00000800, - 0x021b48b8, 0x00000800, - 0x021b0004, 0x00020036, - 0x021b0008, 0x09444040, - 0x021b000c, 0x8A8F7955, - 0x021b0010, 0xFF328F64, - 0x021b0014, 0x01FF00DB, - 0x021b0018, 0x00001740, - 0x021b001c, 0x00008000, - 0x021b002c, 0x000026d2, - 0x021b0030, 0x008F1023, - 0x021b0040, 0x00000047, - 0x021b0000, 0x841A0000, - 0x021b001c, 0x04088032, - 0x021b001c, 0x00008033, - 0x021b001c, 0x00048031, - 0x021b001c, 0x09408030, - 0x021b001c, 0x04008040, - 0x021b0020, 0x00005800, - 0x021b0818, 0x00011117, - 0x021b4818, 0x00011117, - 0x021b0004, 0x00025576, - 0x021b0404, 0x00011006, - 0x021b001c, 0x00000000, - 0x020c4068, 0x00C03F3F, - 0x020c406c, 0x0030FC03, - 0x020c4070, 0x0FFFC000, - 0x020c4074, 0x3FF00000, - 0x020c4078, 0xFFFFF300, - 0x020c407c, 0x0F0000F3, - 0x020c4080, 0x00000FFF, - 0x020e0010, 0xF00000CF, - 0x020e0018, 0x007F007F, - 0x020e001c, 0x007F007F, -}; - -static int mx6qp_dcd_table[] = { - 0x020e0798, 0x000C0000, - 0x020e0758, 0x00000000, - 0x020e0588, 0x00000030, - 0x020e0594, 0x00000030, - 0x020e056c, 0x00000030, - 0x020e0578, 0x00000030, - 0x020e074c, 0x00000030, - 0x020e057c, 0x00000030, - 0x020e058c, 0x00000000, - 0x020e059c, 0x00000030, - 0x020e05a0, 0x00000030, - 0x020e078c, 0x00000030, - 0x020e0750, 0x00020000, - 0x020e05a8, 0x00000030, - 0x020e05b0, 0x00000030, - 0x020e0524, 0x00000030, - 0x020e051c, 0x00000030, - 0x020e0518, 0x00000030, - 0x020e050c, 0x00000030, - 0x020e05b8, 0x00000030, - 0x020e05c0, 0x00000030, - 0x020e0774, 0x00020000, - 0x020e0784, 0x00000030, - 0x020e0788, 0x00000030, - 0x020e0794, 0x00000030, - 0x020e079c, 0x00000030, - 0x020e07a0, 0x00000030, - 0x020e07a4, 0x00000030, - 0x020e07a8, 0x00000030, - 0x020e0748, 0x00000030, - 0x020e05ac, 0x00000030, - 0x020e05b4, 0x00000030, - 0x020e0528, 0x00000030, - 0x020e0520, 0x00000030, - 0x020e0514, 0x00000030, - 0x020e0510, 0x00000030, - 0x020e05bc, 0x00000030, - 0x020e05c4, 0x00000030, - 0x021b0800, 0xa1390003, - 0x021b080c, 0x001b001e, - 0x021b0810, 0x002e0029, - 0x021b480c, 0x001b002a, - 0x021b4810, 0x0019002c, - 0x021b083c, 0x43240334, - 0x021b0840, 0x0324031a, - 0x021b483c, 0x43340344, - 0x021b4840, 0x03280276, - 0x021b0848, 0x44383A3E, - 0x021b4848, 0x3C3C3846, - 0x021b0850, 0x2e303230, - 0x021b4850, 0x38283E34, - 0x021b081c, 0x33333333, - 0x021b0820, 0x33333333, - 0x021b0824, 0x33333333, - 0x021b0828, 0x33333333, - 0x021b481c, 0x33333333, - 0x021b4820, 0x33333333, - 0x021b4824, 0x33333333, - 0x021b4828, 0x33333333, - 0x021b08c0, 0x24912492, - 0x021b48c0, 0x24912492, - 0x021b08b8, 0x00000800, - 0x021b48b8, 0x00000800, - 0x021b0004, 0x00020036, - 0x021b0008, 0x09444040, - 0x021b000c, 0x898E7955, - 0x021b0010, 0xFF328F64, - 0x021b0014, 0x01FF00DB, - 0x021b0018, 0x00001740, - 0x021b001c, 0x00008000, - 0x021b002c, 0x000026d2, - 0x021b0030, 0x008E1023, - 0x021b0040, 0x00000047, - 0x021b0400, 0x14420000, - 0x021b0000, 0x841A0000, - 0x00bb0008, 0x00000004, - 0x00bb000c, 0x2891E41A, - 0x00bb0038, 0x00000564, - 0x00bb0014, 0x00000040, - 0x00bb0028, 0x00000020, - 0x00bb002c, 0x00000020, - 0x021b001c, 0x04088032, - 0x021b001c, 0x00008033, - 0x021b001c, 0x00048031, - 0x021b001c, 0x09408030, - 0x021b001c, 0x04008040, - 0x021b0020, 0x00005800, - 0x021b0818, 0x00011117, - 0x021b4818, 0x00011117, - 0x021b0004, 0x00025576, - 0x021b0404, 0x00011006, - 0x021b001c, 0x00000000, - 0x020c4068, 0x00C03F3F, - 0x020c406c, 0x0030FC03, - 0x020c4070, 0x0FFFC000, - 0x020c4074, 0x3FF00000, - 0x020c4078, 0xFFFFF300, - 0x020c407c, 0x0F0000F3, - 0x020c4080, 0x00000FFF, - 0x020e0010, 0xF00000CF, - 0x020e0018, 0x77177717, - 0x020e001c, 0x77177717, -}; - -static int mx6dl_dcd_table[] = { - 0x020e0774, 0x000C0000, - 0x020e0754, 0x00000000, - 0x020e04ac, 0x00000030, - 0x020e04b0, 0x00000030, - 0x020e0464, 0x00000030, - 0x020e0490, 0x00000030, - 0x020e074c, 0x00000030, - 0x020e0494, 0x00000030, - 0x020e04a0, 0x00000000, - 0x020e04b4, 0x00000030, - 0x020e04b8, 0x00000030, - 0x020e076c, 0x00000030, - 0x020e0750, 0x00020000, - 0x020e04bc, 0x00000028, - 0x020e04c0, 0x00000028, - 0x020e04c4, 0x00000028, - 0x020e04c8, 0x00000028, - 0x020e04cc, 0x00000028, - 0x020e04d0, 0x00000028, - 0x020e04d4, 0x00000028, - 0x020e04d8, 0x00000028, - 0x020e0760, 0x00020000, - 0x020e0764, 0x00000028, - 0x020e0770, 0x00000028, - 0x020e0778, 0x00000028, - 0x020e077c, 0x00000028, - 0x020e0780, 0x00000028, - 0x020e0784, 0x00000028, - 0x020e078c, 0x00000028, - 0x020e0748, 0x00000028, - 0x020e0470, 0x00000028, - 0x020e0474, 0x00000028, - 0x020e0478, 0x00000028, - 0x020e047c, 0x00000028, - 0x020e0480, 0x00000028, - 0x020e0484, 0x00000028, - 0x020e0488, 0x00000028, - 0x020e048c, 0x00000028, - 0x021b0800, 0xa1390003, - 0x021b080c, 0x001F001F, - 0x021b0810, 0x001F001F, - 0x021b480c, 0x001F001F, - 0x021b4810, 0x001F001F, - 0x021b083c, 0x42190217, - 0x021b0840, 0x017B017B, - 0x021b483c, 0x4176017B, - 0x021b4840, 0x015F016C, - 0x021b0848, 0x4C4C4D4C, - 0x021b4848, 0x4A4D4C48, - 0x021b0850, 0x3F3F3F40, - 0x021b4850, 0x3538382E, - 0x021b081c, 0x33333333, - 0x021b0820, 0x33333333, - 0x021b0824, 0x33333333, - 0x021b0828, 0x33333333, - 0x021b481c, 0x33333333, - 0x021b4820, 0x33333333, - 0x021b4824, 0x33333333, - 0x021b4828, 0x33333333, - 0x021b08b8, 0x00000800, - 0x021b48b8, 0x00000800, - 0x021b0004, 0x00020025, - 0x021b0008, 0x00333030, - 0x021b000c, 0x676B5313, - 0x021b0010, 0xB66E8B63, - 0x021b0014, 0x01FF00DB, - 0x021b0018, 0x00001740, - 0x021b001c, 0x00008000, - 0x021b002c, 0x000026d2, - 0x021b0030, 0x006B1023, - 0x021b0040, 0x00000047, - 0x021b0000, 0x841A0000, - 0x021b001c, 0x04008032, - 0x021b001c, 0x00008033, - 0x021b001c, 0x00048031, - 0x021b001c, 0x05208030, - 0x021b001c, 0x04008040, - 0x021b0020, 0x00005800, - 0x021b0818, 0x00011117, - 0x021b4818, 0x00011117, - 0x021b0004, 0x00025565, - 0x021b0404, 0x00011006, - 0x021b001c, 0x00000000, - 0x020c4068, 0x00C03F3F, - 0x020c406c, 0x0030FC03, - 0x020c4070, 0x0FFFC000, - 0x020c4074, 0x3FF00000, - 0x020c4078, 0xFFFFF300, - 0x020c407c, 0x0F0000C3, - 0x020c4080, 0x00000FFF, - 0x020e0010, 0xF00000CF, - 0x020e0018, 0x007F007F, - 0x020e001c, 0x007F007F, -}; - -static void ddr_init(int *table, int size) -{ - int i; - - for (i = 0; i < size / 2 ; i++) - writel(table[2 * i + 1], table[2 * i]); -} - -static void spl_dram_init(void) -{ - if (is_mx6dq()) - ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table)); - else if (is_mx6dqp()) - ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table)); - else if (is_mx6sdl()) - ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); -} - -void board_init_f(ulong dummy) -{ - /* DDR initialization */ - spl_dram_init(); - - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - ccgr_init(); - gpr_init(); - - board_early_init_f(); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); -} -#endif - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - if (is_mx6dq()) { - if (!strcmp(name, "imx6q-sabreauto")) - return 0; - } else if (is_mx6dqp()) { - if (!strcmp(name, "imx6qp-sabreauto")) - return 0; - } else if (is_mx6dl()) { - if (!strcmp(name, "imx6dl-sabreauto")) - return 0; - } - - return -1; -} -#endif diff --git a/board/freescale/mx6sabresd/Kconfig b/board/freescale/mx6sabresd/Kconfig deleted file mode 100644 index e87dea0d7a2..00000000000 --- a/board/freescale/mx6sabresd/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MX6SABRESD - -config SYS_BOARD - default "mx6sabresd" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "mx6sabresd" - -endif diff --git a/board/freescale/mx6sabresd/MAINTAINERS b/board/freescale/mx6sabresd/MAINTAINERS deleted file mode 100644 index 5e256ef163e..00000000000 --- a/board/freescale/mx6sabresd/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX6SABRESD BOARD -M: Fabio Estevam -S: Maintained -F: board/freescale/mx6sabresd/ -F: include/configs/mx6sabresd.h -F: configs/mx6sabresd_defconfig diff --git a/board/freescale/mx6sabresd/Makefile b/board/freescale/mx6sabresd/Makefile deleted file mode 100644 index 92e1ff72a4f..00000000000 --- a/board/freescale/mx6sabresd/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski -# -# (C) Copyright 2011 Freescale Semiconductor, Inc. - -obj-y := mx6sabresd.o diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c deleted file mode 100644 index dff3a9c33bf..00000000000 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ /dev/null @@ -1,868 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/pfuze.h" -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define DISP0_PWR_EN IMX_GPIO_NR(1, 21) - -#define KEY_VOL_UP IMX_GPIO_NR(1, 4) - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - return 0; -} - -static iomux_v3_cfg_t const uart1_pads[] = { - IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const usdhc2_pads[] = { - IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */ -}; - -static iomux_v3_cfg_t const usdhc3_pads[] = { - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */ -}; - -static iomux_v3_cfg_t const usdhc4_pads[] = { - IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const ecspi1_pads[] = { - IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), - IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const rgb_pads[] = { - IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)), - IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static iomux_v3_cfg_t const bl_pads[] = { - IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static void enable_backlight(void) -{ - SETUP_IOMUX_PADS(bl_pads); - gpio_request(DISP0_PWR_EN, "Display Power Enable"); - gpio_direction_output(DISP0_PWR_EN, 1); -} - -static void enable_rgb(struct display_info_t const *dev) -{ - SETUP_IOMUX_PADS(rgb_pads); - enable_backlight(); -} - -static void enable_lvds(struct display_info_t const *dev) -{ - enable_backlight(); -} - -static void setup_spi(void) -{ - SETUP_IOMUX_PADS(ecspi1_pads); -} - -iomux_v3_cfg_t const di0_pads[] = { - IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */ - IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* DISP0_HSYNC */ - IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* DISP0_VSYNC */ -}; - -static void setup_iomux_uart(void) -{ - SETUP_IOMUX_PADS(uart1_pads); -} - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg usdhc_cfg[3] = { - {USDHC2_BASE_ADDR}, - {USDHC3_BASE_ADDR}, - {USDHC4_BASE_ADDR}, -}; - -#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) -#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) - -int board_mmc_get_env_dev(int devno) -{ - return devno - 1; -} - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - ret = !gpio_get_value(USDHC3_CD_GPIO); - break; - case USDHC4_BASE_ADDR: - ret = 1; /* eMMC/uSDHC4 is always present */ - break; - } - - return ret; -} - -int board_mmc_init(struct bd_info *bis) -{ - struct src *psrc = (struct src *)SRC_BASE_ADDR; - unsigned reg = readl(&psrc->sbmr1) >> 11; - /* - * Upon reading BOOT_CFG register the following map is done: - * Bit 11 and 12 of BOOT_CFG register can determine the current - * mmc port - * 0x1 SD1 - * 0x2 SD2 - * 0x3 SD4 - */ - - switch (reg & 0x3) { - case 0x1: - SETUP_IOMUX_PADS(usdhc2_pads); - usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - break; - case 0x2: - SETUP_IOMUX_PADS(usdhc3_pads); - usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - break; - case 0x3: - SETUP_IOMUX_PADS(usdhc4_pads); - usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - break; - } - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} -#endif - -#if defined(CONFIG_VIDEO_IPUV3) -static void disable_lvds(struct display_info_t const *dev) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - int reg = readl(&iomux->gpr[2]); - - reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK | - IOMUXC_GPR2_LVDS_CH1_MODE_MASK); - - writel(reg, &iomux->gpr[2]); -} - -static void do_enable_hdmi(struct display_info_t const *dev) -{ - disable_lvds(dev); - imx_enable_hdmi_phy(); -} - -struct display_info_t const displays[] = {{ - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB666, - .detect = NULL, - .enable = enable_lvds, - .mode = { - .name = "Hannstar-XGA", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15384, - .left_margin = 160, - .right_margin = 24, - .upper_margin = 29, - .lower_margin = 3, - .hsync_len = 136, - .vsync_len = 6, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED -} }, { - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, - .enable = do_enable_hdmi, - .mode = { - .name = "HDMI", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15384, - .left_margin = 160, - .right_margin = 24, - .upper_margin = 29, - .lower_margin = 3, - .hsync_len = 136, - .vsync_len = 6, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED -} }, { - .bus = 0, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = NULL, - .enable = enable_rgb, - .mode = { - .name = "SEIKO-WVGA", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 29850, - .left_margin = 89, - .right_margin = 164, - .upper_margin = 23, - .lower_margin = 10, - .hsync_len = 10, - .vsync_len = 10, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED -} } }; -size_t display_count = ARRAY_SIZE(displays); - -static void setup_display(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - int reg; - - /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ - SETUP_IOMUX_PADS(di0_pads); - - enable_ipu_clock(); - imx_setup_hdmi(); - - /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ - reg = readl(&mxc_ccm->CCGR3); - reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; - writel(reg, &mxc_ccm->CCGR3); - - /* set LDB0, LDB1 clk select to 011/011 */ - reg = readl(&mxc_ccm->cs2cdr); - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK - | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); - reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) - | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); - writel(reg, &mxc_ccm->cs2cdr); - - reg = readl(&mxc_ccm->cscmr2); - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; - writel(reg, &mxc_ccm->cscmr2); - - reg = readl(&mxc_ccm->chsccdr); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); - writel(reg, &mxc_ccm->chsccdr); - - reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES - | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW - | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW - | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG - | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT - | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG - | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT - | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED - | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; - writel(reg, &iomux->gpr[2]); - - reg = readl(&iomux->gpr[3]); - reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK - | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) - | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 - << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); - writel(reg, &iomux->gpr[3]); -} -#endif /* CONFIG_VIDEO_IPUV3 */ - -/* - * Do not overwrite the console - * Use always serial for U-Boot console - */ -int overwrite_console(void) -{ - return 1; -} - -#ifdef CONFIG_USB_EHCI_MX6 -static void setup_usb(void) -{ - /* - * set daisy chain for otg_pin_id on 6q. - * for 6dl, this bit is reserved - */ - imx_iomux_set_gpr_register(1, 13, 1, 0); -} -#endif - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - -#ifdef CONFIG_MXC_SPI - setup_spi(); -#endif - -#if defined(CONFIG_VIDEO_IPUV3) - setup_display(); -#endif -#ifdef CONFIG_USB_EHCI_MX6 - setup_usb(); -#endif - - return 0; -} - -int power_init_board(void) -{ - struct udevice *dev; - unsigned int reg; - int ret; - - ret = pmic_get("pfuze100@8", &dev); - if (ret == -ENODEV) - return 0; - - if (ret != 0) - return ret; - - ret = pfuze_mode_init(dev, APS_PFM); - if (ret < 0) - return ret; - - /* Increase VGEN3 from 2.5 to 2.8V */ - reg = pmic_reg_read(dev, PFUZE100_VGEN3VOL); - reg &= ~LDO_VOL_MASK; - reg |= LDOB_2_80V; - pmic_reg_write(dev, PFUZE100_VGEN3VOL, reg); - - /* Increase VGEN5 from 2.8 to 3V */ - reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); - reg &= ~LDO_VOL_MASK; - reg |= LDOB_3_00V; - pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); - - return 0; -} - -#ifdef CONFIG_MXC_SPI -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; -} -#endif - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ - {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, - {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, - /* 8 bit bus width */ - {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - -int board_late_init(void) -{ -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - env_set("board_name", "SABRESD"); - - if (is_mx6dqp()) - env_set("board_rev", "MX6QP"); - else if (is_mx6dq()) - env_set("board_rev", "MX6Q"); - else if (is_mx6sdl()) - env_set("board_rev", "MX6DL"); -#endif - - return 0; -} - -#ifdef CONFIG_XPL_BUILD -#include -#include -#include - -#ifdef CONFIG_SPL_OS_BOOT -int spl_start_uboot(void) -{ - gpio_request(KEY_VOL_UP, "KEY Volume UP"); - gpio_direction_input(KEY_VOL_UP); - - /* Only enter in Falcon mode if KEY_VOL_UP is pressed */ - return gpio_get_value(KEY_VOL_UP); -} -#endif - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0x00C03F3F, &ccm->CCGR0); - writel(0x0030FC03, &ccm->CCGR1); - writel(0x0FFFC000, &ccm->CCGR2); - writel(0x3FF00000, &ccm->CCGR3); - writel(0x00FFF300, &ccm->CCGR4); - writel(0x0F0000C3, &ccm->CCGR5); - writel(0x000003FF, &ccm->CCGR6); -} - -static int mx6q_dcd_table[] = { - 0x020e0798, 0x000C0000, - 0x020e0758, 0x00000000, - 0x020e0588, 0x00000030, - 0x020e0594, 0x00000030, - 0x020e056c, 0x00000030, - 0x020e0578, 0x00000030, - 0x020e074c, 0x00000030, - 0x020e057c, 0x00000030, - 0x020e058c, 0x00000000, - 0x020e059c, 0x00000030, - 0x020e05a0, 0x00000030, - 0x020e078c, 0x00000030, - 0x020e0750, 0x00020000, - 0x020e05a8, 0x00000030, - 0x020e05b0, 0x00000030, - 0x020e0524, 0x00000030, - 0x020e051c, 0x00000030, - 0x020e0518, 0x00000030, - 0x020e050c, 0x00000030, - 0x020e05b8, 0x00000030, - 0x020e05c0, 0x00000030, - 0x020e0774, 0x00020000, - 0x020e0784, 0x00000030, - 0x020e0788, 0x00000030, - 0x020e0794, 0x00000030, - 0x020e079c, 0x00000030, - 0x020e07a0, 0x00000030, - 0x020e07a4, 0x00000030, - 0x020e07a8, 0x00000030, - 0x020e0748, 0x00000030, - 0x020e05ac, 0x00000030, - 0x020e05b4, 0x00000030, - 0x020e0528, 0x00000030, - 0x020e0520, 0x00000030, - 0x020e0514, 0x00000030, - 0x020e0510, 0x00000030, - 0x020e05bc, 0x00000030, - 0x020e05c4, 0x00000030, - 0x021b0800, 0xa1390003, - 0x021b080c, 0x001F001F, - 0x021b0810, 0x001F001F, - 0x021b480c, 0x001F001F, - 0x021b4810, 0x001F001F, - 0x021b083c, 0x43270338, - 0x021b0840, 0x03200314, - 0x021b483c, 0x431A032F, - 0x021b4840, 0x03200263, - 0x021b0848, 0x4B434748, - 0x021b4848, 0x4445404C, - 0x021b0850, 0x38444542, - 0x021b4850, 0x4935493A, - 0x021b081c, 0x33333333, - 0x021b0820, 0x33333333, - 0x021b0824, 0x33333333, - 0x021b0828, 0x33333333, - 0x021b481c, 0x33333333, - 0x021b4820, 0x33333333, - 0x021b4824, 0x33333333, - 0x021b4828, 0x33333333, - 0x021b08b8, 0x00000800, - 0x021b48b8, 0x00000800, - 0x021b0004, 0x00020036, - 0x021b0008, 0x09444040, - 0x021b000c, 0x555A7975, - 0x021b0010, 0xFF538F64, - 0x021b0014, 0x01FF00DB, - 0x021b0018, 0x00001740, - 0x021b001c, 0x00008000, - 0x021b002c, 0x000026d2, - 0x021b0030, 0x005A1023, - 0x021b0040, 0x00000027, - 0x021b0000, 0x831A0000, - 0x021b001c, 0x04088032, - 0x021b001c, 0x00008033, - 0x021b001c, 0x00048031, - 0x021b001c, 0x09408030, - 0x021b001c, 0x04008040, - 0x021b0020, 0x00005800, - 0x021b0818, 0x00011117, - 0x021b4818, 0x00011117, - 0x021b0004, 0x00025576, - 0x021b0404, 0x00011006, - 0x021b001c, 0x00000000, -}; - -static int mx6qp_dcd_table[] = { - 0x020e0798, 0x000c0000, - 0x020e0758, 0x00000000, - 0x020e0588, 0x00000030, - 0x020e0594, 0x00000030, - 0x020e056c, 0x00000030, - 0x020e0578, 0x00000030, - 0x020e074c, 0x00000030, - 0x020e057c, 0x00000030, - 0x020e058c, 0x00000000, - 0x020e059c, 0x00000030, - 0x020e05a0, 0x00000030, - 0x020e078c, 0x00000030, - 0x020e0750, 0x00020000, - 0x020e05a8, 0x00000030, - 0x020e05b0, 0x00000030, - 0x020e0524, 0x00000030, - 0x020e051c, 0x00000030, - 0x020e0518, 0x00000030, - 0x020e050c, 0x00000030, - 0x020e05b8, 0x00000030, - 0x020e05c0, 0x00000030, - 0x020e0774, 0x00020000, - 0x020e0784, 0x00000030, - 0x020e0788, 0x00000030, - 0x020e0794, 0x00000030, - 0x020e079c, 0x00000030, - 0x020e07a0, 0x00000030, - 0x020e07a4, 0x00000030, - 0x020e07a8, 0x00000030, - 0x020e0748, 0x00000030, - 0x020e05ac, 0x00000030, - 0x020e05b4, 0x00000030, - 0x020e0528, 0x00000030, - 0x020e0520, 0x00000030, - 0x020e0514, 0x00000030, - 0x020e0510, 0x00000030, - 0x020e05bc, 0x00000030, - 0x020e05c4, 0x00000030, - 0x021b0800, 0xa1390003, - 0x021b080c, 0x001b001e, - 0x021b0810, 0x002e0029, - 0x021b480c, 0x001b002a, - 0x021b4810, 0x0019002c, - 0x021b083c, 0x43240334, - 0x021b0840, 0x0324031a, - 0x021b483c, 0x43340344, - 0x021b4840, 0x03280276, - 0x021b0848, 0x44383A3E, - 0x021b4848, 0x3C3C3846, - 0x021b0850, 0x2e303230, - 0x021b4850, 0x38283E34, - 0x021b081c, 0x33333333, - 0x021b0820, 0x33333333, - 0x021b0824, 0x33333333, - 0x021b0828, 0x33333333, - 0x021b481c, 0x33333333, - 0x021b4820, 0x33333333, - 0x021b4824, 0x33333333, - 0x021b4828, 0x33333333, - 0x021b08c0, 0x24912249, - 0x021b48c0, 0x24914289, - 0x021b08b8, 0x00000800, - 0x021b48b8, 0x00000800, - 0x021b0004, 0x00020036, - 0x021b0008, 0x24444040, - 0x021b000c, 0x555A7955, - 0x021b0010, 0xFF320F64, - 0x021b0014, 0x01ff00db, - 0x021b0018, 0x00001740, - 0x021b001c, 0x00008000, - 0x021b002c, 0x000026d2, - 0x021b0030, 0x005A1023, - 0x021b0040, 0x00000027, - 0x021b0400, 0x14420000, - 0x021b0000, 0x831A0000, - 0x021b0890, 0x00400C58, - 0x00bb0008, 0x00000000, - 0x00bb000c, 0x2891E41A, - 0x00bb0038, 0x00000564, - 0x00bb0014, 0x00000040, - 0x00bb0028, 0x00000020, - 0x00bb002c, 0x00000020, - 0x021b001c, 0x04088032, - 0x021b001c, 0x00008033, - 0x021b001c, 0x00048031, - 0x021b001c, 0x09408030, - 0x021b001c, 0x04008040, - 0x021b0020, 0x00005800, - 0x021b0818, 0x00011117, - 0x021b4818, 0x00011117, - 0x021b0004, 0x00025576, - 0x021b0404, 0x00011006, - 0x021b001c, 0x00000000, -}; - -static int mx6dl_dcd_table[] = { - 0x020e0774, 0x000C0000, - 0x020e0754, 0x00000000, - 0x020e04ac, 0x00000030, - 0x020e04b0, 0x00000030, - 0x020e0464, 0x00000030, - 0x020e0490, 0x00000030, - 0x020e074c, 0x00000030, - 0x020e0494, 0x00000030, - 0x020e04a0, 0x00000000, - 0x020e04b4, 0x00000030, - 0x020e04b8, 0x00000030, - 0x020e076c, 0x00000030, - 0x020e0750, 0x00020000, - 0x020e04bc, 0x00000030, - 0x020e04c0, 0x00000030, - 0x020e04c4, 0x00000030, - 0x020e04c8, 0x00000030, - 0x020e04cc, 0x00000030, - 0x020e04d0, 0x00000030, - 0x020e04d4, 0x00000030, - 0x020e04d8, 0x00000030, - 0x020e0760, 0x00020000, - 0x020e0764, 0x00000030, - 0x020e0770, 0x00000030, - 0x020e0778, 0x00000030, - 0x020e077c, 0x00000030, - 0x020e0780, 0x00000030, - 0x020e0784, 0x00000030, - 0x020e078c, 0x00000030, - 0x020e0748, 0x00000030, - 0x020e0470, 0x00000030, - 0x020e0474, 0x00000030, - 0x020e0478, 0x00000030, - 0x020e047c, 0x00000030, - 0x020e0480, 0x00000030, - 0x020e0484, 0x00000030, - 0x020e0488, 0x00000030, - 0x020e048c, 0x00000030, - 0x021b0800, 0xa1390003, - 0x021b080c, 0x001F001F, - 0x021b0810, 0x001F001F, - 0x021b480c, 0x001F001F, - 0x021b4810, 0x001F001F, - 0x021b083c, 0x4220021F, - 0x021b0840, 0x0207017E, - 0x021b483c, 0x4201020C, - 0x021b4840, 0x01660172, - 0x021b0848, 0x4A4D4E4D, - 0x021b4848, 0x4A4F5049, - 0x021b0850, 0x3F3C3D31, - 0x021b4850, 0x3238372B, - 0x021b081c, 0x33333333, - 0x021b0820, 0x33333333, - 0x021b0824, 0x33333333, - 0x021b0828, 0x33333333, - 0x021b481c, 0x33333333, - 0x021b4820, 0x33333333, - 0x021b4824, 0x33333333, - 0x021b4828, 0x33333333, - 0x021b08b8, 0x00000800, - 0x021b48b8, 0x00000800, - 0x021b0004, 0x0002002D, - 0x021b0008, 0x00333030, - 0x021b000c, 0x3F435313, - 0x021b0010, 0xB66E8B63, - 0x021b0014, 0x01FF00DB, - 0x021b0018, 0x00001740, - 0x021b001c, 0x00008000, - 0x021b002c, 0x000026d2, - 0x021b0030, 0x00431023, - 0x021b0040, 0x00000027, - 0x021b0000, 0x831A0000, - 0x021b001c, 0x04008032, - 0x021b001c, 0x00008033, - 0x021b001c, 0x00048031, - 0x021b001c, 0x05208030, - 0x021b001c, 0x04008040, - 0x021b0020, 0x00005800, - 0x021b0818, 0x00011117, - 0x021b4818, 0x00011117, - 0x021b0004, 0x0002556D, - 0x021b0404, 0x00011006, - 0x021b001c, 0x00000000, -}; - -static void ddr_init(int *table, int size) -{ - int i; - - for (i = 0; i < size / 2 ; i++) - writel(table[2 * i + 1], table[2 * i]); -} - -static void spl_dram_init(void) -{ - if (is_mx6dq()) - ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table)); - else if (is_mx6dqp()) - ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table)); - else if (is_mx6sdl()) - ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); -} - -void board_init_f(ulong dummy) -{ - /* DDR initialization */ - spl_dram_init(); - - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - ccgr_init(); - gpr_init(); - - board_early_init_f(); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); -} -#endif - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - if (is_mx6dq()) { - if (!strcmp(name, "imx6q-sabresd")) - return 0; - } else if (is_mx6dqp()) { - if (!strcmp(name, "imx6qp-sabresd")) - return 0; - } else if (is_mx6dl()) { - if (!strcmp(name, "imx6dl-sabresd")) - return 0; - } - - return -1; -} -#endif diff --git a/board/freescale/mx6slevk/Kconfig b/board/freescale/mx6slevk/Kconfig deleted file mode 100644 index e6bbb4194f4..00000000000 --- a/board/freescale/mx6slevk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX6SLEVK - -config SYS_BOARD - default "mx6slevk" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "mx6slevk" - -config IMX_CONFIG - default "board/freescale/mx6slevk/imximage.cfg" - -endif diff --git a/board/freescale/mx6slevk/MAINTAINERS b/board/freescale/mx6slevk/MAINTAINERS deleted file mode 100644 index ae87fe472bc..00000000000 --- a/board/freescale/mx6slevk/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -MX6SLEVK BOARD -M: Fabio Estevam -M: Peng Fan -S: Maintained -F: board/freescale/mx6slevk/ -F: include/configs/mx6slevk.h -F: configs/mx6slevk_defconfig -F: configs/mx6slevk_spl_defconfig -F: configs/mx6slevk_spinor_defconfig diff --git a/board/freescale/mx6slevk/Makefile b/board/freescale/mx6slevk/Makefile deleted file mode 100644 index 770f7aac6b9..00000000000 --- a/board/freescale/mx6slevk/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# (C) Copyright 2013 Freescale Semiconductor, Inc. - -obj-y := mx6slevk.o diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg deleted file mode 100644 index 64be101d6ec..00000000000 --- a/board/freescale/mx6slevk/imximage.cfg +++ /dev/null @@ -1,122 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ -#include - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ - -BOOT_FROM sd - -/* - * Secure boot support - */ -#ifdef CONFIG_IMX_HAB -CSF CONFIG_CSF_SIZE -#endif - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -DATA 4 0x020c4018 0x00260324 - -DATA 4 0x020c4068 0xffffffff -DATA 4 0x020c406c 0xffffffff -DATA 4 0x020c4070 0xffffffff -DATA 4 0x020c4074 0xffffffff -DATA 4 0x020c4078 0xffffffff -DATA 4 0x020c407c 0xffffffff -DATA 4 0x020c4080 0xffffffff - -DATA 4 0x020e0344 0x00003030 -DATA 4 0x020e0348 0x00003030 -DATA 4 0x020e034c 0x00003030 -DATA 4 0x020e0350 0x00003030 -DATA 4 0x020e030c 0x00000030 -DATA 4 0x020e0310 0x00000030 -DATA 4 0x020e0314 0x00000030 -DATA 4 0x020e0318 0x00000030 -DATA 4 0x020e0300 0x00000030 -DATA 4 0x020e031c 0x00000030 -DATA 4 0x020e0338 0x00000028 -DATA 4 0x020e0320 0x00000030 -DATA 4 0x020e032c 0x00000000 -DATA 4 0x020e033c 0x00000008 -DATA 4 0x020e0340 0x00000008 -DATA 4 0x020e05c4 0x00000030 -DATA 4 0x020e05cc 0x00000030 -DATA 4 0x020e05d4 0x00000030 -DATA 4 0x020e05d8 0x00000030 -DATA 4 0x020e05ac 0x00000030 -DATA 4 0x020e05c8 0x00000030 -DATA 4 0x020e05b0 0x00020000 -DATA 4 0x020e05b4 0x00000000 -DATA 4 0x020e05c0 0x00020000 -DATA 4 0x020e05d0 0x00080000 - -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b085c 0x1b4700c7 -DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b0890 0x00400000 -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 -DATA 4 0x021b082c 0xf3333333 -DATA 4 0x021b0830 0xf3333333 -DATA 4 0x021b0834 0xf3333333 -DATA 4 0x021b0838 0xf3333333 -DATA 4 0x021b0848 0x4241444a -DATA 4 0x021b0850 0x3030312b -DATA 4 0x021b083c 0x20000000 -DATA 4 0x021b0840 0x00000000 -DATA 4 0x021b08c0 0x24911492 -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b000c 0x33374133 -DATA 4 0x021b0004 0x00020024 -DATA 4 0x021b0010 0x00100A82 -DATA 4 0x021b0014 0x00000093 -DATA 4 0x021b0018 0x00001688 -DATA 4 0x021b002c 0x0f9f26d2 -DATA 4 0x021b0030 0x009f0e10 -DATA 4 0x021b0038 0x00190778 -DATA 4 0x021b0008 0x00000000 -DATA 4 0x021b0040 0x0000004f -DATA 4 0x021b0000 0xc3110000 -DATA 4 0x021b001c 0x003f8030 -DATA 4 0x021b001c 0xff0a8030 -DATA 4 0x021b001c 0x82018030 -DATA 4 0x021b001c 0x04028030 -DATA 4 0x021b001c 0x02038030 -DATA 4 0x021b001c 0xff0a8038 -DATA 4 0x021b001c 0x82018038 -DATA 4 0x021b001c 0x04028038 -DATA 4 0x021b001c 0x02038038 -DATA 4 0x021b0800 0xa1310003 -DATA 4 0x021b0020 0x00001800 -DATA 4 0x021b0818 0x00000000 -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b0004 0x00025564 -DATA 4 0x021b0404 0x00011006 -DATA 4 0x021b001c 0x00000000 diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c deleted file mode 100644 index fb145fa6aac..00000000000 --- a/board/freescale/mx6slevk/mx6slevk.c +++ /dev/null @@ -1,390 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/pfuze.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ - PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ - PAD_CTL_SRE_FAST) - -#define ETH_PHY_POWER IMX_GPIO_NR(4, 21) - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -#ifdef CONFIG_XPL_BUILD -static iomux_v3_cfg_t const usdhc1_pads[] = { - /* 8 bit SD */ - MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - - /*CD pin*/ - MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - - /*CD pin*/ - MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - - /*CD pin*/ - MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; -#endif - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -int board_mmc_get_env_dev(int devno) -{ - return devno; -} - -#ifdef CONFIG_DM_PMIC_PFUZE100 -int power_init_board(void) -{ - struct udevice *dev; - int ret; - u32 dev_id, rev_id, i; - u32 switch_num = 6; - u32 offset = PFUZE100_SW1CMODE; - - ret = pmic_get("pfuze100@08", &dev); - if (ret == -ENODEV) - return 0; - - if (ret != 0) - return ret; - - dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); - rev_id = pmic_reg_read(dev, PFUZE100_REVID); - printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); - - /* set SW1AB staby volatage 0.975V */ - pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); - - /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); - - /* set SW1C staby volatage 0.975V */ - pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b); - - /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ - pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); - - /* Init mode to APS_PFM */ - pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM); - - for (i = 0; i < switch_num - 1; i++) - pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM); - - return 0; -} -#endif - -#ifdef CONFIG_FEC_MXC - -static int setup_fec(void) -{ - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* clear gpr1[14], gpr1[18:17] to select anatop clock */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); - - return enable_fec_anatop_clock(0, ENET_50MHZ); -} -#endif - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - -#ifdef CONFIG_FEC_MXC - setup_fec(); -#endif - - return 0; -} - -int checkboard(void) -{ - puts("Board: MX6SLEVK\n"); - - return 0; -} - -#ifdef CONFIG_XPL_BUILD -#include -#include - -#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7) -#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0) -#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22) - -static struct fsl_esdhc_cfg usdhc_cfg[3] = { - {USDHC1_BASE_ADDR}, - {USDHC2_BASE_ADDR, 0, 4}, - {USDHC3_BASE_ADDR, 0, 4}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - gpio_request(USDHC1_CD_GPIO, "cd1_gpio"); - ret = !gpio_get_value(USDHC1_CD_GPIO); - break; - case USDHC2_BASE_ADDR: - gpio_request(USDHC2_CD_GPIO, "cd2_gpio"); - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - gpio_request(USDHC3_CD_GPIO, "cd3_gpio"); - ret = !gpio_get_value(USDHC3_CD_GPIO); - break; - } - - return ret; -} - -int board_mmc_init(struct bd_info *bis) -{ - struct src *src_regs = (struct src *)SRC_BASE_ADDR; - u32 val; - u32 port; - - val = readl(&src_regs->sbmr1); - - /* Boot from USDHC */ - port = (val >> 11) & 0x3; - switch (port) { - case 0: - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, - ARRAY_SIZE(usdhc1_pads)); - gpio_direction_input(USDHC1_CD_GPIO); - usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - break; - case 1: - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, - ARRAY_SIZE(usdhc2_pads)); - gpio_direction_input(USDHC2_CD_GPIO); - usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; - usdhc_cfg[0].max_bus_width = 4; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - break; - case 2: - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, - ARRAY_SIZE(usdhc3_pads)); - gpio_direction_input(USDHC3_CD_GPIO); - usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; - usdhc_cfg[0].max_bus_width = 4; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - } - - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} - -const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = { - .dram_sdqs0 = 0x00003030, - .dram_sdqs1 = 0x00003030, - .dram_sdqs2 = 0x00003030, - .dram_sdqs3 = 0x00003030, - .dram_dqm0 = 0x00000030, - .dram_dqm1 = 0x00000030, - .dram_dqm2 = 0x00000030, - .dram_dqm3 = 0x00000030, - .dram_cas = 0x00000030, - .dram_ras = 0x00000030, - .dram_sdclk_0 = 0x00000028, - .dram_reset = 0x00000030, - .dram_sdba2 = 0x00000000, - .dram_odt0 = 0x00000008, - .dram_odt1 = 0x00000008, -}; - -const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = { - .grp_b0ds = 0x00000030, - .grp_b1ds = 0x00000030, - .grp_b2ds = 0x00000030, - .grp_b3ds = 0x00000030, - .grp_addds = 0x00000030, - .grp_ctlds = 0x00000030, - .grp_ddrmode_ctl = 0x00020000, - .grp_ddrpke = 0x00000000, - .grp_ddrmode = 0x00020000, - .grp_ddr_type = 0x00080000, -}; - -const struct mx6_mmdc_calibration mx6_mmcd_calib = { - .p0_mpdgctrl0 = 0x20000000, - .p0_mpdgctrl1 = 0x00000000, - .p0_mprddlctl = 0x4241444a, - .p0_mpwrdlctl = 0x3030312b, - .mpzqlp2ctl = 0x1b4700c7, -}; - -static struct mx6_lpddr2_cfg mem_ddr = { - .mem_speed = 800, - .density = 4, - .width = 32, - .banks = 8, - .rowaddr = 14, - .coladdr = 10, - .trcd_lp = 2000, - .trppb_lp = 2000, - .trpab_lp = 2250, - .trasmin = 4200, -}; - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0xFFFFFFFF, &ccm->CCGR0); - writel(0xFFFFFFFF, &ccm->CCGR1); - writel(0xFFFFFFFF, &ccm->CCGR2); - writel(0xFFFFFFFF, &ccm->CCGR3); - writel(0xFFFFFFFF, &ccm->CCGR4); - writel(0xFFFFFFFF, &ccm->CCGR5); - writel(0xFFFFFFFF, &ccm->CCGR6); - - writel(0x00260324, &ccm->cbcmr); -} - -static void spl_dram_init(void) -{ - struct mx6_ddr_sysinfo sysinfo = { - .dsize = mem_ddr.width / 32, - .cs_density = 20, - .ncs = 2, - .cs1_mirror = 0, - .walat = 0, - .ralat = 2, - .mif3_mode = 3, - .bi_on = 1, - .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */ - .rtt_nom = 0, - .sde_to_rst = 0, /* LPDDR2 does not need this field */ - .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ - .ddr_type = DDR_TYPE_LPDDR2, - .refsel = 0, /* Refresh cycles at 64KHz */ - .refr = 3, /* 4 refresh commands per refresh cycle */ - }; - mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); -} - -void board_init_f(ulong dummy) -{ - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - ccgr_init(); - - /* iomux and setup of i2c */ - board_early_init_f(); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* DDR initialization */ - spl_dram_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); -} -#endif diff --git a/board/freescale/mx6sllevk/Kconfig b/board/freescale/mx6sllevk/Kconfig deleted file mode 100644 index d47f1fa9096..00000000000 --- a/board/freescale/mx6sllevk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX6SLLEVK - -config SYS_BOARD - default "mx6sllevk" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "mx6sllevk" - -config IMX_CONFIG - default "board/freescale/mx6sllevk/imximage.cfg" - -endif diff --git a/board/freescale/mx6sllevk/MAINTAINERS b/board/freescale/mx6sllevk/MAINTAINERS deleted file mode 100644 index b82273c0162..00000000000 --- a/board/freescale/mx6sllevk/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MX6SLLEVK BOARD -M: Peng Fan -S: Maintained -F: board/freescale/mx6sllevk/ -F: include/configs/mx6sllevk.h -F: configs/mx6sllevk_defconfig -F: configs/mx6sllevk_plugin_defconfig diff --git a/board/freescale/mx6sllevk/Makefile b/board/freescale/mx6sllevk/Makefile deleted file mode 100644 index 8f724ccfc92..00000000000 --- a/board/freescale/mx6sllevk/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# (C) Copyright 2016 Freescale Semiconductor, Inc. - -obj-y := mx6sllevk.o diff --git a/board/freescale/mx6sllevk/imximage.cfg b/board/freescale/mx6sllevk/imximage.cfg deleted file mode 100644 index 550be3f6c12..00000000000 --- a/board/freescale/mx6sllevk/imximage.cfg +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * - * Refer docs/README.imxmage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -#include - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ - -BOOT_FROM sd - -#ifdef CONFIG_USE_IMXIMG_PLUGIN -/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ -PLUGIN board/freescale/mx6sllevk/plugin.bin 0x00907000 -#else - -#ifdef CONFIG_IMX_HAB -CSF CONFIG_CSF_SIZE -#endif - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* Enable all clocks */ -DATA 4 0x020c4068 0xffffffff -DATA 4 0x020c406c 0xffffffff -DATA 4 0x020c4070 0xffffffff -DATA 4 0x020c4074 0xffffffff -DATA 4 0x020c4078 0xffffffff -DATA 4 0x020c407c 0xffffffff -DATA 4 0x020c4080 0xffffffff - -DATA 4 0x020E0550 0x00080000 -DATA 4 0x020E0534 0x00000000 -DATA 4 0x020E02AC 0x00000030 -DATA 4 0x020E0548 0x00000030 -DATA 4 0x020E052C 0x00000030 -DATA 4 0x020E0530 0x00020000 -DATA 4 0x020E02B0 0x00003030 -DATA 4 0x020E02B4 0x00003030 -DATA 4 0x020E02B8 0x00003030 -DATA 4 0x020E02BC 0x00003030 -DATA 4 0x020E0540 0x00020000 -DATA 4 0x020E0544 0x00000030 -DATA 4 0x020E054C 0x00000030 -DATA 4 0x020E0554 0x00000030 -DATA 4 0x020E0558 0x00000030 -DATA 4 0x020E0294 0x00000030 -DATA 4 0x020E0298 0x00000030 -DATA 4 0x020E029C 0x00000030 -DATA 4 0x020E02A0 0x00000030 -DATA 4 0x020E02C0 0x00082030 - -DATA 4 0x021B001C 0x00008000 - -DATA 4 0x021B0800 0xA1390003 -DATA 4 0x021B085c 0x084700C7 -DATA 4 0x021B0890 0x00400000 -DATA 4 0x021B0848 0x3F393B3C -DATA 4 0x021B0850 0x262C3826 -DATA 4 0x021B081C 0x33333333 -DATA 4 0x021B0820 0x33333333 -DATA 4 0x021B0824 0x33333333 -DATA 4 0x021B0828 0x33333333 - -DATA 4 0x021B082C 0xf3333333 -DATA 4 0x021B0830 0xf3333333 -DATA 4 0x021B0834 0xf3333333 -DATA 4 0x021B0838 0xf3333333 -DATA 4 0x021B08C0 0x24922492 -DATA 4 0x021B08b8 0x00000800 - -DATA 4 0x021B0004 0x00020052 -DATA 4 0x021B000C 0x53574333 -DATA 4 0x021B0010 0x00100B22 -DATA 4 0x021B0038 0x00170778 -DATA 4 0x021B0014 0x00C700DB -DATA 4 0x021B0018 0x00201718 -DATA 4 0x021B002C 0x0F9F26D2 -DATA 4 0x021B0030 0x009F0E10 -DATA 4 0x021B0040 0x0000005F -DATA 4 0x021B0000 0xC4190000 - -DATA 4 0x021B083C 0x20000000 - -DATA 4 0x021B001C 0x00008050 -DATA 4 0x021B001C 0x00008058 -DATA 4 0x021B001C 0x003F8030 -DATA 4 0x021B001C 0x003F8038 -DATA 4 0x021B001C 0xFF0A8030 -DATA 4 0x021B001C 0xFF0A8038 -DATA 4 0x021B001C 0x04028030 -DATA 4 0x021B001C 0x04028038 -DATA 4 0x021B001C 0x83018030 -DATA 4 0x021B001C 0x83018038 -DATA 4 0x021B001C 0x01038030 -DATA 4 0x021B001C 0x01038038 - -DATA 4 0x021B0020 0x00001800 -DATA 4 0x021B0800 0xA1390003 -DATA 4 0x021B0004 0x00020052 -DATA 4 0x021B0404 0x00011006 -DATA 4 0x021B001C 0x00000000 -#endif diff --git a/board/freescale/mx6sllevk/mx6sllevk.c b/board/freescale/mx6sllevk/mx6sllevk.c deleted file mode 100644 index 9e39e39ac90..00000000000 --- a/board/freescale/mx6sllevk/mx6sllevk.c +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/pfuze.h" - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -static iomux_v3_cfg_t const wdog_pads[] = { - MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -#ifdef CONFIG_DM_PMIC_PFUZE100 -int power_init_board(void) -{ - struct udevice *dev; - int ret; - u32 dev_id, rev_id, i; - u32 switch_num = 6; - u32 offset = PFUZE100_SW1CMODE; - - ret = pmic_get("pfuze100@8", &dev); - if (ret == -ENODEV) - return 0; - - if (ret != 0) - return ret; - - dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); - rev_id = pmic_reg_read(dev, PFUZE100_REVID); - printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); - - /* Init mode to APS_PFM */ - pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM); - - for (i = 0; i < switch_num - 1; i++) - pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM); - - /* set SW1AB staby volatage 0.975V */ - pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); - - /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); - - /* set SW1C staby volatage 0.975V */ - pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b); - - /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ - pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); - - return 0; -} -#endif - -int board_early_init_f(void) -{ - return 0; -} - -int board_init(void) -{ - /* Address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -int board_late_init(void) -{ - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - return 0; -} - -int checkboard(void) -{ - puts("Board: MX6SLL EVK\n"); - - return 0; -} - -int board_mmc_get_env_dev(int devno) -{ - return devno; -} - -int mmc_map_to_kernel_blk(int devno) -{ - return devno; -} diff --git a/board/freescale/mx6sllevk/plugin.S b/board/freescale/mx6sllevk/plugin.S deleted file mode 100644 index dcf5e14d48a..00000000000 --- a/board/freescale/mx6sllevk/plugin.S +++ /dev/null @@ -1,154 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#include - -/* DDR script */ -.macro imx6sll_evk_ddr_setting - ldr r0, =IOMUXC_BASE_ADDR - ldr r1, =0x00080000 - str r1, [r0, #0x550] - ldr r1, =0x00000000 - str r1, [r0, #0x534] - ldr r1, =0x00000030 - str r1, [r0, #0x2AC] - str r1, [r0, #0x548] - str r1, [r0, #0x52C] - ldr r1, =0x00020000 - str r1, [r0, #0x530] - ldr r1, =0x00003030 - str r1, [r0, #0x2B0] - str r1, [r0, #0x2B4] - str r1, [r0, #0x2B8] - str r1, [r0, #0x2BC] - - ldr r1, =0x00020000 - str r1, [r0, #0x540] - ldr r1, =0x00000030 - str r1, [r0, #0x544] - str r1, [r0, #0x54C] - str r1, [r0, #0x554] - str r1, [r0, #0x558] - str r1, [r0, #0x294] - str r1, [r0, #0x298] - str r1, [r0, #0x29C] - str r1, [r0, #0x2A0] - - ldr r1, =0x00082030 - str r1, [r0, #0x2C0] - - ldr r0, =MMDC_P0_BASE_ADDR - ldr r1, =0x00008000 - str r1, [r0, #0x1C] - ldr r1, =0xA1390003 - str r1, [r0, #0x800] - ldr r1, =0x084700C7 - str r1, [r0, #0x85C] - ldr r1, =0x00400000 - str r1, [r0, #0x890] - - ldr r1, =0x3F393B3C - str r1, [r0, #0x848] - ldr r1, =0x262C3826 - str r1, [r0, #0x850] - - ldr r1, =0x33333333 - str r1, [r0, #0x81C] - str r1, [r0, #0x820] - str r1, [r0, #0x824] - str r1, [r0, #0x828] - - ldr r1, =0xf3333333 - str r1, [r0, #0x82C] - str r1, [r0, #0x830] - str r1, [r0, #0x834] - str r1, [r0, #0x838] - - ldr r1, =0x24922492 - str r1, [r0, #0x8C0] - ldr r1, =0x00000800 - str r1, [r0, #0x8B8] - - ldr r1, =0x00020052 - str r1, [r0, #0x004] - ldr r1, =0x53574333 - str r1, [r0, #0x00C] - ldr r1, =0x00100B22 - str r1, [r0, #0x010] - ldr r1, =0x00170778 - str r1, [r0, #0x038] - ldr r1, =0x00C700DB - str r1, [r0, #0x014] - ldr r1, =0x00201718 - str r1, [r0, #0x018] - ldr r1, =0x0F9F26D2 - str r1, [r0, #0x02C] - ldr r1, =0x009F0E10 - str r1, [r0, #0x030] - ldr r1, =0x0000005F - str r1, [r0, #0x040] - ldr r1, =0xC4190000 - str r1, [r0, #0x000] - ldr r1, =0x20000000 - str r1, [r0, #0x83C] - - ldr r1, =0x00008050 - str r1, [r0, #0x01C] - ldr r1, =0x00008058 - str r1, [r0, #0x01C] - ldr r1, =0x003F8030 - str r1, [r0, #0x01C] - ldr r1, =0x003F8038 - str r1, [r0, #0x01C] - ldr r1, =0xFF0A8030 - str r1, [r0, #0x01C] - ldr r1, =0xFF0A8038 - str r1, [r0, #0x01C] - ldr r1, =0x04028030 - str r1, [r0, #0x01C] - ldr r1, =0x04028038 - str r1, [r0, #0x01C] - ldr r1, =0x83018030 - str r1, [r0, #0x01C] - ldr r1, =0x83018038 - str r1, [r0, #0x01C] - ldr r1, =0x01038030 - str r1, [r0, #0x01C] - ldr r1, =0x01038038 - str r1, [r0, #0x01C] - - ldr r1, =0x00001800 - str r1, [r0, #0x020] - ldr r1, =0xA1390003 - str r1, [r0, #0x800] - ldr r1, =0x00020052 - str r1, [r0, #0x004] - ldr r1, =0x00011006 - str r1, [r0, #0x404] - ldr r1, =0x00000000 - str r1, [r0, #0x01C] -.endm - -.macro imx6_clock_gating - ldr r0, =CCM_BASE_ADDR - ldr r1, =0xffffffff - str r1, [r0, #0x068] - str r1, [r0, #0x06c] - str r1, [r0, #0x070] - str r1, [r0, #0x074] - str r1, [r0, #0x078] - str r1, [r0, #0x07c] - str r1, [r0, #0x080] -.endm - -.macro imx6_qos_setting -.endm - -.macro imx6_ddr_setting - imx6sll_evk_ddr_setting -.endm - -/* include the common plugin code here */ -#include diff --git a/board/freescale/mx6sxsabreauto/Kconfig b/board/freescale/mx6sxsabreauto/Kconfig deleted file mode 100644 index e6da7b38f91..00000000000 --- a/board/freescale/mx6sxsabreauto/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX6SXSABREAUTO - -config SYS_BOARD - default "mx6sxsabreauto" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "mx6sxsabreauto" - -config IMX_CONFIG - default "board/freescale/mx6sxsabreauto/imximage.cfg" - -endif diff --git a/board/freescale/mx6sxsabreauto/MAINTAINERS b/board/freescale/mx6sxsabreauto/MAINTAINERS deleted file mode 100644 index 8dc62e5e3e5..00000000000 --- a/board/freescale/mx6sxsabreauto/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX6SXSABREAUTO BOARD -M: Peng Fan -S: Maintained -F: board/freescale/mx6sxsabreauto/ -F: include/configs/mx6sxsabreauto.h -F: configs/mx6sxsabreauto_defconfig diff --git a/board/freescale/mx6sxsabreauto/Makefile b/board/freescale/mx6sxsabreauto/Makefile deleted file mode 100644 index 50f29a9dd02..00000000000 --- a/board/freescale/mx6sxsabreauto/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# (C) Copyright 2014 Freescale Semiconductor, Inc. - -obj-y := mx6sxsabreauto.o diff --git a/board/freescale/mx6sxsabreauto/imximage.cfg b/board/freescale/mx6sxsabreauto/imximage.cfg deleted file mode 100644 index da703093aa6..00000000000 --- a/board/freescale/mx6sxsabreauto/imximage.cfg +++ /dev/null @@ -1,134 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - */ - -#include - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi/sd/nand/onenand, qspi/nor - */ - -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* Enable all clocks */ -DATA 4 0x020c4068 0xffffffff -DATA 4 0x020c406c 0xffffffff -DATA 4 0x020c4070 0xffffffff -DATA 4 0x020c4074 0xffffffff -DATA 4 0x020c4078 0xffffffff -DATA 4 0x020c407c 0xffffffff -DATA 4 0x020c4080 0xffffffff -DATA 4 0x020c4084 0xffffffff - -/* IOMUX - DDR IO Type */ -DATA 4 0x020e0618 0x000c0000 -DATA 4 0x020e05fc 0x00000000 - -/* Clock */ -DATA 4 0x020e032c 0x00000030 - -/* Address */ -DATA 4 0x020e0300 0x00000030 -DATA 4 0x020e02fc 0x00000030 -DATA 4 0x020e05f4 0x00000030 - -/* Control */ -DATA 4 0x020e0340 0x00000030 - -DATA 4 0x020e0320 0x00000000 -DATA 4 0x020e0310 0x00000030 -DATA 4 0x020e0314 0x00000030 -DATA 4 0x020e0614 0x00000030 - -/* Data Strobe */ -DATA 4 0x020e05f8 0x00020000 -DATA 4 0x020e0330 0x00000030 -DATA 4 0x020e0334 0x00000030 -DATA 4 0x020e0338 0x00000030 -DATA 4 0x020e033c 0x00000030 - -/* Data */ -DATA 4 0x020e0608 0x00020000 -DATA 4 0x020e060c 0x00000030 -DATA 4 0x020e0610 0x00000030 -DATA 4 0x020e061c 0x00000030 -DATA 4 0x020e0620 0x00000030 -DATA 4 0x020e02ec 0x00000030 -DATA 4 0x020e02f0 0x00000030 -DATA 4 0x020e02f4 0x00000030 -DATA 4 0x020e02f8 0x00000030 - -/* Calibrations - ZQ */ -DATA 4 0x021b0800 0xa1390003 - -/* Write leveling */ -DATA 4 0x021b080c 0x002C003D -DATA 4 0x021b0810 0x00110046 - -/* DQS Read Gate */ -DATA 4 0x021b083c 0x4160016C -DATA 4 0x021b0840 0x013C016C - -/* Read/Write Delay */ -DATA 4 0x021b0848 0x46424446 -DATA 4 0x021b0850 0x3A3C3C3A - -DATA 4 0x021b08c0 0x2492244A - -/* read data bit delay */ -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 - -/* Complete calibration by forced measurement */ -DATA 4 0x021b08b8 0x00000800 - -/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ -DATA 4 0x021b0004 0x0002002d -DATA 4 0x021b0008 0x00333030 -DATA 4 0x021b000c 0x676b52f3 -DATA 4 0x021b0010 0xb66d8b63 -DATA 4 0x021b0014 0x01ff00db -DATA 4 0x021b0018 0x00011740 -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b002c 0x000026d2 -DATA 4 0x021b0030 0x006b1023 -DATA 4 0x021b0040 0x0000007f -DATA 4 0x021b0000 0x85190000 - -/* Initialize MT41K256M16HA-125 - MR2 */ -DATA 4 0x021b001c 0x04008032 -/* MR3 */ -DATA 4 0x021b001c 0x00008033 -/* MR1 */ -DATA 4 0x021b001c 0x00068031 -/* MR0 */ -DATA 4 0x021b001c 0x05208030 -/* DDR device ZQ calibration */ -DATA 4 0x021b001c 0x04008040 - -/* Final DDR setup, before operation start */ -DATA 4 0x021b0020 0x00000800 -DATA 4 0x021b0818 0x00022227 -DATA 4 0x021b0004 0x0002556d -DATA 4 0x021b0404 0x00011006 -DATA 4 0x021b001c 0x00000000 diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c deleted file mode 100644 index d80cfd4ab27..00000000000 --- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +++ /dev/null @@ -1,324 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - * - * Author: Ye Li - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/pfuze.h" -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) - -#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) - -#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) -#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ - PAD_CTL_SRE_FAST) -#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -static iomux_v3_cfg_t const fec2_pads[] = { - MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -static int setup_fec(void) -{ - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); - - return enable_fec_anatop_clock(1, ENET_125MHZ); -} - -int board_eth_init(struct bd_info *bis) -{ - int ret; - - imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); - setup_fec(); - - ret = fecmxc_initialize_multi(bis, 1, - CFG_FEC_MXC_PHYADDR, IMX_FEC_BASE); - if (ret) - printf("FEC%d MXC: %s:failed\n", 1, __func__); - - return ret; -} - -int board_phy_config(struct phy_device *phydev) -{ - /* - * Enable 1.8V(SEL_1P5_1P8_POS_REG) on - * Phy control debug reg 0 - */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); - - /* rgmii tx clock delay enable */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int power_init_board(void) -{ - struct udevice *dev; - int ret; - u32 dev_id, rev_id, i; - u32 switch_num = 6; - u32 offset = PFUZE100_SW1CMODE; - - ret = pmic_get("pfuze100", &dev); - if (ret == -ENODEV) - return 0; - - if (ret != 0) - return ret; - - dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); - rev_id = pmic_reg_read(dev, PFUZE100_REVID); - printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); - - /* Init mode to APS_PFM */ - pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM); - - for (i = 0; i < switch_num - 1; i++) - pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM); - - /* set SW1AB staby volatage 0.975V */ - pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); - - /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); - - /* set SW1C staby volatage 1.10V */ - pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20); - - /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ - pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); - - return 0; -} - -#ifdef CONFIG_USB_EHCI_MX6 -#define USB_OTHERREGS_OFFSET 0x800 -#define UCTRL_PWR_POL (1 << 9) - -static iomux_v3_cfg_t const usb_otg_pads[] = { - /* OGT1 */ - MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), - /* OTG2 */ - MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) -}; - -static void setup_usb(void) -{ - imx_iomux_v3_setup_multiple_pads(usb_otg_pads, - ARRAY_SIZE(usb_otg_pads)); -} - -int board_usb_phy_mode(int port) -{ - if (port == 1) - return USB_INIT_HOST; - else - return usb_phy_mode(port); -} - -int board_ehci_hcd_init(int port) -{ - u32 *usbnc_usb_ctrl; - - if (port > 1) - return -EINVAL; - - usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + - port * 4); - - /* Set Power polarity */ - setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); - - return 0; -} -#endif - -int board_early_init_f(void) -{ - return 0; -} - -#ifdef CONFIG_FSL_QSPI -int board_qspi_init(void) -{ - /* Set the clock */ - enable_qspi_clk(0); - - return 0; -} -#endif - -#ifdef CONFIG_NAND_MXS -iomux_v3_cfg_t gpmi_pads[] = { - MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0), - MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), -}; - -static void setup_gpmi_nand(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - /* config gpmi nand iomux */ - imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); - - setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) | - MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) | - MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3))); - - /* enable apbh clock gating */ - setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); -} -#endif - -int board_init(void) -{ - struct gpio_desc desc; - int ret; - - /* Address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - ret = dm_gpio_lookup_name("gpio@30_4", &desc); - if (ret) - return ret; - - ret = dm_gpio_request(&desc, "cpu_per_rst_b"); - if (ret) - return ret; - /* Reset CPU_PER_RST_B signal for enet phy and PCIE */ - dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); - udelay(500); - dm_gpio_set_value(&desc, 1); - - ret = dm_gpio_lookup_name("gpio@32_2", &desc); - if (ret) - return ret; - - ret = dm_gpio_request(&desc, "steer_enet"); - if (ret) - return ret; - - dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); - udelay(500); - /* Set steering signal to L for selecting B0 */ - dm_gpio_set_value(&desc, 0); - -#ifdef CONFIG_USB_EHCI_MX6 - setup_usb(); -#endif - -#ifdef CONFIG_FSL_QSPI - board_qspi_init(); -#endif - -#ifdef CONFIG_NAND_MXS - setup_gpmi_nand(); -#endif - - return 0; -} - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - {"sda", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)}, - {"sdb", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, - {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, - {"nand", MAKE_CFGVAL(0x82, 0x00, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - -int board_late_init(void) -{ -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - - return 0; -} - -int checkboard(void) -{ - puts("Board: MX6SX SABRE AUTO\n"); - - return 0; -} diff --git a/board/freescale/mx6sxsabresd/Kconfig b/board/freescale/mx6sxsabresd/Kconfig deleted file mode 100644 index 88ac7ee8050..00000000000 --- a/board/freescale/mx6sxsabresd/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX6SXSABRESD - -config SYS_BOARD - default "mx6sxsabresd" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "mx6sxsabresd" - -config IMX_CONFIG - default "board/freescale/mx6sxsabresd/imximage.cfg" - -endif diff --git a/board/freescale/mx6sxsabresd/MAINTAINERS b/board/freescale/mx6sxsabresd/MAINTAINERS deleted file mode 100644 index b3c8b56f1f1..00000000000 --- a/board/freescale/mx6sxsabresd/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX6SXSABRESD BOARD -M: Fabio Estevam -S: Maintained -F: board/freescale/mx6sxsabresd/ -F: include/configs/mx6sxsabresd.h -F: configs/mx6sxsabresd_defconfig diff --git a/board/freescale/mx6sxsabresd/Makefile b/board/freescale/mx6sxsabresd/Makefile deleted file mode 100644 index 266bd4ac495..00000000000 --- a/board/freescale/mx6sxsabresd/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# (C) Copyright 2014 Freescale Semiconductor, Inc. - -obj-y := mx6sxsabresd.o diff --git a/board/freescale/mx6sxsabresd/imximage.cfg b/board/freescale/mx6sxsabresd/imximage.cfg deleted file mode 100644 index 313ab589505..00000000000 --- a/board/freescale/mx6sxsabresd/imximage.cfg +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - */ - -#include - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi/sd/nand/onenand, qspi/nor - */ - -BOOT_FROM sd - -/* - * Secure boot support - */ -#ifdef CONFIG_IMX_HAB -CSF CONFIG_CSF_SIZE -#endif - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* Enable all clocks */ -DATA 4 0x020c4068 0xffffffff -DATA 4 0x020c406c 0xffffffff -DATA 4 0x020c4070 0xffffffff -DATA 4 0x020c4074 0xffffffff -DATA 4 0x020c4078 0xffffffff -DATA 4 0x020c407c 0xffffffff -DATA 4 0x020c4080 0xffffffff -DATA 4 0x020c4084 0xffffffff - -/* IOMUX - DDR IO Type */ -DATA 4 0x020e0618 0x000c0000 -DATA 4 0x020e05fc 0x00000000 - -/* Clock */ -DATA 4 0x020e032c 0x00000030 - -/* Address */ -DATA 4 0x020e0300 0x00000020 -DATA 4 0x020e02fc 0x00000020 -DATA 4 0x020e05f4 0x00000020 - -/* Control */ -DATA 4 0x020e0340 0x00000020 - -DATA 4 0x020e0320 0x00000000 -DATA 4 0x020e0310 0x00000020 -DATA 4 0x020e0314 0x00000020 -DATA 4 0x020e0614 0x00000020 - -/* Data Strobe */ -DATA 4 0x020e05f8 0x00020000 -DATA 4 0x020e0330 0x00000028 -DATA 4 0x020e0334 0x00000028 -DATA 4 0x020e0338 0x00000028 -DATA 4 0x020e033c 0x00000028 - -/* Data */ -DATA 4 0x020e0608 0x00020000 -DATA 4 0x020e060c 0x00000028 -DATA 4 0x020e0610 0x00000028 -DATA 4 0x020e061c 0x00000028 -DATA 4 0x020e0620 0x00000028 -DATA 4 0x020e02ec 0x00000028 -DATA 4 0x020e02f0 0x00000028 -DATA 4 0x020e02f4 0x00000028 -DATA 4 0x020e02f8 0x00000028 - -/* Calibrations - ZQ */ -DATA 4 0x021b0800 0xa1390003 - -/* Write leveling */ -DATA 4 0x021b080c 0x00290025 -DATA 4 0x021b0810 0x00220022 - -/* DQS Read Gate */ -DATA 4 0x021b083c 0x41480144 -DATA 4 0x021b0840 0x01340130 - -/* Read/Write Delay */ -DATA 4 0x021b0848 0x3C3E4244 -DATA 4 0x021b0850 0x34363638 - -/* Read data bit delay */ -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 - -/* Complete calibration by forced measurement */ -DATA 4 0x021b08b8 0x00000800 - -/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ -DATA 4 0x021b0004 0x0002002d -DATA 4 0x021b0008 0x00333030 -DATA 4 0x021b000c 0x676b52f3 -DATA 4 0x021b0010 0xb66d8b63 -DATA 4 0x021b0014 0x01ff00db -DATA 4 0x021b0018 0x00011740 -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b002c 0x000026d2 -DATA 4 0x021b0030 0x006b1023 -DATA 4 0x021b0040 0x0000005f -DATA 4 0x021b0000 0x84190000 - -/* Initialize MT41K256M16HA-125 - MR2 */ -DATA 4 0x021b001c 0x04008032 -/* MR3 */ -DATA 4 0x021b001c 0x00008033 -/* MR1 */ -DATA 4 0x021b001c 0x00048031 -/* MR0 */ -DATA 4 0x021b001c 0x05208030 -/* DDR device ZQ calibration */ -DATA 4 0x021b001c 0x04008040 - -/* Final DDR setup, before operation start */ -DATA 4 0x021b0020 0x00000800 -DATA 4 0x021b0818 0x00011117 -DATA 4 0x021b001c 0x00000000 diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c deleted file mode 100644 index e3353feec68..00000000000 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ /dev/null @@ -1,328 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/pfuze.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) - -#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) - -#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) - -#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm) - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const wdog_b_pad = { - MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; -static iomux_v3_cfg_t const fec1_pads[] = { - MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -static iomux_v3_cfg_t const peri_3v3_pads[] = { - MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const phy_control_pads[] = { - /* 25MHz Ethernet PHY Clock */ - MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), - - /* ENET PHY Power */ - MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL), - - /* AR8031 PHY Reset */ - MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -static int setup_fec(void) -{ - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - int reg, ret; - - /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); - - ret = enable_fec_anatop_clock(0, ENET_125MHZ); - if (ret) - return ret; - - imx_iomux_v3_setup_multiple_pads(phy_control_pads, - ARRAY_SIZE(phy_control_pads)); - - /* Enable the ENET power, active low */ - gpio_request(IMX_GPIO_NR(2, 6), "enet_rst"); - gpio_direction_output(IMX_GPIO_NR(2, 6) , 0); - - /* Reset AR8031 PHY */ - gpio_request(IMX_GPIO_NR(2, 7), "phy_rst"); - gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); - mdelay(10); - gpio_set_value(IMX_GPIO_NR(2, 7), 1); - - reg = readl(&anatop->pll_enet); - reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; - writel(reg, &anatop->pll_enet); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); - setup_fec(); - - return cpu_eth_init(bis); -} - -int power_init_board(void) -{ - struct udevice *dev; - unsigned int reg; - int ret; - - dev = pfuze_common_init(); - if (!dev) - return -ENODEV; - - ret = pfuze_mode_init(dev, APS_PFM); - if (ret < 0) - return ret; - - /* Enable power of VGEN5 3V3, needed for SD3 */ - reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); - reg &= ~LDO_VOL_MASK; - reg |= (LDOB_3_30V | (1 << LDO_EN)); - pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - /* - * Enable 1.8V(SEL_1P5_1P8_POS_REG) on - * Phy control debug reg 0 - */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); - - /* rgmii tx clock delay enable */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ - imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, - ARRAY_SIZE(peri_3v3_pads)); - - return 0; -} - -int board_mmc_get_env_dev(int devno) -{ - return devno; -} - -#ifdef CONFIG_FSL_QSPI - -int board_qspi_init(void) -{ - /* Set the clock */ - enable_qspi_clk(1); - - return 0; -} -#endif - -#ifdef CONFIG_VIDEO_MXS -static iomux_v3_cfg_t const lcd_pads[] = { - MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL), - - /* Use GPIO for Brightness adjustment, duty cycle = period */ - MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static int setup_lcd(void) -{ - enable_lcdif_clock(LCDIF1_BASE_ADDR, 1); - - imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); - - /* Reset the LCD */ - gpio_request(IMX_GPIO_NR(3, 27), "lcd_rst"); - gpio_direction_output(IMX_GPIO_NR(3, 27) , 0); - udelay(500); - gpio_direction_output(IMX_GPIO_NR(3, 27) , 1); - - /* Set Brightness to high */ - gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright"); - gpio_direction_output(IMX_GPIO_NR(6, 4) , 1); - - return 0; -} -#endif - -int board_init(void) -{ - /* Address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - /* - * Because kernel set WDOG_B mux before pad with the common pinctrl - * framwork now and wdog reset will be triggered once set WDOG_B mux - * with default pad setting, we set pad setting here to workaround this. - * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set - * as GPIO mux firstly here to workaround it. - */ - imx_iomux_v3_setup_pad(wdog_b_pad); - - /* Active high for ncp692 */ - gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en"); - gpio_direction_output(IMX_GPIO_NR(4, 16), 1); - -#ifdef CONFIG_FSL_QSPI - board_qspi_init(); -#endif - -#ifdef CONFIG_VIDEO_MXS - setup_lcd(); -#endif - - return 0; -} - -static bool is_reva(void) -{ - return (nxp_board_rev() == 1); -} - -int board_late_init(void) -{ -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - if (is_reva()) - env_set("board_rev", "REVA"); -#endif - return 0; -} - -int checkboard(void) -{ -#ifdef CONFIG_NXP_BOARD_REVISION - printf("Board: MX6SX SABRE SDB rev%c\n", nxp_board_rev_string()); -#else - puts("Board: MX6SX SABRE SDB"); -#endif - return 0; -} diff --git a/board/freescale/mx6ul_14x14_evk/Kconfig b/board/freescale/mx6ul_14x14_evk/Kconfig deleted file mode 100644 index 8210cd3cb88..00000000000 --- a/board/freescale/mx6ul_14x14_evk/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MX6UL_14X14_EVK || TARGET_MX6UL_9X9_EVK - -config SYS_BOARD - default "mx6ul_14x14_evk" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "mx6ul_14x14_evk" - -endif diff --git a/board/freescale/mx6ul_14x14_evk/MAINTAINERS b/board/freescale/mx6ul_14x14_evk/MAINTAINERS deleted file mode 100644 index 7c7a196d22c..00000000000 --- a/board/freescale/mx6ul_14x14_evk/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MX6ULEVK BOARD -M: Peng Fan -S: Maintained -F: board/freescale/mx6ul_14x14_evk/ -F: include/configs/mx6ul_14x14_evk.h -F: configs/mx6ul_14x14_evk_defconfig -F: configs/mx6ul_9x9_evk_defconfig diff --git a/board/freescale/mx6ul_14x14_evk/Makefile b/board/freescale/mx6ul_14x14_evk/Makefile deleted file mode 100644 index 272ada720e1..00000000000 --- a/board/freescale/mx6ul_14x14_evk/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# (C) Copyright 2015 Freescale Semiconductor, Inc. - -obj-y := mx6ul_14x14_evk.o diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c deleted file mode 100644 index fbb5a12212d..00000000000 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ /dev/null @@ -1,471 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/pfuze.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) - -#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) - -#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) - -#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#ifdef CONFIG_DM_PMIC -int power_init_board(void) -{ - struct udevice *dev; - int ret, dev_id, rev_id; - unsigned int reg; - - ret = pmic_get("pfuze3000", &dev); - if (ret == -ENODEV) - return 0; - if (ret != 0) - return ret; - - dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); - rev_id = pmic_reg_read(dev, PFUZE3000_REVID); - printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); - - /* disable Low Power Mode during standby mode */ - reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); - reg |= 0x1; - pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); - - /* SW1B step ramp up time from 2us to 4us/25mV */ - pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40); - - /* SW1B mode to APS/PFM */ - pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc); - - /* SW1B standby voltage set to 0.975V */ - pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb); - - return 0; -} -#endif - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -#ifdef CONFIG_FSL_QSPI -static int board_qspi_init(void) -{ - /* Set the clock */ - enable_qspi_clk(0); - - return 0; -} -#endif - -#ifdef CONFIG_XPL_BUILD - -#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC2_BASE_ADDR, 0, 4}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - return 1; -} - -int board_mmc_init(struct bd_info *bis) -{ - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} -#endif - -#ifdef CONFIG_FEC_MXC -static int setup_fec(int fec_id) -{ - struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - int ret; - - if (fec_id == 0) { - /* - * Use 50M anatop loopback REF_CLK1 for ENET1, - * clear gpr1[13], set gpr1[17]. - */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, - IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); - } else { - /* - * Use 50M anatop loopback REF_CLK2 for ENET2, - * clear gpr1[14], set gpr1[18]. - */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, - IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); - } - - ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); - if (ret) - return ret; - - enable_enet_clk(1); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} -#endif - -#ifdef CONFIG_VIDEO -static iomux_v3_cfg_t const lcd_pads[] = { - /* Use GPIO for Brightness adjustment, duty cycle = period. */ - MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static int setup_lcd(void) -{ - enable_lcdif_clock(LCDIF1_BASE_ADDR, 1); - - imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); - - /* Reset the LCD */ - gpio_request(IMX_GPIO_NR(5, 9), "lcd reset"); - gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); - udelay(500); - gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); - - /* Set Brightness to high */ - gpio_request(IMX_GPIO_NR(1, 8), "backlight"); - gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); - - return 0; -} -#else -static inline int setup_lcd(void) { return 0; } -#endif - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - return 0; -} - -int board_init(void) -{ - /* Address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - -#ifdef CONFIG_FEC_MXC - setup_fec(CFG_FEC_ENET_DEV); -#endif - -#ifdef CONFIG_FSL_QSPI - board_qspi_init(); -#endif - - return 0; -} - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ - {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, - {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, - {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - -int board_late_init(void) -{ -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - env_set("board_name", "EVK"); - - if (is_mx6ul_9x9_evk()) - env_set("board_rev", "9X9"); - else - env_set("board_rev", "14X14"); -#endif - - setup_lcd(); - - return 0; -} - -int checkboard(void) -{ - if (is_mx6ul_9x9_evk()) - puts("Board: MX6UL 9x9 EVK\n"); - else - puts("Board: MX6UL 14x14 EVK\n"); - - return 0; -} - -/* - * Backlight off and reset LCD before OS handover - */ -void board_preboot_os(void) -{ - gpio_set_value(IMX_GPIO_NR(1, 8), 0); - gpio_set_value(IMX_GPIO_NR(5, 9), 0); -} - -#ifdef CONFIG_XPL_BUILD -#include -#include -#include - -static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { - .grp_addds = 0x00000030, - .grp_ddrmode_ctl = 0x00020000, - .grp_b0ds = 0x00000030, - .grp_ctlds = 0x00000030, - .grp_b1ds = 0x00000030, - .grp_ddrpke = 0x00000000, - .grp_ddrmode = 0x00020000, -#ifdef CONFIG_TARGET_MX6UL_9X9_EVK - .grp_ddr_type = 0x00080000, -#else - .grp_ddr_type = 0x000c0000, -#endif -}; - -#ifdef CONFIG_TARGET_MX6UL_9X9_EVK -static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { - .dram_dqm0 = 0x00000030, - .dram_dqm1 = 0x00000030, - .dram_ras = 0x00000030, - .dram_cas = 0x00000030, - .dram_odt0 = 0x00000000, - .dram_odt1 = 0x00000000, - .dram_sdba2 = 0x00000000, - .dram_sdclk_0 = 0x00000030, - .dram_sdqs0 = 0x00003030, - .dram_sdqs1 = 0x00003030, - .dram_reset = 0x00000030, -}; - -static struct mx6_mmdc_calibration mx6_mmcd_calib = { - .p0_mpwldectrl0 = 0x00000000, - .p0_mpdgctrl0 = 0x20000000, - .p0_mprddlctl = 0x4040484f, - .p0_mpwrdlctl = 0x40405247, - .mpzqlp2ctl = 0x1b4700c7, -}; - -static struct mx6_lpddr2_cfg mem_ddr = { - .mem_speed = 800, - .density = 2, - .width = 16, - .banks = 4, - .rowaddr = 14, - .coladdr = 10, - .trcd_lp = 1500, - .trppb_lp = 1500, - .trpab_lp = 2000, - .trasmin = 4250, -}; - -struct mx6_ddr_sysinfo ddr_sysinfo = { - .dsize = 0, - .cs_density = 18, - .ncs = 1, - .cs1_mirror = 0, - .walat = 0, - .ralat = 5, - .mif3_mode = 3, - .bi_on = 1, - .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */ - .rtt_nom = 0, - .sde_to_rst = 0, /* LPDDR2 does not need this field */ - .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ - .ddr_type = DDR_TYPE_LPDDR2, - .refsel = 0, /* Refresh cycles at 64KHz */ - .refr = 3, /* 4 refresh commands per refresh cycle */ -}; - -#else -static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { - .dram_dqm0 = 0x00000030, - .dram_dqm1 = 0x00000030, - .dram_ras = 0x00000030, - .dram_cas = 0x00000030, - .dram_odt0 = 0x00000030, - .dram_odt1 = 0x00000030, - .dram_sdba2 = 0x00000000, - .dram_sdclk_0 = 0x00000030, - .dram_sdqs0 = 0x00000030, - .dram_sdqs1 = 0x00000030, - .dram_reset = 0x00000030, -}; - -static struct mx6_mmdc_calibration mx6_mmcd_calib = { - .p0_mpwldectrl0 = 0x00000000, - .p0_mpdgctrl0 = 0x41570155, - .p0_mprddlctl = 0x4040474A, - .p0_mpwrdlctl = 0x40405550, -}; - -struct mx6_ddr_sysinfo ddr_sysinfo = { - .dsize = 0, - .cs_density = 20, - .ncs = 1, - .cs1_mirror = 0, - .rtt_wr = 2, - .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ - .walat = 0, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .ddr_type = DDR_TYPE_DDR3, - .refsel = 0, /* Refresh cycles at 64KHz */ - .refr = 1, /* 2 refresh commands per refresh cycle */ -}; - -static struct mx6_ddr3_cfg mem_ddr = { - .mem_speed = 800, - .density = 4, - .width = 16, - .banks = 8, - .rowaddr = 15, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; -#endif - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0xFFFFFFFF, &ccm->CCGR0); - writel(0xFFFFFFFF, &ccm->CCGR1); - writel(0xFFFFFFFF, &ccm->CCGR2); - writel(0xFFFFFFFF, &ccm->CCGR3); - writel(0xFFFFFFFF, &ccm->CCGR4); - writel(0xFFFFFFFF, &ccm->CCGR5); - writel(0xFFFFFFFF, &ccm->CCGR6); - writel(0xFFFFFFFF, &ccm->CCGR7); -} - -static void spl_dram_init(void) -{ - mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); -} - -void board_init_f(ulong dummy) -{ - ccgr_init(); - - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - /* iomux and setup of i2c */ - board_early_init_f(); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* DDR initialization */ - spl_dram_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); -} -#endif diff --git a/board/freescale/mx6ullevk/Kconfig b/board/freescale/mx6ullevk/Kconfig deleted file mode 100644 index 49aa302553e..00000000000 --- a/board/freescale/mx6ullevk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX6ULL_14X14_EVK - -config SYS_BOARD - default "mx6ullevk" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "mx6ullevk" - -config IMX_CONFIG - default "board/freescale/mx6ullevk/imximage.cfg" - -endif diff --git a/board/freescale/mx6ullevk/MAINTAINERS b/board/freescale/mx6ullevk/MAINTAINERS deleted file mode 100644 index 3d1b2560363..00000000000 --- a/board/freescale/mx6ullevk/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -MX6ULLEVK BOARD -M: Peng Fan -S: Maintained -F: board/freescale/mx6ullevk/ -F: include/configs/mx6ullevk.h -F: configs/mx6ull_14x14_evk_defconfig -F: configs/mx6ull_14x14_evk_plugin_defconfig -F: configs/mx6ulz_14x14_evk_defconfig diff --git a/board/freescale/mx6ullevk/Makefile b/board/freescale/mx6ullevk/Makefile deleted file mode 100644 index 1ff03b5f1cd..00000000000 --- a/board/freescale/mx6ullevk/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# (C) Copyright 2016 Freescale Semiconductor, Inc. - -obj-y := mx6ullevk.o diff --git a/board/freescale/mx6ullevk/imximage.cfg b/board/freescale/mx6ullevk/imximage.cfg deleted file mode 100644 index 0c6f444a7a3..00000000000 --- a/board/freescale/mx6ullevk/imximage.cfg +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -#include - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi/sd/nand/onenand, qspi/nor - */ - -#ifdef CONFIG_QSPI_BOOT -BOOT_FROM qspi -#elif defined(CONFIG_NOR_BOOT) -BOOT_FROM nor -#else -BOOT_FROM sd -#endif - -#ifdef CONFIG_USE_IMXIMG_PLUGIN -/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ -PLUGIN board/freescale/mx6ullevk/plugin.bin 0x00907000 -#else - -#ifdef CONFIG_IMX_HAB -CSF CONFIG_CSF_SIZE -#endif - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* Enable all clocks */ -DATA 4 0x020c4068 0xffffffff -DATA 4 0x020c406c 0xffffffff -DATA 4 0x020c4070 0xffffffff -DATA 4 0x020c4074 0xffffffff -DATA 4 0x020c4078 0xffffffff -DATA 4 0x020c407c 0xffffffff -DATA 4 0x020c4080 0xffffffff - -DATA 4 0x020E04B4 0x000C0000 -DATA 4 0x020E04AC 0x00000000 -DATA 4 0x020E027C 0x00000030 -DATA 4 0x020E0250 0x00000030 -DATA 4 0x020E024C 0x00000030 -DATA 4 0x020E0490 0x00000030 -DATA 4 0x020E0288 0x000C0030 -DATA 4 0x020E0270 0x00000000 -DATA 4 0x020E0260 0x00000030 -DATA 4 0x020E0264 0x00000030 -DATA 4 0x020E04A0 0x00000030 -DATA 4 0x020E0494 0x00020000 -DATA 4 0x020E0280 0x00000030 -DATA 4 0x020E0284 0x00000030 -DATA 4 0x020E04B0 0x00020000 -DATA 4 0x020E0498 0x00000030 -DATA 4 0x020E04A4 0x00000030 -DATA 4 0x020E0244 0x00000030 -DATA 4 0x020E0248 0x00000030 -DATA 4 0x021B001C 0x00008000 -DATA 4 0x021B0800 0xA1390003 -DATA 4 0x021B080C 0x00000004 -DATA 4 0x021B083C 0x41640158 -DATA 4 0x021B0848 0x40403237 -DATA 4 0x021B0850 0x40403C33 -DATA 4 0x021B081C 0x33333333 -DATA 4 0x021B0820 0x33333333 -DATA 4 0x021B082C 0xf3333333 -DATA 4 0x021B0830 0xf3333333 -DATA 4 0x021B08C0 0x00944009 -DATA 4 0x021B08b8 0x00000800 -DATA 4 0x021B0004 0x0002002D -DATA 4 0x021B0008 0x1B333030 -DATA 4 0x021B000C 0x676B52F3 -DATA 4 0x021B0010 0xB66D0B63 -DATA 4 0x021B0014 0x01FF00DB -DATA 4 0x021B0018 0x00201740 -DATA 4 0x021B001C 0x00008000 -DATA 4 0x021B002C 0x000026D2 -DATA 4 0x021B0030 0x006B1023 -DATA 4 0x021B0040 0x0000004F -DATA 4 0x021B0000 0x84180000 -DATA 4 0x021B0890 0x00400000 -DATA 4 0x021B001C 0x02008032 -DATA 4 0x021B001C 0x00008033 -DATA 4 0x021B001C 0x00048031 -DATA 4 0x021B001C 0x15208030 -DATA 4 0x021B001C 0x04008040 -DATA 4 0x021B0020 0x00000800 -DATA 4 0x021B0818 0x00000227 -DATA 4 0x021B0004 0x0002552D -DATA 4 0x021B0404 0x00011006 -DATA 4 0x021B001C 0x00000000 - -#endif diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c deleted file mode 100644 index 189eddefea3..00000000000 --- a/board/freescale/mx6ullevk/mx6ullevk.c +++ /dev/null @@ -1,138 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -int board_mmc_get_env_dev(int devno) -{ - return devno; -} - -int mmc_map_to_kernel_blk(int devno) -{ - return devno; -} - -int board_early_init_f(void) -{ - return 0; -} - -#ifdef CONFIG_FEC_MXC -static int setup_fec(int fec_id) -{ - struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - int ret; - - if (fec_id == 0) { - /* - * Use 50MHz anatop loopback REF_CLK1 for ENET1, - * clear gpr1[13], set gpr1[17]. - */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, - IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); - } else { - /* - * Use 50MHz anatop loopback REF_CLK2 for ENET2, - * clear gpr1[14], set gpr1[18]. - */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, - IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); - } - - ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); - if (ret) - return ret; - - enable_enet_clk(1); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} -#endif - -int board_init(void) -{ - /* Address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - -#ifdef CONFIG_FEC_MXC - setup_fec(CFG_FEC_ENET_DEV); -#endif - - return 0; -} - -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ - {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, - {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, - {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - -int board_late_init(void) -{ -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - if (is_cpu_type(MXC_CPU_MX6ULZ)) - env_set("board_name", "ULZ-EVK"); - else - env_set("board_name", "EVK"); - env_set("board_rev", "14X14"); -#endif - - return 0; -} - -int checkboard(void) -{ - if (is_cpu_type(MXC_CPU_MX6ULZ)) - puts("Board: MX6ULZ 14x14 EVK\n"); - else - puts("Board: MX6ULL 14x14 EVK\n"); - - return 0; -} diff --git a/board/freescale/mx6ullevk/plugin.S b/board/freescale/mx6ullevk/plugin.S deleted file mode 100644 index 1f631ff5e3e..00000000000 --- a/board/freescale/mx6ullevk/plugin.S +++ /dev/null @@ -1,138 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#include - -/* DDR script */ -.macro imx6ull_ddr3_evk_setting - ldr r0, =IOMUXC_BASE_ADDR - ldr r1, =0x000C0000 - str r1, [r0, #0x4B4] - ldr r1, =0x00000000 - str r1, [r0, #0x4AC] - ldr r1, =0x00000030 - str r1, [r0, #0x27C] - ldr r1, =0x00000030 - str r1, [r0, #0x250] - str r1, [r0, #0x24C] - str r1, [r0, #0x490] - ldr r1, =0x000C0030 - str r1, [r0, #0x288] - - ldr r1, =0x00000000 - str r1, [r0, #0x270] - - ldr r1, =0x00000030 - str r1, [r0, #0x260] - str r1, [r0, #0x264] - str r1, [r0, #0x4A0] - - ldr r1, =0x00020000 - str r1, [r0, #0x494] - - ldr r1, =0x00000030 - str r1, [r0, #0x280] - ldr r1, =0x00000030 - str r1, [r0, #0x284] - - ldr r1, =0x00020000 - str r1, [r0, #0x4B0] - - ldr r1, =0x00000030 - str r1, [r0, #0x498] - str r1, [r0, #0x4A4] - str r1, [r0, #0x244] - str r1, [r0, #0x248] - - ldr r0, =MMDC_P0_BASE_ADDR - ldr r1, =0x00008000 - str r1, [r0, #0x1C] - ldr r1, =0xA1390003 - str r1, [r0, #0x800] - ldr r1, =0x00000004 - str r1, [r0, #0x80C] - ldr r1, =0x41640158 - str r1, [r0, #0x83C] - ldr r1, =0x40403237 - str r1, [r0, #0x848] - ldr r1, =0x40403C33 - str r1, [r0, #0x850] - ldr r1, =0x33333333 - str r1, [r0, #0x81C] - str r1, [r0, #0x820] - ldr r1, =0xF3333333 - str r1, [r0, #0x82C] - str r1, [r0, #0x830] - ldr r1, =0x00944009 - str r1, [r0, #0x8C0] - ldr r1, =0x00000800 - str r1, [r0, #0x8B8] - ldr r1, =0x0002002D - str r1, [r0, #0x004] - ldr r1, =0x1B333030 - str r1, [r0, #0x008] - ldr r1, =0x676B52F3 - str r1, [r0, #0x00C] - ldr r1, =0xB66D0B63 - str r1, [r0, #0x010] - ldr r1, =0x01FF00DB - str r1, [r0, #0x014] - ldr r1, =0x00201740 - str r1, [r0, #0x018] - ldr r1, =0x00008000 - str r1, [r0, #0x01C] - ldr r1, =0x000026D2 - str r1, [r0, #0x02C] - ldr r1, =0x006B1023 - str r1, [r0, #0x030] - ldr r1, =0x0000004F - str r1, [r0, #0x040] - ldr r1, =0x84180000 - str r1, [r0, #0x000] - ldr r1, =0x00400000 - str r1, [r0, #0x890] - ldr r1, =0x02008032 - str r1, [r0, #0x01C] - ldr r1, =0x00008033 - str r1, [r0, #0x01C] - ldr r1, =0x00048031 - str r1, [r0, #0x01C] - ldr r1, =0x15208030 - str r1, [r0, #0x01C] - ldr r1, =0x04008040 - str r1, [r0, #0x01C] - ldr r1, =0x00000800 - str r1, [r0, #0x020] - ldr r1, =0x00000227 - str r1, [r0, #0x818] - ldr r1, =0x0002552D - str r1, [r0, #0x004] - ldr r1, =0x00011006 - str r1, [r0, #0x404] - ldr r1, =0x00000000 - str r1, [r0, #0x01C] -.endm - -.macro imx6_clock_gating - ldr r0, =CCM_BASE_ADDR - ldr r1, =0xFFFFFFFF - str r1, [r0, #0x68] - str r1, [r0, #0x6C] - str r1, [r0, #0x70] - str r1, [r0, #0x74] - str r1, [r0, #0x78] - str r1, [r0, #0x7C] - str r1, [r0, #0x80] -.endm - -.macro imx6_qos_setting -.endm - -.macro imx6_ddr_setting - imx6ull_ddr3_evk_setting -.endm - -/* include the common plugin code here */ -#include diff --git a/board/freescale/mx7dsabresd/Kconfig b/board/freescale/mx7dsabresd/Kconfig deleted file mode 100644 index bf3ceafe2b4..00000000000 --- a/board/freescale/mx7dsabresd/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX7DSABRESD - -config SYS_BOARD - default "mx7dsabresd" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "mx7dsabresd" - -config IMX_CONFIG - default "board/freescale/mx7dsabresd/imximage.cfg" - -endif diff --git a/board/freescale/mx7dsabresd/MAINTAINERS b/board/freescale/mx7dsabresd/MAINTAINERS deleted file mode 100644 index 721321c9cca..00000000000 --- a/board/freescale/mx7dsabresd/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -MX7DSABRESD BOARD -M: Adrian Alonso -M: Fabio Estevam -S: Maintained -F: board/freescale/mx7dsabresd -F: include/configs/mx7dsabresd.h -F: configs/mx7dsabresd_defconfig -F: configs/mx7dsabresd_qspi_defconfig diff --git a/board/freescale/mx7dsabresd/Makefile b/board/freescale/mx7dsabresd/Makefile deleted file mode 100644 index 852b3d87ad5..00000000000 --- a/board/freescale/mx7dsabresd/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# (C) Copyright 2015 Freescale Semiconductor, Inc. - -obj-y := mx7dsabresd.o diff --git a/board/freescale/mx7dsabresd/imximage.cfg b/board/freescale/mx7dsabresd/imximage.cfg deleted file mode 100644 index 59e66fbda16..00000000000 --- a/board/freescale/mx7dsabresd/imximage.cfg +++ /dev/null @@ -1,99 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -#include - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : sd - */ - -BOOT_FROM sd - -/* - * Secure boot support - */ -#ifdef CONFIG_IMX_HAB -CSF CONFIG_CSF_SIZE -#endif - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -DATA 4 0x30340004 0x4F400005 - -DATA 4 0x30391000 0x00000002 -DATA 4 0x307a0000 0x01040001 -DATA 4 0x307a01a0 0x80400003 -DATA 4 0x307a01a4 0x00100020 -DATA 4 0x307a01a8 0x80100004 -DATA 4 0x307a0064 0x00400046 -DATA 4 0x307a0490 0x00000001 -DATA 4 0x307a00d0 0x00020083 -DATA 4 0x307a00d4 0x00690000 -DATA 4 0x307a00dc 0x09300004 -DATA 4 0x307a00e0 0x04080000 -DATA 4 0x307a00e4 0x00100004 -DATA 4 0x307a00f4 0x0000033f -DATA 4 0x307a0100 0x09081109 -DATA 4 0x307a0104 0x0007020d -DATA 4 0x307a0108 0x03040407 -DATA 4 0x307a010c 0x00002006 -DATA 4 0x307a0110 0x04020205 -DATA 4 0x307a0114 0x03030202 -DATA 4 0x307a0120 0x00000803 -DATA 4 0x307a0180 0x00800020 -DATA 4 0x307a0184 0x02000100 -DATA 4 0x307a0190 0x02098204 -DATA 4 0x307a0194 0x00030303 -DATA 4 0x307a0200 0x00000016 -DATA 4 0x307a0204 0x00171717 -DATA 4 0x307a0214 0x04040404 -DATA 4 0x307a0218 0x0f040404 -DATA 4 0x307a0240 0x06000604 -DATA 4 0x307a0244 0x00000001 -DATA 4 0x30391000 0x00000000 -DATA 4 0x30790000 0x17420f40 -DATA 4 0x30790004 0x10210100 -DATA 4 0x30790010 0x00060807 -DATA 4 0x307900b0 0x1010007e -DATA 4 0x3079009c 0x00000d6e -DATA 4 0x30790020 0x08080808 -DATA 4 0x30790030 0x08080808 -DATA 4 0x30790050 0x01000010 -DATA 4 0x30790050 0x00000010 - -DATA 4 0x307900c0 0x0e407304 -DATA 4 0x307900c0 0x0e447304 -DATA 4 0x307900c0 0x0e447306 - -CHECK_BITS_SET 4 0x307900c4 0x1 - -DATA 4 0x307900c0 0x0e447304 -DATA 4 0x307900c0 0x0e407304 - -DATA 4 0x30384130 0x00000000 -DATA 4 0x30340020 0x00000178 -DATA 4 0x30384130 0x00000002 -DATA 4 0x30790018 0x0000000f - -CHECK_BITS_SET 4 0x307a0004 0x1 diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c deleted file mode 100644 index bef4f901ff7..00000000000 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ /dev/null @@ -1,327 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/pfuze.h" -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ - PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) - -#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ - PAD_CTL_DSE_3P3V_49OHM) - -#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) - -#define SPI_PAD_CTRL \ - (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST) - -#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) - -#ifdef CONFIG_MXC_SPI -static iomux_v3_cfg_t const ecspi3_pads[] = { - MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1; -} - -static void setup_spi(void) -{ - imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads)); -} -#endif - -int dram_init(void) -{ - gd->ram_size = PHYS_SDRAM_SIZE; - - return 0; -} - -static iomux_v3_cfg_t const wdog_pads[] = { - MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const uart1_pads[] = { - MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -#ifdef CONFIG_NAND_MXS -static iomux_v3_cfg_t const gpmi_pads[] = { - MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), -}; - -static void setup_gpmi_nand(void) -{ - imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); - - /* NAND_USDHC_BUS_CLK is set in rom */ - set_clk_nand(); -} -#endif - -#ifdef CONFIG_VIDEO_MXS -static iomux_v3_cfg_t const lcd_pads[] = { - MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), - - MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL), -}; - -static iomux_v3_cfg_t const pwm_pads[] = { - /* Use GPIO for Brightness adjustment, duty cycle = period */ - MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static int setup_lcd(void) -{ - imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); - - imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); - - /* Reset LCD */ - gpio_request(IMX_GPIO_NR(3, 4), "lcd reset"); - gpio_direction_output(IMX_GPIO_NR(3, 4) , 0); - udelay(500); - gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); - - /* Set Brightness to high */ - gpio_request(IMX_GPIO_NR(1, 1), "lcd backlight"); - gpio_direction_output(IMX_GPIO_NR(1, 1) , 1); - - return 0; -} -#endif - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -int board_mmc_get_env_dev(int devno) -{ - if (devno == 2) - devno--; - - return devno; -} - -int mmc_map_to_kernel_blk(int dev_no) -{ - if (dev_no == 1) - dev_no++; - - return dev_no; -} - -#ifdef CONFIG_FEC_MXC -static int setup_fec(void) -{ - struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs - = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; - - /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ - clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], - (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | - IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); - - return set_clk_enet(ENET_125MHZ); -} - -int board_phy_config(struct phy_device *phydev) -{ - /* enable rgmii rxc skew and phy mode select to RGMII copper */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7); - - if (phydev->drv->config) - phydev->drv->config(phydev); - return 0; -} -#endif - -#ifdef CONFIG_FSL_QSPI -int board_qspi_init(void) -{ - /* Set the clock */ - set_clk_qspi(); - - return 0; -} -#endif - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - -#ifdef CONFIG_FEC_MXC - setup_fec(); -#endif - -#ifdef CONFIG_NAND_MXS - setup_gpmi_nand(); -#endif - -#ifdef CONFIG_VIDEO_MXS - setup_lcd(); -#endif - -#ifdef CONFIG_FSL_QSPI - board_qspi_init(); -#endif - -#ifdef CONFIG_MXC_SPI - setup_spi(); -#endif - - return 0; -} - -#ifdef CONFIG_DM_PMIC -int power_init_board(void) -{ - struct udevice *dev; - int ret, dev_id, rev_id; - - ret = pmic_get("pmic@8", &dev); - if (ret == -ENODEV) - return 0; - if (ret != 0) - return ret; - - dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); - rev_id = pmic_reg_read(dev, PFUZE3000_REVID); - printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); - - pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); - - /* - * Set the voltage of VLDO4 output to 2.8V which feeds - * the MIPI DSI and MIPI CSI inputs. - */ - pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA); - - return 0; -} -#endif - -int board_late_init(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; - unsigned char eth1addr[6]; - - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - - set_wdog_reset(wdog); - - /* - * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), - * since we use PMIC_PWRON to reset the board. - */ - clrsetbits_le16(&wdog->wcr, 0, 0x10); - - /* Get the second MAC address */ - imx_get_mac_from_fuse(1, eth1addr); - if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr)) - eth_env_set_enetaddr("eth1addr", eth1addr); - - return 0; -} - -int checkboard(void) -{ - char *mode; - - if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT)) - mode = "secure"; - else - mode = "non-secure"; - - printf("Board: i.MX7D SABRESD in %s mode\n", mode); - - return 0; -} diff --git a/board/freescale/mx7ulp_evk/Kconfig b/board/freescale/mx7ulp_evk/Kconfig deleted file mode 100644 index 591697041dd..00000000000 --- a/board/freescale/mx7ulp_evk/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX7ULP_EVK - -config SYS_BOARD - default "mx7ulp_evk" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "mx7ulp_evk" - -config IMX_CONFIG - default "board/freescale/mx7ulp_evk/imximage.cfg" - -endif diff --git a/board/freescale/mx7ulp_evk/MAINTAINERS b/board/freescale/mx7ulp_evk/MAINTAINERS deleted file mode 100644 index 1aa26445632..00000000000 --- a/board/freescale/mx7ulp_evk/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MX7ULPEVK BOARD -M: Peng Fan -S: Maintained -F: board/freescale/mx7ulp_evk/ -F: include/configs/mx7ulp_evk.h -F: configs/mx7ulp_evk_defconfig -F: configs/mx7ulp_evk_plugin_defconfig diff --git a/board/freescale/mx7ulp_evk/Makefile b/board/freescale/mx7ulp_evk/Makefile deleted file mode 100644 index 9f33c61f03b..00000000000 --- a/board/freescale/mx7ulp_evk/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# (C) Copyright 2016 Freescale Semiconductor, Inc. - -obj-y := mx7ulp_evk.o diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg deleted file mode 100644 index 62fd79afd6c..00000000000 --- a/board/freescale/mx7ulp_evk/imximage.cfg +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * - * Refer docs/README.imxmage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -#include - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi/sd/nand/onenand, qspi/nor - */ - -BOOT_FROM sd - -#ifdef CONFIG_USE_IMXIMG_PLUGIN -/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ -PLUGIN board/freescale/mx7ulp_evk/plugin.bin 0x2F020000 -#else - -#ifdef CONFIG_IMX_HAB -CSF CONFIG_CSF_SIZE -#endif -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -DATA 4 0x403f00dc 0x00000000 -DATA 4 0x403e0040 0x01000020 -DATA 4 0x403e0500 0x01000000 -DATA 4 0x403e050c 0x80808080 -DATA 4 0x403e0508 0x00160002 -DATA 4 0x403E0510 0x00000001 -DATA 4 0x403E0514 0x00000014 -DATA 4 0x403e0500 0x00000001 -CHECK_BITS_SET 4 0x403e0500 0x01000000 -DATA 4 0x403e050c 0x8080801B -CHECK_BITS_SET 4 0x403e050c 0x00000040 -DATA 4 0x403E0030 0x00000001 -DATA 4 0x403e0040 0x11000020 -DATA 4 0x403f00dc 0x42000000 - -DATA 4 0x40B300AC 0x40000000 - -DATA 4 0x40AD0128 0x00040000 -DATA 4 0x40AD00F8 0x00000000 -DATA 4 0x40AD00D8 0x00000180 -DATA 4 0x40AD0108 0x00000180 -DATA 4 0x40AD0104 0x00000180 -DATA 4 0x40AD0124 0x00010000 -DATA 4 0x40AD0080 0x0000018C -DATA 4 0x40AD0084 0x0000018C -DATA 4 0x40AD0088 0x0000018C -DATA 4 0x40AD008C 0x0000018C - -DATA 4 0x40AD0120 0x00010000 -DATA 4 0x40AD010C 0x00000180 -DATA 4 0x40AD0110 0x00000180 -DATA 4 0x40AD0114 0x00000180 -DATA 4 0x40AD0118 0x00000180 -DATA 4 0x40AD0090 0x00000180 -DATA 4 0x40AD0094 0x00000180 -DATA 4 0x40AD0098 0x00000180 -DATA 4 0x40AD009C 0x00000180 - -DATA 4 0x40AD00E0 0x00040000 -DATA 4 0x40AD00E4 0x00040000 - -DATA 4 0x40AB001C 0x00008000 -DATA 4 0x40AB0800 0xA1390003 -DATA 4 0x40AB085C 0x0D3900A0 -DATA 4 0x40AB0890 0x00400000 - -DATA 4 0x40AB0848 0x40404040 -DATA 4 0x40AB0850 0x40404040 -DATA 4 0x40AB081C 0x33333333 -DATA 4 0x40AB0820 0x33333333 -DATA 4 0x40AB0824 0x33333333 -DATA 4 0x40AB0828 0x33333333 - -DATA 4 0x40AB08C0 0x24922492 -DATA 4 0x40AB08B8 0x00000800 - -DATA 4 0x40AB0004 0x00020052 -DATA 4 0x40AB000C 0x292C42F3 -DATA 4 0x40AB0010 0x00100A22 -DATA 4 0x40AB0038 0x00120556 -DATA 4 0x40AB0014 0x00C700DB -DATA 4 0x40AB0018 0x00211718 -DATA 4 0x40AB002C 0x0F9F26D2 -DATA 4 0x40AB0030 0x009F0E10 -DATA 4 0x40AB0040 0x0000003F -DATA 4 0x40AB0000 0xC3190000 - -DATA 4 0x40AB001C 0x00008010 -DATA 4 0x40AB001C 0x00008018 -DATA 4 0x40AB001C 0x003F8030 -DATA 4 0x40AB001C 0x003F8038 -DATA 4 0x40AB001C 0xFF0A8030 -DATA 4 0x40AB001C 0xFF0A8038 -DATA 4 0x40AB001C 0x04028030 -DATA 4 0x40AB001C 0x04028038 -DATA 4 0x40AB001C 0x83018030 -DATA 4 0x40AB001C 0x83018038 -DATA 4 0x40AB001C 0x01038030 -DATA 4 0x40AB001C 0x01038038 - -DATA 4 0x40AB083C 0x20000000 - -DATA 4 0x40AB0020 0x00001800 -DATA 4 0x40AB0800 0xA1310000 -DATA 4 0x40AB0004 0x00020052 -DATA 4 0x40AB0404 0x00011006 -DATA 4 0x40AB001C 0x00000000 -#endif diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c deleted file mode 100644 index af68e57854e..00000000000 --- a/board/freescale/mx7ulp_evk/mx7ulp_evk.c +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_UP) - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; -} - -static iomux_cfg_t const lpuart4_pads[] = { - MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static void setup_iomux_uart(void) -{ - mx7ulp_iomux_setup_multiple_pads(lpuart4_pads, - ARRAY_SIZE(lpuart4_pads)); -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - const char *path; - int rc, nodeoff; - - if (get_boot_device() == USB_BOOT) { - path = fdt_get_alias(blob, "mmc0"); - if (!path) { - puts("Not found mmc0\n"); - return 0; - } - - nodeoff = fdt_path_offset(blob, path); - if (nodeoff < 0) - return 0; - - printf("Found usdhc0 node\n"); - if (fdt_get_property(blob, nodeoff, "vqmmc-supply", - NULL) != NULL) { - rc = fdt_delprop(blob, nodeoff, "vqmmc-supply"); - if (!rc) { - puts("Removed vqmmc-supply property\n"); -add: - rc = fdt_setprop(blob, nodeoff, - "no-1-8-v", NULL, 0); - if (rc == -FDT_ERR_NOSPACE) { - rc = fdt_increase_size(blob, 32); - if (!rc) - goto add; - } else if (rc) { - printf("Failed to add no-1-8-v property, %d\n", rc); - } else { - puts("Added no-1-8-v property\n"); - } - } else { - printf("Failed to remove vqmmc-supply property, %d\n", rc); - } - } - } - - return 0; -} -#endif diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S deleted file mode 100644 index 2cc93dbdd57..00000000000 --- a/board/freescale/mx7ulp_evk/plugin.S +++ /dev/null @@ -1,216 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2019 NXP - */ - -#include - -.macro imx7ulp_ddr_freq_decrease - ldr r2, =0x403f0000 - ldr r3, =0x00000000 - str r3, [r2, #0xdc] - - ldr r2, =0x403e0000 - ldr r3, =0x01000020 - str r3, [r2, #0x40] - ldr r3, =0x01000000 - str r3, [r2, #0x500] - - ldr r3, =0x80808080 - str r3, [r2, #0x50c] - ldr r3, =0x00160002 - str r3, [r2, #0x508] - ldr r3, =0x00000001 - str r3, [r2, #0x510] - ldr r3, =0x00000014 - str r3, [r2, #0x514] - ldr r3, =0x00000001 - str r3, [r2, #0x500] - - ldr r3, =0x01000000 -wait1: - ldr r4, [r2, #0x500] - and r4, r3 - cmp r4, r3 - bne wait1 - - ldr r3, =0x8080801B - str r3, [r2, #0x50c] - - ldr r3, =0x00000040 -wait2: - ldr r4, [r2, #0x50c] - and r4, r3 - cmp r4, r3 - bne wait2 - - ldr r3, =0x00000001 - str r3, [r2, #0x30] - ldr r3, =0x11000020 - str r3, [r2, #0x40] - - ldr r2, =0x403f0000 - ldr r3, =0x42000000 - str r3, [r2, #0xdc] - -.endm - -.macro imx7ulp_evk_ddr_setting - - imx7ulp_ddr_freq_decrease - - /* Enable MMDC PCC clock */ - ldr r2, =0x40b30000 - ldr r3, =0x40000000 - str r3, [r2, #0xac] - - /* Configure DDR pad */ - ldr r0, =0x40ad0000 - ldr r1, =0x00040000 - str r1, [r0, #0x128] - ldr r1, =0x0 - str r1, [r0, #0xf8] - ldr r1, =0x00000180 - str r1, [r0, #0xd8] - ldr r1, =0x00000180 - str r1, [r0, #0x108] - ldr r1, =0x00000180 - str r1, [r0, #0x104] - ldr r1, =0x00010000 - str r1, [r0, #0x124] - ldr r1, =0x0000018C - str r1, [r0, #0x80] - ldr r1, =0x0000018C - str r1, [r0, #0x84] - ldr r1, =0x0000018C - str r1, [r0, #0x88] - ldr r1, =0x0000018C - str r1, [r0, #0x8c] - - ldr r1, =0x00010000 - str r1, [r0, #0x120] - ldr r1, =0x00000180 - str r1, [r0, #0x10c] - ldr r1, =0x00000180 - str r1, [r0, #0x110] - ldr r1, =0x00000180 - str r1, [r0, #0x114] - ldr r1, =0x00000180 - str r1, [r0, #0x118] - ldr r1, =0x00000180 - str r1, [r0, #0x90] - ldr r1, =0x00000180 - str r1, [r0, #0x94] - ldr r1, =0x00000180 - str r1, [r0, #0x98] - ldr r1, =0x00000180 - str r1, [r0, #0x9c] - ldr r1, =0x00040000 - str r1, [r0, #0xe0] - ldr r1, =0x00040000 - str r1, [r0, #0xe4] - - ldr r0, =0x40ab0000 - ldr r1, =0x00008000 - str r1, [r0, #0x1c] - ldr r1, =0xA1390003 - str r1, [r0, #0x800] - ldr r1, =0x0D3900A0 - str r1, [r0, #0x85c] - ldr r1, =0x00400000 - str r1, [r0, #0x890] - - ldr r1, =0x40404040 - str r1, [r0, #0x848] - ldr r1, =0x40404040 - str r1, [r0, #0x850] - ldr r1, =0x33333333 - str r1, [r0, #0x81c] - ldr r1, =0x33333333 - str r1, [r0, #0x820] - ldr r1, =0x33333333 - str r1, [r0, #0x824] - ldr r1, =0x33333333 - str r1, [r0, #0x828] - - ldr r1, =0x24922492 - str r1, [r0, #0x8c0] - ldr r1, =0x00000800 - str r1, [r0, #0x8b8] - - ldr r1, =0x00020052 - str r1, [r0, #0x4] - ldr r1, =0x292C42F3 - str r1, [r0, #0xc] - ldr r1, =0x00100A22 - str r1, [r0, #0x10] - ldr r1, =0x00120556 - str r1, [r0, #0x38] - ldr r1, =0x00C700DB - str r1, [r0, #0x14] - ldr r1, =0x00211718 - str r1, [r0, #0x18] - - ldr r1, =0x0F9F26D2 - str r1, [r0, #0x2c] - ldr r1, =0x009F0E10 - str r1, [r0, #0x30] - ldr r1, =0x0000003F - str r1, [r0, #0x40] - ldr r1, =0xC3190000 - str r1, [r0, #0x0] - - ldr r1, =0x00008010 - str r1, [r0, #0x1c] - ldr r1, =0x00008018 - str r1, [r0, #0x1c] - ldr r1, =0x003F8030 - str r1, [r0, #0x1c] - ldr r1, =0x003F8038 - str r1, [r0, #0x1c] - ldr r1, =0xFF0A8030 - str r1, [r0, #0x1c] - ldr r1, =0xFF0A8038 - str r1, [r0, #0x1c] - ldr r1, =0x04028030 - str r1, [r0, #0x1c] - ldr r1, =0x04028038 - str r1, [r0, #0x1c] - ldr r1, =0x83018030 - str r1, [r0, #0x1c] - ldr r1, =0x83018038 - str r1, [r0, #0x1c] - ldr r1, =0x01038030 - str r1, [r0, #0x1c] - ldr r1, =0x01038038 - str r1, [r0, #0x1c] - - ldr r1, =0x20000000 - str r1, [r0, #0x83c] - - ldr r1, =0x00001800 - str r1, [r0, #0x20] - ldr r1, =0xA1310000 - str r1, [r0, #0x800] - ldr r1, =0x00020052 - str r1, [r0, #0x4] - ldr r1, =0x00011006 - str r1, [r0, #0x404] - ldr r1, =0x00000000 - str r1, [r0, #0x1c] - -.endm - -.macro imx7ulp_clock_gating -.endm - -.macro imx7ulp_qos_setting -.endm - -.macro imx7ulp_ddr_setting - imx7ulp_evk_ddr_setting -.endm - -/* include the common plugin code here */ -#include diff --git a/board/freescale/p1010rdb/Kconfig b/board/freescale/p1010rdb/Kconfig deleted file mode 100644 index 159bcc4f54d..00000000000 --- a/board/freescale/p1010rdb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB - -config SYS_BOARD - default "p1010rdb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P1010RDB" - -endif diff --git a/board/freescale/p1010rdb/MAINTAINERS b/board/freescale/p1010rdb/MAINTAINERS deleted file mode 100644 index 6e940dd8759..00000000000 --- a/board/freescale/p1010rdb/MAINTAINERS +++ /dev/null @@ -1,21 +0,0 @@ -P1010RDB BOARD -M: Qiang Zhao -S: Maintained -F: board/freescale/p1010rdb/ -F: include/configs/P1010RDB.h -F: configs/P1010RDB-PA_36BIT_NAND_defconfig -F: configs/P1010RDB-PA_36BIT_NOR_defconfig -F: configs/P1010RDB-PA_36BIT_SDCARD_defconfig -F: configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig -F: configs/P1010RDB-PA_NAND_defconfig -F: configs/P1010RDB-PA_NOR_defconfig -F: configs/P1010RDB-PA_SDCARD_defconfig -F: configs/P1010RDB-PA_SPIFLASH_defconfig -F: configs/P1010RDB-PB_36BIT_NAND_defconfig -F: configs/P1010RDB-PB_36BIT_NOR_defconfig -F: configs/P1010RDB-PB_36BIT_SDCARD_defconfig -F: configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig -F: configs/P1010RDB-PB_NAND_defconfig -F: configs/P1010RDB-PB_NOR_defconfig -F: configs/P1010RDB-PB_SDCARD_defconfig -F: configs/P1010RDB-PB_SPIFLASH_defconfig diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile deleted file mode 100644 index df4e8001d38..00000000000 --- a/board/freescale/p1010rdb/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2010-2011 Freescale Semiconductor, Inc. - -MINIMAL= - -ifdef CONFIG_XPL_BUILD -ifndef CONFIG_TPL_BUILD -ifdef CONFIG_SPL_INIT_MINIMAL -MINIMAL=y -endif -endif -endif - -ifdef MINIMAL -obj-y += spl_minimal.o -else -ifdef CONFIG_XPL_BUILD -obj-y += spl.o -endif -obj-y += p1010rdb.o -obj-y += ddr.o -endif - -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/p1010rdb/README.P1010RDB-PA b/board/freescale/p1010rdb/README.P1010RDB-PA deleted file mode 100644 index 0cb950d845e..00000000000 --- a/board/freescale/p1010rdb/README.P1010RDB-PA +++ /dev/null @@ -1,207 +0,0 @@ -Overview -========= -The P1010RDB is a Freescale reference design board that hosts the P1010 SoC. - -The P1010 is a cost-effective, low-power, highly integrated host processor -based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz), -that addresses the requirements of several routing, gateways, storage, consumer, -and industrial applications. Applications of interest include the main CPUs and -I/O processors in network attached storage (NAS), the voice over IP (VoIP) -router/gateway, and wireless LAN (WLAN) and industrial controllers. - -The P1010RDB board features are as follows: -Memory subsystem: - - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) - - 32 Mbyte NOR flash single-chip memory - - 32 Mbyte NAND flash memory - - 256 Kbit M24256 I2C EEPROM - - 16 Mbyte SPI memory - - I2C Board EEPROM 128x8 bit memory - - SD/MMC connector to interface with the SD memory card -Interfaces: - - PCIe: - - Lane0: x1 mini-PCIe slot - - Lane1: x1 PCIe standard slot - - SATA: - - 1 internal SATA connector to 2.5” 160G SATA2 HDD - - 1 eSATA connector to rear panel - - 10/100/1000 BaseT Ethernet ports: - - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO - - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221 - - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221 - - USB 2.0 port: - - x1 USB2.0 port via an external ULPI PHY to micro-AB connector - - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector - - FlexCAN ports: - - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B) - interface; - - DUART interface: - - DUART interface: supports two UARTs up to 115200 bps for - console display - - RJ45 connectors are used for these 2 UART ports. - - TDM - - 2 FXS ports connected via an external SLIC to the TDM interface. - SLIC is controllled via SPI. - - 1 FXO port connected via a relay to FXS for switchover to POTS -Board connectors: - - Mini-ITX power supply connector - - JTAG/COP for debugging -IEEE Std. 1588 signals for test and measurement -Real-time clock on I2C bus -POR - - support critical POR setting changed via switch on board -PCB - - 6-layer routing (4-layer signals, 2-layer power and ground) - - -Physical Memory Map on P1010RDB -=============================== -Address Start Address End Memory type Attributes -0x0000_0000 0x3fff_ffff DDR 1G Cacheable -0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable -0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable -0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable -0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable -0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable -0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0 -0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - - -Serial Port Configuration on P1010RDB -===================================== -Configure the serial port of the attached computer with the following values: - -Data rate: 115200 bps - -Number of data bits: 8 - -Parity: None - -Number of Stop bits: 1 - -Flow Control: Hardware/None - - -Settings of DIP-switch -====================== - SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash - SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash - SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash -Note: 1 stands for 'on', 0 stands for 'off' - - -Setting of hwconfig -=================== -If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or -"fsl_p1010mux:tdm_can=tdm" explicitly in u-boot prompt as below for example: -setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi" -By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection -is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM -instead of to CAN/UART1. - - -Build and burn U-Boot to NOR flash -================================== -1. Build u-boot.bin image - export CROSS_COMPILE=/your_path/powerpc-linux-gnu- - make P1010RDB_NOR - -2. Burn u-boot.bin into NOR flash - => tftp $loadaddr $uboot - => protect off eff40000 +$filesize - => erase eff40000 +$filesize - => cp.b $loadaddr eff40000 $filesize - -3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. - - -Alternate NOR bank -================== -1. Burn u-boot.bin into alternate NOR bank - => tftp $loadaddr $uboot - => protect off eef40000 +$filesize - => erase eef40000 +$filesize - => cp.b $loadaddr eef40000 $filesize - -2. Switch to alternate NOR bank - => mw.b ffb00009 1 - => reset - or set SW1[8]= ON - -SW1[8]= OFF: Upper bank used for booting start -SW1[8]= ON: Lower bank used for booting start -CPLD NOR bank selection register address 0xFFB00009 Bit[0]: -0 - boot from upper 4 sectors -1 - boot from lower 4 sectors - - -Build and burn U-Boot to NAND flash -=================================== -1. Build u-boot.bin image - export ARCH=powerpc - export CROSS_COMPILE=/your_path/powerpc-linux-gnu- - make P1010RDB_NAND - -2. Burn u-boot-nand.bin into NAND flash - => tftp $loadaddr $uboot-nand - => nand erase 0 $filesize - => nand write $loadaddr 0 $filesize - -3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on. - - -Build and burn U-Boot to SPI flash -================================== -1. Build u-boot-spi.bin image - make P1010RDB_SPIFLASH_config; make - Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb - Download u-boot.bin to linux and you can find some config files - under /usr/share such as config_xx.dat. Do below command: - boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \ - u-boot-spi.bin - to generate u-boot-spi.bin. - -2. Burn u-boot-spi.bin into SPI flash - => tftp $loadaddr $uboot-spi - => sf erase 0 100000 - => sf write $loadaddr 0 $filesize - -3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on. - - -CPLD POR setting registers -========================== -1. Set POR switch selection register (addr 0xFFB00011) to 0. -2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with - proper values. - If change boot ROM location to NOR or NAND flash, need write the IFC_CS0 - switch command by I2C. -3. Send reset command. - After reset, the new POR setting will be implemented. - -Two examples are given in below: -Switch from NOR to NAND boot with default frequency: - => i2c dev 0 - => i2c mw 18 1 f9 - => i2c mw 18 3 f0 - => mw.b ffb00011 0 - => mw.b ffb00017 1 - => reset -Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz): - => i2c dev 0 - => i2c mw 18 1 f1 - => i2c mw 18 3 f0 - => mw.b ffb00011 0 - => mw.b ffb00014 2 - => mw.b ffb00015 5 - => mw.b ffb00016 3 - => mw.b ffb00017 f - => reset - - -Boot Linux from network using TFTP on P1010RDB -============================================== -Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area. - => tftp 1000000 uImage - => tftp 2000000 p1010rdb.dtb - => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb - => bootm 1000000 3000000 2000000 - - -For more details, please refer to P1010RDB User Guide and access website -www.freescale.com diff --git a/board/freescale/p1010rdb/README.P1010RDB-PB b/board/freescale/p1010rdb/README.P1010RDB-PB deleted file mode 100644 index 4a3b389877f..00000000000 --- a/board/freescale/p1010rdb/README.P1010RDB-PB +++ /dev/null @@ -1,187 +0,0 @@ -Overview -========= -The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC. -P1010RDB-PB is a variation of previous P1010RDB-PA board. - -The P1010 is a cost-effective, low-power, highly integrated host processor -based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that -addresses the requirements of several routing, gateways, storage, consumer, -and industrial applications. Applications of interest include the main CPUs and -I/O processors in network attached storage (NAS), the voice over IP (VoIP) -router/gateway, and wireless LAN (WLAN) and industrial controllers. - -The P1010RDB-PB board features are as following: -Memory subsystem: - - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus) - - 32M bytes NOR flash single-chip memory - - 2G bytes NAND flash memory - - 16M bytes SPI memory - - 256K bit M24256 I2C EEPROM - - I2C Board EEPROM 128x8 bit memory - - SD/MMC connector to interface with the SD memory card -Interfaces: - - Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII) - - PCIe 2.0: two x1 mini-PCIe slots - - SATA 2.0: two SATA interfaces - - USB 2.0: one USB interface - - FlexCAN: two FlexCAN interfaces (revision 2.0B) - - UART: one USB-to-Serial interface - - TDM: 2 FXS ports connected via an external SLIC to the TDM interface. - 1 FXO port connected via a relay to FXS for switchover to POTS - -Board connectors: - - Mini-ITX power supply connector - - JTAG/COP for debugging - -POR: support critical POR setting changed via switch on board -PCB: 6-layer routing (4-layer signals, 2-layer power and ground) - -Physical Memory Map on P1010RDB -=============================== -Address Start Address End Memory type Attributes -0x0000_0000 0x3fff_ffff DDR 1G Cacheable -0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable -0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable -0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable -0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable -0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable -0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0 -0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - - -Serial Port Configuration on P1010RDB -===================================== -Configure the serial port of the attached computer with the following values: - -Data rate: 115200 bps - -Number of data bits: 8 - -Parity: None - -Number of Stop bits: 1 - -Flow Control: Hardware/None - - -P1010RDB-PB default DIP-switch settings -======================================= -SW1[1:8]= 10101010 -SW2[1:8]= 11011000 -SW3[1:8]= 10010000 -SW4[1:4]= 1010 -SW5[1:8]= 11111010 - - -P1010RDB-PB boot mode settings via DIP-switch -============================================= -SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot -SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot -SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot -SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot -Note: 1 stands for 'on', 0 stands for 'off' - - -Switch P1010RDB-PB boot mode via software without setting DIP-switch -==================================================================== -=> run boot_bank0 (boot from NOR bank0) -=> run boot_bank1 (boot from NOR bank1) -=> run boot_nand (boot from NAND flash) -=> run boot_spi (boot from SPI flash) -=> run boot_sd (boot from SD card) - - -Frequency combination support on P1010RDB-PB -============================================= -SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s) -0101 1 1010 0 800 400 800 -1001 1 1010 0 800 400 667 -1010 1 1100 0 667 333 667 -1000 0 1010 0 533 266 667 -0101 1 1010 1 1000 400 800 -1001 1 1010 1 1000 400 667 - - -Setting of pin mux -================== -Since pins multiplexing, TDM and CAN are muxed with SPI flash. -SDHC is muxed with IFC. IFC and SPI flash are enabled by default. - -To enable TDM: -=> setenv hwconfig fsl_p1010mux:tdm_can=tdm -=> save;reset - -To enable FlexCAN: -=> setenv hwconfig fsl_p1010mux:tdm_can=can -=> save;reset - -To enable SDHC in case of NOR/NAND/SPI boot - a) For temporary use case in runtime without reboot system - run 'mux sdhc' in U-Boot to validate SDHC with invalidating IFC. - - b) For long-term use case - set 'esdhc' in hwconfig and save it. - -To enable IFC in case of SD boot - a) For temporary use case in runtime without reboot system - run 'mux ifc' in U-Boot to validate IFC with invalidating SDHC. - - b) For long-term use case - set 'ifc' in hwconfig and save it. - - -Build images for different boot mode -==================================== -First setup cross compile environment on build host - $ export CROSS_COMPILE=/powerpc-linux-gnu- - -1. For NOR boot - $ make P1010RDB-PB_NOR - -2. For NAND boot - $ make P1010RDB-PB_NAND - -3. For SPI boot - $ make P1010RDB-PB_SPIFLASH - -4. For SD boot - $ make P1010RDB-PB_SDCARD - - -Steps to program images to flash for different boot mode -======================================================== -1. NOR boot - => tftp 1000000 u-boot.bin - For bank0 - => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize - set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board - - For bank1 - => pro off all;era eef40000 eeffffff;cp.b 1000000 eef40000 $filesize - set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board - -2. NAND boot - => tftp 1000000 u-boot-nand.bin - => nand erase 0 $filesize; nand write $loadaddr 0 $filesize - Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board - -3. SPI boot - 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin - 2) => tftp 1000000 u-boot-spi-combined.bin - 3) => sf probe 0; sf erase 0 100000; sf write 1000000 0 100000 - set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board - -4. SD boot - 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin - 2) => tftp 1000000 u-boot-sd-combined.bin - 3) => mux sdhc - 4) => mmc write 1000000 0 1050 - set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board - - -Boot Linux from network using TFTP on P1010RDB-PB -================================================= -Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path. - => tftp 1000000 uImage - => tftp 2000000 p1010rdb.dtb - => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb - => bootm 1000000 3000000 2000000 - - -For more details, please refer to P1010RDB-PB User Guide and access website -www.freescale.com and Freescale QorIQ SDK Infocenter document. diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c deleted file mode 100644 index 43a0936bc9a..00000000000 --- a/board/freescale/p1010rdb/ddr.c +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Samsung K4B2G0846C-HCF8 - * The following timing are for "downshift" - * i.e. to use CL9 part as CL7 - * otherwise, tAA, tRCD, tRP will be 13500ps - * and tRC will be 49500ps - */ -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 1073741824u, - .capacity = 1073741824u, - .primary_sdram_width = 32, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 15, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 1875, - .caslat_x = 0x1e << 4, /* 5,6,7,8 */ - .taa_ps = 13125, - .twr_ps = 15000, - .trcd_ps = 13125, - .trrd_ps = 7500, - .trp_ps = 13125, - .tras_ps = 37500, - .trc_ps = 50625, - .trfc_ps = 160000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 37500, -}; - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - const char dimm_model[] = "Fixed DDR on board"; - - if ((controller_number == 0) && (dimm_number == 0)) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - struct cpu_type *cpu; - int i; - popts->clk_adjust = 6; - popts->cpo_override = 0x1f; - popts->write_data_delay = 2; - popts->half_strength_driver_enable = 1; - /* Write leveling override */ - popts->wrlvl_en = 1; - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - popts->wrlvl_start = 0x8; - popts->trwt_override = 1; - popts->trwt = 0; - - cpu = gd->arch.cpu; - /* P1014 and it's derivatives support max 16it DDR width */ - if (cpu->soc_ver == SVR_P1014) - popts->data_bus_width = DDR_DATA_BUS_WIDTH_16; - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; - popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; - } -} diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c deleted file mode 100644 index a7d80f28521..00000000000 --- a/board/freescale/p1010rdb/law.c +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC), - SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), - SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c deleted file mode 100644 index 9b4b6f34f46..00000000000 --- a/board/freescale/p1010rdb/p1010rdb.c +++ /dev/null @@ -1,679 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define GPIO4_PCIE_RESET_SET 0x08000000 -#define MUX_CPLD_CAN_UART 0x00 -#define MUX_CPLD_TDM 0x01 -#define MUX_CPLD_SPICS0_FLASH 0x00 -#define MUX_CPLD_SPICS0_SLIC 0x02 -#define PMUXCR1_IFC_MASK 0x00ffff00 -#define PMUXCR1_SDHC_MASK 0x00fff000 -#define PMUXCR1_SDHC_ENABLE 0x00555000 - -enum { - MUX_TYPE_IFC, - MUX_TYPE_SDHC, - MUX_TYPE_SPIFLASH, - MUX_TYPE_TDM, - MUX_TYPE_CAN, - MUX_TYPE_CS0_NOR, - MUX_TYPE_CS0_NAND, -}; - -enum { - I2C_READ_BANK, - I2C_READ_PCB_VER, -}; - -static uint sd_ifc_mux; - -struct cpld_data { - u8 cpld_ver; /* cpld revision */ -#if defined(CONFIG_TARGET_P1010RDB_PA) - u8 pcba_ver; /* pcb revision number */ - u8 twindie_ddr3; - u8 res1[6]; - u8 bank_sel; /* NOR Flash bank */ - u8 res2[5]; - u8 usb2_sel; - u8 res3[1]; - u8 porsw_sel; - u8 tdm_can_sel; - u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */ - u8 por0; /* POR Options */ - u8 por1; /* POR Options */ - u8 por2; /* POR Options */ - u8 por3; /* POR Options */ -#elif defined(CONFIG_TARGET_P1010RDB_PB) - u8 rom_loc; -#endif -}; - -int board_early_init_f(void) -{ - ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); - struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; - /* Clock configuration to access CPLD using IFC(GPCM) */ - setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); - /* - * Reset PCIe slots via GPIO4 - */ - setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET); - setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET); - - return 0; -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CFG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_16M, 1); - - set_tlb(1, flashbase + 0x1000000, - CFG_SYS_FLASH_BASE_PHYS + 0x1000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel+1, BOOKE_PAGESZ_16M, 1); - return 0; -} - -int config_board_mux(int ctrl_type) -{ - ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u8 tmp; - -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - int ret; -#if defined(CONFIG_TARGET_P1010RDB_PA) - struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); - - ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, - I2C_PCA9557_ADDR1, 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", - __func__, I2C_PCA9557_BUS_NUM); - return ret; - } - switch (ctrl_type) { - case MUX_TYPE_IFC: - tmp = 0xf0; - dm_i2c_write(dev, 3, &tmp, 1); - tmp = 0x01; - dm_i2c_write(dev, 1, &tmp, 1); - sd_ifc_mux = MUX_TYPE_IFC; - clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); - break; - case MUX_TYPE_SDHC: - tmp = 0xf0; - dm_i2c_write(dev, 3, &tmp, 1); - tmp = 0x05; - dm_i2c_write(dev, 1, &tmp, 1); - sd_ifc_mux = MUX_TYPE_SDHC; - clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, - PMUXCR1_SDHC_ENABLE); - break; - case MUX_TYPE_SPIFLASH: - out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); - break; - case MUX_TYPE_TDM: - out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); - out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); - break; - case MUX_TYPE_CAN: - out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); - break; - default: - break; - } -#elif defined(CONFIG_TARGET_P1010RDB_PB) - ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, - I2C_PCA9557_ADDR2, 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", - __func__, I2C_PCA9557_BUS_NUM); - return ret; - } - switch (ctrl_type) { - case MUX_TYPE_IFC: - dm_i2c_read(dev, 0, &tmp, 1); - clrbits_8(&tmp, 0x04); - dm_i2c_write(dev, 1, &tmp, 1); - dm_i2c_read(dev, 3, &tmp, 1); - clrbits_8(&tmp, 0x04); - dm_i2c_write(dev, 3, &tmp, 1); - sd_ifc_mux = MUX_TYPE_IFC; - clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); - break; - case MUX_TYPE_SDHC: - dm_i2c_read(dev, 0, &tmp, 1); - setbits_8(&tmp, 0x04); - dm_i2c_write(dev, 1, &tmp, 1); - dm_i2c_read(dev, 3, &tmp, 1); - clrbits_8(&tmp, 0x04); - dm_i2c_write(dev, 3, &tmp, 1); - sd_ifc_mux = MUX_TYPE_SDHC; - clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, - PMUXCR1_SDHC_ENABLE); - break; - case MUX_TYPE_SPIFLASH: - dm_i2c_read(dev, 0, &tmp, 1); - clrbits_8(&tmp, 0x80); - dm_i2c_write(dev, 1, &tmp, 1); - dm_i2c_read(dev, 3, &tmp, 1); - clrbits_8(&tmp, 0x80); - dm_i2c_write(dev, 3, &tmp, 1); - break; - case MUX_TYPE_TDM: - dm_i2c_read(dev, 0, &tmp, 1); - setbits_8(&tmp, 0x82); - dm_i2c_write(dev, 1, &tmp, 1); - dm_i2c_read(dev, 3, &tmp, 1); - clrbits_8(&tmp, 0x82); - dm_i2c_write(dev, 3, &tmp, 1); - break; - case MUX_TYPE_CAN: - dm_i2c_read(dev, 0, &tmp, 1); - clrbits_8(&tmp, 0x02); - dm_i2c_write(dev, 1, &tmp, 1); - dm_i2c_read(dev, 3, &tmp, 1); - clrbits_8(&tmp, 0x02); - dm_i2c_write(dev, 3, &tmp, 1); - break; - case MUX_TYPE_CS0_NOR: - dm_i2c_read(dev, 0, &tmp, 1); - clrbits_8(&tmp, 0x08); - dm_i2c_write(dev, 1, &tmp, 1); - dm_i2c_read(dev, 3, &tmp, 1); - clrbits_8(&tmp, 0x08); - dm_i2c_write(dev, 3, &tmp, 1); - break; - case MUX_TYPE_CS0_NAND: - dm_i2c_read(dev, 0, &tmp, 1); - setbits_8(&tmp, 0x08); - dm_i2c_write(dev, 1, &tmp, 1); - dm_i2c_read(dev, 3, &tmp, 1); - clrbits_8(&tmp, 0x08); - dm_i2c_write(dev, 3, &tmp, 1); - break; - default: - break; - } -#endif -#else -#if defined(CONFIG_TARGET_P1010RDB_PA) - struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); - - switch (ctrl_type) { - case MUX_TYPE_IFC: - i2c_set_bus_num(I2C_PCA9557_BUS_NUM); - tmp = 0xf0; - i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1); - tmp = 0x01; - i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1); - sd_ifc_mux = MUX_TYPE_IFC; - clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); - break; - case MUX_TYPE_SDHC: - i2c_set_bus_num(I2C_PCA9557_BUS_NUM); - tmp = 0xf0; - i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1); - tmp = 0x05; - i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1); - sd_ifc_mux = MUX_TYPE_SDHC; - clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, - PMUXCR1_SDHC_ENABLE); - break; - case MUX_TYPE_SPIFLASH: - out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); - break; - case MUX_TYPE_TDM: - out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); - out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); - break; - case MUX_TYPE_CAN: - out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); - break; - default: - break; - } -#elif defined(CONFIG_TARGET_P1010RDB_PB) - uint orig_bus = i2c_get_bus_num(); - i2c_set_bus_num(I2C_PCA9557_BUS_NUM); - - switch (ctrl_type) { - case MUX_TYPE_IFC: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - clrbits_8(&tmp, 0x04); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x04); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - sd_ifc_mux = MUX_TYPE_IFC; - clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); - break; - case MUX_TYPE_SDHC: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - setbits_8(&tmp, 0x04); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x04); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - sd_ifc_mux = MUX_TYPE_SDHC; - clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, - PMUXCR1_SDHC_ENABLE); - break; - case MUX_TYPE_SPIFLASH: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - clrbits_8(&tmp, 0x80); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x80); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - break; - case MUX_TYPE_TDM: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - setbits_8(&tmp, 0x82); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x82); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - break; - case MUX_TYPE_CAN: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - clrbits_8(&tmp, 0x02); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x02); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - break; - case MUX_TYPE_CS0_NOR: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - clrbits_8(&tmp, 0x08); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x08); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - break; - case MUX_TYPE_CS0_NAND: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - setbits_8(&tmp, 0x08); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x08); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - break; - default: - break; - } - i2c_set_bus_num(orig_bus); -#endif -#endif - return 0; -} - -#ifdef CONFIG_TARGET_P1010RDB_PB -int i2c_pca9557_read(int type) -{ - u8 val; - int bus_num = I2C_PCA9557_BUS_NUM; - -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", - __func__, bus_num); - return ret; - } - dm_i2c_read(dev, 0, &val, 1); -#else - i2c_set_bus_num(bus_num); - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1); -#endif - - switch (type) { - case I2C_READ_BANK: - val = (val & 0x10) >> 4; - break; - case I2C_READ_PCB_VER: - val = ((val & 0x60) >> 5) + 1; - break; - default: - break; - } - - return val; -} -#endif - -int checkboard(void) -{ - struct cpu_type *cpu; - struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); - u8 val; - - cpu = gd->arch.cpu; -#if defined(CONFIG_TARGET_P1010RDB_PA) - printf("Board: %sRDB-PA, ", cpu->name); -#elif defined(CONFIG_TARGET_P1010RDB_PB) - printf("Board: %sRDB-PB, ", cpu->name); -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - I2C_PCA9557_BUS_NUM); - return ret; - } - val = 0x0; /* no polarity inversion */ - dm_i2c_write(dev, 2, &val, 1); -#else - i2c_set_bus_num(I2C_PCA9557_BUS_NUM); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - val = 0x0; /* no polarity inversion */ - i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1); -#endif -#endif - -#ifdef CONFIG_SDCARD - /* switch to IFC to read info from CPLD */ - config_board_mux(MUX_TYPE_IFC); -#endif - -#if defined(CONFIG_TARGET_P1010RDB_PA) - val = (in_8(&cpld_data->pcba_ver) & 0xf); - printf("PCB: v%x.0\n", val); -#elif defined(CONFIG_TARGET_P1010RDB_PB) - val = in_8(&cpld_data->cpld_ver); - printf("CPLD: v%x.%x, ", val >> 4, val & 0xf); - printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER)); - val = in_8(&cpld_data->rom_loc) & 0xf; - puts("Boot from: "); - switch (val) { - case 0xf: - config_board_mux(MUX_TYPE_CS0_NOR); - printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK)); - break; - case 0xe: - puts("SDHC\n"); - val = 0x60; /* set pca9557 pin input/output */ -#if CONFIG_IS_ENABLED(DM_I2C) - dm_i2c_write(dev, 3, &val, 1); -#else - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1); -#endif - break; - case 0x5: - config_board_mux(MUX_TYPE_IFC); - config_board_mux(MUX_TYPE_CS0_NAND); - puts("NAND\n"); - break; - case 0x6: - config_board_mux(MUX_TYPE_IFC); - puts("SPI\n"); - break; - default: - puts("unknown\n"); - break; - } -#endif - return 0; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void fdt_del_flexcan(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "fsl,p1010-flexcan")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -void fdt_del_spi_flash(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "spansion,s25sl12801")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -void fdt_del_spi_slic(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "zarlink,le88266")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -void fdt_del_tdm(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "fsl,starlite-tdm")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -void fdt_del_sdhc(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "fsl,esdhc")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -void fdt_del_ifc(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "fsl,ifc")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -void fdt_disable_uart1(void *blob) -{ - int nodeoff; - - nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550", - CFG_SYS_NS16550_COM2); - - if (nodeoff > 0) { - fdt_status_disabled(blob, nodeoff); - } else { - printf("WARNING unable to set status for fsl,ns16550 " - "uart1: %s\n", fdt_strerror(nodeoff)); - } -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - phys_addr_t base; - phys_size_t size; - struct cpu_type *cpu; - - cpu = gd->arch.cpu; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#if defined(CONFIG_HAS_FSL_DR_USB) - fsl_fdt_fixup_dr_usb(blob, bd); -#endif - - /* P1014 and it's derivatives don't support CAN and eTSEC3 */ - if (cpu->soc_ver == SVR_P1014) { - fdt_del_flexcan(blob); - fdt_del_node_and_alias(blob, "ethernet2"); - } - - /* Delete IFC node as IFC pins are multiplexing with SDHC */ - if (sd_ifc_mux != MUX_TYPE_IFC) - fdt_del_ifc(blob); - else - fdt_del_sdhc(blob); - - if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { - fdt_del_tdm(blob); - fdt_del_spi_slic(blob); - } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { - fdt_del_flexcan(blob); - fdt_del_spi_flash(blob); - fdt_disable_uart1(blob); - } else { - /* - * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm" - * explicitly, defaultly spi_cs_sel to spi-flash instead of - * to tdm/slic. - */ - fdt_del_tdm(blob); - fdt_del_flexcan(blob); - fdt_disable_uart1(blob); - } - - return 0; -} -#endif - -#ifdef CONFIG_SDCARD -int board_mmc_init(struct bd_info *bis) -{ - config_board_mux(MUX_TYPE_SDHC); - return -1; -} -#else -void board_reset(void) -{ - /* mux to IFC to enable CPLD for reset */ - if (sd_ifc_mux != MUX_TYPE_IFC) - config_board_mux(MUX_TYPE_IFC); -} -#endif - -int misc_init_r(void) -{ - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - - if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { - clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM | - MPC85xx_PMUXCR_CAN1_UART | - MPC85xx_PMUXCR_CAN2_TDM | - MPC85xx_PMUXCR_CAN2_UART); - config_board_mux(MUX_TYPE_CAN); - } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { - clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART | - MPC85xx_PMUXCR_CAN1_UART); - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM | - MPC85xx_PMUXCR_CAN1_TDM); - clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO); - setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM); - config_board_mux(MUX_TYPE_TDM); - } else { - /* defaultly spi_cs_sel to flash */ - config_board_mux(MUX_TYPE_SPIFLASH); - } - - if (hwconfig("esdhc")) - config_board_mux(MUX_TYPE_SDHC); - else if (hwconfig("ifc")) - config_board_mux(MUX_TYPE_IFC); - -#ifdef CONFIG_TARGET_P1010RDB_PB - setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); -#endif - return 0; -} - -#ifndef CONFIG_XPL_BUILD -static int pin_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - if (argc < 2) - return CMD_RET_USAGE; - if (strcmp(argv[1], "ifc") == 0) - config_board_mux(MUX_TYPE_IFC); - else if (strcmp(argv[1], "sdhc") == 0) - config_board_mux(MUX_TYPE_SDHC); - else - return CMD_RET_USAGE; - return 0; -} - -U_BOOT_CMD( - mux, 2, 0, pin_mux_cmd, - "configure multiplexing pin for IFC/SDHC bus in runtime", - "bus_type (e.g. mux sdhc)" -); -#endif diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c deleted file mode 100644 index fc26cef2cc8..00000000000 --- a/board/freescale/p1010rdb/spl.c +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/spl.h" - -DECLARE_GLOBAL_DATA_PTR; - -phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_L2_SIZE; -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio; - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; - struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; - - console_init_f(); - - /* Clock configuration to access CPLD using IFC(GPCM) */ - setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); - -#ifdef CONFIG_TARGET_P1010RDB_PB - setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); -#endif - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - gd->bus_clk = get_board_sys_clk() * plat_ratio; - - ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, - gd->bus_clk / 16 / CONFIG_BAUDRATE); - -#ifdef CONFIG_SPL_MMC_BOOT - puts("\nSD boot...\n"); -#elif defined(CONFIG_SPL_SPI_BOOT) - puts("\nSPI Flash boot...\n"); -#endif - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_VAL(RELOC_STACK), 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *)CONFIG_VAL(GD_ADDR); - struct bd_info *bd; - - memset(gd, 0, sizeof(gd_t)); - bd = (struct bd_info *)(CONFIG_VAL(GD_ADDR) + sizeof(gd_t)); - memset(bd, 0, sizeof(struct bd_info)); - gd->bd = bd; - - arch_cpu_init(); - get_clocks(); - mem_malloc_init(CONFIG_VAL(RELOC_MALLOC_ADDR), - CONFIG_VAL(RELOC_MALLOC_SIZE)); - gd->flags |= GD_FLG_FULL_MALLOC_INIT; - -#ifndef CONFIG_SPL_NAND_BOOT - env_init(); -#endif -#ifdef CONFIG_SPL_MMC_BOOT - mmc_initialize(bd); -#endif - - /* relocate environment function pointers etc. */ -#ifdef CONFIG_SPL_NAND_BOOT - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); - gd->env_addr = (ulong)(SPL_ENV_ADDR); - gd->env_valid = ENV_VALID; -#else - env_relocate(); -#endif - - i2c_init_all(); - - dram_init(); -#ifdef CONFIG_SPL_NAND_BOOT - puts("\nTertiary program loader running in sram..."); -#else - puts("\nSecond program loader running in sram..."); -#endif - -#ifdef CONFIG_SPL_MMC_BOOT - mmc_boot(); -#elif defined(CONFIG_SPL_SPI_BOOT) - fsl_spi_boot(); -#elif defined(CONFIG_SPL_NAND_BOOT) - nand_boot(); -#endif -} diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c deleted file mode 100644 index 8cd79c6fb5f..00000000000 --- a/board/freescale/p1010rdb/spl_minimal.c +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio; - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; - -#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM) - set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM); -#endif - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - gd->bus_clk = get_board_sys_clk() * plat_ratio; - - ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, - gd->bus_clk / 16 / CONFIG_BAUDRATE); - - puts("\nNAND boot... "); - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - puts("\nSecond program loader running in sram..."); - nand_boot(); -} - -void putc(char c) -{ - if (c == '\n') - ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, '\r'); - - ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, c); -} - -void puts(const char *str) -{ - while (*str) - putc(*str++); -} diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c deleted file mode 100644 index aa130ccf78b..00000000000 --- a/board/freescale/p1010rdb/tlb.c +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CFG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CFG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CFG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SPL_NAND_BOOT - SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - -#ifndef CONFIG_XPL_BUILD - SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_16M, 1), - - SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE + 0x1000000, - CFG_SYS_FLASH_BASE_PHYS + 0x1000000, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 3, BOOKE_PAGESZ_16M, 1), - -#ifdef CONFIG_PCI - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256K, 1), -#endif -#endif - - /* *I*G - Board CPLD */ - SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), - - SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_1M, 1), - -#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR) - SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 8, BOOKE_PAGESZ_1G, 1), -#endif - -#ifdef CFG_SYS_INIT_L2_ADDR - /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR, CFG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, - 0, 11, BOOKE_PAGESZ_256K, 1) -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig deleted file mode 100644 index cd36150f637..00000000000 --- a/board/freescale/p1_p2_rdb_pc/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -if TARGET_P1020RDB_PC || \ - TARGET_P1020RDB_PD || \ - TARGET_P2020RDB - -config SYS_BOARD - default "p1_p2_rdb_pc" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "p1_p2_rdb_pc" - -endif diff --git a/board/freescale/p1_p2_rdb_pc/MAINTAINERS b/board/freescale/p1_p2_rdb_pc/MAINTAINERS deleted file mode 100644 index 0004d717d1d..00000000000 --- a/board/freescale/p1_p2_rdb_pc/MAINTAINERS +++ /dev/null @@ -1,25 +0,0 @@ -P1_P2_RDB_PC BOARD -M: Priyanka Jain -S: Maintained -F: board/freescale/p1_p2_rdb_pc/ -F: include/configs/p1_p2_rdb_pc.h -F: configs/P1020RDB-PC_defconfig -F: configs/P1020RDB-PC_36BIT_defconfig -F: configs/P1020RDB-PC_36BIT_NAND_defconfig -F: configs/P1020RDB-PC_36BIT_SDCARD_defconfig -F: configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig -F: configs/P1020RDB-PC_NAND_defconfig -F: configs/P1020RDB-PC_SDCARD_defconfig -F: configs/P1020RDB-PC_SPIFLASH_defconfig -F: configs/P1020RDB-PD_defconfig -F: configs/P1020RDB-PD_NAND_defconfig -F: configs/P1020RDB-PD_SDCARD_defconfig -F: configs/P1020RDB-PD_SPIFLASH_defconfig -F: configs/P2020RDB-PC_defconfig -F: configs/P2020RDB-PC_36BIT_defconfig -F: configs/P2020RDB-PC_36BIT_NAND_defconfig -F: configs/P2020RDB-PC_36BIT_SDCARD_defconfig -F: configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig -F: configs/P2020RDB-PC_NAND_defconfig -F: configs/P2020RDB-PC_SDCARD_defconfig -F: configs/P2020RDB-PC_SPIFLASH_defconfig diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile deleted file mode 100644 index 8c13813e3b0..00000000000 --- a/board/freescale/p1_p2_rdb_pc/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2010-2011 Freescale Semiconductor, Inc. - -MINIMAL= - -ifdef CONFIG_XPL_BUILD -ifndef CONFIG_TPL_BUILD -ifdef CONFIG_SPL_INIT_MINIMAL -MINIMAL=y -endif -endif -endif - -ifdef MINIMAL -obj-y += spl_minimal.o -else -ifdef CONFIG_XPL_BUILD -obj-y += spl.o -endif -obj-y += p1_p2_rdb_pc.o -obj-y += ddr.o -endif - -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README deleted file mode 100644 index fd849bfc29a..00000000000 --- a/board/freescale/p1_p2_rdb_pc/README +++ /dev/null @@ -1,64 +0,0 @@ -Overview --------- -P1_P2_RDB_PC represents a set of boards including - P1020MSBG-PC - P1020RDB-PC - P1020RDB-PD - P1021RDB-PC - P1024RDB - P2020RDB-PC - -They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC -has 64-bit DDR. All others have 32-bit DDR. - -Key features on these boards include: - * DDR3 - * NOR flash - * NAND flash (on RDB's only) - * SPI flash (on RDB's only) - * SDHC/MMC card slot - * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB) - * PCIE slot and mini-PCIE slots - -As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM -is used to store SPD data. In case of absent or corrupted SPD, falling back -to timing data embedded in the source code will be used. Raw timing data is -extracted from DDR chip datasheet. Different speeds of DDR are supported with -this approach. ODT option is forced to fit this set of boards, again because -they don't have regular DIMMs. - -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification -for writing timing. - -VSC firmware Address is defined by default in config file for eTSEC1. - -SD width is based off DIP switch. DIP switch is detected on the -board by reading i2c bus and setting the appropriate mux values. - -Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have -pins multiplexing. QE function needs to be disabled to access Nor Flash and -CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe" -in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to -enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below - -'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD. -'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD. - -Device tree support and how to enable it for different configs --------------------------------------------------------------- -Device tree support is available for p1020rdb and p2020rdb for below mentioned boot, -1. NOR Boot -2. NAND Boot -3. SD Boot -4. SPIFLASH Boot - -To enable device tree support for other boot, below configs need to be -enabled in relative defconfig file, -1. CONFIG_DEFAULT_DEVICE_TREE="p1020rdb" (Change default device tree name if required) -2. CONFIG_OF_CONTROL -3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at - CFG_RESET_VECTOR_ADDRESS - 0xffc - -If device tree support is enabled in defconfig, -1. use 'u-boot.bin' for NOR boot. -2. use 'u-boot-with-spl.bin' for other boot. diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c deleted file mode 100644 index 8622a5a610a..00000000000 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ /dev/null @@ -1,290 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_SYS_DDR_RAW_TIMING -#if defined(CONFIG_P1020RDB_PROTO) -/* Micron MT41J256M8_187E */ -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 1073741824u, - .capacity = 1073741824u, - .primary_sdram_width = 32, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 15, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 1870, - .caslat_x = 0x1e << 4, /* 5,6,7,8 */ - .taa_ps = 13125, - .twr_ps = 15000, - .trcd_ps = 13125, - .trrd_ps = 7500, - .trp_ps = 13125, - .tras_ps = 37500, - .trc_ps = 50625, - .trfc_ps = 160000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 37500, -}; -#elif defined(CONFIG_TARGET_P2020RDB) -/* Micron MT41J128M16_15E */ -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 1073741824u, - .capacity = 1073741824u, - .primary_sdram_width = 64, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 14, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 1500, - .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */ - .taa_ps = 13500, - .twr_ps = 15000, - .trcd_ps = 13500, - .trrd_ps = 6000, - .trp_ps = 13500, - .tras_ps = 36000, - .trc_ps = 49500, - .trfc_ps = 160000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 30000, -}; -#elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) -/* Micron MT41J512M8_187E */ -dimm_params_t ddr_raw_timing = { - .n_ranks = 2, - .rank_density = 1073741824u, - .capacity = 2147483648u, - .primary_sdram_width = 32, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 15, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 1870, - .caslat_x = 0x1e << 4, /* 5,6,7,8 */ - .taa_ps = 13125, - .twr_ps = 15000, - .trcd_ps = 13125, - .trrd_ps = 7500, - .trp_ps = 13125, - .tras_ps = 37500, - .trc_ps = 50625, - .trfc_ps = 160000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 37500, -}; -#elif defined(CONFIG_TARGET_P1020RDB_PC) -/* - * Samsung K4B2G0846C-HCF8 - * The following timing are for "downshift" - * i.e. to use CL9 part as CL7 - * otherwise, tAA, tRCD, tRP will be 13500ps - * and tRC will be 49500ps - */ -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 1073741824u, - .capacity = 1073741824u, - .primary_sdram_width = 32, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 15, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 1875, - .caslat_x = 0x1e << 4, /* 5,6,7,8 */ - .taa_ps = 13125, - .twr_ps = 15000, - .trcd_ps = 13125, - .trrd_ps = 7500, - .trp_ps = 13125, - .tras_ps = 37500, - .trc_ps = 50625, - .trfc_ps = 160000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 37500, -}; -#elif defined(CONFIG_TARGET_P1024RDB) -/* - * Samsung K4B2G0846C-HCH9 - * The following timing are for "downshift" - * i.e. to use CL9 part as CL7 - * otherwise, tAA, tRCD, tRP will be 13500ps - * and tRC will be 49500ps - */ -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 1073741824u, - .capacity = 1073741824u, - .primary_sdram_width = 32, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 15, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 1500, - .caslat_x = 0x3e << 4, /* 5,6,7,8,9 */ - .taa_ps = 13125, - .twr_ps = 15000, - .trcd_ps = 13125, - .trrd_ps = 6000, - .trp_ps = 13125, - .tras_ps = 36000, - .trc_ps = 49125, - .trfc_ps = 160000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 30000, -}; -#else -#error Missing raw timing data for this board -#endif - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - const char dimm_model[] = "Fixed DDR on board"; - - if ((controller_number == 0) && (dimm_number == 0)) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} -#endif /* CONFIG_SYS_DDR_RAW_TIMING */ - -#ifdef CFG_SYS_DDR_CS0_BNDS -/* Fixed sdram init -- doesn't use serial presence detect. */ -phys_size_t fixed_sdram(void) -{ - sys_info_t sysinfo; - char buf[32]; - size_t ddr_size; - fsl_ddr_cfg_regs_t ddr_cfg_regs = { - .cs[0].bnds = CFG_SYS_DDR_CS0_BNDS, - .cs[0].config = CFG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CFG_SYS_DDR_CS0_CONFIG_2, -#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 - .cs[1].bnds = CFG_SYS_DDR_CS1_BNDS, - .cs[1].config = CFG_SYS_DDR_CS1_CONFIG, - .cs[1].config_2 = CFG_SYS_DDR_CS1_CONFIG_2, -#endif - .timing_cfg_3 = CFG_SYS_DDR_TIMING_3, - .timing_cfg_0 = CFG_SYS_DDR_TIMING_0, - .timing_cfg_1 = CFG_SYS_DDR_TIMING_1, - .timing_cfg_2 = CFG_SYS_DDR_TIMING_2, - .ddr_sdram_cfg = CFG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CFG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CFG_SYS_DDR_MODE_1, - .ddr_sdram_mode_2 = CFG_SYS_DDR_MODE_2, - .ddr_sdram_md_cntl = CFG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CFG_SYS_DDR_INTERVAL, - .ddr_data_init = 0xdeadbeef, /* Poison value */ - .ddr_sdram_clk_cntl = CFG_SYS_DDR_CLK_CTRL, - .ddr_init_addr = CFG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CFG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CFG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CFG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CFG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CFG_SYS_DDR_WRLVL_CONTROL, - .ddr_sr_cntr = CFG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CFG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CFG_SYS_DDR_RCW_2 - }; - - get_sys_info(&sysinfo); - printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, sysinfo.freq_ddrbus)); - - ddr_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; - - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); - - if (set_ddr_laws(CFG_SYS_DDR_SDRAM_BASE, - ddr_size, LAW_TRGT_IF_DDR_1) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - }; - - return ddr_size; -} -#endif - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - int i; - popts->clk_adjust = 6; - popts->cpo_override = 0x1f; - popts->write_data_delay = 2; - popts->half_strength_driver_enable = 1; - /* Write leveling override */ - popts->wrlvl_en = 1; - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - popts->wrlvl_start = 0x8; - popts->trwt_override = 1; - popts->trwt = 0; - - if (pdimm->primary_sdram_width == 64) - popts->data_bus_width = 0; - else if (pdimm->primary_sdram_width == 32) - popts->data_bus_width = 1; - else - printf("Error in DDR bus width configuration!\n"); - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; - popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; - } -} diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c deleted file mode 100644 index 49594070b83..00000000000 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -#ifdef CONFIG_VSC7385_ENET - SET_LAW(CFG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -#endif - SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), -#ifdef CFG_SYS_NAND_BASE_PHYS - SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c deleted file mode 100644 index a19a98dd0d1..00000000000 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ /dev/null @@ -1,481 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_QE - -#define GPIO_GETH_SW_PORT 1 -#define GPIO_GETH_SW_PIN 29 -#define GPIO_GETH_SW_DATA (1 << (31 - GPIO_GETH_SW_PIN)) - -#define GPIO_SLIC_PORT 1 -#define GPIO_SLIC_PIN 30 -#define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN)) - -const qe_iop_conf_t qe_iop_conf_tab[] = { - /* GPIO */ - {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */ - {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */ - {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */ - {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */ - {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ -}; -#endif - -struct cpld_data { - u8 cpld_rev_major; - u8 pcba_rev; - u8 wd_cfg; - u8 rst_bps_sw; - u8 load_default_n; - u8 rst_bps_wd; - u8 bypass_enable; - u8 bps_led; - u8 status_led; /* offset: 0x8 */ - u8 fxo_led; /* offset: 0x9 */ - u8 fxs_led; /* offset: 0xa */ - u8 rev4[2]; - u8 system_rst; /* offset: 0xd */ - u8 bps_out; - u8 rev5[3]; - u8 cpld_rev_minor; -}; - -#define CPLD_WD_CFG 0x03 -#define CPLD_RST_BSW 0x00 -#define CPLD_RST_BWD 0x00 -#define CPLD_BYPASS_EN 0x03 -#define CPLD_STATUS_LED 0x01 -#define CPLD_FXO_LED 0x01 -#define CPLD_FXS_LED 0x0F -#define CPLD_SYS_RST 0x00 - -void board_reset_prepare(void) -{ - /* - * During reset preparation, turn off external watchdog. - * This ensures that external watchdog does not trigger - * another reset or possible infinite reset loop. - */ - struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); - out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); - in_8(&cpld_data->wd_cfg); /* Read back to sync write */ -} - -void board_reset_last(void) -{ - struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); - out_8(&cpld_data->system_rst, 1); -} - -void board_cpld_init(void) -{ - struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); - u8 prev_wd_cfg = in_8(&cpld_data->wd_cfg); - - out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); - out_8(&cpld_data->status_led, CPLD_STATUS_LED); - out_8(&cpld_data->fxo_led, CPLD_FXO_LED); - out_8(&cpld_data->fxs_led, CPLD_FXS_LED); - - /* - * CPLD's system reset register on P1/P2 RDB boards is not autocleared - * after flipping it. If this register is set to one then CPLD triggers - * reset of CPU in few ms. - * - * CPLD does not trigger reset of CPU for 100ms after the last reset. - * - * This means that trying to reset board via CPLD system reset register - * cause reboot loop. To prevent this reboot loop, the only workaround - * is to try to clear CPLD's system reset register as early as possible - * and it has to be done in 100ms since the last start of reset. - */ - out_8(&cpld_data->system_rst, CPLD_SYS_RST); - - /* - * If watchdog timer was already set to non-disabled value then it means - * that watchdog timer was already activated, has already expired and - * caused CPU reset. If this happened then due to CPLD firmware bug, - * writing to wd_cfg register has no effect and therefore it is not - * possible to reactivate watchdog timer again. Also if CPU was reset - * via watchdog then some peripherals like i2c do not work. Watchdog and - * i2c start working again after CPU reset via non-watchdog method. - * - * So in case watchdog timer register in CPLD was already enabled then - * disable it in CPLD and reset CPU which cause new boot. Watchdog timer - * is disabled few lines above, after reading CPLD previous value. - * This logic (disabling timer before reset) prevents reboot loop. - */ - if (prev_wd_cfg != CPLD_WD_CFG) { - eieio(); - do_reset(NULL, 0, 0, NULL); - while (1); /* do_reset() does not occur immediately */ - } -} - -void board_gpio_init(void) -{ -#ifdef CONFIG_QE - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); - - /* Enable VSC7385 switch */ - setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA); - - /* Enable SLIC */ - setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA); -#else - - ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); - - /* - * GPIO10 DDR Reset, open drain - * GPIO7 LOAD_DEFAULT_N Input - * GPIO11 WDI (watchdog input) - * GPIO12 Ethernet Switch Reset - * GPIO13 SLIC Reset - */ - - setbits_be32(&pgpio->gpdir, 0x02130000); -#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL) - /* init DDR3 reset signal */ - setbits_be32(&pgpio->gpdir, 0x00200000); - setbits_be32(&pgpio->gpodr, 0x00200000); - clrbits_be32(&pgpio->gpdat, 0x00200000); - udelay(1000); - setbits_be32(&pgpio->gpdat, 0x00200000); - udelay(1000); - clrbits_be32(&pgpio->gpdir, 0x00200000); -#endif - -#ifdef CONFIG_VSC7385_ENET - /* reset VSC7385 Switch */ - setbits_be32(&pgpio->gpdir, 0x00080000); - setbits_be32(&pgpio->gpdat, 0x00080000); -#endif - -#ifdef CFG_SLIC - /* reset SLIC */ - setbits_be32(&pgpio->gpdir, 0x00040000); - setbits_be32(&pgpio->gpdat, 0x00040000); -#endif -#endif -} - -int board_early_init_f(void) -{ - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_CD); -#ifndef SDHC_WP_IS_GPIO - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_WP); -#endif - clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV); - - clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); -#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC) - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA); -#endif - - board_gpio_init(); - board_cpld_init(); - - return 0; -} - -#if defined(CONFIG_TARGET_P1020RDB_PC) -#define BOARD_NAME "P1020RDB-PC" -#elif defined(CONFIG_TARGET_P1020RDB_PD) -#define BOARD_NAME "P1020RDB-PD" -#elif defined(CONFIG_TARGET_P2020RDB) -#define BOARD_NAME "P2020RDB-PC" -#endif - -int checkboard_p1_p2(void) -{ - struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u8 in, out, invert, io_config, val; - int bus_num = CONFIG_SYS_SPD_BUS_NUM; - - /* FIXME: This should just use the model from the device tree or similar */ -#ifdef BOARD_NAME - printf("Board: %s ", BOARD_NAME); -#endif - - printf("CPLD: V%d.%d PCBA: V%d.0\n", - in_8(&cpld_data->cpld_rev_major) & 0x0F, - in_8(&cpld_data->cpld_rev_minor) & 0x0F, - in_8(&cpld_data->pcba_rev) & 0x0F); - - /* Initialize i2c early for rom_loc and flash bank information */ - #if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_PCA9557_ADDR, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return 0; /* Don't want to hang() on this error */ - } - - if (dm_i2c_read(dev, 0, &in, 1) < 0 || - dm_i2c_read(dev, 1, &out, 1) < 0 || - dm_i2c_read(dev, 2, &invert, 1) < 0 || - dm_i2c_read(dev, 3, &io_config, 1) < 0) { - printf("Error reading i2c boot information!\n"); - return 0; /* Don't want to hang() on this error */ - } - #else /* Non DM I2C support - will be removed */ - i2c_set_bus_num(bus_num); - - if (i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 || - i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 || - i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 || - i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) { - printf("Error reading i2c boot information!\n"); - return 0; /* Don't want to hang() on this error */ - } - #endif - - val = ((in ^ invert) & io_config) | (out & (~io_config)); - - puts("rom_loc: "); - if (0) { -#ifdef __SW_BOOT_SD - } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) { - puts("sd"); -#endif -#ifdef __SW_BOOT_SD2 - } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD2) { - puts("sd"); -#endif -#ifdef __SW_BOOT_SPI - } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) { - puts("spi"); -#endif -#ifdef __SW_BOOT_NAND - } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) { - puts("nand"); -#endif -#ifdef __SW_BOOT_PCIE - } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) { - puts("pcie"); -#endif - } else { - if (val & 0x2) - puts("nor lower bank"); - else - puts("nor upper bank"); - } - puts("\n"); - - if (val & 0x1) { - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); - puts("SD/MMC : 8-bit Mode\n"); - puts("eSPI : Disabled\n"); - } else { - puts("SD/MMC : 4-bit Mode\n"); - puts("eSPI : Enabled\n"); - } - - return 0; -} - -#if !defined(CONFIG_TARGET_TURRIS_1X) -int checkboard(void) -{ - return checkboard_p1_p2(); -} -#endif - -int board_early_init_r(void) -{ - const unsigned int flashbase = CFG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); -#ifdef CONFIG_VSC7385_ENET - unsigned int vscfw_addr; - char *tmp; -#endif - - /* - * Remap Boot flash region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */ - 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */ - -#ifdef CONFIG_VSC7385_ENET - /* If a VSC7385 microcode image is present, then upload it. */ - tmp = env_get("vscfw_addr"); - if (tmp) { - vscfw_addr = hextoul(tmp, NULL); - printf("uploading VSC7385 microcode from %x\n", vscfw_addr); - if (vsc7385_upload_firmware((void *)vscfw_addr, - CFG_VSC7385_IMAGE_SIZE)) - puts("Failure uploading VSC7385 microcode.\n"); - } else { - puts("No address specified for VSC7385 microcode.\n"); - } -#endif - return 0; -} - -__weak void p1_p2_rdb_pc_fix_fdt_model(void *blob) {} - -#if defined(CONFIG_OF_BOARD_SETUP) || defined(CONFIG_OF_BOARD_FIXUP) -static void fix_max6370_watchdog(void *blob) -{ - int off = fdt_node_offset_by_compatible(blob, -1, "maxim,max6370"); - ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); - u32 gpioval = in_be32(&pgpio->gpdat); - - /* - * Delete watchdog max6370 node in load_default mode (detected by - * GPIO7 - LOAD_DEFAULT_N) because CPLD in load_default mode ignores - * watchdog reset signal. CPLD in load_default mode does not reset - * board when watchdog triggers reset signal. - */ - if (!(gpioval & BIT(31-7)) && off >= 0) - fdt_del_node(blob, off); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, struct bd_info *bd) -{ - phys_addr_t base; - phys_size_t size; -#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC) - const char *soc_usb_compat = "fsl-usb2-dr"; - int usb_err, usb1_off, usb2_off; -#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) - int err; -#endif -#endif - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_QE - do_fixup_by_compat(blob, "fsl,qe", "status", "okay", - sizeof("okay"), 0); -#endif - - p1_p2_rdb_pc_fix_fdt_model(blob); - fix_max6370_watchdog(blob); - -#if defined(CONFIG_HAS_FSL_DR_USB) - fsl_fdt_fixup_dr_usb(blob, bd); -#endif - -#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC) -#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) - /* Delete eLBC node as it is muxed with USB2 controller */ - if (hwconfig("usb2")) { - const char *soc_elbc_compat = "fsl,p1020-elbc"; - int off = fdt_node_offset_by_compatible(blob, -1, - soc_elbc_compat); - if (off < 0) { - printf("WARNING: could not find compatible node %s\n", - soc_elbc_compat); - return off; - } - err = fdt_del_node(blob, off); - if (err < 0) { - printf("WARNING: could not remove %s\n", - soc_elbc_compat); - return err; - } - return 0; - } -#endif - -/* Delete USB2 node as it is muxed with eLBC */ - usb1_off = fdt_node_offset_by_compatible(blob, -1, - soc_usb_compat); - if (usb1_off < 0) { - printf("WARNING: could not find compatible node %s\n", - soc_usb_compat); - return usb1_off; - } - usb2_off = fdt_node_offset_by_compatible(blob, usb1_off, - soc_usb_compat); - if (usb2_off < 0) { - printf("WARNING: could not find compatible node %s\n", - soc_usb_compat); - return usb2_off; - } - usb_err = fdt_del_node(blob, usb2_off); - if (usb_err < 0) { - printf("WARNING: could not remove %s\n", soc_usb_compat); - return usb_err; - } -#endif - - return 0; -} -#endif - -#ifdef CONFIG_OF_BOARD_FIXUP -int board_fix_fdt(void *blob) -{ - p1_p2_rdb_pc_fix_fdt_model(blob); - fix_max6370_watchdog(blob); - return 0; -} -#endif diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c deleted file mode 100644 index b07f481fbf9..00000000000 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/spl.h" - -DECLARE_GLOBAL_DATA_PTR; - -phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_L2_SIZE; -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio, bus_clk; - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; - - /* - * Call board_early_init_f() as early as possible as it workarounds - * reboot loop due to broken CPLD state machine for reset line. - */ - board_early_init_f(); - - console_init_f(); - - /* Set pmuxcr to allow both i2c1 and i2c2 */ - setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); - setbits_be32(&gur->pmuxcr, - in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); - - /* Read back the register to synchronize the write. */ - in_be32(&gur->pmuxcr); - -#ifdef CONFIG_SPL_SPI_BOOT - clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); -#endif - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - bus_clk = get_board_sys_clk() * plat_ratio; - gd->bus_clk = bus_clk; - - ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, - bus_clk / 16 / CONFIG_BAUDRATE); -#ifdef CONFIG_SPL_MMC_BOOT - puts("\nSD boot...\n"); -#elif defined(CONFIG_SPL_SPI_BOOT) - puts("\nSPI Flash boot...\n"); -#endif - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_VAL(RELOC_STACK), 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *)CONFIG_VAL(GD_ADDR); - struct bd_info *bd; - - memset(gd, 0, sizeof(gd_t)); - bd = (struct bd_info *)(CONFIG_VAL(GD_ADDR) + sizeof(gd_t)); - memset(bd, 0, sizeof(struct bd_info)); - gd->bd = bd; - - arch_cpu_init(); - get_clocks(); - mem_malloc_init(CONFIG_VAL(RELOC_MALLOC_ADDR), - CONFIG_VAL(RELOC_MALLOC_SIZE)); - gd->flags |= GD_FLG_FULL_MALLOC_INIT; - -#ifdef CONFIG_SPL_ENV_SUPPORT -#ifndef CONFIG_SPL_NAND_BOOT - env_init(); -#endif -#endif -#ifdef CONFIG_SPL_MMC_BOOT - mmc_initialize(bd); -#endif -#ifdef CONFIG_SPL_ENV_SUPPORT - /* relocate environment function pointers etc. */ -#ifdef CONFIG_SPL_NAND_BOOT - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); - gd->env_addr = (ulong)(SPL_ENV_ADDR); - gd->env_valid = ENV_VALID; -#else - env_relocate(); -#endif -#endif - -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) - i2c_init_all(); -#else - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - - dram_init(); -#ifdef CONFIG_SPL_NAND_BOOT - puts("Tertiary program loader running in sram..."); -#else - puts("Second program loader running in sram...\n"); -#endif - -#ifdef CONFIG_SPL_MMC_BOOT - mmc_boot(); -#elif defined(CONFIG_SPL_SPI_BOOT) - fsl_spi_boot(); -#elif defined(CONFIG_SPL_NAND_BOOT) - nand_boot(); -#endif -} diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c deleted file mode 100644 index 511bcf5506b..00000000000 --- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio; - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; - -#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM) - set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM); -#endif - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - gd->bus_clk = get_board_sys_clk() * plat_ratio; - - ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, - gd->bus_clk / 16 / CONFIG_BAUDRATE); - - puts("\nNAND boot... "); - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - puts("\nSecond program loader running in sram..."); - nand_boot(); -} - -void putc(char c) -{ - if (c == '\n') - ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, '\r'); - - ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, c); -} - -void puts(const char *str) -{ - while (*str) - putc(*str++); -} diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c deleted file mode 100644 index f27821418eb..00000000000 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, - CFG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - -#ifndef CONFIG_XPL_BUILD - /* W**G* - Flash/promjet, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_64M, 1), - -#ifdef CONFIG_PCI - /* *I*G* - PCI memory 1.5G */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI I/O effective: 192K */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256K, 1), -#endif - -#ifdef CONFIG_VSC7385_ENET - /* *I*G - VSC7385 Switch */ - SET_TLB_ENTRY(1, CFG_SYS_VSC7385_BASE, CFG_SYS_VSC7385_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_1M, 1), -#endif -#endif /* not SPL */ - - SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_1M, 1), - -#ifdef CFG_SYS_NAND_BASE - /* *I*G - NAND */ - SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_1M, 1), -#endif - -#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR) - /* **M** - 1G DDR for eSDHC/eSPI/NAND boot */ - SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 8, BOOKE_PAGESZ_1G, 1), - -#if defined(CONFIG_TARGET_P1020RDB_PD) - /* **M** - 2G DDR on P1020MBG, map the second 1G */ - SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000, - CFG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 9, BOOKE_PAGESZ_1G, 1), -#endif -#endif /* RAMBOOT/SPL */ - -#ifdef CFG_SYS_INIT_L2_ADDR - /* ***G - L2SRAM */ - SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR, CFG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, - 0, 11, BOOKE_PAGESZ_256K, 1), -#if CONFIG_SYS_L2_SIZE >= (256 << 10) - SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR + 0x40000, - CFG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, - 0, 12, BOOKE_PAGESZ_256K, 1) -#endif -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p2041rdb/Kconfig b/board/freescale/p2041rdb/Kconfig deleted file mode 100644 index 78e11214a5b..00000000000 --- a/board/freescale/p2041rdb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_P2041RDB - -config SYS_BOARD - default "p2041rdb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P2041RDB" - -endif diff --git a/board/freescale/p2041rdb/MAINTAINERS b/board/freescale/p2041rdb/MAINTAINERS deleted file mode 100644 index 2121243e148..00000000000 --- a/board/freescale/p2041rdb/MAINTAINERS +++ /dev/null @@ -1,11 +0,0 @@ -P2041RDB BOARD -M: Priyanka Jain -S: Maintained -F: board/freescale/p2041rdb/ -F: include/configs/P2041RDB.h -F: configs/P2041RDB_defconfig -F: configs/P2041RDB_NAND_defconfig -F: configs/P2041RDB_SDCARD_defconfig -F: configs/P2041RDB_SECURE_BOOT_defconfig -F: configs/P2041RDB_SPIFLASH_defconfig -F: configs/P2041RDB_SRIO_PCIE_BOOT_defconfig diff --git a/board/freescale/p2041rdb/Makefile b/board/freescale/p2041rdb/Makefile deleted file mode 100644 index ebd0982b5db..00000000000 --- a/board/freescale/p2041rdb/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2011 Freescale Semiconductor, Inc. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += p2041rdb.o -obj-y += cpld.o -obj-y += ddr.o -obj-y += eth.o diff --git a/board/freescale/p2041rdb/README b/board/freescale/p2041rdb/README deleted file mode 100644 index ae770277372..00000000000 --- a/board/freescale/p2041rdb/README +++ /dev/null @@ -1,138 +0,0 @@ -Overview -========= -The P2041 Processor combines four Power Architecture processor cores -with high-performance datapath acceleration architecture(DPAA), CoreNet -fabric infrastructure, as well as network and peripheral bus interfaces -required for networking, telecom/datacom, wireless infrastructure, and -military/aerospace applications. - -P2041RDB board is a quad core platform supporting the P2041 processor -of QorIQ DPAA series. - -Boot from NOR flash -=================== -1. Build image - make P2041RDB_config - make all - -2. Program image - => tftp 1000000 u-boot.bin - => protect off all - => erase eff40000 efffffff - => cp.b 1000000 eff40000 c0000 - -3. Program RCW - => tftp 1000000 rcw.bin - => protect off all - => erase e8000000 e801ffff - => cp.b 1000000 e8000000 50 - -4. Program FMAN Firmware ucode - => tftp 1000000 ucode.bin - => protect off all - => erase eff00000 eff3ffff - => cp.b 1000000 eff00000 2000 - -5. Change DIP-switch - SW1[1-5] = 10110 - Note: 1 stands for 'on', 0 stands for 'off' - -Boot from SDCard -=================== -1. Build image - make P2041RDB_SDCARD_config - make all - -2. Generate PBL imge - Use PE tool to produce a image used to be programed to - SDCard which contains RCW and U-Boot image. - -3. Program the PBL image to SDCard - => tftp 1000000 pbl_sd.bin - => mmcinfo - => mmc write 1000000 8 672 - -4. Program FMAN Firmware ucode - => tftp 1000000 ucode.bin - => mmc write 1000000 690 10 - -5. Change DIP-switch - SW1[1-5] = 01100 - Note: 1 stands for 'on', 0 stands for 'off' - -Boot from SPI flash -=================== -1. Build image - make P2041RDB_SPIFLASH_config - make all - -2. Generate PBL imge - Use PE tool to produce a image used to be programed to - SPI flash which contains RCW and U-Boot image. - -3. Program the PBL image to SPI flash - => tftp 1000000 pbl_spi.bin - => spi probe 0 - => sf erase 0 100000 - => sf write 1000000 0 $filesize - -4. Program FMAN Firmware ucode - => tftp 1000000 ucode.bin - => sf erase 110000 10000 - => sf write 1000000 110000 $filesize - -5. Change DIP-switch - SW1[1-5] = 10100 - Note: 1 stands for 'on', 0 stands for 'off' - -Device tree support and how to enable it for different configs --------------------------------------------------------------- -Device tree support is available for p2041rdb for below mentioned boot, -1. NOR Boot -2. NAND Boot -3. SD Boot -4. SPIFLASH Boot - -To enable device tree support for other boot, below configs need to be -enabled in relative defconfig file, -1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required) -2. CONFIG_OF_CONTROL -3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at - CFG_RESET_VECTOR_ADDRESS - 0xffc - -CPLD command -============ -The CPLD is used to control the power sequence and some serdes lane -mux function. - -cpld reset - hard reset to default bank -cpld reset altbank - reset to alternate bank -cpld lane_mux - set multiplexed lane pin - lane 6: 0 -> slot1 (Default) - 1 -> SGMII - lane a: 0 -> slot2 (Default) - 1 -> AURORA - lane c: 0 -> slot2 (Default) - 1 -> SATA0 - lane d: 0 -> slot2 (Default) - 1 -> SATA1 - -Using the Device Tree Source File -================================= -To create the DTB (Device Tree Binary) image file, use a command -similar to this: - dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb - -Or use the following command: - {linux-2.6}/make p2041rdb.dtb ARCH=powerpc - -then the dtb file will be generated under the following directory: - {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb - -Booting Linux -============= -Place a linux uImage in the TFTP disk area. - tftp 1000000 uImage - tftp 2000000 rootfs.ext2.gz.uboot - tftp 3000000 p2041rdb.dtb - bootm 1000000 2000000 3000000 diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c deleted file mode 100644 index 2bba377d4d4..00000000000 --- a/board/freescale/p2041rdb/cpld.c +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/** - * Copyright 2011 Freescale Semiconductor - * Author: Mingkai Hu - * - * This file provides support for the board-specific CPLD used on some Freescale - * reference boards. - * - * The following macros need to be defined: - * - * CPLD_BASE - The virtual address of the base of the CPLD register map - */ - -#include -#include -#include - -#include "cpld.h" - -static u8 __cpld_read(unsigned int reg) -{ - void *p = (void *)CPLD_BASE; - - return in_8(p + reg); -} -u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read"))); - -static void __cpld_write(unsigned int reg, u8 value) -{ - void *p = (void *)CPLD_BASE; - - out_8(p + reg, value); -} -void cpld_write(unsigned int reg, u8 value) - __attribute__((weak, alias("__cpld_write"))); - -/* - * Reset the board. This honors the por_cfg registers. - */ -void __cpld_reset(void) -{ - CPLD_WRITE(system_rst, 1); -} -void cpld_reset(void) __attribute__((weak, alias("__cpld_reset"))); - -/** - * Set the boot bank to the alternate bank - */ -void __cpld_set_altbank(void) -{ - u8 reg5 = CPLD_READ(sw_ctl_on); - - CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE); - CPLD_WRITE(fbank_sel, 1); - CPLD_WRITE(system_rst, 1); -} -void cpld_set_altbank(void) - __attribute__((weak, alias("__cpld_set_altbank"))); - -/** - * Set the boot bank to the default bank - */ -void __cpld_set_defbank(void) -{ - CPLD_WRITE(system_rst_default, 1); -} -void cpld_set_defbank(void) - __attribute__((weak, alias("__cpld_set_defbank"))); - -#ifdef DEBUG -static void cpld_dump_regs(void) -{ - printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); - printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); - printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver)); - printf("system_rst = 0x%02x\n", CPLD_READ(system_rst)); - printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on)); - printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg)); - printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe)); - printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel)); - printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk)); - printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk)); - printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel)); - printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux)); - printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2))); - putc('\n'); -} -#endif - -int cpld_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - int rc = 0; - - if (argc <= 1) - return cmd_usage(cmdtp); - - if (strcmp(argv[1], "reset") == 0) { - if (strcmp(argv[2], "altbank") == 0) - cpld_set_altbank(); - else - cpld_set_defbank(); - } else if (strcmp(argv[1], "lane_mux") == 0) { - u32 lane = hextoul(argv[2], NULL); - u8 val = (u8)hextoul(argv[3], NULL); - u8 reg = CPLD_READ(serdes_mux); - - switch (lane) { - case 0x6: - reg &= ~SERDES_MUX_LANE_6_MASK; - reg |= val << SERDES_MUX_LANE_6_SHIFT; - break; - case 0xa: - reg &= ~SERDES_MUX_LANE_A_MASK; - reg |= val << SERDES_MUX_LANE_A_SHIFT; - break; - case 0xc: - reg &= ~SERDES_MUX_LANE_C_MASK; - reg |= val << SERDES_MUX_LANE_C_SHIFT; - break; - case 0xd: - reg &= ~SERDES_MUX_LANE_D_MASK; - reg |= val << SERDES_MUX_LANE_D_SHIFT; - break; - default: - printf("Invalid value\n"); - break; - } - - CPLD_WRITE(serdes_mux, reg); -#ifdef DEBUG - } else if (strcmp(argv[1], "dump") == 0) { - cpld_dump_regs(); -#endif - } else - rc = cmd_usage(cmdtp); - - return rc; -} - -U_BOOT_CMD( - cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd, - "Reset the board or pin mulexing selection using the CPLD sequencer", - "reset - hard reset to default bank\n" - "cpld_cmd reset altbank - reset to alternate bank\n" - "cpld_cmd lane_mux - set multiplexed lane pin\n" - " lane 6: 0 -> slot1\n" - " 1 -> SGMII (Default)\n" - " lane a: 0 -> slot2\n" - " 1 -> AURORA (Default)\n" - " lane c: 0 -> slot2\n" - " 1 -> SATA0 (Default)\n" - " lane d: 0 -> slot2\n" - " 1 -> SATA1 (Default)\n" -#ifdef DEBUG - "cpld_cmd dump - display the CPLD registers\n" -#endif - ); diff --git a/board/freescale/p2041rdb/cpld.h b/board/freescale/p2041rdb/cpld.h deleted file mode 100644 index 8c90c1ccf32..00000000000 --- a/board/freescale/p2041rdb/cpld.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/** - * Copyright 2011 Freescale Semiconductor - * Author: Mingkai Hu - * - * This file provides support for the ngPIXIS, a board-specific FPGA used on - * some Freescale reference boards. - */ - -/* - * CPLD register set. Feel free to add board-specific #ifdefs where necessary. - */ -typedef struct cpld_data { - u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ - u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ - u8 pcba_ver; /* 0x2 - PCBA Revision Register */ - u8 system_rst; /* 0x3 - system reset register */ - u8 res0; /* 0x4 - not used */ - u8 sw_ctl_on; /* 0x5 - Switch Control Enable Register */ - u8 por_cfg; /* 0x6 - POR Control Register */ - u8 switch_strobe; /* 0x7 - Multiplexed pin Select Register */ - u8 jtag_sel; /* 0x8 - JTAG or AURORA Selection */ - u8 sdbank1_clk; /* 0x9 - SerDes Bank1 Reference clock */ - u8 sdbank2_clk; /* 0xa - SerDes Bank2 Reference clock */ - u8 fbank_sel; /* 0xb - Flash bank selection */ - u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */ - u8 sw[1]; /* 0xd - SW2 Status */ - u8 system_rst_default; /* 0xe - system reset to default register */ - u8 sysclk_sw1; /* 0xf - sysclk configuration register */ -} __attribute__ ((packed)) cpld_data_t; - -#define SERDES_MUX_LANE_6_MASK 0x2 -#define SERDES_MUX_LANE_6_SHIFT 1 -#define SERDES_MUX_LANE_A_MASK 0x1 -#define SERDES_MUX_LANE_A_SHIFT 0 -#define SERDES_MUX_LANE_C_MASK 0x4 -#define SERDES_MUX_LANE_C_SHIFT 2 -#define SERDES_MUX_LANE_D_MASK 0x8 -#define SERDES_MUX_LANE_D_SHIFT 3 -#define CPLD_SWITCH_BANK_ENABLE 0x40 -#define CPLD_SYSCLK_83 0x1 /* system clock 83.3MHz */ -#define CPLD_SYSCLK_100 0x2 /* system clock 100MHz */ - -/* Pointer to the CPLD register set */ -#define cpld ((cpld_data_t *)CPLD_BASE) - -/* The CPLD SW register that corresponds to board switch X, where x >= 1 */ -#define CPLD_SW(x) (cpld->sw[(x) - 2]) - -u8 cpld_read(unsigned int reg); -void cpld_write(unsigned int reg, u8 value); - -#define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg)) -#define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value) diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c deleted file mode 100644 index b8b765a85ef..00000000000 --- a/board/freescale/p2041rdb/ddr.c +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2011 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 clk_adjust; - u32 wrlvl_start; - u32 cpo; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - * - * ranges for parameters: - * wr_data_delay = 0-6 - * clk adjust = 0-8 - * cpo 2-0x1E (30) - */ -static const struct board_specific_parameters dimm0[] = { - /* - * memory controller 0 - * num| hi| clk| wrlvl | cpo |wrdata|2T - * ranks| mhz|adjst| start | delay| - */ - {2, 750, 3, 5, 0xff, 2, 0}, - {2, 1250, 4, 6, 0xff, 2, 0}, - {2, 1350, 5, 7, 0xff, 2, 0}, - {2, 1666, 5, 8, 0xff, 2, 0}, - {} -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num) { - printf("Wrong parameter for controller number %d", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - pbsp = dimm0; - - /* - * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->twot_en = pbsp->force_2t; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found " - "for data rate %lu MT/s!\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->twot_en = pbsp_highest->force_2t; - } else { - panic("DIMM is not supported by this board"); - } - -found: - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - /* Write leveling override */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* Rtt and Rtt_WR override */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 60 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN; -} - -int dram_init(void) -{ - phys_size_t dram_size = 0; - - puts("Initializing...."); - - if (fsl_use_spd()) { - puts("using SPD\n"); - dram_size = fsl_ddr_sdram(); - } else { - puts("no SPD and fixed parameters\n"); - return -ENXIO; - } - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - debug(" DDR: "); - gd->ram_size = dram_size; - - return 0; -} diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c deleted file mode 100644 index 65850866777..00000000000 --- a/board/freescale/p2041rdb/eth.c +++ /dev/null @@ -1,210 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Author: Mingkai Hu - */ - -/* - * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs - * are provided by the three on-board PHY or by the standard Freescale - * four-port SGMII riser card. We need to change the phy-handle in the - * kernel dts file to point to the correct PHY according to serdes mux - * and serdes protocol selection. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpld.h" -#include "../common/fman.h" - -#ifdef CONFIG_FMAN_ENET -/* - * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means - * that the mapping must be determined dynamically, or that the lane maps to - * something other than a board slot - */ -static u8 lane_to_slot[] = { - 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0 -}; - -static int riser_phy_addr[] = { - CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, - CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, - CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, - CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, -}; - -/* - * Initialize the lane_to_slot[] array. - * - * On the P2040RDB board the mapping is controlled by CPLD register. - */ -static void initialize_lane_to_slot(void) -{ - u8 mux = CPLD_READ(serdes_mux); - - lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1; - lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2; - lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2; - lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2; -} - -/* - * Given the following ... - * - * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' - * compatible string and 'addr' physical address) - * - * 2) An Fman port - * - * ... update the phy-handle property of the Ethernet node to point to the - * right PHY. This assumes that we already know the PHY for each port. - * - * The offset of the Fman Ethernet node is also passed in for convenience, but - * it is not used, and we recalculate the offset anyway. - * - * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. - * Inside the Fman, "ports" are things that connect to MACs. We only call them - * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs - * and ports are the same thing. - * - */ -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - phy_interface_t intf = fm_info_get_enet_if(port); - char phy[16]; - int lane; - u8 slot; - - switch (intf) { - /* The RGMII PHY is identified by the MAC connected to it */ - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1); - fdt_set_phy_handle(fdt, compat, addr, phy); - break; - /* The SGMII PHY is identified by the MAC connected to it */ - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); - if (lane < 0) - return; - slot = lane_to_slot[lane]; - if (slot) { - sprintf(phy, "phy_sgmii_%x", - CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR - + (port - FM1_DTSEC1)); - fdt_set_phy_handle(fdt, compat, addr, phy); - } else { - sprintf(phy, "phy_sgmii_%x", - CFG_SYS_FM1_DTSEC1_PHY_ADDR - + (port - FM1_DTSEC1)); - fdt_set_phy_handle(fdt, compat, addr, phy); - } - break; - case PHY_INTERFACE_MODE_XGMII: - /* XAUI */ - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - /* The XAUI PHY is identified by the slot */ - sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); - fdt_set_phy_handle(fdt, compat, addr, phy); - } - break; - default: - break; - } -} -#endif /* #ifdef CONFIG_FMAN_ENET */ - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct fsl_pq_mdio_info dtsec_mdio_info; - struct tgec_mdio_info tgec_mdio_info; - unsigned int i, slot; - int lane; - - printf("Initializing Fman\n"); - - initialize_lane_to_slot(); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CFG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct tgec_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the real 10G MDIO bus */ - fm_tgec_mdio_init(bis, &tgec_mdio_info); - - /* - * Program the three on-board SGMII PHY addresses. If the SGMII Riser - * card used, we'll override the PHY address later. For any DTSEC that - * is RGMII, we'll also override its PHY address later. We assume that - * DTSEC4 and DTSEC5 are used for RGMII. - */ - fm_info_set_phy_address(FM1_DTSEC1, CFG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CFG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, CFG_SYS_FM1_DTSEC3_PHY_ADDR); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - if (slot) - fm_info_set_phy_address(i, riser_phy_addr[i]); - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ - fm_info_set_phy_address(i, i == FM1_DTSEC5 ? - CFG_SYS_FM1_DTSEC5_PHY_ADDR : - CFG_SYS_FM1_DTSEC4_PHY_ADDR); - break; - default: - printf("Fman1: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - break; - } - - fm_info_set_mdio(i, - miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); - } - - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - slot = lane_to_slot[lane]; - if (slot) - fm_info_set_phy_address(FM1_10GEC1, - CFG_SYS_FM1_10GEC1_PHY_ADDR); - } - - fm_info_set_mdio(FM1_10GEC1, - miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c deleted file mode 100644 index d5b71f78430..00000000000 --- a/board/freescale/p2041rdb/p2041rdb.c +++ /dev/null @@ -1,248 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011,2012 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern void pci_of_setup(void *blob, struct bd_info *bd); - -#include "cpld.h" - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - u8 sw; - struct cpu_type *cpu = gd->arch.cpu; - unsigned int i; - - printf("Board: %sRDB, ", cpu->name); - printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver), - CPLD_READ(cpld_ver_sub)); - - sw = CPLD_READ(fbank_sel); - printf("vBank: %d\n", sw & 0x1); - - /* - * Display the actual SERDES reference clocks as configured by the - * dip switches on the board. Note that the SWx registers could - * technically be set to force the reference clocks to match the - * values that the SERDES expects (or vice versa). For now, however, - * we just display both values and hope the user notices when they - * don't match. - */ - puts("SERDES Reference Clocks: "); - sw = in_8(&CPLD_SW(2)) >> 2; - for (i = 0; i < 2; i++) { - static const char * const freq[][3] = {{"0", "100", "125"}, - {"100", "156.25", "125"} - }; - unsigned int clock = (sw >> (2 * i)) & 3; - - printf("Bank%u=%sMhz ", i+1, freq[i][clock]); - } - puts("\n"); - - return 0; -} - -int board_early_init_f(void) -{ - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - - /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */ - setbits_be32(&gur->ddrclkdr, 0x000f000f); - - return 0; -} - -#define CPLD_LANE_A_SEL 0x1 -#define CPLD_LANE_G_SEL 0x2 -#define CPLD_LANE_C_SEL 0x4 -#define CPLD_LANE_D_SEL 0x8 - -void board_config_lanes_mux(void) -{ - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; - int srds_prtcl = (in_be32(&gur->rcwsr[4]) & - FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; - - u8 mux = 0; - switch (srds_prtcl) { - case 0x2: - case 0x5: - case 0x9: - case 0xa: - case 0xf: - break; - case 0x8: - mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; - break; - case 0x14: - mux |= CPLD_LANE_A_SEL; - break; - case 0x17: - mux |= CPLD_LANE_G_SEL; - break; - case 0x16: - case 0x19: - case 0x1a: - mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; - break; - case 0x1c: - mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL; - break; - default: - printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl); - break; - } - CPLD_WRITE(serdes_mux, mux); -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CFG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - board_config_lanes_mux(); - - return 0; -} - -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = CPLD_READ(sysclk_sw1); - - switch (sysclk_conf & 0x7) { - case CPLD_SYSCLK_83: - return 83333333; - case CPLD_SYSCLK_100: - return 100000000; - default: - return 66666666; - } -} - -#define NUM_SRDS_BANKS 2 - -int misc_init_r(void) -{ - serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; - u32 actual[NUM_SRDS_BANKS]; - unsigned int i; - u8 sw; - static const int freq[][3] = { - {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125}, - {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25, - SRDS_PLLCR0_RFCK_SEL_125} - }; - - sw = in_8(&CPLD_SW(2)) >> 2; - for (i = 0; i < NUM_SRDS_BANKS; i++) { - unsigned int clock = (sw >> (2 * i)) & 3; - if (clock == 0x3) { - printf("Warning: SDREFCLK%u switch setting of '11' is " - "unsupported\n", i + 1); - break; - } - if (i == 0 && clock == 0) - puts("Warning: SDREFCLK1 switch setting of" - "'00' is unsupported\n"); - else - actual[i] = freq[i][clock]; - - /* - * PC board uses a different CPLD with PB board, this CPLD - * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB - * board has cpld_ver_sub = 0, and pcba_ver = 4. - */ - if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) && - (CPLD_READ(pcba_ver) == 5)) { - /* PC board bank2 frequency */ - actual[i] = freq[i-1][clock]; - } - } - - for (i = 0; i < NUM_SRDS_BANKS; i++) { - u32 expected = in_be32(®s->bank[i].pllcr0); - expected &= SRDS_PLLCR0_RFCK_SEL_MASK; - if (expected != actual[i]) { - printf("Warning: SERDES bank %u expects reference clock" - " %sMHz, but actual is %sMHz\n", i + 1, - serdes_clock_to_string(expected), - serdes_clock_to_string(actual[i])); - } - } - - return 0; -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#if defined(CONFIG_HAS_FSL_DR_USB) - fsl_fdt_fixup_dr_usb(blob, bd); -#endif - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif -#endif - - return 0; -} diff --git a/board/freescale/p2041rdb/pbi.cfg b/board/freescale/p2041rdb/pbi.cfg deleted file mode 100644 index 75dfc321626..00000000000 --- a/board/freescale/p2041rdb/pbi.cfg +++ /dev/null @@ -1,33 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2012 Freescale Semiconductor, Inc. -# Refer doc/README.pblimage for more details about how-to configure -# and create PBL boot image -# - -#PBI commands -#Initialize CPC1 as 1MB SRAM -09010000 00200400 -09138000 00000000 -091380c0 00000100 -09010100 00000000 -09010104 fff0000b -09010f00 08000000 -09010000 80000000 -#Configure LAW for CPC1 -09000d00 00000000 -09000d04 fff00000 -09000d08 81000013 -09000010 00000000 -09000014 ff000000 -09000018 81000000 -#Initialize eSPI controller, default configuration is slow for eSPI to -#load data, this configuration comes from u-boot eSPI driver. -09110000 80000403 -09110020 2d170008 -09110024 00100008 -09110028 00100008 -0911002c 00100008 -#Flush PBL data -09138000 00000000 -091380c0 00000000 diff --git a/board/freescale/p2041rdb/rcw_p2041rdb.cfg b/board/freescale/p2041rdb/rcw_p2041rdb.cfg deleted file mode 100644 index 8df19dd3fe4..00000000000 --- a/board/freescale/p2041rdb/rcw_p2041rdb.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for P2041RDB. -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -12600000 00000000 241C0000 00000000 -649FA0C1 C3C02000 58000000 40000000 -00000000 00000000 00000000 D0030F07 -00000000 00000000 00000000 00000000 diff --git a/board/freescale/t102xrdb/Kconfig b/board/freescale/t102xrdb/Kconfig deleted file mode 100644 index d538386d434..00000000000 --- a/board/freescale/t102xrdb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_T1023RDB || TARGET_T1024RDB - -config SYS_BOARD - default "t102xrdb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "T102xRDB" - -endif diff --git a/board/freescale/t102xrdb/MAINTAINERS b/board/freescale/t102xrdb/MAINTAINERS deleted file mode 100644 index df1f0bed939..00000000000 --- a/board/freescale/t102xrdb/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -T102XRDB BOARD -M: Priyanka Jain -S: Maintained -F: board/freescale/t102xrdb/ -F: include/configs/T102xRDB.h -F: configs/T1024RDB_defconfig -F: configs/T1024RDB_NAND_defconfig -F: configs/T1024RDB_SDCARD_defconfig -F: configs/T1024RDB_SPIFLASH_defconfig diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile deleted file mode 100644 index b0f27c47191..00000000000 --- a/board/freescale/t102xrdb/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright 2014 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_XPL_BUILD -obj-y += spl.o -else -obj-y += t102xrdb.o -obj-$(CONFIG_TARGET_T1024RDB) += cpld.o -obj-y += eth_t102xrdb.o -endif -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README deleted file mode 100644 index de170f52b4d..00000000000 --- a/board/freescale/t102xrdb/README +++ /dev/null @@ -1,340 +0,0 @@ -T1024 SoC Overview ------------------- -The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor -combines two or one 64-bit Power Architecture e5500 core respectively with high -performance datapath acceleration logic, and network peripheral bus interfaces -required for networking and telecommunications. This processor can be used in -applications such as enterprise WLAN access points, routers, switches, firewall -and other packet processing intensive small enterprise and branch office appliances, -and general-purpose embedded computing. Its high level of integration offers -significant performance benefits and greatly helps to simplify board design. - - -The T1024 SoC includes the following function and features: -- two e5500 cores, each with a private 256 KB L2 cache - - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant) - - Three levels of instructions: User, supervisor, and hypervisor - - Independent boot and reset - - Secure boot capability -- 256 KB shared L3 CoreNet platform cache (CPC) -- Interconnect CoreNet platform - - CoreNet coherency manager supporting coherent and noncoherent transactions - with prioritization and bandwidth allocation amongst CoreNet endpoints - - 150 Gbps coherent read bandwidth -- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support -- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - - Packet parsing, classification, and distribution - - Queue management for scheduling, packet sequencing, and congestion management - - Cryptography Acceleration (SEC 5.x) - - IEEE 1588 support - - Hardware buffer management for buffer allocation and deallocation - - MACSEC on DPAA-based Ethernet ports -- Ethernet interfaces - - Four 1 Gbps Ethernet controllers -- Parallel Ethernet interfaces - - Two RGMII interfaces -- High speed peripheral interfaces - - Three PCI Express 2.0 controllers/ports running at up to 5 GHz - - One SATA controller supporting 1.5 and 3.0 Gb/s operation - - One QSGMII interface - - Four SGMII interface supporting 1000 Mbps - - Three SGMII interfaces supporting up to 2500 Mbps - - 10GBase-R or 10Base-KR interface -- Additional peripheral interfaces - - Two USB 2.0 controllers with integrated PHY - - SD/eSDHC/eMMC - - eSPI controller - - Four I2C controllers - - Four UARTs - - Four GPIO controllers - - Integrated flash controller (IFC) - - LCD interface (DIU) with 12 bit dual data rate -- Multicore programmable interrupt controller (PIC) -- Two 8-channel DMA engines -- Single source clocking implementation -- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) -- QUICC Engine block - - 32-bit RISC controller for flexible support of the communications peripherals - - Serial DMA channel for receive and transmit on all serial channels - - Two universal communication controllers, supporting TDM, HDLC, and UART - -T1023 Personality ------------------- -T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and -unavailable deep sleep. Rest of the blocks are almost same as T1024. -Differences between T1024 and T1023 -Feature T1024 T1023 -QUICC Engine: yes no -DIU: yes no -Deep Sleep: yes no -I2C controller: 4 3 -DDR: 64-bit 32-bit -IFC: 32-bit 28-bit -Package: 23x23 19x19 - - -T1024RDB board Overview ------------------------ - - Ethernet - - Two on-board 10M/100M/1G bps RGMII ethernet ports - - One on-board 10G bps Base-T port. - - DDR Memory - - Supports 64-bit 4GB DDR3L DIMM - - PCIe - - One on-board PCIe slot. - - Two on-board PCIe Mini-PCIe connectors. - - IFC/Local Bus - - NOR: 128MB 16-bit NOR Flash - - NAND: 1GB 8-bit NAND flash - - CPLD: for system controlling with programable header on-board - - USB - - Supports two USB 2.0 ports with integrated PHYs - - Two type A ports with 5V@1.5A per port. - - SDHC - - one SD connector supporting 1.8V/3.3V via J53. - - SPI - - On-board 64MB SPI flash - - Other - - Two Serial ports - - Four I2C ports - - -T1023RDB board Overview ------------------------ -- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz -- CoreNet fabric supporting coherent and noncoherent transactions with - prioritization and bandwidth allocation -- SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC -- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC -- Ethernet interfaces: - - one 1G RGMII port on-board(RTL8211FS PHY) - - one 1G SGMII port on-board(RTL8211FS PHY) - - one 2.5G SGMII port on-board(AQR105 PHY) -- PCIe: Two Mini-PCIe connectors on-board. -- SerDes: 4 lanes up to 10.3125GHz -- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash -- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash -- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash. -- USB: one Type-A USB 2.0 port with internal PHY -- eSDHC: support SD/MMC and eMMC card -- 256Kbit M24256 I2C EEPROM -- RTC: Real-time clock DS1339U on I2C bus -- UART: one serial port on-board with RJ45 connector -- Debugging: JTAG/COP for T1023 debugging - - -Memory map on T1024RDB ----------------------- -Start Address End Address Description Size -0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB -0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB -0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB -0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB -0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB -0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB -0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB -0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB -0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB -0xF_0000_0000 0xF_003F_FFFF DCSR 4MB -0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB -0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB -0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB -0x0_0000_0000 0x0_ffff_ffff DDR 4GB - - -128MB NOR Flash Memory Layout ------------------------------ -Start Address End Address Definition Max size -0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB -0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB -0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB -0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB -0xED300000 0xEFDFFFFF rootfs (alt bank) 44MB -0xED000000 0xED2FFFFF Guest image #3 (alternate bank) 3MB -0xECD00000 0xECFFFFFF Guest image #2 (alternate bank) 3MB -0xECA00000 0xECCFFFFF Guest image #1 (alternate bank) 3MB -0xEC900000 0xEC9FFFFF HV config device tree(alt bank) 1MB -0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB -0xEC700000 0xEC7FFFFF HV.uImage (alternate bank) 1MB -0xEC020000 0xEC6FFFFF Linux.uImage (alt bank) ~7MB -0xEC000000 0xEC01FFFF RCW (alt bank) 128KB -0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB -0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB -0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB -0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB -0xE9300000 0xEBDFFFFF rootfs (current bank) 44MB -0xE9000000 0xE92FFFFF Guest image #3 (current bank) 3MB -0xE8D00000 0xE8FFFFFF Guest image #2 (current bank) 3MB -0xE8A00000 0xE8CFFFFF Guest image #1 (current bank) 3MB -0xE8900000 0xE89FFFFF HV config device tree(cur bank) 1MB -0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB -0xE8700000 0xE87FFFFF HV.uImage (current bank) 1MB -0xE8020000 0xE86FFFFF Linux.uImage (current bank) ~7MB -0xE8000000 0xE801FFFF RCW (current bank) 128KB - - -T1024/T1023 Clock frequency ---------------------------- -BIN Core DDR Platform FMan -Bin1: 1400MHz 1600MT/s 400MHz 700MHz -Bin2: 1200MHz 1600MT/s 400MHz 600MHz -Bin3: 1000MHz 1600MT/s 400MHz 500MHz - - -Software configurations and board settings ------------------------------------------- -1. NOR boot: - a. build NOR boot image - $ make T1024RDB_defconfig - $ make - b. program u-boot.bin image to NOR flash - => tftp 1000000 u-boot.bin - => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize - on T1024RDB: - set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot - on T1023RDB: - set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot - - Switching between default bank0 and alternate bank4 on NOR flash - To change boot source to vbank4: - on T1024RDB: - via software: run command 'cpld reset altbank' in U-Boot. - via DIP-switch: set SW3[5:7] = '100' - on T1023RDB: - via software: run command 'switch bank4' in U-Boot. - via DIP-switch: set SW3[5:7] = '100' - - To change boot source to vbank0: - on T1024RDB: - via software: run command 'cpld reset' in U-Boot. - via DIP-Switch: set SW3[5:7] = '000' - on T1023RDB: - via software: run command 'switch bank0' in U-Boot. - via DIP-switch: set SW3[5:7] = '000' - -2. NAND Boot: - a. build PBL image for NAND boot - $ make T1024RDB_NAND_defconfig - $ make - b. program u-boot-with-spl-pbl.bin to NAND flash - => tftp 1000000 u-boot-with-spl-pbl.bin - => nand erase 0 $filesize - => nand write 1000000 0 $filesize - set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot - -3. SPI Boot: - a. build PBL image for SPI boot - $ make T1024RDB_SPIFLASH_defconfig - $ make - b. program u-boot-with-spl-pbl.bin to SPI flash - => tftp 1000000 u-boot-with-spl-pbl.bin - => sf probe 0 - => sf erase 0 100000 - => sf write 1000000 0 $filesize - => tftp 1000000 fsl_fman_ucode_t1024_xx.bin - => sf erase 100000 100000 - => sf write 1000000 110000 20000 - set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot - -4. SD Boot: - a. build PBL image for SD boot - $ make T1024RDB_SDCARD_defconfig - $ make - b. program u-boot-with-spl-pbl.bin to SD/MMC card - => tftp 1000000 u-boot-with-spl-pbl.bin - => mmc write 1000000 8 0x7f0 - => tftp 1000000 fsl_fman_ucode_t1024_xx.bin - => mmc write 1000000 0x820 80 - set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot - - SW3[3] = '1' for SD card(or 'switch sd' by software) - SW3[3] = '0' for eMMC (or 'switch emmc' by software) - - -device tree support and how to enable it for different configs --------------------------------------------------------------- -device tree support is available for t1024rdb for below mentioned boot, -1. nor boot -2. nand boot -3. sd boot -4. spiflash boot - -to enable device tree support for other boot, below configs need to be -enabled in relative defconfig file, -1. config_default_device_tree="t1024rdb" (change default device tree name if required) -2. config_of_control -3. config_mpc85xx_have_reset_vector if reset vector is located at - config_reset_vector_address - 0xffc - -if device tree support is enabled in defconfig, -1. use 'u-boot.bin' for nor boot. -2. use 'u-boot-with-spl-pbl.bin' for other boot. - -2-stage NAND/SPI/SD boot loader -------------------------------- -PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. -SPL further initializes DDR using SPD and environment variables -and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR. -Finally SPL transers control to U-Boot for futher booting. - -SPL has following features: - - Executes within 256K - - No relocation required - -Run time view of SPL framework -------------------------------------------------- -|Area | Address | -------------------------------------------------- -|SecureBoot header | 0xFFFC0000 (32KB) | -------------------------------------------------- -|GD, BD | 0xFFFC8000 (4KB) | -------------------------------------------------- -|ENV | 0xFFFC9000 (8KB) | -------------------------------------------------- -|HEAP | 0xFFFCB000 (30KB) | -------------------------------------------------- -|STACK | 0xFFFD8000 (22KB) | -------------------------------------------------- -|U-Boot SPL | 0xFFFD8000 (160KB) | -------------------------------------------------- - -NAND Flash memory Map on T1024RDB -------------------------------------------------------------- -Start End Definition Size -0x000000 0x0FFFFF U-Boot 1MB(2 block) -0x100000 0x17FFFF U-Boot env 512KB(1 block) -0x180000 0x1FFFFF FMAN Ucode 512KB(1 block) -0x200000 0x27FFFF QE Firmware 512KB(1 block) - - -NAND Flash memory Map on T1023RDB ----------------------------------------------------- -Start End Definition Size -0x000000 0x0FFFFF U-Boot 1MB -0x100000 0x15FFFF U-Boot env 8KB -0x160000 0x17FFFF FMAN Ucode 128KB - - -SD Card memory Map on T102xRDB ----------------------------------------------------- -Block #blocks Definition Size -0x008 2048 U-Boot img 1MB -0x800 0016 U-Boot env 8KB -0x820 0256 FMAN Ucode 128KB -0x920 0256 QE Firmware 128KB(only T1024RDB) - - -64MB SPI Flash memory Map on T102xRDB ----------------------------------------------------- -Start End Definition Size -0x000000 0x0FFFFF U-Boot img 1MB -0x100000 0x101FFF U-Boot env 8KB -0x110000 0x12FFFF FMAN Ucode 128KB -0x130000 0x14FFFF QE Firmware 128KB(only T1024RDB) -0x300000 0x3FFFFF device tree 128KB -0x400000 0x9FFFFF Linux kernel 6MB -0xa00000 0x3FFFFFF rootfs 54MB - - -For more details, please refer to T1024RDB/T1023RDB User Guide -and Freescale QorIQ SDK Infocenter document. diff --git a/board/freescale/t102xrdb/cpld.c b/board/freescale/t102xrdb/cpld.c deleted file mode 100644 index 00ea9d8f503..00000000000 --- a/board/freescale/t102xrdb/cpld.c +++ /dev/null @@ -1,103 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/** - * Copyright 2014 Freescale Semiconductor - * - * Freescale T1024RDB board-specific CPLD controlling supports. - * - * The following macros need to be defined: - */ - -#include -#include -#include -#include -#include "cpld.h" - -u8 cpld_read(unsigned int reg) -{ - void *p = (void *)CFG_SYS_CPLD_BASE; - - return in_8(p + reg); -} - -void cpld_write(unsigned int reg, u8 value) -{ - void *p = (void *)CFG_SYS_CPLD_BASE; - - out_8(p + reg, value); -} - -/** - * Set the boot bank to the alternate bank - */ -void cpld_set_altbank(void) -{ - u8 reg = CPLD_READ(flash_csr); - - reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; - - CPLD_WRITE(flash_csr, reg); - CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); -} - -/** - * Set the boot bank to the default bank - */ -void cpld_set_defbank(void) -{ - u8 reg = CPLD_READ(flash_csr); - - reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; - - CPLD_WRITE(flash_csr, reg); - CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); -} - -static void cpld_dump_regs(void) -{ - printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); - printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); - printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); - printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); - printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); - printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); - printf("int_status = 0x%02x\n", CPLD_READ(int_status)); - printf("flash_csr = 0x%02x\n", CPLD_READ(flash_csr)); - printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status)); - printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status)); - printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status)); - printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status)); - printf("boot_override = 0x%02x\n", CPLD_READ(boot_override)); - printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1)); - printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2)); - putc('\n'); -} - -int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - int rc = 0; - - if (argc <= 1) - return cmd_usage(cmdtp); - - if (strcmp(argv[1], "reset") == 0) { - if (strcmp(argv[2], "altbank") == 0) - cpld_set_altbank(); - else - cpld_set_defbank(); - } else if (strcmp(argv[1], "dump") == 0) { - cpld_dump_regs(); - } else { - rc = cmd_usage(cmdtp); - } - - return rc; -} - -U_BOOT_CMD( - cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, - "Reset the board or alternate bank", - "reset - hard reset to default bank\n" - "cpld reset altbank - reset to alternate bank\n" - "cpld dump - display the CPLD registers\n" - ); diff --git a/board/freescale/t102xrdb/cpld.h b/board/freescale/t102xrdb/cpld.h deleted file mode 100644 index b504c3fcc47..00000000000 --- a/board/freescale/t102xrdb/cpld.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/** - * Copyright 2014 Freescale Semiconductor - * - */ - -struct cpld_data { - u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */ - u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */ - u8 hw_ver; /* 0x02 - Hardware Revision Register */ - u8 sw_ver; /* 0x03 - Software Revision register */ - u8 res0[12]; /* 0x04 - 0x0F - not used */ - u8 reset_ctl1; /* 0x10 - Reset control Register1 */ - u8 reset_ctl2; /* 0x11 - Reset control Register2 */ - u8 int_status; /* 0x12 - Interrupt status Register */ - u8 flash_csr; /* 0x13 - Flash control and status register */ - u8 fan_ctl_status; /* 0x14 - Fan control and status register */ - u8 led_ctl_status; /* 0x15 - LED control and status register */ - u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ - u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ - u8 boot_override; /* 0x18 - Boot override register */ - u8 boot_config1; /* 0x19 - Boot config override register*/ - u8 boot_config2; /* 0x1A - Boot config override register*/ -}; - -/* Pointer to the CPLD register set */ - -u8 cpld_read(unsigned int reg); -void cpld_write(unsigned int reg, u8 value); - -#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) -#define CPLD_WRITE(reg, value)\ - cpld_write(offsetof(struct cpld_data, reg), value) - -/* CPLD on IFC */ -#define CPLD_LBMAP_MASK 0x3F -#define CPLD_BANK_SEL_MASK 0x07 -#define CPLD_BANK_OVERRIDE 0x40 -#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ -#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */ -#define CPLD_LBMAP_RESET 0xFF -#define CPLD_LBMAP_SHIFT 0x03 -#define CPLD_BOOT_SEL 0x80 - -#define CPLD_PCIE_SGMII_MUX 0x80 -#define CPLD_OVERRIDE_BOOT_EN 0x01 -#define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override enable */ diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c deleted file mode 100644 index 1a8a131cdcc..00000000000 --- a/board/freescale/t102xrdb/ddr.c +++ /dev/null @@ -1,258 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * datarate_mhz_high values need to be in ascending order - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | - */ - {2, 833, 0, 8, 6, 0x06060607, 0x08080807,}, - {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, - {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, - {1, 833, 0, 8, 6, 0x06060607, 0x08080807,}, - {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, - {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - struct cpu_type *cpu = gd->arch.cpu; - - if (ctrl_num > 1) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - pbsp = udimms[0]; - - /* Get clk_adjust according to the board ddr freqency and n_banks - * specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks && - (pdimm->rank_density >> 30) >= pbsp->rank_gb) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found\n"); - printf("for data rate %lu MT/s\n", ddr_freq); - printf("Trying to use the highest speed (%u) parameters\n", - pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); - debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ", - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2); - debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3); - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * rtt and rtt_wr override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF); - - /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit, - * force DDR bus width to 32bit for T1023 - */ - if (cpu->soc_ver == SVR_T1023) - popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; - -#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32 - /* for DDR bus 32bit test on T1024 */ - popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; -#endif - -#ifdef CONFIG_TARGET_T1023RDB - popts->wrlvl_ctl_2 = 0x07070606; - popts->half_strength_driver_enable = 1; - popts->cpo_sample = 0x43; -#elif defined(CONFIG_TARGET_T1024RDB) - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x52; -#endif -} - -#ifdef CONFIG_SYS_DDR_RAW_TIMING -/* 2GB discrete DDR4 MT40A512M8HX on T1023RDB */ -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 0x80000000, - .capacity = 0x80000000, - .primary_sdram_width = 32, - .ec_sdram_width = 8, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 15, - .n_col_addr = 10, - .bank_addr_bits = 2, - .bank_group_bits = 2, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - .tckmin_x_ps = 938, - .tckmax_ps = 1500, - .caslat_x = 0x000DFA00, - .taa_ps = 13500, - .trcd_ps = 13500, - .trp_ps = 13500, - .tras_ps = 33000, - .trc_ps = 46500, - .trfc1_ps = 260000, - .trfc2_ps = 160000, - .trfc4_ps = 110000, - .tfaw_ps = 25000, - .trrds_ps = 3700, - .trrdl_ps = 5300, - .tccdl_ps = 5355, - .refresh_rate_ps = 7800000, - .dq_mapping[0] = 0x0, - .dq_mapping[1] = 0x0, - .dq_mapping[2] = 0x0, - .dq_mapping[3] = 0x0, - .dq_mapping[4] = 0x0, - .dq_mapping[5] = 0x0, - .dq_mapping[6] = 0x0, - .dq_mapping[7] = 0x0, - .dq_mapping[8] = 0x0, - .dq_mapping[9] = 0x0, - .dq_mapping[10] = 0x0, - .dq_mapping[11] = 0x0, - .dq_mapping[12] = 0x0, - .dq_mapping[13] = 0x0, - .dq_mapping[14] = 0x0, - .dq_mapping[15] = 0x0, - .dq_mapping[16] = 0x0, - .dq_mapping[17] = 0x0, - .dq_mapping_ors = 1, -}; - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - const char dimm_model[] = "Fixed DDR4 on board"; - - if (((controller_number == 0) && (dimm_number == 0)) || - ((controller_number == 1) && (dimm_number == 0))) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} -#endif - -#if defined(CONFIG_DEEP_SLEEP) -void board_mem_sleep_setup(void) -{ - void __iomem *cpld_base = (void *)CFG_SYS_CPLD_BASE; - - /* does not provide HW signals for power management */ - clrbits_8(cpld_base + 0x17, 0x40); - /* Disable MCKE isolation */ - gpio_set_value(2, 0); - udelay(1); -} -#endif - -int dram_init(void) -{ - phys_size_t dram_size; - -#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) -#ifndef CONFIG_SYS_DDR_RAW_TIMING - puts("Initializing....using SPD\n"); -#endif - dram_size = fsl_ddr_sdram(); -#else - /* DDR has been initialised by first stage boot loader */ - dram_size = fsl_ddr_sdram_size(); -#endif - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - -#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD) - fsl_dp_resume(); -#endif - - gd->ram_size = dram_size; - - return 0; -} diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c deleted file mode 100644 index 7185a0abd52..00000000000 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * Shengzhou Liu - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Set the on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); - - switch (srds_s1) { -#ifdef CONFIG_TARGET_T1024RDB - case 0x95: - /* set the on-board RGMII2 PHY */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); - - /* set 10GBase-R with Aquantia AQR105 PHY */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - break; -#endif - case 0x6a: - case 0x6b: - case 0x77: - case 0x135: - /* set the on-board 2.5G SGMII AQR105 PHY */ - fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR); -#ifdef CONFIG_TARGET_T1023RDB - /* set the on-board 1G SGMII RTL8211F PHY */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR); -#endif - break; - default: - printf("SerDes protocol 0x%x is not supported on T102xRDB\n", - srds_s1); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - case PHY_INTERFACE_MODE_SGMII: -#if defined(CONFIG_TARGET_T1023RDB) - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); -#elif defined(CONFIG_TARGET_T1024RDB) - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); -#endif - fm_info_set_mdio(i, dev); - break; - case PHY_INTERFACE_MODE_2500BASEX: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ -#if defined(CONFIG_TARGET_T1024RDB) - if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) || - (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) && - (port == FM1_DTSEC3)) { - fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4"); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "2500base-x"); - fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3"); - } -#endif -} - -void fdt_fixup_board_enet(void *fdt) -{ -} diff --git a/board/freescale/t102xrdb/law.c b/board/freescale/t102xrdb/law.c deleted file mode 100644 index 81caa961897..00000000000 --- a/board/freescale/t102xrdb/law.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct law_entry law_table[] = { -#ifdef CONFIG_MTD_NOR_FLASH - SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#endif -#ifdef CFG_SYS_BMAN_MEM_PHYS - SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), -#endif -#ifdef CFG_SYS_QMAN_MEM_PHYS - SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), -#endif -#ifdef CFG_SYS_CPLD_BASE_PHYS - SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), -#endif -#ifdef CFG_SYS_DCSRBAR_PHYS - SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), -#endif -#ifdef CFG_SYS_NAND_BASE_PHYS - SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c deleted file mode 100644 index de6cdda194e..00000000000 --- a/board/freescale/t102xrdb/spl.c +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/sleep.h" -#include "../common/spl.h" - -DECLARE_GLOBAL_DATA_PTR; - -phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_L3_SIZE; -} - -#if defined(CONFIG_SPL_MMC_BOOT) -#define GPIO1_SD_SEL 0x00020000 -int board_mmc_getcd(struct mmc *mmc) -{ - ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); - u32 val = in_be32(&pgpio->gpdat); - - /* GPIO1_14, 0: eMMC, 1: SD */ - val &= GPIO1_SD_SEL; - - return val ? -1 : 1; -} - -int board_mmc_getwp(struct mmc *mmc) -{ - ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); - u32 val = in_be32(&pgpio->gpdat); - - val &= GPIO1_SD_SEL; - - return val ? -1 : 0; -} -#endif - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio, sys_clk, ccb_clk; - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; - - /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ - memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); - - /* Update GD pointer */ - gd = (gd_t *)(CONFIG_SPL_GD_ADDR); - - console_init_f(); - -#ifdef CONFIG_DEEP_SLEEP - /* disable the console if boot from deep sleep */ - if (is_warm_boot()) - fsl_dp_disable_console(); -#endif - - /* initialize selected port with appropriate baud rate */ - sys_clk = get_board_sys_clk(); - plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; - ccb_clk = sys_clk * plat_ratio / 2; - - ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, - ccb_clk / 16 / CONFIG_BAUDRATE); - -#if defined(CONFIG_SPL_MMC_BOOT) - puts("\nSD boot...\n"); -#elif defined(CONFIG_SPL_SPI_BOOT) - puts("\nSPI boot...\n"); -#elif defined(CONFIG_SPL_NAND_BOOT) - puts("\nNAND boot...\n"); -#endif - - relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - struct bd_info *bd; - - bd = (struct bd_info *)(gd + sizeof(gd_t)); - memset(bd, 0, sizeof(struct bd_info)); - gd->bd = bd; - - arch_cpu_init(); - get_clocks(); - mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, - CONFIG_SPL_RELOC_MALLOC_SIZE); - gd->flags |= GD_FLG_FULL_MALLOC_INIT; - -#ifdef CONFIG_SPL_NAND_BOOT - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); -#endif -#ifdef CONFIG_SPL_MMC_BOOT - mmc_initialize(bd); - mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); -#endif -#ifdef CONFIG_SPL_SPI_BOOT - fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); -#endif - - gd->env_addr = (ulong)(SPL_ENV_ADDR); - gd->env_valid = ENV_VALID; - - i2c_init_all(); - - dram_init(); - -#ifdef CONFIG_SPL_MMC_BOOT - mmc_boot(); -#elif defined(CONFIG_SPL_SPI_BOOT) - fsl_spi_boot(); -#elif defined(CONFIG_SPL_NAND_BOOT) - nand_boot(); -#endif -} diff --git a/board/freescale/t102xrdb/t1023_nand_rcw.cfg b/board/freescale/t102xrdb/t1023_nand_rcw.cfg deleted file mode 100644 index f8f72826b16..00000000000 --- a/board/freescale/t102xrdb/t1023_nand_rcw.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header for T1023RDB -aa55aa55 010e0100 -#SerDes Protocol: 0x77 -#Default Core=1200MHz, DDR=1600MT/s with single source clock -0810000c 00000000 00000000 00000000 -3b800003 00000012 e8104000 21000000 -00000000 00000000 00000000 00022800 -00000130 04020200 00000000 00000006 diff --git a/board/freescale/t102xrdb/t1023_sd_rcw.cfg b/board/freescale/t102xrdb/t1023_sd_rcw.cfg deleted file mode 100644 index dbf8fba5535..00000000000 --- a/board/freescale/t102xrdb/t1023_sd_rcw.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header for T1023RDB -aa55aa55 010e0100 -#SerDes Protocol: 0x77 -#Default Core=1200MHz, DDR=1600MT/s with single source clock -0810000c 00000000 00000000 00000000 -3b800003 00000012 68104000 21000000 -00000000 00000000 00000000 00022800 -00000130 04020200 00000000 00000006 diff --git a/board/freescale/t102xrdb/t1023_spi_rcw.cfg b/board/freescale/t102xrdb/t1023_spi_rcw.cfg deleted file mode 100644 index 5edcdb50ea9..00000000000 --- a/board/freescale/t102xrdb/t1023_spi_rcw.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header for T1023RDB -aa55aa55 010e0100 -#SerDes Protocol: 0x77 -#Default Core=1200MHz, DDR=1600MT/s with single source clock -0810000c 00000000 00000000 00000000 -3b800003 00000012 58104000 21000000 -00000000 00000000 00000000 00022800 -00000130 04020200 00000000 00000006 diff --git a/board/freescale/t102xrdb/t1024_nand_rcw.cfg b/board/freescale/t102xrdb/t1024_nand_rcw.cfg deleted file mode 100644 index cd6f906396e..00000000000 --- a/board/freescale/t102xrdb/t1024_nand_rcw.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header for T1024RDB -aa55aa55 010e0100 -#SerDes Protocol: 0x95 -#Core/DDR: 1400Mhz/1600MT/s with single source clock -0810000c 00000000 00000000 00000000 -4a800003 80000012 ec027000 21000000 -00000000 00000000 00000000 00030810 -00000000 0b005a08 00000000 00000006 diff --git a/board/freescale/t102xrdb/t1024_pbi.cfg b/board/freescale/t102xrdb/t1024_pbi.cfg deleted file mode 100644 index 98efca25a29..00000000000 --- a/board/freescale/t102xrdb/t1024_pbi.cfg +++ /dev/null @@ -1,26 +0,0 @@ -#PBI commands -#Initialize CPC1 -09010000 00200400 -09138000 00000000 -091380c0 00000100 -#Configure CPC1 as 256KB SRAM -09010100 00000000 -09010104 fffc0007 -09010f00 081e000d -09010000 80000000 -#Configure LAW for CPC1 -09000cd0 00000000 -09000cd4 fffc0000 -09000cd8 81000011 -#Configure alternate space -09000010 00000000 -09000014 ff000000 -09000018 81000000 -#Configure SPI controller -09110000 80000403 -09110020 2d170008 -09110024 00100008 -09110028 00100008 -0911002c 00100008 -#Flush PBL data -091380c0 000FFFFF diff --git a/board/freescale/t102xrdb/t1024_sd_rcw.cfg b/board/freescale/t102xrdb/t1024_sd_rcw.cfg deleted file mode 100644 index 05b3f377636..00000000000 --- a/board/freescale/t102xrdb/t1024_sd_rcw.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header for T1024RDB -aa55aa55 010e0100 -#SerDes Protocol: 0x95 -#Core/DDR: 1400Mhz/1600MT/s with single source clock -0810000c 00000000 00000000 00000000 -4a800003 80000012 6c027000 21000000 -00000000 00000000 00000000 00030810 -00000000 0b005a08 00000000 00000006 diff --git a/board/freescale/t102xrdb/t1024_spi_rcw.cfg b/board/freescale/t102xrdb/t1024_spi_rcw.cfg deleted file mode 100644 index 8b695b4ab7b..00000000000 --- a/board/freescale/t102xrdb/t1024_spi_rcw.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header for T1024RDB -aa55aa55 010e0100 -#SerDes Protocol: 0x95 -#Core/DDR: 1400Mhz/1600MT/s with single source clock -0810000c 00000000 00000000 00000000 -4a800003 80000012 5c027000 21000000 -00000000 00000000 00000000 00030810 -00000000 0b005a08 00000000 00000006 diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c deleted file mode 100644 index 0a29e27b42c..00000000000 --- a/board/freescale/t102xrdb/t102xrdb.c +++ /dev/null @@ -1,397 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2020-2023 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "t102xrdb.h" -#ifdef CONFIG_TARGET_T1024RDB -#include "cpld.h" -#elif defined(CONFIG_TARGET_T1023RDB) -#include -#include -#endif -#include "../common/sleep.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_TARGET_T1023RDB -enum { - GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */ - GPIO1_EMMC_SEL, - GPIO3_GET_VERSION, /* GPIO3_4/5, 00:RevB, 01: RevC */ - GPIO3_BRD_VER_MASK = 0x0c000000, - GPIO3_OFFSET = 0x2000, - I2C_GET_BANK, - I2C_SET_BANK0, - I2C_SET_BANK4, -}; -#endif - -#if CONFIG_IS_ENABLED(DM_SERIAL) -int get_serial_clock(void) -{ - return get_bus_freq(0) / 2; -} -#endif - -int checkboard(void) -{ - struct cpu_type *cpu = gd->arch.cpu; - static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; - ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - printf("Board: %sRDB, ", cpu->name); -#if defined(CONFIG_TARGET_T1024RDB) - printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", - CPLD_READ(hw_ver), CPLD_READ(sw_ver)); -#elif defined(CONFIG_TARGET_T1023RDB) - printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B'); -#endif - printf("boot from "); - -#ifdef CONFIG_SDCARD - puts("SD/MMC\n"); -#elif CONFIG_SPIFLASH - puts("SPI\n"); -#elif defined(CONFIG_TARGET_T1024RDB) - u8 reg; - - reg = CPLD_READ(flash_csr); - - if (reg & CPLD_BOOT_SEL) { - puts("NAND\n"); - } else { - reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); - printf("NOR vBank%d\n", reg); - } -#elif defined(CONFIG_TARGET_T1023RDB) -#ifdef CONFIG_MTD_RAW_NAND - puts("NAND\n"); -#else - printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK)); -#endif -#endif - - puts("SERDES Reference Clocks:\n"); - if (srds_s1 == 0x95) - printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); - else - printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]); - - return 0; -} - -#ifdef CONFIG_TARGET_T1024RDB -static void board_mux_lane(void) -{ - ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_prtcl_s1; - u8 reg = CPLD_READ(misc_ctl_status); - - srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - if (srds_prtcl_s1 == 0x95) { - /* Route Lane B to PCIE */ - CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX); - } else { - /* Route Lane B to SGMII */ - CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX); - } - CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN); -} -#endif - -int board_early_init_f(void) -{ -#if defined(CONFIG_DEEP_SLEEP) - if (is_warm_boot()) - fsl_dp_disable_console(); -#endif - - return 0; -} - -int board_early_init_r(void) -{ -#ifdef CFG_SYS_FLASH_BASE - const unsigned int flashbase = CFG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - /* - * Remap Boot flash region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); -#endif - -#ifdef CONFIG_TARGET_T1024RDB - board_mux_lane(); -#endif - - pci_init(); - - return 0; -} - -#ifdef CONFIG_TARGET_T1024RDB -void board_reset(void) -{ - CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); -} -#endif - -int misc_init_r(void) -{ - return 0; -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); - fsl_fdt_fixup_dr_usb(blob, bd); - -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif - fdt_fixup_board_enet(blob); -#endif - -#ifdef CONFIG_TARGET_T1023RDB - if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0) - fdt_enable_nor(blob); -#endif - - return 0; -} - -#ifdef CONFIG_TARGET_T1023RDB -/* Enable NOR flash for RevC */ -static void fdt_enable_nor(void *blob) -{ - int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash"); - - if (nodeoff >= 0) - fdt_status_okay(blob, nodeoff); - else - printf("WARNING unable to set status for NOR\n"); -} - -int board_mmc_getcd(struct mmc *mmc) -{ - ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); - u32 val = in_be32(&pgpio->gpdat); - - /* GPIO1_14, 0: eMMC, 1: SD/MMC */ - val &= GPIO1_SD_SEL; - - return val ? -1 : 1; -} - -int board_mmc_getwp(struct mmc *mmc) -{ - ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); - u32 val = in_be32(&pgpio->gpdat); - - val &= GPIO1_SD_SEL; - - return val ? -1 : 0; -} - -static u32 t1023rdb_ctrl(u32 ctrl_type) -{ - ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); - ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 val; - u8 tmp; - int bus_num = I2C_PCA6408_BUS_NUM; - -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA6408_ADDR, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - switch (ctrl_type) { - case GPIO1_SD_SEL: - val = in_be32(&pgpio->gpdat); - val |= GPIO1_SD_SEL; - out_be32(&pgpio->gpdat, val); - setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); - break; - case GPIO1_EMMC_SEL: - val = in_be32(&pgpio->gpdat); - val &= ~GPIO1_SD_SEL; - out_be32(&pgpio->gpdat, val); - setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); - break; - case GPIO3_GET_VERSION: - pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR - + GPIO3_OFFSET); - val = in_be32(&pgpio->gpdat); - val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3; - if (val == 0x3) /* GPIO3_4/5 not used on RevB */ - val = 0; - return val; - case I2C_GET_BANK: - dm_i2c_read(dev, 0, &tmp, 1); - tmp &= 0x7; - tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2); - return tmp; - case I2C_SET_BANK0: - tmp = 0x0; - dm_i2c_write(dev, 1, &tmp, 1); - tmp = 0xf8; - dm_i2c_write(dev, 3, &tmp, 1); - /* asserting HRESET_REQ */ - out_be32(&gur->rstcr, 0x2); - break; - case I2C_SET_BANK4: - tmp = 0x1; - dm_i2c_write(dev, 1, &tmp, 1); - tmp = 0xf8; - dm_i2c_write(dev, 3, &tmp, 1); - out_be32(&gur->rstcr, 0x2); - break; - default: - break; - } -#else - u32 orig_bus; - - orig_bus = i2c_get_bus_num(); - - switch (ctrl_type) { - case GPIO1_SD_SEL: - val = in_be32(&pgpio->gpdat); - val |= GPIO1_SD_SEL; - out_be32(&pgpio->gpdat, val); - setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); - break; - case GPIO1_EMMC_SEL: - val = in_be32(&pgpio->gpdat); - val &= ~GPIO1_SD_SEL; - out_be32(&pgpio->gpdat, val); - setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); - break; - case GPIO3_GET_VERSION: - pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR - + GPIO3_OFFSET); - val = in_be32(&pgpio->gpdat); - val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3; - if (val == 0x3) /* GPIO3_4/5 not used on RevB */ - val = 0; - return val; - case I2C_GET_BANK: - i2c_set_bus_num(bus_num); - i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1); - tmp &= 0x7; - tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2); - i2c_set_bus_num(orig_bus); - return tmp; - case I2C_SET_BANK0: - i2c_set_bus_num(bus_num); - tmp = 0x0; - i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1); - tmp = 0xf8; - i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1); - /* asserting HRESET_REQ */ - out_be32(&gur->rstcr, 0x2); - break; - case I2C_SET_BANK4: - i2c_set_bus_num(bus_num); - tmp = 0x1; - i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1); - tmp = 0xf8; - i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1); - out_be32(&gur->rstcr, 0x2); - break; - default: - break; - } -#endif - return 0; -} - -static int switch_cmd(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - if (argc < 2) - return CMD_RET_USAGE; - if (!strcmp(argv[1], "bank0")) - t1023rdb_ctrl(I2C_SET_BANK0); - else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank")) - t1023rdb_ctrl(I2C_SET_BANK4); - else if (!strcmp(argv[1], "sd")) - t1023rdb_ctrl(GPIO1_SD_SEL); - else if (!strcmp(argv[1], "emmc")) - t1023rdb_ctrl(GPIO1_EMMC_SEL); - else - return CMD_RET_USAGE; - return 0; -} - -U_BOOT_CMD( - switch, 2, 0, switch_cmd, - "for bank0/bank4/sd/emmc switch control in runtime", - "command (e.g. switch bank4)" -); -#endif diff --git a/board/freescale/t102xrdb/t102xrdb.h b/board/freescale/t102xrdb/t102xrdb.h deleted file mode 100644 index 33df0f24df8..00000000000 --- a/board/freescale/t102xrdb/t102xrdb.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __T1024_RDB_H__ -#define __T1024_RDB_H__ - -void fdt_fixup_board_enet(void *blob); -void pci_of_setup(void *blob, struct bd_info *bd); -#ifdef CONFIG_TARGET_T1023RDB -static u32 t1023rdb_ctrl(u32 ctrl_type); -static void fdt_enable_nor(void *blob); -#endif -#endif diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c deleted file mode 100644 index 8e99c2c7022..00000000000 --- a/board/freescale/t102xrdb/tlb.c +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, - CFG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, - CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, - CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, - CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) - /* - * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the - * SRAM is at 0xfffc0000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_256K, 1), -#else - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), - - /* *I*G* - Flash, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - -#ifndef CONFIG_XPL_BUILD - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256K, 1), - - /* Bman/Qman */ -#ifdef CFG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 5, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, - CFG_SYS_BMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_16M, 1), -#endif -#ifdef CFG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, - CFG_SYS_QMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_16M, 1), -#endif -#endif -#ifdef CFG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 9, BOOKE_PAGESZ_4M, 1), -#endif -#ifdef CFG_SYS_NAND_BASE - SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_64K, 1), -#endif -#ifdef CFG_SYS_CPLD_BASE - SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 11, BOOKE_PAGESZ_256K, 1), -#endif - -#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD) - SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 12, BOOKE_PAGESZ_1G, 1), - SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000, - CFG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 13, BOOKE_PAGESZ_1G, 1) -#endif - /* entry 14 and 15 has been used hard coded, they will be disabled - * in cpu_init_f, so if needed more, will use entry 16 later. - */ -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t104xrdb/Kconfig b/board/freescale/t104xrdb/Kconfig deleted file mode 100644 index e4814915e33..00000000000 --- a/board/freescale/t104xrdb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_T1042D4RDB - -config SYS_BOARD - default "t104xrdb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "T104xRDB" - -endif diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS deleted file mode 100644 index 55fdb600a16..00000000000 --- a/board/freescale/t104xrdb/MAINTAINERS +++ /dev/null @@ -1,26 +0,0 @@ -T104XRDB BOARD -M: Priyanka Jain -S: Maintained -F: board/freescale/t104xrdb/ -F: include/configs/T104xRDB.h -F: configs/T1040RDB_defconfig -F: configs/T1040RDB_NAND_defconfig -F: configs/T1040RDB_SPIFLASH_defconfig -F: configs/T1040D4RDB_defconfig -F: configs/T1040D4RDB_NAND_defconfig -F: configs/T1040D4RDB_SPIFLASH_defconfig -F: configs/T1042RDB_defconfig -F: configs/T1042D4RDB_defconfig -F: configs/T1042D4RDB_NAND_defconfig -F: configs/T1042D4RDB_SPIFLASH_defconfig -F: configs/T1042RDB_PI_defconfig -F: configs/T1042RDB_PI_NAND_defconfig -F: configs/T1042RDB_PI_SPIFLASH_defconfig - -T1040RDB_SDCARD BOARD -M: Priyanka Jain -S: Maintained -F: configs/T1040RDB_SDCARD_defconfig -F: configs/T1040D4RDB_SDCARD_defconfig -F: configs/T1042D4RDB_SDCARD_defconfig -F: configs/T1042RDB_PI_SDCARD_defconfig diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile deleted file mode 100644 index 9bca1a1fbcc..00000000000 --- a/board/freescale/t104xrdb/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2013 Freescale Semiconductor, Inc. - -ifdef CONFIG_XPL_BUILD -obj-y += spl.o -else -obj-y += t104xrdb.o -obj-y += cpld.o -obj-y += eth.o -endif -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README deleted file mode 100644 index f312e6a3e32..00000000000 --- a/board/freescale/t104xrdb/README +++ /dev/null @@ -1,386 +0,0 @@ -Overview --------- -The T1040RDB is a Freescale reference board that hosts the T1040 SoC -(and variants). Variants inclued T1042 presonality of T1040, in which -case T1040RDB can also be called T1042RDB. - -The T1042RDB is a Freescale reference board that hosts the T1042 SoC -(and variants). The board is similar to T1040RDB, T1040 is a reduced -personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch). - -The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC. -(a personality of T1040 SoC). The board is similar to T1040RDB but is -designed specially with low power features targeted for Printing Image Market. - -The T1040D4RDB is a Freescale reference board that hosts the T1040 SoC. -The board is re-designed T1040RDB board with following changes : - - Support of DDR4 memory and some enhancements - -The T1042D4RDB is a Freescale reference board that hosts the T1042 SoC. -The board is re-designed T1040RDB board with following changes : - - Support of DDR4 memory - - Support for 0x86 serdes protocol which can support following interfaces - - 2 RGMII's on DTSEC4, DTSEC5 - - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3 - -Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB -------------------------------------------------------------------------- -Board Si Protocol Targeted Market -------------------------------------------------------------------------- -T1040RDB T1040 0x66 Networking -T1040RDB T1042 0x86 Networking -T1042RDB_PI T1042 0x06 Printing & Imaging -T1040D4RDB T1040 0x66 Networking -T1042D4RDB T1042 0x86 Networking - - -T1040 SoC Overview ------------------- -The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA -processor cores with high-performance data path acceleration architecture -and network peripheral interfaces required for networking & telecommunications. - -The T1040/T1042 SoC includes the following function and features: - - - Four e5500 cores, each with a private 256 KB L2 cache - - 256 KB shared L3 CoreNet platform cache (CPC) - - Interconnect CoreNet platform - - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving - support - - Data Path Acceleration Architecture (DPAA) incorporating acceleration - for the following functions: - - Packet parsing, classification, and distribution - - Queue management for scheduling, packet sequencing, and congestion - management - - Cryptography Acceleration (SEC 5.0) - - RegEx Pattern Matching Acceleration (PME 2.2) - - IEEE Std 1588 support - - Hardware buffer management for buffer allocation and deallocation - - Ethernet interfaces - - Integrated 8-port Gigabit Ethernet switch (T1040 only) - - Four 1 Gbps Ethernet controllers - - Two RGMII interfaces or one RGMII and one MII interfaces - - High speed peripheral interfaces - - Four PCI Express 2.0 controllers running at up to 5 GHz - - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation - - Upto two QSGMII interface - - Upto six SGMII interface supporting 1000 Mbps - - One SGMII interface supporting upto 2500 Mbps - - Additional peripheral interfaces - - Two USB 2.0 controllers with integrated PHY - - SD/eSDHC/eMMC - - eSPI controller - - Four I2C controllers - - Four UARTs - - Four GPIO controllers - - Integrated flash controller (IFC) - - LCD and HDMI interface (DIU) with 12 bit dual data rate - - TDM interface - - Multicore programmable interrupt controller (PIC) - - Two 8-channel DMA engines - - Single source clocking implementation - - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - -T1040 SoC Personalities -------------------------- -T1022 Personality: -T1022 is a reduced personality of T1040 with less core/clusters. - -T1042 Personality: -T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit -Ethernet switch. Rest of the blocks are same as T1040 - - -T1040RDB board Overview -------------------------- - - SERDES Connections, 8 lanes information: - 1: None - 2: SGMII - 3: QSGMII - 4: QSGMII - 5: PCIe1 x1 slot - 6: mini PCIe connector - 7: mini PCIe connector - 8: SATA connector - - DDR Controller - - Supports rates of up to 1600 MHz data-rate - - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types. - - IFC/Local Bus - - NAND flash: 1GB 8-bit NAND flash - - NOR: 128MB 16-bit NOR Flash - - Ethernet - - Two on-board RGMII 10/100/1G ethernet ports. - - CPLD - - Clocks - - System and DDR clock (SYSCLK, “DDRCLK”) - - SERDES clocks - - Power Supplies - - USB - - Supports two USB 2.0 ports with integrated PHYs - - Two type A ports with 5V@1.5A per port. - - SDHC - - SDHC/SDXC connector - - SPI - - On-board 64MB SPI flash - - Other IO - - Two Serial ports - - Four I2C ports - -T1042RDB_PI board Overview -------------------------- - - SERDES Connections, 8 lanes information: - 1, 2, 3, 4 : PCIe x4 slot - 5: mini PCIe connector - 6: mini PCIe connector - 7: NA - 8: SATA connector - - DDR Controller - - Supports rates of up to 1600 MHz data-rate - - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types. - - IFC/Local Bus - - NAND flash: 1GB 8-bit NAND flash - - NOR: 128MB 16-bit NOR Flash - - Ethernet - - Two on-board RGMII 10/100/1G ethernet ports. - - CPLD - - Clocks - - System and DDR clock (SYSCLK, “DDRCLK”) - - SERDES clocks - - Video - - DIU supports video at up to 1280x1024x32bpp - - Power Supplies - - USB - - Supports two USB 2.0 ports with integrated PHYs - - Two type A ports with 5V@1.5A per port. - - SDHC - - SDHC/SDXC connector - - SPI - - On-board 64MB SPI flash - - Other IO - - Two Serial ports - - Four I2C ports - -Memory map ------------ -The addresses in brackets are physical addresses. - -Start Address End Address Description Size -0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB -0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB -0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB -0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB -0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB -0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB -0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB -0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB -0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB -0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB -0xF_0000_0000 0xF_003F_FFFF DCSR 4MB -0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB -0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB -0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB -0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB -0x0_0000_0000 0x0_ffff_ffff DDR 2GB - - -NOR Flash memory Map ---------------------- - Start End Definition Size -0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB -0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB -0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB -0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB -0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB -0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB -0xEC000000 0xEC01FFFF RCW (alt bank) 128KB -0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB -0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB -0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB -0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB -0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB -0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB -0xE8000000 0xE801FFFF RCW (current bank) 128KB - - -Various Software configurations/environment variables/commands --------------------------------------------------------------- -The below commands apply to the board - -1. U-Boot environment variable hwconfig - The default hwconfig is: - hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1: - dr_mode=host,phy_type=utmi - Note: For USB gadget set "dr_mode=peripheral" - -2. FMAN Ucode versions - fsl_fman_ucode_t1040.bin - -3. Switching to alternate bank - Commands for switching to alternate bank. - - 1. To change from vbank0 to vbank4 - => cpld reset altbank (it will boot using vbank4) - - 2.To change from vbank4 to vbank0 - => cpld reset (it will boot using vbank0) - -NAND boot with 2 Stage boot loader ----------------------------------- -PBL initialise the internal SRAM and copy SPL(160KB) in SRAM. -SPL further initialise DDR using SPD and environment variables and copy -U-Boot(768 KB) from flash to DDR. -Finally SPL transer control to U-Boot for futher booting. - -SPL has following features: - - Executes within 256K - - No relocation required - - Run time view of SPL framework during boot :- - ----------------------------------------------- - Area | Address | ------------------------------------------------ - Secure boot | 0xFFFC0000 (32KB) | - headers | | - ----------------------------------------------- - GD, BD | 0xFFFC8000 (4KB) | - ----------------------------------------------- - ENV | 0xFFFC9000 (8KB) | - ----------------------------------------------- - HEAP | 0xFFFCB000 (30KB) | - ----------------------------------------------- - STACK | 0xFFFD8000 (22KB) | - ----------------------------------------------- - U-Boot SPL | 0xFFFD8000 (160KB) | - ----------------------------------------------- - -NAND Flash memory Map on T104xRDB ------------------------------------------- - Start End Definition Size -0x000000 0x0FFFFF U-Boot 1MB -0x180000 0x19FFFF U-Boot env 128KB -0x280000 0x29FFFF FMAN Ucode 128KB -0x380000 0x39FFFF QE Firmware 128KB - -SD Card memory Map on T104xRDB ------------------------------------------- - Block #blocks Definition Size -0x008 2048 U-Boot 1MB -0x800 0024 U-Boot env 8KB -0x820 0256 FMAN Ucode 128KB -0x920 0256 QE Firmware 128KB - -SPI Flash memory Map on T104xRDB ------------------------------------------- - Start End Definition Size -0x000000 0x0FFFFF U-Boot 1MB -0x100000 0x101FFF U-Boot env 8KB -0x110000 0x12FFFF FMAN Ucode 128KB -0x130000 0x14FFFF QE Firmware 128KB - -Please note QE Firmware is only valid for T1040RDB - - -Switch Settings for T104xRDB boards: (ON is 0, OFF is 1) -========================================================== -NOR boot SW setting: -SW1: 00010011 -SW2: 10111011 -SW3: 11100001 - -NAND boot SW setting: -SW1: 10001000 -SW2: 00111011 -SW3: 11110001 - -SPI boot SW setting: -SW1: 00100010 -SW2: 10111011 -SW3: 11100001 - -SD boot SW setting: -SW1: 00100000 -SW2: 00111011 -SW3: 11100001 - -Switch Settings for T104xD4RDB boards: (ON is 0, OFF is 1) -============================================================= -NOR boot SW setting: -SW1: 00010011 -SW2: 10111001 -SW3: 11100001 - -NAND boot SW setting: -SW1: 10001000 -SW2: 00111001 -SW3: 11110001 - -SPI boot SW setting: -SW1: 00100010 -SW2: 10111001 -SW3: 11100001 - -SD boot SW setting: -SW1: 00100000 -SW2: 00111001 -SW3: 11100001 - -PBL-based image generation -========================== -Changes only the required register bit in in PBI commands. - -Provides reference code which might needs some -modification as per requirement. -example: -By default PBI_SRC=14 (which is for IFC-NAND/NOR) in rcw.cfg file -which needs to be changed for SPI and SD. - -For SD-boot -============== -1. Set RCW[192:195], PBI_SRC bits as 6 in RCW file (t1040d4_rcw.cfg type files) - -example: - RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg - -Change -66000002 40000002 ec027000 01000000 -to -66000002 40000002 6c027000 01000000 - -2. SD does not support flush so remove flush from pbl, make changes in - tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000 - with 0x091380c0 - -For SPI-boot -============== -1. Set RCW[192:195], PBI_SRC bits as 5 in RCW file (t1040d4_rcw.cfg type files) - -example: - RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg - -Change -66000002 40000002 ec027000 01000000 -to -66000002 40000002 5c027000 01000000 - -2. SPI does not support flush so remove flush from pbl, make changes in - tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000 - with 0x091380c0 - -Device tree support and how to enable it for different configs --------------------------------------------------------------- -Device tree support is available for t1042d4rdb for below mentioned boot, -1. NOR Boot -2. NAND Boot -3. SD Boot -4. SPIFLASH Boot - -To enable device tree support for other boot, below configs need to be -enabled in relative defconfig file, -1. CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" (Change default device tree name if required) -2. CONFIG_OF_CONTROL -3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at - CFG_RESET_VECTOR_ADDRESS - 0xffc - -If device tree support is enabled in defconfig, -1. use 'u-boot.bin' for NOR boot. -2. use 'u-boot-with-spl-pbl.bin' for other boot. diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c deleted file mode 100644 index 038e40e2fae..00000000000 --- a/board/freescale/t104xrdb/cpld.c +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/** - * Copyright 2014 Freescale Semiconductor - * - * This file provides support for the board-specific CPLD used on some Freescale - * reference boards. - * - * The following macros need to be defined: - * - * CFG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map - */ - -#include -#include -#include -#include - -#include "cpld.h" - -u8 cpld_read(unsigned int reg) -{ - void *p = (void *)CFG_SYS_CPLD_BASE; - - return in_8(p + reg); -} - -void cpld_write(unsigned int reg, u8 value) -{ - void *p = (void *)CFG_SYS_CPLD_BASE; - - out_8(p + reg, value); -} - -/** - * Set the boot bank to the alternate bank - */ -void cpld_set_altbank(void) -{ - u8 reg = CPLD_READ(flash_ctl_status); - - reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; - - CPLD_WRITE(flash_ctl_status, reg); - CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); -} - -/** - * Set the boot bank to the default bank - */ -void cpld_set_defbank(void) -{ - u8 reg = CPLD_READ(flash_ctl_status); - - reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; - - CPLD_WRITE(flash_ctl_status, reg); - CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); -} - -#ifdef DEBUG -static void cpld_dump_regs(void) -{ - printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); - printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); - printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); - printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); - printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); - printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); - printf("int_status = 0x%02x\n", CPLD_READ(int_status)); - printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status)); - printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status)); -#if defined(CONFIG_TARGET_T1040D4D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) - printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); -#else - printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status)); -#endif - printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status)); - printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status)); - printf("boot_override = 0x%02x\n", CPLD_READ(boot_override)); - printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1)); - printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2)); - putc('\n'); -} -#endif - -int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - int rc = 0; - - if (argc <= 1) - return cmd_usage(cmdtp); - - if (strcmp(argv[1], "reset") == 0) { - if (strcmp(argv[2], "altbank") == 0) - cpld_set_altbank(); - else - cpld_set_defbank(); -#ifdef DEBUG - } else if (strcmp(argv[1], "dump") == 0) { - cpld_dump_regs(); -#endif - } else - rc = cmd_usage(cmdtp); - - return rc; -} - -U_BOOT_CMD( - cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, - "Reset the board or alternate bank", - "reset - hard reset to default bank\n" - "cpld reset altbank - reset to alternate bank\n" -#ifdef DEBUG - "cpld dump - display the CPLD registers\n" -#endif - ); diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h deleted file mode 100644 index 0384202fbcb..00000000000 --- a/board/freescale/t104xrdb/cpld.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/** - * Copyright 2013 Freescale Semiconductor - * - * This file provides support for the ngPIXIS, a board-specific FPGA used on - * some Freescale reference boards. - */ - -/* - * CPLD register set. Feel free to add board-specific #ifdefs where necessary. - */ -struct cpld_data { - u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */ - u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */ - u8 hw_ver; /* 0x02 - Hardware Revision Register */ - u8 sw_ver; /* 0x03 - Software Revision register */ - u8 res0[12]; /* 0x04 - 0x0F - not used */ - u8 reset_ctl1; /* 0x10 - Reset control Register1 */ - u8 reset_ctl2; /* 0x11 - Reset control Register2 */ - u8 int_status; /* 0x12 - Interrupt status Register */ - u8 flash_ctl_status; /* 0x13 - Flash control and status register */ - u8 fan_ctl_status; /* 0x14 - Fan control and status register */ -#if defined(CONFIG_TARGET_T1042D4RDB) - u8 int_mask; /* 0x15 - Interrupt mask Register */ -#else - u8 led_ctl_status; /* 0x15 - LED control and status register */ -#endif - u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ - u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ - u8 boot_override; /* 0x18 - Boot override register */ - u8 boot_config1; /* 0x19 - Boot config override register*/ - u8 boot_config2; /* 0x1A - Boot config override register*/ -}; - -/* Pointer to the CPLD register set */ - -u8 cpld_read(unsigned int reg); -void cpld_write(unsigned int reg, u8 value); - -#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) -#define CPLD_WRITE(reg, value)\ - cpld_write(offsetof(struct cpld_data, reg), value) -#define MISC_CTL_SG_SEL 0x80 -#define MISC_CTL_AURORA_SEL 0x02 -#define MISC_MUX_QE_TDM 0xc0 diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c deleted file mode 100644 index 6c066480b46..00000000000 --- a/board/freescale/t104xrdb/ddr.c +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * Copyright 2021 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 1) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - pbsp = udimms[0]; - - /* Get clk_adjust according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks && - (pdimm->rank_density >> 30) >= pbsp->rank_gb) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found\n"); - printf("for data rate %lu MT/s\n", ddr_freq); - printf("Trying to use the highest speed (%u) parameters\n", - pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" - "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " - "wrlvl_ctrl_3 0x%x\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, - pbsp->wrlvl_ctl_3); - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ -#ifdef CONFIG_SYS_FSL_DDR4 - popts->half_strength_driver_enable = 1; - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x59; -#else - popts->cpo_sample = 0x54; - popts->half_strength_driver_enable = 0; -#endif - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * rtt and rtt_wr override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 75 Ohm */ -#ifdef CONFIG_SYS_FSL_DDR4 - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) | - DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ -#else - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); -#endif -} - -#if defined(CONFIG_DEEP_SLEEP) -void board_mem_sleep_setup(void) -{ - void __iomem *cpld_base = (void *)CFG_SYS_CPLD_BASE; - - /* does not provide HW signals for power management */ - clrbits_8(cpld_base + 0x17, 0x40); - /* Disable MCKE isolation */ - gpio_set_value(2, 0); - udelay(1); -} -#endif - -int dram_init(void) -{ - phys_size_t dram_size; - -#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) - puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); -#else - dram_size = fsl_ddr_sdram_size(); -#endif - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - -#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD) - fsl_dp_resume(); -#endif - - gd->ram_size = dram_size; - - return 0; -} diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h deleted file mode 100644 index f9d667f6174..00000000000 --- a/board/freescale/t104xrdb/ddr.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ - -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 - */ -#ifdef CONFIG_SYS_FSL_DDR4 - {2, 1600, 4, 8, 6, 0x07090A0c, 0x0e0f100a}, - {1, 1600, 4, 8, 5, 0x0607080B, 0x0C0C0D09}, -#elif defined(CONFIG_SYS_FSL_DDR3) - {2, 833, 4, 8, 6, 0x06060607, 0x08080807}, - {2, 833, 0, 8, 6, 0x06060607, 0x08080807}, - {2, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09}, - {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09}, - {2, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A}, - {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A}, - {1, 833, 4, 8, 6, 0x06060607, 0x08080807}, - {1, 833, 0, 8, 6, 0x06060607, 0x08080807}, - {1, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09}, - {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09}, - {1, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A}, - {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A}, -#else -#error DDR type not defined -#endif - {} -}; - -#endif - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c deleted file mode 100644 index c35ec368a45..00000000000 --- a/board/freescale/t104xrdb/eth.c +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct memac_mdio_info memac_mdio_info; - unsigned int i; - int phy_addr = 0; - - printf("Initializing Fman\n"); - - memac_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fm_memac_mdio_init(bis, &memac_mdio_info); - - /* - * Program on board RGMII, SGMII PHY addresses. - */ - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { -#ifdef CONFIG_TARGET_T1042D4RDB - case PHY_INTERFACE_MODE_SGMII: - /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2 - * & DTSEC3 - */ - if (FM1_DTSEC1 == i) - phy_addr = CFG_SYS_SGMII1_PHY_ADDR; - if (FM1_DTSEC2 == i) - phy_addr = CFG_SYS_SGMII2_PHY_ADDR; - if (FM1_DTSEC3 == i) - phy_addr = CFG_SYS_SGMII3_PHY_ADDR; - fm_info_set_phy_address(i, phy_addr); - break; -#endif - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (FM1_DTSEC4 == i) - phy_addr = CFG_SYS_RGMII1_PHY_ADDR; - if (FM1_DTSEC5 == i) - phy_addr = CFG_SYS_RGMII2_PHY_ADDR; - fm_info_set_phy_address(i, phy_addr); - break; - case PHY_INTERFACE_MODE_QSGMII: - fm_info_set_phy_address(i, 0); - break; - case PHY_INTERFACE_MODE_NA: - fm_info_set_phy_address(i, 0); - break; - default: - printf("Fman1: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - fm_info_set_phy_address(i, 0); - break; - } - if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII || - fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NA) - fm_info_set_mdio(i, NULL); - else - fm_info_set_mdio(i, - miiphy_get_dev_by_name( - DEFAULT_FM_MDIO_NAME)); - } - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c deleted file mode 100644 index d34641c2397..00000000000 --- a/board/freescale/t104xrdb/law.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct law_entry law_table[] = { -#ifdef CONFIG_MTD_NOR_FLASH - SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#endif -#ifdef CFG_SYS_BMAN_MEM_PHYS - SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), -#endif -#ifdef CFG_SYS_QMAN_MEM_PHYS - SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), -#endif -#ifdef CFG_SYS_CPLD_BASE_PHYS - SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), -#endif -#ifdef CFG_SYS_DCSRBAR_PHYS - SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), -#endif -#ifdef CFG_SYS_NAND_BASE_PHYS - SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c deleted file mode 100644 index e02a1f95d4c..00000000000 --- a/board/freescale/t104xrdb/spl.c +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/sleep.h" -#include "../common/spl.h" - -DECLARE_GLOBAL_DATA_PTR; - -phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_L3_SIZE; -} - -#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 -void board_init_f(ulong bootflag) -{ - u32 plat_ratio, sys_clk, uart_clk; -#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) - u32 porsr1, pinctl; - u32 svr = get_svr(); -#endif - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; - -#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) - if (IS_SVR_REV(svr, 1, 0)) { - /* - * There is T1040 SoC issue where NOR, FPGA are inaccessible - * during NAND boot because IFC signals > IFC_AD7 are not - * enabled. This workaround changes RCW source to make all - * signals enabled. - */ - porsr1 = in_be32(&gur->porsr1); - pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) - | 0x24800000); - out_be32((unsigned int *)(CFG_SYS_DCSRBAR + 0x20000), - pinctl); - } -#endif - - /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ - memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); - - /* Update GD pointer */ - gd = (gd_t *)(CONFIG_SPL_GD_ADDR); - -#ifdef CONFIG_DEEP_SLEEP - /* disable the console if boot from deep sleep */ - if (is_warm_boot()) - fsl_dp_disable_console(); -#endif - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("" : : : "memory"); - - console_init_f(); - - /* initialize selected port with appropriate baud rate */ - sys_clk = get_board_sys_clk(); - plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; - uart_clk = sys_clk * plat_ratio / 2; - - ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, - uart_clk / 16 / CONFIG_BAUDRATE); - - relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - struct bd_info *bd; - - bd = (struct bd_info *)(gd + sizeof(gd_t)); - memset(bd, 0, sizeof(struct bd_info)); - gd->bd = bd; - - arch_cpu_init(); - get_clocks(); - mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, - CONFIG_SPL_RELOC_MALLOC_SIZE); - gd->flags |= GD_FLG_FULL_MALLOC_INIT; - -#ifdef CONFIG_SPL_MMC_BOOT - mmc_initialize(bd); -#endif - - /* relocate environment function pointers etc. */ -#if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_MMC) || \ - defined(CONFIG_ENV_IS_IN_SPI_FLASH) -#ifdef CONFIG_SPL_NAND_BOOT - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); -#endif -#ifdef CONFIG_SPL_MMC_BOOT - mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); -#endif -#ifdef CONFIG_SPL_SPI_BOOT - fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); -#endif - gd->env_addr = (ulong)(SPL_ENV_ADDR); - gd->env_valid = ENV_VALID; -#endif - - i2c_init_all(); - - puts("\n\n"); - - dram_init(); - -#ifdef CONFIG_SPL_MMC_BOOT - mmc_boot(); -#elif defined(CONFIG_SPL_SPI_BOOT) - fsl_spi_boot(); -#elif defined(CONFIG_SPL_NAND_BOOT) - nand_boot(); -#endif -} diff --git a/board/freescale/t104xrdb/t1040_nand_rcw.cfg b/board/freescale/t104xrdb/t1040_nand_rcw.cfg deleted file mode 100644 index 3300c184a1a..00000000000 --- a/board/freescale/t104xrdb/t1040_nand_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -# serdes protocol 0x66 -0c18000e 0e000000 00000000 00000000 -66000002 80000002 e8106000 01000000 -00000000 00000000 00000000 00032810 -00000000 0342500f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1040_sd_rcw.cfg b/board/freescale/t104xrdb/t1040_sd_rcw.cfg deleted file mode 100644 index fd3e8c5bbf5..00000000000 --- a/board/freescale/t104xrdb/t1040_sd_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -# serdes protocol 0x66 -0c18000e 0e000000 00000000 00000000 -66000002 80000002 68106000 01000000 -00000000 00000000 00000000 00032810 -00000000 0342500f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1040_spi_rcw.cfg b/board/freescale/t104xrdb/t1040_spi_rcw.cfg deleted file mode 100644 index fccde5e01fe..00000000000 --- a/board/freescale/t104xrdb/t1040_spi_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -# serdes protocol 0x66 -0c18000e 0e000000 00000000 00000000 -66000002 80000002 58106000 01000000 -00000000 00000000 00000000 00032810 -00000000 0342500f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg b/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg deleted file mode 100644 index c1034b3dfa3..00000000000 --- a/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -# serdes protocol 0x66 -0c18000e 0e000000 00000000 00000000 -66000002 40000002 ec027000 01000000 -00000000 00000000 00000000 00030810 -00000000 0342580f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg b/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg deleted file mode 100644 index e6f7585bb02..00000000000 --- a/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -# serdes protocol 0x66 -0c18000e 0e000000 00000000 00000000 -66000002 40000002 6c027000 01000000 -00000000 00000000 00000000 00030810 -00000000 0342580f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg b/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg deleted file mode 100644 index cde862dff5c..00000000000 --- a/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -# serdes protocol 0x66 -0c18000e 0e000000 00000000 00000000 -66000002 40000002 5c027000 01000000 -00000000 00000000 00000000 00030810 -00000000 0342580f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1042_nand_rcw.cfg b/board/freescale/t104xrdb/t1042_nand_rcw.cfg deleted file mode 100644 index db4d52f397d..00000000000 --- a/board/freescale/t104xrdb/t1042_nand_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -# serdes protocol 0x86 -0c18000e 0e000000 00000000 00000000 -86000002 80000002 ec027000 01000000 -00000000 00000000 00000000 00032810 -00000000 0342500f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg b/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg deleted file mode 100644 index 57de89ad0e7..00000000000 --- a/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -# serdes protocol 0x06 -0c18000e 0e000000 00000000 00000000 -06000002 00400002 e8106000 01000000 -00000000 00000000 00000000 00030810 -00000000 01fe0a06 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg b/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg deleted file mode 100644 index bbce9a36930..00000000000 --- a/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -# serdes protocol 0x06 -0c18000e 0e000000 00000000 00000000 -06000002 00400002 68106000 01000000 -00000000 00000000 00000000 00030810 -00000000 01fe0a06 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg b/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg deleted file mode 100644 index b1d8b4c65af..00000000000 --- a/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -# serdes protocol 0x06 -0c18000e 0e000000 00000000 00000000 -06000002 00400002 58106000 01000000 -00000000 00000000 00000000 00030810 -00000000 01fe0a06 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1042_sd_rcw.cfg b/board/freescale/t104xrdb/t1042_sd_rcw.cfg deleted file mode 100644 index d77bf189b22..00000000000 --- a/board/freescale/t104xrdb/t1042_sd_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -# serdes protocol 0x86 -0c18000e 0e000000 00000000 00000000 -86000002 80000002 6c027000 01000000 -00000000 00000000 00000000 00032810 -00000000 0342500f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1042_spi_rcw.cfg b/board/freescale/t104xrdb/t1042_spi_rcw.cfg deleted file mode 100644 index e8a3ad12804..00000000000 --- a/board/freescale/t104xrdb/t1042_spi_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -# serdes protocol 0x86 -0c18000e 0e000000 00000000 00000000 -86000002 80000002 5c027000 01000000 -00000000 00000000 00000000 00032810 -00000000 0342500f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg b/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg deleted file mode 100644 index 9e0ee2795f8..00000000000 --- a/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -# serdes protocol 0x86 -0c18000e 0e000000 00000000 00000000 -86000002 40000002 ec027000 01000000 -00000000 00000000 00000000 00030810 -00000000 0342500f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg b/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg deleted file mode 100644 index 9d9046d6549..00000000000 --- a/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -# serdes protocol 0x86 -0c18000e 0e000000 00000000 00000000 -86000002 40000002 6c027000 01000000 -00000000 00000000 00000000 00030810 -00000000 0342500f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg b/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg deleted file mode 100644 index f1ec98932f8..00000000000 --- a/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -# serdes protocol 0x86 -0c18000e 0e000000 00000000 00000000 -86000002 40000002 5c027000 01000000 -00000000 00000000 00000000 00030810 -00000000 0342500f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t104x_pbi.cfg b/board/freescale/t104xrdb/t104x_pbi.cfg deleted file mode 100644 index 51945b47489..00000000000 --- a/board/freescale/t104xrdb/t104x_pbi.cfg +++ /dev/null @@ -1,36 +0,0 @@ -#PBI commands -#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed -09250100 00000400 -09250108 00002000 -#Software Workaround for errata A-008007 to reset PVR register -09000010 0000000b -09000014 c0000000 -09000018 81d00017 -89020400 a1000000 -091380c0 000f0000 -89020400 00000000 -#Initialize CPC1 -09010000 00200400 -09138000 00000000 -091380c0 00000100 -#Configure CPC1 as 256KB SRAM -09010100 00000000 -09010104 fffc0007 -09010f00 081e000d -09010000 80000000 -#Configure LAW for CPC1 -09000cd0 00000000 -09000cd4 fffc0000 -09000cd8 81000011 -#Configure alternate space -09000010 00000000 -09000014 ff000000 -09000018 81000000 -#Configure SPI controller -09110000 80000403 -09110020 2d170008 -09110024 00100008 -09110028 00100008 -0911002c 00100008 -#Flush PBL data -091380c0 000FFFFF diff --git a/board/freescale/t104xrdb/t104x_pbi_sb.cfg b/board/freescale/t104xrdb/t104x_pbi_sb.cfg deleted file mode 100644 index 98dc8e4c240..00000000000 --- a/board/freescale/t104xrdb/t104x_pbi_sb.cfg +++ /dev/null @@ -1,38 +0,0 @@ -#PBI commands -#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed -09250100 00000400 -09250108 00002000 -#Software Workaround for errata A-008007 to reset PVR register -09000010 0000000b -09000014 c0000000 -09000018 81d00017 -89020400 a1000000 -091380c0 000f0000 -89020400 00000000 -#Initialize CPC1 -09010000 00200400 -09138000 00000000 -091380c0 00000100 -#Configure CPC1 as 256KB SRAM -09010100 00000000 -09010104 bffc0007 -09010f00 081e000d -09010000 80000000 -#Configure LAW for CPC1 -09000cd0 00000000 -09000cd4 bffc0000 -09000cd8 81000011 -#Configure alternate space -09000010 00000000 -09000014 bf000000 -09000018 81000000 -#Configure SPI controller -09110000 80000403 -09110020 2d170008 -09110024 00100008 -09110028 00100008 -0911002c 00100008 -#Flush PBL data -091380c0 000FFFFF -090e0200 bffd0000 -091380c0 000FFFFF diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c deleted file mode 100644 index ef4dfef4965..00000000000 --- a/board/freescale/t104xrdb/t104xrdb.c +++ /dev/null @@ -1,159 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * Copyright 2023 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/sleep.h" -#include "t104xrdb.h" -#include "cpld.h" - -DECLARE_GLOBAL_DATA_PTR; - -#if CONFIG_IS_ENABLED(DM_SERIAL) -int get_serial_clock(void) -{ - return get_bus_freq(0) / 2; -} -#endif - -int checkboard(void) -{ - struct cpu_type *cpu = gd->arch.cpu; - u8 sw; - -#if defined(CONFIG_TARGET_T1042D4RDB) - printf("Board: %sD4RDB\n", cpu->name); -#else - printf("Board: %sRDB\n", cpu->name); -#endif - printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", - CPLD_READ(hw_ver), CPLD_READ(sw_ver)); - - sw = CPLD_READ(flash_ctl_status); - sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); - - printf("vBank: %d\n", sw); - - return 0; -} - -int board_early_init_f(void) -{ -#if defined(CONFIG_DEEP_SLEEP) - if (is_warm_boot()) - fsl_dp_disable_console(); -#endif - - return 0; -} - -int board_early_init_r(void) -{ -#ifdef CFG_SYS_FLASH_BASE - const unsigned int flashbase = CFG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); -#endif - - pci_init(); - - return 0; -} - -int misc_init_r(void) -{ - ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) >> 24; - - printf("SERDES Reference : 0x%X\n", srds_s1); - - /* select SGMII*/ - if (srds_s1 == 0x86) - CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | - MISC_CTL_SG_SEL); - - /* select SGMII and Aurora*/ - if (srds_s1 == 0x8E) - CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | - MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL); - - return 0; -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); - -#ifdef CONFIG_HAS_FSL_DR_USB - fsl_fdt_fixup_dr_usb(blob, bd); -#endif - -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif -#endif - - if (hwconfig("qe-tdm")) - fdt_del_diu(blob); - return 0; -} diff --git a/board/freescale/t104xrdb/t104xrdb.h b/board/freescale/t104xrdb/t104xrdb.h deleted file mode 100644 index 678724c7e2b..00000000000 --- a/board/freescale/t104xrdb/t104xrdb.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __T104x_RDB_H__ -#define __T104x_RDB_H__ - -void fdt_fixup_board_enet(void *blob); -void pci_of_setup(void *blob, struct bd_info *bd); - -#endif diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c deleted file mode 100644 index 7b2183da8b0..00000000000 --- a/board/freescale/t104xrdb/tlb.c +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, - CFG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, - CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, - CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, - CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) && \ - !defined(CONFIG_NXP_ESBC) - /* - * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the - * SRAM is at 0xfffc0000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_256K, 1), - -#elif defined(CONFIG_NXP_ESBC) && defined(CONFIG_XPL_BUILD) - /* - * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot - * the physical address of the SRAM is at 0xbffc0000, - * and virtual address is 0xfffc0000 - */ - - SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_VADDR, - CFG_SYS_INIT_L3_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_256K, 1), -#else - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), - - /* *I*G* - Flash, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - -#ifndef CONFIG_XPL_BUILD - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256K, 1), - - /* Bman/Qman */ -#ifdef CFG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 5, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, - CFG_SYS_BMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_16M, 1), -#endif -#ifdef CFG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, - CFG_SYS_QMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_16M, 1), -#endif -#endif -#ifdef CFG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 9, BOOKE_PAGESZ_4M, 1), -#endif -#ifdef CFG_SYS_NAND_BASE - /* - * *I*G - NAND - * entry 14 and 15 has been used hard coded, they will be disabled - * in cpu_init_f, so we use entry 16 for nand. - */ - SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_64K, 1), -#endif -#ifdef CFG_SYS_CPLD_BASE - SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 11, BOOKE_PAGESZ_256K, 1), -#endif - -#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD) - SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 12, BOOKE_PAGESZ_1G, 1), - SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000, - CFG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 13, BOOKE_PAGESZ_1G, 1) -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t208xqds/Kconfig b/board/freescale/t208xqds/Kconfig deleted file mode 100644 index c419a59dbb6..00000000000 --- a/board/freescale/t208xqds/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_T2080QDS - -config SYS_BOARD - default "t208xqds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "T208xQDS" - -config SRIO_PCIE_BOOT_SLAVE - bool "Boot as a SRIO PCIe slave device" - -endif diff --git a/board/freescale/t208xqds/MAINTAINERS b/board/freescale/t208xqds/MAINTAINERS deleted file mode 100644 index 790b009c516..00000000000 --- a/board/freescale/t208xqds/MAINTAINERS +++ /dev/null @@ -1,20 +0,0 @@ -T208XQDS BOARD -M: Shengzhou Liu -S: Maintained -F: board/freescale/t208xqds/ -F: include/configs/T208xQDS.h -F: configs/T2080QDS_defconfig -F: configs/T2080QDS_NAND_defconfig -F: configs/T2080QDS_SDCARD_defconfig -F: configs/T2080QDS_SPIFLASH_defconfig -F: configs/T2080QDS_SRIO_PCIE_BOOT_defconfig -F: configs/T2081QDS_defconfig -F: configs/T2081QDS_NAND_defconfig -F: configs/T2081QDS_SDCARD_defconfig -F: configs/T2081QDS_SPIFLASH_defconfig -F: configs/T2081QDS_SRIO_PCIE_BOOT_defconfig - -T2080QDS_SECURE_BOOT BOARD -M: Ruchika Gupta -S: Maintained -F: configs/T2080QDS_SECURE_BOOT_defconfig diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile deleted file mode 100644 index eb99d921b4a..00000000000 --- a/board/freescale/t208xqds/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright 2013 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_XPL_BUILD -obj-y += spl.o -else -obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o -endif - -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README deleted file mode 100644 index 0d80c6901fb..00000000000 --- a/board/freescale/t208xqds/README +++ /dev/null @@ -1,292 +0,0 @@ -The T2080QDS is a high-performance computing evaluation, development and -test platform supporting the T2080 QorIQ Power Architecture processor. - -T2080 SoC Overview ------------------- -The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power -Architecture processor cores with high-performance datapath acceleration -logic and network and peripheral bus interfaces required for networking, -telecom/datacom, wireless infrastructure, and mil/aerospace applications. - -T2080 includes the following functions and features: - - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - - Hierarchical interconnect fabric - - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - - Data Path Acceleration Architecture (DPAA) incorporating acceleration - - 16 SerDes lanes up to 10.3125 GHz - - 8 Ethernet interfaces, supporting combinations of the following: - - Up to four 10 Gbps Ethernet MACs - - Up to eight 1 Gbps Ethernet MACs - - Up to four 2.5 Gbps Ethernet MACs - - High-speed peripheral interfaces - - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - - Additional peripheral interfaces - - Two serial ATA (SATA 2.0) controllers - - Two high-speed USB 2.0 controllers with integrated PHY - - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - - Enhanced serial peripheral interface (eSPI) - - Four I2C controllers - - Four 2-pin UARTs or two 4-pin UARTs - - Integrated Flash Controller supporting NAND and NOR flash - - Three eight-channel DMA engines - - Support for hardware virtualization and partitioning enforcement - - QorIQ Platform's Trust Architecture 2.0 - -Differences between T2080 and T2081 ------------------------------------ - Feature T2080 T2081 - 1G Ethernet numbers: 8 6 - 10G Ethernet numbers: 4 2 - SerDes lanes: 16 8 - Serial RapidIO,RMan: 2 no - SATA Controller: 2 no - Aurora: yes no - SoC Package: 896-pins 780-pins - - -T2080QDS feature overview -------------------------- -Processor: - - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz -Memory: - - Single memory controller capable of supporting DDR3 and DDR3-LV devices - - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support -Ethernet interfaces: - - Two 1Gbps RGMII on-board ports - - Four 10GBase-R on-board cages - - 1Gbps/2.5Gbps SGMII Riser card - - 10Gbps XAUI Riser card -Accelerator: - - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC -SerDes: - - 16 lanes up to 10.3125GHz - - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, 10GBase-R and XAUI -IFC: - - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA -eSPI: - - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040) -USB: - - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB) -PCIE: - - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) -SATA: - - Two SATA 2.0 ports on-board -SRIO: - - Two Serial RapidIO 2.0 ports up to 5 GHz -eSDHC: - - Supports SD/SDHC/SDXC/eMMC Card -I2C: - - Four I2C controllers. -UART: - - Dual 4-pins UART serial ports -System Logic: - - QIXIS-II FPGA system controll -Debug Features: - - Support Legacy, COP/JTAG, Aurora, Event and EVT -10GBase-R: - - 10GBase-R is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to - a on-board SFP+ cages, which to house optical module (fiber cable) or - direct attach cable(copper), the copper cable is used to emulate - 10GBASE-KR scenario. - So, for 10GBase-R usage, there are two scenarios, one will use fiber cable, - another will use copper cable. An hwconfig env "fsl_10gkr_copper" is - introduced to indicate a 10GBase-R port will use copper cable, and U-Boot - will fixup the dtb accordingly. - It's used as: fsl_10gkr_copper:<10g_mac_name> - The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they - do not have to be coexist in hwconfig. If a MAC is listed in the env - "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable - will be used by default. - for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in - hwconfig, then both four 10GBase-R ports will use copper cable. - set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two - 10GBase-R ports will use copper cable, the other two 10GBase-R ports will use - fiber cable. -1000BASE-KX(1G-KX): - - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane - runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane - in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration - Register 1 (PCCR1), and U-Boot fixup the dtb for kernel to do proper - initialization. - Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC - 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a - MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1' - stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc. - For ex. set "fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10" in - hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode. - -System Memory map ----------------- - -Start Address End Address Description Size -0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB -0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB -0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB -0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB -0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB -0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB -0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB -0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB -0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB -0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB -0xF_0000_0000 0xF_003F_FFFF DCSR 4MB -0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB -0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB -0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB -0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB -0x0_0000_0000 0x0_ffff_ffff DDR 4GB - - -128M NOR Flash memory Map -------------------------- -Start Address End Address Definition Max size -0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB -0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB -0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB -0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB -0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB -0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB -0xEC000000 0xEC01FFFF RCW (alt bank) 128KB -0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB -0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB -0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB -0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB -0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB -0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB -0xE8000000 0xE801FFFF RCW (current bank) 128KB - - -Software configurations and board settings ------------------------------------------- -1. NOR boot: - a. build NOR boot image - $ make T2080QDS_config - $ make - b. program u-boot.bin image to NOR flash - => tftp 1000000 u-boot.bin - => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize - set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot - - Switching between default bank0 and alternate bank4 on NOR flash - To change boot source to vbank4: - by software: run command 'qixis_reset altbank' in U-Boot. - by DIP-switch: set SW6[1:4] = '0100' - - To change boot source to vbank0: - by software: run command 'qixis_reset' in U-Boot. - by DIP-Switch: set SW6[1:4] = '0000' - -2. NAND Boot: - a. build PBL image for NAND boot - $ make T2080QDS_NAND_config - $ make - b. program u-boot-with-spl-pbl.bin to NAND flash - => tftp 1000000 u-boot-with-spl-pbl.bin - => nand erase 0 $filesize - => nand write 1000000 0 $filesize - set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot - -3. SPI Boot: - a. build PBL image for SPI boot - $ make T2080QDS_SPIFLASH_config - $ make - b. program u-boot-with-spl-pbl.bin to SPI flash - => tftp 1000000 u-boot-with-spl-pbl.bin - => sf probe 0 - => sf erase 0 f0000 - => sf write 1000000 0 $filesize - set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot - -4. SD Boot: - a. build PBL image for SD boot - $ make T2080QDS_SDCARD_config - $ make - b. program u-boot-with-spl-pbl.bin to SD/MMC card - => tftp 1000000 u-boot-with-spl-pbl.bin - => mmc write 1000000 8 0x800 - => tftp 1000000 fsl_fman_ucode_T2080_xx.bin - => mmc write 1000000 0x820 80 - set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot - - -2-stage NAND/SPI/SD boot loader -------------------------------- -PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. -SPL further initializes DDR using SPD and environment variables -and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR. -Finally SPL transers control to U-Boot for futher booting. - -SPL has following features: - - Executes within 256K - - No relocation required - -Run time view of SPL framework -------------------------------------------------- -|Area | Address | -------------------------------------------------- -|SecureBoot header | 0xFFFC0000 (32KB) | -------------------------------------------------- -|GD, BD | 0xFFFC8000 (4KB) | -------------------------------------------------- -|ENV | 0xFFFC9000 (8KB) | -------------------------------------------------- -|HEAP | 0xFFFCB000 (50KB) | -------------------------------------------------- -|STACK | 0xFFFD8000 (22KB) | -------------------------------------------------- -|U-Boot SPL | 0xFFFD8000 (160KB) | -------------------------------------------------- - -NAND Flash memory Map on T2080QDS --------------------------------------------------------------- -Start End Definition Size -0x000000 0x0FFFFF U-Boot img 1MB (2 blocks) -0x100000 0x17FFFF U-Boot env 512KB (1 block) -0x180000 0x1FFFFF FMAN ucode 512KB (1 block) - - -Micro SD Card memory Map on T2080QDS ----------------------------------------------------- -Block #blocks Definition Size -0x008 2048 U-Boot img 1MB -0x800 0016 U-Boot env 8KB -0x820 0128 FMAN ucode 64KB - - -SPI Flash memory Map on T2080QDS ----------------------------------------------------- -Start End Definition Size -0x000000 0x0FFFFF U-Boot img 1MB -0x100000 0x101FFF U-Boot env 8KB -0x110000 0x11FFFF FMAN ucode 64KB - - -How to update the ucode of Freescale FMAN ------------------------------------------ -=> tftp 1000000 fsl_fman_ucode_t2080_xx.bin -=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize - - -For more details, please refer to T2080QDS User Guide and access -website www.freescale.com and Freescale QorIQ SDK Infocenter document. - -Device tree support and how to enable it for different configs --------------------------------------------------------------- -Device tree support is available for t2080qds for below mentioned boot, -1. NOR Boot -2. NAND Boot -3. SD Boot -4. SPIFLASH Boot - -To enable device tree support for other boot, below configs need to be -enabled in relative defconfig file, -1. CONFIG_DEFAULT_DEVICE_TREE="t2080qds" (Change default device tree name if required) -2. CONFIG_OF_CONTROL -3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at - CFG_RESET_VECTOR_ADDRESS - 0xffc - -If device tree support is enabled in defconfig, -1. use 'u-boot.bin' for NOR boot. -2. use 'u-boot-with-spl-pbl.bin' for other boot. diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c deleted file mode 100644 index 77c8ce0c870..00000000000 --- a/board/freescale/t208xqds/ddr.c +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 1) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - /* - * we use identical timing for all slots. If needed, change the code - * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; - */ - if (popts->registered_dimm_en) - pbsp = rdimms[0]; - else - pbsp = udimms[0]; - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks && - (pdimm->rank_density >> 30) >= pbsp->rank_gb) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found"); - printf("for data rate %lu MT/s\n", ddr_freq); - printf("Trying to use the highest speed (%u) parameters\n", - pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" - "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " - "wrlvl_ctrl_3 0x%x\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, - pbsp->wrlvl_ctl_3); - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); - - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x64; -} - -int dram_init(void) -{ - phys_size_t dram_size; - -#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) - puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); -#else - /* DDR has been initialised by first stage boot loader */ - dram_size = fsl_ddr_sdram_size(); -#endif - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - gd->ram_size = dram_size; - - return 0; -} diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h deleted file mode 100644 index 9dd39813bf0..00000000000 --- a/board/freescale/t208xqds/ddr.h +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ - -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | - */ - {2, 1200, 0, 10, 7, 0x0708090a, 0x0b0c0d09}, - {2, 1400, 0, 10, 7, 0x08090a0c, 0x0d0e0f0a}, - {2, 1700, 0, 10, 8, 0x090a0b0c, 0x0e10110c}, - {2, 1900, 0, 10, 8, 0x090b0c0f, 0x1012130d}, - {2, 2140, 0, 10, 8, 0x090b0c0f, 0x1012130d}, - {1, 1200, 0, 10, 7, 0x0808090a, 0x0b0c0c0a}, - {1, 1500, 0, 10, 6, 0x07070809, 0x0a0b0b09}, - {1, 1600, 0, 10, 8, 0x090b0b0d, 0x0d0e0f0b}, - {1, 1700, 0, 8, 8, 0x080a0a0c, 0x0c0d0e0a}, - {1, 1900, 0, 10, 8, 0x090a0c0d, 0x0e0f110c}, - {1, 2140, 0, 8, 8, 0x090a0b0d, 0x0e0f110b}, - {} -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | - */ - /* TODO: need tuning these parameters if RDIMM is used */ - {4, 1350, 0, 10, 9, 0x08070605, 0x06070806}, - {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906}, - {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, - {2, 1350, 0, 10, 9, 0x08070605, 0x06070806}, - {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, - {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, - {1, 1350, 0, 10, 9, 0x08070605, 0x06070806}, - {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, - {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -static const struct board_specific_parameters *rdimms[] = { - rdimm0, -}; -#endif diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c deleted file mode 100644 index b55078c8fe1..00000000000 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ /dev/null @@ -1,723 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - * - * Shengzhou Liu - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/qixis.h" -#include "../common/fman.h" -#include "t208xqds_qixis.h" -#include - -#define EMI_NONE 0xFFFFFFFF -#define EMI1_RGMII1 0 -#define EMI1_RGMII2 1 -#define EMI1_SLOT1 2 -#if defined(CONFIG_TARGET_T2080QDS) -#define EMI1_SLOT2 6 -#define EMI1_SLOT3 3 -#define EMI1_SLOT4 4 -#define EMI1_SLOT5 5 -#define EMI2 7 -#endif - -#define PCCR1_SGMIIA_KX_MASK 0x00008000 -#define PCCR1_SGMIIB_KX_MASK 0x00004000 -#define PCCR1_SGMIIC_KX_MASK 0x00002000 -#define PCCR1_SGMIID_KX_MASK 0x00001000 -#define PCCR1_SGMIIE_KX_MASK 0x00000800 -#define PCCR1_SGMIIF_KX_MASK 0x00000400 -#define PCCR1_SGMIIG_KX_MASK 0x00000200 -#define PCCR1_SGMIIH_KX_MASK 0x00000100 - -static int mdio_mux[NUM_FM_PORTS]; - -static const char * const mdio_names[] = { -#if defined(CONFIG_TARGET_T2080QDS) - "T2080QDS_MDIO_RGMII1", - "T2080QDS_MDIO_RGMII2", - "T2080QDS_MDIO_SLOT1", - "T2080QDS_MDIO_SLOT3", - "T2080QDS_MDIO_SLOT4", - "T2080QDS_MDIO_SLOT5", - "T2080QDS_MDIO_SLOT2", - "T2080QDS_MDIO_10GC", -#endif -}; - -/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ -#if defined(CONFIG_TARGET_T2080QDS) -static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; -#endif - -static const char *t208xqds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name = t208xqds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -struct t208xqds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void t208xqds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - if (muxval < 8) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct t208xqds_mdio *priv = bus->priv; - - t208xqds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct t208xqds_mdio *priv = bus->priv; - - t208xqds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int t208xqds_mdio_reset(struct mii_dev *bus) -{ - struct t208xqds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int t208xqds_mdio_init(char *realbusname, u8 muxval) -{ - struct t208xqds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate t208xqds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate t208xqds private data\n"); - free(bus); - return -1; - } - - bus->read = t208xqds_mdio_read; - bus->write = t208xqds_mdio_write; - bus->reset = t208xqds_mdio_reset; - strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - int phy; - char alias[20]; - char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"}; - char buf[32] = "serdes-1,"; - struct fixed_link f_link; - int media_type = 0; - const char *phyconn; - int off; - - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); -#ifdef CONFIG_TARGET_T2080QDS - serdes_corenet_t *srds_regs = - (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; - u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1); -#endif - u32 srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - phy = fm_info_get_phy_address(port); - switch (port) { -#if defined(CONFIG_TARGET_T2080QDS) - case FM1_DTSEC1: - if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx1"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1"); - strcat(buf, "lane-c,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIH_KX_MASK); - break; - } - case FM1_DTSEC2: - if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx2"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2"); - strcat(buf, "lane-d,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIG_KX_MASK); - break; - } - case FM1_DTSEC9: - if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx9"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9"); - strcat(buf, "lane-a,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIE_KX_MASK); - break; - } - case FM1_DTSEC10: - if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx10"); - fdt_status_okay_by_alias(fdt, - "1gkx_pcs_mdio10"); - strcat(buf, "lane-b,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIF_KX_MASK); - break; - } - if (mdio_mux[port] == EMI1_SLOT2) { - sprintf(alias, "phy_sgmii_s2_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot2"); - } else if (mdio_mux[port] == EMI1_SLOT3) { - sprintf(alias, "phy_sgmii_s3_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot3"); - } - break; - case FM1_DTSEC5: - if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx5"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5"); - strcat(buf, "lane-g,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIC_KX_MASK); - break; - } - case FM1_DTSEC6: - if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx6"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6"); - strcat(buf, "lane-h,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIID_KX_MASK); - break; - } - if (mdio_mux[port] == EMI1_SLOT1) { - sprintf(alias, "phy_sgmii_s1_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot1"); - } else if (mdio_mux[port] == EMI1_SLOT2) { - sprintf(alias, "phy_sgmii_s2_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot2"); - } - break; -#endif - default: - break; - } - if (media_type) { - /* set property for 1000BASE-KX in dtb */ - off = fdt_node_offset_by_compat_reg(fdt, - "fsl,fman-memac-mdio", addr + 0x1000); - fdt_setprop_string(fdt, off, "lane-instance", buf); - } - - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { - switch (srds_s1) { - case 0x66: /* 10GBase-R interface */ - case 0x6b: - case 0x6c: - case 0x6d: - case 0x71: - /* - * Check hwconfig to see what is the media type, there - * are two types, fiber or copper, fix the dtb - * accordingly. - */ - switch (port) { - case FM1_10GEC1: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { - /* it's MAC9 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi9"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9"); - strcat(buf, "lane-a,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - case FM1_10GEC2: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) { - /* it's MAC10 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi10"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10"); - strcat(buf, "lane-b,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - case FM1_10GEC3: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) { - /* it's MAC1 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi1"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1"); - strcat(buf, "lane-c,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - case FM1_10GEC4: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) { - /* it's MAC2 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi2"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2"); - strcat(buf, "lane-d,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - default: - return; - } - - if (!media_type) { - phyconn = fdt_getprop(fdt, offset, - "phy-connection-type", - NULL); - if (is_backplane_mode(phyconn)) { - /* Backplane KR mode: skip fixups */ - printf("Interface %d in backplane KR mode\n", - port); - } else { - /* fixed-link for 10GBase-R fiber cable */ - f_link.phy_id = port; - f_link.duplex = 1; - f_link.link_speed = 10000; - f_link.pause = 0; - f_link.asym_pause = 0; - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", - &f_link, sizeof(f_link)); - } - } else { - /* set property for copper cable */ - off = fdt_node_offset_by_compat_reg(fdt, - "fsl,fman-memac-mdio", addr + 0x1000); - fdt_setprop_string(fdt, off, - "lane-instance", buf); - } - break; - default: - break; - } - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - return; -} - -/* - * This function reads RCW to check if Serdes1{A:H} is configured - * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly - */ -static void initialize_lane_to_slot(void) -{ - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - switch (srds_s1) { -#if defined(CONFIG_TARGET_T2080QDS) - case 0x51: - case 0x5f: - case 0x65: - case 0x6b: - case 0x71: - lane_to_slot[5] = 2; - lane_to_slot[6] = 2; - lane_to_slot[7] = 2; - break; - case 0xa6: - case 0x8e: - case 0x8f: - case 0x82: - case 0x83: - case 0xd3: - case 0xd9: - case 0xcb: - lane_to_slot[6] = 2; - lane_to_slot[7] = 2; - break; - case 0xda: - lane_to_slot[4] = 3; - lane_to_slot[5] = 3; - lane_to_slot[6] = 3; - lane_to_slot[7] = 3; - break; -#endif - default: - break; - } -} - -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, idx, lane, slot, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 rcwsr13 = in_be32(&gur->rcwsr[13]); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - initialize_lane_to_slot(); - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); -#if defined(CONFIG_TARGET_T2080QDS) - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); -#endif - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); - t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == - FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII) - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - else - fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x1b: - case 0x1c: - case 0x95: - case 0xa2: - case 0x94: - /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x50: - case 0x51: - case 0x5e: - case 0x5f: - case 0x64: - case 0x65: - /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x66: - case 0x67: - /* - * 10GBase-R does not need a PHY to work, but to avoid U-Boot - * use default PHY address which is zero to a MAC when it found - * a MAC has no PHY address, we give a PHY address to 10GBase-R - * MAC, and should not use a real XAUI PHY address, since - * MDIO can access it successfully, and then MDIO thinks - * the XAUI card is used for the 10GBase-R MAC, which will cause - * error. - */ - fm_info_set_phy_address(FM1_10GEC1, 4); - fm_info_set_phy_address(FM1_10GEC2, 5); - fm_info_set_phy_address(FM1_10GEC3, 6); - fm_info_set_phy_address(FM1_10GEC4, 7); - break; - case 0x6a: - case 0x6b: - fm_info_set_phy_address(FM1_10GEC1, 4); - fm_info_set_phy_address(FM1_10GEC2, 5); - fm_info_set_phy_address(FM1_10GEC3, 6); - fm_info_set_phy_address(FM1_10GEC4, 7); - /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; - case 0x6c: - case 0x6d: - fm_info_set_phy_address(FM1_10GEC1, 4); - fm_info_set_phy_address(FM1_10GEC2, 5); - /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x70: - case 0x71: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; - case 0xa6: - case 0x8e: - case 0x8f: - case 0x82: - case 0x83: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; - case 0xa4: - case 0x96: - case 0x8a: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - break; -#if defined(CONFIG_TARGET_T2080QDS) - case 0xd9: - case 0xd3: - case 0xcb: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; -#endif - case 0xf2: - /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - default: - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (i == FM1_DTSEC3) - mdio_mux[i] = EMI1_RGMII1; - else if (i == FM1_DTSEC4 || FM1_DTSEC10) - mdio_mux[i] = EMI1_RGMII2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { - idx = i - FM1_10GEC1; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - if (srds_s1 == 0x51) { - lane = serdes_get_first_lane(FSL_SRDS_1, - XAUI_FM1_MAC9 + idx); - } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) { - lane = serdes_get_first_lane(FSL_SRDS_1, - HIGIG_FM1_MAC9 + idx); - } else { - if (i == FM1_10GEC1 || i == FM1_10GEC2) - lane = serdes_get_first_lane(FSL_SRDS_1, - XFI_FM1_MAC9 + idx); - else - lane = serdes_get_first_lane(FSL_SRDS_1, - XFI_FM1_MAC1 + idx); - } - - if (lane < 0) - break; - mdio_mux[i] = EMI2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - - if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) || - (srds_s1 == 0x6a) || (srds_s1 == 0x70) || - (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || - (srds_s1 == 0x71)) { - /* As 10GBase-R is in cage intead of a slot, so - * ensure doesn't disable the corresponding port - */ - break; - } - - slot = lane_to_slot[lane]; - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - break; - default: - break; - } - } - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c deleted file mode 100644 index 287f4650e05..00000000000 --- a/board/freescale/t208xqds/law.c +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#ifdef CFG_SYS_BMAN_MEM_PHYS - SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), -#endif -#ifdef CFG_SYS_QMAN_MEM_PHYS - SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), -#endif -#ifdef QIXIS_BASE_PHYS - SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), -#endif -#ifdef CFG_SYS_DCSRBAR_PHYS - /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), -#endif -#ifdef CFG_SYS_NAND_BASE_PHYS - SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c deleted file mode 100644 index 44ad4e68d9f..00000000000 --- a/board/freescale/t208xqds/spl.c +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/qixis.h" -#include "t208xqds_qixis.h" -#include "../common/spl.h" - -DECLARE_GLOBAL_DATA_PTR; - -phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_L3_SIZE; -} - -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); - - switch (sysclk_conf & 0x0F) { - case QIXIS_SYSCLK_83: - return 83333333; - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - case QIXIS_SYSCLK_150: - return 150000000; - case QIXIS_SYSCLK_160: - return 160000000; - case QIXIS_SYSCLK_166: - return 166666666; - } - return 66666666; -} - -unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); - - switch ((ddrclk_conf & 0x30) >> 4) { - case QIXIS_DDRCLK_100: - return 100000000; - case QIXIS_DDRCLK_125: - return 125000000; - case QIXIS_DDRCLK_133: - return 133333333; - } - return 66666666; -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio, sys_clk, ccb_clk; - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; - - /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ - memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); - - /* Update GD pointer */ - gd = (gd_t *)(CONFIG_SPL_GD_ADDR); - - console_init_f(); - - /* initialize selected port with appropriate baud rate */ - sys_clk = get_board_sys_clk(); - plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; - ccb_clk = sys_clk * plat_ratio / 2; - - ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, - ccb_clk / 16 / CONFIG_BAUDRATE); - -#if defined(CONFIG_SPL_MMC_BOOT) - puts("\nSD boot...\n"); -#elif defined(CONFIG_SPL_SPI_BOOT) - puts("\nSPI boot...\n"); -#elif defined(CONFIG_SPL_NAND_BOOT) - puts("\nNAND boot...\n"); -#endif - - relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - struct bd_info *bd; - - bd = (struct bd_info *)(gd + sizeof(gd_t)); - memset(bd, 0, sizeof(struct bd_info)); - gd->bd = bd; - - arch_cpu_init(); - get_clocks(); - mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, - CONFIG_SPL_RELOC_MALLOC_SIZE); - gd->flags |= GD_FLG_FULL_MALLOC_INIT; - -#ifdef CONFIG_SPL_NAND_BOOT - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); -#endif -#ifdef CONFIG_SPL_MMC_BOOT - mmc_initialize(bd); - mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); -#endif -#ifdef CONFIG_SPL_SPI_BOOT - fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); -#endif - - gd->env_addr = (ulong)(SPL_ENV_ADDR); - gd->env_valid = ENV_VALID; - - i2c_init_all(); - - dram_init(); - -#ifdef CONFIG_SPL_MMC_BOOT - mmc_boot(); -#elif defined(CONFIG_SPL_SPI_BOOT) - fsl_spi_boot(); -#elif defined(CONFIG_SPL_NAND_BOOT) - nand_boot(); -#endif -} diff --git a/board/freescale/t208xqds/t2080_nand_rcw.cfg b/board/freescale/t208xqds/t2080_nand_rcw.cfg deleted file mode 100644 index 52a1652a222..00000000000 --- a/board/freescale/t208xqds/t2080_nand_rcw.cfg +++ /dev/null @@ -1,16 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 - -#For T2080 v1.0 -#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s -#12100017 15000000 00000000 00000000 -#66150002 00008400 e8104000 c1000000 -#00000000 00000000 00000000 000307fc -#00000000 00000000 00000000 00000004 - -#For T2080 v1.1 -#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s -0c070012 0e000000 00000000 00000000 -66150002 00000000 e8104000 c1000000 -00000000 00000000 00000000 000307fc -00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xqds/t2080_sd_rcw.cfg b/board/freescale/t208xqds/t2080_sd_rcw.cfg deleted file mode 100644 index 73f53faa259..00000000000 --- a/board/freescale/t208xqds/t2080_sd_rcw.cfg +++ /dev/null @@ -1,16 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 - -#For T2080 v1.0 -#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s -#12100017 15000000 00000000 00000000 -#66150002 00008400 e8104000 c1000000 -#00000000 00000000 00000000 000307fc -#00000000 00000000 00000000 00000004 - -#For T2080 v1.1 -#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s -0c070012 0e000000 00000000 00000000 -66150002 00000000 68104000 c1000000 -00000000 00000000 00000000 000307fc -00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xqds/t2080_spi_rcw.cfg b/board/freescale/t208xqds/t2080_spi_rcw.cfg deleted file mode 100644 index 8474c8ef7ce..00000000000 --- a/board/freescale/t208xqds/t2080_spi_rcw.cfg +++ /dev/null @@ -1,16 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 - -#For T2080 v1.0 -#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s -#12100017 15000000 00000000 00000000 -#66150002 00008400 e8104000 c1000000 -#00000000 00000000 00000000 000307fc -#00000000 00000000 00000000 00000004 - -#For T2080 v1.1 -#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s -0c070012 0e000000 00000000 00000000 -66150002 00000000 58104000 c1000000 -00000000 00000000 00000000 000307fc -00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xqds/t2081_nand_rcw.cfg b/board/freescale/t208xqds/t2081_nand_rcw.cfg deleted file mode 100644 index a2d5ecf4adc..00000000000 --- a/board/freescale/t208xqds/t2081_nand_rcw.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -#Default SerDes Protocol: 0x6C -#Core/DDR: 1533Mhz/2133MT/s -12100017 15000000 00000000 00000000 -6c000002 00008000 e8104000 c1000000 -00000000 00000000 00000000 000307fc -00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xqds/t2081_sd_rcw.cfg b/board/freescale/t208xqds/t2081_sd_rcw.cfg deleted file mode 100644 index daced6796ba..00000000000 --- a/board/freescale/t208xqds/t2081_sd_rcw.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -#Default SerDes Protocol: 0x6C -#Core/DDR: 1533Mhz/2133MT/s -12100017 15000000 00000000 00000000 -6c000002 00008000 68104000 c1000000 -00000000 00000000 00000000 000307fc -00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xqds/t2081_spi_rcw.cfg b/board/freescale/t208xqds/t2081_spi_rcw.cfg deleted file mode 100644 index 79ba1f1ab77..00000000000 --- a/board/freescale/t208xqds/t2081_spi_rcw.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -#Default SerDes Protocol: 0x6C -#Core/DDR: 1533Mhz/2133MT/s -12100017 15000000 00000000 00000000 -6c000002 00008000 58104000 c1000000 -00000000 00000000 00000000 000307fc -00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xqds/t208x_pbi.cfg b/board/freescale/t208xqds/t208x_pbi.cfg deleted file mode 100644 index 43be8a864e3..00000000000 --- a/board/freescale/t208xqds/t208x_pbi.cfg +++ /dev/null @@ -1,40 +0,0 @@ -# -# Copyright 2013 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.pblimage for more details about how-to configure -# and create PBL boot image -# - -#PBI commands -#Initialize CPC1 -09010000 00200400 -09138000 00000000 -091380c0 00000100 -#512KB SRAM -09010100 00000000 -09010104 fff80009 -09010f00 08000000 -#enable CPC1 -09010000 80000000 -#Configure LAW for CPC1 -09000d00 00000000 -09000d04 fff80000 -09000d08 81000012 -#Initialize eSPI controller, default configuration is slow for eSPI to -#load data, this configuration comes from u-boot eSPI driver. -09110000 80000403 -09110020 2d170008 -09110024 00100008 -09110028 00100008 -0911002c 00100008 -#Errata for slowing down the MDC clock to make it <= 2.5 MHZ -094fc030 00008148 -094fd030 00008148 -#Configure alternate space -09000010 00000000 -09000014 ff000000 -09000018 81000000 -#Flush PBL data -091380c0 00100000 diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c deleted file mode 100644 index 5e71da0e163..00000000000 --- a/board/freescale/t208xqds/t208xqds.c +++ /dev/null @@ -1,426 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2013 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/i2c_mux.h" - -#include "../common/qixis.h" -#include "../common/vsc3316_3308.h" -#include "../common/vid.h" -#include "t208xqds.h" -#include "t208xqds_qixis.h" - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - char buf[64]; - u8 sw; - struct cpu_type *cpu = gd->arch.cpu; - static const char *freq[4] = { - "100.00MHZ(from 8T49N222A)", "125.00MHz", - "156.25MHZ", "100.00MHz" - }; - - printf("Board: %sQDS, ", cpu->name); - sw = QIXIS_READ(arch); - printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4); - printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); - -#ifdef CONFIG_SDCARD - puts("SD/MMC\n"); -#elif CONFIG_SPIFLASH - puts("SPI\n"); -#else - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank%d\n", sw); - else if (sw == 0x8) - puts("Promjet\n"); - else if (sw == 0x9) - puts("NAND\n"); - else - printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); -#endif - - printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver), - qixis_read_tag(buf), (int)qixis_read_minor()); - /* the timestamp string contains "\n" at the end */ - printf(" on %s", qixis_read_time(buf)); - - puts("SERDES Reference Clocks:\n"); - sw = QIXIS_READ(brdcfg[2]); - printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6], - freq[(sw >> 4) & 0x3]); - printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2], - freq[sw & 0x3]); - - return 0; -} - -int i2c_multiplexer_select_vid_channel(u8 channel) -{ - return select_i2c_ch_pca9547(channel, 0); -} - -int brd_mux_lane_to_slot(void) -{ - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_prtcl_s1; - - srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; -#if defined(CONFIG_TARGET_T2080QDS) - u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS2_PRTCL; - srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; -#endif - - switch (srds_prtcl_s1) { - case 0: - /* SerDes1 is not enabled */ - break; -#if defined(CONFIG_TARGET_T2080QDS) - case 0x1b: - case 0x1c: - case 0xa2: - /* SD1(A:D) => SLOT3 SGMII - * SD1(G:H) => SLOT1 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0x1a); - break; - case 0x94: - case 0x95: - /* SD1(A:B) => SLOT3 SGMII@1.25bps - * SD1(C:D) => SFP Module, SGMII@3.125bps - * SD1(E:H) => SLOT1 SGMII@1.25bps - */ - case 0x96: - /* SD1(A:B) => SLOT3 SGMII@1.25bps - * SD1(C) => SFP Module, SGMII@3.125bps - * SD1(D) => SFP Module, SGMII@1.25bps - * SD1(E:H) => SLOT1 PCIe4 x4 - */ - QIXIS_WRITE(brdcfg[12], 0x3a); - break; - case 0x50: - case 0x51: - /* SD1(A:D) => SLOT3 XAUI - * SD1(E) => SLOT1 PCIe4 - * SD1(F:H) => SLOT2 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0x15); - break; - case 0x66: - case 0x67: - /* SD1(A:D) => 10GBase-R cage - * SD1(E:H) => SLOT1 PCIe4 - */ - QIXIS_WRITE(brdcfg[12], 0xfe); - break; - case 0x6a: - case 0x6b: - /* SD1(A:D) => 10GBase-R cage - * SD1(E) => SLOT1 PCIe4 - * SD1(F:H) => SLOT2 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0xf1); - break; - case 0x6c: - case 0x6d: - /* SD1(A:B) => 10GBase-R cage - * SD1(C:D) => SLOT3 SGMII - * SD1(E:H) => SLOT1 PCIe4 - */ - QIXIS_WRITE(brdcfg[12], 0xda); - break; - case 0x6e: - /* SD1(A:B) => SFP Module, 10GBase-R - * SD1(C:D) => SLOT3 SGMII - * SD1(E:F) => SLOT1 PCIe4 x2 - * SD1(G:H) => SLOT2 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0xd9); - break; - case 0xda: - /* SD1(A:H) => SLOT3 PCIe3 x8 - */ - QIXIS_WRITE(brdcfg[12], 0x0); - break; - case 0xc8: - /* SD1(A) => SLOT3 PCIe3 x1 - * SD1(B) => SFP Module, SGMII@1.25bps - * SD1(C:D) => SFP Module, SGMII@3.125bps - * SD1(E:F) => SLOT1 PCIe4 x2 - * SD1(G:H) => SLOT2 SGMII - */ - QIXIS_WRITE(brdcfg[12], 0x79); - break; - case 0xab: - /* SD1(A:D) => SLOT3 PCIe3 x4 - * SD1(E:H) => SLOT1 PCIe4 x4 - */ - QIXIS_WRITE(brdcfg[12], 0x1a); - break; -#endif - default: - printf("WARNING: unsupported for SerDes1 Protocol %d\n", - srds_prtcl_s1); - return -1; - } - -#ifdef CONFIG_TARGET_T2080QDS - switch (srds_prtcl_s2) { - case 0: - /* SerDes2 is not enabled */ - break; - case 0x01: - case 0x02: - /* SD2(A:H) => SLOT4 PCIe1 */ - QIXIS_WRITE(brdcfg[13], 0x10); - break; - case 0x15: - case 0x16: - /* - * SD2(A:D) => SLOT4 PCIe1 - * SD2(E:F) => SLOT5 PCIe2 - * SD2(G:H) => SATA1,SATA2 - */ - QIXIS_WRITE(brdcfg[13], 0xb0); - break; - case 0x18: - /* - * SD2(A:D) => SLOT4 PCIe1 - * SD2(E:F) => SLOT5 Aurora - * SD2(G:H) => SATA1,SATA2 - */ - QIXIS_WRITE(brdcfg[13], 0x78); - break; - case 0x1f: - /* - * SD2(A:D) => SLOT4 PCIe1 - * SD2(E:H) => SLOT5 PCIe2 - */ - QIXIS_WRITE(brdcfg[13], 0xa0); - break; - case 0x29: - case 0x2d: - case 0x2e: - /* - * SD2(A:D) => SLOT4 SRIO2 - * SD2(E:H) => SLOT5 SRIO1 - */ - QIXIS_WRITE(brdcfg[13], 0xa0); - break; - case 0x36: - /* - * SD2(A:D) => SLOT4 SRIO2 - * SD2(E:F) => Aurora - * SD2(G:H) => SATA1,SATA2 - */ - QIXIS_WRITE(brdcfg[13], 0x78); - break; - default: - printf("WARNING: unsupported for SerDes2 Protocol %d\n", - srds_prtcl_s2); - return -1; - } -#endif - return 0; -} - -static void esdhc_adapter_card_ident(void) -{ - u8 card_id, value; - - card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; - - switch (card_id) { - case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: - value = QIXIS_READ(brdcfg[5]); - value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); - QIXIS_WRITE(brdcfg[5], value); - break; - case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: - value = QIXIS_READ(pwr_ctl[1]); - value |= QIXIS_EVDD_BY_SDHC_VS; - QIXIS_WRITE(pwr_ctl[1], value); - break; - case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: - value = QIXIS_READ(brdcfg[5]); - value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); - QIXIS_WRITE(brdcfg[5], value); - break; - default: - break; - } -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CFG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - /* Disable remote I2C connection to qixis fpga */ - QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); - - /* - * Adjust core voltage according to voltage ID - * This function changes I2C mux to channel 2. - */ - if (adjust_vdd(0)) - printf("Warning: Adjusting core voltage failed.\n"); - - brd_mux_lane_to_slot(); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - esdhc_adapter_card_ident(); - return 0; -} - -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); -#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT - /* use accurate clock measurement */ - int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]); - int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); - u32 val; - - val = freq * base; - if (val) { - debug("SYS Clock measurement is: %d\n", val); - return val; - } else { - printf("Warning: SYS clock measurement is invalid, "); - printf("using value from brdcfg1.\n"); - } -#endif - - switch (sysclk_conf & 0x0F) { - case QIXIS_SYSCLK_83: - return 83333333; - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - case QIXIS_SYSCLK_150: - return 150000000; - case QIXIS_SYSCLK_160: - return 160000000; - case QIXIS_SYSCLK_166: - return 166666666; - } - return 66666666; -} - -unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); -#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT - /* use accurate clock measurement */ - int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]); - int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); - u32 val; - - val = freq * base; - if (val) { - debug("DDR Clock measurement is: %d\n", val); - return val; - } else { - printf("Warning: DDR clock measurement is invalid, "); - printf("using value from brdcfg1.\n"); - } -#endif - - switch ((ddrclk_conf & 0x30) >> 4) { - case QIXIS_DDRCLK_100: - return 100000000; - case QIXIS_DDRCLK_125: - return 125000000; - case QIXIS_DDRCLK_133: - return 133333333; - } - return 66666666; -} - -int misc_init_r(void) -{ - return 0; -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); - fsl_fdt_fixup_dr_usb(blob, bd); - -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif - fdt_fixup_board_enet(blob); -#endif - - return 0; -} diff --git a/board/freescale/t208xqds/t208xqds.h b/board/freescale/t208xqds/t208xqds.h deleted file mode 100644 index 50ebb6f6f98..00000000000 --- a/board/freescale/t208xqds/t208xqds.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011-2013 Freescale Semiconductor, Inc. - */ - -#ifndef __CORENET_DS_H__ -#define __CORENET_DS_H__ - -void fdt_fixup_board_enet(void *blob); -void pci_of_setup(void *blob, struct bd_info *bd); - -#endif diff --git a/board/freescale/t208xqds/t208xqds_qixis.h b/board/freescale/t208xqds/t208xqds_qixis.h deleted file mode 100644 index 66651422031..00000000000 --- a/board/freescale/t208xqds/t208xqds_qixis.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __T208xQDS_QIXIS_H__ -#define __T208xQDS_QIXIS_H__ - -/* Definitions of QIXIS Registers for T208xQDS */ - -#define QIXIS_SRDS1CLK_122 0x5a -#define QIXIS_SRDS1CLK_125 0x5e - -/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ -#define BRDCFG4_EMISEL_MASK 0xE0 -#define BRDCFG4_EMISEL_SHIFT 5 - -/* SYSCLK */ -#define QIXIS_SYSCLK_66 0x0 -#define QIXIS_SYSCLK_83 0x1 -#define QIXIS_SYSCLK_100 0x2 -#define QIXIS_SYSCLK_125 0x3 -#define QIXIS_SYSCLK_133 0x4 -#define QIXIS_SYSCLK_150 0x5 -#define QIXIS_SYSCLK_160 0x6 -#define QIXIS_SYSCLK_166 0x7 - -/* DDRCLK */ -#define QIXIS_DDRCLK_66 0x0 -#define QIXIS_DDRCLK_100 0x1 -#define QIXIS_DDRCLK_125 0x2 -#define QIXIS_DDRCLK_133 0x3 - -#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */ - -#define BRDCFG9_SFP_TX_EN 0x10 - -#define BRDCFG12_SD3EN_MASK 0x20 -#define BRDCFG12_SD3MX_MASK 0x08 -#define BRDCFG12_SD3MX_SLOT5 0x08 -#define BRDCFG12_SD3MX_SLOT6 0x00 -#define BRDCFG12_SD4EN_MASK 0x04 -#define BRDCFG12_SD4MX_MASK 0x03 -#define BRDCFG12_SD4MX_SLOT7 0x02 -#define BRDCFG12_SD4MX_SLOT8 0x01 -#define BRDCFG12_SD4MX_AURO_SATA 0x00 -#endif diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c deleted file mode 100644 index 08c140afc68..00000000000 --- a/board/freescale/t208xqds/tlb.c +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008-2013 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, - CFG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, - CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, - CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, - CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) - /* - * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the - * SRAM is at 0xfff00000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) - /* - * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the - * space is at 0xfff00000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, - CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), -#else - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), - - /* *I*G* - Flash, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - -#ifndef CONFIG_XPL_BUILD - /* *I*G* - PCIe 1, 0x80000000 */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_512M, 1), - - /* *I*G* - PCIe 2, 0xa0000000 */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE2_MEM_VIRT, CFG_SYS_PCIE2_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCIe 3, 0xb0000000 */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE3_MEM_VIRT, CFG_SYS_PCIE3_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCIe 4, 0xc0000000 */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256K, 1), - - /* Bman/Qman */ -#ifdef CFG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, - CFG_SYS_BMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_16M, 1), -#endif -#ifdef CFG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 11, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, - CFG_SYS_QMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 12, BOOKE_PAGESZ_16M, 1), -#endif -#endif -#ifdef CFG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 13, BOOKE_PAGESZ_32M, 1), -#endif -#ifdef CFG_SYS_NAND_BASE - /* - * *I*G - NAND - * entry 14 and 15 has been used hard coded, they will be disabled - * in cpu_init_f, so we use entry 16 for nand. - */ - SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 16, BOOKE_PAGESZ_64K, 1), -#endif -#ifdef QIXIS_BASE_PHYS - SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 17, BOOKE_PAGESZ_4K, 1), -#endif -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE - /* - * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for - * fetching ucode and ENV from master - */ - SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, - CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, - 0, 18, BOOKE_PAGESZ_1M, 1), -#endif - -#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD) - SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 19, BOOKE_PAGESZ_2G, 1) -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t208xrdb/Kconfig b/board/freescale/t208xrdb/Kconfig deleted file mode 100644 index 35d884e6ccb..00000000000 --- a/board/freescale/t208xrdb/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_T2080RDB - -config SYS_BOARD - default "t208xrdb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "T208xRDB" - -config T2080RDB_REV_D - bool "Support for T2080RDB revisions D and up" - -endif diff --git a/board/freescale/t208xrdb/MAINTAINERS b/board/freescale/t208xrdb/MAINTAINERS deleted file mode 100644 index 5be7a25c03b..00000000000 --- a/board/freescale/t208xrdb/MAINTAINERS +++ /dev/null @@ -1,14 +0,0 @@ -T208XRDB BOARD -M: Shengzhou Liu -S: Maintained -F: board/freescale/t208xrdb/ -F: include/configs/T208xRDB.h -F: configs/T2080RDB_defconfig -F: configs/T2080RDB_NAND_defconfig -F: configs/T2080RDB_SDCARD_defconfig -F: configs/T2080RDB_SPIFLASH_defconfig -F: configs/T2080RDB_SRIO_PCIE_BOOT_defconfig -F: configs/T2080RDB_revD_defconfig -F: configs/T2080RDB_revD_NAND_defconfig -F: configs/T2080RDB_revD_SDCARD_defconfig -F: configs/T2080RDB_revD_SPIFLASH_defconfig diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile deleted file mode 100644 index e5ef250c8b2..00000000000 --- a/board/freescale/t208xrdb/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright 2014 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_XPL_BUILD -obj-y += spl.o -else -obj-$(CONFIG_TARGET_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o -endif - -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README deleted file mode 100644 index 533054bfe19..00000000000 --- a/board/freescale/t208xrdb/README +++ /dev/null @@ -1,288 +0,0 @@ -T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC. -It can work in two mode: standalone mode and PCIe endpoint mode. - -T2080 SoC Overview ------------------- -The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power -Architecture processor cores with high-performance datapath acceleration -logic and network and peripheral bus interfaces required for networking, -telecom/datacom, wireless infrastructure, and mil/aerospace applications. - -T2080 includes the following functions and features: - - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - - Hierarchical interconnect fabric - - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - - Data Path Acceleration Architecture (DPAA) incorporating acceleration - - 16 SerDes lanes up to 10.3125 GHz - - 8 Ethernet interfaces, supporting combinations of the following: - - Up to four 10 Gbps Ethernet MACs - - Up to eight 1 Gbps Ethernet MACs - - Up to four 2.5 Gbps Ethernet MACs - - High-speed peripheral interfaces - - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - - Additional peripheral interfaces - - Two serial ATA (SATA 2.0) controllers - - Two high-speed USB 2.0 controllers with integrated PHY - - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - - Enhanced serial peripheral interface (eSPI) - - Four I2C controllers - - Four 2-pin UARTs or two 4-pin UARTs - - Integrated Flash Controller supporting NAND and NOR flash - - Three eight-channel DMA engines - - Support for hardware virtualization and partitioning enforcement - - QorIQ Platform's Trust Architecture 2.0 - -User Guide ----------- -The T2080RDB User Guide is available on the web at -https://www.nxp.com/docs/en/user-guide/T2080RDBPCUG.pdf - -Differences between T2080 and T2081 ------------------------------------ - Feature T2080 T2081 - 1G Ethernet numbers: 8 6 - 10G Ethernet numbers: 4 2 - SerDes lanes: 16 8 - Serial RapidIO,RMan: 2 no - SATA Controller: 2 no - Aurora: yes no - SoC Package: 896-pins 780-pins - - -T2080PCIe-RDB board Overview ----------------------------- - - SERDES Configuration - - SerDes-1 Lane A-B: to two 10GBase-R fiber (MAC9 & MAC10) - - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) - - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) - - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) - - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2) - - SerDes-2 Lane G-H: to SATA1 & SATA2 - - Ethernet - - Two on-board 10M/100M/1G RGMII ethernet ports - - Two on-board 10GBase-R fiber ports - - Two on-board 10Gbps Base-T copper ports - - DDR Memory - - Supports 72bit 4GB DDR3-LP SODIMM - - PCIe - - One PCIe x4 gold-finger - - One PCIe x4 connector - - One PCIe x2 end-point device (C293 Crypto co-processor) - - IFC/Local Bus - - NOR: 128MB 16-bit NOR Flash - - NAND: 1GB 8-bit NAND flash - - CPLD: for system controlling with programable header on-board - - SATA - - Two SATA 2.0 onnectors on-board - - USB - - Supports two USB 2.0 ports with integrated PHYs - - Two type A ports with 5V@1.5A per port. - - SDHC - - one TF-card connector on-board - - SPI - - On-board 64MB SPI flash - - Other - - Two Serial ports - - Four I2C ports - - -System Memory map ------------------ -Start Address End Address Description Size -0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB -0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB -0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB -0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB -0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB -0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB -0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB -0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB -0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB -0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB -0xF_0000_0000 0xF_003F_FFFF DCSR 4MB -0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB -0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB -0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB -0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB -0x0_0000_0000 0x0_ffff_ffff DDR 4GB - - -128M NOR Flash memory Map -------------------------- -Start Address End Address Definition Max size -0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB -0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB -0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB -0xEFE00000 0xEFE3FFFF PHY CS4315 firmware 256KB -0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB -0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB -0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB -0xEC000000 0xEC01FFFF RCW (alt bank) 128KB -0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB -0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB -0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB -0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB -0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB -0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB -0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB -0xE8000000 0xE801FFFF RCW (current bank) 128KB - - -T2080PCIe-RDB Ethernet Port Map -------------------------------- -Label In Uboot In Linux FMan Address Comments PHY -ETH0 FM1@GTEC1 fm1-mac9 0xfe4f0000 10G SFP+ (CS4315) -ETH1 FM1@GTEC2 fm1-mac10 0xfe4f2000 10G SFP+ (CS4315) -ETH2 FM1@GTEC3 fm1-mac1 0xfe4e0000 10G Base-T (AQ1202) -ETH3 FM1@GTEC4 fm1-mac2 0xfe4e2000 10G Base-T (AQ1202) -ETH4 FM1@DTSEC3 fm1-mac3 0xfe4e4000 1G RGMII (RTL8211E) -ETH5 FM1@DTSEC4 fm1-mac4 0xfe4e6000 1G RGMII (RTL8211E) - - -T2080PCIe-RDB Default DIP-Switch setting ----------------------------------------- -SW1[1:8] = '00010011' -SW2[1:8] = '10111111' -SW3[1:8] = '11100001' - -Software configurations and board settings ------------------------------------------- -1. NOR boot: - a. build NOR boot image - $ make T2080RDB_config - $ make - b. program u-boot.bin image to NOR flash - => tftp 1000000 u-boot.bin - => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize - set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot - - Switching between default bank and alternate bank on NOR flash - To change boot source to vbank4: - via software: run command 'cpld reset altbank' in U-Boot. - via DIP-switch: set SW3[5:7] = '100' - - To change boot source to vbank0: - via software: run command 'cpld reset' in U-Boot. - via DIP-Switch: set SW3[5:7] = '000' - -2. NAND Boot: - a. build PBL image for NAND boot - $ make T2080RDB_NAND_config - $ make - b. program u-boot-with-spl-pbl.bin to NAND flash - => tftp 1000000 u-boot-with-spl-pbl.bin - => nand erase 0 d0000 - => nand write 1000000 0 $filesize - set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot - -3. SPI Boot: - a. build PBL image for SPI boot - $ make T2080RDB_SPIFLASH_config - $ make - b. program u-boot-with-spl-pbl.bin to SPI flash - => tftp 1000000 u-boot-with-spl-pbl.bin - => sf probe 0 - => sf erase 0 d0000 - => sf write 1000000 0 $filesize - set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot - -4. SD Boot: - a. build PBL image for SD boot - $ make T2080RDB_SDCARD_config - $ make - b. program u-boot-with-spl-pbl.bin to micro-SD/TF card - => tftp 1000000 u-boot-with-spl-pbl.bin - => mmc write 1000000 8 0x800 - set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot - - -2-stage NAND/SPI/SD boot loader -------------------------------- -PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. -SPL further initializes DDR using SPD and environment variables -and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR. -Finally SPL transers control to U-Boot for futher booting. - -SPL has following features: - - Executes within 256K - - No relocation required - -Run time view of SPL framework -------------------------------------------------- -|Area | Address | -------------------------------------------------- -|SecureBoot header | 0xFFFC0000 (32KB) | -------------------------------------------------- -|GD, BD | 0xFFFC8000 (4KB) | -------------------------------------------------- -|ENV | 0xFFFC9000 (8KB) | -------------------------------------------------- -|HEAP | 0xFFFCB000 (50KB) | -------------------------------------------------- -|STACK | 0xFFFD8000 (22KB) | -------------------------------------------------- -|U-Boot SPL | 0xFFFD8000 (160KB) | -------------------------------------------------- - -NAND Flash memory Map on T2080RDB --------------------------------------------------------------- -Start End Definition Size -0x000000 0x0FFFFF U-Boot img 1MB (2 blocks) -0x100000 0x17FFFF U-Boot env 512KB (1 block) -0x180000 0x1FFFFF FMAN ucode 512KB (1 block) -0x200000 0x27FFFF CS4315 ucode 512KB (1 block) - - -Micro SD Card memory Map on T2080RDB ----------------------------------------------------- -Block #blocks Definition Size -0x008 2048 U-Boot img 1MB -0x800 0016 U-Boot env 8KB -0x820 0128 FMAN ucode 64KB -0x8a0 0512 CS4315 ucode 256KB - - -SPI Flash memory Map on T2080RDB ----------------------------------------------------- -Start End Definition Size -0x000000 0x0FFFFF U-Boot img 1MB -0x100000 0x101FFF U-Boot env 8KB -0x110000 0x11FFFF FMAN ucode 64KB -0x120000 0x15FFFF CS4315 ucode 256KB - - -How to update the ucode of Cortina CS4315/CS4340 10G PHY --------------------------------------------------------- -=> tftp 1000000 CS4315-CS4340-PHY-ucode.txt -=> pro off all;era 0xefe00000 0xefefffff;cp.b 1000000 0xefe00000 $filesize - - -How to update the ucode of Freescale FMAN ------------------------------------------ -=> tftp 1000000 fsl_fman_ucode_t2080_r1.0.bin -=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize - - -For more details, please refer to T2080PCIe-RDB User Guide and access -website www.freescale.com and Freescale QorIQ SDK Infocenter document. - -Device tree support and how to enable it for different configs --------------------------------------------------------------- -Device tree support is available for t2080rdb for below mentioned boot, -1. NOR Boot -2. NAND Boot -3. SD Boot -4. SPIFLASH Boot - -To enable device tree support for other boot, below configs need to be -enabled in relative defconfig file, -1. CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" (Change default device tree name if required) -2. CONFIG_OF_CONTROL -3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at - CFG_RESET_VECTOR_ADDRESS - 0xffc - -If device tree support is enabled in defconfig, -1. use 'u-boot.bin' for NOR boot. -2. use 'u-boot-with-spl-pbl.bin' for other boot. diff --git a/board/freescale/t208xrdb/cpld.c b/board/freescale/t208xrdb/cpld.c deleted file mode 100644 index 838d88d977e..00000000000 --- a/board/freescale/t208xrdb/cpld.c +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor - * - * Freescale T2080RDB board-specific CPLD controlling supports. - */ - -#include -#include -#include -#include -#include "cpld.h" - -u8 cpld_read(unsigned int reg) -{ - void *p = (void *)CFG_SYS_CPLD_BASE; - - return in_8(p + reg); -} - -void cpld_write(unsigned int reg, u8 value) -{ - void *p = (void *)CFG_SYS_CPLD_BASE; - - out_8(p + reg, value); -} - -/* Set the boot bank to the alternate bank */ -void cpld_set_altbank(void) -{ - u8 reg = CPLD_READ(flash_csr); - - reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; - CPLD_WRITE(flash_csr, reg); - CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET); -} - -/* Set the boot bank to the default bank */ -void cpld_set_defbank(void) -{ - u8 reg = CPLD_READ(flash_csr); - - reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; - CPLD_WRITE(flash_csr, reg); - CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET); -} - -int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - int rc = 0; - - if (argc <= 1) - return cmd_usage(cmdtp); - - if (strcmp(argv[1], "reset") == 0) { - if (strcmp(argv[2], "altbank") == 0) - cpld_set_altbank(); - else - cpld_set_defbank(); - } else { - rc = cmd_usage(cmdtp); - } - - return rc; -} - -U_BOOT_CMD( - cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, - "Reset the board or alternate bank", - "reset: reset to default bank\n" - "cpld reset altbank: reset to alternate bank\n" -); diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h deleted file mode 100644 index 3139c2b85fd..00000000000 --- a/board/freescale/t208xrdb/cpld.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor - * Copyright 2021 NXP - */ - -/* - * CPLD register set of T2080RDB board-specific. - */ -struct cpld_data { - u8 chip_id1; /* 0x00 - Chip ID1 register */ - u8 chip_id2; /* 0x01 - Chip ID2 register */ - u8 hw_ver; /* 0x02 - Hardware Revision Register */ - u8 sw_ver; /* 0x03 - Software Revision register */ - u8 res0[12]; /* 0x04 - 0x0F - not used */ - u8 reset_ctl; /* 0x10 - Reset control Register */ - u8 flash_csr; /* 0x11 - Flash control and status register */ - u8 thermal_csr; /* 0x12 - Thermal control and status register */ - u8 led_csr; /* 0x13 - LED control and status register */ - u8 sfp_csr; /* 0x14 - SFP+ control and status register */ - u8 misc_csr; /* 0x15 - Misc control and status register */ - u8 boot_or; /* 0x16 - Boot config override register */ - u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */ - u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */ -}; - -u8 cpld_read(unsigned int reg); -void cpld_write(unsigned int reg, u8 value); - -#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) -#define CPLD_WRITE(reg, value) \ - cpld_write(offsetof(struct cpld_data, reg), value) - -/* CPLD on IFC */ -#define CPLD_LBMAP_MASK 0x3F -#define CPLD_BANK_SEL_MASK 0x07 -#define CPLD_BANK_OVERRIDE 0x40 -#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ -#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */ -#define CPLD_LBMAP_RESET 0xFF -#define CPLD_LBMAP_SHIFT 0x03 -#define CPLD_BOOT_SEL 0x80 - -/* RSTCON Register */ -#define CPLD_RSTCON_EDC_RST 0x04 - -/* MISCCSR Register */ -#define CPLD_MISC_POR_EN 0x30 diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c deleted file mode 100644 index cc9586eaa14..00000000000 --- a/board/freescale/t208xrdb/ddr.c +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 1) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - pbsp = udimms[0]; - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks && - (pdimm->rank_density >> 30) >= pbsp->rank_gb) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found"); - printf("for data rate %lu MT/s\n", ddr_freq); - printf("Trying to use the highest speed (%u) parameters\n", - pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" - "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " - "wrlvl_ctrl_3 0x%x\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, - pbsp->wrlvl_ctl_3); - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); - - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x54; -} - -int dram_init(void) -{ - phys_size_t dram_size; - -#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) - puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); -#else - /* DDR has been initialised by first stage boot loader */ - dram_size = fsl_ddr_sdram_size(); -#endif - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - gd->ram_size = dram_size; - - return 0; -} diff --git a/board/freescale/t208xrdb/ddr.h b/board/freescale/t208xrdb/ddr.h deleted file mode 100644 index c00f1781667..00000000000 --- a/board/freescale/t208xrdb/ddr.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ - -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | - */ - {2, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a}, - {2, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09}, - {2, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a}, - {2, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a}, - {2, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09}, - {1, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a}, - {1, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09}, - {1, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a}, - {1, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a}, - {1, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; -#endif diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c deleted file mode 100644 index 5223eccb280..00000000000 --- a/board/freescale/t208xrdb/eth_t208xrdb.c +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2021 NXP - * - * Shengzhou Liu - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern u8 get_hw_revision(void); - -/* Disable the MAC5 and MAC6 "fsl,fman-memac" nodes and the two - * "fsl,dpa-ethernet" nodes that reference them. - */ -void fdt_fixup_board_fman_ethernet(void *fdt) -{ - int mac_off, eth_off, i; - char mac_path[2][42] = { - "/soc@ffe000000/fman@400000/ethernet@e8000", - "/soc@ffe000000/fman@400000/ethernet@ea000", - }; - u32 eth_ph; - - for (i = 0; i < 2; i++) { - /* Disable the MAC node */ - mac_off = fdt_path_offset(fdt, mac_path[i]); - if (mac_off < 0) - continue; - fdt_status_disabled(fdt, mac_off); - - /* Disable the fsl,dpa-ethernet node that points to the MAC. - * The fsl,fman-mac property refers to the MAC's phandle. - */ - eth_ph = fdt_get_phandle(fdt, mac_off); - if (eth_ph <= 0) - continue; - - eth_off = fdt_node_offset_by_prop_value(fdt, -1, "fsl,fman-mac", - ð_ph, - sizeof(eth_ph)); - if (eth_off >= 0) - fdt_status_disabled(fdt, eth_off); - } -} - -/* Update the address of the second Aquantia PHY on boards revision D and up. - * Also rename the PHY node to align with the address change. - */ -void fdt_fixup_board_phy(void *fdt) -{ - const char phy_path[] = - "/soc@ffe000000/fman@400000/mdio@fd000/ethernet-phy@1"; - int ret, offset, new_addr = AQR113C_PHY_ADDR2; - char new_name[] = "ethernet-phy@00"; - - if (get_hw_revision() == 'C') - return; - - offset = fdt_path_offset(fdt, phy_path); - if (offset < 0) { - printf("ethernet-phy@1 node not found in the dts\n"); - return; - } - - ret = fdt_setprop(fdt, offset, "reg", &new_addr, sizeof(new_addr)); - if (ret < 0) { - printf("Unable to set 'reg' for node ethernet-phy@1: %s\n", - fdt_strerror(ret)); - return; - } - - sprintf(new_name, "ethernet-phy@%x", new_addr); - ret = fdt_set_name(fdt, offset, new_name); - if (ret < 0) - printf("Unable to rename node ethernet-phy@1: %s\n", - fdt_strerror(ret)); -} - -void fdt_fixup_board_enet(void *fdt) -{ - return; -} diff --git a/board/freescale/t208xrdb/law.c b/board/freescale/t208xrdb/law.c deleted file mode 100644 index e1f570a8935..00000000000 --- a/board/freescale/t208xrdb/law.c +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008-2014 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#ifdef CFG_SYS_BMAN_MEM_PHYS - SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), -#endif -#ifdef CFG_SYS_QMAN_MEM_PHYS - SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), -#endif -#ifdef CFG_SYS_CPLD_BASE_PHYS - SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), -#endif -#ifdef CFG_SYS_DCSRBAR_PHYS - /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), -#endif -#ifdef CFG_SYS_NAND_BASE_PHYS - SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c deleted file mode 100644 index df3b9c6fe40..00000000000 --- a/board/freescale/t208xrdb/spl.c +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/spl.h" - -DECLARE_GLOBAL_DATA_PTR; - -phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_L3_SIZE; -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio, sys_clk, ccb_clk; - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; - - /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ - memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); - - /* Update GD pointer */ - gd = (gd_t *)(CONFIG_SPL_GD_ADDR); - - console_init_f(); - - /* initialize selected port with appropriate baud rate */ - sys_clk = get_board_sys_clk(); - plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; - ccb_clk = sys_clk * plat_ratio / 2; - - ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, - ccb_clk / 16 / CONFIG_BAUDRATE); - -#if defined(CONFIG_SPL_MMC_BOOT) - puts("\nSD boot...\n"); -#elif defined(CONFIG_SPL_SPI_BOOT) - puts("\nSPI boot...\n"); -#elif defined(CONFIG_SPL_NAND_BOOT) - puts("\nNAND boot...\n"); -#endif - - relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - struct bd_info *bd; - - bd = (struct bd_info *)(gd + sizeof(gd_t)); - memset(bd, 0, sizeof(struct bd_info)); - gd->bd = bd; - - arch_cpu_init(); - get_clocks(); - mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, - CONFIG_SPL_RELOC_MALLOC_SIZE); - gd->flags |= GD_FLG_FULL_MALLOC_INIT; - -#ifdef CONFIG_SPL_NAND_BOOT - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); -#endif -#ifdef CONFIG_SPL_MMC_BOOT - mmc_initialize(bd); - mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); -#endif -#ifdef CONFIG_SPL_SPI_BOOT - fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); -#endif - - gd->env_addr = (ulong)(SPL_ENV_ADDR); - gd->env_valid = ENV_VALID; - - i2c_init_all(); - - dram_init(); - -#ifdef CONFIG_SPL_MMC_BOOT - mmc_boot(); -#elif defined(CONFIG_SPL_SPI_BOOT) - fsl_spi_boot(); -#elif defined(CONFIG_SPL_NAND_BOOT) - nand_boot(); -#endif -} diff --git a/board/freescale/t208xrdb/t2080_nand_rcw.cfg b/board/freescale/t208xrdb/t2080_nand_rcw.cfg deleted file mode 100644 index 8096ff9f372..00000000000 --- a/board/freescale/t208xrdb/t2080_nand_rcw.cfg +++ /dev/null @@ -1,19 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 - -#For T2080 v1.0 -#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s -#120c0017 15000000 00000000 00000000 -#66150002 00008400 ec104000 c1000000 -#00000000 00000000 00000000 000307fc -#00000000 00000000 00000000 00000004 - -#For T2080 v1.1 -#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s -#1206001b 15000000 00000000 00000000 - -#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s -1207001b 15000000 00000000 00000000 -66150002 00000000 e8104000 c1000000 -00800000 00000000 00000000 000307fc -00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xrdb/t2080_pbi.cfg b/board/freescale/t208xrdb/t2080_pbi.cfg deleted file mode 100644 index 43be8a864e3..00000000000 --- a/board/freescale/t208xrdb/t2080_pbi.cfg +++ /dev/null @@ -1,40 +0,0 @@ -# -# Copyright 2013 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.pblimage for more details about how-to configure -# and create PBL boot image -# - -#PBI commands -#Initialize CPC1 -09010000 00200400 -09138000 00000000 -091380c0 00000100 -#512KB SRAM -09010100 00000000 -09010104 fff80009 -09010f00 08000000 -#enable CPC1 -09010000 80000000 -#Configure LAW for CPC1 -09000d00 00000000 -09000d04 fff80000 -09000d08 81000012 -#Initialize eSPI controller, default configuration is slow for eSPI to -#load data, this configuration comes from u-boot eSPI driver. -09110000 80000403 -09110020 2d170008 -09110024 00100008 -09110028 00100008 -0911002c 00100008 -#Errata for slowing down the MDC clock to make it <= 2.5 MHZ -094fc030 00008148 -094fd030 00008148 -#Configure alternate space -09000010 00000000 -09000014 ff000000 -09000018 81000000 -#Flush PBL data -091380c0 00100000 diff --git a/board/freescale/t208xrdb/t2080_sd_rcw.cfg b/board/freescale/t208xrdb/t2080_sd_rcw.cfg deleted file mode 100644 index 6309b1d2200..00000000000 --- a/board/freescale/t208xrdb/t2080_sd_rcw.cfg +++ /dev/null @@ -1,19 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 - -#For T2080 v1.0 -#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s -#120c0017 15000000 00000000 00000000 -#66150002 00008400 ec104000 c1000000 -#00000000 00000000 00000000 000307fc -#00000000 00000000 00000000 00000004 - -#For T2080 v1.1 -#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s -#1206001b 15000000 00000000 00000000 - -#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s -1207001b 15000000 00000000 00000000 -66150002 00000000 68104000 c1000000 -00800000 00000000 00000000 000307fc -00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xrdb/t2080_spi_rcw.cfg b/board/freescale/t208xrdb/t2080_spi_rcw.cfg deleted file mode 100644 index f1674958870..00000000000 --- a/board/freescale/t208xrdb/t2080_spi_rcw.cfg +++ /dev/null @@ -1,19 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 - -#For T2080 v1.0 -#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s -#120c0017 15000000 00000000 00000000 -#66150002 00008400 ec104000 c1000000 -#00000000 00000000 00000000 000307fc -#00000000 00000000 00000000 00000004 - -#For T2080 v1.1 -#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s -#1206001b 15000000 00000000 00000000 - -#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s -1207001b 15000000 00000000 00000000 -66150002 00000000 58104000 c1000000 -00800000 00000000 00000000 000307fc -00000000 00000000 00000000 00000004 diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c deleted file mode 100644 index d93edf007ad..00000000000 --- a/board/freescale/t208xrdb/t208xrdb.c +++ /dev/null @@ -1,188 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2013 Freescale Semiconductor, Inc. - * Copyright 2021-2023 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "t208xrdb.h" -#include "cpld.h" -#include "../common/vid.h" - -DECLARE_GLOBAL_DATA_PTR; - -u8 get_hw_revision(void) -{ - u8 ver = CPLD_READ(hw_ver); - - switch (ver) { - default: - case 0x1: - return 'C'; - case 0x0: - return 'D'; - case 0x2: - return 'E'; - } -} - -#if CONFIG_IS_ENABLED(DM_SERIAL) -int get_serial_clock(void) -{ - return get_bus_freq(0) / 2; -} -#endif - -int checkboard(void) -{ - struct cpu_type *cpu = gd->arch.cpu; - static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; - - printf("Board: %sRDB, ", cpu->name); - printf("Board rev: %c CPLD ver: 0x%02x, boot from ", - get_hw_revision(), CPLD_READ(sw_ver)); - -#ifdef CONFIG_SDCARD - puts("SD/MMC\n"); -#elif CONFIG_SPIFLASH - puts("SPI\n"); -#else - u8 reg; - - reg = CPLD_READ(flash_csr); - - if (reg & CPLD_BOOT_SEL) { - puts("NAND\n"); - } else { - reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); - printf("NOR vBank%d\n", reg); - } -#endif - - puts("SERDES Reference Clocks:\n"); - printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); - printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]); - - return 0; -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CFG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - /* - * Adjust core voltage according to voltage ID - * This function changes I2C mux to channel 2. - */ - if (adjust_vdd(0)) - printf("Warning: Adjusting core voltage failed.\n"); - - pci_init(); - - return 0; -} - -int misc_init_r(void) -{ - u8 reg; - - /* Reset CS4315 PHY */ - reg = CPLD_READ(reset_ctl); - reg |= CPLD_RSTCON_EDC_RST; - CPLD_WRITE(reset_ctl, reg); - - /* Enable POR for boards revisions D and up */ - if (get_hw_revision() >= 'D') { - reg = CPLD_READ(misc_csr); - reg |= CPLD_MISC_POR_EN; - CPLD_WRITE(misc_csr, reg); - } - - return 0; -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); - fsl_fdt_fixup_dr_usb(blob, bd); - -#ifdef CONFIG_SYS_DPAA_FMAN - fdt_fixup_board_fman_ethernet(blob); - fdt_fixup_board_enet(blob); - fdt_fixup_board_phy(blob); -#endif - - return 0; -} - -ulong *cs4340_get_fw_addr(void) -{ - ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR; - -#ifdef CONFIG_SYS_CORTINA_FW_IN_NOR - u8 reg; - - reg = CPLD_READ(flash_csr); - if (!(reg & CPLD_BOOT_SEL)) { - reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); - if (reg == 0) - cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR; - else if (reg == 4) - cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK; - } -#endif - - return (ulong *)cortina_fw_addr; -} diff --git a/board/freescale/t208xrdb/t208xrdb.h b/board/freescale/t208xrdb/t208xrdb.h deleted file mode 100644 index 26998898e82..00000000000 --- a/board/freescale/t208xrdb/t208xrdb.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2021 NXP - */ - -#ifndef __CORENET_DS_H__ -#define __CORENET_DS_H__ - -#define CORTINA_FW_ADDR_IFCNOR 0xefe00000 -#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebe00000 - -void fdt_fixup_board_enet(void *blob); -void pci_of_setup(void *blob, struct bd_info *bd); -void fdt_fixup_board_fman_ethernet(void *blob); -void fdt_fixup_board_phy(void *blob); - -#endif diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c deleted file mode 100644 index a3f283548f3..00000000000 --- a/board/freescale/t208xrdb/tlb.c +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008-2014 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, - CFG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, - CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, - CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, - CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) - /* - * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the - * SRAM is at 0xfff00000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) - /* - * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the - * space is at 0xfff00000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, - CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), -#else - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), - - /* *I*G* - Flash, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - -#ifndef CONFIG_XPL_BUILD - /* *I*G* - PCIe 1, 0x80000000 */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_512M, 1), - - /* *I*G* - PCIe 2, 0xa0000000 */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE2_MEM_VIRT, CFG_SYS_PCIE2_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCIe 3, 0xb0000000 */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE3_MEM_VIRT, CFG_SYS_PCIE3_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCIe 4, 0xc0000000 */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256K, 1), - - /* Bman/Qman */ -#ifdef CFG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, - CFG_SYS_BMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_16M, 1), -#endif -#ifdef CFG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 11, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, - CFG_SYS_QMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 12, BOOKE_PAGESZ_16M, 1), -#endif -#endif -#ifdef CFG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 13, BOOKE_PAGESZ_32M, 1), -#endif -#ifdef CFG_SYS_NAND_BASE - /* - * *I*G - NAND - * entry 14 and 15 has been used hard coded, they will be disabled - * in cpu_init_f, so we use entry 16 for nand. - */ - SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 16, BOOKE_PAGESZ_64K, 1), -#endif -#ifdef CFG_SYS_CPLD_BASE - SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 17, BOOKE_PAGESZ_4K, 1), -#endif -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE - /* - * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for - * fetching ucode and ENV from master - */ - SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, - CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, - 0, 18, BOOKE_PAGESZ_1M, 1), -#endif -#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD) - SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 19, BOOKE_PAGESZ_2G, 1) -#endif - -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t4rdb/Kconfig b/board/freescale/t4rdb/Kconfig deleted file mode 100644 index d93e4532ac4..00000000000 --- a/board/freescale/t4rdb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_T4240RDB - -config SYS_BOARD - default "t4rdb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "T4240RDB" - -endif diff --git a/board/freescale/t4rdb/MAINTAINERS b/board/freescale/t4rdb/MAINTAINERS deleted file mode 100644 index 844a15259c0..00000000000 --- a/board/freescale/t4rdb/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -T4RDB BOARD -M: Priyanka Jain -S: Maintained -F: board/freescale/t4rdb/ -F: include/configs/T4240RDB.h -F: configs/T4240RDB_defconfig -F: configs/T4240RDB_SDCARD_defconfig diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile deleted file mode 100644 index 8d94faaba1c..00000000000 --- a/board/freescale/t4rdb/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright 2014 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_XPL_BUILD -obj-y += spl.o -else -obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o -obj-y += cpld.o -obj-y += eth.o -endif - -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c deleted file mode 100644 index 258581eee96..00000000000 --- a/board/freescale/t4rdb/cpld.c +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/** - * Copyright 2014 Freescale Semiconductor - * - * Author: Chunhe Lan - * - * This file provides support for the board-specific CPLD used on some Freescale - * reference boards. - * - * The following macros need to be defined: - * - * CFG_SYS_CPLD_BASE - The virtual address of the base of the - * CPLD register map - * - */ - -#include -#include -#include -#include - -#include "cpld.h" - -u8 cpld_read(unsigned int reg) -{ - void *p = (void *)CFG_SYS_CPLD_BASE; - - return in_8(p + reg); -} - -void cpld_write(unsigned int reg, u8 value) -{ - void *p = (void *)CFG_SYS_CPLD_BASE; - - out_8(p + reg, value); -} - -/** - * Set the boot bank to the alternate bank - */ -void cpld_set_altbank(void) -{ - u8 val, curbank, altbank, override; - - val = CPLD_READ(vbank); - curbank = val & CPLD_BANK_SEL_MASK; - - switch (curbank) { - case CPLD_SELECT_BANK0: - case CPLD_SELECT_BANK4: - altbank = CPLD_SELECT_BANK4; - CPLD_WRITE(vbank, altbank); - override = CPLD_READ(software_on); - CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); - CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET); - break; - default: - printf("CPLD Altbank Fail: Invalid value!\n"); - return; - } -} - -/** - * Set the boot bank to the default bank - */ -void cpld_set_defbank(void) -{ - u8 val; - - val = CPLD_DEFAULT_BANK; - - CPLD_WRITE(global_reset, val); -} - -#ifdef DEBUG -static void cpld_dump_regs(void) -{ - printf("chip_id1 = 0x%02x\n", CPLD_READ(chip_id1)); - printf("chip_id2 = 0x%02x\n", CPLD_READ(chip_id2)); - printf("sw_maj_ver = 0x%02x\n", CPLD_READ(sw_maj_ver)); - printf("sw_min_ver = 0x%02x\n", CPLD_READ(sw_min_ver)); - printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); - printf("software_on = 0x%02x\n", CPLD_READ(software_on)); - printf("cfg_rcw_src = 0x%02x\n", CPLD_READ(cfg_rcw_src)); - printf("res0 = 0x%02x\n", CPLD_READ(res0)); - printf("vbank = 0x%02x\n", CPLD_READ(vbank)); - printf("sw1_sysclk = 0x%02x\n", CPLD_READ(sw1_sysclk)); - printf("sw2_status = 0x%02x\n", CPLD_READ(sw2_status)); - printf("sw3_status = 0x%02x\n", CPLD_READ(sw3_status)); - printf("sw4_status = 0x%02x\n", CPLD_READ(sw4_status)); - printf("sys_reset = 0x%02x\n", CPLD_READ(sys_reset)); - printf("global_reset = 0x%02x\n", CPLD_READ(global_reset)); - printf("res1 = 0x%02x\n", CPLD_READ(res1)); - putc('\n'); -} -#endif - -#ifndef CONFIG_XPL_BUILD -int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - int rc = 0; - - if (argc <= 1) - return cmd_usage(cmdtp); - - if (strcmp(argv[1], "reset") == 0) { - if (strcmp(argv[2], "altbank") == 0) - cpld_set_altbank(); - else - cpld_set_defbank(); -#ifdef DEBUG - } else if (strcmp(argv[1], "dump") == 0) { - cpld_dump_regs(); -#endif - } else - rc = cmd_usage(cmdtp); - - return rc; -} - -U_BOOT_CMD( - cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, - "Reset the board or alternate bank", - "reset - reset to default bank\n" - "cpld reset altbank - reset to alternate bank\n" -#ifdef DEBUG - "cpld dump - display the CPLD registers\n" -#endif - ); -#endif diff --git a/board/freescale/t4rdb/cpld.h b/board/freescale/t4rdb/cpld.h deleted file mode 100644 index fcac9244c8a..00000000000 --- a/board/freescale/t4rdb/cpld.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/** - * Copyright 2014 Freescale Semiconductor - * - * Author: Chunhe Lan - * - * This file provides support for the ngPIXIS, a board-specific FPGA used on - * some Freescale reference boards. - */ - -/* - * CPLD register set. Feel free to add board-specific #ifdefs where necessary. - */ -struct cpld_data { - u8 chip_id1; /* 0x00 - CPLD Chip ID1 Register */ - u8 chip_id2; /* 0x01 - CPLD Chip ID2 Register */ - u8 sw_maj_ver; /* 0x02 - CPLD Code Major Version Register */ - u8 sw_min_ver; /* 0x03 - CPLD Code Minor Version Register */ - u8 hw_ver; /* 0x04 - PCBA Version Register */ - u8 software_on; /* 0x05 - Override Physical Switch Enable Register */ - u8 cfg_rcw_src; /* 0x06 - RCW Source Location Control Register */ - u8 res0; /* 0x07 - not used */ - u8 vbank; /* 0x08 - Flash Bank Selection Control Register */ - u8 sw1_sysclk; /* 0x09 - SW1 Status Read Back Register */ - u8 sw2_status; /* 0x0a - SW2 Status Read Back Register */ - u8 sw3_status; /* 0x0b - SW3 Status Read Back Register */ - u8 sw4_status; /* 0x0c - SW4 Status Read Back Register */ - u8 sys_reset; /* 0x0d - Reset System With Reserving Registers Value*/ - u8 global_reset;/* 0x0e - Reset System With Default Registers Value */ - u8 res1; /* 0x0f - not used */ -}; - -#define CPLD_BANK_SEL_MASK 0x07 -#define CPLD_BANK_SEL_EN 0x04 -#define CPLD_SYSTEM_RESET 0x01 -#define CPLD_SELECT_BANK0 0x00 -#define CPLD_SELECT_BANK4 0x04 -#define CPLD_DEFAULT_BANK 0x01 - -/* Pointer to the CPLD register set */ - -u8 cpld_read(unsigned int reg); -void cpld_write(unsigned int reg, u8 value); - -#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) -#define CPLD_WRITE(reg, value) \ - cpld_write(offsetof(struct cpld_data, reg), value) diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c deleted file mode 100644 index 1ce70962264..00000000000 --- a/board/freescale/t4rdb/ddr.c +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 2) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - /* - * we use identical timing for all slots. If needed, change the code - * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; - */ - if (popts->registered_dimm_en) - pbsp = rdimms[0]; - else - pbsp = udimms[0]; - - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks && - (pdimm->rank_density >> 30) >= pbsp->rank_gb) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for data\n" - "rate %lu MT/s\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" - "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n" - "wrlvl_ctrl_3 0x%x\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, - pbsp->wrlvl_ctl_3); - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); - - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x64; -} - -int dram_init(void) -{ - phys_size_t dram_size; - - puts("Initializing....using SPD\n"); - -#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) - dram_size = fsl_ddr_sdram(); -#else - /* DDR has been initialised by first stage boot loader */ - dram_size = fsl_ddr_sdram_size(); -#endif - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - gd->ram_size = dram_size; - - return 0; -} diff --git a/board/freescale/t4rdb/ddr.h b/board/freescale/t4rdb/ddr.h deleted file mode 100644 index 241b13475da..00000000000 --- a/board/freescale/t4rdb/ddr.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a}, - {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09}, - {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b}, - {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a}, - {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c}, - {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c}, - {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a}, - {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a}, - {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a}, - {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b}, - {} -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 - */ - {4, 1350, 0, 10, 9, 0x08070605, 0x06070806}, - {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906}, - {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, - {2, 1350, 0, 10, 9, 0x08070605, 0x06070806}, - {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, - {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, - {1, 1350, 0, 10, 9, 0x08070605, 0x06070806}, - {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, - {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07}, - {} -}; - -/* - * The three slots have slightly different timing. The center values are good - * for all slots. We use identical speed tables for them. In future use, if - * DIMMs require separated tables, make more entries as needed. - */ -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -/* - * The three slots have slightly different timing. See comments above. - */ -static const struct board_specific_parameters *rdimms[] = { - rdimm0, -}; - -#endif diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c deleted file mode 100644 index e7646365d7d..00000000000 --- a/board/freescale/t4rdb/eth.c +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * Chunhe Lan - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/fman.h" -#include "t4rdb.h" - -void fdt_fixup_board_enet(void *fdt) -{ - return; -} - -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_prtcl_s1, srds_prtcl_s2; - - srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS2_PRTCL; - srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM2_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM2_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) { - /* SGMII */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2); - fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3); - fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4); - } else { - puts("Invalid SerDes1 protocol for T4240RDB\n"); - } - - fm_disable_port(FM1_DTSEC5); - fm_disable_port(FM1_DTSEC6); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - -#if (CFG_SYS_NUM_FMAN == 2) - if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) { - /* SGMII && 10GBase-R */ - fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); - fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); - fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7); - fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8); - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR); - } else { - puts("Invalid SerDes2 protocol for T4240RDB\n"); - } - - fm_disable_port(FM2_DTSEC5); - fm_disable_port(FM2_DTSEC6); - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CFG_SYS_NUM_FM2_DTSEC; i++) { - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - for (i = FM2_10GEC1; i < FM2_10GEC1 + CFG_SYS_NUM_FM2_10GEC; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } -#endif /* CFG_SYS_NUM_FMAN */ - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c deleted file mode 100644 index c43ac0f30d7..00000000000 --- a/board/freescale/t4rdb/law.c +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#ifdef CFG_SYS_BMAN_MEM_PHYS - SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), -#endif -#ifdef CFG_SYS_QMAN_MEM_PHYS - SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), -#endif -#ifdef CFG_SYS_CPLD_BASE_PHYS - SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), -#endif -#ifdef CFG_SYS_DCSRBAR_PHYS - /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), -#endif -#ifdef CFG_SYS_NAND_BASE_PHYS - SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c deleted file mode 100644 index 9d2472dec25..00000000000 --- a/board/freescale/t4rdb/spl.c +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * - * Author: Chunhe Lan - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "t4rdb.h" - -#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 - -DECLARE_GLOBAL_DATA_PTR; - -phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_L3_SIZE; -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio, sys_clk, ccb_clk; - ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; - - /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ - memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); - - /* Update GD pointer */ - gd = (gd_t *)(CONFIG_SPL_GD_ADDR); - - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("" : : : "memory"); - - console_init_f(); - - /* initialize selected port with appropriate baud rate */ - sys_clk = get_board_sys_clk(); - plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; - ccb_clk = sys_clk * plat_ratio / 2; - - ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, - ccb_clk / 16 / CONFIG_BAUDRATE); - - puts("\nSD boot...\n"); - - relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - struct bd_info *bd; - - bd = (struct bd_info *)(gd + sizeof(gd_t)); - memset(bd, 0, sizeof(struct bd_info)); - gd->bd = bd; - - arch_cpu_init(); - get_clocks(); - mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, - CONFIG_SPL_RELOC_MALLOC_SIZE); - gd->flags |= GD_FLG_FULL_MALLOC_INIT; - - mmc_initialize(bd); - mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); - - gd->env_addr = (ulong)(SPL_ENV_ADDR); - gd->env_valid = ENV_VALID; - - i2c_init_all(); - - dram_init(); - - mmc_boot(); -} diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c deleted file mode 100644 index 5cacfd27380..00000000000 --- a/board/freescale/t4rdb/t4240rdb.c +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2023 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "t4rdb.h" -#include "cpld.h" -#include "../common/vid.h" - -DECLARE_GLOBAL_DATA_PTR; - -#if CONFIG_IS_ENABLED(DM_SERIAL) -int get_serial_clock(void) -{ - return get_bus_freq(0) / 2; -} -#endif - -int checkboard(void) -{ - struct cpu_type *cpu = gd->arch.cpu; - u8 sw; - - printf("Board: %sRDB, ", cpu->name); - printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ", - CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver)); - - sw = CPLD_READ(vbank); - sw = sw & CPLD_BANK_SEL_MASK; - - if (sw <= 7) - printf("vBank: %d\n", sw); - else - printf("Unsupported Bank=%x\n", sw); - - puts("SERDES Reference Clocks:\n"); - printf(" SERDES1=100MHz SERDES2=156.25MHz\n" - " SERDES3=100MHz SERDES4=100MHz\n"); - - return 0; -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CFG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - /* - * Adjust core voltage according to voltage ID - * This function changes I2C mux to channel 2. - */ - if (adjust_vdd(0)) - printf("Warning: Adjusting core voltage failed.\n"); - - pci_init(); - - return 0; -} - -int misc_init_r(void) -{ - return 0; -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); - fsl_fdt_fixup_dr_usb(blob, bd); - -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif - fdt_fixup_board_enet(blob); -#endif - - return 0; -} - -/* - * This function is called by bdinfo to print detail board information. - * As an exmaple for future board, we organize the messages into - * several sections. If applicable, the message is in the format of - * = - * It should aligned with normal output of bdinfo command. - * - * Voltage: Core, DDR and another configurable voltages - * Clock : Critical clocks which are not printed already - * RCW : RCW source if not printed already - * Misc : Other important information not in above catagories - */ -void board_detail(void) -{ - int rcwsrc; - - /* RCW section SW3[4] */ - rcwsrc = 0x0; - puts("RCW source = "); - switch (rcwsrc & 0x1) { - case 0x1: - puts("SDHC/eMMC\n"); - break; - default: - puts("I2C normal addressing\n"); - break; - } -} - -ulong *cs4340_get_fw_addr(void) -{ - ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR; - -#ifdef CONFIG_SYS_CORTINA_FW_IN_NOR - u8 sw; - - sw = CPLD_READ(vbank); - sw = sw & CPLD_BANK_SEL_MASK; - - if (sw == 0) - cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR; - else if (sw == 4) - cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK; -#endif - - return (ulong *)cortina_fw_addr; -} diff --git a/board/freescale/t4rdb/t4_pbi.cfg b/board/freescale/t4rdb/t4_pbi.cfg deleted file mode 100644 index 0b326fa1635..00000000000 --- a/board/freescale/t4rdb/t4_pbi.cfg +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright 2014 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -#PBI commands -#Initialize CPC1 -09010000 00200400 -09138000 00000000 -091380c0 00000100 -#512KB SRAM -09010100 00000000 -09010104 fff80009 -09010f00 08000000 -#enable CPC1 -09010000 80000000 -#Configure LAW for CPC1 -09000d00 00000000 -09000d04 fff80000 -09000d08 81000012 -#Configure alternate space -09000010 00000000 -09000014 ff000000 -09000018 81000000 -#Flush PBL data -091380c0 00100000 diff --git a/board/freescale/t4rdb/t4_sd_rcw.cfg b/board/freescale/t4rdb/t4_sd_rcw.cfg deleted file mode 100644 index cc2bff68269..00000000000 --- a/board/freescale/t4rdb/t4_sd_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -#serdes protocol 27_55_1_9 -16070019 18101916 00000000 00000000 -6c6e0848 00448c00 6c020000 f5000000 -00000000 ee0000ee 00000000 000307fc -00000000 00000000 00000000 00000028 diff --git a/board/freescale/t4rdb/t4rdb.h b/board/freescale/t4rdb/t4rdb.h deleted file mode 100644 index bb3ce216d7d..00000000000 --- a/board/freescale/t4rdb/t4rdb.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __T4RDB_H__ -#define __T4RDB_H__ - -#undef CFG_SYS_NUM_FM1_DTSEC -#undef CFG_SYS_NUM_FM2_DTSEC -#define CFG_SYS_NUM_FM1_DTSEC 4 -#define CFG_SYS_NUM_FM2_DTSEC 4 - -#define CORTINA_FW_ADDR_IFCNOR 0xefe00000 -#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebf00000 - -void fdt_fixup_board_enet(void *blob); -void pci_of_setup(void *blob, struct bd_info *bd); - -#endif diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c deleted file mode 100644 index 7c58c14f3b6..00000000000 --- a/board/freescale/t4rdb/tlb.c +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, - CFG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, - CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, - CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, - CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) - /* - * *I*G - L3SRAM. When L3 is used as 512K SRAM */ - SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_512K, 1), -#else - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), - - /* *I*G* - Flash, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - -#ifndef CONFIG_XPL_BUILD - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x40000000, - CFG_SYS_PCIE1_MEM_PHYS + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x50000000, - CFG_SYS_PCIE1_MEM_PHYS + 0x50000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), - - /* Bman/Qman */ -#ifdef CFG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, - CFG_SYS_BMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_16M, 1), -#endif -#ifdef CFG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 11, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, - CFG_SYS_QMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 12, BOOKE_PAGESZ_16M, 1), -#endif -#endif - -#ifdef CFG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 13, BOOKE_PAGESZ_32M, 1), -#endif -#ifdef CFG_SYS_NAND_BASE - /* - * *I*G - NAND - * entry 14 and 15 has been used hard coded, they will be disabled - * in cpu_init_f, so we use entry 16 for nand. - */ - SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 16, BOOKE_PAGESZ_64K, 1), -#endif -#ifdef CFG_SYS_CPLD_BASE - SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, - MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 17, BOOKE_PAGESZ_4K, 1), -#endif -#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD) - SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 18, BOOKE_PAGESZ_2G, 1) -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/vf610twr/Kconfig b/board/freescale/vf610twr/Kconfig deleted file mode 100644 index 208c7ae2f42..00000000000 --- a/board/freescale/vf610twr/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_VF610TWR - -config SYS_BOARD - default "vf610twr" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "vf610twr" - -config IMX_CONFIG - default "board/freescale/vf610twr/imximage.cfg" - -endif diff --git a/board/freescale/vf610twr/MAINTAINERS b/board/freescale/vf610twr/MAINTAINERS deleted file mode 100644 index b2eef8e24be..00000000000 --- a/board/freescale/vf610twr/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -VF610TWR BOARD -M: Alison Wang -S: Maintained -F: board/freescale/vf610twr/ -F: include/configs/vf610twr.h -F: configs/vf610twr_defconfig -F: configs/vf610twr_nand_defconfig diff --git a/board/freescale/vf610twr/Makefile b/board/freescale/vf610twr/Makefile deleted file mode 100644 index 43934e8b2ae..00000000000 --- a/board/freescale/vf610twr/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2013 Freescale Semiconductor, Inc. - -obj-y := vf610twr.o diff --git a/board/freescale/vf610twr/imximage.cfg b/board/freescale/vf610twr/imximage.cfg deleted file mode 100644 index e2fa1a582d2..00000000000 --- a/board/freescale/vf610twr/imximage.cfg +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ -#include - -/* image version */ -IMAGE_VERSION 2 - -/* Boot Offset 0x400, valid for both SD and NAND boot */ -BOOT_OFFSET FLASH_OFFSET_STANDARD diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c deleted file mode 100644 index bfb49ad8604..00000000000 --- a/board/freescale/vf610twr/vf610twr.c +++ /dev/null @@ -1,386 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE) - -#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) - -static struct ddrmc_cr_setting vf610twr_cr_settings[] = { - /* levelling */ - { DDRMC_CR97_WRLVL_EN, 97 }, - { DDRMC_CR98_WRLVL_DL_0(0), 98 }, - { DDRMC_CR99_WRLVL_DL_1(0), 99 }, - { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 }, - { DDRMC_CR105_RDLVL_DL_0(0), 105 }, - { DDRMC_CR106_RDLVL_GTDL_0(4), 106 }, - { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 }, - /* AXI */ - { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 }, - { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, - { DDRMC_CR120_AXI0_PRI1_RPRI(2) | - DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 }, - { DDRMC_CR121_AXI0_PRI3_RPRI(2) | - DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 }, - { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | - DDRMC_CR122_AXI0_PRIRLX(100), 122 }, - { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | - DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 }, - { DDRMC_CR124_AXI1_PRIRLX(100), 124 }, - { DDRMC_CR126_PHY_RDLAT(8), 126 }, - { DDRMC_CR132_WRLAT_ADJ(5) | - DDRMC_CR132_RDLAT_ADJ(6), 132 }, - { DDRMC_CR137_PHYCTL_DL(2), 137 }, - { DDRMC_CR138_PHY_WRLV_MXDL(256) | - DDRMC_CR138_PHYDRAM_CK_EN(1), 138 }, - { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | - DDRMC_CR139_PHY_WRLV_DLL(3) | - DDRMC_CR139_PHY_WRLV_EN(3), 139 }, - { DDRMC_CR140_PHY_WRLV_WW(64), 140 }, - { DDRMC_CR143_RDLV_GAT_MXDL(1536) | - DDRMC_CR143_RDLV_MXDL(128), 143 }, - { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) | - DDRMC_CR144_PHY_RDLV_DLL(3) | - DDRMC_CR144_PHY_RDLV_EN(3), 144 }, - { DDRMC_CR145_PHY_RDLV_RR(64), 145 }, - { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 }, - { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 }, - { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 }, - { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) | - DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 }, - - { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | - DDRMC_CR154_PAD_ZQ_MODE(1) | - DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | - DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 }, - { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 }, - { DDRMC_CR158_TWR(6), 158 }, - { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) | - DDRMC_CR161_TODTH_WR(2), 161 }, - /* end marker */ - { 0, -1 } -}; - -int dram_init(void) -{ - static const struct ddr3_jedec_timings timings = { - .tinit = 5, - .trst_pwron = 80000, - .cke_inactive = 200000, - .wrlat = 5, - .caslat_lin = 12, - .trc = 21, - .trrd = 4, - .tccd = 4, - .tbst_int_interval = 0, - .tfaw = 20, - .trp = 6, - .twtr = 4, - .tras_min = 15, - .tmrd = 4, - .trtp = 4, - .tras_max = 28080, - .tmod = 12, - .tckesr = 4, - .tcke = 3, - .trcd_int = 6, - .tras_lockout = 0, - .tdal = 12, - .bstlen = 3, - .tdll = 512, - .trp_ab = 6, - .tref = 3120, - .trfc = 44, - .tref_int = 0, - .tpdex = 3, - .txpdll = 10, - .txsnr = 48, - .txsr = 468, - .cksrx = 5, - .cksre = 5, - .freq_chg_en = 0, - .zqcl = 256, - .zqinit = 512, - .zqcs = 64, - .ref_per_zq = 64, - .zqcs_rotate = 0, - .aprebit = 10, - .cmd_age_cnt = 64, - .age_cnt = 64, - .q_fullness = 7, - .odt_rd_mapcs0 = 0, - .odt_wr_mapcs0 = 1, - .wlmrd = 40, - .wldqsen = 25, - }; - - ddrmc_setup_iomux(NULL, 0); - - ddrmc_ctrl_init_ddr3(&timings, vf610twr_cr_settings, NULL, 1, 3); - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - - return 0; -} - -static void setup_iomux_uart(void) -{ - static const iomux_v3_cfg_t uart1_pads[] = { - NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -static void setup_iomux_enet(void) -{ - static const iomux_v3_cfg_t enet0_pads[] = { - NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL), - }; - - imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); -} - -static void setup_iomux_i2c(void) -{ - static const iomux_v3_cfg_t i2c0_pads[] = { - VF610_PAD_PTB14__I2C0_SCL, - VF610_PAD_PTB15__I2C0_SDA, - }; - - imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads)); -} - -#ifdef CONFIG_NAND_VF610_NFC -static void setup_iomux_nfc(void) -{ - static const iomux_v3_cfg_t nfc_pads[] = { - VF610_PAD_PTD31__NF_IO15, - VF610_PAD_PTD30__NF_IO14, - VF610_PAD_PTD29__NF_IO13, - VF610_PAD_PTD28__NF_IO12, - VF610_PAD_PTD27__NF_IO11, - VF610_PAD_PTD26__NF_IO10, - VF610_PAD_PTD25__NF_IO9, - VF610_PAD_PTD24__NF_IO8, - VF610_PAD_PTD23__NF_IO7, - VF610_PAD_PTD22__NF_IO6, - VF610_PAD_PTD21__NF_IO5, - VF610_PAD_PTD20__NF_IO4, - VF610_PAD_PTD19__NF_IO3, - VF610_PAD_PTD18__NF_IO2, - VF610_PAD_PTD17__NF_IO1, - VF610_PAD_PTD16__NF_IO0, - VF610_PAD_PTB24__NF_WE_B, - VF610_PAD_PTB25__NF_CE0_B, - VF610_PAD_PTB27__NF_RE_B, - VF610_PAD_PTC26__NF_RB_B, - VF610_PAD_PTC27__NF_ALE, - VF610_PAD_PTC28__NF_CLE - }; - - imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); -} -#endif - -static void setup_iomux_qspi(void) -{ - static const iomux_v3_cfg_t qspi0_pads[] = { - VF610_PAD_PTD0__QSPI0_A_QSCK, - VF610_PAD_PTD1__QSPI0_A_CS0, - VF610_PAD_PTD2__QSPI0_A_DATA3, - VF610_PAD_PTD3__QSPI0_A_DATA2, - VF610_PAD_PTD4__QSPI0_A_DATA1, - VF610_PAD_PTD5__QSPI0_A_DATA0, - VF610_PAD_PTD7__QSPI0_B_QSCK, - VF610_PAD_PTD8__QSPI0_B_CS0, - VF610_PAD_PTD9__QSPI0_B_DATA3, - VF610_PAD_PTD10__QSPI0_B_DATA2, - VF610_PAD_PTD11__QSPI0_B_DATA1, - VF610_PAD_PTD12__QSPI0_B_DATA0, - }; - - imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads)); -} - -#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg esdhc_cfg[1] = { - {ESDHC1_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - /* eSDHC1 is always present */ - return 1; -} - -int board_mmc_init(struct bd_info *bis) -{ - static const iomux_v3_cfg_t esdhc1_pads[] = { - NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), - NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), - }; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - - imx_iomux_v3_setup_multiple_pads( - esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); - - return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); -} -#endif - -static void clock_init(void) -{ - struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; - struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; - - clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, - CCM_CCGR0_UART1_CTRL_MASK); - clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, - CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); - clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, - CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | - CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | - CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK | - CCM_CCGR2_QSPI0_CTRL_MASK); - clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, - CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK); - clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, - CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | - CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK); - clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, - CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); - clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, - CCM_CCGR7_SDHC1_CTRL_MASK); - clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, - CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); - clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, - CCM_CCGR10_NFC_CTRL_MASK); - - clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, - ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); - clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, - ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); - - clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, - CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); - clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, - CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN | - CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN | - CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN | - CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN | - CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) | - CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4)); - clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, - CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | - CCM_CACRR_ARM_CLK_DIV(0)); - clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, - CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) | - CCM_CSCMR1_NFC_CLK_SEL(0)); - clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, - CCM_CSCDR1_RMII_CLK_EN); - clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, - CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | - CCM_CSCDR2_NFC_EN); - clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, - CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) | - CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) | - CCM_CSCDR3_NFC_PRE_DIV(5)); - clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, - CCM_CSCMR2_RMII_CLK_SEL(0)); -} - -static void mscm_init(void) -{ - struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; - int i; - - for (i = 0; i < MSCM_IRSPRC_NUM; i++) - writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); -} - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int board_early_init_f(void) -{ - clock_init(); - mscm_init(); - - setup_iomux_uart(); - setup_iomux_enet(); - setup_iomux_i2c(); - setup_iomux_qspi(); -#ifdef CONFIG_NAND_VF610_NFC - setup_iomux_nfc(); -#endif - - return 0; -} - -int board_init(void) -{ - struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR; - - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - /* - * Enable external 32K Oscillator - * - * The internal clock experiences significant drift - * so we must use the external oscillator in order - * to maintain correct time in the hwclock - */ - setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN); - - return 0; -} - -int checkboard(void) -{ - puts("Board: vf610twr\n"); - - return 0; -} diff --git a/board/ge/mx53ppd/Makefile b/board/ge/mx53ppd/Makefile index 9fae4143998..112bceda3f6 100644 --- a/board/ge/mx53ppd/Makefile +++ b/board/ge/mx53ppd/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # Copyright 2017 General Electric Company # -# Based on board/freescale/mx53loco/Makefile: +# Based on board/nxp/mx53loco/Makefile: # # (C) Copyright 2011 Freescale Semiconductor, Inc. # Jason Liu diff --git a/board/ge/mx53ppd/imximage.cfg b/board/ge/mx53ppd/imximage.cfg index 1ee81983907..533f18b674b 100644 --- a/board/ge/mx53ppd/imximage.cfg +++ b/board/ge/mx53ppd/imximage.cfg @@ -2,7 +2,7 @@ /* * Copyright 2017 General Electric Company * - * Based on board/freescale/mx53loco/imximage.cfg: + * Based on board/nxp/mx53loco/imximage.cfg: * * Copyright (C) 2011 Freescale Semiconductor, Inc. * Jason Liu diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index 9396d43f8ad..cb9b88a1a58 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -2,7 +2,7 @@ /* * Copyright 2017 General Electric Company * - * Based on board/freescale/mx53loco/mx53loco.c: + * Based on board/nxp/mx53loco/mx53loco.c: * * Copyright (C) 2011 Freescale Semiconductor, Inc. * Jason Liu diff --git a/board/ge/mx53ppd/mx53ppd_video.c b/board/ge/mx53ppd/mx53ppd_video.c index eb4dd758b3b..32e208aadd1 100644 --- a/board/ge/mx53ppd/mx53ppd_video.c +++ b/board/ge/mx53ppd/mx53ppd_video.c @@ -2,7 +2,7 @@ /* * Copyright 2017 General Electric Company * - * Based on board/freescale/mx53loco/mx53loco_video.c: + * Based on board/nxp/mx53loco/mx53loco_video.c: * * Copyright (C) 2012 Freescale Semiconductor, Inc. * Fabio Estevam diff --git a/board/k+p/kp_imx53/Kconfig b/board/k+p/kp_imx53/Kconfig index fb35127696b..ef6696b1160 100644 --- a/board/k+p/kp_imx53/Kconfig +++ b/board/k+p/kp_imx53/Kconfig @@ -13,6 +13,6 @@ config SYS_CONFIG_NAME default "kp_imx53" config IMX_CONFIG - default "board/freescale/mx53loco/imximage.cfg" + default "board/nxp/mx53loco/imximage.cfg" endif diff --git a/board/keymile/pg-wcom-ls102xa/Makefile b/board/keymile/pg-wcom-ls102xa/Makefile index 229b0c28278..88cb95bb8c3 100644 --- a/board/keymile/pg-wcom-ls102xa/Makefile +++ b/board/keymile/pg-wcom-ls102xa/Makefile @@ -6,6 +6,6 @@ obj-y += pg-wcom-ls102xa.o ddr.o obj-y += ../common/common.o ../common/ivm.o ../common/qrio.o -obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ../../freescale/common/ns_access.o -obj-$(CONFIG_LS102XA_STREAM_ID) += ../../freescale/common/ls102xa_stream_id.o -obj-$(CONFIG_ID_EEPROM) += ../../freescale/common/sys_eeprom.o +obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ../../nxp/common/ns_access.o +obj-$(CONFIG_LS102XA_STREAM_ID) += ../../nxp/common/ls102xa_stream_id.o +obj-$(CONFIG_ID_EEPROM) += ../../nxp/common/sys_eeprom.o diff --git a/board/nxp/common/Makefile b/board/nxp/common/Makefile new file mode 100644 index 00000000000..ed102ae7bf7 --- /dev/null +++ b/board/nxp/common/Makefile @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +MINIMAL= + +ifdef CONFIG_XPL_BUILD +ifndef CONFIG_TPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif +endif + +ifdef MINIMAL +# necessary to create built-in.a +obj- := __dummy__.a +else +# include i2c_common.o once if either VID or FSL_USE_PCA9547_MUX +I2C_COMMON= +ifdef CONFIG_VID +I2C_COMMON=y +endif +ifdef CONFIG_FSL_USE_PCA9547_MUX +I2C_COMMON=y +endif + +obj-$(CONFIG_FSL_CADMUS) += cadmus.o +obj-$(CONFIG_FSL_VIA) += cds_via.o +obj-$(CONFIG_FMAN_ENET) += fman.o +ifndef CONFIG_XPL_BUILD +obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o +endif +obj-$(I2C_COMMON) += i2c_common.o +obj-$(CONFIG_FSL_USE_PCA9547_MUX) += i2c_mux.o +obj-$(CONFIG_$(PHASE_)VID) += vid.o +obj-$(CONFIG_FSL_QIXIS) += qixis.o +ifndef CONFIG_XPL_BUILD +obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o +endif +ifndef CONFIG_RAMBOOT_PBL +obj-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o +endif + +ifdef CONFIG_ARM +obj-$(CONFIG_DEEP_SLEEP) += arm_sleep.o +else +obj-$(CONFIG_DEEP_SLEEP) += mpc85xx_sleep.o +endif + +obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o + +obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o +obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o +obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o +ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y) +obj-$(CONFIG_POWER_PFUZE100) += pfuze.o +endif +obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o +obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o +ifneq (,$(filter $(SOC), imx8m imx8ulp imx9)) +obj-y += mmc.o +endif + +obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o + +obj-$(CONFIG_EMC2305) += emc2305.o + +# deal with common files for P-series corenet based devices +obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/ +obj-$(CONFIG_TARGET_P3041DS) += p_corenet/ +obj-$(CONFIG_TARGET_P4080DS) += p_corenet/ +obj-$(CONFIG_TARGET_P5040DS) += p_corenet/ + +obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o + +ifdef CONFIG_NXP_ESBC +obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o +endif +obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o + +endif diff --git a/board/nxp/common/arm_sleep.c b/board/nxp/common/arm_sleep.c new file mode 100644 index 00000000000..228f07502f7 --- /dev/null +++ b/board/nxp/common/arm_sleep.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#ifndef CONFIG_ARMV7_NONSEC +#error " Deep sleep needs non-secure mode support. " +#else +#include +#endif +#include + +#if defined(CONFIG_ARCH_LS1021A) +#include +#endif + +#include "sleep.h" +#ifdef CONFIG_U_QE +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +void __weak board_mem_sleep_setup(void) +{ +} + +void __weak board_sleep_prepare(void) +{ +} + +bool is_warm_boot(void) +{ + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; + + if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) + return 1; + + return 0; +} + +void fsl_dp_disable_console(void) +{ + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; +} + +/* + * When wakeup from deep sleep, the first 128 bytes space + * will be used to do DDR training which corrupts the data + * in there. This function will restore them. + */ +static void dp_ddr_restore(void) +{ + u64 *src, *dst; + int i; + struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; + + /* get the address of ddr date from SPARECR3 */ + src = (u64 *)in_le32(&scfg->sparecr[2]); + dst = (u64 *)CFG_SYS_SDRAM_BASE; + + for (i = 0; i < DDR_BUFF_LEN / 8; i++) + *dst++ = *src++; +} + +#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A) +void ls1_psci_resume_fixup(void) +{ + u32 tmp; + struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; + +#ifdef QIXIS_BASE + void *qixis_base = (void *)QIXIS_BASE; + + /* Pull on PCIe RST# */ + out_8(qixis_base + QIXIS_RST_FORCE_3, 0); + + /* disable deep sleep signals in FPGA */ + tmp = in_8(qixis_base + QIXIS_PWR_CTL2); + tmp &= ~QIXIS_PWR_CTL2_PCTL; + out_8(qixis_base + QIXIS_PWR_CTL2, tmp); +#endif + + /* Disable wakeup interrupt during deep sleep */ + out_be32(&scfg->pmcintecr, 0); + /* Clear PMC interrupt status */ + out_be32(&scfg->pmcintsr, 0xffffffff); + + /* Disable Warm Device Reset */ + tmp = in_be32(&scfg->dpslpcr); + tmp &= ~SCFG_DPSLPCR_WDRR_EN; + out_be32(&scfg->dpslpcr, tmp); +} +#endif + +static void dp_resume_prepare(void) +{ + dp_ddr_restore(); + board_sleep_prepare(); + armv7_init_nonsec(); +#ifdef CONFIG_U_QE + u_qe_resume(); +#endif +#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A) + ls1_psci_resume_fixup(); +#endif +} + +int fsl_dp_resume(void) +{ + u32 start_addr; + void (*kernel_resume)(void); + struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; + + if (!is_warm_boot()) + return 0; + + dp_resume_prepare(); + + /* Get the entry address and jump to kernel */ + start_addr = in_le32(&scfg->sparecr[3]); + debug("Entry address is 0x%08x\n", start_addr); + kernel_resume = (void (*)(void))start_addr; + secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0); + + return 0; +} diff --git a/board/nxp/common/cadmus.c b/board/nxp/common/cadmus.c new file mode 100644 index 00000000000..e5ecd0e19c6 --- /dev/null +++ b/board/nxp/common/cadmus.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2004, 2011 Freescale Semiconductor. + */ + +#include +#include +#include + +/* + * CADMUS Board System Registers + */ +#ifndef CFG_SYS_CADMUS_BASE_REG +#define CFG_SYS_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000) +#endif + +typedef struct cadmus_reg { + u_char cm_ver; /* Board version */ + u_char cm_csr; /* General control/status */ + u_char cm_rst; /* Reset control */ + u_char cm_hsclk; /* High speed clock */ + u_char cm_hsxclk; /* High speed clock extended */ + u_char cm_led; /* LED data */ + u_char cm_pci; /* PCI control/status */ + u_char cm_dma; /* DMA control */ + u_char cm_reserved[248]; /* Total 256 bytes */ +} cadmus_reg_t; + +unsigned int +get_board_version(void) +{ + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG; + + return cadmus->cm_ver; +} + +unsigned long +get_board_sys_clk(void) +{ + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG; + + uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */ + + if (pci1_speed == 0) { + return 33333333; + } else if (pci1_speed == 1) { + return 66666666; + } else { + /* Really, unknown. Be safe? */ + return 33333333; + } +} + +unsigned int +get_pci_slot(void) +{ + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG; + + /* + * PCI slot in USER bits CSR[6:7] by convention. + */ + return ((cadmus->cm_csr >> 6) & 0x3) + 1; +} + +unsigned int +get_pci_dual(void) +{ + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_SYS_CADMUS_BASE_REG; + + /* + * PCI DUAL in CM_PCI[3] + */ + return cadmus->cm_pci & 0x10; +} diff --git a/board/nxp/common/cadmus.h b/board/nxp/common/cadmus.h new file mode 100644 index 00000000000..93cea120845 --- /dev/null +++ b/board/nxp/common/cadmus.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2004 Freescale Semiconductor. + */ + +#ifndef __CADMUS_H_ +#define __CADMUS_H_ + +/* + * CADMUS Board System Register interface. + */ + +/* + * Returns board version register. + */ +extern unsigned int get_board_version(void); + +/* + * Returns either 33000000 or 66000000 as the SYS_CLK_FREQ. + */ +extern unsigned long get_board_sys_clk(void); + +/* + * Returns 1 - 4, as found in the USER CSR[6:7] bits. + */ +extern unsigned int get_pci_slot(void); + +/* + * Returns PCI DUAL as found in CM_PCI[3]. + */ +extern unsigned int get_pci_dual(void); + +#endif /* __CADMUS_H_ */ diff --git a/board/nxp/common/cds_pci_ft.c b/board/nxp/common/cds_pci_ft.c new file mode 100644 index 00000000000..56b01e3f51f --- /dev/null +++ b/board/nxp/common/cds_pci_ft.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2004 Freescale Semiconductor. + */ + +#include +#include +#include "cadmus.h" + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + ft_cpu_setup(blob, bd); + + return 0; +} +#endif diff --git a/board/nxp/common/cds_via.c b/board/nxp/common/cds_via.c new file mode 100644 index 00000000000..6fc3a21780f --- /dev/null +++ b/board/nxp/common/cds_via.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2006 Freescale Semiconductor. + */ + +#include + +/* Config the VIA chip */ +void mpc85xx_config_via(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *tab) +{ + pci_dev_t bridge; + unsigned int cmdstat; + + /* Enable USB and IDE functions */ + pci_hose_write_config_byte(hose, dev, 0x48, 0x08); + + pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); + cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER; + pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + + /* + * Force the backplane P2P bridge to have a window + * open from 0x00000000-0x00001fff in PCI I/O space. + * This allows legacy I/O (i8259, etc) on the VIA + * southbridge to be accessed. + */ +#ifdef CONFIG_TARGET_MPC8548CDS_LEGACY + bridge = PCI_BDF(0, 17, 0); +#else + bridge = PCI_BDF(0, 28, 0); +#endif + pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0); + pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0); + pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10); + pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0); +} + +/* Function 1, IDE */ +void mpc85xx_config_via_usbide(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + /* + * Since the P2P window was forced to cover the fixed + * legacy I/O addresses, it is necessary to manually + * place the base addresses for the IDE and USB functions + * within this window. + */ + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0); +} + +/* Function 2, USB ports 0-1 */ +void mpc85xx_config_via_usb(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0); +} + +/* Function 3, USB ports 2-3 */ +void mpc85xx_config_via_usb2(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80); +} + +/* Function 5, Power Management */ +void mpc85xx_config_via_power(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8); +} + +/* Function 6, AC97 Interface */ +void mpc85xx_config_via_ac97(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00); +} diff --git a/board/nxp/common/cmd_esbc_validate.c b/board/nxp/common/cmd_esbc_validate.c new file mode 100644 index 00000000000..7629d7091e9 --- /dev/null +++ b/board/nxp/common/cmd_esbc_validate.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include + +int do_esbc_halt(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (fsl_check_boot_mode_secure() == 0) { + printf("Boot Mode is Non-Secure. Not entering spin loop.\n"); + return 0; + } + + printf("Core is entering spin loop.\n"); +loop: + goto loop; + + return 0; +} + +#ifndef CONFIG_XPL_BUILD +static int do_esbc_validate(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + char *hash_str = NULL; + uintptr_t haddr; + int ret; + uintptr_t img_addr = 0; + char buf[20]; + + if (argc < 2) + return cmd_usage(cmdtp); + else if (argc > 2) + /* Second arg - Optional - Hash Str*/ + hash_str = argv[2]; + + /* First argument - header address -32/64bit */ + haddr = (uintptr_t)hextoul(argv[1], NULL); + + /* With esbc_validate command, Image address must be + * part of header. So, the function is called + * by passing this argument as 0. + */ + ret = fsl_secboot_validate(haddr, hash_str, &img_addr); + + /* Need to set "img_addr" even if validation failure. + * Required when SB_EN in RCW set and non-fatal error + * to continue U-Boot + */ + sprintf(buf, "%lx", img_addr); + env_set("img_addr", buf); + + if (ret) + return 1; + + printf("esbc_validate command successful\n"); + return 0; +} + +/***************************************************/ +U_BOOT_LONGHELP(esbc_validate, + "esbc_validate hdr_addr - Validates signature using\n" + " RSA verification\n" + " $hdr_addr Address of header of the image\n" + " to be validated.\n" + " $hash_val -Optional\n" + " It provides Hash of public/srk key to be\n" + " used to verify signature.\n"); + +U_BOOT_CMD( + esbc_validate, 3, 0, do_esbc_validate, + "Validates signature on a given image using RSA verification", + esbc_validate_help_text +); + +U_BOOT_CMD( + esbc_halt, 1, 0, do_esbc_halt, + "Put the core in spin loop (Secure Boot Only)", + "" +); +#endif diff --git a/board/nxp/common/eeprom.h b/board/nxp/common/eeprom.h new file mode 100644 index 00000000000..1d0685fde67 --- /dev/null +++ b/board/nxp/common/eeprom.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2004 Freescale Semiconductor. + */ + +#ifndef __EEPROM_H_ +#define __EEPROM_H_ + +/* + * EEPROM Board System Register interface. + */ + +/* + * CPU Board Revision + */ +#define MPC85XX_CPU_BOARD_REV(maj, min) ((((maj)&0xff) << 8) | ((min) & 0xff)) +#define MPC85XX_CPU_BOARD_MAJOR(rev) (((rev) >> 8) & 0xff) +#define MPC85XX_CPU_BOARD_MINOR(rev) ((rev) & 0xff) + +#define MPC85XX_CPU_BOARD_REV_UNKNOWN MPC85XX_CPU_BOARD_REV(0,0) +#define MPC85XX_CPU_BOARD_REV_1_0 MPC85XX_CPU_BOARD_REV(1,0) +#define MPC85XX_CPU_BOARD_REV_1_1 MPC85XX_CPU_BOARD_REV(1,1) + +/* + * Returns CPU board revision register as a 16-bit value with + * the Major in the high byte, and Minor in the low byte. + */ +extern unsigned int get_cpu_board_revision(void); + +#endif /* __CADMUS_H_ */ diff --git a/board/nxp/common/emc2305.c b/board/nxp/common/emc2305.c new file mode 100644 index 00000000000..50252bb5007 --- /dev/null +++ b/board/nxp/common/emc2305.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2020 NXP. + * + */ + +#include +#include +#include +#include + +#include "emc2305.h" + +DECLARE_GLOBAL_DATA_PTR; + +void set_fan_speed(u8 data, int chip_addr) +{ + u8 index; + u8 Fan[NUM_OF_FANS] = {I2C_EMC2305_FAN1, + I2C_EMC2305_FAN2, + I2C_EMC2305_FAN3, + I2C_EMC2305_FAN4, + I2C_EMC2305_FAN5}; + + for (index = 0; index < NUM_OF_FANS; index++) { +#if !CONFIG_IS_ENABLED(DM_I2C) + if (i2c_write(chip_addr, Fan[index], 1, &data, 1) != 0) { + printf("Error: failed to change fan speed @%x\n", + Fan[index]); + } +#else + struct udevice *dev; + + if (i2c_get_chip_for_busnum(0, chip_addr, 1, &dev)) + continue; + + if (dm_i2c_write(dev, Fan[index], &data, 1) != 0) { + printf("Error: failed to change fan speed @%x\n", + Fan[index]); + } +#endif + } +} + +void emc2305_init(int chip_addr) +{ + u8 data; + + data = I2C_EMC2305_CMD; +#if !CONFIG_IS_ENABLED(DM_I2C) + if (i2c_write(chip_addr, I2C_EMC2305_CONF, 1, &data, 1) != 0) + printf("Error: failed to configure EMC2305\n"); +#else + struct udevice *dev; + + if (!i2c_get_chip_for_busnum(0, chip_addr, 1, &dev)) + if (dm_i2c_write(dev, I2C_EMC2305_CONF, &data, 1)) + printf("Error: failed to configure EMC2305\n"); +#endif + +} diff --git a/board/nxp/common/emc2305.h b/board/nxp/common/emc2305.h new file mode 100644 index 00000000000..24c5410d120 --- /dev/null +++ b/board/nxp/common/emc2305.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018-2020 NXP + * + */ + +#ifndef __EMC2305_H_ +#define __EMC2305_H_ + +#define I2C_EMC2305_CONF 0x20 +#define I2C_EMC2305_FAN1 0x30 +#define I2C_EMC2305_FAN2 0x40 +#define I2C_EMC2305_FAN3 0x50 +#define I2C_EMC2305_FAN4 0x60 +#define I2C_EMC2305_FAN5 0x70 + +#define NUM_OF_FANS 5 + +void emc2305_init(int chip_addr); +void set_fan_speed(u8 data, int chip_addr); + +#endif /* __EMC2305_H_ */ diff --git a/board/nxp/common/fman.c b/board/nxp/common/fman.c new file mode 100644 index 00000000000..650ecc7b440 --- /dev/null +++ b/board/nxp/common/fman.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2011-2015 Freescale Semiconductor, Inc. + */ + +#include +#include +#include + +#include +#ifdef CONFIG_FSL_LAYERSCAPE +#include +#else +#include +#endif + +/* + * Given the following ... + * + * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' + * compatible string and 'addr' physical address) + * + * 2) The name of an alias that points to the ethernet-phy node (usually inside + * a virtual MDIO node) + * + * ... update that Ethernet node's phy-handle property to point to the + * ethernet-phy node. This is how we link an Ethernet node to its PHY, so each + * PHY in a virtual MDIO node must have an alias. + * + * Returns 0 on success, or a negative FDT error code on error. + */ +int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr, + const char *alias) +{ + int offset; + unsigned int ph; + const char *path; + + /* Get a path to the node that 'alias' points to */ + path = fdt_get_alias(fdt, alias); + if (!path) + return -FDT_ERR_BADPATH; + + /* Get the offset of that node */ + offset = fdt_path_offset(fdt, path); + if (offset < 0) + return offset; + + ph = fdt_create_phandle(fdt, offset); + if (!ph) + return -FDT_ERR_BADPHANDLE; + + ph = cpu_to_fdt32(ph); + + offset = fdt_node_offset_by_compat_reg(fdt, compat, addr); + if (offset < 0) + return offset; + + return fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph)); +} + +/* + * Return the SerDes device enum for a given Fman port + * + * This function just maps the fm_port namespace to the srds_prtcl namespace. + */ +enum srds_prtcl serdes_device_from_fm_port(enum fm_port port) +{ + static const enum srds_prtcl srds_table[] = { + [FM1_DTSEC1] = SGMII_FM1_DTSEC1, + [FM1_DTSEC2] = SGMII_FM1_DTSEC2, + [FM1_DTSEC3] = SGMII_FM1_DTSEC3, + [FM1_DTSEC4] = SGMII_FM1_DTSEC4, + [FM1_DTSEC5] = SGMII_FM1_DTSEC5, + [FM1_10GEC1] = XAUI_FM1, + [FM2_DTSEC1] = SGMII_FM2_DTSEC1, + [FM2_DTSEC2] = SGMII_FM2_DTSEC2, + [FM2_DTSEC3] = SGMII_FM2_DTSEC3, + [FM2_DTSEC4] = SGMII_FM2_DTSEC4, + [FM2_DTSEC5] = SGMII_FM2_DTSEC5, + [FM2_10GEC1] = XAUI_FM2, + }; + + if ((port < FM1_DTSEC1) || (port > FM2_10GEC1)) + return NONE; + else + return srds_table[port]; +} diff --git a/board/nxp/common/fman.h b/board/nxp/common/fman.h new file mode 100644 index 00000000000..16afc34b03e --- /dev/null +++ b/board/nxp/common/fman.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + */ + +#ifndef __FMAN_BOARD_HELPER__ +#define __FMAN_BOARD_HELPER__ + +int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr, + const char *alias); + +enum srds_prtcl serdes_device_from_fm_port(enum fm_port port); + +#endif diff --git a/board/nxp/common/fsl_chain_of_trust.c b/board/nxp/common/fsl_chain_of_trust.c new file mode 100644 index 00000000000..3d44357caf7 --- /dev/null +++ b/board/nxp/common/fsl_chain_of_trust.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2022 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK) +#include +#endif + +#ifdef CONFIG_FSL_CORENET +#include +#endif + +#ifdef CONFIG_ARCH_LS1021A +#include +#endif + +#if defined(CONFIG_MPC85xx) +#define CFG_DCFG_ADDR CFG_SYS_MPC85xx_GUTS_ADDR +#else +#define CFG_DCFG_ADDR CFG_SYS_FSL_GUTS_ADDR +#endif + +#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE +#define gur_in32(a) in_le32(a) +#else +#define gur_in32(a) in_be32(a) +#endif + +/* Check the Boot Mode. If Secure, return 1 else return 0 */ +int fsl_check_boot_mode_secure(void) +{ + uint32_t val; + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_DCFG_ADDR); + + val = sfp_in32(&sfp_regs->ospr) & ITS_MASK; + if (val == ITS_MASK) + return 1; + +#if defined(CONFIG_FSL_CORENET) || !defined(CONFIG_MPC85xx) + /* For PBL based platforms check the SB_EN bit in RCWSR */ + val = gur_in32(&gur->rcwsr[RCW_SB_EN_REG_INDEX - 1]) & RCW_SB_EN_MASK; + if (val == RCW_SB_EN_MASK) + return 1; +#endif + +#if defined(CONFIG_MPC85xx) && !defined(CONFIG_FSL_CORENET) + /* For Non-PBL Platforms, check the Device Status register 2*/ + val = gur_in32(&gur->pordevsr2) & MPC85xx_PORDEVSR2_SBC_MASK; + if (val != MPC85xx_PORDEVSR2_SBC_MASK) + return 1; + +#endif + return 0; +} + +#ifndef CONFIG_XPL_BUILD +int fsl_setenv_chain_of_trust(void) +{ + /* Check Boot Mode + * If Boot Mode is Non-Secure, no changes are required + */ + if (fsl_check_boot_mode_secure() == 0) + return 0; + + /* If Boot mode is Secure, set the environment variables + * bootdelay = 0 (To disable Boot Prompt) + * bootcmd = CHAIN_BOOT_CMD (Validate and execute Boot script) + */ + env_set("bootdelay", "-2"); + +#ifdef CONFIG_ARM + env_set("secureboot", "y"); +#else + env_set("bootcmd", CHAIN_BOOT_CMD); +#endif + + return 0; +} +#endif + +#ifdef CONFIG_XPL_BUILD +void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr) +{ + int res; + + /* + * Check Boot Mode + * If Boot Mode is Non-Secure, skip validation + */ + if (fsl_check_boot_mode_secure() == 0) + return; + + printf("SPL: Validating U-Boot image\n"); + +#ifdef CONFIG_ADDR_MAP + init_addr_map(); +#endif + +#ifdef CONFIG_FSL_CORENET + if (pamu_init() < 0) + fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); +#endif + +/* + * dm_init_and_scan() is called as part of common SPL framework, so no + * need to call it again but in case of powerpc platforms which currently + * do not use common SPL framework, so need to call this function here. + */ +#if defined(CONFIG_SPL_DM) && (!defined(CONFIG_SPL_FRAMEWORK)) + dm_init_and_scan(true); +#endif + res = fsl_secboot_validate(hdr_addr, CONFIG_SPL_UBOOT_KEY_HASH, + &img_addr); + + if (res == 0) + printf("SPL: Validation of U-Boot successful\n"); +} + +#ifdef CONFIG_SPL_FRAMEWORK +/* Override weak funtion defined in SPL framework to enable validation + * of main u-boot image before jumping to u-boot image. + */ +void __noreturn jump_to_image(struct spl_image_info *spl_image) +{ + typedef void __noreturn (*image_entry_noargs_t)(void); + uint32_t hdr_addr; + + image_entry_noargs_t image_entry = + (image_entry_noargs_t)(unsigned long)spl_image->entry_point; + + hdr_addr = (spl_image->entry_point + spl_image->size - + FSL_U_BOOT_HDR_SIZE); + spl_validate_uboot(hdr_addr, (uintptr_t)spl_image->entry_point); + /* + * In case of failure in validation, spl_validate_uboot would + * not return back in case of Production environment with ITS=1. + * Thus U-Boot will not start. + * In Development environment (ITS=0 and SB_EN=1), the function + * may return back in case of non-fatal failures. + */ + + debug("image entry point: 0x%lX\n", spl_image->entry_point); + image_entry(); +} +#endif /* ifdef CONFIG_SPL_FRAMEWORK */ +#endif /* ifdef CONFIG_XPL_BUILD */ diff --git a/board/nxp/common/fsl_validate.c b/board/nxp/common/fsl_validate.c new file mode 100644 index 00000000000..df0c1a1f406 --- /dev/null +++ b/board/nxp/common/fsl_validate.c @@ -0,0 +1,973 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2021-2022 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_ARCH_LS1021A +#include +#endif +#include + +#define SHA256_BITS 256 +#define SHA256_BYTES (256/8) +#define SHA256_NIBBLES (256/4) +#define NUM_HEX_CHARS (sizeof(ulong) * 2) + +#define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \ + ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \ + ((key_len) == 2 * KEY_SIZE_BYTES)) +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) +/* Global data structure */ +static struct fsl_secboot_glb glb; +#endif + +/* This array contains DER value for SHA-256 */ +static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, + 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, + 0x04, 0x20 + }; + +static u8 hash_val[SHA256_BYTES]; + +#ifdef CONFIG_ESBC_HDR_LS +/* New Barker Code for LS ESBC Header */ +static const u8 barker_code[ESBC_BARKER_LEN] = { 0x12, 0x19, 0x20, 0x01 }; +#else +static const u8 barker_code[ESBC_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 }; +#endif + +void branch_to_self(void) __attribute__ ((noreturn)); + +/* + * This function will put core in infinite loop. + * This will be called when the ESBC can not proceed further due + * to some unknown errors. + */ +void branch_to_self(void) +{ + printf("Core is in infinite loop due to errors.\n"); +self: + goto self; +} + +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) +static u32 check_ie(struct fsl_secboot_img_priv *img) +{ + if (img->hdr.ie_flag & IE_FLAG_MASK) + return 1; + + return 0; +} + +/* This function returns the CSF Header Address of uboot + * For MPC85xx based platforms, the LAW mapping for NOR + * flash changes in uboot code. Hence the offset needs + * to be calculated and added to the new NOR flash base + * address + */ +#if defined(CONFIG_MPC85xx) +#include + +int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) +{ + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); + u32 csf_flash_offset = csf_hdr_addr & ~(CFG_SYS_PBI_FLASH_BASE); + u32 flash_addr, addr; + int found = 0; + int i = 0; + + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { + flash_addr = flash_info[i].start[0]; + addr = flash_info[i].start[0] + csf_flash_offset; + if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) { + debug("Barker found on addr %x\n", addr); + found = 1; + break; + } + } + + if (!found) + return -1; + + *csf_addr = addr; + *flash_base_addr = flash_addr; + + return 0; +} +#else +/* For platforms like LS1020, correct flash address is present in + * the header. So the function reqturns flash base address as 0 + */ +int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) +{ + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); + + if (memcmp((u8 *)(uintptr_t)csf_hdr_addr, + barker_code, ESBC_BARKER_LEN)) + return -1; + + *csf_addr = csf_hdr_addr; + *flash_base_addr = 0; + return 0; +} +#endif + +#if defined(CONFIG_ESBC_HDR_LS) +static int get_ie_info_addr(uintptr_t *ie_addr) +{ + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + /* For LS-CH3, the address of IE Table is + * stated in Scratch13 and scratch14 of DCFG. + * Bootrom validates this table while validating uboot. + * DCFG is LE*/ + *ie_addr = in_le32(&gur->scratchrw[SCRATCH_IE_HIGH_ADR - 1]); + *ie_addr = *ie_addr << 32; + *ie_addr |= in_le32(&gur->scratchrw[SCRATCH_IE_LOW_ADR - 1]); + return 0; +} +#else /* CONFIG_ESBC_HDR_LS */ +static int get_ie_info_addr(uintptr_t *ie_addr) +{ + struct fsl_secboot_img_hdr *hdr; + struct fsl_secboot_sg_table *sg_tbl; + u32 flash_base_addr, csf_addr; + + if (get_csf_base_addr(&csf_addr, &flash_base_addr)) + return -1; + + hdr = (struct fsl_secboot_img_hdr *)(uintptr_t)csf_addr; + + /* For SoC's with Trust Architecture v1 with corenet bus + * the sg table field in CSF header has absolute address + * for sg table in memory. In other Trust Architecture, + * this field specifies the offset of sg table from the + * base address of CSF Header + */ +#if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET) + sg_tbl = (struct fsl_secboot_sg_table *) + (((u32)hdr->psgtable & ~(CFG_SYS_PBI_FLASH_BASE)) + + flash_base_addr); +#else + sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr + + (u32)hdr->psgtable); +#endif + + /* IE Key Table is the first entry in the SG Table */ +#if defined(CONFIG_MPC85xx) + *ie_addr = (uintptr_t)((sg_tbl->src_addr & + ~(CFG_SYS_PBI_FLASH_BASE)) + + flash_base_addr); +#else + *ie_addr = (uintptr_t)sg_tbl->src_addr; +#endif + + debug("IE Table address is %lx\n", *ie_addr); + return 0; +} +#endif /* CONFIG_ESBC_HDR_LS */ +#endif + +#ifdef CONFIG_KEY_REVOCATION +/* This function checks srk_table_flag in header and set/reset srk_flag.*/ +static u32 check_srk(struct fsl_secboot_img_priv *img) +{ +#ifdef CONFIG_ESBC_HDR_LS + /* In LS, No SRK Flag as SRK is always present if IE not present*/ +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) + return !check_ie(img); +#endif + return 1; +#else + if (img->hdr.len_kr.srk_table_flag & SRK_FLAG) + return 1; + + return 0; +#endif +} + +/* This function returns ospr's key_revoc values.*/ +static u32 get_key_revoc(void) +{ + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); + return (sfp_in32(&sfp_regs->ospr) & OSPR_KEY_REVOC_MASK) >> + OSPR_KEY_REVOC_SHIFT; +} + +/* This function checks if selected key is revoked or not.*/ +static u32 is_key_revoked(u32 keynum, u32 rev_flag) +{ + if (keynum == UNREVOCABLE_KEY) + return 0; + + if ((u32)(1 << (ALIGN_REVOC_KEY - keynum)) & rev_flag) + return 1; + + return 0; +} + +/* It read validates srk_table key lengths.*/ +static u32 read_validate_srk_tbl(struct fsl_secboot_img_priv *img) +{ + int i = 0; + u32 ret, key_num, key_revoc_flag, size; + struct fsl_secboot_img_hdr *hdr = &img->hdr; + void *esbc = (u8 *)(uintptr_t)img->ehdrloc; + + if ((hdr->len_kr.num_srk == 0) || + (hdr->len_kr.num_srk > MAX_KEY_ENTRIES)) + return ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY; + + key_num = hdr->len_kr.srk_sel; + if (key_num == 0 || key_num > hdr->len_kr.num_srk) + return ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM; + + /* Get revoc key from sfp */ + key_revoc_flag = get_key_revoc(); + ret = is_key_revoked(key_num, key_revoc_flag); + if (ret) + return ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED; + + size = hdr->len_kr.num_srk * sizeof(struct srk_table); + + memcpy(&img->srk_tbl, esbc + hdr->srk_tbl_off, size); + + for (i = 0; i < hdr->len_kr.num_srk; i++) { + if (!CHECK_KEY_LEN(img->srk_tbl[i].key_len)) + return ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN; + } + + img->key_len = img->srk_tbl[key_num - 1].key_len; + + memcpy(&img->img_key, &(img->srk_tbl[key_num - 1].pkey), + img->key_len); + + return 0; +} +#endif + +#ifndef CONFIG_ESBC_HDR_LS +static u32 read_validate_single_key(struct fsl_secboot_img_priv *img) +{ + struct fsl_secboot_img_hdr *hdr = &img->hdr; + void *esbc = (u8 *)(uintptr_t)img->ehdrloc; + + /* check key length */ + if (!CHECK_KEY_LEN(hdr->key_len)) + return ERROR_ESBC_CLIENT_HEADER_KEY_LEN; + + memcpy(&img->img_key, esbc + hdr->pkey, hdr->key_len); + + img->key_len = hdr->key_len; + + return 0; +} +#endif /* CONFIG_ESBC_HDR_LS */ + +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) + +static void install_ie_tbl(uintptr_t ie_tbl_addr, + struct fsl_secboot_img_priv *img) +{ + /* Copy IE tbl to Global Data */ + memcpy(&glb.ie_tbl, (u8 *)ie_tbl_addr, sizeof(struct ie_key_info)); + img->ie_addr = (uintptr_t)&glb.ie_tbl; + glb.ie_addr = img->ie_addr; +} + +static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img) +{ + struct fsl_secboot_img_hdr *hdr = &img->hdr; + u32 ie_key_len, ie_revoc_flag, ie_num; + struct ie_key_info *ie_info; + + if (!img->ie_addr) { + if (get_ie_info_addr(&img->ie_addr)) + return ERROR_IE_TABLE_NOT_FOUND; + else + install_ie_tbl(img->ie_addr, img); + } + + ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr; + if (ie_info->num_keys == 0 || ie_info->num_keys > 32) + return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY; + + ie_num = hdr->ie_key_sel; + if (ie_num == 0 || ie_num > ie_info->num_keys) + return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM; + + ie_revoc_flag = ie_info->key_revok; + if ((u32)(1 << (ie_num - 1)) & ie_revoc_flag) + return ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED; + + ie_key_len = ie_info->ie_key_tbl[ie_num - 1].key_len; + + if (!CHECK_KEY_LEN(ie_key_len)) + return ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN; + + memcpy(&img->img_key, &(ie_info->ie_key_tbl[ie_num - 1].pkey), + ie_key_len); + + img->key_len = ie_key_len; + return 0; +} +#endif + +/* This function return length of public key.*/ +static inline u32 get_key_len(struct fsl_secboot_img_priv *img) +{ + return img->key_len; +} + +/* + * Handles the ESBC uboot client header verification failure. + * This function handles all the errors which might occur in the + * parsing and checking of ESBC uboot client header. It will also + * set the error bits in the SEC_MON. + */ +static void fsl_secboot_header_verification_failure(void) +{ + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); + + /* 29th bit of OSPR is ITS */ + u32 its = sfp_in32(&sfp_regs->ospr) >> 2; + + if (its == 1) + set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL); + else + set_sec_mon_state(HPSR_SSM_ST_NON_SECURE); + + printf("Generating reset request\n"); + do_reset(NULL, 0, 0, NULL); + /* If reset doesn't coocur, halt execution */ + do_esbc_halt(NULL, 0, 0, NULL); +} + +/* + * Handles the ESBC uboot client image verification failure. + * This function handles all the errors which might occur in the + * public key hash comparison and signature verification of + * ESBC uboot client image. It will also + * set the error bits in the SEC_MON. + */ +static void fsl_secboot_image_verification_failure(void) +{ + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); + + u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT; + + if (its == 1) { + set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL); + + printf("Generating reset request\n"); + do_reset(NULL, 0, 0, NULL); + /* If reset doesn't coocur, halt execution */ + do_esbc_halt(NULL, 0, 0, NULL); + + } else { + set_sec_mon_state(HPSR_SSM_ST_NON_SECURE); + } +} + +static void fsl_secboot_bootscript_parse_failure(void) +{ + fsl_secboot_header_verification_failure(); +} + +/* + * Handles the errors in esbc boot. + * This function handles all the errors which might occur in the + * esbc boot phase. It will call the appropriate api to log the + * errors and set the error bits in the SEC_MON. + */ +void fsl_secboot_handle_error(int error) +{ +#ifndef CONFIG_XPL_BUILD + const struct fsl_secboot_errcode *e; + + for (e = fsl_secboot_errcodes; e->errcode != ERROR_ESBC_CLIENT_MAX; + e++) { + if (e->errcode == error) + printf("ERROR :: %x :: %s\n", error, e->name); + } +#else + printf("ERROR :: %x\n", error); +#endif + + /* If Boot Mode is secure, transition the SNVS state and issue + * reset based on type of failure and ITS setting. + * If Boot mode is non-secure, return from this function. + */ + if (fsl_check_boot_mode_secure() == 0) + return; + + switch (error) { + case ERROR_ESBC_CLIENT_HEADER_BARKER: + case ERROR_ESBC_CLIENT_HEADER_IMG_SIZE: + case ERROR_ESBC_CLIENT_HEADER_KEY_LEN: + case ERROR_ESBC_CLIENT_HEADER_SIG_LEN: + case ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN: + case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1: + case ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2: + case ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD: + case ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP: + case ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD: + case ERROR_KEY_TABLE_NOT_FOUND: +#ifdef CONFIG_KEY_REVOCATION + case ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED: + case ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY: + case ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM: + case ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN: +#endif +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) + /*@fallthrough@*/ + case ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED: + case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY: + case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM: + case ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN: + case ERROR_IE_TABLE_NOT_FOUND: +#endif + fsl_secboot_header_verification_failure(); + break; + case ERROR_ESBC_SEC_RESET: + case ERROR_ESBC_SEC_DEQ: + case ERROR_ESBC_SEC_ENQ: + case ERROR_ESBC_SEC_DEQ_TO: + case ERROR_ESBC_SEC_JOBQ_STATUS: + case ERROR_ESBC_CLIENT_HASH_COMPARE_KEY: + case ERROR_ESBC_CLIENT_HASH_COMPARE_EM: + fsl_secboot_image_verification_failure(); + break; + case ERROR_ESBC_MISSING_BOOTM: + fsl_secboot_bootscript_parse_failure(); + break; + case ERROR_ESBC_WRONG_CMD: + default: + branch_to_self(); + break; + } +} + +static void fsl_secblk_handle_error(int error) +{ + switch (error) { + case ERROR_ESBC_SEC_ENQ: + fsl_secboot_handle_error(ERROR_ESBC_SEC_ENQ); + break; + case ERROR_ESBC_SEC_DEQ: + fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ); + break; + case ERROR_ESBC_SEC_DEQ_TO: + fsl_secboot_handle_error(ERROR_ESBC_SEC_DEQ_TO); + break; + default: + printf("Job Queue Output status %x\n", error); + fsl_secboot_handle_error(ERROR_ESBC_SEC_JOBQ_STATUS); + break; + } +} + +/* + * Calculate hash of key obtained via offset present in ESBC uboot + * client hdr. This function calculates the hash of key which is obtained + * through offset present in ESBC uboot client header. + */ +static int calc_img_key_hash(struct fsl_secboot_img_priv *img) +{ + struct hash_algo *algo; + void *ctx; + int i, srk = 0; + int ret = 0; + const char *algo_name = "sha256"; + + /* Calculate hash of the esbc key */ + ret = hash_progressive_lookup_algo(algo_name, &algo); + if (ret) + return ret; + + ret = algo->hash_init(algo, &ctx); + if (ret) + return ret; + /* Update hash for ESBC key */ +#ifdef CONFIG_KEY_REVOCATION + if (check_srk(img)) { + ret = algo->hash_update(algo, ctx, + (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off), + img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1); + srk = 1; + } +#endif + if (!srk) + ret = algo->hash_update(algo, ctx, + img->img_key, img->key_len, 1); + if (ret) + return ret; + /* Copy hash at destination buffer */ + ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size); + if (ret) { + free(ctx); + return ret; + } + for (i = 0; i < SHA256_BYTES; i++) + img->img_key_hash[i] = hash_val[i]; + + return 0; +} + +/* + * Calculate hash of ESBC hdr and ESBC. This function calculates the + * single hash of ESBC header and ESBC image. If SG flag is on, all + * SG entries are also hashed alongwith the complete SG table. + */ +static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) +{ + struct hash_algo *algo; + void *ctx; + int ret = 0; + int key_hash = 0; + const char *algo_name = "sha256"; + + /* Calculate the hash of the ESBC */ + ret = hash_progressive_lookup_algo(algo_name, &algo); + if (ret) + return ret; + + ret = algo->hash_init(algo, &ctx); + /* Copy hash at destination buffer */ + if (ret) + return ret; + + /* Update hash for CSF Header */ + ret = algo->hash_update(algo, ctx, + (u8 *)&img->hdr, sizeof(struct fsl_secboot_img_hdr), 0); + if (ret) + return ret; + + /* Update the hash with that of srk table if srk flag is 1 + * If IE Table is selected, key is not added in the hash + * If neither srk table nor IE key table available, add key + * from header in the hash calculation + */ +#ifdef CONFIG_KEY_REVOCATION + if (check_srk(img)) { + ret = algo->hash_update(algo, ctx, + (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off), + img->hdr.len_kr.num_srk * sizeof(struct srk_table), 0); + key_hash = 1; + } +#endif +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) + if (!key_hash && check_ie(img)) + key_hash = 1; +#endif +#ifndef CONFIG_ESBC_HDR_LS +/* No single key support in LS ESBC header */ + if (!key_hash) { + ret = algo->hash_update(algo, ctx, + img->img_key, img->hdr.key_len, 0); + key_hash = 1; + } +#endif + if (ret) + return ret; + if (!key_hash) { + free(ctx); + return ERROR_KEY_TABLE_NOT_FOUND; + } + /* Update hash for actual Image */ + ret = algo->hash_update(algo, ctx, + (u8 *)(*(img->img_addr_ptr)), img->img_size, 1); + if (ret) + return ret; + + /* Copy hash at destination buffer */ + ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size); + if (ret) { + free(ctx); + return ret; + } + return 0; +} + +/* + * Construct encoded hash EM' wrt PKCSv1.5. This function calculates the + * pointers for padding, DER value and hash. And finally, constructs EM' + * which includes hash of complete CSF header and ESBC image. If SG flag + * is on, hash of SG table and entries is also included. + */ +static void construct_img_encoded_hash_second(struct fsl_secboot_img_priv *img) +{ + /* + * RSA PKCSv1.5 encoding format for encoded message is below + * EM = 0x0 || 0x1 || PS || 0x0 || DER || Hash + * PS is Padding String + * DER is DER value for SHA-256 + * Hash is SHA-256 hash + * ********************************************************* + * representative points to first byte of EM initially and is + * filled with 0x0 + * representative is incremented by 1 and second byte is filled + * with 0x1 + * padding points to third byte of EM + * digest points to full length of EM - 32 bytes + * hash_id (DER value) points to 19 bytes before pDigest + * separator is one byte which separates padding and DER + */ + + size_t len; + u8 *representative; + u8 *padding, *digest; + u8 *hash_id, *separator; + int i; + + len = (get_key_len(img) / 2) - 1; + representative = img->img_encoded_hash_second; + representative[0] = 0; + representative[1] = 1; /* block type 1 */ + + padding = &representative[2]; + digest = &representative[1] + len - 32; + hash_id = digest - sizeof(hash_identifier); + separator = hash_id - 1; + + /* fill padding area pointed by padding with 0xff */ + memset(padding, 0xff, separator - padding); + + /* fill byte pointed by separator */ + *separator = 0; + + /* fill SHA-256 DER value pointed by HashId */ + memcpy(hash_id, hash_identifier, sizeof(hash_identifier)); + + /* fill hash pointed by Digest */ + for (i = 0; i < SHA256_BYTES; i++) + digest[i] = hash_val[i]; +} + +/* + * Reads and validates the ESBC client header. + * This function reads key and signature from the ESBC client header. + * If Scatter/Gather flag is on, lengths and offsets of images + * present as SG entries are also read. This function also checks + * whether the header is valid or not. + */ +static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) +{ + struct fsl_secboot_img_hdr *hdr = &img->hdr; + void *esbc = (u8 *)(uintptr_t)img->ehdrloc; + u8 *k, *s; + u32 ret = 0; + + int key_found = 0; + + /* check barker code */ + if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN)) + return ERROR_ESBC_CLIENT_HEADER_BARKER; + + /* If Image Address is not passed as argument to function, + * then Address and Size must be read from the Header. + */ + if (*(img->img_addr_ptr) == 0) { + #ifdef CONFIG_ESBC_ADDR_64BIT + *(img->img_addr_ptr) = hdr->pimg64; + #else + *(img->img_addr_ptr) = hdr->pimg; + #endif + } + + if (!hdr->img_size) + return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE; + + img->img_size = hdr->img_size; + + /* Key checking*/ +#ifdef CONFIG_KEY_REVOCATION + if (check_srk(img)) { + ret = read_validate_srk_tbl(img); + if (ret != 0) + return ret; + key_found = 1; + } +#endif + +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) + if (!key_found && check_ie(img)) { + ret = read_validate_ie_tbl(img); + if (ret != 0) + return ret; + key_found = 1; + } +#endif +#ifndef CONFIG_ESBC_HDR_LS +/* Single Key Feature not available in LS ESBC Header */ + if (key_found == 0) { + ret = read_validate_single_key(img); + if (ret != 0) + return ret; + key_found = 1; + } +#endif + if (!key_found) + return ERROR_KEY_TABLE_NOT_FOUND; + + /* check signaure */ + if (get_key_len(img) == 2 * hdr->sign_len) { + /* check signature length */ + if (!((hdr->sign_len == KEY_SIZE_BYTES / 4) || + (hdr->sign_len == KEY_SIZE_BYTES / 2) || + (hdr->sign_len == KEY_SIZE_BYTES))) + return ERROR_ESBC_CLIENT_HEADER_SIG_LEN; + } else { + return ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN; + } + + memcpy(&img->img_sign, esbc + hdr->psign, hdr->sign_len); +/* No SG support in LS-CH3 */ +#ifndef CONFIG_ESBC_HDR_LS + /* No SG support */ + if (hdr->sg_flag) + return ERROR_ESBC_CLIENT_HEADER_SG; +#endif + + /* modulus most significant bit should be set */ + k = (u8 *)&img->img_key; + + if ((k[0] & 0x80) == 0) + return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1; + + /* modulus value should be odd */ + if ((k[get_key_len(img) / 2 - 1] & 0x1) == 0) + return ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2; + + /* Check signature value < modulus value */ + s = (u8 *)&img->img_sign; + + if (!(memcmp(s, k, hdr->sign_len) < 0)) + return ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD; + + return ESBC_VALID_HDR; +} + +static inline int str2longbe(const char *p, ulong *num) +{ + char *endptr; + ulong tmp; + + if (!p) { + return 0; + } else { + tmp = hextoul(p, &endptr); + if (sizeof(ulong) == 4) + *num = cpu_to_be32(tmp); + else + *num = cpu_to_be64(tmp); + } + + return *p != '\0' && *endptr == '\0'; +} +/* Function to calculate the ESBC Image Hash + * and hash from Digital signature. + * The Two hash's are compared to yield the + * result of signature validation. + */ +static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img) +{ + int ret; + uint32_t key_len; + struct key_prop prop; +#if !defined(USE_HOSTCC) + struct udevice *mod_exp_dev; +#endif + ret = calc_esbchdr_esbc_hash(img); + if (ret) + return ret; + + /* Construct encoded hash EM' wrt PKCSv1.5 */ + construct_img_encoded_hash_second(img); + + /* Fill prop structure for public key */ + memset(&prop, 0, sizeof(struct key_prop)); + key_len = get_key_len(img) / 2; + prop.modulus = img->img_key; + prop.public_exponent = img->img_key + key_len; + prop.num_bits = key_len * 8; + prop.exp_len = key_len; + +#if defined(CONFIG_XPL_BUILD) + ret = device_bind_driver(NULL, "fsl_rsa_mod_exp", "fsl_rsa_mod_exp", NULL); + if (ret) { + printf("Couldn't bind fsl_rsa_mod_exp driver (%d)\n", ret); + return -EINVAL; + } +#endif + ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev); + if (ret) { + printf("RSA: Can't find Modular Exp implementation\n"); + return -EINVAL; + } + + ret = rsa_mod_exp(mod_exp_dev, img->img_sign, img->hdr.sign_len, + &prop, img->img_encoded_hash); + if (ret) + return ret; + + /* + * compare the encoded messages EM' and EM wrt RSA PKCSv1.5 + * memcmp returns zero on success + * memcmp returns non-zero on failure + */ + ret = memcmp(&img->img_encoded_hash_second, &img->img_encoded_hash, + img->hdr.sign_len); + + if (ret) + return ERROR_ESBC_CLIENT_HASH_COMPARE_EM; + + return 0; +} +/* Function to initialize img priv and global data structure + */ +static int secboot_init(struct fsl_secboot_img_priv **img_ptr) +{ + *img_ptr = malloc(sizeof(struct fsl_secboot_img_priv)); + + struct fsl_secboot_img_priv *img = *img_ptr; + + if (!img) + return -ENOMEM; + memset(img, 0, sizeof(struct fsl_secboot_img_priv)); + +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) + if (glb.ie_addr) + img->ie_addr = glb.ie_addr; +#endif + return 0; +} + +/* haddr - Address of the header of image to be validated. + * arg_hash_str - Option hash string. If provided, this + * overrides the key hash in the SFP fuses. + * img_addr_ptr - Optional pointer to address of image to be validated. + * If non zero addr, this overrides the addr of image in header, + * otherwise updated to image addr in header. + * Acts as both input and output of function. + * This pointer shouldn't be NULL. + */ +int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, + uintptr_t *img_addr_ptr) +{ + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); + ulong hash[SHA256_BYTES/sizeof(ulong)]; + char hash_str[NUM_HEX_CHARS + 1]; + struct fsl_secboot_img_priv *img; + struct fsl_secboot_img_hdr *hdr; + void *esbc; + int ret, i, hash_cmd = 0; + u32 srk_hash[8]; + + if (strlen(arg_hash_str) != 0) { + const char *cp = arg_hash_str; + int i = 0; + + if (*cp == '0' && *(cp + 1) == 'x') + cp += 2; + + /* The input string expected is in hex, where + * each 4 bits would be represented by a hex + * sha256 hash is 256 bits long, which would mean + * num of characters = 256 / 4 + */ + if (strlen(cp) != SHA256_NIBBLES) { + printf("%s is not a 256 bits hex string as expected\n", + arg_hash_str); + return -1; + } + + for (i = 0; i < sizeof(hash)/sizeof(ulong); i++) { + strncpy(hash_str, cp + (i * NUM_HEX_CHARS), + NUM_HEX_CHARS); + hash_str[NUM_HEX_CHARS] = '\0'; + if (!str2longbe(hash_str, &hash[i])) { + printf("%s is not a 256 bits hex string ", + arg_hash_str); + return -1; + } + } + + hash_cmd = 1; + } + + ret = secboot_init(&img); + if (ret) + goto exit; + + /* Update the information in Private Struct */ + hdr = &img->hdr; + img->ehdrloc = haddr; + img->img_addr_ptr = img_addr_ptr; + esbc = (u8 *)img->ehdrloc; + + memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr)); + + /* read and validate esbc header */ + ret = read_validate_esbc_client_header(img); + + if (ret != ESBC_VALID_HDR) { + fsl_secboot_handle_error(ret); + goto exit; + } + + /* SRKH present in SFP */ + for (i = 0; i < NUM_SRKH_REGS; i++) + srk_hash[i] = srk_in32(&sfp_regs->srk_hash[i]); + + /* + * Calculate hash of key obtained via offset present in + * ESBC uboot client hdr + */ + ret = calc_img_key_hash(img); + if (ret) { + fsl_secblk_handle_error(ret); + goto exit; + } + + /* Compare hash obtained above with SRK hash present in SFP */ + if (hash_cmd) + ret = memcmp(&hash, &img->img_key_hash, SHA256_BYTES); + else + ret = memcmp(srk_hash, img->img_key_hash, SHA256_BYTES); + +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) + if (!hash_cmd && check_ie(img)) + ret = 0; +#endif + + if (ret != 0) { + fsl_secboot_handle_error(ERROR_ESBC_CLIENT_HASH_COMPARE_KEY); + goto exit; + } + + ret = calculate_cmp_img_sig(img); + if (ret) { + fsl_secboot_handle_error(ret); + goto exit; + } + +exit: + /* Free Img as it was malloc'ed*/ + free(img); + return ret; +} diff --git a/board/nxp/common/i2c_common.c b/board/nxp/common/i2c_common.c new file mode 100644 index 00000000000..20705ecc8e4 --- /dev/null +++ b/board/nxp/common/i2c_common.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020-21 NXP + * Copyright 2021 Microsoft Corporation + */ + +#include +#include +#include "i2c_common.h" + +#if CONFIG_IS_ENABLED(DM_I2C) + +/* If DM is in use, retrieve the chip for the specified bus number */ +int fsl_i2c_get_device(int address, int bus, DEVICE_HANDLE_T *dev) +{ + int ret = i2c_get_chip_for_busnum(bus, address, 1, dev); + + if (ret) + printf("I2C: Bus %d has no device with address 0x%02X\n", + bus, address); + return ret; +} + +#else + +/* Handle is passed directly */ +int fsl_i2c_get_device(int address, int bus, DEVICE_HANDLE_T *dev) +{ + *dev = address; + return 0; +} + +#endif diff --git a/board/nxp/common/i2c_common.h b/board/nxp/common/i2c_common.h new file mode 100644 index 00000000000..77a7b6aedd7 --- /dev/null +++ b/board/nxp/common/i2c_common.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020-21 NXP + * Copyright 2021 Microsoft Corporation + */ + +#ifndef __NXP_I2C_COMMON_H__ +#define __NXP_I2C_COMMON_H__ + +/* Common functionality shared by the I2C drivers for VID and the mux. */ +#if CONFIG_IS_ENABLED(DM_I2C) +#define DEVICE_HANDLE_T struct udevice * + +#define I2C_READ(dev, register, data, length) \ + dm_i2c_read(dev, register, data, length) +#define I2C_WRITE(dev, register, data, length) \ + dm_i2c_write(dev, register, data, length) +#else +#define DEVICE_HANDLE_T int + +#define I2C_READ(dev, register, data, length) \ + i2c_read(dev, register, 1, data, length) +#define I2C_WRITE(dev, register, data, length) \ + i2c_write(dev, register, 1, data, length) +#endif + +int fsl_i2c_get_device(int address, int bus, DEVICE_HANDLE_T *dev); + +#endif diff --git a/board/nxp/common/i2c_mux.c b/board/nxp/common/i2c_mux.c new file mode 100644 index 00000000000..89151ccaf06 --- /dev/null +++ b/board/nxp/common/i2c_mux.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020-21 NXP + * Copyright 2021 Microsoft Corporation + */ + +#include +#include +#include +#include "i2c_common.h" +#include "i2c_mux.h" + +/* + * A new Kconfig option for something that used to always be built should be + * "default y". + */ +#ifdef CONFIG_FSL_USE_PCA9547_MUX + +int select_i2c_ch_pca9547(u8 ch, int bus) +{ + int ret; + DEVICE_HANDLE_T dev; + + /* Open device handle */ + ret = fsl_i2c_get_device(I2C_MUX_PCA_ADDR_PRI, bus, &dev); + if (ret) { + printf("PCA: No PCA9547 device found\n"); + return ret; + } + + ret = I2C_WRITE(dev, 0, &ch, sizeof(ch)); + if (ret) { + printf("PCA: Unable to select channel %d (%d)\n", (int)ch, ret); + return ret; + } + + return 0; +} + +#endif diff --git a/board/nxp/common/i2c_mux.h b/board/nxp/common/i2c_mux.h new file mode 100644 index 00000000000..0870c1918e6 --- /dev/null +++ b/board/nxp/common/i2c_mux.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020-21 NXP + * Copyright 2021 Microsoft Corporation + */ + +#ifndef __NXP_I2C_MUX_H__ +#define __NXP_I2C_MUX_H__ + +#ifdef CONFIG_FSL_USE_PCA9547_MUX +int select_i2c_ch_pca9547(u8 ch, int bus); +#endif + +#endif diff --git a/board/nxp/common/ics307_clk.c b/board/nxp/common/ics307_clk.c new file mode 100644 index 00000000000..af30faa0c5f --- /dev/null +++ b/board/nxp/common/ics307_clk.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include + +#include "ics307_clk.h" + +#if defined(CONFIG_FSL_NGPIXIS) +#include "ngpixis.h" +#define fpga_reg pixis +#elif defined(CONFIG_FSL_QIXIS) +#include "qixis.h" +#define fpga_reg ((struct qixis *)QIXIS_BASE) +#else +#include "pixis.h" +#define fpga_reg pixis +#endif + +/* define for SYS CLK or CLK1Frequency */ +#define TTL 1 +#define CLK2 0 +#define CRYSTAL 0 +#define MAX_VDW (511 + 8) +#define MAX_RDW (127 + 2) +#define MIN_VDW (4 + 8) +#define MIN_RDW (1 + 2) +#define NUM_OD_SETTING 8 +/* + * These defines cover the industrial temperature range part, + * for commercial, change below to 400000 and 55000, respectively + */ +#define MAX_VCO 360000 +#define MIN_VCO 60000 + +/* decode S[0-2] to Output Divider (OD) */ +static u8 ics307_s_to_od[] = { + 10, 2, 8, 4, 5, 7, 3, 6 +}; + +/* + * Find one solution to generate required frequency for SYSCLK + * out_freq: KHz, required frequency to the SYSCLK + * the result will be retuned with component RDW, VDW, OD, TTL, + * CLK2 and crystal + */ +unsigned long ics307_sysclk_calculator(unsigned long out_freq) +{ + const unsigned long input_freq = CFG_ICS307_REFCLK_HZ; + unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od; + unsigned long tmp_out, diff, result = 0; + int found = 0; + + for (odp = 0; odp < NUM_OD_SETTING; odp++) { + od = ics307_s_to_od[odp]; + if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO) + continue; + for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) { + /* Calculate the VDW */ + vdw = out_freq * 1000 * od * rdw / (input_freq * 2); + if (vdw > MAX_VDW) + vdw = MAX_VDW; + if (vdw < MIN_VDW) + continue; + /* Calculate the temp out frequency */ + tmp_out = input_freq * 2 * vdw / (rdw * od * 1000); + diff = max(out_freq, tmp_out) - min(out_freq, tmp_out); + /* + * calculate the percent, the precision is 1/1000 + * If greater than 1/1000, continue + * otherwise, we think the solution is we required + */ + if (diff * 1000 / out_freq > 1) + continue; + else { + s_vdw = vdw; + s_rdw = rdw; + s_odp = odp; + found = 1; + break; + } + } + } + + if (found) + result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 | + CLK2 << 19 | TTL << 21 | CRYSTAL << 22; + + debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8, + ics307_s_to_od[s_odp]); + return result; +} + +/* + * Calculate frequency being generated by ICS307-02 clock chip based upon + * the control bytes being programmed into it. + */ +static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2) +{ + const unsigned long input_freq = CFG_ICS307_REFCLK_HZ; + unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); + unsigned long rdw = cw2 & 0x7F; + unsigned long od = ics307_s_to_od[cw0 & 0x7]; + unsigned long freq; + + /* + * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD) + * + * cw0: C1 C0 TTL F1 F0 S2 S1 S0 + * cw1: V8 V7 V6 V5 V4 V3 V2 V1 + * cw2: V0 R6 R5 R4 R3 R2 R1 R0 + * + * R6:R0 = Reference Divider Word (RDW) + * V8:V0 = VCO Divider Word (VDW) + * S2:S0 = Output Divider Select (OD) + * F1:F0 = Function of CLK2 Output + * TTL = duty cycle + * C1:C0 = internal load capacitance for cyrstal + * + */ + + freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od); + + debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2, + freq); + return freq; +} + +unsigned long get_board_sys_clk(void) +{ + return ics307_clk_freq( + in_8(&fpga_reg->sclk[0]), + in_8(&fpga_reg->sclk[1]), + in_8(&fpga_reg->sclk[2])); +} + +#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ +unsigned long get_board_ddr_clk(void) +{ + return ics307_clk_freq( + in_8(&fpga_reg->dclk[0]), + in_8(&fpga_reg->dclk[1]), + in_8(&fpga_reg->dclk[2])); +} +#endif diff --git a/board/nxp/common/ics307_clk.h b/board/nxp/common/ics307_clk.h new file mode 100644 index 00000000000..163496930c8 --- /dev/null +++ b/board/nxp/common/ics307_clk.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + */ +#ifndef __ICS_CLK_H_ +#define __ICS_CLK_H_ 1 + +#ifndef __ASSEMBLY__ + +extern unsigned long get_board_sys_clk(void); +extern unsigned long ics307_sysclk_calculator(unsigned long out_freq); +#endif + +#endif /* __ICS_CLK_H_ */ diff --git a/board/nxp/common/ls102xa_stream_id.c b/board/nxp/common/ls102xa_stream_id.c new file mode 100644 index 00000000000..bf76274c43c --- /dev/null +++ b/board/nxp/common/ls102xa_stream_id.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor + */ + +#include +#include +#include + +void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num) +{ + void *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; + int i; + u32 icid; + + for (i = 0; i < num; i++) { + icid = (id[i].stream_id & 0xff) << 24; + out_be32((u32 *)(scfg + id[i].offset), icid); + } +} + +void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size) +{ + int i; + u32 liodn; + + for (i = 0; i < size; i++) { + if (tbl[i].num_ids == 2) + liodn = (tbl[i].id[0] << 16) | tbl[i].id[1]; + else + liodn = tbl[i].id[0]; + + out_le32((u32 *)(tbl[i].reg_offset), liodn); + } +} diff --git a/board/nxp/common/mc34vr500.c b/board/nxp/common/mc34vr500.c new file mode 100644 index 00000000000..cf14b29a3ec --- /dev/null +++ b/board/nxp/common/mc34vr500.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Hou Zhiqiang + */ + +#include +#include +#include +#include +#include + +static uint8_t swxvolt_addr[4] = { MC34VR500_SW1VOLT, + MC34VR500_SW2VOLT, + MC34VR500_SW3VOLT, + MC34VR500_SW4VOLT }; + +static uint8_t swx_set_point_base[4] = { 13, 9, 9, 9 }; + +int mc34vr500_get_sw_volt(uint8_t sw) +{ + struct pmic *p; + u32 swxvolt; + uint8_t spb; + int sw_volt; + int ret; + + debug("%s: Get SW%u volt from swxvolt_addr = 0x%x\n", + __func__, sw + 1, swxvolt_addr[sw]); + if (sw > SW4) { + printf("%s: Unsupported SW(sw%d)\n", __func__, sw + 1); + return -EINVAL; + } + + p = pmic_get("MC34VR500"); + if (!p) { + printf("%s: Did NOT find PMIC MC34VR500\n", __func__); + return -ENODEV; + } + + ret = pmic_probe(p); + if (ret) + return ret; + + ret = pmic_reg_read(p, swxvolt_addr[sw], &swxvolt); + if (ret) { + printf("%s: Failed to get SW%u volt\n", __func__, sw + 1); + return ret; + } + + debug("%s: SW%d step point swxvolt = %u\n", __func__, sw + 1, swxvolt); + spb = swx_set_point_base[sw]; + /* The base of SW volt is 625mV and increase by step 25mV */ + sw_volt = 625 + (swxvolt - spb) * 25; + + debug("%s: SW%u volt = %dmV\n", __func__, sw + 1, sw_volt); + return sw_volt; +} + +int mc34vr500_set_sw_volt(uint8_t sw, int sw_volt) +{ + struct pmic *p; + u32 swxvolt; + uint8_t spb; + int ret; + + debug("%s: Set SW%u volt to %dmV\n", __func__, sw + 1, sw_volt); + /* The least SW volt is 625mV, and only 4 SW outputs */ + if (sw > SW4 || sw_volt < 625) + return -EINVAL; + + p = pmic_get("MC34VR500"); + if (!p) { + printf("%s: Did NOT find PMIC MC34VR500\n", __func__); + return -ENODEV; + } + + ret = pmic_probe(p); + if (ret) + return ret; + + spb = swx_set_point_base[sw]; + /* The base of SW volt is 625mV and increase by step 25mV */ + swxvolt = (sw_volt - 625) / 25 + spb; + debug("%s: SW%d step point swxvolt = %u\n", __func__, sw + 1, swxvolt); + if (swxvolt > 63) + return -EINVAL; + + ret = pmic_reg_write(p, swxvolt_addr[sw], swxvolt); + if (ret) + return ret; + + return 0; +} diff --git a/board/nxp/common/mmc.c b/board/nxp/common/mmc.c new file mode 100644 index 00000000000..00e4f3675fe --- /dev/null +++ b/board/nxp/common/mmc.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2018-2022 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static int check_mmc_autodetect(void) +{ + char *autodetect_str = env_get("mmcautodetect"); + + if (autodetect_str && !strcmp(autodetect_str, "yes")) + return 1; + + return 0; +} + +/* This should be defined for each board */ +__weak int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no; +} + +void board_late_mmc_env_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + if (!check_mmc_autodetect()) + return; + + env_set_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", mmc_map_to_kernel_blk(dev_no)); + env_set("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} diff --git a/board/nxp/common/mpc85xx_sleep.c b/board/nxp/common/mpc85xx_sleep.c new file mode 100644 index 00000000000..d4ca278e883 --- /dev/null +++ b/board/nxp/common/mpc85xx_sleep.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include "sleep.h" +#ifdef CONFIG_U_QE +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +void __weak board_mem_sleep_setup(void) +{ +} + +void __weak board_sleep_prepare(void) +{ +} + +bool is_warm_boot(void) +{ + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + + if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR) + return 1; + + return 0; +} + +void fsl_dp_disable_console(void) +{ + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; +} + +/* + * When wakeup from deep sleep, the first 128 bytes space + * will be used to do DDR training which corrupts the data + * in there. This function will restore them. + */ +static void dp_ddr_restore(void) +{ + u64 *src, *dst; + int i; + struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85xx_SCFG; + + /* get the address of ddr date from SPARECR3 */ + src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8); + dst = (u64 *)(CFG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8); + + for (i = 0; i < DDR_BUFF_LEN / 8; i++) + *dst-- = *src--; + + flush_dcache(); +} + +static void dp_resume_prepare(void) +{ + dp_ddr_restore(); + + board_sleep_prepare(); + + l2cache_init(); +#if defined(CONFIG_RAMBOOT_PBL) + disable_cpc_sram(); +#endif + enable_cpc(); + +#ifdef CONFIG_U_QE + u_qe_resume(); +#endif + +} + +int fsl_dp_resume(void) +{ + u32 start_addr; + void (*kernel_resume)(void); + struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85xx_SCFG; + + if (!is_warm_boot()) + return 0; + + dp_resume_prepare(); + + /* Get the entry address and jump to kernel */ + start_addr = in_be32(&scfg->sparecr[1]); + debug("Entry address is 0x%08x\n", start_addr); + kernel_resume = (void (*)(void))start_addr; + kernel_resume(); + + return 0; +} diff --git a/board/nxp/common/ngpixis.c b/board/nxp/common/ngpixis.c new file mode 100644 index 00000000000..74c345807e6 --- /dev/null +++ b/board/nxp/common/ngpixis.c @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * Copyright 2010-2011 Freescale Semiconductor + * Author: Timur Tabi + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + * + * A "switch" is black rectangular block on the motherboard. It contains + * eight "bits". The ngPIXIS has a set of memory-mapped registers (SWx) that + * shadow the actual physical switches. There is also another set of + * registers (ENx) that tell the ngPIXIS which bits of SWx should actually be + * used to override the values of the bits in the physical switches. + * + * The following macros need to be defined: + * + * PIXIS_BASE - The virtual address of the base of the PIXIS register map + * + * PIXIS_LBMAP_SWITCH - The switch number (i.e. the "x" in "SWx"). This value + * is used in the PIXIS_SW() macro to determine which offset in + * the PIXIS register map corresponds to the physical switch that controls + * the boot bank. + * + * PIXIS_LBMAP_MASK - A bit mask the defines which bits in SWx to use. + * + * PIXIS_LBMAP_SHIFT - The shift value that corresponds to PIXIS_LBMAP_MASK. + * + * PIXIS_LBMAP_ALTBANK - The value to program into SWx to tell the ngPIXIS to + * boot from the alternate bank. + */ + +#include +#include + +#include "ngpixis.h" + +static u8 __pixis_read(unsigned int reg) +{ + void *p = (void *)PIXIS_BASE; + + return in_8(p + reg); +} +u8 pixis_read(unsigned int reg) __attribute__((weak, alias("__pixis_read"))); + +static void __pixis_write(unsigned int reg, u8 value) +{ + void *p = (void *)PIXIS_BASE; + + out_8(p + reg, value); +} +void pixis_write(unsigned int reg, u8 value) + __attribute__((weak, alias("__pixis_write"))); + +/* + * Reset the board. This ignores the ENx registers. + */ +void __pixis_reset(void) +{ + PIXIS_WRITE(rst, 0); + + while (1); +} +void pixis_reset(void) __attribute__((weak, alias("__pixis_reset"))); + +/* + * Reset the board. Like pixis_reset(), but it honors the ENx registers. + */ +void __pixis_bank_reset(void) +{ + PIXIS_WRITE(vctl, 0); + PIXIS_WRITE(vctl, 1); + + while (1); +} +void pixis_bank_reset(void) __attribute__((weak, alias("__pixis_bank_reset"))); + +/** + * Set the boot bank to the power-on default bank + */ +void __clear_altbank(void) +{ + u8 reg; + + /* Tell the ngPIXIS to use this the bits in the physical switch for the + * boot bank value, instead of the SWx register. We need to be careful + * only to set the bits in SWx that correspond to the boot bank. + */ + reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].en); + reg &= ~PIXIS_LBMAP_MASK; + PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].en, reg); +} +void clear_altbank(void) __attribute__((weak, alias("__clear_altbank"))); + +/** + * Set the boot bank to the alternate bank + */ +void __set_altbank(void) +{ + u8 reg; + + /* Program the alternate bank number into the SWx register. + */ + reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].sw); + reg = (reg & ~PIXIS_LBMAP_MASK) | PIXIS_LBMAP_ALTBANK; + PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].sw, reg); + + /* Tell the ngPIXIS to use this the bits in the SWx register for the + * boot bank value, instead of the physical switch. We need to be + * careful only to set the bits in SWx that correspond to the boot bank. + */ + reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].en); + reg |= PIXIS_LBMAP_MASK; + PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].en, reg); +} +void set_altbank(void) __attribute__((weak, alias("__set_altbank"))); + +#ifdef DEBUG +static void pixis_dump_regs(void) +{ + unsigned int i; + + printf("id=%02x\n", PIXIS_READ(id)); + printf("arch=%02x\n", PIXIS_READ(arch)); + printf("scver=%02x\n", PIXIS_READ(scver)); + printf("csr=%02x\n", PIXIS_READ(csr)); + printf("rst=%02x\n", PIXIS_READ(rst)); + printf("aux=%02x\n", PIXIS_READ(aux)); + printf("spd=%02x\n", PIXIS_READ(spd)); + printf("brdcfg0=%02x\n", PIXIS_READ(brdcfg0)); + printf("brdcfg1=%02x\n", PIXIS_READ(brdcfg1)); + printf("addr=%02x\n", PIXIS_READ(addr)); + printf("data=%02x\n", PIXIS_READ(data)); + printf("led=%02x\n", PIXIS_READ(led)); + printf("vctl=%02x\n", PIXIS_READ(vctl)); + printf("vstat=%02x\n", PIXIS_READ(vstat)); + printf("vcfgen0=%02x\n", PIXIS_READ(vcfgen0)); + printf("ocmcsr=%02x\n", PIXIS_READ(ocmcsr)); + printf("ocmmsg=%02x\n", PIXIS_READ(ocmmsg)); + printf("gmdbg=%02x\n", PIXIS_READ(gmdbg)); + printf("sclk=%02x%02x%02x\n", + PIXIS_READ(sclk[0]), PIXIS_READ(sclk[1]), PIXIS_READ(sclk[2])); + printf("dclk=%02x%02x%02x\n", + PIXIS_READ(dclk[0]), PIXIS_READ(dclk[1]), PIXIS_READ(dclk[2])); + printf("watch=%02x\n", PIXIS_READ(watch)); + + for (i = 0; i < 8; i++) { + printf("SW%u=%02x/%02x ", i + 1, + PIXIS_READ(s[i].sw), PIXIS_READ(s[i].en)); + } + putc('\n'); +} +#endif + +void pixis_sysclk_set(unsigned long sysclk) +{ + unsigned long freq_word; + u8 sclk0, sclk1, sclk2; + + freq_word = ics307_sysclk_calculator(sysclk); + sclk2 = freq_word & 0xff; + sclk1 = (freq_word >> 8) & 0xff; + sclk0 = (freq_word >> 16) & 0xff; + + /* set SYSCLK enable bit */ + PIXIS_WRITE(vcfgen0, 0x01); + + /* SYSCLK to required frequency */ + PIXIS_WRITE(sclk[0], sclk0); + PIXIS_WRITE(sclk[1], sclk1); + PIXIS_WRITE(sclk[2], sclk2); +} + +int pixis_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + unsigned int i; + unsigned long sysclk; + char *p_altbank = NULL; +#ifdef DEBUG + char *p_dump = NULL; +#endif + char *unknown_param = NULL; + + /* No args is a simple reset request. + */ + if (argc <= 1) + pixis_reset(); + + for (i = 1; i < argc; i++) { + if (strcmp(argv[i], "altbank") == 0) { + p_altbank = argv[i]; + continue; + } + +#ifdef DEBUG + if (strcmp(argv[i], "dump") == 0) { + p_dump = argv[i]; + continue; + } +#endif + if (strcmp(argv[i], "sysclk") == 0) { + sysclk = simple_strtoul(argv[i + 1], NULL, 0); + i += 1; + pixis_sysclk_set(sysclk); + continue; + } + + unknown_param = argv[i]; + } + + if (unknown_param) { + printf("Invalid option: %s\n", unknown_param); + return 1; + } + +#ifdef DEBUG + if (p_dump) { + pixis_dump_regs(); + + /* 'dump' ignores other commands */ + return 0; + } +#endif + + if (p_altbank) + set_altbank(); + else + clear_altbank(); + + pixis_bank_reset(); + + /* Shouldn't be reached. */ + return 0; +} + +U_BOOT_LONGHELP(pixis, + "- hard reset to default bank\n" + "pixis_reset altbank - reset to alternate bank\n" +#ifdef DEBUG + "pixis_reset dump - display the PIXIS registers\n" +#endif + "pixis_reset sysclk - reset with SYSCLK frequency(KHz)\n"); + +U_BOOT_CMD( + pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd, + "Reset the board using the FPGA sequencer", pixis_help_text + ); diff --git a/board/nxp/common/ngpixis.h b/board/nxp/common/ngpixis.h new file mode 100644 index 00000000000..7a20ee015fa --- /dev/null +++ b/board/nxp/common/ngpixis.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/** + * Copyright 2010-2011 Freescale Semiconductor + * Author: Timur Tabi + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* ngPIXIS register set. Hopefully, this won't change too much over time. + * Feel free to add board-specific #ifdefs where necessary. + */ +typedef struct ngpixis { + u8 id; + u8 arch; + u8 scver; + u8 csr; + u8 rst; + u8 serclk; + u8 aux; + u8 spd; + u8 brdcfg0; + u8 brdcfg1; /* On some boards, this register is called 'dma' */ + u8 addr; + u8 brdcfg2; + u8 gpiodir; + u8 data; + u8 led; + u8 tag; + u8 vctl; + u8 vstat; + u8 vcfgen0; + u8 res4; + u8 ocmcsr; + u8 ocmmsg; + u8 gmdbg; + u8 res5[2]; + u8 sclk[3]; + u8 dclk[3]; + u8 watch; + struct { + u8 sw; + u8 en; + } s[9]; /* s[0]..s[7] is SW1..SW8, and s[8] is SW11 */ +} __attribute__ ((packed)) ngpixis_t; + +/* Pointer to the PIXIS register set */ +#define pixis ((ngpixis_t *)PIXIS_BASE) + +/* The PIXIS SW register that corresponds to board switch X, where x >= 1 */ +#define PIXIS_SW(x) (pixis->s[(x) - 1].sw) + +/* The PIXIS EN register that corresponds to board switch X, where x >= 1 */ +#define PIXIS_EN(x) (pixis->s[(x) - 1].en) + +u8 pixis_read(unsigned int reg); +void pixis_write(unsigned int reg, u8 value); + +#define PIXIS_READ(reg) pixis_read(offsetof(ngpixis_t, reg)) +#define PIXIS_WRITE(reg, value) pixis_write(offsetof(ngpixis_t, reg), value) diff --git a/board/nxp/common/ns_access.c b/board/nxp/common/ns_access.c new file mode 100644 index 00000000000..c46e87f4cce --- /dev/null +++ b/board/nxp/common/ns_access.c @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor + */ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_ARCH_LS1021A +static struct csu_ns_dev ns_dev[] = { + { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, + { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, + { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, + { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, + { CSU_CSLX_OCRAM, CSU_ALL_RW }, + { CSU_CSLX_GIC, CSU_ALL_RW }, + { CSU_CSLX_PCIE1, CSU_ALL_RW }, + { CSU_CSLX_OCRAM2, CSU_ALL_RW }, + { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, + { CSU_CSLX_PCIE2, CSU_ALL_RW }, + { CSU_CSLX_SATA, CSU_ALL_RW }, + { CSU_CSLX_USB3, CSU_ALL_RW }, + { CSU_CSLX_SERDES, CSU_ALL_RW }, + { CSU_CSLX_QDMA, CSU_ALL_RW }, + { CSU_CSLX_LPUART2, CSU_ALL_RW }, + { CSU_CSLX_LPUART1, CSU_ALL_RW }, + { CSU_CSLX_LPUART4, CSU_ALL_RW }, + { CSU_CSLX_LPUART3, CSU_ALL_RW }, + { CSU_CSLX_LPUART6, CSU_ALL_RW }, + { CSU_CSLX_LPUART5, CSU_ALL_RW }, + { CSU_CSLX_DSPI2, CSU_ALL_RW }, + { CSU_CSLX_DSPI1, CSU_ALL_RW }, + { CSU_CSLX_QSPI, CSU_ALL_RW }, + { CSU_CSLX_ESDHC, CSU_ALL_RW }, + { CSU_CSLX_2D_ACE, CSU_ALL_RW }, + { CSU_CSLX_IFC, CSU_ALL_RW }, + { CSU_CSLX_I2C1, CSU_ALL_RW }, + { CSU_CSLX_USB2, CSU_ALL_RW }, + { CSU_CSLX_I2C3, CSU_ALL_RW }, + { CSU_CSLX_I2C2, CSU_ALL_RW }, + { CSU_CSLX_DUART2, CSU_ALL_RW }, + { CSU_CSLX_DUART1, CSU_ALL_RW }, + { CSU_CSLX_WDT2, CSU_ALL_RW }, + { CSU_CSLX_WDT1, CSU_ALL_RW }, + { CSU_CSLX_EDMA, CSU_ALL_RW }, + { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, + { CSU_CSLX_DDR, CSU_ALL_RW }, + { CSU_CSLX_QUICC, CSU_ALL_RW }, + { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, + { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, + { CSU_CSLX_SFP, CSU_ALL_RW }, + { CSU_CSLX_TMU, CSU_ALL_RW }, + { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, + { CSU_CSLX_RESERVED0, CSU_ALL_RW }, + { CSU_CSLX_ETSEC1, CSU_ALL_RW }, + { CSU_CSLX_SEC5_5, CSU_ALL_RW }, + { CSU_CSLX_ETSEC3, CSU_ALL_RW }, + { CSU_CSLX_ETSEC2, CSU_ALL_RW }, + { CSU_CSLX_GPIO2, CSU_ALL_RW }, + { CSU_CSLX_GPIO1, CSU_ALL_RW }, + { CSU_CSLX_GPIO4, CSU_ALL_RW }, + { CSU_CSLX_GPIO3, CSU_ALL_RW }, + { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, + { CSU_CSLX_CSU, CSU_ALL_RW }, + { CSU_CSLX_ASRC, CSU_ALL_RW }, + { CSU_CSLX_SPDIF, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, + { CSU_CSLX_SAI2, CSU_ALL_RW }, + { CSU_CSLX_SAI1, CSU_ALL_RW }, + { CSU_CSLX_SAI4, CSU_ALL_RW }, + { CSU_CSLX_SAI3, CSU_ALL_RW }, + { CSU_CSLX_FTM2, CSU_ALL_RW }, + { CSU_CSLX_FTM1, CSU_ALL_RW }, + { CSU_CSLX_FTM4, CSU_ALL_RW }, + { CSU_CSLX_FTM3, CSU_ALL_RW }, + { CSU_CSLX_FTM6, CSU_ALL_RW }, + { CSU_CSLX_FTM5, CSU_ALL_RW }, + { CSU_CSLX_FTM8, CSU_ALL_RW }, + { CSU_CSLX_FTM7, CSU_ALL_RW }, + { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, + { CSU_CSLX_EPU, CSU_ALL_RW }, + { CSU_CSLX_GDI, CSU_ALL_RW }, + { CSU_CSLX_DDI, CSU_ALL_RW }, + { CSU_CSLX_RESERVED1, CSU_ALL_RW }, + { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, + { CSU_CSLX_RESERVED2, CSU_ALL_RW }, +}; + +#else +static struct csu_ns_dev ns_dev[] = { + {CSU_CSLX_PCIE2_IO, CSU_ALL_RW}, + {CSU_CSLX_PCIE1_IO, CSU_ALL_RW}, + {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW}, + {CSU_CSLX_IFC_MEM, CSU_ALL_RW}, + {CSU_CSLX_OCRAM, CSU_ALL_RW}, + {CSU_CSLX_GIC, CSU_ALL_RW}, + {CSU_CSLX_PCIE1, CSU_ALL_RW}, + {CSU_CSLX_OCRAM2, CSU_ALL_RW}, + {CSU_CSLX_QSPI_MEM, CSU_ALL_RW}, + {CSU_CSLX_PCIE2, CSU_ALL_RW}, + {CSU_CSLX_SATA, CSU_ALL_RW}, + {CSU_CSLX_USB1, CSU_ALL_RW}, + {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW}, + {CSU_CSLX_PCIE3, CSU_ALL_RW}, + {CSU_CSLX_PCIE3_IO, CSU_ALL_RW}, + {CSU_CSLX_USB3, CSU_ALL_RW}, + {CSU_CSLX_USB2, CSU_ALL_RW}, + {CSU_CSLX_PFE, CSU_ALL_RW}, + {CSU_CSLX_SERDES, CSU_ALL_RW}, + {CSU_CSLX_QDMA, CSU_ALL_RW}, + {CSU_CSLX_LPUART2, CSU_ALL_RW}, + {CSU_CSLX_LPUART1, CSU_ALL_RW}, + {CSU_CSLX_LPUART4, CSU_ALL_RW}, + {CSU_CSLX_LPUART3, CSU_ALL_RW}, + {CSU_CSLX_LPUART6, CSU_ALL_RW}, + {CSU_CSLX_LPUART5, CSU_ALL_RW}, + {CSU_CSLX_DSPI1, CSU_ALL_RW}, + {CSU_CSLX_QSPI, CSU_ALL_RW}, + {CSU_CSLX_ESDHC, CSU_ALL_RW}, + {CSU_CSLX_IFC, CSU_ALL_RW}, + {CSU_CSLX_I2C1, CSU_ALL_RW}, + {CSU_CSLX_I2C3, CSU_ALL_RW}, + {CSU_CSLX_I2C2, CSU_ALL_RW}, + {CSU_CSLX_DUART2, CSU_ALL_RW}, + {CSU_CSLX_DUART1, CSU_ALL_RW}, + {CSU_CSLX_WDT2, CSU_ALL_RW}, + {CSU_CSLX_WDT1, CSU_ALL_RW}, + {CSU_CSLX_EDMA, CSU_ALL_RW}, + {CSU_CSLX_SYS_CNT, CSU_ALL_RW}, + {CSU_CSLX_DMA_MUX2, CSU_ALL_RW}, + {CSU_CSLX_DMA_MUX1, CSU_ALL_RW}, + {CSU_CSLX_DDR, CSU_ALL_RW}, + {CSU_CSLX_QUICC, CSU_ALL_RW}, + {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW}, + {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW}, + {CSU_CSLX_SFP, CSU_ALL_RW}, + {CSU_CSLX_TMU, CSU_ALL_RW}, + {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW}, + {CSU_CSLX_SCFG, CSU_ALL_RW}, + {CSU_CSLX_FM, CSU_ALL_RW}, + {CSU_CSLX_SEC5_5, CSU_ALL_RW}, + {CSU_CSLX_BM, CSU_ALL_RW}, + {CSU_CSLX_QM, CSU_ALL_RW}, + {CSU_CSLX_GPIO2, CSU_ALL_RW}, + {CSU_CSLX_GPIO1, CSU_ALL_RW}, + {CSU_CSLX_GPIO4, CSU_ALL_RW}, + {CSU_CSLX_GPIO3, CSU_ALL_RW}, + {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW}, + {CSU_CSLX_CSU, CSU_ALL_RW}, + {CSU_CSLX_IIC4, CSU_ALL_RW}, + {CSU_CSLX_WDT4, CSU_ALL_RW}, + {CSU_CSLX_WDT3, CSU_ALL_RW}, + {CSU_CSLX_ESDHC2, CSU_ALL_RW}, + {CSU_CSLX_WDT5, CSU_ALL_RW}, + {CSU_CSLX_SAI2, CSU_ALL_RW}, + {CSU_CSLX_SAI1, CSU_ALL_RW}, + {CSU_CSLX_SAI4, CSU_ALL_RW}, + {CSU_CSLX_SAI3, CSU_ALL_RW}, + {CSU_CSLX_FTM2, CSU_ALL_RW}, + {CSU_CSLX_FTM1, CSU_ALL_RW}, + {CSU_CSLX_FTM4, CSU_ALL_RW}, + {CSU_CSLX_FTM3, CSU_ALL_RW}, + {CSU_CSLX_FTM6, CSU_ALL_RW}, + {CSU_CSLX_FTM5, CSU_ALL_RW}, + {CSU_CSLX_FTM8, CSU_ALL_RW}, + {CSU_CSLX_FTM7, CSU_ALL_RW}, + {CSU_CSLX_DSCR, CSU_ALL_RW}, +}; +#endif + +void set_devices_ns_access(unsigned long index, u16 val) +{ + u32 *base = (u32 *)CFG_SYS_FSL_CSU_ADDR; + u32 *reg; + uint32_t tmp; + + reg = base + index / 2; + tmp = in_be32(reg); + if (index % 2 == 0) { + tmp &= 0x0000ffff; + tmp |= val << 16; + } else { + tmp &= 0xffff0000; + tmp |= val; + } + + out_be32(reg, tmp); +} + +static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) +{ + int i; + + for (i = 0; i < num; i++) + set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val); +} + +void enable_layerscape_ns_access(void) +{ +#ifdef CONFIG_ARM64 + if (current_el() == 3) +#endif + enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +} + +void set_pcie_ns_access(int pcie, u16 val) +{ + switch (pcie) { +#ifdef CONFIG_PCIE1 + case PCIE1: + set_devices_ns_access(CSU_CSLX_PCIE1, val); + set_devices_ns_access(CSU_CSLX_PCIE1_IO, val); + return; +#endif +#ifdef CONFIG_PCIE2 + case PCIE2: + set_devices_ns_access(CSU_CSLX_PCIE2, val); + set_devices_ns_access(CSU_CSLX_PCIE2_IO, val); + return; +#endif +#ifdef CONFIG_PCIE3 + case PCIE3: + set_devices_ns_access(CSU_CSLX_PCIE3, val); + set_devices_ns_access(CSU_CSLX_PCIE3_IO, val); + return; +#endif + default: + debug("The PCIE%d doesn't exist!\n", pcie); + return; + } +} diff --git a/board/nxp/common/p_corenet/Makefile b/board/nxp/common/p_corenet/Makefile new file mode 100644 index 00000000000..ce156018a06 --- /dev/null +++ b/board/nxp/common/p_corenet/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2002-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y += law.o +obj-y += tlb.o diff --git a/board/nxp/common/p_corenet/law.c b/board/nxp/common/p_corenet/law.c new file mode 100644 index 00000000000..83818d6d847 --- /dev/null +++ b/board/nxp/common/p_corenet/law.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), +#endif +#ifdef PIXIS_BASE_PHYS + SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), +#endif +#ifdef CPLD_BASE_PHYS + SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), +#endif +#ifdef CFG_SYS_DCSRBAR_PHYS + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/nxp/common/p_corenet/tlb.c b/board/nxp/common/p_corenet/tlb.c new file mode 100644 index 00000000000..cebdedfa4a7 --- /dev/null +++ b/board/nxp/common/p_corenet/tlb.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#include +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), +#ifdef CPLD_BASE + SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 0), +#endif + +#ifdef PIXIS_BASE + SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 0), +#endif + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) + +#if !defined(CONFIG_NXP_ESBC) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot + * the physical address of the SRAM is at CFG_SYS_INIT_L3_ADDR, + * and virtual address is CONFIG_SYS_MONITOR_BASE + */ + + SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000, + CFG_SYS_INIT_L3_ADDR & 0xfff00000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#endif + +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) + /* + * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the + * space is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CFG_SYS_PCIE1_MEM_PHYS + 0x40000000, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CFG_SYS_PCIE1_MEM_PHYS + 0x50000000, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, + MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x00100000, + CFG_SYS_BMAN_MEM_PHYS + 0x00100000, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_1M, 1), +#endif +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, + MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x00100000, + CFG_SYS_QMAN_MEM_PHYS + 0x00100000, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_1M, 1), +#endif +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_4M, 1), +#endif +#ifdef CFG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_1M, 1), +#endif +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE + /* + * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for + * fetching ucode and ENV from master + */ + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 17, BOOKE_PAGESZ_1M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/nxp/common/pfuze.c b/board/nxp/common/pfuze.c new file mode 100644 index 00000000000..0d7a94fd232 --- /dev/null +++ b/board/nxp/common/pfuze.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include +#include +#include + +#ifndef CONFIG_DM_PMIC_PFUZE100 +int pfuze_mode_init(struct pmic *p, u32 mode) +{ + unsigned char offset, i, switch_num; + u32 id; + int ret; + + pmic_reg_read(p, PFUZE100_DEVICEID, &id); + id = id & 0xf; + + if (id == 0) { + switch_num = 6; + offset = PFUZE100_SW1CMODE; + } else if (id == 1) { + switch_num = 4; + offset = PFUZE100_SW2MODE; + } else { + printf("Not supported, id=%d\n", id); + return -EINVAL; + } + + ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); + if (ret < 0) { + printf("Set SW1AB mode error!\n"); + return ret; + } + + for (i = 0; i < switch_num - 1; i++) { + ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); + if (ret < 0) { + printf("Set switch 0x%x mode error!\n", + offset + i * SWITCH_SIZE); + return ret; + } + } + + return ret; +} + +struct pmic *pfuze_common_init(unsigned char i2cbus) +{ + struct pmic *p; + int ret; + unsigned int reg; + + ret = power_pfuze100_init(i2cbus); + if (ret) + return NULL; + + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return NULL; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + /* Set SW1AB stanby volage to 0.975V */ + pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PFUZE100_SW1ABCONF, ®); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); + + /* Set SW1C standby voltage to 0.975V */ + pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); + + /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PFUZE100_SW1CCONF, ®); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(p, PFUZE100_SW1CCONF, reg); + + return p; +} +#elif defined(CONFIG_DM_PMIC) +int pfuze_mode_init(struct udevice *dev, u32 mode) +{ + unsigned char offset, i, switch_num; + u32 id; + int ret; + + id = pmic_reg_read(dev, PFUZE100_DEVICEID); + id = id & 0xf; + + if (id == 0) { + switch_num = 6; + offset = PFUZE100_SW1CMODE; + } else if (id == 1) { + switch_num = 4; + offset = PFUZE100_SW2MODE; + } else { + printf("Not supported, id=%d\n", id); + return -EINVAL; + } + + ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode); + if (ret < 0) { + printf("Set SW1AB mode error!\n"); + return ret; + } + + for (i = 0; i < switch_num - 1; i++) { + ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode); + if (ret < 0) { + printf("Set switch 0x%x mode error!\n", + offset + i * SWITCH_SIZE); + return ret; + } + } + + return ret; +} + +struct udevice *pfuze_common_init(void) +{ + struct udevice *dev; + int ret; + unsigned int reg, dev_id, rev_id; + + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) + return NULL; + + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* Set SW1AB stanby volage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* Set SW1C standby voltage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + + return dev; +} +#endif diff --git a/board/nxp/common/pfuze.h b/board/nxp/common/pfuze.h new file mode 100644 index 00000000000..45b49afaeb7 --- /dev/null +++ b/board/nxp/common/pfuze.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __PFUZE_BOARD_HELPER__ +#define __PFUZE_BOARD_HELPER__ + +#ifdef CONFIG_DM_PMIC_PFUZE100 +struct udevice *pfuze_common_init(void); +int pfuze_mode_init(struct udevice *dev, u32 mode); +#else +struct pmic *pfuze_common_init(unsigned char i2cbus); +int pfuze_mode_init(struct pmic *p, u32 mode); +#endif + +#endif diff --git a/board/nxp/common/qixis.c b/board/nxp/common/qixis.c new file mode 100644 index 00000000000..04cad48f033 --- /dev/null +++ b/board/nxp/common/qixis.c @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2011 Freescale Semiconductor + * Copyright 2020 NXP + * Author: Shengzhou Liu + * + * This file provides support for the QIXIS of some Freescale reference boards. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "qixis.h" + +#ifndef QIXIS_LBMAP_BRDCFG_REG +/* + * For consistency with existing platforms + */ +#define QIXIS_LBMAP_BRDCFG_REG 0x00 +#endif + +#ifndef QIXIS_RCFG_CTL_RECONFIG_IDLE +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#endif +#ifndef QIXIS_RCFG_CTL_RECONFIG_START +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#endif + +#ifdef CFG_SYS_I2C_FPGA_ADDR +u8 qixis_read_i2c(unsigned int reg) +{ +#if !CONFIG_IS_ENABLED(DM_I2C) + return i2c_reg_read(CFG_SYS_I2C_FPGA_ADDR, reg); +#else + struct udevice *dev; + + if (i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev)) + return 0xff; + + return dm_i2c_reg_read(dev, reg); +#endif +} + +void qixis_write_i2c(unsigned int reg, u8 value) +{ + u8 val = value; +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_reg_write(CFG_SYS_I2C_FPGA_ADDR, reg, val); +#else + struct udevice *dev; + + if (!i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev)) + dm_i2c_reg_write(dev, reg, val); +#endif + +} +#endif + +#ifdef QIXIS_BASE +u8 qixis_read(unsigned int reg) +{ + void *p = (void *)QIXIS_BASE; + + return in_8(p + reg); +} + +void qixis_write(unsigned int reg, u8 value) +{ + void *p = (void *)QIXIS_BASE; + + out_8(p + reg, value); +} +#endif + +u16 qixis_read_minor(void) +{ + u16 minor; + + /* this data is in little endian */ + QIXIS_WRITE(tagdata, 5); + minor = QIXIS_READ(tagdata); + QIXIS_WRITE(tagdata, 6); + minor += QIXIS_READ(tagdata) << 8; + + return minor; +} + +char *qixis_read_time(char *result) +{ + time_t time = 0; + int i; + + /* timestamp is in 32-bit big endian */ + for (i = 8; i <= 11; i++) { + QIXIS_WRITE(tagdata, i); + time = (time << 8) + QIXIS_READ(tagdata); + } + + return ctime_r(&time, result); +} + +char *qixis_read_tag(char *buf) +{ + int i; + char tag, *ptr = buf; + + for (i = 16; i <= 63; i++) { + QIXIS_WRITE(tagdata, i); + tag = QIXIS_READ(tagdata); + *(ptr++) = tag; + if (!tag) + break; + } + if (i > 63) + *ptr = '\0'; + + return buf; +} + +/* + * return the string of binary of u8 in the format of + * 1010 10_0. The masked bit is filled as underscore. + */ +const char *byte_to_binary_mask(u8 val, u8 mask, char *buf) +{ + char *ptr; + int i; + + ptr = buf; + for (i = 0x80; i > 0x08 ; i >>= 1, ptr++) + *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0'); + *(ptr++) = ' '; + for (i = 0x08; i > 0 ; i >>= 1, ptr++) + *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0'); + + *ptr = '\0'; + + return buf; +} + +#ifdef QIXIS_RST_FORCE_MEM +void board_assert_mem_reset(void) +{ + u8 rst; + + rst = QIXIS_READ(rst_frc[0]); + if (!(rst & QIXIS_RST_FORCE_MEM)) + QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM); +} + +void board_deassert_mem_reset(void) +{ + u8 rst; + + rst = QIXIS_READ(rst_frc[0]); + if (rst & QIXIS_RST_FORCE_MEM) + QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM); +} +#endif + +#ifndef CONFIG_XPL_BUILD +static void qixis_reset(void) +{ + QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET); +} + +#ifdef QIXIS_LBMAP_ALTBANK +static void qixis_bank_reset(void) +{ + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); +} +#endif + +static void __maybe_unused set_lbmap(int lbmap) +{ + u8 reg; + + reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); + reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap; + QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg); +} + +static void __maybe_unused set_rcw_src(int rcw_src) +{ +#ifdef CONFIG_NXP_LSCH3_2 + QIXIS_WRITE(dutcfg[0], (rcw_src & 0xff)); +#else + u8 reg; + + reg = QIXIS_READ(dutcfg[1]); + reg = (reg & ~1) | (rcw_src & 1); + QIXIS_WRITE(dutcfg[1], reg); + QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff); +#endif +} + +static void qixis_dump_regs(void) +{ + int i; + + printf("id = %02x\n", QIXIS_READ(id)); + printf("arch = %02x\n", QIXIS_READ(arch)); + printf("scver = %02x\n", QIXIS_READ(scver)); + printf("model = %02x\n", QIXIS_READ(model)); + printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl)); + printf("aux = %02x\n", QIXIS_READ(aux)); + for (i = 0; i < 16; i++) + printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i])); + for (i = 0; i < 16; i++) + printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i])); + printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]), + QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2])); + printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]), + QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2])); + printf("aux = %02x\n", QIXIS_READ(aux)); + printf("watch = %02x\n", QIXIS_READ(watch)); + printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys)); + printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl)); + printf("present = %02x\n", QIXIS_READ(present)); + printf("present2 = %02x\n", QIXIS_READ(present2)); + printf("clk_spd = %02x\n", QIXIS_READ(clk_spd)); + printf("stat_dut = %02x\n", QIXIS_READ(stat_dut)); + printf("stat_sys = %02x\n", QIXIS_READ(stat_sys)); + printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm)); +} + +void __weak qixis_dump_switch(void) +{ + puts("Reverse engineering switch is not implemented for this board\n"); +} + +static int qixis_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int i; + + if (argc <= 1) { + set_lbmap(QIXIS_LBMAP_DFLTBANK); + qixis_reset(); + } else if (strcmp(argv[1], "altbank") == 0) { +#ifdef QIXIS_LBMAP_ALTBANK + set_lbmap(QIXIS_LBMAP_ALTBANK); + qixis_bank_reset(); +#else + printf("No Altbank!\n"); +#endif + } else if (strcmp(argv[1], "nand") == 0) { +#ifdef QIXIS_LBMAP_NAND + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); + set_lbmap(QIXIS_LBMAP_NAND); + set_rcw_src(QIXIS_RCW_SRC_NAND); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); +#else + printf("Not implemented\n"); +#endif + } else if (strcmp(argv[1], "sd") == 0) { +#ifdef QIXIS_LBMAP_SD + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); +#ifdef NON_EXTENDED_DUTCFG + QIXIS_WRITE(dutcfg[0], QIXIS_RCW_SRC_SD); +#else + set_lbmap(QIXIS_LBMAP_SD); + set_rcw_src(QIXIS_RCW_SRC_SD); +#endif + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); +#else + printf("Not implemented\n"); +#endif + } else if (strcmp(argv[1], "ifc") == 0) { +#ifdef QIXIS_LBMAP_IFC + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); + set_lbmap(QIXIS_LBMAP_IFC); + set_rcw_src(QIXIS_RCW_SRC_IFC); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); +#else + printf("Not implemented\n"); +#endif + } else if (strcmp(argv[1], "emmc") == 0) { +#ifdef QIXIS_LBMAP_EMMC + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); +#ifndef NON_EXTENDED_DUTCFG + set_lbmap(QIXIS_LBMAP_EMMC); +#endif + set_rcw_src(QIXIS_RCW_SRC_EMMC); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); + QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); +#else + printf("Not implemented\n"); +#endif + } else if (strcmp(argv[1], "sd_qspi") == 0) { +#ifdef QIXIS_LBMAP_SD_QSPI + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); + set_lbmap(QIXIS_LBMAP_SD_QSPI); + set_rcw_src(QIXIS_RCW_SRC_SD); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_IDLE); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_START); +#else + printf("Not implemented\n"); +#endif + } else if (strcmp(argv[1], "qspi") == 0) { +#ifdef QIXIS_LBMAP_QSPI + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); + set_lbmap(QIXIS_LBMAP_QSPI); + set_rcw_src(QIXIS_RCW_SRC_QSPI); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_IDLE); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_START); +#else + printf("Not implemented\n"); +#endif + } else if (strcmp(argv[1], "xspi") == 0) { +#ifdef QIXIS_LBMAP_XSPI + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); + set_lbmap(QIXIS_LBMAP_XSPI); + set_rcw_src(QIXIS_RCW_SRC_XSPI); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_IDLE); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_START); +#else + printf("Not implemented\n"); +#endif + } else if (strcmp(argv[1], "watchdog") == 0) { + static char *period[9] = {"2s", "4s", "8s", "16s", "32s", + "1min", "2min", "4min", "8min"}; + u8 rcfg = QIXIS_READ(rcfg_ctl); + + if (argv[2] == NULL) { + printf("qixis watchdog \n"); + return 0; + } + for (i = 0; i < ARRAY_SIZE(period); i++) { + if (strcmp(argv[2], period[i]) == 0) { + /* disable watchdog */ + QIXIS_WRITE(rcfg_ctl, + rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE); + QIXIS_WRITE(watch, ((i<<2) - 1)); + QIXIS_WRITE(rcfg_ctl, rcfg); + return 0; + } + } + } else if (strcmp(argv[1], "dump") == 0) { + qixis_dump_regs(); + return 0; + } else if (strcmp(argv[1], "switch") == 0) { + qixis_dump_switch(); + return 0; + } else { + printf("Invalid option: %s\n", argv[1]); + return 1; + } + + return 0; +} + +U_BOOT_CMD( + qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd, + "Reset the board using the FPGA sequencer", + "- hard reset to default bank\n" + "qixis_reset altbank - reset to alternate bank\n" + "qixis_reset nand - reset to nand\n" + "qixis_reset sd - reset to sd\n" + "qixis_reset sd_qspi - reset to sd with qspi support\n" + "qixis_reset qspi - reset to qspi\n" + "qixis watchdog - set the watchdog period\n" + " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n" + "qixis_reset dump - display the QIXIS registers\n" + "qixis_reset emmc - reset to emmc\n" + "qixis_reset switch - display switch\n" + ); +#endif diff --git a/board/nxp/common/qixis.h b/board/nxp/common/qixis.h new file mode 100644 index 00000000000..0a0df6f34f8 --- /dev/null +++ b/board/nxp/common/qixis.h @@ -0,0 +1,190 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2011 Freescale Semiconductor + * Copyright 2020 NXP + * Author: Shengzhou Liu + * + * This file provides support for the QIXIS of some Freescale reference boards. + */ + +#ifndef __QIXIS_H_ +#define __QIXIS_H_ + +struct qixis { + u8 id; /* ID value uniquely identifying each QDS board type */ + u8 arch; /* Board version information */ + u8 scver; /* QIXIS Version Register */ + u8 model; /* Information of software programming model version */ + u8 tagdata; + u8 ctl_sys; + u8 aux; /* Auxiliary Register,0x06 */ + u8 clk_spd; + u8 stat_dut; + u8 stat_sys; + u8 stat_alrm; + u8 present; + u8 present2; /* Presence Status Register 2,0x0c */ + u8 rcw_ctl; + u8 ctl_led; + u8 i2cblk; + u8 rcfg_ctl; /* Reconfig Control Register,0x10 */ + u8 rcfg_st; + u8 dcm_ad; + u8 dcm_da; + u8 dcmd; + u8 dmsg; + u8 gdc; + u8 gdd; /* DCM Debug Data Register,0x17 */ + u8 dmack; + u8 res1; + u8 sdhc1; + u8 sdhc2; + u8 stat_pres3; + u8 los_stat; + u8 usb_ctl; + u8 watch; /* Watchdog Register,0x1F */ + u8 pwr_ctl[2]; /* Power Control Register,0x20 */ + u8 res2[2]; + u8 pwr_stat[4]; /* Power Status Register,0x24 */ + u8 res3[8]; + u8 clk_spd2[2]; /* SYSCLK clock Speed Register,0x30 */ + u8 res4[2]; + u8 sclk[3]; /* Clock Configuration Registers,0x34 */ + u8 res5; + u8 dclk[3]; + u8 res6; + u8 clk_dspd[3]; + u8 res7; + u8 rst_ctl; /* Reset Control Register,0x40 */ + u8 rst_stat; /* Reset Status Register */ + u8 rst_rsn; /* Reset Reason Register */ + u8 rst_frc[2]; /* Reset Force Registers,0x43 */ + u8 res8[11]; + u8 brdcfg[16]; /* Board Configuration Register,0x50 */ + u8 dutcfg[16]; + u8 rcw_ad[2]; /* RCW SRAM Address Registers,0x70 */ + u8 rcw_data; + u8 res9[5]; + u8 post_ctl; + u8 post_stat; + u8 post_dat[2]; + u8 pi_d[4]; + u8 gpio_io[4]; + u8 gpio_dir[4]; + u8 res10[20]; + u8 rjtag_ctl; + u8 rjtag_dat; + u8 res11[2]; + u8 trig_src[4]; + u8 trig_dst[4]; + u8 trig_stat; + u8 res12[3]; + u8 trig_ctr[4]; + u8 res13[16]; + u8 clk_freq[6]; /* Clock Measurement Registers */ + u8 res_c6[8]; + u8 clk_base[2]; /* Clock Frequency Base Reg */ + u8 res_d0[8]; + u8 cms[2]; /* Core Management Space Address Register, 0xD8 */ + u8 res_c0[6]; + u8 aux2[4]; /* Auxiliary Registers,0xE0 */ + u8 res14[10]; + u8 aux_ad; + u8 aux_da; + u8 res15[16]; +}; + +u8 qixis_read(unsigned int reg); +void qixis_write(unsigned int reg, u8 value); +u16 qixis_read_minor(void); +char *qixis_read_time(char *result); +char *qixis_read_tag(char *buf); +const char *byte_to_binary_mask(u8 val, u8 mask, char *buf); +#ifdef CFG_SYS_I2C_FPGA_ADDR +u8 qixis_read_i2c(unsigned int reg); +void qixis_write_i2c(unsigned int reg, u8 value); +#endif + +#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CFG_SYS_I2C_FPGA_ADDR) +#define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg)) +#define QIXIS_WRITE(reg, value) \ + qixis_write_i2c(offsetof(struct qixis, reg), value) +#else +#define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg)) +#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value) +#endif + +#ifdef CFG_SYS_I2C_FPGA_ADDR +#define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg)) +#define QIXIS_WRITE_I2C(reg, value) \ + qixis_write_i2c(offsetof(struct qixis, reg), value) +#endif + +/* Use for SDHC adapter card type identification and operation */ +#define QIXIS_SDID_MASK 0x07 + +#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC45 0x1 /* eMMC Card Rev4.5 */ +#define QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY 0x2 /* SD/MMC Legacy Card */ +#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC44 0x3 /* eMMC Card Rev4.4 */ +#define QIXIS_ESDHC_ADAPTER_TYPE_RSV 0x4 /* Reserved */ +#define QIXIS_ESDHC_ADAPTER_TYPE_MMC 0x5 /* MMC Card */ +#define QIXIS_ESDHC_ADAPTER_TYPE_SD 0x6 /* SD Card Rev2.0 3.0 */ +#define QIXIS_ESDHC_NO_ADAPTER 0x7 /* No Card is Present*/ + +#define QIXIS_SDHC1_S1V3 0x80 /* SDHC1: SDHC1 3.3V power control */ +#define QIXIS_SDHC1_VS 0x30 /* BRDCFG11: route to SDHC1_VS */ + +#define QIXIS_SDCLKIN 0x08 +#define QIXIS_SDCLKOUT 0x02 +#define QIXIS_DAT5_6_7 0x02 +#define QIXIS_DAT4 0x01 + +#define QIXIS_EVDD_BY_SDHC_VS 0x0c + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \ +defined(CONFIG_TARGET_LX2160ARDB) +#define QIXIS_XMAP_MASK 0x07 +#define QIXIS_RST_CTL_RESET_EN 0x30 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x20 +#define QIXIS_LBMAP_QSPI 0x00 +#define QIXIS_RCW_SRC_QSPI 0xff +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SD +#define QIXIS_LBMAP_EMMC +#define QIXIS_RCW_SRC_SD 0x08 +#define QIXIS_RCW_SRC_EMMC 0x09 +#define NON_EXTENDED_DUTCFG +#endif + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +#define QIXIS_SDID_MASK 0x07 +#define QIXIS_ESDHC_NO_ADAPTER 0x7 +#endif + +/* + * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro. + */ +static inline u8 qixis_esdhc_detect_quirk(void) +{ + /* + * SDHC1 Card ID: + * Specifies the type of card installed in the SDHC1 adapter slot. + * 000= (reserved) + * 001= eMMC V4.5 adapter is installed. + * 010= SD/MMC 3.3V adapter is installed. + * 011= eMMC V4.4 adapter is installed. + * 100= eMMC V5.0 adapter is installed. + * 101= MMC card/Legacy (3.3V) adapter is installed. + * 110= SDCard V2/V3 adapter installed. + * 111= no adapter is installed. + */ + return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) != + QIXIS_ESDHC_NO_ADAPTER); +} + +#endif diff --git a/board/nxp/common/sdhc_boot.c b/board/nxp/common/sdhc_boot.c new file mode 100644 index 00000000000..5ee730cefd0 --- /dev/null +++ b/board/nxp/common/sdhc_boot.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + */ + +#include +#include + +/* + * The environment variables are written to just after the u-boot image + * on SDCard, so we must read the MBR to get the start address and code + * length of the u-boot image, then calculate the address of the env. + */ +#define ESDHC_BOOT_IMAGE_SIZE 0x48 +#define ESDHC_BOOT_IMAGE_ADDR 0x50 + +#define ESDHC_DEFAULT_ENVADDR 0x400 + +int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) +{ + u8 *tmp_buf; + u32 blklen, code_offset, code_len, n; + + blklen = mmc->read_bl_len; + tmp_buf = malloc(blklen); + if (!tmp_buf) + return 1; + + /* read out the first block, get the config data information */ +#ifdef CONFIG_BLK + n = blk_dread(mmc_get_blk_desc(mmc), 0, 1, tmp_buf); +#else + n = mmc->block_dev.block_read(&mmc->block_dev, 0, 1, tmp_buf); +#endif + if (!n) { + free(tmp_buf); + return 1; + } + + /* Get the Source Address, from offset 0x50 */ + code_offset = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_ADDR); + + /* Get the code size from offset 0x48 */ + code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE); + +#ifdef CONFIG_ESDHC_HC_BLK_ADDR + /* + * On soc BSC9131, BSC9132: + * In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and + * code length of these soc specify the memory address in block address + * format. Block length is fixed to 512 bytes as per the SD High + * Capacity specification. + */ + u64 tmp; + + if (mmc->high_capacity) { + tmp = (u64)code_offset * blklen; + tmp += code_len * blklen; + } else + tmp = code_offset + code_len; + + if ((tmp + CONFIG_ENV_SIZE > mmc->capacity) || + (tmp > 0xFFFFFFFFU)) + *env_addr = ESDHC_DEFAULT_ENVADDR; + else + *env_addr = tmp; + + free(tmp_buf); + + return 0; +#endif + + *env_addr = code_offset + code_len; + + free(tmp_buf); + + return 0; +} diff --git a/board/nxp/common/sgmii_riser.h b/board/nxp/common/sgmii_riser.h new file mode 100644 index 00000000000..e1fcc858f3f --- /dev/null +++ b/board/nxp/common/sgmii_riser.h @@ -0,0 +1,16 @@ +/* + * Freescale SGMII Riser Card + * + * This driver supports the SGMII Riser card found on the + * "DS" style of development board from Freescale. + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + */ + +void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num); +void fsl_sgmii_riser_fdt_fixup(void *fdt); diff --git a/board/nxp/common/sleep.h b/board/nxp/common/sleep.h new file mode 100644 index 00000000000..1450baa0725 --- /dev/null +++ b/board/nxp/common/sleep.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __SLEEP_H +#define __SLEEP_H + +#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) +#define DDR_BUFF_LEN 128 + +/* determine if it is a wakeup from deep sleep */ +bool is_warm_boot(void); + +/* disable console output */ +void fsl_dp_disable_console(void); + +/* clean up everything and jump to kernel */ +int fsl_dp_resume(void); +#endif diff --git a/board/nxp/common/spl.h b/board/nxp/common/spl.h new file mode 100644 index 00000000000..d4689d3d726 --- /dev/null +++ b/board/nxp/common/spl.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Google, Inc + */ + +#ifndef __FREESCALE_BOARD_SPL_H +#define __FREESCALE_BOARD_SPL_H + +void fsl_spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst); +void fsl_spi_boot(void) __noreturn; + +#endif diff --git a/board/nxp/common/sys_eeprom.c b/board/nxp/common/sys_eeprom.c new file mode 100644 index 00000000000..ec3c9e37222 --- /dev/null +++ b/board/nxp/common/sys_eeprom.c @@ -0,0 +1,648 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor + * York Sun (yorksun@freescale.com) + * Haiying Wang (haiying.wang@freescale.com) + * Timur Tabi (timur@freescale.com) + */ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SYS_I2C_EEPROM_CCID +#include "../common/eeprom.h" +#define MAX_NUM_PORTS 8 +#endif + +#ifdef CONFIG_SYS_I2C_EEPROM_NXID +/* some boards with non-256-bytes EEPROM have special define */ +/* for MAX_NUM_PORTS in board-specific file */ +#ifndef MAX_NUM_PORTS +#define MAX_NUM_PORTS 16 +#endif +#define NXID_VERSION 1 +#endif + +/** + * static eeprom: EEPROM layout for CCID or NXID formats + * + * See application note AN3638 for details. + */ +static struct __attribute__ ((__packed__)) eeprom { +#ifdef CONFIG_SYS_I2C_EEPROM_CCID + u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'CCID' */ + u8 major; /* 0x04 Board revision, major */ + u8 minor; /* 0x05 Board revision, minor */ + u8 sn[10]; /* 0x06 - 0x0F Serial Number*/ + u8 errata[2]; /* 0x10 - 0x11 Errata Level */ + u8 date[6]; /* 0x12 - 0x17 Build Date */ + u8 res_0[40]; /* 0x18 - 0x3f Reserved */ + u8 mac_count; /* 0x40 Number of MAC addresses */ + u8 mac_flag; /* 0x41 MAC table flags */ + u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */ + u32 crc; /* 0x72 CRC32 checksum */ +#endif +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'NXID' */ + u8 sn[12]; /* 0x04 - 0x0F Serial Number */ + u8 errata[5]; /* 0x10 - 0x14 Errata Level */ + u8 date[6]; /* 0x15 - 0x1a Build Date */ + u8 res_0; /* 0x1b Reserved */ + u32 version; /* 0x1c - 0x1f NXID Version */ + u8 tempcal[8]; /* 0x20 - 0x27 Temperature Calibration Factors */ + u8 tempcalsys[2]; /* 0x28 - 0x29 System Temperature Calibration Factors */ + u8 tempcalflags; /* 0x2a Temperature Calibration Flags */ + u8 res_1[21]; /* 0x2b - 0x3f Reserved */ + u8 mac_count; /* 0x40 Number of MAC addresses */ + u8 mac_flag; /* 0x41 MAC table flags */ + u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0xa1 MAC addresses */ + u8 res_2[90]; /* 0xa2 - 0xfb Reserved */ + u32 crc; /* 0xfc - 0xff CRC32 checksum */ +#endif +} e; + +/* Set to 1 if we've read EEPROM into memory */ +static int has_been_read = 0; + +#ifdef CONFIG_SYS_I2C_EEPROM_NXID +/* Is this a valid NXID EEPROM? */ +#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \ + (e.id[2] == 'I') || (e.id[3] == 'D')) +#endif + +#ifdef CONFIG_SYS_I2C_EEPROM_CCID +/* Is this a valid CCID EEPROM? */ +#define is_valid ((e.id[0] == 'C') || (e.id[1] == 'C') || \ + (e.id[2] == 'I') || (e.id[3] == 'D')) +#endif + +/** + * show_eeprom - display the contents of the EEPROM + */ +static void show_eeprom(void) +{ + int i; + unsigned int crc; + + /* EEPROM tag ID, either CCID or NXID */ +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], + be32_to_cpu(e.version)); +#else + printf("ID: %c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]); +#endif + + /* Serial number */ + printf("SN: %s\n", e.sn); + + /* Errata level. */ +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + printf("Errata: %s\n", e.errata); +#else + printf("Errata: %c%c\n", + e.errata[0] ? e.errata[0] : '.', + e.errata[1] ? e.errata[1] : '.'); +#endif + + /* Build date, BCD date values, as YYMMDDhhmmss */ + printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n", + e.date[0], e.date[1], e.date[2], + e.date[3] & 0x7F, e.date[4], e.date[5], + e.date[3] & 0x80 ? "PM" : ""); + + /* Show MAC addresses */ + for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) { + + u8 *p = e.mac[i]; + + printf("Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n", i, + p[0], p[1], p[2], p[3], p[4], p[5]); + } + + crc = crc32(0, (void *)&e, sizeof(e) - 4); + + if (crc == be32_to_cpu(e.crc)) + printf("CRC: %08x\n", be32_to_cpu(e.crc)); + else + printf("CRC: %08x (should be %08x)\n", + be32_to_cpu(e.crc), crc); + +#ifdef DEBUG + printf("EEPROM dump: (0x%x bytes)\n", sizeof(e)); + for (i = 0; i < sizeof(e); i++) { + if ((i % 16) == 0) + printf("%02X: ", i); + printf("%02X ", ((u8 *)&e)[i]); + if (((i % 16) == 15) || (i == sizeof(e) - 1)) + printf("\n"); + } +#endif +} + +/** + * read_eeprom - read the EEPROM into memory + */ +static int read_eeprom(void) +{ + int ret; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM +#if !CONFIG_IS_ENABLED(DM_I2C) + unsigned int bus; +#endif +#endif + + if (has_been_read) + return 0; + +#ifdef CONFIG_SYS_EEPROM_BUS_NUM +#if !CONFIG_IS_ENABLED(DM_I2C) + bus = i2c_get_bus_num(); + i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); +#endif +#endif + +#if !CONFIG_IS_ENABLED(DM_I2C) + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (void *)&e, sizeof(e)); +#else + struct udevice *dev; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev); +#endif + if (!ret) + ret = dm_i2c_read(dev, 0, (void *)&e, sizeof(e)); +#endif + +#ifdef CONFIG_SYS_EEPROM_BUS_NUM +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_set_bus_num(bus); +#endif +#endif + +#ifdef DEBUG + show_eeprom(); +#endif + + has_been_read = (ret == 0) ? 1 : 0; + + return ret; +} + +/** + * update_crc - update the CRC + * + * This function should be called after each update to the EEPROM structure, + * to make sure the CRC is always correct. + */ +static void update_crc(void) +{ + u32 crc; + + crc = crc32(0, (void *)&e, sizeof(e) - 4); + e.crc = cpu_to_be32(crc); +} + +/** + * prog_eeprom - write the EEPROM from memory + */ +static int prog_eeprom(void) +{ + int ret = 0; + int i; + void *p; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM +#if !CONFIG_IS_ENABLED(DM_I2C) + unsigned int bus; +#endif +#endif + + /* Set the reserved values to 0xFF */ +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + e.res_0 = 0xFF; + memset(e.res_1, 0xFF, sizeof(e.res_1)); +#else + memset(e.res_0, 0xFF, sizeof(e.res_0)); +#endif + update_crc(); + +#if !CONFIG_IS_ENABLED(DM_I2C) +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + bus = i2c_get_bus_num(); + i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); +#endif +#endif + + /* + * The AT24C02 datasheet says that data can only be written in page + * mode, which means 8 bytes at a time, and it takes up to 5ms to + * complete a given write. + */ + for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) { +#if !CONFIG_IS_ENABLED(DM_I2C) + ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + p, min((int)(sizeof(e) - i), 8)); +#else + struct udevice *dev; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#endif + if (!ret) + ret = dm_i2c_write(dev, i, p, min((int)(sizeof(e) - i), + 8)); +#endif + if (ret) + break; + udelay(5000); /* 5ms write cycle timing */ + } + + if (!ret) { + /* Verify the write by reading back the EEPROM and comparing */ + struct eeprom e2; + +#if !CONFIG_IS_ENABLED(DM_I2C) + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (void *)&e2, sizeof(e2)); +#else + struct udevice *dev; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#endif + if (!ret) + ret = dm_i2c_read(dev, 0, (void *)&e2, sizeof(e2)); +#endif + if (!ret && memcmp(&e, &e2, sizeof(e))) + ret = -1; + } + +#if !CONFIG_IS_ENABLED(DM_I2C) +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + i2c_set_bus_num(bus); +#endif +#endif + + if (ret) { + printf("Programming failed.\n"); + has_been_read = 0; + return -1; + } + + printf("Programming passed.\n"); + return 0; +} + +/** + * h2i - converts hex character into a number + * + * This function takes a hexadecimal character (e.g. '7' or 'C') and returns + * the integer equivalent. + */ +static inline u8 h2i(char p) +{ + if ((p >= '0') && (p <= '9')) + return p - '0'; + + if ((p >= 'A') && (p <= 'F')) + return (p - 'A') + 10; + + if ((p >= 'a') && (p <= 'f')) + return (p - 'a') + 10; + + return 0; +} + +/** + * set_date - stores the build date into the EEPROM + * + * This function takes a pointer to a string in the format "YYMMDDhhmmss" + * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string, + * and stores it in the build date field of the EEPROM local copy. + */ +static void set_date(const char *string) +{ + unsigned int i; + + if (strlen(string) != 12) { + printf("Usage: mac date YYMMDDhhmmss\n"); + return; + } + + for (i = 0; i < 6; i++) + e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]); + + update_crc(); +} + +/** + * set_mac_address - stores a MAC address into the EEPROM + * + * This function takes a pointer to MAC address string + * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and + * stores it in one of the MAC address fields of the EEPROM local copy. + */ +static void set_mac_address(unsigned int index, const char *string) +{ + char *p = (char *) string; + unsigned int i; + + if ((index >= MAX_NUM_PORTS) || !string) { + printf("Usage: mac XX:XX:XX:XX:XX:XX\n"); + return; + } + + for (i = 0; *p && (i < 6); i++) { + e.mac[index][i] = hextoul(p, &p); + if (*p == ':') + p++; + } + + update_crc(); +} + +int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + char cmd; + + if (argc == 1) { + show_eeprom(); + return 0; + } + + cmd = argv[1][0]; + + if (cmd == 'r') { + read_eeprom(); + return 0; + } + + if (cmd == 'i') { +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + memcpy(e.id, "NXID", sizeof(e.id)); + e.version = cpu_to_be32(NXID_VERSION); +#else + memcpy(e.id, "CCID", sizeof(e.id)); +#endif + update_crc(); + return 0; + } + + if (!is_valid) { + printf("Please read the EEPROM ('r') and/or set the ID ('i') first.\n"); + return 0; + } + + if (argc == 2) { + switch (cmd) { + case 's': /* save */ + prog_eeprom(); + break; + default: + return CMD_RET_USAGE; + } + + return 0; + } + + /* We know we have at least one parameter */ + + switch (cmd) { + case 'n': /* serial number */ + memset(e.sn, 0, sizeof(e.sn)); + strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1); + update_crc(); + break; + case 'e': /* errata */ +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + memset(e.errata, 0, 5); + strncpy((char *)e.errata, argv[2], 4); +#else + e.errata[0] = argv[2][0]; + e.errata[1] = argv[2][1]; +#endif + update_crc(); + break; + case 'd': /* date BCD format YYMMDDhhmmss */ + set_date(argv[2]); + break; + case 'p': /* MAC table size */ + e.mac_count = hextoul(argv[2], NULL); + update_crc(); + break; + case '0' ... '9': /* "mac 0" through "mac 22" */ + set_mac_address(dectoul(argv[1], NULL), argv[2]); + break; + case 'h': /* help */ + default: + return cmd_usage(cmdtp); + } + + return 0; +} + +/** + * mac_read_from_eeprom - read the MAC addresses from EEPROM + * + * This function reads the MAC addresses from EEPROM and sets the + * appropriate environment variables for each one read. + * + * The environment variables are only set if they haven't been set already. + * This ensures that any user-saved variables are never overwritten. + * + * This function must be called after relocation. + * + * For NXID v1 EEPROMs, we support loading and up-converting the older NXID v0 + * format. In a v0 EEPROM, there are only eight MAC addresses and the CRC is + * located at a different offset. + */ +int mac_read_from_eeprom(void) +{ + unsigned int i; + u32 crc, crc_offset = offsetof(struct eeprom, crc); + u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */ + + puts("EEPROM: "); + + if (read_eeprom()) { + printf("Read failed.\n"); + return 0; + } + + if (!is_valid) { + printf("Invalid ID (%02x %02x %02x %02x)\n", + e.id[0], e.id[1], e.id[2], e.id[3]); + return 0; + } + +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + /* + * If we've read an NXID v0 EEPROM, then we need to set the CRC offset + * to where it is in v0. + */ + if (e.version == 0) + crc_offset = 0x72; +#endif + + crc = crc32(0, (void *)&e, crc_offset); + crcp = (void *)&e + crc_offset; + if (crc != be32_to_cpu(*crcp)) { + printf("CRC mismatch (%08x != %08x)\n", crc, be32_to_cpu(e.crc)); + return 0; + } + +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + /* + * MAC address #9 in v1 occupies the same position as the CRC in v0. + * Erase it so that it's not mistaken for a MAC address. We'll + * update the CRC later. + */ + if (e.version == 0) + memset(e.mac[8], 0xff, 6); +#endif + + for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) { + if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) && + memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) { + char ethaddr[18]; + char enetvar[9]; + + sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", + e.mac[i][0], + e.mac[i][1], + e.mac[i][2], + e.mac[i][3], + e.mac[i][4], + e.mac[i][5]); + sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i); + /* Only initialize environment variables that are blank + * (i.e. have not yet been set) + */ + if (!env_get(enetvar)) + env_set(enetvar, ethaddr); + } + } + +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], + be32_to_cpu(e.version)); +#else + printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]); +#endif + +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + /* + * Now we need to upconvert the data into v1 format. We do this last so + * that at boot time, U-Boot will still say "NXID v0". + */ + if (e.version == 0) { + e.version = cpu_to_be32(NXID_VERSION); + update_crc(); + } +#endif + + return 0; +} + +#ifdef CONFIG_SYS_I2C_EEPROM_CCID + +/** + * get_cpu_board_revision - get the CPU board revision on 85xx boards + * + * Read the EEPROM to determine the board revision. + * + * This function is called before relocation, so we need to read a private + * copy of the EEPROM into a local variable on the stack. + * + * Also, we assume that CONFIG_SYS_EEPROM_BUS_NUM == CONFIG_SYS_SPD_BUS_NUM. The global + * variable i2c_bus_num must be compile-time initialized to CONFIG_SYS_SPD_BUS_NUM, + * so that the SPD code will work. This means that all pre-relocation I2C + * operations can only occur on the CONFIG_SYS_SPD_BUS_NUM bus. So if + * CONFIG_SYS_EEPROM_BUS_NUM != CONFIG_SYS_SPD_BUS_NUM, then we can't read the EEPROM when + * this function is called. Oh well. + */ +unsigned int get_cpu_board_revision(void) +{ + struct board_eeprom { + u32 id; /* 0x00 - 0x03 EEPROM Tag 'CCID' */ + u8 major; /* 0x04 Board revision, major */ + u8 minor; /* 0x05 Board revision, minor */ + } be; + +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (void *)&be, sizeof(be)); +#else + struct udevice *dev; + int ret; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, + CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#else + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + &dev); +#endif + if (!ret) + dm_i2c_read(dev, 0, (void *)&be, sizeof(be)); +#endif + + if (be.id != (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D')) + return MPC85XX_CPU_BOARD_REV(0, 0); + + if ((be.major == 0xff) && (be.minor == 0xff)) + return MPC85XX_CPU_BOARD_REV(0, 0); + + return MPC85XX_CPU_BOARD_REV(be.major, be.minor); +} +#endif + +U_BOOT_LONGHELP(mac, + "[read|save|id|num|errata|date|ports|port_number]\n" + "mac read\n" + " - read EEPROM content into memory data structure\n" + "mac save\n" + " - save memory data structure to the EEPROM\n" + "mac id\n" + " - program system id per hard coded value\n" + "mac num string\n" + " - program system serial number to value string\n" + "mac errata string\n" + " - program errata data to value string\n" + "mac date YYMMDDhhmmss\n" + " - program date to string value YYMMDDhhmmss\n" + "mac ports N\n" + " - program the number of network ports to integer N\n" + "mac X string\n" + " - program MAC addr for port X [X=0,1..] to colon separated string"); + +U_BOOT_CMD( + mac, 3, 1, do_mac, + "display and program the system ID and MAC addresses in EEPROM", + mac_help_text); diff --git a/board/nxp/common/via.h b/board/nxp/common/via.h new file mode 100644 index 00000000000..77cfacc5261 --- /dev/null +++ b/board/nxp/common/via.h @@ -0,0 +1,18 @@ +#ifndef _MPC85xx_VIA_H +void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 1, IDE */ +void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 2, USB ports 0-1 */ +void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 3, USB ports 2-3 */ +void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 5, Power Management */ +void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 6, AC97 Interface */ +void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); +#endif /* _MPC85xx_VIA_H */ diff --git a/board/nxp/common/vid.c b/board/nxp/common/vid.c new file mode 100644 index 00000000000..84cb43fad56 --- /dev/null +++ b/board/nxp/common/vid.c @@ -0,0 +1,797 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020-21 NXP + * Copyright 2020 Stephen Carlson + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_FSL_LSCH2 +#include +#elif defined(CONFIG_FSL_LSCH3) +#include +#else +#include +#endif +#include +#include "i2c_common.h" +#include "vid.h" + +#ifndef I2C_VOL_MONITOR_BUS +#define I2C_VOL_MONITOR_BUS 0 +#endif + +/* Voltages are generally handled in mV to keep them as integers */ +#define MV_PER_V 1000 + +/* + * Select the channel on the I2C mux (on some NXP boards) that contains + * the voltage regulator to use for VID. Return 0 for success or nonzero + * for failure. + */ +int __weak i2c_multiplexer_select_vid_channel(u8 channel) +{ + return 0; +} + +/* + * Compensate for a board specific voltage drop between regulator and SoC. + * Returns the voltage offset in mV. + */ +int __weak board_vdd_drop_compensation(void) +{ + return 0; +} + +/* + * Performs any board specific adjustments after the VID voltage has been + * set. Return 0 for success or nonzero for failure. + */ +int __weak board_adjust_vdd(int vdd) +{ + return 0; +} + +/* + * Processor specific method of converting the fuse value read from VID + * registers into the core voltage to supply. Return the voltage in mV. + */ +u16 __weak soc_get_fuse_vid(int vid_index) +{ + /* Default VDD for Layerscape Chassis 1 devices */ + static const u16 vdd[32] = { + 0, /* unused */ + 9875, /* 0.9875V */ + 9750, + 9625, + 9500, + 9375, + 9250, + 9125, + 9000, + 8875, + 8750, + 8625, + 8500, + 8375, + 8250, + 8125, + 10000, /* 1.0000V */ + 10125, + 10250, + 10375, + 10500, + 10625, + 10750, + 10875, + 11000, + 0, /* reserved */ + }; + return vdd[vid_index]; +} + +#ifndef I2C_VOL_MONITOR_ADDR +#define I2C_VOL_MONITOR_ADDR 0 +#endif + +#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ + defined(CONFIG_VOL_MONITOR_IR36021_READ) +/* + * Get the i2c address configuration for the IR regulator chip + * + * There are some variance in the RDB HW regarding the I2C address configuration + * for the IR regulator chip, which is likely a problem of external resistor + * accuracy. So we just check each address in a hopefully non-intrusive mode + * and use the first one that seems to work + * + * The IR chip can show up under the following addresses: + * 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA) + * 0x09 (Verified on T1040RDB-PA) + * 0x38 (Verified on T2080QDS, T2081QDS, T4240RDB) + */ +static int find_ir_chip_on_i2c(void) +{ + int i2caddress, ret, i; + u8 mfrID; + const int ir_i2c_addr[] = {0x38, 0x08, 0x09}; + DEVICE_HANDLE_T dev; + + /* Check all the address */ + for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) { + i2caddress = ir_i2c_addr[i]; + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); + if (!ret) { + ret = I2C_READ(dev, IR36021_MFR_ID_OFFSET, + (void *)&mfrID, sizeof(mfrID)); + /* If manufacturer ID matches the IR36021 */ + if (!ret && mfrID == IR36021_MFR_ID) + return i2caddress; + } + } + return -1; +} +#endif + +/* Maximum loop count waiting for new voltage to take effect */ +#define MAX_LOOP_WAIT_NEW_VOL 100 +/* Maximum loop count waiting for the voltage to be stable */ +#define MAX_LOOP_WAIT_VOL_STABLE 100 +/* + * read_voltage from sensor on I2C bus + * We use average of 4 readings, waiting for WAIT_FOR_ADC before + * another reading + */ +#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */ + +/* If an INA220 chip is available, we can use it to read back the voltage + * as it may have a higher accuracy than the IR chip for the same purpose + */ +#ifdef CONFIG_VOL_MONITOR_INA220 +#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */ +#define ADC_MIN_ACCURACY 4 +#else +#define WAIT_FOR_ADC 138 /* wait for 138 microseconds for ADC */ +#define ADC_MIN_ACCURACY 4 +#endif + +#ifdef CONFIG_VOL_MONITOR_INA220 +static int read_voltage_from_INA220(int i2caddress) +{ + int i, ret, voltage_read = 0; + u16 vol_mon; + u8 buf[2]; + DEVICE_HANDLE_T dev; + + /* Open device handle */ + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); + if (ret) + return ret; + + for (i = 0; i < NUM_READINGS; i++) { + ret = I2C_READ(dev, I2C_VOL_MONITOR_BUS_V_OFFSET, + (void *)&buf[0], sizeof(buf)); + if (ret) { + printf("VID: failed to read core voltage\n"); + return ret; + } + + vol_mon = (buf[0] << 8) | buf[1]; + if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { + printf("VID: Core voltage sensor error\n"); + return -1; + } + + debug("VID: bus voltage reads 0x%04x\n", vol_mon); + /* LSB = 4mv */ + voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; + udelay(WAIT_FOR_ADC); + } + + /* calculate the average */ + voltage_read /= NUM_READINGS; + + return voltage_read; +} +#endif + +#ifdef CONFIG_VOL_MONITOR_IR36021_READ +/* read voltage from IR */ +static int read_voltage_from_IR(int i2caddress) +{ + int i, ret, voltage_read = 0; + u16 vol_mon; + u8 buf; + DEVICE_HANDLE_T dev; + + /* Open device handle */ + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); + if (ret) + return ret; + + for (i = 0; i < NUM_READINGS; i++) { + ret = I2C_READ(dev, IR36021_LOOP1_VOUT_OFFSET, (void *)&buf, + sizeof(buf)); + if (ret) { + printf("VID: failed to read core voltage\n"); + return ret; + } + vol_mon = buf; + if (!vol_mon) { + printf("VID: Core voltage sensor error\n"); + return -1; + } + debug("VID: bus voltage reads 0x%02x\n", vol_mon); + /* Resolution is 1/128V. We scale up here to get 1/128mV + * and divide at the end + */ + voltage_read += vol_mon * MV_PER_V; + udelay(WAIT_FOR_ADC); + } + /* Scale down to the real mV as IR resolution is 1/128V, rounding up */ + voltage_read = DIV_ROUND_UP(voltage_read, 128); + + /* calculate the average */ + voltage_read /= NUM_READINGS; + + /* Compensate for a board specific voltage drop between regulator and + * SoC before converting into an IR VID value + */ + voltage_read -= board_vdd_drop_compensation(); + + return voltage_read; +} +#endif + +#if defined(CONFIG_VOL_MONITOR_ISL68233_READ) || \ + defined(CONFIG_VOL_MONITOR_LTC3882_READ) || \ + defined(CONFIG_VOL_MONITOR_ISL68233_SET) || \ + defined(CONFIG_VOL_MONITOR_LTC3882_SET) + +/* + * The message displayed if the VOUT exponent causes a resolution + * worse than 1.0 V (if exponent is >= 0). + */ +#define VOUT_WARNING "VID: VOUT_MODE exponent has resolution worse than 1 V!\n" + +/* Checks the PMBus voltage monitor for the format used for voltage values */ +static int get_pmbus_multiplier(DEVICE_HANDLE_T dev) +{ + u8 mode; + int exponent, multiplier, ret; + + ret = I2C_READ(dev, PMBUS_CMD_VOUT_MODE, &mode, sizeof(mode)); + if (ret) { + printf("VID: unable to determine voltage multiplier\n"); + return 1; + } + + /* Upper 3 bits is mode, lower 5 bits is exponent */ + exponent = (int)mode & 0x1F; + mode >>= 5; + switch (mode) { + case 0: + /* Linear, 5 bit twos component exponent */ + if (exponent & 0x10) { + multiplier = 1 << (16 - (exponent & 0xF)); + } else { + /* If exponent is >= 0, then resolution is 1 V! */ + printf(VOUT_WARNING); + multiplier = 1; + } + break; + case 1: + /* VID code identifier */ + printf("VID: custom VID codes are not supported\n"); + multiplier = MV_PER_V; + break; + default: + /* Direct, in mV */ + multiplier = MV_PER_V; + break; + } + + debug("VID: calculated multiplier is %d\n", multiplier); + return multiplier; +} +#endif + +#if defined(CONFIG_VOL_MONITOR_ISL68233_READ) || \ + defined(CONFIG_VOL_MONITOR_LTC3882_READ) +static int read_voltage_from_pmbus(int i2caddress) +{ + int ret, multiplier, vout; + u8 channel = PWM_CHANNEL0; + u16 vcode; + DEVICE_HANDLE_T dev; + + /* Open device handle */ + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); + if (ret) + return ret; + + /* Select the right page */ + ret = I2C_WRITE(dev, PMBUS_CMD_PAGE, &channel, sizeof(channel)); + if (ret) { + printf("VID: failed to select VDD page %d\n", channel); + return ret; + } + + /* VOUT is little endian */ + ret = I2C_READ(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, sizeof(vcode)); + if (ret) { + printf("VID: failed to read core voltage\n"); + return ret; + } + + /* Scale down to the real mV */ + multiplier = get_pmbus_multiplier(dev); + vout = (int)vcode; + /* Multiplier 1000 (direct mode) requires no change to convert */ + if (multiplier != MV_PER_V) + vout = DIV_ROUND_UP(vout * MV_PER_V, multiplier); + return vout - board_vdd_drop_compensation(); +} +#endif + +static int read_voltage(int i2caddress) +{ + int voltage_read; +#ifdef CONFIG_VOL_MONITOR_INA220 + voltage_read = read_voltage_from_INA220(I2C_VOL_MONITOR_ADDR); +#elif defined CONFIG_VOL_MONITOR_IR36021_READ + voltage_read = read_voltage_from_IR(i2caddress); +#elif defined(CONFIG_VOL_MONITOR_ISL68233_READ) || \ + defined(CONFIG_VOL_MONITOR_LTC3882_READ) + voltage_read = read_voltage_from_pmbus(i2caddress); +#else + voltage_read = -1; +#endif + return voltage_read; +} + +#ifdef CONFIG_VOL_MONITOR_IR36021_SET +/* + * We need to calculate how long before the voltage stops to drop + * or increase. It returns with the loop count. Each loop takes + * several readings (WAIT_FOR_ADC) + */ +static int wait_for_new_voltage(int vdd, int i2caddress) +{ + int timeout, vdd_current; + + vdd_current = read_voltage(i2caddress); + /* wait until voltage starts to reach the target. Voltage slew + * rates by typical regulators will always lead to stable readings + * within each fairly long ADC interval in comparison to the + * intended voltage delta change until the target voltage is + * reached. The fairly small voltage delta change to any target + * VID voltage also means that this function will always complete + * within few iterations. If the timeout was ever reached, it would + * point to a serious failure in the regulator system. + */ + for (timeout = 0; + abs(vdd - vdd_current) > (IR_VDD_STEP_UP + IR_VDD_STEP_DOWN) && + timeout < MAX_LOOP_WAIT_NEW_VOL; timeout++) { + vdd_current = read_voltage(i2caddress); + } + if (timeout >= MAX_LOOP_WAIT_NEW_VOL) { + printf("VID: Voltage adjustment timeout\n"); + return -1; + } + return timeout; +} + +/* + * Blocks and reads the VID voltage until it stabilizes, or the + * timeout expires + */ +static int wait_for_voltage_stable(int i2caddress) +{ + int timeout, vdd_current, vdd; + + vdd = read_voltage(i2caddress); + udelay(NUM_READINGS * WAIT_FOR_ADC); + + vdd_current = read_voltage(i2caddress); + /* + * The maximum timeout is + * MAX_LOOP_WAIT_VOL_STABLE * NUM_READINGS * WAIT_FOR_ADC + */ + for (timeout = MAX_LOOP_WAIT_VOL_STABLE; + abs(vdd - vdd_current) > ADC_MIN_ACCURACY && + timeout > 0; timeout--) { + vdd = vdd_current; + udelay(NUM_READINGS * WAIT_FOR_ADC); + vdd_current = read_voltage(i2caddress); + } + if (timeout == 0) + return -1; + return vdd_current; +} + +/* Sets the VID voltage using the IR36021 */ +static int set_voltage_to_IR(int i2caddress, int vdd) +{ + int wait, vdd_last; + int ret; + u8 vid; + DEVICE_HANDLE_T dev; + + /* Open device handle */ + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); + if (ret) + return ret; + + /* Compensate for a board specific voltage drop between regulator and + * SoC before converting into an IR VID value + */ + vdd += board_vdd_drop_compensation(); +#ifdef CONFIG_FSL_LSCH2 + vid = DIV_ROUND_UP(vdd - 265, 5); +#else + vid = DIV_ROUND_UP(vdd - 245, 5); +#endif + + ret = I2C_WRITE(dev, IR36021_LOOP1_MANUAL_ID_OFFSET, (void *)&vid, + sizeof(vid)); + if (ret) { + printf("VID: failed to write new voltage\n"); + return -1; + } + wait = wait_for_new_voltage(vdd, i2caddress); + if (wait < 0) + return -1; + debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC); + + vdd_last = wait_for_voltage_stable(i2caddress); + if (vdd_last < 0) + return -1; + debug("VID: Current voltage is %d mV\n", vdd_last); + return vdd_last; +} +#endif + +#if defined(CONFIG_VOL_MONITOR_ISL68233_SET) || \ + defined(CONFIG_VOL_MONITOR_LTC3882_SET) +static int set_voltage_to_pmbus(int i2caddress, int vdd) +{ + int ret, vdd_last, vdd_target = vdd; + int count = MAX_LOOP_WAIT_NEW_VOL, temp = 0, multiplier; + unsigned char value; + + /* The data to be sent with the PMBus command PAGE_PLUS_WRITE */ + u8 buffer[5] = { 0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, 0, 0 }; + DEVICE_HANDLE_T dev; + + /* Open device handle */ + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); + if (ret) + return ret; + + /* Scale up to the proper value for the VOUT command, little endian */ + multiplier = get_pmbus_multiplier(dev); + vdd += board_vdd_drop_compensation(); + if (multiplier != MV_PER_V) + vdd = DIV_ROUND_UP(vdd * multiplier, MV_PER_V); + buffer[3] = vdd & 0xFF; + buffer[4] = (vdd & 0xFF00) >> 8; + + /* Check write protect state */ + ret = I2C_READ(dev, PMBUS_CMD_WRITE_PROTECT, (void *)&value, + sizeof(value)); + if (ret) + goto exit; + + if (value != EN_WRITE_ALL_CMD) { + value = EN_WRITE_ALL_CMD; + ret = I2C_WRITE(dev, PMBUS_CMD_WRITE_PROTECT, + (void *)&value, sizeof(value)); + if (ret) + goto exit; + } + + /* Write the desired voltage code to the regulator */ + ret = I2C_WRITE(dev, PMBUS_CMD_PAGE_PLUS_WRITE, (void *)&buffer[0], + sizeof(buffer)); + if (ret) { + printf("VID: I2C failed to write to the voltage regulator\n"); + return -1; + } + +exit: + /* Wait for the voltage to get to the desired value */ + do { + vdd_last = read_voltage_from_pmbus(i2caddress); + if (vdd_last < 0) { + printf("VID: Couldn't read sensor abort VID adjust\n"); + return -1; + } + count--; + temp = vdd_last - vdd_target; + } while ((abs(temp) > 2) && (count > 0)); + + return vdd_last; +} +#endif + +static int set_voltage(int i2caddress, int vdd) +{ + int vdd_last = -1; + +#ifdef CONFIG_VOL_MONITOR_IR36021_SET + vdd_last = set_voltage_to_IR(i2caddress, vdd); +#elif defined(CONFIG_VOL_MONITOR_ISL68233_SET) || \ + defined(CONFIG_VOL_MONITOR_LTC3882_SET) + vdd_last = set_voltage_to_pmbus(i2caddress, vdd); +#else + #error Specific voltage monitor must be defined +#endif + return vdd_last; +} + +int adjust_vdd(ulong vdd_override) +{ + int re_enable = disable_interrupts(); +#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); +#else + ccsr_gur_t __iomem *gur = + (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); +#endif + u8 vid; + u32 fusesr; + int vdd_current, vdd_last, vdd_target; + int ret, i2caddress = I2C_VOL_MONITOR_ADDR; + unsigned long vdd_string_override; + char *vdd_string; + +#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ + defined(CONFIG_VOL_MONITOR_IR36021_READ) + u8 buf; + DEVICE_HANDLE_T dev; +#endif + + /* + * VID is used according to the table below + * --------------------------------------- + * | DA_V | + * |-------------------------------------| + * | 5b00000 | 5b00001-5b11110 | 5b11111 | + * ---------------+---------+-----------------+---------| + * | D | 5b00000 | NO VID | VID = DA_V | NO VID | + * | A |----------+---------+-----------------+---------| + * | _ | 5b00001 |VID = | VID = |VID = | + * | V | ~ | DA_V_ALT| DA_V_ALT | DA_A_VLT| + * | _ | 5b11110 | | | | + * | A |----------+---------+-----------------+---------| + * | L | 5b11111 | No VID | VID = DA_V | NO VID | + * | T | | | | | + * ------------------------------------------------------ + */ +#if defined(CONFIG_FSL_LSCH3) + fusesr = in_le32(&gur->dcfg_fusesr); + vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; + if (vid == 0 || vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK) { + vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & + FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; + } +#elif defined(CONFIG_FSL_LSCH2) + fusesr = in_be32(&gur->dcfg_fusesr); + vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK; + if (vid == 0 || vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK) { + vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & + FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; + } +#else + fusesr = in_be32(&gur->dcfg_fusesr); + vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; + if (vid == 0 || vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK) { + vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & + FSL_CORENET_DCFG_FUSESR_VID_MASK; + } +#endif + vdd_target = soc_get_fuse_vid((int)vid); + + ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); + if (ret) { + debug("VID: I2C failed to switch channel\n"); + ret = -1; + goto exit; + } + +#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ + defined(CONFIG_VOL_MONITOR_IR36021_READ) + ret = find_ir_chip_on_i2c(); + if (ret < 0) { + printf("VID: Could not find voltage regulator on I2C.\n"); + ret = -1; + goto exit; + } else { + i2caddress = ret; + debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); + } + + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); + if (ret) + return ret; + + /* check IR chip work on Intel mode */ + ret = I2C_READ(dev, IR36021_INTEL_MODE_OFFSET, (void *)&buf, + sizeof(buf)); + if (ret) { + printf("VID: failed to read IR chip mode.\n"); + ret = -1; + goto exit; + } + if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) { + printf("VID: IR Chip is not used in Intel mode.\n"); + ret = -1; + goto exit; + } +#endif + + /* check override variable for overriding VDD */ + vdd_string = env_get(CONFIG_VID_FLS_ENV); + debug("VID: Initial VDD value is %d mV\n", + DIV_ROUND_UP(vdd_target, 10)); + if (vdd_override == 0 && vdd_string && + !strict_strtoul(vdd_string, 10, &vdd_string_override)) + vdd_override = vdd_string_override; + if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) { + vdd_target = vdd_override * 10; /* convert to 1/10 mV */ + debug("VID: VDD override is %lu\n", vdd_override); + } else if (vdd_override != 0) { + printf("VID: Invalid VDD value.\n"); + } + if (vdd_target == 0) { + debug("VID: VID not used\n"); + ret = 0; + goto exit; + } else { + /* divide and round up by 10 to get a value in mV */ + vdd_target = DIV_ROUND_UP(vdd_target, 10); + debug("VID: vid = %d mV\n", vdd_target); + } + + /* + * Read voltage monitor to check real voltage. + */ + vdd_last = read_voltage(i2caddress); + if (vdd_last < 0) { + printf("VID: Couldn't read sensor abort VID adjustment\n"); + ret = -1; + goto exit; + } + vdd_current = vdd_last; + debug("VID: Core voltage is currently at %d mV\n", vdd_last); + +#if defined(CONFIG_VOL_MONITOR_LTC3882_SET) || \ + defined(CONFIG_VOL_MONITOR_ISL68233_SET) + /* Set the target voltage */ + vdd_current = set_voltage(i2caddress, vdd_target); + vdd_last = vdd_current; +#else + /* + * Adjust voltage to at or one step above target. + * As measurements are less precise than setting the values + * we may run through dummy steps that cancel each other + * when stepping up and then down. + */ + while (vdd_last > 0 && + vdd_last < vdd_target) { + vdd_current += IR_VDD_STEP_UP; + vdd_last = set_voltage(i2caddress, vdd_current); + } + while (vdd_last > 0 && + vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) { + vdd_current -= IR_VDD_STEP_DOWN; + vdd_last = set_voltage(i2caddress, vdd_current); + } +#endif + + /* Board specific adjustments */ + if (board_adjust_vdd(vdd_target) < 0) { + ret = -1; + goto exit; + } + + if (vdd_last > 0) + printf("VID: Core voltage after adjustment is at %d mV\n", + vdd_last); + else + ret = -1; +exit: + if (re_enable) + enable_interrupts(); + + i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); + + return ret; +} + +static int print_vdd(void) +{ + int vdd_last, ret, i2caddress = I2C_VOL_MONITOR_ADDR; + + ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); + if (ret) { + debug("VID : I2c failed to switch channel\n"); + return -1; + } +#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ + defined(CONFIG_VOL_MONITOR_IR36021_READ) + ret = find_ir_chip_on_i2c(); + if (ret < 0) { + printf("VID: Could not find voltage regulator on I2C.\n"); + goto exit; + } else { + i2caddress = ret; + debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); + } +#endif + + /* + * Read voltage monitor to check real voltage. + */ + vdd_last = read_voltage(i2caddress); + if (vdd_last < 0) { + printf("VID: Couldn't read sensor abort VID adjustment\n"); + goto exit; + } + printf("VID: Core voltage is at %d mV\n", vdd_last); +exit: + i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); + + return ret < 0 ? -1 : 0; +} + +static int do_vdd_override(struct cmd_tbl *cmdtp, + int flag, int argc, + char *const argv[]) +{ + ulong override; + int ret = 0; + + if (argc < 2) + return CMD_RET_USAGE; + + if (!strict_strtoul(argv[1], 10, &override)) { + ret = adjust_vdd(override); + if (ret < 0) + return CMD_RET_FAILURE; + } else + return CMD_RET_USAGE; + return 0; +} + +static int do_vdd_read(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (argc < 1) + return CMD_RET_USAGE; + print_vdd(); + + return 0; +} + +U_BOOT_CMD( + vdd_override, 2, 0, do_vdd_override, + "override VDD", + " - override with the voltage specified in mV, eg. 1050" +); + +U_BOOT_CMD( + vdd_read, 1, 0, do_vdd_read, + "read VDD", + " - Read the voltage specified in mV" +); diff --git a/board/nxp/common/vid.h b/board/nxp/common/vid.h new file mode 100644 index 00000000000..b34c080b4ba --- /dev/null +++ b/board/nxp/common/vid.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + */ + +#ifndef __VID_H_ +#define __VID_H_ + +/* IR36021 command codes */ +#define IR36021_LOOP1_MANUAL_ID_OFFSET 0x6A +#define IR36021_LOOP1_VOUT_OFFSET 0x9A +#define IR36021_MFR_ID_OFFSET 0x92 +#define IR36021_MFR_ID 0x43 +#define IR36021_INTEL_MODE_OFFSET 0x14 +#define IR36021_MODE_MASK 0x20 +#define IR36021_INTEL_MODE 0x00 +#define IR36021_AMD_MODE 0x20 + +/* Step the IR regulator in 5mV increments */ +#define IR_VDD_STEP_DOWN 5 +#define IR_VDD_STEP_UP 5 + +/* LTC3882 */ +#define PMBUS_CMD_WRITE_PROTECT 0x10 +/* + * WRITE_PROTECT command supported values + * 0x80: Disable all writes except WRITE_PROTECT, PAGE, + * STORE_USER_ALL and MFR_EE_UNLOCK commands. + * 0x40: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ALL, + * MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS and CLEAR_FAULTS commands. + * Individual faults can also be cleared by writing a 1 to the + * respective status bit. + * 0x20: Disable all writes except WRITE_PROTECT, PAGE, STORE_USER_ ALL, + * MFR_EE_UNLOCK, OPERATION, CLEAR_PEAKS, CLEAR_FAULTS, ON_OFF_CONFIG + * and VOUT_COMMAND commands. Individual faults can be cleared by + * writing a 1 to the respective status bit. + * 0x00: Enables write to all commands + */ +#define EN_WRITE_ALL_CMD (0) + +#ifdef CONFIG_TARGET_LX2160ARDB +/* The lowest and highest voltage allowed*/ +#define VDD_MV_MIN 775 +#define VDD_MV_MAX 855 +#endif + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +/* The lowest and highest voltage allowed*/ +#define VDD_MV_MIN 775 +#define VDD_MV_MAX 925 +#endif + +/* PM Bus commands code for LTC3882*/ +#define PWM_CHANNEL0 0x0 +#define PMBUS_CMD_PAGE 0x0 +#define PMBUS_CMD_READ_VOUT 0x8B +#define PMBUS_CMD_VOUT_MODE 0x20 +#define PMBUS_CMD_VOUT_COMMAND 0x21 +#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \ +defined(CONFIG_TARGET_LX2160ARDB) +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 +#define I2C_VOL_MONITOR_ADDR 0x63 +#define I2C_MUX_CH_VOL_MONITOR 0xA +#endif + +int adjust_vdd(ulong vdd_override); +u16 soc_get_fuse_vid(int vid_index); + +#endif /* __VID_H_ */ diff --git a/board/nxp/common/vsc3316_3308.h b/board/nxp/common/vsc3316_3308.h new file mode 100644 index 00000000000..9725d6d9e39 --- /dev/null +++ b/board/nxp/common/vsc3316_3308.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + */ + +#ifndef __VSC_CROSSBAR_H_ +#define __VSC_CROSSBAR_H_ + +#include +#include + +int vsc_if_enable(unsigned int vsc_addr); +int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2], + unsigned int num_con); +#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR +int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2], + unsigned int num_con); +#endif +int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2], + unsigned int num_con); +void vsc_wp_config(unsigned int vsc_addr); + +#endif /* __VSC_CROSSBAR_H_ */ diff --git a/board/nxp/imx8mm_evk/Kconfig b/board/nxp/imx8mm_evk/Kconfig new file mode 100644 index 00000000000..3b7025af053 --- /dev/null +++ b/board/nxp/imx8mm_evk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_IMX8MM_EVK + +config SYS_BOARD + default "imx8mm_evk" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "imx8mm_evk" + +config IMX_CONFIG + default "board/nxp/imx8mm_evk/imximage-8mm-lpddr4.cfg" + +endif diff --git a/board/nxp/imx8mm_evk/MAINTAINERS b/board/nxp/imx8mm_evk/MAINTAINERS new file mode 100644 index 00000000000..d63202418f9 --- /dev/null +++ b/board/nxp/imx8mm_evk/MAINTAINERS @@ -0,0 +1,7 @@ +i.MX8MM EVK BOARD +M: Peng Fan +S: Maintained +F: board/nxp/imx8mm_evk/ +F: include/configs/imx8mm_evk.h +F: configs/imx8mm_evk_defconfig +F: configs/imx8mm_evk_fspi_defconfig diff --git a/board/nxp/imx8mm_evk/Makefile b/board/nxp/imx8mm_evk/Makefile new file mode 100644 index 00000000000..9fecd8dd8cb --- /dev/null +++ b/board/nxp/imx8mm_evk/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mm_evk.o + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +endif diff --git a/board/nxp/imx8mm_evk/imx8mm_evk.c b/board/nxp/imx8mm_evk/imx8mm_evk.c new file mode 100644 index 00000000000..ecc20768cb5 --- /dev/null +++ b/board/nxp/imx8mm_evk/imx8mm_evk.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0xead2005e, 0x7780, 0x400b, 0x93, 0x48, \ + 0xa2, 0x82, 0xeb, 0x85, 0x8b, 0x6b) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MM-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 2=flash-bin raw 0x42 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + +#if IS_ENABLED(CONFIG_FEC_MXC) +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_FEC_MXC)) + setup_fec(); + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + board_late_mmc_env_init(); + + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + env_set("board_name", "EVK"); + env_set("board_rev", "iMX8MM"); + } + + return 0; +} diff --git a/board/nxp/imx8mm_evk/imx8mm_evk.env b/board/nxp/imx8mm_evk/imx8mm_evk.env new file mode 100644 index 00000000000..299b8472c74 --- /dev/null +++ b/board/nxp/imx8mm_evk/imx8mm_evk.env @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +boot_fdt=try +boot_fit=no +boot_targets=mmc1 mmc2 dhcp +bootm_size=0x10000000 +console=ttymxc1,115200 +fdt_addr_r=0x48000000 +fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtoverlay_addr_r=0x49000000 +initrd_addr=0x48080000 +image=Image +ip_dyn=yes +kernel_addr_r=0x42000000 +loadaddr=CONFIG_SYS_LOAD_ADDR +mmcautodetect=yes +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk1p2 rootwait rw +prepare_mcore=setenv mcore_clk clk-imx8mm.mcore_booted; +pxefile_addr_r=0x40100000 +ramdisk_addr_r=0x48080000 +scriptaddr=0x40000000 + +mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} +prepare_mcore=setenv mcore_clk clk-imx8mn.mcore_booted +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if run loadfdt; then + booti ${loadaddr} - ${fdt_addr_r}; + else + echo WARN: Cannot load the DT; + fi; + fi +netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + ${get_cmd} ${loadaddr} ${image}; + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + booti ${loadaddr} - ${fdt_addr_r}; + else + echo WARN: Cannot load the DT; + fi; + fi; +bsp_bootcmd=echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; + if mmc rescan; then + if run loadimage; then + run mmcboot; + else + run netboot; + fi; + fi; diff --git a/board/nxp/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg b/board/nxp/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg new file mode 100644 index 00000000000..fcace8a93a0 --- /dev/null +++ b/board/nxp/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +BOOT_FROM fspi +LOADER u-boot-spl-ddr.bin 0x7E2000 diff --git a/board/nxp/imx8mm_evk/imximage-8mm-lpddr4.cfg b/board/nxp/imx8mm_evk/imximage-8mm-lpddr4.cfg new file mode 100644 index 00000000000..20061521f22 --- /dev/null +++ b/board/nxp/imx8mm_evk/imximage-8mm-lpddr4.cfg @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + + +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x7E1000 diff --git a/board/nxp/imx8mm_evk/lpddr4_timing.c b/board/nxp/imx8mm_evk/lpddr4_timing.c new file mode 100644 index 00000000000..4373ca624e4 --- /dev/null +++ b/board/nxp/imx8mm_evk/lpddr4_timing.c @@ -0,0 +1,1848 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * + * Generated code from MX8M_DDR_tool + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /* Initialize DDRC registers */ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x223 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b00d2 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x66004d }, + { 0x3d4000ec, 0x16004d }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x1f }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + + /* performance setting */ + { 0x3d400250, 0x29001701 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + + /* P1: 400mts */ + { 0x3d402020, 0x21 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d040 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004d }, + { 0x3d4020ec, 0x16004d }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + + /* p2: 100mts */ + { 0x3d403020, 0x21 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d040 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x310000 }, + { 0x3d4030e8, 0x66004d }, + { 0x3d4030ec, 0x16004d }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + + /* default boot point */ + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x120024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x220024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0xdc }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0xdc }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0xdc }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x200c7, 0x21 }, + { 0x1200c7, 0x21 }, + { 0x2200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x1200ca, 0x24 }, + { 0x2200ca, 0x24 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xf }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a7, 0x0 }, + { 0x900a8, 0x790 }, + { 0x900a9, 0x11a }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x7b2 }, + { 0x900af, 0x2a }, + { 0x900b0, 0x0 }, + { 0x900b1, 0x7c8 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xc }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x0 }, + { 0x90169, 0x8 }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x448 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0xf }, + { 0x9016e, 0x7c0 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x630 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x618 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x7c8 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x10c }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x5d }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x120010, 0x5a }, + { 0x120011, 0x3 }, + { 0x220010, 0x5a }, + { 0x220011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x2003a, 0x2 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; diff --git a/board/nxp/imx8mm_evk/spl.c b/board/nxp/imx8mm_evk/spl.c new file mode 100644 index 00000000000..cd251d274ff --- /dev/null +++ b/board/nxp/imx8mm_evk/spl.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019, 2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case USB_BOOT: + return BOOT_DEVICE_BOARD; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC1; + case SD3_BOOT: + case MMC3_BOOT: + return BOOT_DEVICE_MMC2; + case QSPI_BOOT: + return BOOT_DEVICE_NOR; + default: + return BOOT_DEVICE_NONE; + } +} + +static void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +void spl_board_init(void) +{ + arch_misc_init(); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +static int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pca9450@25", &dev); + if (ret == -ENODEV) { + puts("No pmic\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* Buck 1 DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* Set DVS1 to 0.8v for suspend */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10); + + /* increase VDD_DRAM to 0.95v for 3Ghz DDR */ + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C); + + /* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */ + pmic_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a); + + /* set VDD_SNVS_0V8 from default 0.85V */ + pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); + + return 0; +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + arch_cpu_init(); + + init_uart_clk(1); + + timer_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@30380000", + &dev); + if (ret < 0) { + printf("Failed to find clock node. Check device tree\n"); + hang(); + } + + preloader_console_init(); + + enable_tzc380(); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/board/nxp/imx8mn_evk/Kconfig b/board/nxp/imx8mn_evk/Kconfig new file mode 100644 index 00000000000..9ae21db6974 --- /dev/null +++ b/board/nxp/imx8mn_evk/Kconfig @@ -0,0 +1,18 @@ +if TARGET_IMX8MN_EVK || TARGET_IMX8MN_DDR4_EVK + +config SYS_BOARD + default "imx8mn_evk" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "imx8mn_evk" + +config IMX8MN_LOW_DRIVE_MODE + bool "Enable the low drive mode of iMX8MN on EVK board" + +config IMX_CONFIG + default "board/nxp/imx8mn_evk/imximage-8mn-ddr4.cfg" + +endif diff --git a/board/nxp/imx8mn_evk/MAINTAINERS b/board/nxp/imx8mn_evk/MAINTAINERS new file mode 100644 index 00000000000..19ebfb2b1a1 --- /dev/null +++ b/board/nxp/imx8mn_evk/MAINTAINERS @@ -0,0 +1,7 @@ +i.MX8MN EVK BOARD +M: Peng Fan +S: Maintained +F: board/nxp/imx8mn_evk/ +F: include/configs/imx8mn_evk.h +F: configs/imx8mn_ddr4_evk_defconfig +F: configs/imx8mn_evk_defconfig diff --git a/board/nxp/imx8mn_evk/Makefile b/board/nxp/imx8mn_evk/Makefile new file mode 100644 index 00000000000..5ef666a36dd --- /dev/null +++ b/board/nxp/imx8mn_evk/Makefile @@ -0,0 +1,18 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mn_evk.o + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_ld.o +obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing_ld.o +else +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o +endif +endif diff --git a/board/nxp/imx8mn_evk/ddr4_timing.c b/board/nxp/imx8mn_evk/ddr4_timing.c new file mode 100644 index 00000000000..ce39c9e2bcf --- /dev/null +++ b/board/nxp/imx8mn_evk/ddr4_timing.c @@ -0,0 +1,1053 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400000, 0x81040010 }, + { 0x3d400030, 0x20 }, + { 0x3d400034, 0x221306 }, + { 0x3d400050, 0x210070 }, + { 0x3d400054, 0x10008 }, + { 0x3d400060, 0x0 }, + { 0x3d400064, 0x92014a }, + { 0x3d4000c0, 0x0 }, + { 0x3d4000c4, 0x1000 }, + { 0x3d4000d0, 0xc0030126 }, + { 0x3d4000d4, 0x770000 }, + { 0x3d4000dc, 0x8340105 }, + { 0x3d4000e0, 0x180200 }, + { 0x3d4000e4, 0x110000 }, + { 0x3d4000e8, 0x2000600 }, + { 0x3d4000ec, 0x810 }, + { 0x3d4000f0, 0x20 }, + { 0x3d4000f4, 0xec7 }, + { 0x3d400100, 0x11122914 }, + { 0x3d400104, 0x4051c }, + { 0x3d400108, 0x608050d }, + { 0x3d40010c, 0x400c }, + { 0x3d400110, 0x8030409 }, + { 0x3d400114, 0x6060403 }, + { 0x3d40011c, 0x606 }, + { 0x3d400120, 0x7070d0c }, + { 0x3d400124, 0x2040a }, + { 0x3d40012c, 0x1809010e }, + { 0x3d400130, 0x8 }, + { 0x3d40013c, 0x0 }, + { 0x3d400180, 0x1000040 }, + { 0x3d400184, 0x493e }, + { 0x3d400190, 0x38b8207 }, + { 0x3d400194, 0x2020303 }, + { 0x3d400198, 0x7f04011 }, + { 0x3d40019c, 0xb0 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0x48005a }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x1 }, + { 0x3d4001b4, 0xb07 }, + { 0x3d4001b8, 0x4 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d400200, 0x3f1f }, + { 0x3d400204, 0x3f0909 }, + { 0x3d400208, 0x700 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf07 }, + { 0x3d400220, 0x3f01 }, + { 0x3d400240, 0x6000610 }, + { 0x3d400244, 0x1323 }, + { 0x3d400400, 0x100 }, + + /* performance setting */ + { 0x3d400250, 0x00001f05 }, + { 0x3d400254, 0x1f }, + { 0x3d400264, 0x900003ff }, + { 0x3d40026c, 0x200003ff }, + { 0x3d400494, 0x01000e00 }, + { 0x3d400498, 0x03ff0000 }, + { 0x3d40049c, 0x01000e00 }, + { 0x3d4004a0, 0x03ff0000 }, + + { 0x3d402050, 0x210070 }, + { 0x3d402064, 0x400093 }, + { 0x3d4020dc, 0x105 }, + { 0x3d4020e0, 0x0 }, + { 0x3d4020e8, 0x2000600 }, + { 0x3d4020ec, 0x10 }, + { 0x3d402100, 0xb081209 }, + { 0x3d402104, 0x2020d }, + { 0x3d402108, 0x5050309 }, + { 0x3d40210c, 0x400c }, + { 0x3d402110, 0x5030206 }, + { 0x3d402114, 0x3030202 }, + { 0x3d40211c, 0x303 }, + { 0x3d402120, 0x4040d06 }, + { 0x3d402124, 0x20208 }, + { 0x3d40212c, 0x1205010e }, + { 0x3d402130, 0x8 }, + { 0x3d40213c, 0x0 }, + { 0x3d402180, 0x1000040 }, + { 0x3d402190, 0x3848204 }, + { 0x3d402194, 0x2020303 }, + { 0x3d4021b4, 0x404 }, + { 0x3d4021b8, 0x4 }, + { 0x3d402240, 0x6000600 }, + { 0x3d4020f4, 0xec7 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x1005f, 0x2fd }, + { 0x1015f, 0x2fd }, + { 0x1105f, 0x2fd }, + { 0x1115f, 0x2fd }, + { 0x11005f, 0x2fd }, + { 0x11015f, 0x2fd }, + { 0x11105f, 0x2fd }, + { 0x11115f, 0x2fd }, + { 0x55, 0x355 }, + { 0x1055, 0x355 }, + { 0x2055, 0x355 }, + { 0x3055, 0x355 }, + { 0x4055, 0x55 }, + { 0x5055, 0x55 }, + { 0x6055, 0x355 }, + { 0x7055, 0x355 }, + { 0x8055, 0x355 }, + { 0x9055, 0x355 }, + { 0x200c5, 0xa }, + { 0x1200c5, 0x6 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x1 }, + { 0x20024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x6 }, + { 0x120056, 0xa }, + { 0x1004d, 0x1a }, + { 0x1014d, 0x1a }, + { 0x1104d, 0x1a }, + { 0x1114d, 0x1a }, + { 0x11004d, 0x1a }, + { 0x11014d, 0x1a }, + { 0x11104d, 0x1a }, + { 0x11114d, 0x1a }, + { 0x10049, 0xe38 }, + { 0x10149, 0xe38 }, + { 0x11049, 0xe38 }, + { 0x11149, 0xe38 }, + { 0x110049, 0xe38 }, + { 0x110149, 0xe38 }, + { 0x111049, 0xe38 }, + { 0x111149, 0xe38 }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x1 }, + { 0x20075, 0x2 }, + { 0x20050, 0x0 }, + { 0x20008, 0x258 }, + { 0x120008, 0x10a }, + { 0x20088, 0x9 }, + { 0x200b2, 0x268 }, + { 0x10043, 0x5b1 }, + { 0x10143, 0x5b1 }, + { 0x11043, 0x5b1 }, + { 0x11143, 0x5b1 }, + { 0x1200b2, 0x268 }, + { 0x110043, 0x5b1 }, + { 0x110143, 0x5b1 }, + { 0x111043, 0x5b1 }, + { 0x111143, 0x5b1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x2005b, 0x7529 }, + { 0x2005c, 0x0 }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x200cc, 0x1f7 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x1200cc, 0x1f7 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2, 0x0}, + {0x1200b2, 0x0}, + {0x2200b2, 0x0}, + {0x0200cb, 0x0}, + {0x010043, 0x0}, + {0x110043, 0x0}, + {0x210043, 0x0}, + {0x010143, 0x0}, + {0x110143, 0x0}, + {0x210143, 0x0}, + {0x011043, 0x0}, + {0x111043, 0x0}, + {0x211043, 0x0}, + {0x011143, 0x0}, + {0x111143, 0x0}, + {0x211143, 0x0}, + {0x000080, 0x0}, + {0x100080, 0x0}, + {0x200080, 0x0}, + {0x001080, 0x0}, + {0x101080, 0x0}, + {0x201080, 0x0}, + {0x002080, 0x0}, + {0x102080, 0x0}, + {0x202080, 0x0}, + {0x003080, 0x0}, + {0x103080, 0x0}, + {0x203080, 0x0}, + {0x004080, 0x0}, + {0x104080, 0x0}, + {0x204080, 0x0}, + {0x005080, 0x0}, + {0x105080, 0x0}, + {0x205080, 0x0}, + {0x006080, 0x0}, + {0x106080, 0x0}, + {0x206080, 0x0}, + {0x007080, 0x0}, + {0x107080, 0x0}, + {0x207080, 0x0}, + {0x008080, 0x0}, + {0x108080, 0x0}, + {0x208080, 0x0}, + {0x009080, 0x0}, + {0x109080, 0x0}, + {0x209080, 0x0}, + {0x010080, 0x0}, + {0x110080, 0x0}, + {0x210080, 0x0}, + {0x010180, 0x0}, + {0x110180, 0x0}, + {0x210180, 0x0}, + {0x010081, 0x0}, + {0x110081, 0x0}, + {0x210081, 0x0}, + {0x010181, 0x0}, + {0x110181, 0x0}, + {0x210181, 0x0}, + {0x010082, 0x0}, + {0x110082, 0x0}, + {0x210082, 0x0}, + {0x010182, 0x0}, + {0x110182, 0x0}, + {0x210182, 0x0}, + {0x010083, 0x0}, + {0x110083, 0x0}, + {0x210083, 0x0}, + {0x010183, 0x0}, + {0x110183, 0x0}, + {0x210183, 0x0}, + {0x011080, 0x0}, + {0x111080, 0x0}, + {0x211080, 0x0}, + {0x011180, 0x0}, + {0x111180, 0x0}, + {0x211180, 0x0}, + {0x011081, 0x0}, + {0x111081, 0x0}, + {0x211081, 0x0}, + {0x011181, 0x0}, + {0x111181, 0x0}, + {0x211181, 0x0}, + {0x011082, 0x0}, + {0x111082, 0x0}, + {0x211082, 0x0}, + {0x011182, 0x0}, + {0x111182, 0x0}, + {0x211182, 0x0}, + {0x011083, 0x0}, + {0x111083, 0x0}, + {0x211083, 0x0}, + {0x011183, 0x0}, + {0x111183, 0x0}, + {0x211183, 0x0}, + {0x0100d0, 0x0}, + {0x1100d0, 0x0}, + {0x2100d0, 0x0}, + {0x0101d0, 0x0}, + {0x1101d0, 0x0}, + {0x2101d0, 0x0}, + {0x0100d1, 0x0}, + {0x1100d1, 0x0}, + {0x2100d1, 0x0}, + {0x0101d1, 0x0}, + {0x1101d1, 0x0}, + {0x2101d1, 0x0}, + {0x0100d2, 0x0}, + {0x1100d2, 0x0}, + {0x2100d2, 0x0}, + {0x0101d2, 0x0}, + {0x1101d2, 0x0}, + {0x2101d2, 0x0}, + {0x0100d3, 0x0}, + {0x1100d3, 0x0}, + {0x2100d3, 0x0}, + {0x0101d3, 0x0}, + {0x1101d3, 0x0}, + {0x2101d3, 0x0}, + {0x0110d0, 0x0}, + {0x1110d0, 0x0}, + {0x2110d0, 0x0}, + {0x0111d0, 0x0}, + {0x1111d0, 0x0}, + {0x2111d0, 0x0}, + {0x0110d1, 0x0}, + {0x1110d1, 0x0}, + {0x2110d1, 0x0}, + {0x0111d1, 0x0}, + {0x1111d1, 0x0}, + {0x2111d1, 0x0}, + {0x0110d2, 0x0}, + {0x1110d2, 0x0}, + {0x2110d2, 0x0}, + {0x0111d2, 0x0}, + {0x1111d2, 0x0}, + {0x2111d2, 0x0}, + {0x0110d3, 0x0}, + {0x1110d3, 0x0}, + {0x2110d3, 0x0}, + {0x0111d3, 0x0}, + {0x1111d3, 0x0}, + {0x2111d3, 0x0}, + {0x010068, 0x0}, + {0x010168, 0x0}, + {0x010268, 0x0}, + {0x010368, 0x0}, + {0x010468, 0x0}, + {0x010568, 0x0}, + {0x010668, 0x0}, + {0x010768, 0x0}, + {0x010868, 0x0}, + {0x010069, 0x0}, + {0x010169, 0x0}, + {0x010269, 0x0}, + {0x010369, 0x0}, + {0x010469, 0x0}, + {0x010569, 0x0}, + {0x010669, 0x0}, + {0x010769, 0x0}, + {0x010869, 0x0}, + {0x01006a, 0x0}, + {0x01016a, 0x0}, + {0x01026a, 0x0}, + {0x01036a, 0x0}, + {0x01046a, 0x0}, + {0x01056a, 0x0}, + {0x01066a, 0x0}, + {0x01076a, 0x0}, + {0x01086a, 0x0}, + {0x01006b, 0x0}, + {0x01016b, 0x0}, + {0x01026b, 0x0}, + {0x01036b, 0x0}, + {0x01046b, 0x0}, + {0x01056b, 0x0}, + {0x01066b, 0x0}, + {0x01076b, 0x0}, + {0x01086b, 0x0}, + {0x011068, 0x0}, + {0x011168, 0x0}, + {0x011268, 0x0}, + {0x011368, 0x0}, + {0x011468, 0x0}, + {0x011568, 0x0}, + {0x011668, 0x0}, + {0x011768, 0x0}, + {0x011868, 0x0}, + {0x011069, 0x0}, + {0x011169, 0x0}, + {0x011269, 0x0}, + {0x011369, 0x0}, + {0x011469, 0x0}, + {0x011569, 0x0}, + {0x011669, 0x0}, + {0x011769, 0x0}, + {0x011869, 0x0}, + {0x01106a, 0x0}, + {0x01116a, 0x0}, + {0x01126a, 0x0}, + {0x01136a, 0x0}, + {0x01146a, 0x0}, + {0x01156a, 0x0}, + {0x01166a, 0x0}, + {0x01176a, 0x0}, + {0x01186a, 0x0}, + {0x01106b, 0x0}, + {0x01116b, 0x0}, + {0x01126b, 0x0}, + {0x01136b, 0x0}, + {0x01146b, 0x0}, + {0x01156b, 0x0}, + {0x01166b, 0x0}, + {0x01176b, 0x0}, + {0x01186b, 0x0}, + {0x01008c, 0x0}, + {0x11008c, 0x0}, + {0x21008c, 0x0}, + {0x01018c, 0x0}, + {0x11018c, 0x0}, + {0x21018c, 0x0}, + {0x01008d, 0x0}, + {0x11008d, 0x0}, + {0x21008d, 0x0}, + {0x01018d, 0x0}, + {0x11018d, 0x0}, + {0x21018d, 0x0}, + {0x01008e, 0x0}, + {0x11008e, 0x0}, + {0x21008e, 0x0}, + {0x01018e, 0x0}, + {0x11018e, 0x0}, + {0x21018e, 0x0}, + {0x01008f, 0x0}, + {0x11008f, 0x0}, + {0x21008f, 0x0}, + {0x01018f, 0x0}, + {0x11018f, 0x0}, + {0x21018f, 0x0}, + {0x01108c, 0x0}, + {0x11108c, 0x0}, + {0x21108c, 0x0}, + {0x01118c, 0x0}, + {0x11118c, 0x0}, + {0x21118c, 0x0}, + {0x01108d, 0x0}, + {0x11108d, 0x0}, + {0x21108d, 0x0}, + {0x01118d, 0x0}, + {0x11118d, 0x0}, + {0x21118d, 0x0}, + {0x01108e, 0x0}, + {0x11108e, 0x0}, + {0x21108e, 0x0}, + {0x01118e, 0x0}, + {0x11118e, 0x0}, + {0x21118e, 0x0}, + {0x01108f, 0x0}, + {0x11108f, 0x0}, + {0x21108f, 0x0}, + {0x01118f, 0x0}, + {0x11118f, 0x0}, + {0x21118f, 0x0}, + {0x0100c0, 0x0}, + {0x1100c0, 0x0}, + {0x2100c0, 0x0}, + {0x0101c0, 0x0}, + {0x1101c0, 0x0}, + {0x2101c0, 0x0}, + {0x0102c0, 0x0}, + {0x1102c0, 0x0}, + {0x2102c0, 0x0}, + {0x0103c0, 0x0}, + {0x1103c0, 0x0}, + {0x2103c0, 0x0}, + {0x0104c0, 0x0}, + {0x1104c0, 0x0}, + {0x2104c0, 0x0}, + {0x0105c0, 0x0}, + {0x1105c0, 0x0}, + {0x2105c0, 0x0}, + {0x0106c0, 0x0}, + {0x1106c0, 0x0}, + {0x2106c0, 0x0}, + {0x0107c0, 0x0}, + {0x1107c0, 0x0}, + {0x2107c0, 0x0}, + {0x0108c0, 0x0}, + {0x1108c0, 0x0}, + {0x2108c0, 0x0}, + {0x0100c1, 0x0}, + {0x1100c1, 0x0}, + {0x2100c1, 0x0}, + {0x0101c1, 0x0}, + {0x1101c1, 0x0}, + {0x2101c1, 0x0}, + {0x0102c1, 0x0}, + {0x1102c1, 0x0}, + {0x2102c1, 0x0}, + {0x0103c1, 0x0}, + {0x1103c1, 0x0}, + {0x2103c1, 0x0}, + {0x0104c1, 0x0}, + {0x1104c1, 0x0}, + {0x2104c1, 0x0}, + {0x0105c1, 0x0}, + {0x1105c1, 0x0}, + {0x2105c1, 0x0}, + {0x0106c1, 0x0}, + {0x1106c1, 0x0}, + {0x2106c1, 0x0}, + {0x0107c1, 0x0}, + {0x1107c1, 0x0}, + {0x2107c1, 0x0}, + {0x0108c1, 0x0}, + {0x1108c1, 0x0}, + {0x2108c1, 0x0}, + {0x0100c2, 0x0}, + {0x1100c2, 0x0}, + {0x2100c2, 0x0}, + {0x0101c2, 0x0}, + {0x1101c2, 0x0}, + {0x2101c2, 0x0}, + {0x0102c2, 0x0}, + {0x1102c2, 0x0}, + {0x2102c2, 0x0}, + {0x0103c2, 0x0}, + {0x1103c2, 0x0}, + {0x2103c2, 0x0}, + {0x0104c2, 0x0}, + {0x1104c2, 0x0}, + {0x2104c2, 0x0}, + {0x0105c2, 0x0}, + {0x1105c2, 0x0}, + {0x2105c2, 0x0}, + {0x0106c2, 0x0}, + {0x1106c2, 0x0}, + {0x2106c2, 0x0}, + {0x0107c2, 0x0}, + {0x1107c2, 0x0}, + {0x2107c2, 0x0}, + {0x0108c2, 0x0}, + {0x1108c2, 0x0}, + {0x2108c2, 0x0}, + {0x0100c3, 0x0}, + {0x1100c3, 0x0}, + {0x2100c3, 0x0}, + {0x0101c3, 0x0}, + {0x1101c3, 0x0}, + {0x2101c3, 0x0}, + {0x0102c3, 0x0}, + {0x1102c3, 0x0}, + {0x2102c3, 0x0}, + {0x0103c3, 0x0}, + {0x1103c3, 0x0}, + {0x2103c3, 0x0}, + {0x0104c3, 0x0}, + {0x1104c3, 0x0}, + {0x2104c3, 0x0}, + {0x0105c3, 0x0}, + {0x1105c3, 0x0}, + {0x2105c3, 0x0}, + {0x0106c3, 0x0}, + {0x1106c3, 0x0}, + {0x2106c3, 0x0}, + {0x0107c3, 0x0}, + {0x1107c3, 0x0}, + {0x2107c3, 0x0}, + {0x0108c3, 0x0}, + {0x1108c3, 0x0}, + {0x2108c3, 0x0}, + {0x0110c0, 0x0}, + {0x1110c0, 0x0}, + {0x2110c0, 0x0}, + {0x0111c0, 0x0}, + {0x1111c0, 0x0}, + {0x2111c0, 0x0}, + {0x0112c0, 0x0}, + {0x1112c0, 0x0}, + {0x2112c0, 0x0}, + {0x0113c0, 0x0}, + {0x1113c0, 0x0}, + {0x2113c0, 0x0}, + {0x0114c0, 0x0}, + {0x1114c0, 0x0}, + {0x2114c0, 0x0}, + {0x0115c0, 0x0}, + {0x1115c0, 0x0}, + {0x2115c0, 0x0}, + {0x0116c0, 0x0}, + {0x1116c0, 0x0}, + {0x2116c0, 0x0}, + {0x0117c0, 0x0}, + {0x1117c0, 0x0}, + {0x2117c0, 0x0}, + {0x0118c0, 0x0}, + {0x1118c0, 0x0}, + {0x2118c0, 0x0}, + {0x0110c1, 0x0}, + {0x1110c1, 0x0}, + {0x2110c1, 0x0}, + {0x0111c1, 0x0}, + {0x1111c1, 0x0}, + {0x2111c1, 0x0}, + {0x0112c1, 0x0}, + {0x1112c1, 0x0}, + {0x2112c1, 0x0}, + {0x0113c1, 0x0}, + {0x1113c1, 0x0}, + {0x2113c1, 0x0}, + {0x0114c1, 0x0}, + {0x1114c1, 0x0}, + {0x2114c1, 0x0}, + {0x0115c1, 0x0}, + {0x1115c1, 0x0}, + {0x2115c1, 0x0}, + {0x0116c1, 0x0}, + {0x1116c1, 0x0}, + {0x2116c1, 0x0}, + {0x0117c1, 0x0}, + {0x1117c1, 0x0}, + {0x2117c1, 0x0}, + {0x0118c1, 0x0}, + {0x1118c1, 0x0}, + {0x2118c1, 0x0}, + {0x0110c2, 0x0}, + {0x1110c2, 0x0}, + {0x2110c2, 0x0}, + {0x0111c2, 0x0}, + {0x1111c2, 0x0}, + {0x2111c2, 0x0}, + {0x0112c2, 0x0}, + {0x1112c2, 0x0}, + {0x2112c2, 0x0}, + {0x0113c2, 0x0}, + {0x1113c2, 0x0}, + {0x2113c2, 0x0}, + {0x0114c2, 0x0}, + {0x1114c2, 0x0}, + {0x2114c2, 0x0}, + {0x0115c2, 0x0}, + {0x1115c2, 0x0}, + {0x2115c2, 0x0}, + {0x0116c2, 0x0}, + {0x1116c2, 0x0}, + {0x2116c2, 0x0}, + {0x0117c2, 0x0}, + {0x1117c2, 0x0}, + {0x2117c2, 0x0}, + {0x0118c2, 0x0}, + {0x1118c2, 0x0}, + {0x2118c2, 0x0}, + {0x0110c3, 0x0}, + {0x1110c3, 0x0}, + {0x2110c3, 0x0}, + {0x0111c3, 0x0}, + {0x1111c3, 0x0}, + {0x2111c3, 0x0}, + {0x0112c3, 0x0}, + {0x1112c3, 0x0}, + {0x2112c3, 0x0}, + {0x0113c3, 0x0}, + {0x1113c3, 0x0}, + {0x2113c3, 0x0}, + {0x0114c3, 0x0}, + {0x1114c3, 0x0}, + {0x2114c3, 0x0}, + {0x0115c3, 0x0}, + {0x1115c3, 0x0}, + {0x2115c3, 0x0}, + {0x0116c3, 0x0}, + {0x1116c3, 0x0}, + {0x2116c3, 0x0}, + {0x0117c3, 0x0}, + {0x1117c3, 0x0}, + {0x2117c3, 0x0}, + {0x0118c3, 0x0}, + {0x1118c3, 0x0}, + {0x2118c3, 0x0}, + {0x010020, 0x0}, + {0x110020, 0x0}, + {0x210020, 0x0}, + {0x011020, 0x0}, + {0x111020, 0x0}, + {0x211020, 0x0}, + {0x02007d, 0x0}, + {0x12007d, 0x0}, + {0x22007d, 0x0}, + {0x010040, 0x0}, + {0x010140, 0x0}, + {0x010240, 0x0}, + {0x010340, 0x0}, + {0x010440, 0x0}, + {0x010540, 0x0}, + {0x010640, 0x0}, + {0x010740, 0x0}, + {0x010840, 0x0}, + {0x010030, 0x0}, + {0x010130, 0x0}, + {0x010230, 0x0}, + {0x010330, 0x0}, + {0x010430, 0x0}, + {0x010530, 0x0}, + {0x010630, 0x0}, + {0x010730, 0x0}, + {0x010830, 0x0}, + {0x011040, 0x0}, + {0x011140, 0x0}, + {0x011240, 0x0}, + {0x011340, 0x0}, + {0x011440, 0x0}, + {0x011540, 0x0}, + {0x011640, 0x0}, + {0x011740, 0x0}, + {0x011840, 0x0}, + {0x011030, 0x0}, + {0x011130, 0x0}, + {0x011230, 0x0}, + {0x011330, 0x0}, + {0x011430, 0x0}, + {0x011530, 0x0}, + {0x011630, 0x0}, + {0x011730, 0x0}, + {0x011830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x105 }, + { 0x54031, 0x18 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x810 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x42a }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x10 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x61 }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x5400e, 0x1f7f }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x105 }, + { 0x54031, 0x18 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x810 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x2 }, + { 0x90033, 0x10 }, + { 0x90034, 0x139 }, + { 0x90035, 0xb }, + { 0x90036, 0x7c0 }, + { 0x90037, 0x139 }, + { 0x90038, 0x44 }, + { 0x90039, 0x633 }, + { 0x9003a, 0x159 }, + { 0x9003b, 0x14f }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x47 }, + { 0x9003f, 0x633 }, + { 0x90040, 0x149 }, + { 0x90041, 0x4f }, + { 0x90042, 0x633 }, + { 0x90043, 0x179 }, + { 0x90044, 0x8 }, + { 0x90045, 0xe0 }, + { 0x90046, 0x109 }, + { 0x90047, 0x0 }, + { 0x90048, 0x7c8 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x1 }, + { 0x9004c, 0x8 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x45a }, + { 0x9004f, 0x9 }, + { 0x90050, 0x0 }, + { 0x90051, 0x448 }, + { 0x90052, 0x109 }, + { 0x90053, 0x40 }, + { 0x90054, 0x633 }, + { 0x90055, 0x179 }, + { 0x90056, 0x1 }, + { 0x90057, 0x618 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40c0 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x149 }, + { 0x9005c, 0x8 }, + { 0x9005d, 0x4 }, + { 0x9005e, 0x48 }, + { 0x9005f, 0x4040 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x0 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x40 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x10 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x18 }, + { 0x9006b, 0x0 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x78 }, + { 0x9006e, 0x549 }, + { 0x9006f, 0x633 }, + { 0x90070, 0x159 }, + { 0x90071, 0xd49 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0x94a }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x441 }, + { 0x90078, 0x633 }, + { 0x90079, 0x149 }, + { 0x9007a, 0x42 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x1 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x0 }, + { 0x90081, 0xe0 }, + { 0x90082, 0x109 }, + { 0x90083, 0xa }, + { 0x90084, 0x10 }, + { 0x90085, 0x109 }, + { 0x90086, 0x9 }, + { 0x90087, 0x3c0 }, + { 0x90088, 0x149 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x159 }, + { 0x9008c, 0x18 }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x0 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x109 }, + { 0x90092, 0x18 }, + { 0x90093, 0x4 }, + { 0x90094, 0x48 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x58 }, + { 0x90098, 0xb }, + { 0x90099, 0x10 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x1 }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x5 }, + { 0x9009f, 0x7c0 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x0 }, + { 0x900a2, 0x8140 }, + { 0x900a3, 0x10c }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x8138 }, + { 0x900a6, 0x10c }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7c8 }, + { 0x900a9, 0x101 }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x448 }, + { 0x900ac, 0x109 }, + { 0x900ad, 0xf }, + { 0x900ae, 0x7c0 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x47 }, + { 0x900b1, 0x630 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x8 }, + { 0x900b4, 0x618 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0xe0 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x0 }, + { 0x900ba, 0x7c8 }, + { 0x900bb, 0x109 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x8140 }, + { 0x900be, 0x10c }, + { 0x900bf, 0x0 }, + { 0x900c0, 0x1 }, + { 0x900c1, 0x8 }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x8 }, + { 0x900c5, 0x8 }, + { 0x900c6, 0x7c8 }, + { 0x900c7, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x90026, 0x2b }, + { 0x2000b, 0x4b }, + { 0x2000c, 0x96 }, + { 0x2000d, 0x5dc }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x21 }, + { 0x12000c, 0x42 }, + { 0x12000d, 0x29a }, + { 0x12000e, 0x21 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0xffff }, + { 0x90013, 0x6152 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1066mts 1D */ + .drate = 1066, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1066, }, +}; diff --git a/board/nxp/imx8mn_evk/ddr4_timing_ld.c b/board/nxp/imx8mn_evk/ddr4_timing_ld.c new file mode 100644 index 00000000000..d719b5916f5 --- /dev/null +++ b/board/nxp/imx8mn_evk/ddr4_timing_ld.c @@ -0,0 +1,1054 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400000, 0x81040010 }, + { 0x3d400030, 0x20 }, + { 0x3d400034, 0x221306 }, + { 0x3d400050, 0x210070 }, + { 0x3d400054, 0x10008 }, + { 0x3d400060, 0x0 }, + { 0x3d400064, 0x6100dc }, + { 0x3d4000c0, 0x0 }, + { 0x3d4000c4, 0x1000 }, + { 0x3d4000d0, 0xc00200c5 }, + { 0x3d4000d4, 0x500000 }, + { 0x3d4000dc, 0x2340105 }, + { 0x3d4000e0, 0x0 }, + { 0x3d4000e4, 0x110000 }, + { 0x3d4000e8, 0x2000600 }, + { 0x3d4000ec, 0x410 }, + { 0x3d4000f0, 0x20 }, + { 0x3d4000f4, 0xec7 }, + { 0x3d400100, 0xd0c1b0d }, + { 0x3d400104, 0x30313 }, + { 0x3d400108, 0x508060a }, + { 0x3d40010c, 0x400c }, + { 0x3d400110, 0x6030306 }, + { 0x3d400114, 0x4040302 }, + { 0x3d40011c, 0x404 }, + { 0x3d400120, 0x5050d08 }, + { 0x3d400124, 0x20308 }, + { 0x3d40012c, 0x1406010e }, + { 0x3d400130, 0x8 }, + { 0x3d40013c, 0x0 }, + { 0x3d400180, 0x1000040 }, + { 0x3d400184, 0x30d4 }, + { 0x3d400190, 0x38b8204 }, + { 0x3d400194, 0x2020303 }, + { 0x3d400198, 0x7f04011 }, + { 0x3d40019c, 0xb0 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0x48005a }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x1 }, + { 0x3d4001b4, 0xb04 }, + { 0x3d4001b8, 0x4 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d400200, 0x3f1f }, + { 0x3d400204, 0x3f0909 }, + { 0x3d400208, 0x700 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf07 }, + { 0x3d400220, 0x3f01 }, + { 0x3d400240, 0x600061c }, + { 0x3d400244, 0x1323 }, + { 0x3d400400, 0x100 }, + { 0x3d400250, 0x317d1a07 }, + { 0x3d400254, 0xf }, + { 0x3d40025c, 0x2a001b76 }, + { 0x3d400264, 0x7300b473 }, + { 0x3d40026c, 0x30000e06 }, + { 0x3d400300, 0x14 }, + { 0x3d40036c, 0x10 }, + { 0x3d400404, 0x13193 }, + { 0x3d400408, 0x6096 }, + { 0x3d400490, 0x1 }, + { 0x3d400494, 0x2000c00 }, + { 0x3d400498, 0x3c00db }, + { 0x3d40049c, 0x100009 }, + { 0x3d4004a0, 0x2 }, + { 0x3d402050, 0x210070 }, + { 0x3d402064, 0x400093 }, + { 0x3d4020dc, 0x40105 }, + { 0x3d4020e0, 0x0 }, + { 0x3d4020e8, 0x2000600 }, + { 0x3d4020ec, 0x10 }, + { 0x3d402100, 0xb081209 }, + { 0x3d402104, 0x2020d }, + { 0x3d402108, 0x5050309 }, + { 0x3d40210c, 0x400c }, + { 0x3d402110, 0x5030206 }, + { 0x3d402114, 0x3030202 }, + { 0x3d40211c, 0x303 }, + { 0x3d402120, 0x4040d06 }, + { 0x3d402124, 0x20208 }, + { 0x3d40212c, 0x1205010e }, + { 0x3d402130, 0x8 }, + { 0x3d40213c, 0x0 }, + { 0x3d402180, 0x1000040 }, + { 0x3d402190, 0x3858204 }, + { 0x3d402194, 0x2020303 }, + { 0x3d4021b4, 0x504 }, + { 0x3d4021b8, 0x4 }, + { 0x3d402240, 0x6000604 }, + { 0x3d4020f4, 0xec7 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x1005f, 0x2fd }, + { 0x1015f, 0x2fd }, + { 0x1105f, 0x2fd }, + { 0x1115f, 0x2fd }, + { 0x11005f, 0x2fd }, + { 0x11015f, 0x2fd }, + { 0x11105f, 0x2fd }, + { 0x11115f, 0x2fd }, + { 0x55, 0x355 }, + { 0x1055, 0x355 }, + { 0x2055, 0x355 }, + { 0x3055, 0x355 }, + { 0x4055, 0x55 }, + { 0x5055, 0x55 }, + { 0x6055, 0x355 }, + { 0x7055, 0x355 }, + { 0x8055, 0x355 }, + { 0x9055, 0x355 }, + { 0x200c5, 0xb }, + { 0x1200c5, 0x6 }, + { 0x2002e, 0x1 }, + { 0x12002e, 0x1 }, + { 0x20024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x20056, 0xa }, + { 0x120056, 0xa }, + { 0x1004d, 0x1a }, + { 0x1014d, 0x1a }, + { 0x1104d, 0x1a }, + { 0x1114d, 0x1a }, + { 0x11004d, 0x1a }, + { 0x11014d, 0x1a }, + { 0x11104d, 0x1a }, + { 0x11114d, 0x1a }, + { 0x10049, 0xe38 }, + { 0x10149, 0xe38 }, + { 0x11049, 0xe38 }, + { 0x11149, 0xe38 }, + { 0x110049, 0xe38 }, + { 0x110149, 0xe38 }, + { 0x111049, 0xe38 }, + { 0x111149, 0xe38 }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x1 }, + { 0x20075, 0x2 }, + { 0x20050, 0x0 }, + { 0x20008, 0x190 }, + { 0x120008, 0x10a }, + { 0x20088, 0x9 }, + { 0x200b2, 0x268 }, + { 0x10043, 0x5b1 }, + { 0x10143, 0x5b1 }, + { 0x11043, 0x5b1 }, + { 0x11143, 0x5b1 }, + { 0x1200b2, 0x268 }, + { 0x110043, 0x5b1 }, + { 0x110143, 0x5b1 }, + { 0x111043, 0x5b1 }, + { 0x111143, 0x5b1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x2005b, 0x7529 }, + { 0x2005c, 0x0 }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x200cc, 0x1f7 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x1200cc, 0x1f7 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2, 0x0}, + {0x1200b2, 0x0}, + {0x2200b2, 0x0}, + {0x0200cb, 0x0}, + {0x010043, 0x0}, + {0x110043, 0x0}, + {0x210043, 0x0}, + {0x010143, 0x0}, + {0x110143, 0x0}, + {0x210143, 0x0}, + {0x011043, 0x0}, + {0x111043, 0x0}, + {0x211043, 0x0}, + {0x011143, 0x0}, + {0x111143, 0x0}, + {0x211143, 0x0}, + {0x000080, 0x0}, + {0x100080, 0x0}, + {0x200080, 0x0}, + {0x001080, 0x0}, + {0x101080, 0x0}, + {0x201080, 0x0}, + {0x002080, 0x0}, + {0x102080, 0x0}, + {0x202080, 0x0}, + {0x003080, 0x0}, + {0x103080, 0x0}, + {0x203080, 0x0}, + {0x004080, 0x0}, + {0x104080, 0x0}, + {0x204080, 0x0}, + {0x005080, 0x0}, + {0x105080, 0x0}, + {0x205080, 0x0}, + {0x006080, 0x0}, + {0x106080, 0x0}, + {0x206080, 0x0}, + {0x007080, 0x0}, + {0x107080, 0x0}, + {0x207080, 0x0}, + {0x008080, 0x0}, + {0x108080, 0x0}, + {0x208080, 0x0}, + {0x009080, 0x0}, + {0x109080, 0x0}, + {0x209080, 0x0}, + {0x010080, 0x0}, + {0x110080, 0x0}, + {0x210080, 0x0}, + {0x010180, 0x0}, + {0x110180, 0x0}, + {0x210180, 0x0}, + {0x010081, 0x0}, + {0x110081, 0x0}, + {0x210081, 0x0}, + {0x010181, 0x0}, + {0x110181, 0x0}, + {0x210181, 0x0}, + {0x010082, 0x0}, + {0x110082, 0x0}, + {0x210082, 0x0}, + {0x010182, 0x0}, + {0x110182, 0x0}, + {0x210182, 0x0}, + {0x010083, 0x0}, + {0x110083, 0x0}, + {0x210083, 0x0}, + {0x010183, 0x0}, + {0x110183, 0x0}, + {0x210183, 0x0}, + {0x011080, 0x0}, + {0x111080, 0x0}, + {0x211080, 0x0}, + {0x011180, 0x0}, + {0x111180, 0x0}, + {0x211180, 0x0}, + {0x011081, 0x0}, + {0x111081, 0x0}, + {0x211081, 0x0}, + {0x011181, 0x0}, + {0x111181, 0x0}, + {0x211181, 0x0}, + {0x011082, 0x0}, + {0x111082, 0x0}, + {0x211082, 0x0}, + {0x011182, 0x0}, + {0x111182, 0x0}, + {0x211182, 0x0}, + {0x011083, 0x0}, + {0x111083, 0x0}, + {0x211083, 0x0}, + {0x011183, 0x0}, + {0x111183, 0x0}, + {0x211183, 0x0}, + {0x0100d0, 0x0}, + {0x1100d0, 0x0}, + {0x2100d0, 0x0}, + {0x0101d0, 0x0}, + {0x1101d0, 0x0}, + {0x2101d0, 0x0}, + {0x0100d1, 0x0}, + {0x1100d1, 0x0}, + {0x2100d1, 0x0}, + {0x0101d1, 0x0}, + {0x1101d1, 0x0}, + {0x2101d1, 0x0}, + {0x0100d2, 0x0}, + {0x1100d2, 0x0}, + {0x2100d2, 0x0}, + {0x0101d2, 0x0}, + {0x1101d2, 0x0}, + {0x2101d2, 0x0}, + {0x0100d3, 0x0}, + {0x1100d3, 0x0}, + {0x2100d3, 0x0}, + {0x0101d3, 0x0}, + {0x1101d3, 0x0}, + {0x2101d3, 0x0}, + {0x0110d0, 0x0}, + {0x1110d0, 0x0}, + {0x2110d0, 0x0}, + {0x0111d0, 0x0}, + {0x1111d0, 0x0}, + {0x2111d0, 0x0}, + {0x0110d1, 0x0}, + {0x1110d1, 0x0}, + {0x2110d1, 0x0}, + {0x0111d1, 0x0}, + {0x1111d1, 0x0}, + {0x2111d1, 0x0}, + {0x0110d2, 0x0}, + {0x1110d2, 0x0}, + {0x2110d2, 0x0}, + {0x0111d2, 0x0}, + {0x1111d2, 0x0}, + {0x2111d2, 0x0}, + {0x0110d3, 0x0}, + {0x1110d3, 0x0}, + {0x2110d3, 0x0}, + {0x0111d3, 0x0}, + {0x1111d3, 0x0}, + {0x2111d3, 0x0}, + {0x010068, 0x0}, + {0x010168, 0x0}, + {0x010268, 0x0}, + {0x010368, 0x0}, + {0x010468, 0x0}, + {0x010568, 0x0}, + {0x010668, 0x0}, + {0x010768, 0x0}, + {0x010868, 0x0}, + {0x010069, 0x0}, + {0x010169, 0x0}, + {0x010269, 0x0}, + {0x010369, 0x0}, + {0x010469, 0x0}, + {0x010569, 0x0}, + {0x010669, 0x0}, + {0x010769, 0x0}, + {0x010869, 0x0}, + {0x01006a, 0x0}, + {0x01016a, 0x0}, + {0x01026a, 0x0}, + {0x01036a, 0x0}, + {0x01046a, 0x0}, + {0x01056a, 0x0}, + {0x01066a, 0x0}, + {0x01076a, 0x0}, + {0x01086a, 0x0}, + {0x01006b, 0x0}, + {0x01016b, 0x0}, + {0x01026b, 0x0}, + {0x01036b, 0x0}, + {0x01046b, 0x0}, + {0x01056b, 0x0}, + {0x01066b, 0x0}, + {0x01076b, 0x0}, + {0x01086b, 0x0}, + {0x011068, 0x0}, + {0x011168, 0x0}, + {0x011268, 0x0}, + {0x011368, 0x0}, + {0x011468, 0x0}, + {0x011568, 0x0}, + {0x011668, 0x0}, + {0x011768, 0x0}, + {0x011868, 0x0}, + {0x011069, 0x0}, + {0x011169, 0x0}, + {0x011269, 0x0}, + {0x011369, 0x0}, + {0x011469, 0x0}, + {0x011569, 0x0}, + {0x011669, 0x0}, + {0x011769, 0x0}, + {0x011869, 0x0}, + {0x01106a, 0x0}, + {0x01116a, 0x0}, + {0x01126a, 0x0}, + {0x01136a, 0x0}, + {0x01146a, 0x0}, + {0x01156a, 0x0}, + {0x01166a, 0x0}, + {0x01176a, 0x0}, + {0x01186a, 0x0}, + {0x01106b, 0x0}, + {0x01116b, 0x0}, + {0x01126b, 0x0}, + {0x01136b, 0x0}, + {0x01146b, 0x0}, + {0x01156b, 0x0}, + {0x01166b, 0x0}, + {0x01176b, 0x0}, + {0x01186b, 0x0}, + {0x01008c, 0x0}, + {0x11008c, 0x0}, + {0x21008c, 0x0}, + {0x01018c, 0x0}, + {0x11018c, 0x0}, + {0x21018c, 0x0}, + {0x01008d, 0x0}, + {0x11008d, 0x0}, + {0x21008d, 0x0}, + {0x01018d, 0x0}, + {0x11018d, 0x0}, + {0x21018d, 0x0}, + {0x01008e, 0x0}, + {0x11008e, 0x0}, + {0x21008e, 0x0}, + {0x01018e, 0x0}, + {0x11018e, 0x0}, + {0x21018e, 0x0}, + {0x01008f, 0x0}, + {0x11008f, 0x0}, + {0x21008f, 0x0}, + {0x01018f, 0x0}, + {0x11018f, 0x0}, + {0x21018f, 0x0}, + {0x01108c, 0x0}, + {0x11108c, 0x0}, + {0x21108c, 0x0}, + {0x01118c, 0x0}, + {0x11118c, 0x0}, + {0x21118c, 0x0}, + {0x01108d, 0x0}, + {0x11108d, 0x0}, + {0x21108d, 0x0}, + {0x01118d, 0x0}, + {0x11118d, 0x0}, + {0x21118d, 0x0}, + {0x01108e, 0x0}, + {0x11108e, 0x0}, + {0x21108e, 0x0}, + {0x01118e, 0x0}, + {0x11118e, 0x0}, + {0x21118e, 0x0}, + {0x01108f, 0x0}, + {0x11108f, 0x0}, + {0x21108f, 0x0}, + {0x01118f, 0x0}, + {0x11118f, 0x0}, + {0x21118f, 0x0}, + {0x0100c0, 0x0}, + {0x1100c0, 0x0}, + {0x2100c0, 0x0}, + {0x0101c0, 0x0}, + {0x1101c0, 0x0}, + {0x2101c0, 0x0}, + {0x0102c0, 0x0}, + {0x1102c0, 0x0}, + {0x2102c0, 0x0}, + {0x0103c0, 0x0}, + {0x1103c0, 0x0}, + {0x2103c0, 0x0}, + {0x0104c0, 0x0}, + {0x1104c0, 0x0}, + {0x2104c0, 0x0}, + {0x0105c0, 0x0}, + {0x1105c0, 0x0}, + {0x2105c0, 0x0}, + {0x0106c0, 0x0}, + {0x1106c0, 0x0}, + {0x2106c0, 0x0}, + {0x0107c0, 0x0}, + {0x1107c0, 0x0}, + {0x2107c0, 0x0}, + {0x0108c0, 0x0}, + {0x1108c0, 0x0}, + {0x2108c0, 0x0}, + {0x0100c1, 0x0}, + {0x1100c1, 0x0}, + {0x2100c1, 0x0}, + {0x0101c1, 0x0}, + {0x1101c1, 0x0}, + {0x2101c1, 0x0}, + {0x0102c1, 0x0}, + {0x1102c1, 0x0}, + {0x2102c1, 0x0}, + {0x0103c1, 0x0}, + {0x1103c1, 0x0}, + {0x2103c1, 0x0}, + {0x0104c1, 0x0}, + {0x1104c1, 0x0}, + {0x2104c1, 0x0}, + {0x0105c1, 0x0}, + {0x1105c1, 0x0}, + {0x2105c1, 0x0}, + {0x0106c1, 0x0}, + {0x1106c1, 0x0}, + {0x2106c1, 0x0}, + {0x0107c1, 0x0}, + {0x1107c1, 0x0}, + {0x2107c1, 0x0}, + {0x0108c1, 0x0}, + {0x1108c1, 0x0}, + {0x2108c1, 0x0}, + {0x0100c2, 0x0}, + {0x1100c2, 0x0}, + {0x2100c2, 0x0}, + {0x0101c2, 0x0}, + {0x1101c2, 0x0}, + {0x2101c2, 0x0}, + {0x0102c2, 0x0}, + {0x1102c2, 0x0}, + {0x2102c2, 0x0}, + {0x0103c2, 0x0}, + {0x1103c2, 0x0}, + {0x2103c2, 0x0}, + {0x0104c2, 0x0}, + {0x1104c2, 0x0}, + {0x2104c2, 0x0}, + {0x0105c2, 0x0}, + {0x1105c2, 0x0}, + {0x2105c2, 0x0}, + {0x0106c2, 0x0}, + {0x1106c2, 0x0}, + {0x2106c2, 0x0}, + {0x0107c2, 0x0}, + {0x1107c2, 0x0}, + {0x2107c2, 0x0}, + {0x0108c2, 0x0}, + {0x1108c2, 0x0}, + {0x2108c2, 0x0}, + {0x0100c3, 0x0}, + {0x1100c3, 0x0}, + {0x2100c3, 0x0}, + {0x0101c3, 0x0}, + {0x1101c3, 0x0}, + {0x2101c3, 0x0}, + {0x0102c3, 0x0}, + {0x1102c3, 0x0}, + {0x2102c3, 0x0}, + {0x0103c3, 0x0}, + {0x1103c3, 0x0}, + {0x2103c3, 0x0}, + {0x0104c3, 0x0}, + {0x1104c3, 0x0}, + {0x2104c3, 0x0}, + {0x0105c3, 0x0}, + {0x1105c3, 0x0}, + {0x2105c3, 0x0}, + {0x0106c3, 0x0}, + {0x1106c3, 0x0}, + {0x2106c3, 0x0}, + {0x0107c3, 0x0}, + {0x1107c3, 0x0}, + {0x2107c3, 0x0}, + {0x0108c3, 0x0}, + {0x1108c3, 0x0}, + {0x2108c3, 0x0}, + {0x0110c0, 0x0}, + {0x1110c0, 0x0}, + {0x2110c0, 0x0}, + {0x0111c0, 0x0}, + {0x1111c0, 0x0}, + {0x2111c0, 0x0}, + {0x0112c0, 0x0}, + {0x1112c0, 0x0}, + {0x2112c0, 0x0}, + {0x0113c0, 0x0}, + {0x1113c0, 0x0}, + {0x2113c0, 0x0}, + {0x0114c0, 0x0}, + {0x1114c0, 0x0}, + {0x2114c0, 0x0}, + {0x0115c0, 0x0}, + {0x1115c0, 0x0}, + {0x2115c0, 0x0}, + {0x0116c0, 0x0}, + {0x1116c0, 0x0}, + {0x2116c0, 0x0}, + {0x0117c0, 0x0}, + {0x1117c0, 0x0}, + {0x2117c0, 0x0}, + {0x0118c0, 0x0}, + {0x1118c0, 0x0}, + {0x2118c0, 0x0}, + {0x0110c1, 0x0}, + {0x1110c1, 0x0}, + {0x2110c1, 0x0}, + {0x0111c1, 0x0}, + {0x1111c1, 0x0}, + {0x2111c1, 0x0}, + {0x0112c1, 0x0}, + {0x1112c1, 0x0}, + {0x2112c1, 0x0}, + {0x0113c1, 0x0}, + {0x1113c1, 0x0}, + {0x2113c1, 0x0}, + {0x0114c1, 0x0}, + {0x1114c1, 0x0}, + {0x2114c1, 0x0}, + {0x0115c1, 0x0}, + {0x1115c1, 0x0}, + {0x2115c1, 0x0}, + {0x0116c1, 0x0}, + {0x1116c1, 0x0}, + {0x2116c1, 0x0}, + {0x0117c1, 0x0}, + {0x1117c1, 0x0}, + {0x2117c1, 0x0}, + {0x0118c1, 0x0}, + {0x1118c1, 0x0}, + {0x2118c1, 0x0}, + {0x0110c2, 0x0}, + {0x1110c2, 0x0}, + {0x2110c2, 0x0}, + {0x0111c2, 0x0}, + {0x1111c2, 0x0}, + {0x2111c2, 0x0}, + {0x0112c2, 0x0}, + {0x1112c2, 0x0}, + {0x2112c2, 0x0}, + {0x0113c2, 0x0}, + {0x1113c2, 0x0}, + {0x2113c2, 0x0}, + {0x0114c2, 0x0}, + {0x1114c2, 0x0}, + {0x2114c2, 0x0}, + {0x0115c2, 0x0}, + {0x1115c2, 0x0}, + {0x2115c2, 0x0}, + {0x0116c2, 0x0}, + {0x1116c2, 0x0}, + {0x2116c2, 0x0}, + {0x0117c2, 0x0}, + {0x1117c2, 0x0}, + {0x2117c2, 0x0}, + {0x0118c2, 0x0}, + {0x1118c2, 0x0}, + {0x2118c2, 0x0}, + {0x0110c3, 0x0}, + {0x1110c3, 0x0}, + {0x2110c3, 0x0}, + {0x0111c3, 0x0}, + {0x1111c3, 0x0}, + {0x2111c3, 0x0}, + {0x0112c3, 0x0}, + {0x1112c3, 0x0}, + {0x2112c3, 0x0}, + {0x0113c3, 0x0}, + {0x1113c3, 0x0}, + {0x2113c3, 0x0}, + {0x0114c3, 0x0}, + {0x1114c3, 0x0}, + {0x2114c3, 0x0}, + {0x0115c3, 0x0}, + {0x1115c3, 0x0}, + {0x2115c3, 0x0}, + {0x0116c3, 0x0}, + {0x1116c3, 0x0}, + {0x2116c3, 0x0}, + {0x0117c3, 0x0}, + {0x1117c3, 0x0}, + {0x2117c3, 0x0}, + {0x0118c3, 0x0}, + {0x1118c3, 0x0}, + {0x2118c3, 0x0}, + {0x010020, 0x0}, + {0x110020, 0x0}, + {0x210020, 0x0}, + {0x011020, 0x0}, + {0x111020, 0x0}, + {0x211020, 0x0}, + {0x02007d, 0x0}, + {0x12007d, 0x0}, + {0x22007d, 0x0}, + {0x010040, 0x0}, + {0x010140, 0x0}, + {0x010240, 0x0}, + {0x010340, 0x0}, + {0x010440, 0x0}, + {0x010540, 0x0}, + {0x010640, 0x0}, + {0x010740, 0x0}, + {0x010840, 0x0}, + {0x010030, 0x0}, + {0x010130, 0x0}, + {0x010230, 0x0}, + {0x010330, 0x0}, + {0x010430, 0x0}, + {0x010530, 0x0}, + {0x010630, 0x0}, + {0x010730, 0x0}, + {0x010830, 0x0}, + {0x011040, 0x0}, + {0x011140, 0x0}, + {0x011240, 0x0}, + {0x011340, 0x0}, + {0x011440, 0x0}, + {0x011540, 0x0}, + {0x011640, 0x0}, + {0x011740, 0x0}, + {0x011840, 0x0}, + {0x011030, 0x0}, + {0x011130, 0x0}, + {0x011230, 0x0}, + {0x011330, 0x0}, + {0x011430, 0x0}, + {0x011530, 0x0}, + {0x011630, 0x0}, + {0x011730, 0x0}, + {0x011830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x234 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x410 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x42a }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x4 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x10 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x61 }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x5400e, 0x1f7f }, + { 0x54012, 0x1 }, + { 0x5402f, 0x234 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x410 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x2 }, + { 0x90033, 0x10 }, + { 0x90034, 0x139 }, + { 0x90035, 0xb }, + { 0x90036, 0x7c0 }, + { 0x90037, 0x139 }, + { 0x90038, 0x44 }, + { 0x90039, 0x633 }, + { 0x9003a, 0x159 }, + { 0x9003b, 0x14f }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x47 }, + { 0x9003f, 0x633 }, + { 0x90040, 0x149 }, + { 0x90041, 0x4f }, + { 0x90042, 0x633 }, + { 0x90043, 0x179 }, + { 0x90044, 0x8 }, + { 0x90045, 0xe0 }, + { 0x90046, 0x109 }, + { 0x90047, 0x0 }, + { 0x90048, 0x7c8 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x1 }, + { 0x9004c, 0x8 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x45a }, + { 0x9004f, 0x9 }, + { 0x90050, 0x0 }, + { 0x90051, 0x448 }, + { 0x90052, 0x109 }, + { 0x90053, 0x40 }, + { 0x90054, 0x633 }, + { 0x90055, 0x179 }, + { 0x90056, 0x1 }, + { 0x90057, 0x618 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40c0 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x149 }, + { 0x9005c, 0x8 }, + { 0x9005d, 0x4 }, + { 0x9005e, 0x48 }, + { 0x9005f, 0x4040 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x0 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x40 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x10 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x18 }, + { 0x9006b, 0x0 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x78 }, + { 0x9006e, 0x549 }, + { 0x9006f, 0x633 }, + { 0x90070, 0x159 }, + { 0x90071, 0xd49 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0x94a }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x441 }, + { 0x90078, 0x633 }, + { 0x90079, 0x149 }, + { 0x9007a, 0x42 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x1 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x0 }, + { 0x90081, 0xe0 }, + { 0x90082, 0x109 }, + { 0x90083, 0xa }, + { 0x90084, 0x10 }, + { 0x90085, 0x109 }, + { 0x90086, 0x9 }, + { 0x90087, 0x3c0 }, + { 0x90088, 0x149 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x159 }, + { 0x9008c, 0x18 }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x0 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x109 }, + { 0x90092, 0x18 }, + { 0x90093, 0x4 }, + { 0x90094, 0x48 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x58 }, + { 0x90098, 0xb }, + { 0x90099, 0x10 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x1 }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x5 }, + { 0x9009f, 0x7c0 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x0 }, + { 0x900a2, 0x8140 }, + { 0x900a3, 0x10c }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x8138 }, + { 0x900a6, 0x10c }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7c8 }, + { 0x900a9, 0x101 }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x448 }, + { 0x900ac, 0x109 }, + { 0x900ad, 0xf }, + { 0x900ae, 0x7c0 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x47 }, + { 0x900b1, 0x630 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x8 }, + { 0x900b4, 0x618 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0xe0 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x0 }, + { 0x900ba, 0x7c8 }, + { 0x900bb, 0x109 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x8140 }, + { 0x900be, 0x10c }, + { 0x900bf, 0x0 }, + { 0x900c0, 0x1 }, + { 0x900c1, 0x8 }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x8 }, + { 0x900c5, 0x8 }, + { 0x900c6, 0x7c8 }, + { 0x900c7, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x90026, 0x2b }, + { 0x2000b, 0x32 }, + { 0x2000c, 0x64 }, + { 0x2000d, 0x3e8 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x21 }, + { 0x12000c, 0x42 }, + { 0x12000d, 0x29a }, + { 0x12000e, 0x21 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0xffff }, + { 0x90013, 0x6152 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1600mts 1D */ + .drate = 1600, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1066mts 1D */ + .drate = 1066, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 1600mts 2D */ + .drate = 1600, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1600, 1066, }, +}; diff --git a/board/nxp/imx8mn_evk/imx8mn_evk.c b/board/nxp/imx8mn_evk/imx8mn_evk.c new file mode 100644 index 00000000000..9d3f29f2253 --- /dev/null +++ b/board/nxp/imx8mn_evk/imx8mn_evk.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include + +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0xcbabf44d, 0x12cc, 0x45dd, 0xb0, 0xc5, \ + 0x29, 0xc5, 0xb7, 0x42, 0x2d, 0x34) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MN-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 2=flash-bin raw 0 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +static void setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); +} + +int board_init(void) +{ + setup_fec(); + + return 0; +} + +int board_late_init(void) +{ +#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) + board_late_mmc_env_init(); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "DDR4 EVK"); + env_set("board_rev", "iMX8MN"); +#endif + return 0; +} diff --git a/board/nxp/imx8mn_evk/imx8mn_evk.env b/board/nxp/imx8mn_evk/imx8mn_evk.env new file mode 100644 index 00000000000..487893f9287 --- /dev/null +++ b/board/nxp/imx8mn_evk/imx8mn_evk.env @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +boot_fdt=try +boot_fit=no +boot_targets=mmc1 mmc2 dhcp +bootm_size=0x10000000 +console=ttymxc1,115200 +fdt_addr_r=0x48000000 +fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtoverlay_addr_r=0x49000000 +initrd_addr=0x48080000 +image=Image +ip_dyn=yes +kernel_addr_r=0x42000000 +loadaddr=CONFIG_SYS_LOAD_ADDR +mmcautodetect=yes +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk1p2 rootwait rw +prepare_mcore=setenv mcore_clk clk-imx8mn.mcore_booted; +pxefile_addr_r=0x40100000 +ramdisk_addr_r=0x48080000 +scriptaddr=0x40000000 + +mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} +prepare_mcore=setenv mcore_clk clk-imx8mn.mcore_booted +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if run loadfdt; then + booti ${loadaddr} - ${fdt_addr_r}; + else + echo WARN: Cannot load the DT; + fi; + fi +netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + ${get_cmd} ${loadaddr} ${image}; + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + booti ${loadaddr} - ${fdt_addr_r}; + else + echo WARN: Cannot load the DT; + fi; + fi; +bsp_bootcmd=echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; + if mmc rescan; then + if run loadimage; then + run mmcboot; + else + run netboot; + fi; + fi; diff --git a/board/nxp/imx8mn_evk/imximage-8mn-ddr4.cfg b/board/nxp/imx8mn_evk/imximage-8mn-ddr4.cfg new file mode 100644 index 00000000000..0edda9c5e06 --- /dev/null +++ b/board/nxp/imx8mn_evk/imximage-8mn-ddr4.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + + +ROM_VERSION v2 +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x912000 diff --git a/board/nxp/imx8mn_evk/lpddr4_timing.c b/board/nxp/imx8mn_evk/lpddr4_timing.c new file mode 100644 index 00000000000..671e924132a --- /dev/null +++ b/board/nxp/imx8mn_evk/lpddr4_timing.c @@ -0,0 +1,1587 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x3d400020, 0x00000213}, + {0x3d400024, 0x0003e800}, + {0x3d400030, 0x00000120}, + {0x3d400000, 0xa3080020}, + {0x3d400064, 0x006100e0}, + {0x3d4000d0, 0xc003061c}, + {0x3d4000d4, 0x009e0000}, + {0x3d4000dc, 0x00d4002d}, + {0x3d4000e0, 0x00310000}, + {0x3d4000e8, 0x0066004d}, + {0x3d4000ec, 0x0016004a}, + {0x3d400100, 0x1a201b22}, + {0x3d400104, 0x00060633}, + {0x3d40010c, 0x00c0c000}, + {0x3d400110, 0x0f04080f}, + {0x3d400114, 0x02040c0c}, + {0x3d400118, 0x01010007}, + {0x3d40011c, 0x00000401}, + {0x3d400130, 0x00020600}, + {0x3d400134, 0x0c100002}, + {0x3d400138, 0x000000e6}, + {0x3d400144, 0x00a00050}, + {0x3d400180, 0x03200018}, + {0x3d400184, 0x028061a8}, + {0x3d400188, 0x00000000}, + {0x3d400190, 0x0497820a}, + {0x3d4001b4, 0x0000170a}, + {0x3d400108, 0x070e1617}, + {0x3d4001c0, 0x00000001}, + {0x3d400194, 0x00080303}, + {0x3d4001a0, 0xe0400018}, + {0x3d4001a4, 0x00df00e4}, + {0x3d4001a8, 0x80000000}, + {0x3d4001b0, 0x00000011}, + {0x3d4001c4, 0x00000001}, + {0x3d4000f4, 0x00000c99}, + {0x3d400200, 0x00000017}, + {0x3d400204, 0x00080808}, + {0x3d400208, 0x00000000}, + {0x3d40020c, 0x00000000}, + {0x3d400210, 0x00001f1f}, + {0x3d400214, 0x07070707}, + {0x3d400218, 0x07070707}, + {0x3d40021c, 0x00000f0f}, + {0x3d400250, 0x29001701}, + {0x3d400254, 0x0000002c}, + {0x3d40025c, 0x04000030}, + {0x3d400264, 0x900093e7}, + {0x3d40026c, 0x20005574}, + {0x3d400400, 0x00000111}, + {0x3d400408, 0x000072ff}, + {0x3d400494, 0x02100e07}, + {0x3d400498, 0x00620096}, + {0x3d40049c, 0x01100e07}, + {0x3d4004a0, 0x00c8012c}, + {0x3d402020, 0x00000011}, + {0x3d402024, 0x00007d00}, + {0x3d402050, 0x0020d040}, + {0x3d402064, 0x000c001d}, + {0x3d4020f4, 0x00000c99}, + {0x3d402100, 0x0a040305}, + {0x3d402104, 0x00030407}, + {0x3d402108, 0x0203060b}, + {0x3d40210c, 0x00505000}, + {0x3d402110, 0x02040202}, + {0x3d402114, 0x02030202}, + {0x3d402118, 0x01010004}, + {0x3d40211c, 0x00000301}, + {0x3d402130, 0x00020300}, + {0x3d402134, 0x0a100002}, + {0x3d402138, 0x0000001d}, + {0x3d402144, 0x0014000a}, + {0x3d402180, 0x00650004}, + {0x3d402190, 0x03818200}, + {0x3d402194, 0x00080303}, + {0x3d4021b4, 0x00000100}, + {0x3d4020dc, 0x00840000}, + {0x3d4020e0, 0x00310000}, + {0x3d4020e8, 0x0066004d}, + {0x3d4020ec, 0x0016004a}, + {0x3d403020, 0x00000011}, + {0x3d403024, 0x00001f40}, + {0x3d403050, 0x0020d040}, + {0x3d403064, 0x00030007}, + {0x3d4030f4, 0x00000c99}, + {0x3d403100, 0x0a010102}, + {0x3d403104, 0x00030404}, + {0x3d403108, 0x0203060b}, + {0x3d40310c, 0x00505000}, + {0x3d403110, 0x02040202}, + {0x3d403114, 0x02030202}, + {0x3d403118, 0x01010004}, + {0x3d40311c, 0x00000301}, + {0x3d403130, 0x00020300}, + {0x3d403134, 0x0a100002}, + {0x3d403138, 0x00000008}, + {0x3d403144, 0x00050003}, + {0x3d403180, 0x00190004}, + {0x3d403190, 0x03818200}, + {0x3d403194, 0x00080303}, + {0x3d4031b4, 0x00000100}, + {0x3d4030dc, 0x00840000}, + {0x3d4030e0, 0x00310000}, + {0x3d4030e8, 0x0066004d}, + {0x3d4030ec, 0x0016004a}, + + /* default boot point */ + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x000d0000, 0x00000000}, + {0x000100a0, 0x00000000}, + {0x000100a1, 0x00000001}, + {0x000100a2, 0x00000002}, + {0x000100a3, 0x00000003}, + {0x000100a4, 0x00000004}, + {0x000100a5, 0x00000005}, + {0x000100a6, 0x00000006}, + {0x000100a7, 0x00000007}, + {0x000110a0, 0x00000000}, + {0x000110a1, 0x00000001}, + {0x000110a2, 0x00000003}, + {0x000110a3, 0x00000004}, + {0x000110a4, 0x00000005}, + {0x000110a5, 0x00000002}, + {0x000110a6, 0x00000007}, + {0x000110a7, 0x00000006}, + {0x0001005f, 0x0000015f}, + {0x0001015f, 0x0000015f}, + {0x0001105f, 0x0000015f}, + {0x0001115f, 0x0000015f}, + {0x0011005f, 0x0000015f}, + {0x0011015f, 0x0000015f}, + {0x0011105f, 0x0000015f}, + {0x0011115f, 0x0000015f}, + {0x0021005f, 0x0000015f}, + {0x0021015f, 0x0000015f}, + {0x0021105f, 0x0000015f}, + {0x0021115f, 0x0000015f}, + {0x00000055, 0x0000016f}, + {0x00001055, 0x0000016f}, + {0x00002055, 0x0000016f}, + {0x00003055, 0x0000016f}, + {0x00004055, 0x0000016f}, + {0x00005055, 0x0000016f}, + {0x00006055, 0x0000016f}, + {0x00007055, 0x0000016f}, + {0x00008055, 0x0000016f}, + {0x00009055, 0x0000016f}, + {0x000200c5, 0x00000019}, + {0x001200c5, 0x00000007}, + {0x002200c5, 0x00000007}, + {0x0002002e, 0x00000002}, + {0x0012002e, 0x00000002}, + {0x0022002e, 0x00000002}, + {0x00090204, 0x00000000}, + {0x00190204, 0x00000000}, + {0x00290204, 0x00000000}, + {0x00020024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0002007d, 0x00000212}, + {0x0002007c, 0x00000061}, + {0x00120024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0012007d, 0x00000212}, + {0x0012007c, 0x00000061}, + {0x00220024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0022007d, 0x00000212}, + {0x0022007c, 0x00000061}, + {0x00020056, 0x00000003}, + {0x00120056, 0x00000003}, + {0x00220056, 0x00000003}, + {0x0001004d, 0x00000f80}, + {0x0001014d, 0x00000f80}, + {0x0001104d, 0x00000f80}, + {0x0001114d, 0x00000f80}, + {0x0011004d, 0x00000f80}, + {0x0011014d, 0x00000f80}, + {0x0011104d, 0x00000f80}, + {0x0011114d, 0x00000f80}, + {0x0021004d, 0x00000f80}, + {0x0021014d, 0x00000f80}, + {0x0021104d, 0x00000f80}, + {0x0021114d, 0x00000f80}, + {0x00010049, 0x00000fbe}, + {0x00010149, 0x00000fbe}, + {0x00011049, 0x00000fbe}, + {0x00011149, 0x00000fbe}, + {0x00110049, 0x00000fbe}, + {0x00110149, 0x00000fbe}, + {0x00111049, 0x00000fbe}, + {0x00111149, 0x00000fbe}, + {0x00210049, 0x00000fbe}, + {0x00210149, 0x00000fbe}, + {0x00211049, 0x00000fbe}, + {0x00211149, 0x00000fbe}, + {0x00000043, 0x00000063}, + {0x00001043, 0x00000063}, + {0x00002043, 0x00000063}, + {0x00003043, 0x00000063}, + {0x00004043, 0x00000063}, + {0x00005043, 0x00000063}, + {0x00006043, 0x00000063}, + {0x00007043, 0x00000063}, + {0x00008043, 0x00000063}, + {0x00009043, 0x00000063}, + {0x00020018, 0x00000001}, + {0x00020075, 0x00000004}, + {0x00020050, 0x00000000}, + {0x00020008, 0x00000320}, + {0x00120008, 0x00000064}, + {0x00220008, 0x00000019}, + {0x00020088, 0x00000009}, + {0x000200b2, 0x000000dc}, + {0x00010043, 0x000005a1}, + {0x00010143, 0x000005a1}, + {0x00011043, 0x000005a1}, + {0x00011143, 0x000005a1}, + {0x001200b2, 0x000000dc}, + {0x00110043, 0x000005a1}, + {0x00110143, 0x000005a1}, + {0x00111043, 0x000005a1}, + {0x00111143, 0x000005a1}, + {0x002200b2, 0x000000dc}, + {0x00210043, 0x000005a1}, + {0x00210143, 0x000005a1}, + {0x00211043, 0x000005a1}, + {0x00211143, 0x000005a1}, + {0x000200fa, 0x00000001}, + {0x001200fa, 0x00000001}, + {0x002200fa, 0x00000001}, + {0x00020019, 0x00000001}, + {0x00120019, 0x00000001}, + {0x00220019, 0x00000001}, + {0x000200f0, 0x00000660}, + {0x000200f1, 0x00000000}, + {0x000200f2, 0x00004444}, + {0x000200f3, 0x00008888}, + {0x000200f4, 0x00005665}, + {0x000200f5, 0x00000000}, + {0x000200f6, 0x00000000}, + {0x000200f7, 0x0000f000}, + {0x0001004a, 0x00000500}, + {0x0001104a, 0x00000500}, + {0x00020025, 0x00000000}, + {0x0002002d, 0x00000000}, + {0x0012002d, 0x00000000}, + {0x0022002d, 0x00000000}, + {0x0002002c, 0x00000000}, + {0x000200c7, 0x00000021}, + {0x000200ca, 0x00000024}, + {0x000200cc, 0x000001f7}, + {0x001200c7, 0x00000021}, + {0x001200ca, 0x00000024}, + {0x001200cc, 0x000001f7}, + {0x002200c7, 0x00000021}, + {0x002200ca, 0x00000024}, + {0x002200cc, 0x000001f7}, + {0x00020060, 0x00000002}, + {0x000d0000, 0x00000001}, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2, 0x0}, + {0x1200b2, 0x0}, + {0x2200b2, 0x0}, + {0x0200cb, 0x0}, + {0x010043, 0x0}, + {0x110043, 0x0}, + {0x210043, 0x0}, + {0x010143, 0x0}, + {0x110143, 0x0}, + {0x210143, 0x0}, + {0x011043, 0x0}, + {0x111043, 0x0}, + {0x211043, 0x0}, + {0x011143, 0x0}, + {0x111143, 0x0}, + {0x211143, 0x0}, + {0x000080, 0x0}, + {0x100080, 0x0}, + {0x200080, 0x0}, + {0x001080, 0x0}, + {0x101080, 0x0}, + {0x201080, 0x0}, + {0x002080, 0x0}, + {0x102080, 0x0}, + {0x202080, 0x0}, + {0x003080, 0x0}, + {0x103080, 0x0}, + {0x203080, 0x0}, + {0x004080, 0x0}, + {0x104080, 0x0}, + {0x204080, 0x0}, + {0x005080, 0x0}, + {0x105080, 0x0}, + {0x205080, 0x0}, + {0x006080, 0x0}, + {0x106080, 0x0}, + {0x206080, 0x0}, + {0x007080, 0x0}, + {0x107080, 0x0}, + {0x207080, 0x0}, + {0x008080, 0x0}, + {0x108080, 0x0}, + {0x208080, 0x0}, + {0x009080, 0x0}, + {0x109080, 0x0}, + {0x209080, 0x0}, + {0x010080, 0x0}, + {0x110080, 0x0}, + {0x210080, 0x0}, + {0x010180, 0x0}, + {0x110180, 0x0}, + {0x210180, 0x0}, + {0x011080, 0x0}, + {0x111080, 0x0}, + {0x211080, 0x0}, + {0x011180, 0x0}, + {0x111180, 0x0}, + {0x211180, 0x0}, + {0x010081, 0x0}, + {0x110081, 0x0}, + {0x210081, 0x0}, + {0x010181, 0x0}, + {0x110181, 0x0}, + {0x210181, 0x0}, + {0x011081, 0x0}, + {0x111081, 0x0}, + {0x211081, 0x0}, + {0x011181, 0x0}, + {0x111181, 0x0}, + {0x211181, 0x0}, + {0x0100d0, 0x0}, + {0x1100d0, 0x0}, + {0x2100d0, 0x0}, + {0x0101d0, 0x0}, + {0x1101d0, 0x0}, + {0x2101d0, 0x0}, + {0x0110d0, 0x0}, + {0x1110d0, 0x0}, + {0x2110d0, 0x0}, + {0x0111d0, 0x0}, + {0x1111d0, 0x0}, + {0x2111d0, 0x0}, + {0x0100d1, 0x0}, + {0x1100d1, 0x0}, + {0x2100d1, 0x0}, + {0x0101d1, 0x0}, + {0x1101d1, 0x0}, + {0x2101d1, 0x0}, + {0x0110d1, 0x0}, + {0x1110d1, 0x0}, + {0x2110d1, 0x0}, + {0x0111d1, 0x0}, + {0x1111d1, 0x0}, + {0x2111d1, 0x0}, + {0x010068, 0x0}, + {0x010168, 0x0}, + {0x010268, 0x0}, + {0x010368, 0x0}, + {0x010468, 0x0}, + {0x010568, 0x0}, + {0x010668, 0x0}, + {0x010768, 0x0}, + {0x010868, 0x0}, + {0x011068, 0x0}, + {0x011168, 0x0}, + {0x011268, 0x0}, + {0x011368, 0x0}, + {0x011468, 0x0}, + {0x011568, 0x0}, + {0x011668, 0x0}, + {0x011768, 0x0}, + {0x011868, 0x0}, + {0x010069, 0x0}, + {0x010169, 0x0}, + {0x010269, 0x0}, + {0x010369, 0x0}, + {0x010469, 0x0}, + {0x010569, 0x0}, + {0x010669, 0x0}, + {0x010769, 0x0}, + {0x010869, 0x0}, + {0x011069, 0x0}, + {0x011169, 0x0}, + {0x011269, 0x0}, + {0x011369, 0x0}, + {0x011469, 0x0}, + {0x011569, 0x0}, + {0x011669, 0x0}, + {0x011769, 0x0}, + {0x011869, 0x0}, + {0x01008c, 0x0}, + {0x11008c, 0x0}, + {0x21008c, 0x0}, + {0x01018c, 0x0}, + {0x11018c, 0x0}, + {0x21018c, 0x0}, + {0x01108c, 0x0}, + {0x11108c, 0x0}, + {0x21108c, 0x0}, + {0x01118c, 0x0}, + {0x11118c, 0x0}, + {0x21118c, 0x0}, + {0x01008d, 0x0}, + {0x11008d, 0x0}, + {0x21008d, 0x0}, + {0x01018d, 0x0}, + {0x11018d, 0x0}, + {0x21018d, 0x0}, + {0x01108d, 0x0}, + {0x11108d, 0x0}, + {0x21108d, 0x0}, + {0x01118d, 0x0}, + {0x11118d, 0x0}, + {0x21118d, 0x0}, + {0x0100c0, 0x0}, + {0x1100c0, 0x0}, + {0x2100c0, 0x0}, + {0x0101c0, 0x0}, + {0x1101c0, 0x0}, + {0x2101c0, 0x0}, + {0x0102c0, 0x0}, + {0x1102c0, 0x0}, + {0x2102c0, 0x0}, + {0x0103c0, 0x0}, + {0x1103c0, 0x0}, + {0x2103c0, 0x0}, + {0x0104c0, 0x0}, + {0x1104c0, 0x0}, + {0x2104c0, 0x0}, + {0x0105c0, 0x0}, + {0x1105c0, 0x0}, + {0x2105c0, 0x0}, + {0x0106c0, 0x0}, + {0x1106c0, 0x0}, + {0x2106c0, 0x0}, + {0x0107c0, 0x0}, + {0x1107c0, 0x0}, + {0x2107c0, 0x0}, + {0x0108c0, 0x0}, + {0x1108c0, 0x0}, + {0x2108c0, 0x0}, + {0x0110c0, 0x0}, + {0x1110c0, 0x0}, + {0x2110c0, 0x0}, + {0x0111c0, 0x0}, + {0x1111c0, 0x0}, + {0x2111c0, 0x0}, + {0x0112c0, 0x0}, + {0x1112c0, 0x0}, + {0x2112c0, 0x0}, + {0x0113c0, 0x0}, + {0x1113c0, 0x0}, + {0x2113c0, 0x0}, + {0x0114c0, 0x0}, + {0x1114c0, 0x0}, + {0x2114c0, 0x0}, + {0x0115c0, 0x0}, + {0x1115c0, 0x0}, + {0x2115c0, 0x0}, + {0x0116c0, 0x0}, + {0x1116c0, 0x0}, + {0x2116c0, 0x0}, + {0x0117c0, 0x0}, + {0x1117c0, 0x0}, + {0x2117c0, 0x0}, + {0x0118c0, 0x0}, + {0x1118c0, 0x0}, + {0x2118c0, 0x0}, + {0x0100c1, 0x0}, + {0x1100c1, 0x0}, + {0x2100c1, 0x0}, + {0x0101c1, 0x0}, + {0x1101c1, 0x0}, + {0x2101c1, 0x0}, + {0x0102c1, 0x0}, + {0x1102c1, 0x0}, + {0x2102c1, 0x0}, + {0x0103c1, 0x0}, + {0x1103c1, 0x0}, + {0x2103c1, 0x0}, + {0x0104c1, 0x0}, + {0x1104c1, 0x0}, + {0x2104c1, 0x0}, + {0x0105c1, 0x0}, + {0x1105c1, 0x0}, + {0x2105c1, 0x0}, + {0x0106c1, 0x0}, + {0x1106c1, 0x0}, + {0x2106c1, 0x0}, + {0x0107c1, 0x0}, + {0x1107c1, 0x0}, + {0x2107c1, 0x0}, + {0x0108c1, 0x0}, + {0x1108c1, 0x0}, + {0x2108c1, 0x0}, + {0x0110c1, 0x0}, + {0x1110c1, 0x0}, + {0x2110c1, 0x0}, + {0x0111c1, 0x0}, + {0x1111c1, 0x0}, + {0x2111c1, 0x0}, + {0x0112c1, 0x0}, + {0x1112c1, 0x0}, + {0x2112c1, 0x0}, + {0x0113c1, 0x0}, + {0x1113c1, 0x0}, + {0x2113c1, 0x0}, + {0x0114c1, 0x0}, + {0x1114c1, 0x0}, + {0x2114c1, 0x0}, + {0x0115c1, 0x0}, + {0x1115c1, 0x0}, + {0x2115c1, 0x0}, + {0x0116c1, 0x0}, + {0x1116c1, 0x0}, + {0x2116c1, 0x0}, + {0x0117c1, 0x0}, + {0x1117c1, 0x0}, + {0x2117c1, 0x0}, + {0x0118c1, 0x0}, + {0x1118c1, 0x0}, + {0x2118c1, 0x0}, + {0x010020, 0x0}, + {0x110020, 0x0}, + {0x210020, 0x0}, + {0x011020, 0x0}, + {0x111020, 0x0}, + {0x211020, 0x0}, + {0x020072, 0x0}, + {0x020073, 0x0}, + {0x020074, 0x0}, + {0x0100aa, 0x0}, + {0x0110aa, 0x0}, + {0x020010, 0x0}, + {0x120010, 0x0}, + {0x220010, 0x0}, + {0x020011, 0x0}, + {0x120011, 0x0}, + {0x220011, 0x0}, + {0x0100ae, 0x0}, + {0x1100ae, 0x0}, + {0x2100ae, 0x0}, + {0x0100af, 0x0}, + {0x1100af, 0x0}, + {0x2100af, 0x0}, + {0x0110ae, 0x0}, + {0x1110ae, 0x0}, + {0x2110ae, 0x0}, + {0x0110af, 0x0}, + {0x1110af, 0x0}, + {0x2110af, 0x0}, + {0x020020, 0x0}, + {0x120020, 0x0}, + {0x220020, 0x0}, + {0x0100a0, 0x0}, + {0x0100a1, 0x0}, + {0x0100a2, 0x0}, + {0x0100a3, 0x0}, + {0x0100a4, 0x0}, + {0x0100a5, 0x0}, + {0x0100a6, 0x0}, + {0x0100a7, 0x0}, + {0x0110a0, 0x0}, + {0x0110a1, 0x0}, + {0x0110a2, 0x0}, + {0x0110a3, 0x0}, + {0x0110a4, 0x0}, + {0x0110a5, 0x0}, + {0x0110a6, 0x0}, + {0x0110a7, 0x0}, + {0x02007c, 0x0}, + {0x12007c, 0x0}, + {0x22007c, 0x0}, + {0x02007d, 0x0}, + {0x12007d, 0x0}, + {0x22007d, 0x0}, + {0x0400fd, 0x0}, + {0x0400c0, 0x0}, + {0x090201, 0x0}, + {0x190201, 0x0}, + {0x290201, 0x0}, + {0x090202, 0x0}, + {0x190202, 0x0}, + {0x290202, 0x0}, + {0x090203, 0x0}, + {0x190203, 0x0}, + {0x290203, 0x0}, + {0x090204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x090205, 0x0}, + {0x190205, 0x0}, + {0x290205, 0x0}, + {0x090206, 0x0}, + {0x190206, 0x0}, + {0x290206, 0x0}, + {0x090207, 0x0}, + {0x190207, 0x0}, + {0x290207, 0x0}, + {0x090208, 0x0}, + {0x190208, 0x0}, + {0x290208, 0x0}, + {0x010062, 0x0}, + {0x010162, 0x0}, + {0x010262, 0x0}, + {0x010362, 0x0}, + {0x010462, 0x0}, + {0x010562, 0x0}, + {0x010662, 0x0}, + {0x010762, 0x0}, + {0x010862, 0x0}, + {0x011062, 0x0}, + {0x011162, 0x0}, + {0x011262, 0x0}, + {0x011362, 0x0}, + {0x011462, 0x0}, + {0x011562, 0x0}, + {0x011662, 0x0}, + {0x011762, 0x0}, + {0x011862, 0x0}, + {0x020077, 0x0}, + {0x010001, 0x0}, + {0x011001, 0x0}, + {0x010040, 0x0}, + {0x010140, 0x0}, + {0x010240, 0x0}, + {0x010340, 0x0}, + {0x010440, 0x0}, + {0x010540, 0x0}, + {0x010640, 0x0}, + {0x010740, 0x0}, + {0x010840, 0x0}, + {0x010030, 0x0}, + {0x010130, 0x0}, + {0x010230, 0x0}, + {0x010330, 0x0}, + {0x010430, 0x0}, + {0x010530, 0x0}, + {0x010630, 0x0}, + {0x010730, 0x0}, + {0x010830, 0x0}, + {0x011040, 0x0}, + {0x011140, 0x0}, + {0x011240, 0x0}, + {0x011340, 0x0}, + {0x011440, 0x0}, + {0x011540, 0x0}, + {0x011640, 0x0}, + {0x011740, 0x0}, + {0x011840, 0x0}, + {0x011030, 0x0}, + {0x011130, 0x0}, + {0x011230, 0x0}, + {0x011330, 0x0}, + {0x011430, 0x0}, + {0x011530, 0x0}, + {0x011630, 0x0}, + {0x011730, 0x0}, + {0x011830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000000}, + {0x00054003, 0x00000c80}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000131f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00002dd4}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00002dd4}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x0000d400}, + {0x00054033, 0x0000312d}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x0000d400}, + {0x00054039, 0x0000312d}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000101}, + {0x00054003, 0x00000190}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000121f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00000084}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00000084}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x00008400}, + {0x00054033, 0x00003100}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x00008400}, + {0x00054039, 0x00003100}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000102}, + {0x00054003, 0x00000064}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000121f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00000084}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00000084}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x00008400}, + {0x00054033, 0x00003100}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x00008400}, + {0x00054039, 0x00003100}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000000}, + {0x00054003, 0x00000c80}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x00000061}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00001f7f}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00002dd4}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00002dd4}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x0000d400}, + {0x00054033, 0x0000312d}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x0000d400}, + {0x00054039, 0x0000312d}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x0}, + {0x90051, 0x45a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x448}, + {0x90055, 0x109}, + {0x90056, 0x40}, + {0x90057, 0x633}, + {0x90058, 0x179}, + {0x90059, 0x1}, + {0x9005a, 0x618}, + {0x9005b, 0x109}, + {0x9005c, 0x40c0}, + {0x9005d, 0x633}, + {0x9005e, 0x149}, + {0x9005f, 0x8}, + {0x90060, 0x4}, + {0x90061, 0x48}, + {0x90062, 0x4040}, + {0x90063, 0x633}, + {0x90064, 0x149}, + {0x90065, 0x0}, + {0x90066, 0x4}, + {0x90067, 0x48}, + {0x90068, 0x40}, + {0x90069, 0x633}, + {0x9006a, 0x149}, + {0x9006b, 0x10}, + {0x9006c, 0x4}, + {0x9006d, 0x18}, + {0x9006e, 0x0}, + {0x9006f, 0x4}, + {0x90070, 0x78}, + {0x90071, 0x549}, + {0x90072, 0x633}, + {0x90073, 0x159}, + {0x90074, 0xd49}, + {0x90075, 0x633}, + {0x90076, 0x159}, + {0x90077, 0x94a}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0x441}, + {0x9007b, 0x633}, + {0x9007c, 0x149}, + {0x9007d, 0x42}, + {0x9007e, 0x633}, + {0x9007f, 0x149}, + {0x90080, 0x1}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x0}, + {0x90084, 0xe0}, + {0x90085, 0x109}, + {0x90086, 0xa}, + {0x90087, 0x10}, + {0x90088, 0x109}, + {0x90089, 0x9}, + {0x9008a, 0x3c0}, + {0x9008b, 0x149}, + {0x9008c, 0x9}, + {0x9008d, 0x3c0}, + {0x9008e, 0x159}, + {0x9008f, 0x18}, + {0x90090, 0x10}, + {0x90091, 0x109}, + {0x90092, 0x0}, + {0x90093, 0x3c0}, + {0x90094, 0x109}, + {0x90095, 0x18}, + {0x90096, 0x4}, + {0x90097, 0x48}, + {0x90098, 0x18}, + {0x90099, 0x4}, + {0x9009a, 0x58}, + {0x9009b, 0xb}, + {0x9009c, 0x10}, + {0x9009d, 0x109}, + {0x9009e, 0x1}, + {0x9009f, 0x10}, + {0x900a0, 0x109}, + {0x900a1, 0x5}, + {0x900a2, 0x7c0}, + {0x900a3, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x790}, + {0x900a6, 0x11a}, + {0x900a7, 0x8}, + {0x900a8, 0x7aa}, + {0x900a9, 0x2a}, + {0x900aa, 0x10}, + {0x900ab, 0x7b2}, + {0x900ac, 0x2a}, + {0x900ad, 0x0}, + {0x900ae, 0x7c8}, + {0x900af, 0x109}, + {0x900b0, 0x10}, + {0x900b1, 0x10}, + {0x900b2, 0x109}, + {0x900b3, 0x10}, + {0x900b4, 0x2a8}, + {0x900b5, 0x129}, + {0x900b6, 0x8}, + {0x900b7, 0x370}, + {0x900b8, 0x129}, + {0x900b9, 0xa}, + {0x900ba, 0x3c8}, + {0x900bb, 0x1a9}, + {0x900bc, 0xc}, + {0x900bd, 0x408}, + {0x900be, 0x199}, + {0x900bf, 0x14}, + {0x900c0, 0x790}, + {0x900c1, 0x11a}, + {0x900c2, 0x8}, + {0x900c3, 0x4}, + {0x900c4, 0x18}, + {0x900c5, 0xe}, + {0x900c6, 0x408}, + {0x900c7, 0x199}, + {0x900c8, 0x8}, + {0x900c9, 0x8568}, + {0x900ca, 0x108}, + {0x900cb, 0x18}, + {0x900cc, 0x790}, + {0x900cd, 0x16a}, + {0x900ce, 0x8}, + {0x900cf, 0x1d8}, + {0x900d0, 0x169}, + {0x900d1, 0x10}, + {0x900d2, 0x8558}, + {0x900d3, 0x168}, + {0x900d4, 0x70}, + {0x900d5, 0x788}, + {0x900d6, 0x16a}, + {0x900d7, 0x1ff8}, + {0x900d8, 0x85a8}, + {0x900d9, 0x1e8}, + {0x900da, 0x50}, + {0x900db, 0x798}, + {0x900dc, 0x16a}, + {0x900dd, 0x60}, + {0x900de, 0x7a0}, + {0x900df, 0x16a}, + {0x900e0, 0x8}, + {0x900e1, 0x8310}, + {0x900e2, 0x168}, + {0x900e3, 0x8}, + {0x900e4, 0xa310}, + {0x900e5, 0x168}, + {0x900e6, 0xa}, + {0x900e7, 0x408}, + {0x900e8, 0x169}, + {0x900e9, 0x6e}, + {0x900ea, 0x0}, + {0x900eb, 0x68}, + {0x900ec, 0x0}, + {0x900ed, 0x408}, + {0x900ee, 0x169}, + {0x900ef, 0x0}, + {0x900f0, 0x8310}, + {0x900f1, 0x168}, + {0x900f2, 0x0}, + {0x900f3, 0xa310}, + {0x900f4, 0x168}, + {0x900f5, 0x1ff8}, + {0x900f6, 0x85a8}, + {0x900f7, 0x1e8}, + {0x900f8, 0x68}, + {0x900f9, 0x798}, + {0x900fa, 0x16a}, + {0x900fb, 0x78}, + {0x900fc, 0x7a0}, + {0x900fd, 0x16a}, + {0x900fe, 0x68}, + {0x900ff, 0x790}, + {0x90100, 0x16a}, + {0x90101, 0x8}, + {0x90102, 0x8b10}, + {0x90103, 0x168}, + {0x90104, 0x8}, + {0x90105, 0xab10}, + {0x90106, 0x168}, + {0x90107, 0xa}, + {0x90108, 0x408}, + {0x90109, 0x169}, + {0x9010a, 0x58}, + {0x9010b, 0x0}, + {0x9010c, 0x68}, + {0x9010d, 0x0}, + {0x9010e, 0x408}, + {0x9010f, 0x169}, + {0x90110, 0x0}, + {0x90111, 0x8b10}, + {0x90112, 0x168}, + {0x90113, 0x1}, + {0x90114, 0xab10}, + {0x90115, 0x168}, + {0x90116, 0x0}, + {0x90117, 0x1d8}, + {0x90118, 0x169}, + {0x90119, 0x80}, + {0x9011a, 0x790}, + {0x9011b, 0x16a}, + {0x9011c, 0x18}, + {0x9011d, 0x7aa}, + {0x9011e, 0x6a}, + {0x9011f, 0xa}, + {0x90120, 0x0}, + {0x90121, 0x1e9}, + {0x90122, 0x8}, + {0x90123, 0x8080}, + {0x90124, 0x108}, + {0x90125, 0xf}, + {0x90126, 0x408}, + {0x90127, 0x169}, + {0x90128, 0xc}, + {0x90129, 0x0}, + {0x9012a, 0x68}, + {0x9012b, 0x9}, + {0x9012c, 0x0}, + {0x9012d, 0x1a9}, + {0x9012e, 0x0}, + {0x9012f, 0x408}, + {0x90130, 0x169}, + {0x90131, 0x0}, + {0x90132, 0x8080}, + {0x90133, 0x108}, + {0x90134, 0x8}, + {0x90135, 0x7aa}, + {0x90136, 0x6a}, + {0x90137, 0x0}, + {0x90138, 0x8568}, + {0x90139, 0x108}, + {0x9013a, 0xb7}, + {0x9013b, 0x790}, + {0x9013c, 0x16a}, + {0x9013d, 0x1f}, + {0x9013e, 0x0}, + {0x9013f, 0x68}, + {0x90140, 0x8}, + {0x90141, 0x8558}, + {0x90142, 0x168}, + {0x90143, 0xf}, + {0x90144, 0x408}, + {0x90145, 0x169}, + {0x90146, 0xd}, + {0x90147, 0x0}, + {0x90148, 0x68}, + {0x90149, 0x0}, + {0x9014a, 0x408}, + {0x9014b, 0x169}, + {0x9014c, 0x0}, + {0x9014d, 0x8558}, + {0x9014e, 0x168}, + {0x9014f, 0x8}, + {0x90150, 0x3c8}, + {0x90151, 0x1a9}, + {0x90152, 0x3}, + {0x90153, 0x370}, + {0x90154, 0x129}, + {0x90155, 0x20}, + {0x90156, 0x2aa}, + {0x90157, 0x9}, + {0x90158, 0x0}, + {0x90159, 0x400}, + {0x9015a, 0x10e}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x10c}, + {0x90164, 0x8}, + {0x90165, 0x7c8}, + {0x90166, 0x101}, + {0x90167, 0x8}, + {0x90168, 0x448}, + {0x90169, 0x109}, + {0x9016a, 0xf}, + {0x9016b, 0x7c0}, + {0x9016c, 0x109}, + {0x9016d, 0x0}, + {0x9016e, 0xe8}, + {0x9016f, 0x109}, + {0x90170, 0x47}, + {0x90171, 0x630}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0x618}, + {0x90175, 0x109}, + {0x90176, 0x8}, + {0x90177, 0xe0}, + {0x90178, 0x109}, + {0x90179, 0x0}, + {0x9017a, 0x7c8}, + {0x9017b, 0x109}, + {0x9017c, 0x8}, + {0x9017d, 0x8140}, + {0x9017e, 0x10c}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x8}, + {0x90185, 0x8}, + {0x90186, 0x7c8}, + {0x90187, 0x101}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x8}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x29}, + {0x90026, 0x6a}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x2000b, 0x64}, + {0x2000c, 0xc8}, + {0x2000d, 0x7d0}, + {0x2000e, 0x2c}, + {0x12000b, 0xc}, + {0x12000c, 0x19}, + {0x12000d, 0xfa}, + {0x12000e, 0x10}, + {0x22000b, 0x3}, + {0x22000c, 0x6}, + {0x22000d, 0x3e}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x2}, + {0xd0000, 0x1}, +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 400, 100, }, +}; diff --git a/board/nxp/imx8mn_evk/lpddr4_timing_ld.c b/board/nxp/imx8mn_evk/lpddr4_timing_ld.c new file mode 100644 index 00000000000..aa23c350945 --- /dev/null +++ b/board/nxp/imx8mn_evk/lpddr4_timing_ld.c @@ -0,0 +1,1440 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400020, 0x111 }, + { 0x3d400024, 0x1f400 }, + { 0x3d400064, 0x300070 }, + { 0x3d4000d0, 0xc002030f }, + { 0x3d4000d4, 0x500000 }, + { 0x3d4000dc, 0xa40012 }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x66004d }, + { 0x3d4000ec, 0x16004d }, + { 0x3d400100, 0x10100d11 }, + { 0x3d400104, 0x3041a }, + { 0x3d40010c, 0x606000 }, + { 0x3d400110, 0x8040408 }, + { 0x3d400114, 0x2030606 }, + { 0x3d400118, 0x1010004 }, + { 0x3d40011c, 0x301 }, + { 0x3d400130, 0x20300 }, + { 0x3d400134, 0xa100002 }, + { 0x3d400138, 0x73 }, + { 0x3d400144, 0x500028 }, + { 0x3d400180, 0x190000c }, + { 0x3d400184, 0x14030d4 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x4898204 }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x904 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x4070f0f }, + { 0x3d400200, 0x17 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d400250, 0x29001701 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x11 }, + { 0x3d402024, 0x7d00 }, + { 0x3d402050, 0x20d040 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004d }, + { 0x3d4020ec, 0x16004d }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x11 }, + { 0x3d403024, 0x1f40 }, + { 0x3d403050, 0x20d040 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x310000 }, + { 0x3d4030e8, 0x66004d }, + { 0x3d4030ec, 0x16004d }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0xb }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x1 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x1 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x190 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0xdc }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x1200b2, 0xdc }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x2200b2, 0xdc }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2005b, 0x7529 }, + { 0x2005c, 0x0 }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x200cc, 0x1f7 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x1200cc, 0x1f7 }, + { 0x2200c7, 0x21 }, + { 0x2200ca, 0x24 }, + { 0x2200cc, 0x1f7 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2, 0x0}, + {0x1200b2, 0x0}, + {0x2200b2, 0x0}, + {0x0200cb, 0x0}, + {0x010043, 0x0}, + {0x110043, 0x0}, + {0x210043, 0x0}, + {0x010143, 0x0}, + {0x110143, 0x0}, + {0x210143, 0x0}, + {0x011043, 0x0}, + {0x111043, 0x0}, + {0x211043, 0x0}, + {0x011143, 0x0}, + {0x111143, 0x0}, + {0x211143, 0x0}, + {0x000080, 0x0}, + {0x100080, 0x0}, + {0x200080, 0x0}, + {0x001080, 0x0}, + {0x101080, 0x0}, + {0x201080, 0x0}, + {0x002080, 0x0}, + {0x102080, 0x0}, + {0x202080, 0x0}, + {0x003080, 0x0}, + {0x103080, 0x0}, + {0x203080, 0x0}, + {0x004080, 0x0}, + {0x104080, 0x0}, + {0x204080, 0x0}, + {0x005080, 0x0}, + {0x105080, 0x0}, + {0x205080, 0x0}, + {0x006080, 0x0}, + {0x106080, 0x0}, + {0x206080, 0x0}, + {0x007080, 0x0}, + {0x107080, 0x0}, + {0x207080, 0x0}, + {0x008080, 0x0}, + {0x108080, 0x0}, + {0x208080, 0x0}, + {0x009080, 0x0}, + {0x109080, 0x0}, + {0x209080, 0x0}, + {0x010080, 0x0}, + {0x110080, 0x0}, + {0x210080, 0x0}, + {0x010180, 0x0}, + {0x110180, 0x0}, + {0x210180, 0x0}, + {0x011080, 0x0}, + {0x111080, 0x0}, + {0x211080, 0x0}, + {0x011180, 0x0}, + {0x111180, 0x0}, + {0x211180, 0x0}, + {0x010081, 0x0}, + {0x110081, 0x0}, + {0x210081, 0x0}, + {0x010181, 0x0}, + {0x110181, 0x0}, + {0x210181, 0x0}, + {0x011081, 0x0}, + {0x111081, 0x0}, + {0x211081, 0x0}, + {0x011181, 0x0}, + {0x111181, 0x0}, + {0x211181, 0x0}, + {0x0100d0, 0x0}, + {0x1100d0, 0x0}, + {0x2100d0, 0x0}, + {0x0101d0, 0x0}, + {0x1101d0, 0x0}, + {0x2101d0, 0x0}, + {0x0110d0, 0x0}, + {0x1110d0, 0x0}, + {0x2110d0, 0x0}, + {0x0111d0, 0x0}, + {0x1111d0, 0x0}, + {0x2111d0, 0x0}, + {0x0100d1, 0x0}, + {0x1100d1, 0x0}, + {0x2100d1, 0x0}, + {0x0101d1, 0x0}, + {0x1101d1, 0x0}, + {0x2101d1, 0x0}, + {0x0110d1, 0x0}, + {0x1110d1, 0x0}, + {0x2110d1, 0x0}, + {0x0111d1, 0x0}, + {0x1111d1, 0x0}, + {0x2111d1, 0x0}, + {0x010068, 0x0}, + {0x010168, 0x0}, + {0x010268, 0x0}, + {0x010368, 0x0}, + {0x010468, 0x0}, + {0x010568, 0x0}, + {0x010668, 0x0}, + {0x010768, 0x0}, + {0x010868, 0x0}, + {0x011068, 0x0}, + {0x011168, 0x0}, + {0x011268, 0x0}, + {0x011368, 0x0}, + {0x011468, 0x0}, + {0x011568, 0x0}, + {0x011668, 0x0}, + {0x011768, 0x0}, + {0x011868, 0x0}, + {0x010069, 0x0}, + {0x010169, 0x0}, + {0x010269, 0x0}, + {0x010369, 0x0}, + {0x010469, 0x0}, + {0x010569, 0x0}, + {0x010669, 0x0}, + {0x010769, 0x0}, + {0x010869, 0x0}, + {0x011069, 0x0}, + {0x011169, 0x0}, + {0x011269, 0x0}, + {0x011369, 0x0}, + {0x011469, 0x0}, + {0x011569, 0x0}, + {0x011669, 0x0}, + {0x011769, 0x0}, + {0x011869, 0x0}, + {0x01008c, 0x0}, + {0x11008c, 0x0}, + {0x21008c, 0x0}, + {0x01018c, 0x0}, + {0x11018c, 0x0}, + {0x21018c, 0x0}, + {0x01108c, 0x0}, + {0x11108c, 0x0}, + {0x21108c, 0x0}, + {0x01118c, 0x0}, + {0x11118c, 0x0}, + {0x21118c, 0x0}, + {0x01008d, 0x0}, + {0x11008d, 0x0}, + {0x21008d, 0x0}, + {0x01018d, 0x0}, + {0x11018d, 0x0}, + {0x21018d, 0x0}, + {0x01108d, 0x0}, + {0x11108d, 0x0}, + {0x21108d, 0x0}, + {0x01118d, 0x0}, + {0x11118d, 0x0}, + {0x21118d, 0x0}, + {0x0100c0, 0x0}, + {0x1100c0, 0x0}, + {0x2100c0, 0x0}, + {0x0101c0, 0x0}, + {0x1101c0, 0x0}, + {0x2101c0, 0x0}, + {0x0102c0, 0x0}, + {0x1102c0, 0x0}, + {0x2102c0, 0x0}, + {0x0103c0, 0x0}, + {0x1103c0, 0x0}, + {0x2103c0, 0x0}, + {0x0104c0, 0x0}, + {0x1104c0, 0x0}, + {0x2104c0, 0x0}, + {0x0105c0, 0x0}, + {0x1105c0, 0x0}, + {0x2105c0, 0x0}, + {0x0106c0, 0x0}, + {0x1106c0, 0x0}, + {0x2106c0, 0x0}, + {0x0107c0, 0x0}, + {0x1107c0, 0x0}, + {0x2107c0, 0x0}, + {0x0108c0, 0x0}, + {0x1108c0, 0x0}, + {0x2108c0, 0x0}, + {0x0110c0, 0x0}, + {0x1110c0, 0x0}, + {0x2110c0, 0x0}, + {0x0111c0, 0x0}, + {0x1111c0, 0x0}, + {0x2111c0, 0x0}, + {0x0112c0, 0x0}, + {0x1112c0, 0x0}, + {0x2112c0, 0x0}, + {0x0113c0, 0x0}, + {0x1113c0, 0x0}, + {0x2113c0, 0x0}, + {0x0114c0, 0x0}, + {0x1114c0, 0x0}, + {0x2114c0, 0x0}, + {0x0115c0, 0x0}, + {0x1115c0, 0x0}, + {0x2115c0, 0x0}, + {0x0116c0, 0x0}, + {0x1116c0, 0x0}, + {0x2116c0, 0x0}, + {0x0117c0, 0x0}, + {0x1117c0, 0x0}, + {0x2117c0, 0x0}, + {0x0118c0, 0x0}, + {0x1118c0, 0x0}, + {0x2118c0, 0x0}, + {0x0100c1, 0x0}, + {0x1100c1, 0x0}, + {0x2100c1, 0x0}, + {0x0101c1, 0x0}, + {0x1101c1, 0x0}, + {0x2101c1, 0x0}, + {0x0102c1, 0x0}, + {0x1102c1, 0x0}, + {0x2102c1, 0x0}, + {0x0103c1, 0x0}, + {0x1103c1, 0x0}, + {0x2103c1, 0x0}, + {0x0104c1, 0x0}, + {0x1104c1, 0x0}, + {0x2104c1, 0x0}, + {0x0105c1, 0x0}, + {0x1105c1, 0x0}, + {0x2105c1, 0x0}, + {0x0106c1, 0x0}, + {0x1106c1, 0x0}, + {0x2106c1, 0x0}, + {0x0107c1, 0x0}, + {0x1107c1, 0x0}, + {0x2107c1, 0x0}, + {0x0108c1, 0x0}, + {0x1108c1, 0x0}, + {0x2108c1, 0x0}, + {0x0110c1, 0x0}, + {0x1110c1, 0x0}, + {0x2110c1, 0x0}, + {0x0111c1, 0x0}, + {0x1111c1, 0x0}, + {0x2111c1, 0x0}, + {0x0112c1, 0x0}, + {0x1112c1, 0x0}, + {0x2112c1, 0x0}, + {0x0113c1, 0x0}, + {0x1113c1, 0x0}, + {0x2113c1, 0x0}, + {0x0114c1, 0x0}, + {0x1114c1, 0x0}, + {0x2114c1, 0x0}, + {0x0115c1, 0x0}, + {0x1115c1, 0x0}, + {0x2115c1, 0x0}, + {0x0116c1, 0x0}, + {0x1116c1, 0x0}, + {0x2116c1, 0x0}, + {0x0117c1, 0x0}, + {0x1117c1, 0x0}, + {0x2117c1, 0x0}, + {0x0118c1, 0x0}, + {0x1118c1, 0x0}, + {0x2118c1, 0x0}, + {0x010020, 0x0}, + {0x110020, 0x0}, + {0x210020, 0x0}, + {0x011020, 0x0}, + {0x111020, 0x0}, + {0x211020, 0x0}, + {0x020072, 0x0}, + {0x020073, 0x0}, + {0x020074, 0x0}, + {0x0100aa, 0x0}, + {0x0110aa, 0x0}, + {0x020010, 0x0}, + {0x120010, 0x0}, + {0x220010, 0x0}, + {0x020011, 0x0}, + {0x120011, 0x0}, + {0x220011, 0x0}, + {0x0100ae, 0x0}, + {0x1100ae, 0x0}, + {0x2100ae, 0x0}, + {0x0100af, 0x0}, + {0x1100af, 0x0}, + {0x2100af, 0x0}, + {0x0110ae, 0x0}, + {0x1110ae, 0x0}, + {0x2110ae, 0x0}, + {0x0110af, 0x0}, + {0x1110af, 0x0}, + {0x2110af, 0x0}, + {0x020020, 0x0}, + {0x120020, 0x0}, + {0x220020, 0x0}, + {0x0100a0, 0x0}, + {0x0100a1, 0x0}, + {0x0100a2, 0x0}, + {0x0100a3, 0x0}, + {0x0100a4, 0x0}, + {0x0100a5, 0x0}, + {0x0100a6, 0x0}, + {0x0100a7, 0x0}, + {0x0110a0, 0x0}, + {0x0110a1, 0x0}, + {0x0110a2, 0x0}, + {0x0110a3, 0x0}, + {0x0110a4, 0x0}, + {0x0110a5, 0x0}, + {0x0110a6, 0x0}, + {0x0110a7, 0x0}, + {0x02007c, 0x0}, + {0x12007c, 0x0}, + {0x22007c, 0x0}, + {0x02007d, 0x0}, + {0x12007d, 0x0}, + {0x22007d, 0x0}, + {0x0400fd, 0x0}, + {0x0400c0, 0x0}, + {0x090201, 0x0}, + {0x190201, 0x0}, + {0x290201, 0x0}, + {0x090202, 0x0}, + {0x190202, 0x0}, + {0x290202, 0x0}, + {0x090203, 0x0}, + {0x190203, 0x0}, + {0x290203, 0x0}, + {0x090204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x090205, 0x0}, + {0x190205, 0x0}, + {0x290205, 0x0}, + {0x090206, 0x0}, + {0x190206, 0x0}, + {0x290206, 0x0}, + {0x090207, 0x0}, + {0x190207, 0x0}, + {0x290207, 0x0}, + {0x090208, 0x0}, + {0x190208, 0x0}, + {0x290208, 0x0}, + {0x010062, 0x0}, + {0x010162, 0x0}, + {0x010262, 0x0}, + {0x010362, 0x0}, + {0x010462, 0x0}, + {0x010562, 0x0}, + {0x010662, 0x0}, + {0x010762, 0x0}, + {0x010862, 0x0}, + {0x011062, 0x0}, + {0x011162, 0x0}, + {0x011262, 0x0}, + {0x011362, 0x0}, + {0x011462, 0x0}, + {0x011562, 0x0}, + {0x011662, 0x0}, + {0x011762, 0x0}, + {0x011862, 0x0}, + {0x020077, 0x0}, + {0x010001, 0x0}, + {0x011001, 0x0}, + {0x010040, 0x0}, + {0x010140, 0x0}, + {0x010240, 0x0}, + {0x010340, 0x0}, + {0x010440, 0x0}, + {0x010540, 0x0}, + {0x010640, 0x0}, + {0x010740, 0x0}, + {0x010840, 0x0}, + {0x010030, 0x0}, + {0x010130, 0x0}, + {0x010230, 0x0}, + {0x010330, 0x0}, + {0x010430, 0x0}, + {0x010530, 0x0}, + {0x010630, 0x0}, + {0x010730, 0x0}, + {0x010830, 0x0}, + {0x011040, 0x0}, + {0x011140, 0x0}, + {0x011240, 0x0}, + {0x011340, 0x0}, + {0x011440, 0x0}, + {0x011540, 0x0}, + {0x011640, 0x0}, + {0x011740, 0x0}, + {0x011840, 0x0}, + {0x011030, 0x0}, + {0x011130, 0x0}, + {0x011230, 0x0}, + {0x011330, 0x0}, + {0x011430, 0x0}, + {0x011530, 0x0}, + {0x011630, 0x0}, + {0x011730, 0x0}, + {0x011830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x12a4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x12a4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x54032, 0xa400 }, + { 0x54033, 0x3112 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xa400 }, + { 0x54039, 0x3112 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x12a4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x12a4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x54032, 0xa400 }, + { 0x54033, 0x3112 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xa400 }, + { 0x54039, 0x3112 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x448 }, + { 0x90169, 0x109 }, + { 0x9016a, 0xf }, + { 0x9016b, 0x7c0 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x0 }, + { 0x9016e, 0xe8 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x47 }, + { 0x90171, 0x630 }, + { 0x90172, 0x109 }, + { 0x90173, 0x8 }, + { 0x90174, 0x618 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0xe0 }, + { 0x90178, 0x109 }, + { 0x90179, 0x0 }, + { 0x9017a, 0x7c8 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x8 }, + { 0x9017d, 0x8140 }, + { 0x9017e, 0x10c }, + { 0x9017f, 0x0 }, + { 0x90180, 0x1 }, + { 0x90181, 0x8 }, + { 0x90182, 0x8 }, + { 0x90183, 0x4 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x7c8 }, + { 0x90187, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x32 }, + { 0x2000c, 0x64 }, + { 0x2000d, 0x3e8 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x120010, 0x5a }, + { 0x120011, 0x3 }, + { 0x220010, 0x5a }, + { 0x220011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1600mts 1D */ + .drate = 1600, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 1600mts 2D */ + .drate = 1600, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1600, 400, 100, }, +}; diff --git a/board/nxp/imx8mn_evk/spl.c b/board/nxp/imx8mn_evk/spl.c new file mode 100644 index 00000000000..f96f5c45789 --- /dev/null +++ b/board/nxp/imx8mn_evk/spl.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2018-2019, 2021 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +void spl_board_init(void) +{ + struct udevice *dev; + int ret; + + arch_misc_init(); + + puts("Normal Boot\n"); + + ret = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@30380000", + &dev); + if (ret < 0) + printf("Failed to find clock node. Check device tree\n"); +} + +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + +#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE + /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); +#else + /* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); +#endif + /* Set DVS1 to 0.85v for suspend */ + /* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* set VDD_SNVS_0V8 from default 0.85V */ + pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); + + /* enable LDO4 to 1.2v */ + pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x44); + + return 0; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + arch_cpu_init(); + + timer_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + + enable_tzc380(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/board/nxp/imx8mp_evk/Kconfig b/board/nxp/imx8mp_evk/Kconfig new file mode 100644 index 00000000000..2dfbc2c6786 --- /dev/null +++ b/board/nxp/imx8mp_evk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_IMX8MP_EVK + +config SYS_BOARD + default "imx8mp_evk" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "imx8mp_evk" + +config IMX_CONFIG + default "board/nxp/imx8mp_evk/imximage-8mp-lpddr4.cfg" + +endif diff --git a/board/nxp/imx8mp_evk/MAINTAINERS b/board/nxp/imx8mp_evk/MAINTAINERS new file mode 100644 index 00000000000..4d4e8add9ac --- /dev/null +++ b/board/nxp/imx8mp_evk/MAINTAINERS @@ -0,0 +1,7 @@ +i.MX8MP EVK BOARD +M: Fabio Estevam +M: Peng Fan +S: Maintained +F: board/nxp/imx8mp_evk/ +F: include/configs/imx8mp_evk.h +F: configs/imx8mp_evk_defconfig diff --git a/board/nxp/imx8mp_evk/Makefile b/board/nxp/imx8mp_evk/Makefile new file mode 100644 index 00000000000..3c154d7f7f5 --- /dev/null +++ b/board/nxp/imx8mp_evk/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2019 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mp_evk.o + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +endif diff --git a/board/nxp/imx8mp_evk/imx8mp_evk.c b/board/nxp/imx8mp_evk/imx8mp_evk.c new file mode 100644 index 00000000000..732c0fa561d --- /dev/null +++ b/board/nxp/imx8mp_evk/imx8mp_evk.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include + +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0x928b33bc, 0xe58b, 0x4247, 0x9f, 0x1d, \ + 0x3b, 0xf1, 0xee, 0x1c, 0xda, 0xff) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MP-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 2=flash-bin raw 0 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + +int board_late_init(void) +{ +#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) + board_late_mmc_env_init(); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "EVK"); + env_set("board_rev", "iMX8MP"); +#endif + + return 0; +} diff --git a/board/nxp/imx8mp_evk/imx8mp_evk.env b/board/nxp/imx8mp_evk/imx8mp_evk.env new file mode 100644 index 00000000000..18cdf3da056 --- /dev/null +++ b/board/nxp/imx8mp_evk/imx8mp_evk.env @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +boot_fdt=try +boot_fit=no +boot_targets=mmc1 mmc2 +bootm_size=0x10000000 +console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 +fdt_addr_r=0x43000000 +fdt_addr=0x43000000 +fdtfile=CONFIG_DEFAULT_FDT_FILE +image=Image +ip_dyn=yes +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk1p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} +prepare_mcore=setenv mcore_clk clk-imx8mp.mcore_booted +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if run loadfdt; then + booti ${loadaddr} - ${fdt_addr_r}; + else + echo WARN: Cannot load the DT; + fi; + fi; +netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + ${get_cmd} ${loadaddr} ${image}; + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + booti ${loadaddr} - ${fdt_addr_r}; + else + echo WARN: Cannot load the DT; + fi; + fi; +bsp_bootcmd=echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; + if run loadimage; then + run mmcboot; + else + run netboot; + fi; diff --git a/board/nxp/imx8mp_evk/imximage-8mp-lpddr4.cfg b/board/nxp/imx8mp_evk/imximage-8mp-lpddr4.cfg new file mode 100644 index 00000000000..6dedf1724ab --- /dev/null +++ b/board/nxp/imx8mp_evk/imximage-8mp-lpddr4.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + + +ROM_VERSION v2 +BOOT_FROM sd +LOADER u-boot-spl-ddr.bin 0x920000 diff --git a/board/nxp/imx8mp_evk/lpddr4_timing.c b/board/nxp/imx8mp_evk/lpddr4_timing.c new file mode 100644 index 00000000000..8c5306d5d20 --- /dev/null +++ b/board/nxp/imx8mp_evk/lpddr4_timing.c @@ -0,0 +1,2048 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x3d400020, 0x223 }, + { 0x3d400024, 0x124f800 }, + { 0x3d400064, 0x4900a8 }, + { 0x3d400070, 0x1027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc0030495 }, + { 0x3d4000d4, 0x770000 }, + { 0x3d4000dc, 0xc40024 }, +#else + { 0x3d400020, 0x1323 }, + { 0x3d400024, 0x1e84800 }, + { 0x3d400064, 0x7a017c }, +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC + { 0x3d400070, 0x1027f54 }, +#else + { 0x3d400070, 0x1027f10 }, +#endif + { 0x3d400074, 0x7b0 }, + { 0x3d4000d0, 0xc00307a3 }, + { 0x3d4000d4, 0xc50000 }, + { 0x3d4000dc, 0xf4003f }, +#endif + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x3d400100, 0x1618141a }, + { 0x3d400104, 0x504a6 }, + { 0x3d40010c, 0x909000 }, + { 0x3d400110, 0xb04060b }, + { 0x3d400114, 0x2030909 }, + { 0x3d400118, 0x1010006 }, + { 0x3d40011c, 0x301 }, + { 0x3d400130, 0x20500 }, + { 0x3d400134, 0xb100002 }, + { 0x3d400138, 0xad }, + { 0x3d400144, 0x78003c }, + { 0x3d400180, 0x2580012 }, + { 0x3d400184, 0x1e0493e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x4938208 }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1308 }, +#else + { 0x3d400100, 0x2028222a }, + { 0x3d400104, 0x807bf }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x12040a12 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x501 }, + { 0x3d400130, 0x20800 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x184 }, + { 0x3d400144, 0xc80064 }, + { 0x3d400180, 0x3e8001e }, + { 0x3d400184, 0x3207a12 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x49f820e }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1f0e }, +#endif + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x3d400108, 0x60c1514 }, + { 0x3d400200, 0x16 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x68070707 }, + { 0x3d40021c, 0xf08 }, + { 0x3d400250, 0x1f05 }, + { 0x3d400254, 0x1f }, + { 0x3d400264, 0x90003ff }, + { 0x3d40026c, 0x20003ff }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x1000e00 }, + { 0x3d400498, 0x3ff0000 }, + { 0x3d40049c, 0x1000e00 }, + { 0x3d4004a0, 0x3ff0000 }, + { 0x3d402020, 0x21 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc001c }, +#else + { 0x3d400108, 0x9121c1c }, +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC + { 0x3d400200, 0x13 }, + { 0x3d40020c, 0x13131300 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x50505 }, + { 0x3d400214, 0x4040404 }, + { 0x3d400218, 0x68040404 }, +#else + { 0x3d400200, 0x16 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x68070707 }, +#endif + { 0x3d40021c, 0xf08 }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc0026 }, +#endif + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x27 }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x3d403020, 0x21 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30007 }, +#else + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x3000a }, +#endif + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0xa }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x200c5, 0xa }, +#else + { 0x200c5, 0x18 }, +#endif + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x20008, 0x258 }, +#else + { 0x20008, 0x3e8 }, +#endif + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 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0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x24c4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x24c4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xc400 }, + { 0x54033, 0x3324 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xc400 }, + { 0x54039, 0x3324 }, +#else + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, +#endif + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x24c4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x24c4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xc400 }, + { 0x54033, 0x3324 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xc400 }, + { 0x54039, 0x3324 }, +#else + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, +#endif + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x2000b, 0x4b }, + { 0x2000c, 0x96 }, + { 0x2000d, 0x5dc }, +#else + { 0x200be, 0x3 }, + { 0x2000b, 0x7d }, + { 0x2000c, 0xfa }, + { 0x2000d, 0x9c4 }, +#endif + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x120010, 0x5a }, + { 0x120011, 0x3 }, + { 0x220010, 0x5a }, + { 0x220011, 0x3 }, +#endif + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + /* P0 2400mts 1D */ + .drate = 2400, +#else + /* P0 4000mts 1D */ + .drate = 4000, +#endif + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + /* P0 2400mts 2D */ + .drate = 2400, +#else + /* P0 4000mts 2D */ + .drate = 4000, +#endif + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + .fsp_table = { 2400, 400, 100, }, +#else + .fsp_table = { 4000, 400, 100, }, +#endif +}; + +#ifndef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC +void board_dram_ecc_scrub(void) +{ + ddrc_inline_ecc_scrub(0x0, 0x3ffffff); + ddrc_inline_ecc_scrub(0x20000000, 0x23ffffff); + ddrc_inline_ecc_scrub(0x40000000, 0x43ffffff); + ddrc_inline_ecc_scrub(0x4000000, 0x7ffffff); + ddrc_inline_ecc_scrub(0x24000000, 0x27ffffff); + ddrc_inline_ecc_scrub(0x44000000, 0x47ffffff); + ddrc_inline_ecc_scrub(0x8000000, 0xbffffff); + ddrc_inline_ecc_scrub(0x28000000, 0x2bffffff); + ddrc_inline_ecc_scrub(0x48000000, 0x4bffffff); + ddrc_inline_ecc_scrub(0xc000000, 0xfffffff); + ddrc_inline_ecc_scrub(0x2c000000, 0x2fffffff); + ddrc_inline_ecc_scrub(0x4c000000, 0x4fffffff); + ddrc_inline_ecc_scrub(0x10000000, 0x13ffffff); + ddrc_inline_ecc_scrub(0x30000000, 0x33ffffff); + ddrc_inline_ecc_scrub(0x50000000, 0x53ffffff); + ddrc_inline_ecc_scrub(0x14000000, 0x17ffffff); + ddrc_inline_ecc_scrub(0x34000000, 0x37ffffff); + ddrc_inline_ecc_scrub(0x54000000, 0x57ffffff); + ddrc_inline_ecc_scrub(0x18000000, 0x1bffffff); + ddrc_inline_ecc_scrub(0x38000000, 0x3bffffff); + ddrc_inline_ecc_scrub(0x58000000, 0x5bffffff); + ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff); +} +#endif +#endif diff --git a/board/nxp/imx8mp_evk/spl.c b/board/nxp/imx8mp_evk/spl.c new file mode 100644 index 00000000000..12da1b2abfb --- /dev/null +++ b/board/nxp/imx8mp_evk/spl.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2018-2019, 2021 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_dram_init(void) +{ + ddr_init(&dram_timing); +} + +void spl_board_init(void) +{ + arch_misc_init(); + + /* + * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does + * not allow to change it. Should set the clock after PMIC + * setting done. Default is 400Mhz (system_pll1_800m with div = 2) + * set by ROM for ND VDD_SOC + */ + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); + clock_enable(CCGR_GIC, 1); + + puts("Normal Boot\n"); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pmic@25\n"); + return 0; + } + if (ret < 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* + * Increase VDD_SOC to typical value 0.95V before first + * DRAM access, set DVS1 to 0.85V for suspend. + * Enable DVS control through PMIC_STBY_REQ and + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) + */ + if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV)) + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); + + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* + * Kernel uses OD/OD freq for SOC. + * To avoid timing risk from SOC to ARM,increase VDD_ARM to OD + * voltage 0.95V. + */ + + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); + + return 0; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +/* Do not use BSS area in this phase */ +void board_init_f(ulong dummy) +{ + int ret; + + arch_cpu_init(); + + init_uart_clk(1); + + ret = spl_early_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + + enable_tzc380(); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); +} diff --git a/board/nxp/imx8mq_evk/Kconfig b/board/nxp/imx8mq_evk/Kconfig new file mode 100644 index 00000000000..dd5c58a9d0f --- /dev/null +++ b/board/nxp/imx8mq_evk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_IMX8MQ_EVK + +config SYS_BOARD + default "imx8mq_evk" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "imx8mq_evk" + +config IMX_CONFIG + default "arch/arm/mach-imx/imx8m/imximage.cfg" + +endif diff --git a/board/nxp/imx8mq_evk/MAINTAINERS b/board/nxp/imx8mq_evk/MAINTAINERS new file mode 100644 index 00000000000..2fd584ea97c --- /dev/null +++ b/board/nxp/imx8mq_evk/MAINTAINERS @@ -0,0 +1,7 @@ +i.MX8MQ EVK BOARD +M: Peng Fan +M: Fabio Estevam +S: Maintained +F: board/nxp/imx8mq_evk/ +F: include/configs/imx8mq_evk.h +F: configs/imx8mq_evk_defconfig diff --git a/board/nxp/imx8mq_evk/Makefile b/board/nxp/imx8mq_evk/Makefile new file mode 100644 index 00000000000..ca449e6f369 --- /dev/null +++ b/board/nxp/imx8mq_evk/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mq_evk.o + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o +endif diff --git a/board/nxp/imx8mq_evk/imx8mq_evk.c b/board/nxp/imx8mq_evk/imx8mq_evk.c new file mode 100644 index 00000000000..e90c56c33ff --- /dev/null +++ b/board/nxp/imx8mq_evk/imx8mq_evk.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include +#include +#include + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) + +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0x296119cf, 0xdd70, 0x43de, 0x8a, 0xc8, \ + 0xa7, 0x05, 0x1f, 0x31, 0x25, 0x77) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX8MQ-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=flash-bin raw 0x42 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + return 0; +} + +int board_init(void) +{ +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3) + init_usb_clk(); +#endif + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) + board_late_mmc_env_init(); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "EVK"); + env_set("board_rev", "iMX8MQ"); +#endif + + return 0; +} diff --git a/board/nxp/imx8mq_evk/imx8mq_evk.env b/board/nxp/imx8mq_evk/imx8mq_evk.env new file mode 100644 index 00000000000..cab8c6b70bf --- /dev/null +++ b/board/nxp/imx8mq_evk/imx8mq_evk.env @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +boot_fdt=try +boot_targets=mmc1 mmc2 dhcp +bootm_size=0x10000000 +console=ttymxc0,115200 +fdt_addr_r=0x43000000 +fdtfile=CONFIG_DEFAULT_FDT_FILE +initrd_addr=0x43800000 +image=Image +ip_dyn=yes +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +loadaddr=CONFIG_SYS_LOAD_ADDR +mmcautodetect=yes +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk1p2 rootwait rw +prepare_mcore=setenv mcore_clk clk-imx8mq.mcore_booted; +scriptaddr=CONFIG_SYS_LOAD_ADDR + +mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if run loadfdt; then + booti ${loadaddr} - ${fdt_addr_r}; + else + echo WARN: Cannot load the DT; + fi; + else + echo wait for boot; + fi; +netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + ${get_cmd} ${loadaddr} ${image}; + if test ${boot_fdt} = yes || test ${boot_fit} = try; then + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + booti ${loadaddr} - ${fdt_addr_r}; + else + echo WARN: Cannot load the DT; + fi; + fi; +bsp_bootcmd=echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; + if mmc rescan; then + if run loadimage; then + run mmcboot; + else + run netboot; + fi; + fi; diff --git a/board/nxp/imx8mq_evk/lpddr4_timing.c b/board/nxp/imx8mq_evk/lpddr4_timing.c new file mode 100644 index 00000000000..e9559e3d843 --- /dev/null +++ b/board/nxp/imx8mq_evk/lpddr4_timing.c @@ -0,0 +1,1323 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include + +#define WR_POST_EXT_3200 /* recommened to define */ + +struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /* Start to config, default 3200mbps */ + { DDRC_DBG1(0), 0x00000001 }, + { DDRC_PWRCTL(0), 0x00000001 }, + { DDRC_MSTR(0), 0xa3080020 }, + { DDRC_MSTR2(0), 0x00000000 }, + { DDRC_RFSHTMG(0), 0x006100E0 }, + { DDRC_INIT0(0), 0xC003061B }, + { DDRC_INIT1(0), 0x009D0000 }, + { DDRC_INIT3(0), 0x00D4002D }, +#ifdef WR_POST_EXT_3200 + { DDRC_INIT4(0), 0x00330008 }, +#else + { DDRC_INIT4(0), 0x00310008 }, +#endif + { DDRC_INIT6(0), 0x0066004a }, + { DDRC_INIT7(0), 0x0006004a }, + + { DDRC_DRAMTMG0(0), 0x1A201B22 }, + { DDRC_DRAMTMG1(0), 0x00060633 }, + { DDRC_DRAMTMG3(0), 0x00C0C000 }, + { DDRC_DRAMTMG4(0), 0x0F04080F }, + { DDRC_DRAMTMG5(0), 0x02040C0C }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x00000401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0C100002 }, + { DDRC_DRAMTMG14(0), 0x000000E6 }, + { DDRC_DRAMTMG17(0), 0x00A00050 }, + + { DDRC_ZQCTL0(0), 0x03200018 }, + { DDRC_ZQCTL1(0), 0x028061A8 }, + { DDRC_ZQCTL2(0), 0x00000000 }, + + { DDRC_DFITMG0(0), 0x0497820A }, + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xE0400018 }, + { DDRC_DFIUPD1(0), 0x00DF00E4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000011 }, + { DDRC_DFITMG2(0), 0x0000170A }, + + { DDRC_DBICTL(0), 0x00000001 }, + { DDRC_DFIPHYMSTR(0), 0x00000001 }, + { DDRC_RANKCTL(0), 0x00000c99 }, + { DDRC_DRAMTMG2(0), 0x070E171a }, + + /* address mapping */ + { DDRC_ADDRMAP0(0), 0x00000015 }, + { DDRC_ADDRMAP3(0), 0x00000000 }, + { DDRC_ADDRMAP4(0), 0x00001F1F }, + /* bank interleave */ + { DDRC_ADDRMAP1(0), 0x00080808 }, + { DDRC_ADDRMAP5(0), 0x07070707 }, + { DDRC_ADDRMAP6(0), 0x08080707 }, + + /* performance setting */ + { DDRC_ODTCFG(0), 0x0b060908 }, + { DDRC_ODTMAP(0), 0x00000000 }, + { DDRC_SCHED(0), 0x29511505 }, + { DDRC_SCHED1(0), 0x0000002c }, + { DDRC_PERFHPR1(0), 0x5900575b }, + /* 150T starve and 0x90 max tran len */ + { DDRC_PERFLPR1(0), 0x90000096 }, + /* 300T starve and 0x10 max tran len */ + { DDRC_PERFWR1(0), 0x1000012c }, + { DDRC_DBG0(0), 0x00000016 }, + { DDRC_DBG1(0), 0x00000000 }, + { DDRC_DBGCMD(0), 0x00000000 }, + { DDRC_SWCTL(0), 0x00000001 }, + { DDRC_POISONCFG(0), 0x00000011 }, + { DDRC_PCCFG(0), 0x00000111 }, + { DDRC_PCFGR_0(0), 0x000010f3 }, + { DDRC_PCFGW_0(0), 0x000072ff }, + { DDRC_PCTRL_0(0), 0x00000001 }, + /* disable Read Qos*/ + { DDRC_PCFGQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGQOS1_0(0), 0x0062ffff }, + /* disable Write Qos*/ + { DDRC_PCFGWQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGWQOS1_0(0), 0x0000ffff }, + + /* Frequency 1: 400mbps */ + { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c }, + { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ1_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ1_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ1_RFSHTMG(0), 0x000C001c }, + { DDRC_FREQ1_INIT3(0), 0x00840000 }, + { DDRC_FREQ1_INIT4(0), 0x00310008 }, + { DDRC_FREQ1_INIT6(0), 0x0066004a }, + { DDRC_FREQ1_INIT7(0), 0x0006004a }, + + /* Frequency 2: 100mbps */ + { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ2_DRAMTMG2(0), 0x0305090c }, + { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ2_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ2_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ2_RFSHTMG(0), 0x00030007 }, + { DDRC_FREQ2_INIT3(0), 0x00840000 }, + { DDRC_FREQ2_INIT4(0), 0x00310008 }, + { DDRC_FREQ2_INIT6(0), 0x0066004a }, + { DDRC_FREQ2_INIT7(0), 0x0006004a }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x20110, 0x02 }, + { 0x20111, 0x03 }, + { 0x20112, 0x04 }, + { 0x20113, 0x05 }, + { 0x20114, 0x00 }, + { 0x20115, 0x01 }, + + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + +#ifdef WR_POST_EXT_3200 + { 0x20024, 0xeb }, +#else + { 0x20024, 0xab }, +#endif + { 0x2003a, 0x0 }, + { 0x120024, 0xab }, + { 0x2003a, 0x0 }, + { 0x220024, 0xab }, + { 0x2003a, 0x0 }, + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + + { 0x10049, 0xfbe }, + { 0x10149, 0xfbe }, + { 0x11049, 0xfbe }, + { 0x11149, 0xfbe }, + { 0x12049, 0xfbe }, + { 0x12149, 0xfbe }, + { 0x13049, 0xfbe }, + { 0x13149, 0xfbe }, + { 0x110049, 0xfbe }, + { 0x110149, 0xfbe }, + { 0x111049, 0xfbe }, + { 0x111149, 0xfbe }, + { 0x112049, 0xfbe }, + { 0x112149, 0xfbe }, + { 0x113049, 0xfbe }, + { 0x113149, 0xfbe }, + { 0x210049, 0xfbe }, + { 0x210149, 0xfbe }, + { 0x211049, 0xfbe }, + { 0x211149, 0xfbe }, + { 0x212049, 0xfbe }, + { 0x212149, 0xfbe }, + { 0x213049, 0xfbe }, + { 0x213149, 0xfbe }, + + { 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x320 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + + { 0x200c7, 0x80 }, + { 0x1200c7, 0x80 }, + { 0x2200c7, 0x80 }, + { 0x200ca, 0x106 }, + { 0x1200ca, 0x106 }, + { 0x2200ca, 0x106 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, /* PHY Ron/Rtt */ + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x131f }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + + { 0x54019, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + /* MR3/MR2 */ +#ifdef WR_POST_EXT_3200 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d /*0x312d*/ }, +#else + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ }, +#endif + /* MR11/MR4 */ + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + /* self:0x284d//MR13/MR12 */ + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ }, + /* MR16/MR14*/ + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/ }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x500*/ }, + /* MR1 */ + { 0x54038, 0xd400 }, + /* MR3/MR2 */ +#ifdef WR_POST_EXT_3200 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d/*0x312d*/ }, +#else + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ }, +#endif + /* MR11/MR4 */ + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + /* self:0x284d//MR13/MR12 */ + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ }, + /* MR16/MR14 */ + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/ }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ }, + /* { 0x5403d, 0x500 } */ + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + /* PHY Ron/Rtt */ + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)/*0x2828*/ }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, LPDDR4_TRAIN_SEQ_400 }, + { 0x54009, LPDDR4_HDT_CTL_400_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_400 << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + /* MR4/MR3 */ + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, + /* MR12/MR11 */ + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ)/*0x4d46*/ }, + /* self:0x4d28//MR14/MR13 */ + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)/*0x4d08*/ }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x5*/ }, + { 0x5401f, 0x84 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, /* MR4/MR3 */ + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ)/*0x4d46*/ },/* MR12/MR11 */ + /* self:0x4d28//MR14/MR13 */ + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)/*0x4d08*/ }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0x8400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, LPDDR4_TRAIN_SEQ_100 }, + { 0x54009, LPDDR4_HDT_CTL_100_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_100 << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x84 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0x8400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x61 }, + { 0x54009, LPDDR4_HDT_CTL_2D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 }, + { 0x54010, LPDDR4_2D_WEIGHT }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + + { 0x54032, 0xd400 }, +#ifdef WR_POST_EXT_3200 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, +#else + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d }, +#endif + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0xd400 }, +#ifdef WR_POST_EXT_3200 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, +#else + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d }, +#endif + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xf }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a7, 0x0 }, + { 0x900a8, 0x790 }, + { 0x900a9, 0x11a }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x7b2 }, + { 0x900af, 0x2a }, + { 0x900b0, 0x0 }, + { 0x900b1, 0x7c8 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xc }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x0 }, + { 0x90169, 0x8 }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x448 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0xf }, + { 0x9016e, 0x7c0 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x630 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x618 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x7c8 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x10c }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x64 }, + { 0x2000c, 0xc8 }, + { 0x2000d, 0x7d0 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x2003a, 0x2 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, + { + /* P1 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, +}; + +/* lpddr4 timing config params on EVK board */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + .fsp_table = { 3200, 400, 100, }, +}; diff --git a/board/nxp/imx8mq_evk/lpddr4_timing_b0.c b/board/nxp/imx8mq_evk/lpddr4_timing_b0.c new file mode 100644 index 00000000000..5d8f2803be6 --- /dev/null +++ b/board/nxp/imx8mq_evk/lpddr4_timing_b0.c @@ -0,0 +1,1190 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include + +#define WR_POST_EXT_3200 /* recommened to define */ + +static struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /* Start to config, default 3200mbps */ + /* dis_dq=1, indicates no reads or writes are issued to SDRAM */ + { DDRC_DBG1(0), 0x00000001 }, + /* selfref_en=1, SDRAM enter self-refresh state */ + { DDRC_PWRCTL(0), 0x00000001 }, + { DDRC_MSTR(0), 0xa3080020 }, + { DDRC_MSTR2(0), 0x00000000 }, + { DDRC_RFSHTMG(0), 0x006100E0 }, + { DDRC_INIT0(0), 0xC003061B }, + { DDRC_INIT1(0), 0x009D0000 }, + { DDRC_INIT3(0), 0x00D4002D }, +#ifdef WR_POST_EXT_3200 /* recommened to define */ + { DDRC_INIT4(0), 0x00330008 }, +#else + { DDRC_INIT4(0), 0x00310008 }, +#endif + { DDRC_INIT6(0), 0x0066004a }, + { DDRC_INIT7(0), 0x0006004a }, + + { DDRC_DRAMTMG0(0), 0x1A201B22 }, + { DDRC_DRAMTMG1(0), 0x00060633 }, + { DDRC_DRAMTMG3(0), 0x00C0C000 }, + { DDRC_DRAMTMG4(0), 0x0F04080F }, + { DDRC_DRAMTMG5(0), 0x02040C0C }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x00000401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0C100002 }, + { DDRC_DRAMTMG14(0), 0x000000E6 }, + { DDRC_DRAMTMG17(0), 0x00A00050 }, + + { DDRC_ZQCTL0(0), 0x03200018 }, + { DDRC_ZQCTL1(0), 0x028061A8 }, + { DDRC_ZQCTL2(0), 0x00000000 }, + + { DDRC_DFITMG0(0), 0x0497820A }, + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xE0400018 }, + { DDRC_DFIUPD1(0), 0x00DF00E4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000011 }, + { DDRC_DFITMG2(0), 0x0000170A }, + + { DDRC_DBICTL(0), 0x00000001 }, + { DDRC_DFIPHYMSTR(0), 0x00000001 }, + + /* need be refined by ddrphy trained value */ + { DDRC_RANKCTL(0), 0x00000c99 }, + { DDRC_DRAMTMG2(0), 0x070E171a }, + + /* address mapping */ + /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */ + { DDRC_ADDRMAP0(0), 0x00000015 }, + { DDRC_ADDRMAP3(0), 0x00000000 }, + /* addrmap_col_b10 addrmap_col_b11 set to de-activated (5-bit width) */ + { DDRC_ADDRMAP4(0), 0x00001F1F }, + /* bank interleave */ + /* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */ + { DDRC_ADDRMAP1(0), 0x00080808 }, + /* addrmap_row_b11 addrmap_row_b10_b2 addrmap_row_b1 addrmap_row_b0 */ + { DDRC_ADDRMAP5(0), 0x07070707 }, + /* addrmap_row_b15 addrmap_row_b14 addrmap_row_b13 addrmap_row_b12 */ + { DDRC_ADDRMAP6(0), 0x08080707 }, + + /* 667mts frequency setting */ + { DDRC_FREQ1_DERATEEN(0), 0x0000000 }, + { DDRC_FREQ1_DERATEINT(0), 0x0800000 }, + { DDRC_FREQ1_RFSHCTL0(0), 0x0210000 }, + { DDRC_FREQ1_RFSHTMG(0), 0x014001E }, + { DDRC_FREQ1_INIT3(0), 0x0140009 }, + { DDRC_FREQ1_INIT4(0), 0x00310008 }, + { DDRC_FREQ1_INIT6(0), 0x0066004a }, + { DDRC_FREQ1_INIT7(0), 0x0006004a }, + { DDRC_FREQ1_DRAMTMG0(0), 0xB070A07 }, + { DDRC_FREQ1_DRAMTMG1(0), 0x003040A }, + { DDRC_FREQ1_DRAMTMG2(0), 0x305080C }, + { DDRC_FREQ1_DRAMTMG3(0), 0x0505000 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x3040203 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x2030303 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x2020004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0000302 }, + { DDRC_FREQ1_DRAMTMG12(0), 0x0020310 }, + { DDRC_FREQ1_DRAMTMG13(0), 0xA100002 }, + { DDRC_FREQ1_DRAMTMG14(0), 0x0000020 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x0220011 }, + { DDRC_FREQ1_ZQCTL0(0), 0x0A70005 }, + { DDRC_FREQ1_DFITMG0(0), 0x3858202 }, + { DDRC_FREQ1_DFITMG1(0), 0x0000404 }, + { DDRC_FREQ1_DFITMG2(0), 0x0000502 }, + + /* performance setting */ + { DDRC_ODTCFG(0), 0x0b060908 }, + { DDRC_ODTMAP(0), 0x00000000 }, + { DDRC_SCHED(0), 0x29511505 }, + { DDRC_SCHED1(0), 0x0000002c }, + { DDRC_PERFHPR1(0), 0x5900575b }, + /* 150T starve and 0x90 max tran len */ + { DDRC_PERFLPR1(0), 0x90000096 }, + /* 300T starve and 0x10 max tran len */ + { DDRC_PERFWR1(0), 0x1000012c }, + { DDRC_DBG0(0), 0x00000016 }, + { DDRC_DBG1(0), 0x00000000 }, + { DDRC_DBGCMD(0), 0x00000000 }, + { DDRC_SWCTL(0), 0x00000001 }, + { DDRC_POISONCFG(0), 0x00000011 }, + { DDRC_PCCFG(0), 0x00000111 }, + { DDRC_PCFGR_0(0), 0x000010f3 }, + { DDRC_PCFGW_0(0), 0x000072ff }, + { DDRC_PCTRL_0(0), 0x00000001 }, + /* disable Read Qos*/ + { DDRC_PCFGQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGQOS1_0(0), 0x0062ffff }, + /* disable Write Qos*/ + { DDRC_PCFGWQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGWQOS1_0(0), 0x0000ffff }, + { DDRC_FREQ1_DERATEEN(0), 0x00000202 }, + { DDRC_FREQ1_DERATEINT(0), 0xec78f4b5 }, + { DDRC_FREQ1_RFSHCTL0(0), 0x00618040 }, + { DDRC_FREQ1_RFSHTMG(0), 0x00610090 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x20110, 0x02 }, /* MapCAB0toDFI */ + { 0x20111, 0x03 }, /* MapCAB1toDFI */ + { 0x20112, 0x04 }, /* MapCAB2toDFI */ + { 0x20113, 0x05 }, /* MapCAB3toDFI */ + { 0x20114, 0x00 }, /* MapCAB4toDFI */ + { 0x20115, 0x01 }, /* MapCAB5toDFI */ + + /* Initialize PHY Configuration */ + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x1 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + + { 0x20024, 0xe3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0xa3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0xa3 }, + { 0x2003a, 0x2 }, + + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + + { 0x10049, 0xfbe }, + { 0x10149, 0xfbe }, + { 0x11049, 0xfbe }, + { 0x11149, 0xfbe }, + { 0x12049, 0xfbe }, + { 0x12149, 0xfbe }, + { 0x13049, 0xfbe }, + { 0x13149, 0xfbe }, + + { 0x110049, 0xfbe }, + { 0x110149, 0xfbe }, + { 0x111049, 0xfbe }, + { 0x111149, 0xfbe }, + { 0x112049, 0xfbe }, + { 0x112149, 0xfbe }, + { 0x113049, 0xfbe }, + { 0x113149, 0xfbe }, + + { 0x210049, 0xfbe }, + { 0x210149, 0xfbe }, + { 0x211049, 0xfbe }, + { 0x211149, 0xfbe }, + { 0x212049, 0xfbe }, + { 0x212149, 0xfbe }, + { 0x213049, 0xfbe }, + { 0x213149, 0xfbe }, + + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x320 }, + { 0x120008, 0xa7 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x600 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5655 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x131f }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0xd400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x29c }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x914 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x914 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x1400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 }, + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, 0x600 }, + { 0x54038, 0x1400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 }, + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0xd0000, 0x1 }, + +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x61 }, + { 0x54009, LPDDR4_HDT_CTL_2D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 }, + { 0x54010, LPDDR4_2D_WEIGHT }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54024, 0x5 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0xd400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, + +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0xd }, + { 0x900a5, 0x7c0 }, + { 0x900a6, 0x109 }, + { 0x900a7, 0x4 }, + { 0x900a8, 0x7c0 }, + { 0x900a9, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900aa, 0x0 }, + { 0x900ab, 0x790 }, + { 0x900ac, 0x11a }, + { 0x900ad, 0x8 }, + { 0x900ae, 0x7aa }, + { 0x900af, 0x2a }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x7b2 }, + { 0x900b2, 0x2a }, + { 0x900b3, 0x0 }, + { 0x900b4, 0x7c8 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x10 }, + { 0x900b7, 0x10 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x10 }, + { 0x900ba, 0x2a8 }, + { 0x900bb, 0x129 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x370 }, + { 0x900be, 0x129 }, + { 0x900bf, 0xa }, + { 0x900c0, 0x3c8 }, + { 0x900c1, 0x1a9 }, + { 0x900c2, 0xc }, + { 0x900c3, 0x408 }, + { 0x900c4, 0x199 }, + { 0x900c5, 0x14 }, + { 0x900c6, 0x790 }, + { 0x900c7, 0x11a }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x4 }, + { 0x900ca, 0x18 }, + { 0x900cb, 0xe }, + { 0x900cc, 0x408 }, + { 0x900cd, 0x199 }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x8568 }, + { 0x900d0, 0x108 }, + { 0x900d1, 0x18 }, + { 0x900d2, 0x790 }, + { 0x900d3, 0x16a }, + { 0x900d4, 0x8 }, + { 0x900d5, 0x1d8 }, + { 0x900d6, 0x169 }, + { 0x900d7, 0x10 }, + { 0x900d8, 0x8558 }, + { 0x900d9, 0x168 }, + { 0x900da, 0x70 }, + { 0x900db, 0x788 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x1ff8 }, + { 0x900de, 0x85a8 }, + { 0x900df, 0x1e8 }, + { 0x900e0, 0x50 }, + { 0x900e1, 0x798 }, + { 0x900e2, 0x16a }, + { 0x900e3, 0x60 }, + { 0x900e4, 0x7a0 }, + { 0x900e5, 0x16a }, + { 0x900e6, 0x8 }, + { 0x900e7, 0x8310 }, + { 0x900e8, 0x168 }, + { 0x900e9, 0x8 }, + { 0x900ea, 0xa310 }, + { 0x900eb, 0x168 }, + { 0x900ec, 0xa }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x6e }, + { 0x900f0, 0x0 }, + { 0x900f1, 0x68 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0x408 }, + { 0x900f4, 0x169 }, + { 0x900f5, 0x0 }, + { 0x900f6, 0x8310 }, + { 0x900f7, 0x168 }, + { 0x900f8, 0x0 }, + { 0x900f9, 0xa310 }, + { 0x900fa, 0x168 }, + { 0x900fb, 0x1ff8 }, + { 0x900fc, 0x85a8 }, + { 0x900fd, 0x1e8 }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x798 }, + { 0x90100, 0x16a }, + { 0x90101, 0x78 }, + { 0x90102, 0x7a0 }, + { 0x90103, 0x16a }, + { 0x90104, 0x68 }, + { 0x90105, 0x790 }, + { 0x90106, 0x16a }, + { 0x90107, 0x8 }, + { 0x90108, 0x8b10 }, + { 0x90109, 0x168 }, + { 0x9010a, 0x8 }, + { 0x9010b, 0xab10 }, + { 0x9010c, 0x168 }, + { 0x9010d, 0xa }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x58 }, + { 0x90111, 0x0 }, + { 0x90112, 0x68 }, + { 0x90113, 0x0 }, + { 0x90114, 0x408 }, + { 0x90115, 0x169 }, + { 0x90116, 0x0 }, + { 0x90117, 0x8b10 }, + { 0x90118, 0x168 }, + { 0x90119, 0x0 }, + { 0x9011a, 0xab10 }, + { 0x9011b, 0x168 }, + { 0x9011c, 0x0 }, + { 0x9011d, 0x1d8 }, + { 0x9011e, 0x169 }, + { 0x9011f, 0x80 }, + { 0x90120, 0x790 }, + { 0x90121, 0x16a }, + { 0x90122, 0x18 }, + { 0x90123, 0x7aa }, + { 0x90124, 0x6a }, + { 0x90125, 0xa }, + { 0x90126, 0x0 }, + { 0x90127, 0x1e9 }, + { 0x90128, 0x8 }, + { 0x90129, 0x8080 }, + { 0x9012a, 0x108 }, + { 0x9012b, 0xf }, + { 0x9012c, 0x408 }, + { 0x9012d, 0x169 }, + { 0x9012e, 0xc }, + { 0x9012f, 0x0 }, + { 0x90130, 0x68 }, + { 0x90131, 0x9 }, + { 0x90132, 0x0 }, + { 0x90133, 0x1a9 }, + { 0x90134, 0x0 }, + { 0x90135, 0x408 }, + { 0x90136, 0x169 }, + { 0x90137, 0x0 }, + { 0x90138, 0x8080 }, + { 0x90139, 0x108 }, + { 0x9013a, 0x8 }, + { 0x9013b, 0x7aa }, + { 0x9013c, 0x6a }, + { 0x9013d, 0x0 }, + { 0x9013e, 0x8568 }, + { 0x9013f, 0x108 }, + { 0x90140, 0xb7 }, + { 0x90141, 0x790 }, + { 0x90142, 0x16a }, + { 0x90143, 0x1f }, + { 0x90144, 0x0 }, + { 0x90145, 0x68 }, + { 0x90146, 0x8 }, + { 0x90147, 0x8558 }, + { 0x90148, 0x168 }, + { 0x90149, 0xf }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0xc }, + { 0x9014d, 0x0 }, + { 0x9014e, 0x68 }, + { 0x9014f, 0x0 }, + { 0x90150, 0x408 }, + { 0x90151, 0x169 }, + { 0x90152, 0x0 }, + { 0x90153, 0x8558 }, + { 0x90154, 0x168 }, + { 0x90155, 0x8 }, + { 0x90156, 0x3c8 }, + { 0x90157, 0x1a9 }, + { 0x90158, 0x3 }, + { 0x90159, 0x370 }, + { 0x9015a, 0x129 }, + { 0x9015b, 0x20 }, + { 0x9015c, 0x2aa }, + { 0x9015d, 0x9 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x400 }, + { 0x90160, 0x10e }, + { 0x90161, 0x8 }, + { 0x90162, 0xe8 }, + { 0x90163, 0x109 }, + { 0x90164, 0x0 }, + { 0x90165, 0x8140 }, + { 0x90166, 0x10c }, + { 0x90167, 0x10 }, + { 0x90168, 0x8138 }, + { 0x90169, 0x10c }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x7c8 }, + { 0x9016c, 0x101 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x0 }, + { 0x9016f, 0x8 }, + { 0x90170, 0x8 }, + { 0x90171, 0x448 }, + { 0x90172, 0x109 }, + { 0x90173, 0xf }, + { 0x90174, 0x7c0 }, + { 0x90175, 0x109 }, + { 0x90176, 0x0 }, + { 0x90177, 0xe8 }, + { 0x90178, 0x109 }, + { 0x90179, 0x47 }, + { 0x9017a, 0x630 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x8 }, + { 0x9017d, 0x618 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0xe0 }, + { 0x90181, 0x109 }, + { 0x90182, 0x0 }, + { 0x90183, 0x7c8 }, + { 0x90184, 0x109 }, + { 0x90185, 0x8 }, + { 0x90186, 0x8140 }, + { 0x90187, 0x10c }, + { 0x90188, 0x0 }, + { 0x90189, 0x1 }, + { 0x9018a, 0x8 }, + { 0x9018b, 0x8 }, + { 0x9018c, 0x4 }, + { 0x9018d, 0x8 }, + { 0x9018e, 0x8 }, + { 0x9018f, 0x7c8 }, + { 0x90190, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2b }, + { 0x90026, 0x6c }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x64 }, + { 0x2000c, 0xc8 }, + { 0x2000d, 0x7d0 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x14 }, + { 0x12000c, 0x29 }, + { 0x12000d, 0x1a1 }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, + { + /* P1 667mts 1D */ + .drate = 667, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, +}; + +/* lpddr4 timing config params on EVK board */ +struct dram_timing_info dram_timing_b0 = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + /* + * this table must be initialized if DDRPHY bypass mode is + * not used: all fsp drate > 666MTS. + */ + .fsp_table = { 3200, 667, }, +}; diff --git a/board/nxp/imx8mq_evk/spl.c b/board/nxp/imx8mq_evk/spl.c new file mode 100644 index 00000000000..a346305c863 --- /dev/null +++ b/board/nxp/imx8mq_evk/spl.c @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018, 2021 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" + +DECLARE_GLOBAL_DATA_PTR; + +extern struct dram_timing_info dram_timing_b0; + +static void spl_dram_init(void) +{ + /* ddr init */ + if (soc_rev() >= CHIP_REV_2_1) + ddr_init(&dram_timing); + else + ddr_init(&dram_timing_b0); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + return ret; + } + + return 1; +} + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + init_clk_usdhc(0); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, + ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; + case 1: + init_clk_usdhc(1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, + ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + default: + printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +#if CONFIG_IS_ENABLED(POWER_LEGACY) +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return -ENODEV; + + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return -ENODEV; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + pmic_reg_read(p, PFUZE100_SW3AVOL, ®); + if ((reg & 0x3f) != 0x18) { + reg &= ~0x3f; + reg |= 0x18; + pmic_reg_write(p, PFUZE100_SW3AVOL, reg); + } + + ret = pfuze_mode_init(p, APS_PFM); + if (ret < 0) + return ret; + + /* set SW3A standby mode to off */ + pmic_reg_read(p, PFUZE100_SW3AMODE, ®); + reg &= ~0xf; + reg |= APS_OFF; + pmic_reg_write(p, PFUZE100_SW3AMODE, reg); + + return 0; +} +#endif + +void spl_board_init(void) +{ + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + if (sec_init()) + printf("\nsec_init failed!\n"); + } + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + init_uart_clk(0); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + enable_tzc380(); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/board/nxp/imx8qm_mek/Kconfig b/board/nxp/imx8qm_mek/Kconfig new file mode 100644 index 00000000000..789de0f1a07 --- /dev/null +++ b/board/nxp/imx8qm_mek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_IMX8QM_MEK + +config SYS_BOARD + default "imx8qm_mek" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "imx8qm_mek" + +config IMX_CONFIG + default "board/nxp/imx8qm_mek/imximage.cfg" + +endif diff --git a/board/nxp/imx8qm_mek/MAINTAINERS b/board/nxp/imx8qm_mek/MAINTAINERS new file mode 100644 index 00000000000..b3b4f9b9c23 --- /dev/null +++ b/board/nxp/imx8qm_mek/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8QM MEK BOARD +M: Peng Fan +S: Maintained +F: board/nxp/imx8qm_mek/ +F: include/configs/imx8qm_mek.h +F: configs/imx8qm_mek_defconfig diff --git a/board/nxp/imx8qm_mek/Makefile b/board/nxp/imx8qm_mek/Makefile new file mode 100644 index 00000000000..53b33a0dfb1 --- /dev/null +++ b/board/nxp/imx8qm_mek/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qm_mek.o +obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/board/nxp/imx8qm_mek/README b/board/nxp/imx8qm_mek/README new file mode 100644 index 00000000000..47fae3d2843 --- /dev/null +++ b/board/nxp/imx8qm_mek/README @@ -0,0 +1,54 @@ +U-Boot for the NXP i.MX8QM EVK board + +Quick Start +=========== + +- Build the ARM Trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Build U-Boot +- Flash the binary into the SD card +- Boot + +Get and Build the ARM Trusted firmware +====================================== + +$ git clone https://github.com/nxp-imx/imx-atf +$ cd imx-atf/ +$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga +$ make PLAT=imx8qm bl31 + +And copy the resulting bl31.bin to u-boot directory: + +$ cp build/imx8qm/release/bl31.bin path/to/u-boot/ + +Get scfw_tcm.bin and ahab-container.img +======================================= + +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin +$ chmod +x imx-sc-firmware-1.1.bin +$ ./imx-sc-firmware-1.1.bin +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin +$ chmod +x firmware-imx-8.0.bin +$ ./firmware-imx-8.0.bin + + +And copy the following firmwares to U-Boot folder: + +* `imx-sc-firmware-1.1/mx8qm-mek-scfw-tcm.bin` +* `firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img` + +Build U-Boot +============ +$ make imx8qm_mek_defconfig +$ make + +Flash the binary into the SD card +================================= + +Burn the flash.bin binary to SD card offset 32KB: + +$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 + +Boot +==== +Set Boot switch SW2: 001100. diff --git a/board/nxp/imx8qm_mek/imx8qm_mek.c b/board/nxp/imx8qm_mek/imx8qm_mek.c new file mode 100644 index 00000000000..72527f774ca --- /dev/null +++ b/board/nxp/imx8qm_mek/imx8qm_mek.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + sc_pm_clock_rate_t rate = SC_80MHZ; + int ret; + + /* Set UART0 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_0, rate); + if (ret) + return ret; + + setup_iomux_uart(); + + sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON); + + return 0; +} + +#if CONFIG_IS_ENABLED(DM_GPIO) +static void board_gpio_init(void) +{ + /* TODO */ +} +#else +static inline void board_gpio_init(void) {} +#endif + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int checkboard(void) +{ + puts("Board: iMX8QM MEK\n"); + + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + /* Power up base board */ + sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON); + + board_gpio_init(); + + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ + char *fdt_file; + bool m4_booted; + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "MEK"); + env_set("board_rev", "iMX8QM"); +#endif + + fdt_file = env_get("fdt_file"); + m4_booted = m4_parts_booted(); + + if (fdt_file && !strcmp(fdt_file, "undefined")) { + if (m4_booted) + env_set("fdt_file", "imx8qm-mek-rpmsg.dtb"); + else + env_set("fdt_file", "imx8qm-mek.dtb"); + } + + return 0; +} diff --git a/board/nxp/imx8qm_mek/imximage.cfg b/board/nxp/imx8qm_mek/imximage.cfg new file mode 100644 index 00000000000..71612678c99 --- /dev/null +++ b/board/nxp/imx8qm_mek/imximage.cfg @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QM */ +SOC_TYPE IMX8QM +/* Append seco container image */ +APPEND mx8qm-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qm-mek-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 spl/u-boot-spl.bin 0x00100000 diff --git a/board/nxp/imx8qm_mek/spl.c b/board/nxp/imx8qm_mek/spl.c new file mode 100644 index 00000000000..ad786833309 --- /dev/null +++ b/board/nxp/imx8qm_mek/spl.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2018, 2021 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + struct udevice *dev; + + uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev); + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + puts("Normal Boot\n"); +} + +void spl_board_prepare_for_boot(void) +{ + imx8_power_off_pd_devices(NULL, 0); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/board/nxp/imx8qm_mek/uboot-container.cfg b/board/nxp/imx8qm_mek/uboot-container.cfg new file mode 100644 index 00000000000..e25aa76fe18 --- /dev/null +++ b/board/nxp/imx8qm_mek/uboot-container.cfg @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + + +/* This file is to create a container image could be loaded by SPL */ +BOOT_FROM SD 0x400 +SOC_TYPE IMX8QM +CONTAINER +IMAGE A35 bl31.bin 0x80000000 +IMAGE A35 u-boot.bin CONFIG_TEXT_BASE diff --git a/board/nxp/imx8qxp_mek/Kconfig b/board/nxp/imx8qxp_mek/Kconfig new file mode 100644 index 00000000000..3d0b13061e0 --- /dev/null +++ b/board/nxp/imx8qxp_mek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_IMX8QXP_MEK + +config SYS_BOARD + default "imx8qxp_mek" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "imx8qxp_mek" + +config IMX_CONFIG + default "board/nxp/imx8qxp_mek/imximage.cfg" + +endif diff --git a/board/nxp/imx8qxp_mek/MAINTAINERS b/board/nxp/imx8qxp_mek/MAINTAINERS new file mode 100644 index 00000000000..4e8fbd15876 --- /dev/null +++ b/board/nxp/imx8qxp_mek/MAINTAINERS @@ -0,0 +1,7 @@ +i.MX8QXP MEK BOARD +M: Peng Fan +M: Fabio Estevam +S: Maintained +F: board/nxp/imx8qxp_mek/ +F: include/configs/imx8qxp_mek.h +F: configs/imx8qxp_mek_defconfig diff --git a/board/nxp/imx8qxp_mek/Makefile b/board/nxp/imx8qxp_mek/Makefile new file mode 100644 index 00000000000..459ec771eea --- /dev/null +++ b/board/nxp/imx8qxp_mek/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qxp_mek.o +obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/board/nxp/imx8qxp_mek/imx8qxp_mek.c b/board/nxp/imx8qxp_mek/imx8qxp_mek.c new file mode 100644 index 00000000000..adb9556a021 --- /dev/null +++ b/board/nxp/imx8qxp_mek/imx8qxp_mek.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + sc_pm_clock_rate_t rate = SC_80MHZ; + int ret; + + /* Set UART0 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_0, rate); + if (ret) + return ret; + + setup_iomux_uart(); + + return 0; +} + +#if CONFIG_IS_ENABLED(DM_GPIO) +static void board_gpio_init(void) +{ + struct gpio_desc desc; + int ret; + + ret = dm_gpio_lookup_name("gpio@1a_3", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "bb_per_rst_b"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 0); + udelay(50); + dm_gpio_set_value(&desc, 1); +} +#else +static inline void board_gpio_init(void) {} +#endif + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int checkboard(void) +{ + puts("Board: iMX8QXP MEK\n"); + + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + board_gpio_init(); + +#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO + { + int ret = snvs_security_sc_init(); + + if (ret) + return ret; + } +#endif + + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ + char *fdt_file; + bool m4_booted; + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "MEK"); + env_set("board_rev", "iMX8QXP"); +#endif + + fdt_file = env_get("fdt_file"); + m4_booted = m4_parts_booted(); + + if (fdt_file && !strcmp(fdt_file, "undefined")) { + if (m4_booted) + env_set("fdt_file", "imx8qxp-mek-rpmsg.dtb"); + else + env_set("fdt_file", "imx8qxp-mek.dtb"); + } + + return 0; +} diff --git a/board/nxp/imx8qxp_mek/imximage.cfg b/board/nxp/imx8qxp_mek/imximage.cfg new file mode 100644 index 00000000000..88d6955a9ef --- /dev/null +++ b/board/nxp/imx8qxp_mek/imximage.cfg @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + * + * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure + * and create imx8image boot image + */ + + +BOOT_FROM sd +/* SoC type IMX8QX */ +SOC_TYPE IMX8QX +/* Append seco container image */ +APPEND ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qx-mek-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 spl/u-boot-spl.bin 0x00100000 diff --git a/board/nxp/imx8qxp_mek/spl.c b/board/nxp/imx8qxp_mek/spl.c new file mode 100644 index 00000000000..05e3c0a2ff2 --- /dev/null +++ b/board/nxp/imx8qxp_mek/spl.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2018, 2021 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define USDHC2_SD_PWR IMX_GPIO_NR(4, 19) +static iomux_cfg_t usdhc2_sd_pwr[] = { + SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +void spl_board_init(void) +{ + struct udevice *dev; + + uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev); + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + imx8_iomux_setup_multiple_pads(usdhc2_sd_pwr, ARRAY_SIZE(usdhc2_sd_pwr)); + gpio_direction_output(USDHC2_SD_PWR, 0); + + preloader_console_init(); + + puts("Normal Boot\n"); +} + +void spl_board_prepare_for_boot(void) +{ + imx8_power_off_pd_devices(NULL, 0); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/board/nxp/imx8qxp_mek/uboot-container.cfg b/board/nxp/imx8qxp_mek/uboot-container.cfg new file mode 100644 index 00000000000..b481c98f929 --- /dev/null +++ b/board/nxp/imx8qxp_mek/uboot-container.cfg @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + + +/* This file is to create a container image could be loaded by SPL */ +BOOT_FROM SD 0x400 +SOC_TYPE IMX8QX +CONTAINER +IMAGE A35 bl31.bin 0x80000000 +IMAGE A35 u-boot.bin CONFIG_TEXT_BASE diff --git a/board/nxp/imx8ulp_evk/Kconfig b/board/nxp/imx8ulp_evk/Kconfig new file mode 100644 index 00000000000..c6c48a30f09 --- /dev/null +++ b/board/nxp/imx8ulp_evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX8ULP_EVK + +config SYS_BOARD + default "imx8ulp_evk" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "imx8ulp_evk" + +endif diff --git a/board/nxp/imx8ulp_evk/MAINTAINERS b/board/nxp/imx8ulp_evk/MAINTAINERS new file mode 100644 index 00000000000..67f725b5c54 --- /dev/null +++ b/board/nxp/imx8ulp_evk/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8ULP EVK BOARD +M: Peng Fan +S: Maintained +F: board/nxp/imx8ulp_evk/ +F: include/configs/imx8ulp_evk.h +F: configs/imx8ulp_evk_defconfig diff --git a/board/nxp/imx8ulp_evk/Makefile b/board/nxp/imx8ulp_evk/Makefile new file mode 100644 index 00000000000..7819b2675b3 --- /dev/null +++ b/board/nxp/imx8ulp_evk/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += imx8ulp_evk.o + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +ifdef CONFIG_IMX8ULP_ND_MODE +obj-y += lpddr4_timing_264.o +else +obj-y += lpddr4_timing.o +endif +endif diff --git a/board/nxp/imx8ulp_evk/imx8ulp_evk.c b/board/nxp/imx8ulp_evk/imx8ulp_evk.c new file mode 100644 index 00000000000..4bf77a488cc --- /dev/null +++ b/board/nxp/imx8ulp_evk/imx8ulp_evk.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if IS_ENABLED(CONFIG_FEC_MXC) +#define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_UP | PAD_CTL_DSE | PAD_CTL_IBE_ENABLE) +static iomux_cfg_t const enet_clk_pads[] = { + IMX8ULP_PAD_PTE19__ENET0_REFCLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + IMX8ULP_PAD_PTF10__ENET0_1588_CLKIN | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), +}; + +static int setup_fec(void) +{ + /* + * Since ref clock and timestamp clock are from external, + * set the iomux prior the clock enablement + */ + imx8ulp_iomux_setup_multiple_pads(enet_clk_pads, ARRAY_SIZE(enet_clk_pads)); + + /* Select enet time stamp clock: 001 - External Timestamp Clock */ + cgc1_enet_stamp_sel(1); + + /* enable FEC PCC */ + pcc_clock_enable(4, ENET_PCC4_SLOT, true); + pcc_reset_peripheral(4, ENET_PCC4_SLOT, false); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +#define I2C_PAD_CTRL (PAD_CTL_ODE) +static const iomux_cfg_t lpi2c0_pads[] = { + IMX8ULP_PAD_PTA8__LPI2C0_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + IMX8ULP_PAD_PTA9__LPI2C0_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), +}; + +#define TPM_PAD_CTRL (PAD_CTL_DSE) +static const iomux_cfg_t tpm0_pads[] = { + IMX8ULP_PAD_PTA3__TPM0_CH2 | MUX_PAD_CTRL(TPM_PAD_CTRL), +}; + +void mipi_dsi_mux_panel(void) +{ + int ret; + struct gpio_desc desc; + + /* It is temp solution to directly access i2c, need change to rpmsg later */ + + /* enable lpi2c0 clock and iomux */ + imx8ulp_iomux_setup_multiple_pads(lpi2c0_pads, ARRAY_SIZE(lpi2c0_pads)); + writel(0xD2000000, 0x28091060); + + ret = dm_gpio_lookup_name("gpio@20_9", &desc); + if (ret) { + printf("%s lookup gpio@20_9 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "dsi_mux"); + if (ret) { + printf("%s request dsi_mux failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); +} + +void mipi_dsi_panel_backlight(void) +{ + /* It is temp solution to directly access pwm, need change to rpmsg later */ + imx8ulp_iomux_setup_multiple_pads(tpm0_pads, ARRAY_SIZE(tpm0_pads)); + writel(0xD4000001, 0x28091054); + + /* Use center-aligned PWM mode, CPWMS=1, MSnB:MSnA = 10, ELSnB:ELSnA = 00 */ + writel(1000, 0x28095018); + writel(1000, 0x28095034); /* MOD = CV, full duty */ + writel(0x28, 0x28095010); + writel(0x20, 0x28095030); +} + +int board_init(void) +{ + + if (IS_ENABLED(CONFIG_FEC_MXC)) + setup_fec(); + + /* When sync with M33 is failed, use local driver to set for video */ + if (!is_m33_handshake_necessary() && IS_ENABLED(CONFIG_VIDEO)) { + mipi_dsi_mux_panel(); + mipi_dsi_panel_backlight(); + } + + return 0; +} + +int board_early_init_f(void) +{ + return 0; +} + +int board_late_init(void) +{ + ulong addr; + +#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) + board_late_mmc_env_init(); +#endif + + /* clear fdtaddr to avoid obsolete data */ + addr = env_get_hex("fdt_addr_r", 0); + if (addr) + memset((void *)addr, 0, 0x400); + + return 0; +} diff --git a/board/nxp/imx8ulp_evk/imx8ulp_evk.env b/board/nxp/imx8ulp_evk/imx8ulp_evk.env new file mode 100644 index 00000000000..52d7f447029 --- /dev/null +++ b/board/nxp/imx8ulp_evk/imx8ulp_evk.env @@ -0,0 +1,97 @@ +#ifdef CONFIG_AHAB_BOOT +sec_boot=yes +#else +sec_boot=no +#endif + +jh_clk= +jh_mmcboot=setenv jh_clk kvm.enable_virt_at_load=false clk_ignore_unused mem=896MB; run loadimage; \ + run mmcboot +jh_netboot=setenv jh_clk kvm.enable_virt_at_load=false clk_ignore_unused mem=896MB; run netboot + +initrd_addr=0x83800000 +scriptaddr=0x83500000 +splashimage=0x90000000 +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +fdtoverlay_addr_r=0x83040000 +fdt_addr_r=0x83000000 +fdt_addr=0x83000000 +cntr_addr=0x98000000 +emmc_dev=0 +sd_dev=2 +mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcpart=1 +image=Image +cntr_file=os_cntr_signed.bin +fdtfile=CONFIG_DEFAULT_FDT_FILE +console=ttyLP1,115200 earlycon +bootm_size=0x10000000 +boot_fit=no +mmcroot=/dev/mmcblk0p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot} +netargs=setenv bootargs ${jh_clk} console=${console} + root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} +bootscript=echo Running bootscript from mmc ...; source +auth_os=booti ${cntr_addr} +boot_os=booti ${loadaddr} - ${fdt_addr_r} +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${sec_boot} = yes; then + run auth_os; + else + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if run loadfdt loadimage; then + run boot_os; + else + echo WARN: Cannot load the fdt and image; + fi; + fi; + fi; +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if test ${sec_boot} = yes; then + ${get_cmd} ${cntr_addr} ${cntr_file}; + run auth_os; + else + ${get_cmd} ${loadaddr} ${image}; + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; + fi; +bsp_bootcmd=echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; if mmc rescan; then + if run loadbootscript; then + run bootscript; + else + if test ${sec_boot} = yes; then + if run loadcntr; then + run mmcboot; + else run netboot; + fi; + else + if run loadimage; then + run mmcboot; + else run netboot; + fi; + fi; + fi; + fi; diff --git a/board/nxp/imx8ulp_evk/lpddr4_timing.c b/board/nxp/imx8ulp_evk/lpddr4_timing.c new file mode 100644 index 00000000000..6d2805315b4 --- /dev/null +++ b/board/nxp/imx8ulp_evk/lpddr4_timing.c @@ -0,0 +1,1158 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2021 NXP + * + * Generated code from MX8ULP_DDR_tool + * + */ + +#include +#include + +/** CTL settings **/ +struct dram_cfg_param ddr_ctl_cfg[] = { + { 0x2e060000, 0xb00 }, /* 0 */ + { 0x2e060028, 0x258100 }, /* 10 */ + { 0x2e06002c, 0x17702 }, /* 11 */ + { 0x2e060030, 0x5 }, /* 12 */ + { 0x2e060034, 0x61 }, /* 13 */ + { 0x2e060038, 0x4b00 }, /* 14 */ + { 0x2e06003c, 0x2edfa }, /* 15 */ + { 0x2e060040, 0x5 }, /* 16 */ + { 0x2e060044, 0xc0 }, /* 17 */ + { 0x2e060048, 0x19c7d }, /* 18 */ + { 0x2e06004c, 0x101cdf }, /* 19 */ + { 0x2e060050, 0x5 }, /* 20 */ + { 0x2e060054, 0x420 }, /* 21 */ + { 0x2e060058, 0x1010000 }, /* 22 */ + { 0x2e06005c, 0x2011001 }, /* 23 */ + { 0x2e060060, 0x2010000 }, /* 24 */ + { 0x2e060064, 0x102 }, /* 25 */ + { 0x2e060068, 0xa }, /* 26 */ + { 0x2e06006c, 0x19 }, /* 27 */ + { 0x2e060078, 0x2020200 }, /* 30 */ + { 0x2e06007c, 0x1604 }, /* 31 */ + { 0x2e060090, 0x10 }, /* 36 */ + { 0x2e0600a4, 0x40c040c }, /* 41 */ + { 0x2e0600a8, 0x8040614 }, /* 42 */ + { 0x2e0600ac, 0x604 }, /* 43 */ + { 0x2e0600b0, 0x3090003 }, /* 44 */ + { 0x2e0600b4, 0x40002 }, /* 45 */ + { 0x2e0600b8, 0x50008 }, /* 46 */ + { 0x2e0600bc, 0x40309 }, /* 47 */ + { 0x2e0600c0, 0x2106 }, /* 48 */ + { 0x2e0600c4, 0xa090017 }, /* 49 */ + { 0x2e0600c8, 0x8200016 }, /* 50 */ + { 0x2e0600cc, 0xa0a }, /* 51 */ + { 0x2e0600d0, 0x4000694 }, /* 52 */ + { 0x2e0600d4, 0xa0a0804 }, /* 53 */ + { 0x2e0600d8, 0x4000d29 }, /* 54 */ + { 0x2e0600dc, 0xa0a0804 }, /* 55 */ + { 0x2e0600e0, 0x4004864 }, /* 56 */ + { 0x2e0600e4, 0x2030404 }, /* 57 */ + { 0x2e0600e8, 0x4040400 }, /* 58 */ + { 0x2e0600ec, 0x80b0a04 }, /* 59 */ + { 0x2e0600f0, 0x7010100 }, /* 60 */ + { 0x2e0600f4, 0x41507 }, /* 61 */ + { 0x2e0600fc, 0x1010000 }, /* 63 */ + { 0x2e060100, 0x1000000 }, /* 64 */ + { 0x2e060104, 0xe0403 }, /* 65 */ + { 0x2e060108, 0xb3 }, /* 66 */ + { 0x2e06010c, 0x1b }, /* 67 */ + { 0x2e060110, 0x16e }, /* 68 */ + { 0x2e060114, 0x94 }, /* 69 */ + { 0x2e060118, 0x803 }, /* 70 */ + { 0x2e06011c, 0x5 }, /* 71 */ + { 0x2e060120, 0x70000 }, /* 72 */ + { 0x2e060124, 0xe000f }, /* 73 */ + { 0x2e060128, 0x4a0026 }, /* 74 */ + { 0x2e06012c, 0x4000f9 }, /* 75 */ + { 0x2e060130, 0x120103 }, /* 76 */ + { 0x2e060134, 0x50005 }, /* 77 */ + { 0x2e060138, 0x7070005 }, /* 78 */ + { 0x2e06013c, 0x505010d }, /* 79 */ + { 0x2e060140, 0x101030a }, /* 80 */ + { 0x2e060144, 0x30a0505 }, /* 81 */ + { 0x2e060148, 0x5050101 }, /* 82 */ + { 0x2e06014c, 0x1030a }, /* 83 */ + { 0x2e060150, 0xe000e }, /* 84 */ + { 0x2e060154, 0x1c001c }, /* 85 */ + { 0x2e060158, 0x980098 }, /* 86 */ + { 0x2e06015c, 0x3050505 }, /* 87 */ + { 0x2e060160, 0x3010403 }, /* 88 */ + { 0x2e060164, 0x3050505 }, /* 89 */ + { 0x2e060168, 0x3010403 }, /* 90 */ + { 0x2e06016c, 0x8050505 }, /* 91 */ + { 0x2e060170, 0x3010403 }, /* 92 */ + { 0x2e060174, 0x3010000 }, /* 93 */ + { 0x2e060178, 0x10000 }, /* 94 */ + { 0x2e060180, 0x1000000 }, /* 96 */ + { 0x2e060184, 0x80104002 }, /* 97 */ + { 0x2e060188, 0x40003 }, /* 98 */ + { 0x2e06018c, 0x40005 }, /* 99 */ + { 0x2e060190, 0x30000 }, /* 100 */ + { 0x2e060194, 0x50004 }, /* 101 */ + { 0x2e060198, 0x4 }, /* 102 */ + { 0x2e06019c, 0x40003 }, /* 103 */ + { 0x2e0601a0, 0x40005 }, /* 104 */ + { 0x2e0601a8, 0x2cc0 }, /* 106 */ + { 0x2e0601ac, 0x2cc0 }, /* 107 */ + { 0x2e0601b0, 0x2cc0 }, /* 108 */ + { 0x2e0601b4, 0x2cc0 }, /* 109 */ + { 0x2e0601b8, 0x2cc0 }, /* 110 */ + { 0x2e0601c0, 0x4e5 }, /* 112 */ + { 0x2e0601c4, 0x5b80 }, /* 113 */ + { 0x2e0601c8, 0x5b80 }, /* 114 */ + { 0x2e0601cc, 0x5b80 }, /* 115 */ + { 0x2e0601d0, 0x5b80 }, /* 116 */ + { 0x2e0601d4, 0x5b80 }, /* 117 */ + { 0x2e0601dc, 0xa02 }, /* 119 */ + { 0x2e0601e0, 0x200c0 }, /* 120 */ + { 0x2e0601e4, 0x200c0 }, /* 121 */ + { 0x2e0601e8, 0x200c0 }, /* 122 */ + { 0x2e0601ec, 0x200c0 }, /* 123 */ + { 0x2e0601f0, 0x200c0 }, /* 124 */ + { 0x2e0601f8, 0x3815 }, /* 126 */ + { 0x2e06021c, 0x5000000 }, /* 135 */ + { 0x2e060220, 0x5030503 }, /* 136 */ + { 0x2e060224, 0x3 }, /* 137 */ + { 0x2e060228, 0x7010a09 }, /* 138 */ + { 0x2e06022c, 0xe0a09 }, /* 139 */ + { 0x2e060230, 0x10a0900 }, /* 140 */ + { 0x2e060234, 0xe0a0907 }, /* 141 */ + { 0x2e060238, 0xa090000 }, /* 142 */ + { 0x2e06023c, 0xa090701 }, /* 143 */ + { 0x2e060240, 0x101000e }, /* 144 */ + { 0x2e060244, 0x40003 }, /* 145 */ + { 0x2e060248, 0x7 }, /* 146 */ + { 0x2e060264, 0x4040100 }, /* 153 */ + { 0x2e060268, 0x1000000 }, /* 154 */ + { 0x2e06026c, 0x100000c0 }, /* 155 */ + { 0x2e060270, 0x100000c0 }, /* 156 */ + { 0x2e060274, 0x100000c0 }, /* 157 */ + { 0x2e06027c, 0x1600 }, /* 159 */ + { 0x2e060284, 0x1 }, /* 161 */ + { 0x2e060288, 0x2 }, /* 162 */ + { 0x2e06028c, 0x100e }, /* 163 */ + { 0x2e0602a4, 0xa0000 }, /* 169 */ + { 0x2e0602a8, 0xd0005 }, /* 170 */ + { 0x2e0602ac, 0x404 }, /* 171 */ + { 0x2e0602b0, 0xd }, /* 172 */ + { 0x2e0602b4, 0xa0014 }, /* 173 */ + { 0x2e0602b8, 0x4040018 }, /* 174 */ + { 0x2e0602bc, 0x18 }, /* 175 */ + { 0x2e0602c0, 0x35006a }, /* 176 */ + { 0x2e0602c4, 0x4040084 }, /* 177 */ + { 0x2e0602c8, 0x84 }, /* 178 */ + { 0x2e0602d8, 0x40004 }, /* 182 */ + { 0x2e0602dc, 0x30000914 }, /* 183 */ + { 0x2e0602e0, 0x3030 }, /* 184 */ + { 0x2e0602e4, 0x44440000 }, /* 185 */ + { 0x2e0602e8, 0x19191944 }, /* 186 */ + { 0x2e0602ec, 0x19191908 }, /* 187 */ + { 0x2e0602f0, 0x4000000 }, /* 188 */ + { 0x2e0602f4, 0x40404 }, /* 189 */ + { 0x2e0602f8, 0x9140004 }, /* 190 */ + { 0x2e0602fc, 0x30303000 }, /* 191 */ + { 0x2e060304, 0x19444444 }, /* 193 */ + { 0x2e060308, 0x19081919 }, /* 194 */ + { 0x2e06030c, 0x1919 }, /* 195 */ + { 0x2e060310, 0x4040400 }, /* 196 */ + { 0x2e060314, 0x1010120 }, /* 197 */ + { 0x2e060318, 0x1000100 }, /* 198 */ + { 0x2e06031c, 0x1 }, /* 199 */ + { 0x2e060324, 0x1000000 }, /* 201 */ + { 0x2e060328, 0x1 }, /* 202 */ + { 0x2e060354, 0x11000000 }, /* 213 */ + { 0x2e060358, 0x40c1815 }, /* 214 */ + { 0x2e060390, 0x30000 }, /* 228 */ + { 0x2e060394, 0x1000200 }, /* 229 */ + { 0x2e060398, 0x310040 }, /* 230 */ + { 0x2e06039c, 0x20008 }, /* 231 */ + { 0x2e0603a0, 0x400100 }, /* 232 */ + { 0x2e0603a4, 0x80060 }, /* 233 */ + { 0x2e0603a8, 0x1000200 }, /* 234 */ + { 0x2e0603ac, 0x2100040 }, /* 235 */ + { 0x2e0603b0, 0x10 }, /* 236 */ + { 0x2e0603b4, 0x50003 }, /* 237 */ + { 0x2e0603b8, 0x100001b }, /* 238 */ + { 0x2e0603d8, 0xffff0b00 }, /* 246 */ + { 0x2e0603dc, 0x1010001 }, /* 247 */ + { 0x2e0603e0, 0x1010101 }, /* 248 */ + { 0x2e0603e4, 0x10b0101 }, /* 249 */ + { 0x2e0603e8, 0x10000 }, /* 250 */ + { 0x2e0603ec, 0x4010101 }, /* 251 */ + { 0x2e0603f0, 0x1010000 }, /* 252 */ + { 0x2e0603f4, 0x4 }, /* 253 */ + { 0x2e0603fc, 0x3030101 }, /* 255 */ + { 0x2e060400, 0x103 }, /* 256 */ + { 0x2e0604a4, 0x2020101 }, /* 297 */ + { 0x2e0604a8, 0x10100 }, /* 298 */ + { 0x2e0604ac, 0x1000101 }, /* 299 */ + { 0x2e0604b0, 0x1010101 }, /* 300 */ + { 0x2e0604b4, 0x4030300 }, /* 301 */ + { 0x2e0604b8, 0x8080505 }, /* 302 */ + { 0x2e0604bc, 0x8020808 }, /* 303 */ + { 0x2e0604c0, 0x8020e00 }, /* 304 */ + { 0x2e0604c4, 0xa020e00 }, /* 305 */ + { 0x2e0604c8, 0x8000f00 }, /* 306 */ + { 0x2e0604cc, 0xa08 }, /* 307 */ + { 0x2e0604d0, 0x1010101 }, /* 308 */ + { 0x2e0604d4, 0x01000102 }, /* 309 */ + { 0x2e0604d8, 0x00000101 }, /* 310 */ + { 0x2e0604dc, 0x40400 }, /* 311 */ + { 0x2e0604e0, 0x4040000 }, /* 312 */ + { 0x2e0604e4, 0x4000000 }, /* 313 */ + { 0x2e0604e8, 0x10004 }, /* 314 */ + { 0x2e0604f0, 0xfffff }, /* 316 */ + { 0x2e0604f8, 0xfffff }, /* 318 */ + { 0x2e060500, 0xfffff }, /* 320 */ + { 0x2e060508, 0xfffff }, /* 322 */ + { 0x2e060510, 0xfffff }, /* 324 */ + { 0x2e060518, 0xfffff }, /* 326 */ + { 0x2e060520, 0xfffff }, /* 328 */ + { 0x2e060528, 0xfffff }, /* 330 */ + { 0x2e060530, 0xfffff }, /* 332 */ + { 0x2e060538, 0xfffff }, /* 334 */ + { 0x2e060540, 0xfffff }, /* 336 */ + { 0x2e060548, 0xfffff }, /* 338 */ + { 0x2e060550, 0xfffff }, /* 340 */ + { 0x2e060558, 0xfffff }, /* 342 */ + { 0x2e060560, 0xfffff }, /* 344 */ + { 0x2e060568, 0xfffff }, /* 346 */ + { 0x2e060570, 0xfffff }, /* 348 */ + { 0x2e060578, 0xfffff }, /* 350 */ + { 0x2e060580, 0xfffff }, /* 352 */ + { 0x2e060588, 0xfffff }, /* 354 */ + { 0x2e060590, 0xfffff }, /* 356 */ + { 0x2e060598, 0xfffff }, /* 358 */ + { 0x2e0605a0, 0xfffff }, /* 360 */ + { 0x2e0605a8, 0xfffff }, /* 362 */ + { 0x2e0605b0, 0xfffff }, /* 364 */ + { 0x2e0605b8, 0xfffff }, /* 366 */ + { 0x2e0605c0, 0xfffff }, /* 368 */ + { 0x2e0605c8, 0xfffff }, /* 370 */ + { 0x2e0605d0, 0xfffff }, /* 372 */ + { 0x2e0605d8, 0xfffff }, /* 374 */ + { 0x2e0605e0, 0xfffff }, /* 376 */ + { 0x2e0605e8, 0xfffff }, /* 378 */ + { 0x2e0605f0, 0xfffff }, /* 380 */ + { 0x2e0605f8, 0xfffff }, /* 382 */ + { 0x2e060600, 0xfffff }, /* 384 */ + { 0x2e060608, 0xfffff }, /* 386 */ + { 0x2e060610, 0xfffff }, /* 388 */ + { 0x2e060618, 0xfffff }, /* 390 */ + { 0x2e060620, 0xfffff }, /* 392 */ + { 0x2e060628, 0xfffff }, /* 394 */ + { 0x2e060630, 0xfffff }, /* 396 */ + { 0x2e060638, 0xfffff }, /* 398 */ + { 0x2e060640, 0xfffff }, /* 400 */ + { 0x2e060648, 0xfffff }, /* 402 */ + { 0x2e060650, 0xfffff }, /* 404 */ + { 0x2e060658, 0xfffff }, /* 406 */ + { 0x2e060660, 0xfffff }, /* 408 */ + { 0x2e060668, 0xfffff }, /* 410 */ + { 0x2e060670, 0xfffff }, /* 412 */ + { 0x2e060678, 0xfffff }, /* 414 */ + { 0x2e060680, 0xfffff }, /* 416 */ + { 0x2e060688, 0xfffff }, /* 418 */ + { 0x2e060690, 0xfffff }, /* 420 */ + { 0x2e060698, 0xfffff }, /* 422 */ + { 0x2e0606a0, 0xfffff }, /* 424 */ + { 0x2e0606a8, 0xfffff }, /* 426 */ + { 0x2e0606b0, 0xfffff }, /* 428 */ + { 0x2e0606b8, 0xfffff }, /* 430 */ + { 0x2e0606c0, 0xfffff }, /* 432 */ + { 0x2e0606c8, 0xfffff }, /* 434 */ + { 0x2e0606d0, 0xfffff }, /* 436 */ + { 0x2e0606d8, 0xfffff }, /* 438 */ + { 0x2e0606e0, 0xfffff }, /* 440 */ + { 0x2e0606e8, 0x30fffff }, /* 442 */ + { 0x2e0606ec, 0xffffffff }, /* 443 */ + { 0x2e0606f0, 0x30f0f }, /* 444 */ + { 0x2e0606f4, 0xffffffff }, /* 445 */ + { 0x2e0606f8, 0x30f0f }, /* 446 */ + { 0x2e0606fc, 0xffffffff }, /* 447 */ + { 0x2e060700, 0x30f0f }, /* 448 */ + { 0x2e060704, 0xffffffff }, /* 449 */ + { 0x2e060708, 0x30f0f }, /* 450 */ + { 0x2e06070c, 0xffffffff }, /* 451 */ + { 0x2e060710, 0x30f0f }, /* 452 */ + { 0x2e060714, 0xffffffff }, /* 453 */ + { 0x2e060718, 0x30f0f }, /* 454 */ + { 0x2e06071c, 0xffffffff }, /* 455 */ + { 0x2e060720, 0x30f0f }, /* 456 */ + { 0x2e060724, 0xffffffff }, /* 457 */ + { 0x2e060728, 0x30f0f }, /* 458 */ + { 0x2e06072c, 0xffffffff }, /* 459 */ + { 0x2e060730, 0x30f0f }, /* 460 */ + { 0x2e060734, 0xffffffff }, /* 461 */ + { 0x2e060738, 0x30f0f }, /* 462 */ + { 0x2e06073c, 0xffffffff }, /* 463 */ + { 0x2e060740, 0x30f0f }, /* 464 */ + { 0x2e060744, 0xffffffff }, /* 465 */ + { 0x2e060748, 0x30f0f }, /* 466 */ + { 0x2e06074c, 0xffffffff }, /* 467 */ + { 0x2e060750, 0x30f0f }, /* 468 */ + { 0x2e060754, 0xffffffff }, /* 469 */ + { 0x2e060758, 0x30f0f }, /* 470 */ + { 0x2e06075c, 0xffffffff }, /* 471 */ + { 0x2e060760, 0x30f0f }, /* 472 */ + { 0x2e060764, 0xffffffff }, /* 473 */ + { 0x2e060768, 0x30f0f }, /* 474 */ + { 0x2e06076c, 0xffffffff }, /* 475 */ + { 0x2e060770, 0x30f0f }, /* 476 */ + { 0x2e060774, 0xffffffff }, /* 477 */ + { 0x2e060778, 0x30f0f }, /* 478 */ + { 0x2e06077c, 0xffffffff }, /* 479 */ + { 0x2e060780, 0x30f0f }, /* 480 */ + { 0x2e060784, 0xffffffff }, /* 481 */ + { 0x2e060788, 0x30f0f }, /* 482 */ + { 0x2e06078c, 0xffffffff }, /* 483 */ + { 0x2e060790, 0x30f0f }, /* 484 */ + { 0x2e060794, 0xffffffff }, /* 485 */ + { 0x2e060798, 0x30f0f }, /* 486 */ + { 0x2e06079c, 0xffffffff }, /* 487 */ + { 0x2e0607a0, 0x30f0f }, /* 488 */ + { 0x2e0607a4, 0xffffffff }, /* 489 */ + { 0x2e0607a8, 0x30f0f }, /* 490 */ + { 0x2e0607ac, 0xffffffff }, /* 491 */ + { 0x2e0607b0, 0x30f0f }, /* 492 */ + { 0x2e0607b4, 0xffffffff }, /* 493 */ + { 0x2e0607b8, 0x30f0f }, /* 494 */ + { 0x2e0607bc, 0xffffffff }, /* 495 */ + { 0x2e0607c0, 0x30f0f }, /* 496 */ + { 0x2e0607c4, 0xffffffff }, /* 497 */ + { 0x2e0607c8, 0x30f0f }, /* 498 */ + { 0x2e0607cc, 0xffffffff }, /* 499 */ + { 0x2e0607d0, 0x30f0f }, /* 500 */ + { 0x2e0607d4, 0xffffffff }, /* 501 */ + { 0x2e0607d8, 0x30f0f }, /* 502 */ + { 0x2e0607dc, 0xffffffff }, /* 503 */ + { 0x2e0607e0, 0x30f0f }, /* 504 */ + { 0x2e0607e4, 0xffffffff }, /* 505 */ + { 0x2e0607e8, 0x30f0f }, /* 506 */ + { 0x2e0607ec, 0xffffffff }, /* 507 */ + { 0x2e0607f0, 0x30f0f }, /* 508 */ + { 0x2e0607f4, 0xffffffff }, /* 509 */ + { 0x2e0607f8, 0x30f0f }, /* 510 */ + { 0x2e0607fc, 0xffffffff }, /* 511 */ + { 0x2e060800, 0x30f0f }, /* 512 */ + { 0x2e060804, 0xffffffff }, /* 513 */ + { 0x2e060808, 0x30f0f }, /* 514 */ + { 0x2e06080c, 0xffffffff }, /* 515 */ + { 0x2e060810, 0x30f0f }, /* 516 */ + { 0x2e060814, 0xffffffff }, /* 517 */ + { 0x2e060818, 0x30f0f }, /* 518 */ + { 0x2e06081c, 0xffffffff }, /* 519 */ + { 0x2e060820, 0x30f0f }, /* 520 */ + { 0x2e060824, 0xffffffff }, /* 521 */ + { 0x2e060828, 0x30f0f }, /* 522 */ + { 0x2e06082c, 0xffffffff }, /* 523 */ + { 0x2e060830, 0x30f0f }, /* 524 */ + { 0x2e060834, 0xffffffff }, /* 525 */ + { 0x2e060838, 0x30f0f }, /* 526 */ + { 0x2e06083c, 0xffffffff }, /* 527 */ + { 0x2e060840, 0x30f0f }, /* 528 */ + { 0x2e060844, 0xffffffff }, /* 529 */ + { 0x2e060848, 0x30f0f }, /* 530 */ + { 0x2e06084c, 0xffffffff }, /* 531 */ + { 0x2e060850, 0x30f0f }, /* 532 */ + { 0x2e060854, 0xffffffff }, /* 533 */ + { 0x2e060858, 0x30f0f }, /* 534 */ + { 0x2e06085c, 0xffffffff }, /* 535 */ + { 0x2e060860, 0x30f0f }, /* 536 */ + { 0x2e060864, 0xffffffff }, /* 537 */ + { 0x2e060868, 0x30f0f }, /* 538 */ + { 0x2e06086c, 0xffffffff }, /* 539 */ + { 0x2e060870, 0x30f0f }, /* 540 */ + { 0x2e060874, 0xffffffff }, /* 541 */ + { 0x2e060878, 0x30f0f }, /* 542 */ + { 0x2e06087c, 0xffffffff }, /* 543 */ + { 0x2e060880, 0x30f0f }, /* 544 */ + { 0x2e060884, 0xffffffff }, /* 545 */ + { 0x2e060888, 0x30f0f }, /* 546 */ + { 0x2e06088c, 0xffffffff }, /* 547 */ + { 0x2e060890, 0x30f0f }, /* 548 */ + { 0x2e060894, 0xffffffff }, /* 549 */ + { 0x2e060898, 0x30f0f }, /* 550 */ + { 0x2e06089c, 0xffffffff }, /* 551 */ + { 0x2e0608a0, 0x30f0f }, /* 552 */ + { 0x2e0608a4, 0xffffffff }, /* 553 */ + { 0x2e0608a8, 0x30f0f }, /* 554 */ + { 0x2e0608ac, 0xffffffff }, /* 555 */ + { 0x2e0608b0, 0x30f0f }, /* 556 */ + { 0x2e0608b4, 0xffffffff }, /* 557 */ + { 0x2e0608b8, 0x30f0f }, /* 558 */ + { 0x2e0608bc, 0xffffffff }, /* 559 */ + { 0x2e0608c0, 0x30f0f }, /* 560 */ + { 0x2e0608c4, 0xffffffff }, /* 561 */ + { 0x2e0608c8, 0x30f0f }, /* 562 */ + { 0x2e0608cc, 0xffffffff }, /* 563 */ + { 0x2e0608d0, 0x30f0f }, /* 564 */ + { 0x2e0608d4, 0xffffffff }, /* 565 */ + { 0x2e0608d8, 0x30f0f }, /* 566 */ + { 0x2e0608dc, 0xffffffff }, /* 567 */ + { 0x2e0608e0, 0x30f0f }, /* 568 */ + { 0x2e0608e4, 0xffffffff }, /* 569 */ + { 0x2e0608e8, 0x32070f0f }, /* 570 */ + { 0x2e0608ec, 0x1320000 }, /* 571 */ + { 0x2e0608f0, 0x13200 }, /* 572 */ + { 0x2e0608f4, 0x132 }, /* 573 */ + { 0x2e0608fc, 0x1b1b0000 }, /* 575 */ + { 0x2e060900, 0x21 }, /* 576 */ + { 0x2e060904, 0xa }, /* 577 */ + { 0x2e060908, 0x166 }, /* 578 */ + { 0x2e06090c, 0x200 }, /* 579 */ + { 0x2e060910, 0x200 }, /* 580 */ + { 0x2e060914, 0x200 }, /* 581 */ + { 0x2e060918, 0x200 }, /* 582 */ + { 0x2e06091c, 0x432 }, /* 583 */ + { 0x2e060920, 0xdfc }, /* 584 */ + { 0x2e060924, 0x204 }, /* 585 */ + { 0x2e060928, 0x2dc }, /* 586 */ + { 0x2e06092c, 0x200 }, /* 587 */ + { 0x2e060930, 0x200 }, /* 588 */ + { 0x2e060934, 0x200 }, /* 589 */ + { 0x2e060938, 0x200 }, /* 590 */ + { 0x2e06093c, 0x894 }, /* 591 */ + { 0x2e060940, 0x1c98 }, /* 592 */ + { 0x2e060944, 0x204 }, /* 593 */ + { 0x2e060948, 0x1006 }, /* 594 */ + { 0x2e06094c, 0x200 }, /* 595 */ + { 0x2e060950, 0x200 }, /* 596 */ + { 0x2e060954, 0x200 }, /* 597 */ + { 0x2e060958, 0x200 }, /* 598 */ + { 0x2e06095c, 0x3012 }, /* 599 */ + { 0x2e060960, 0xa03c }, /* 600 */ + { 0x2e060964, 0x2020406 }, /* 601 */ + { 0x2e060968, 0x2030202 }, /* 602 */ + { 0x2e06096c, 0x1000202 }, /* 603 */ + { 0x2e060970, 0x3040100 }, /* 604 */ + { 0x2e060974, 0x10105 }, /* 605 */ + { 0x2e060978, 0x10101 }, /* 606 */ + { 0x2e06097c, 0x10101 }, /* 607 */ + { 0x2e060980, 0x10001 }, /* 608 */ + { 0x2e060984, 0x101 }, /* 609 */ + { 0x2e060988, 0x2000201 }, /* 610 */ + { 0x2e06098c, 0x2010000 }, /* 611 */ + { 0x2e060990, 0x6000200 }, /* 612 */ + { 0x2e060994, 0x3000a06 }, /* 613 */ + { 0x2e060998, 0x2000c03 }, /* 614 */ +}; + +/** PI settings **/ +struct dram_cfg_param ddr_pi_cfg[] = { + { 0x2e062000, 0xb00 }, /* 0 */ + { 0x2e062004, 0xbeedb66f }, /* 1 */ + { 0x2e062008, 0xabef6bd }, /* 2 */ + { 0x2e06200c, 0x1001387 }, /* 3 */ + { 0x2e062010, 0x1 }, /* 4 */ + { 0x2e062014, 0x10064 }, /* 5 */ + { 0x2e06202c, 0x201 }, /* 11 */ + { 0x2e062030, 0x7 }, /* 12 */ + { 0x2e062034, 0x50001 }, /* 13 */ + { 0x2e062038, 0x3030800 }, /* 14 */ + { 0x2e06203c, 0x1 }, /* 15 */ + { 0x2e062040, 0x5 }, /* 16 */ + { 0x2e062064, 0x1000000 }, /* 25 */ + { 0x2e062068, 0xa000001 }, /* 26 */ + { 0x2e06206c, 0x28 }, /* 27 */ + { 0x2e062070, 0x1 }, /* 28 */ + { 0x2e062074, 0x320005 }, /* 29 */ + { 0x2e062080, 0x10102 }, /* 32 */ + { 0x2e062084, 0x1 }, /* 33 */ + { 0x2e062088, 0xaa }, /* 34 */ + { 0x2e06208c, 0x55 }, /* 35 */ + { 0x2e062090, 0xb5 }, /* 36 */ + { 0x2e062094, 0x4a }, /* 37 */ + { 0x2e062098, 0x56 }, /* 38 */ + { 0x2e06209c, 0xa9 }, /* 39 */ + { 0x2e0620a0, 0xa9 }, /* 40 */ + { 0x2e0620a4, 0xb5 }, /* 41 */ + { 0x2e0620a8, 0x10000 }, /* 42 */ + { 0x2e0620ac, 0x100 }, /* 43 */ + { 0x2e0620b0, 0x5050000 }, /* 44 */ + { 0x2e0620b4, 0x13 }, /* 45 */ + { 0x2e0620b8, 0x7d0 }, /* 46 */ + { 0x2e0620bc, 0x300 }, /* 47 */ + { 0x2e0620c8, 0x1000000 }, /* 50 */ + { 0x2e0620cc, 0x10101 }, /* 51 */ + { 0x2e0620d8, 0x10003 }, /* 54 */ + { 0x2e0620dc, 0x170500 }, /* 55 */ + { 0x2e0620ec, 0xa140a01 }, /* 59 */ + { 0x2e0620f0, 0x204010a }, /* 60 */ + { 0x2e0620f4, 0x21010 }, /* 61 */ + { 0x2e0620f8, 0x40401 }, /* 62 */ + { 0x2e0620fc, 0x10e0005 }, /* 63 */ + { 0x2e062100, 0x5000001 }, /* 64 */ + { 0x2e062104, 0x204 }, /* 65 */ + { 0x2e062108, 0x34 }, /* 66 */ + { 0x2e062114, 0x1000000 }, /* 69 */ + { 0x2e062118, 0x1000000 }, /* 70 */ + { 0x2e06211c, 0x80200 }, /* 71 */ + { 0x2e062120, 0x2000200 }, /* 72 */ + { 0x2e062124, 0x1000100 }, /* 73 */ + { 0x2e062128, 0x1000000 }, /* 74 */ + { 0x2e06212c, 0x2000200 }, /* 75 */ + { 0x2e062130, 0x200 }, /* 76 */ + { 0x2e062164, 0x400 }, /* 89 */ + { 0x2e062168, 0x2010000 }, /* 90 */ + { 0x2e06216c, 0x80103 }, /* 91 */ + { 0x2e062174, 0x10008 }, /* 93 */ + { 0x2e06217c, 0xaa00 }, /* 95 */ + { 0x2e062188, 0x10000 }, /* 98 */ + { 0x2e0621ec, 0x8 }, /* 123 */ + { 0x2e062218, 0xf0000 }, /* 134 */ + { 0x2e06221c, 0xa }, /* 135 */ + { 0x2e062220, 0x19 }, /* 136 */ + { 0x2e062224, 0x100 }, /* 137 */ + { 0x2e062228, 0x100 }, /* 138 */ + { 0x2e062238, 0x1000000 }, /* 142 */ + { 0x2e06223c, 0x10003 }, /* 143 */ + { 0x2e062240, 0x2000101 }, /* 144 */ + { 0x2e062244, 0x1030001 }, /* 145 */ + { 0x2e062248, 0x10400 }, /* 146 */ + { 0x2e06224c, 0x6000105 }, /* 147 */ + { 0x2e062250, 0x1070001 }, /* 148 */ + { 0x2e062260, 0x10001 }, /* 152 */ + { 0x2e062274, 0x401 }, /* 157 */ + { 0x2e06227c, 0x10000 }, /* 159 */ + { 0x2e062284, 0x2010000 }, /* 161 */ + { 0x2e062288, 0xb }, /* 162 */ + { 0x2e06228c, 0x34 }, /* 163 */ + { 0x2e062290, 0x34 }, /* 164 */ + { 0x2e062294, 0x2003c }, /* 165 */ + { 0x2e062298, 0x2000200 }, /* 166 */ + { 0x2e06229c, 0xc040c04 }, /* 167 */ + { 0x2e0622a0, 0xe1406 }, /* 168 */ + { 0x2e0622a4, 0xb3 }, /* 169 */ + { 0x2e0622a8, 0x1b }, /* 170 */ + { 0x2e0622ac, 0x16e }, /* 171 */ + { 0x2e0622b0, 0x94 }, /* 172 */ + { 0x2e0622b4, 0x4000803 }, /* 173 */ + { 0x2e0622b8, 0x1010404 }, /* 174 */ + { 0x2e0622bc, 0x1501 }, /* 175 */ + { 0x2e0622c0, 0x1a0016 }, /* 176 */ + { 0x2e0622c4, 0x1000100 }, /* 177 */ + { 0x2e0622c8, 0x100 }, /* 178 */ + { 0x2e0622d0, 0x5040303 }, /* 180 */ + { 0x2e0622d4, 0x1010805 }, /* 181 */ + { 0x2e0622d8, 0x1010101 }, /* 182 */ + { 0x2e0622e8, 0x2060404 }, /* 186 */ + { 0x2e0622ec, 0x2020402 }, /* 187 */ + { 0x2e0622f0, 0x3102 }, /* 188 */ + { 0x2e0622f4, 0x320009 }, /* 189 */ + { 0x2e0622f8, 0x36000a }, /* 190 */ + { 0x2e0622fc, 0x101000e }, /* 191 */ + { 0x2e062300, 0xd0101 }, /* 192 */ + { 0x2e062304, 0x1001801 }, /* 193 */ + { 0x2e062308, 0x1000084 }, /* 194 */ + { 0x2e06230c, 0xe000e }, /* 195 */ + { 0x2e062310, 0x190100 }, /* 196 */ + { 0x2e062314, 0x1000019 }, /* 197 */ + { 0x2e062318, 0x850085 }, /* 198 */ + { 0x2e06231c, 0x220f220f }, /* 199 */ + { 0x2e062320, 0x101220f }, /* 200 */ + { 0x2e062324, 0xa070601 }, /* 201 */ + { 0x2e062328, 0xa07060d }, /* 202 */ + { 0x2e06232c, 0xa07070d }, /* 203 */ + { 0x2e062330, 0xc00d }, /* 204 */ + { 0x2e062334, 0xc01000 }, /* 205 */ + { 0x2e062338, 0xc01000 }, /* 206 */ + { 0x2e06233c, 0x21000 }, /* 207 */ + { 0x2e062340, 0x2000d }, /* 208 */ + { 0x2e062344, 0x140018 }, /* 209 */ + { 0x2e062348, 0x190084 }, /* 210 */ + { 0x2e06234c, 0x220f0056 }, /* 211 */ + { 0x2e062350, 0x101 }, /* 212 */ + { 0x2e062354, 0x560019 }, /* 213 */ + { 0x2e062358, 0x101220f }, /* 214 */ + { 0x2e06235c, 0x1b00 }, /* 215 */ + { 0x2e062360, 0x220f0056 }, /* 216 */ + { 0x2e062364, 0x8000101 }, /* 217 */ + { 0x2e062368, 0x4090403 }, /* 218 */ + { 0x2e06236c, 0x5eb }, /* 219 */ + { 0x2e062370, 0x20010003 }, /* 220 */ + { 0x2e062374, 0x80a0a03 }, /* 221 */ + { 0x2e062378, 0x4090403 }, /* 222 */ + { 0x2e06237c, 0xbd8 }, /* 223 */ + { 0x2e062380, 0x20010005 }, /* 224 */ + { 0x2e062384, 0x80a0a03 }, /* 225 */ + { 0x2e062388, 0xb090a0c }, /* 226 */ + { 0x2e06238c, 0x4126 }, /* 227 */ + { 0x2e062390, 0x20020017 }, /* 228 */ + { 0x2e062394, 0xa0a08 }, /* 229 */ + { 0x2e062398, 0x166 }, /* 230 */ + { 0x2e06239c, 0xdfc }, /* 231 */ + { 0x2e0623a0, 0x2dc }, /* 232 */ + { 0x2e0623a4, 0x1c98 }, /* 233 */ + { 0x2e0623a8, 0x1006 }, /* 234 */ + { 0x2e0623ac, 0xa03c }, /* 235 */ + { 0x2e0623b0, 0x1c000e }, /* 236 */ + { 0x2e0623b4, 0x3030098 }, /* 237 */ + { 0x2e0623b8, 0x258103 }, /* 238 */ + { 0x2e0623bc, 0x17702 }, /* 239 */ + { 0x2e0623c0, 0x5 }, /* 240 */ + { 0x2e0623c4, 0x61 }, /* 241 */ + { 0x2e0623c8, 0xe }, /* 242 */ + { 0x2e0623cc, 0x4b00 }, /* 243 */ + { 0x2e0623d0, 0x17702 }, /* 244 */ + { 0x2e0623d4, 0x5 }, /* 245 */ + { 0x2e0623d8, 0xc0 }, /* 246 */ + { 0x2e0623dc, 0x1c }, /* 247 */ + { 0x2e0623e0, 0x19c7d }, /* 248 */ + { 0x2e0623e4, 0x17702 }, /* 249 */ + { 0x2e0623e8, 0x5 }, /* 250 */ + { 0x2e0623ec, 0x420 }, /* 251 */ + { 0x2e0623f0, 0x1000098 }, /* 252 */ + { 0x2e0623f4, 0x310040 }, /* 253 */ + { 0x2e0623f8, 0x10008 }, /* 254 */ + { 0x2e0623fc, 0x600040 }, /* 255 */ + { 0x2e062400, 0x10008 }, /* 256 */ + { 0x2e062404, 0x2100040 }, /* 257 */ + { 0x2e062408, 0x310 }, /* 258 */ + { 0x2e06240c, 0x1b000e }, /* 259 */ + { 0x2e062410, 0x1010101 }, /* 260 */ + { 0x2e062414, 0x2020101 }, /* 261 */ + { 0x2e062418, 0x8080404 }, /* 262 */ + { 0x2e06241c, 0x5508 }, /* 263 */ + { 0x2e062420, 0x83c5a00 }, /* 264 */ + { 0x2e062424, 0x55 }, /* 265 */ + { 0x2e062428, 0x55083c5a }, /* 266 */ + { 0x2e06242c, 0x5a000000 }, /* 267 */ + { 0x2e062430, 0x55083c }, /* 268 */ + { 0x2e062434, 0x3c5a0000 }, /* 269 */ + { 0x2e062438, 0xf0e0d0c }, /* 270 */ + { 0x2e06243c, 0xb0a0908 }, /* 271 */ + { 0x2e062440, 0x7060504 }, /* 272 */ + { 0x2e062444, 0x3020100 }, /* 273 */ + { 0x2e06244c, 0x2020101 }, /* 275 */ + { 0x2e062450, 0x8080404 }, /* 276 */ + { 0x2e062454, 0x44300004 }, /* 277 */ + { 0x2e062458, 0x4041919 }, /* 278 */ + { 0x2e06245c, 0x19443000 }, /* 279 */ + { 0x2e062460, 0x9140419 }, /* 280 */ + { 0x2e062464, 0x19194430 }, /* 281 */ + { 0x2e062468, 0x30000404 }, /* 282 */ + { 0x2e06246c, 0x4191944 }, /* 283 */ + { 0x2e062470, 0x44300004 }, /* 284 */ + { 0x2e062474, 0x14041919 }, /* 285 */ + { 0x2e062478, 0x19443009 }, /* 286 */ + { 0x2e06247c, 0x40419 }, /* 287 */ + { 0x2e062480, 0x19194430 }, /* 288 */ + { 0x2e062484, 0x30000404 }, /* 289 */ + { 0x2e062488, 0x4191944 }, /* 290 */ + { 0x2e06248c, 0x44300914 }, /* 291 */ + { 0x2e062490, 0x44041919 }, /* 292 */ + { 0x2e062494, 0x19443000 }, /* 293 */ + { 0x2e062498, 0x40419 }, /* 294 */ + { 0x2e06249c, 0x19194430 }, /* 295 */ + { 0x2e0624a0, 0x30091404 }, /* 296 */ + { 0x2e0624a4, 0x4191944 }, /* 297 */ +}; + +/** PHY_F1 settings **/ +struct dram_cfg_param ddr_phy_f1_cfg[] = { + { 0x2e064000, 0x4f0 }, /* 0 */ + { 0x2e064008, 0x1030200 }, /* 2 */ + { 0x2e064014, 0x3000000 }, /* 5 */ + { 0x2e064018, 0x1000001 }, /* 6 */ + { 0x2e06401c, 0x3000400 }, /* 7 */ + { 0x2e064020, 0x1 }, /* 8 */ + { 0x2e064024, 0x1 }, /* 9 */ + { 0x2e064030, 0x10000 }, /* 12 */ + { 0x2e064038, 0xc00004 }, /* 14 */ + { 0x2e06403c, 0xcc0008 }, /* 15 */ + { 0x2e064040, 0x660601 }, /* 16 */ + { 0x2e064044, 0x3 }, /* 17 */ + { 0x2e06404c, 0x1 }, /* 19 */ + { 0x2e064050, 0xaaaa }, /* 20 */ + { 0x2e064054, 0x5555 }, /* 21 */ + { 0x2e064058, 0xb5b5 }, /* 22 */ + { 0x2e06405c, 0x4a4a }, /* 23 */ + { 0x2e064060, 0x5656 }, /* 24 */ + { 0x2e064064, 0xa9a9 }, /* 25 */ + { 0x2e064068, 0xb7b7 }, /* 26 */ + { 0x2e06406c, 0x4848 }, /* 27 */ + { 0x2e064078, 0x8000000 }, /* 30 */ + { 0x2e06407c, 0x4010008 }, /* 31 */ + { 0x2e064080, 0x408 }, /* 32 */ + { 0x2e064084, 0x3102000 }, /* 33 */ + { 0x2e064088, 0xc0020 }, /* 34 */ + { 0x2e06408c, 0x10000 }, /* 35 */ + { 0x2e064090, 0x55555555 }, /* 36 */ + { 0x2e064094, 0xaaaaaaaa }, /* 37 */ + { 0x2e064098, 0x55555555 }, /* 38 */ + { 0x2e06409c, 0xaaaaaaaa }, /* 39 */ + { 0x2e0640a0, 0x5555 }, /* 40 */ + { 0x2e0640a4, 0x1000100 }, /* 41 */ + { 0x2e0640a8, 0x800180 }, /* 42 */ + { 0x2e0640ac, 0x1 }, /* 43 */ + { 0x2e064100, 0x4 }, /* 64 */ + { 0x2e06411c, 0x41f07ff }, /* 71 */ + { 0x2e064120, 0x1 }, /* 72 */ + { 0x2e064124, 0x1cc0800 }, /* 73 */ + { 0x2e064128, 0x3003cc08 }, /* 74 */ + { 0x2e06412c, 0x2000014e }, /* 75 */ + { 0x2e064130, 0x7ff0200 }, /* 76 */ + { 0x2e064134, 0x301 }, /* 77 */ + { 0x2e064140, 0x30000 }, /* 80 */ + { 0x2e064154, 0x2000000 }, /* 85 */ + { 0x2e064158, 0x51515042 }, /* 86 */ + { 0x2e06415c, 0x31c06000 }, /* 87 */ + { 0x2e064160, 0x6bf000a }, /* 88 */ + { 0x2e064164, 0xc0c000 }, /* 89 */ + { 0x2e064168, 0x1000000 }, /* 90 */ + { 0x2e06416c, 0x10001000 }, /* 91 */ + { 0x2e064170, 0xc043242 }, /* 92 */ + { 0x2e064174, 0xf0c0e01 }, /* 93 */ + { 0x2e064178, 0x1000140 }, /* 94 */ + { 0x2e06417c, 0xc000120 }, /* 95 */ + { 0x2e064180, 0x118 }, /* 96 */ + { 0x2e064184, 0x1000203 }, /* 97 */ + { 0x2e064188, 0x56417032 }, /* 98 */ + { 0x2e06418c, 0x8 }, /* 99 */ + { 0x2e064190, 0x2980298 }, /* 100 */ + { 0x2e064194, 0x2980298 }, /* 101 */ + { 0x2e064198, 0x2980298 }, /* 102 */ + { 0x2e06419c, 0x2980298 }, /* 103 */ + { 0x2e0641a0, 0x298 }, /* 104 */ + { 0x2e0641a4, 0x8000 }, /* 105 */ + { 0x2e0641a8, 0x800080 }, /* 106 */ + { 0x2e0641ac, 0x800080 }, /* 107 */ + { 0x2e0641b0, 0x800080 }, /* 108 */ + { 0x2e0641b4, 0x800080 }, /* 109 */ + { 0x2e0641b8, 0x800080 }, /* 110 */ + { 0x2e0641bc, 0x800080 }, /* 111 */ + { 0x2e0641c0, 0x800080 }, /* 112 */ + { 0x2e0641c4, 0x800080 }, /* 113 */ + { 0x2e0641c8, 0x1940080 }, /* 114 */ + { 0x2e0641cc, 0x1a00001 }, /* 115 */ + { 0x2e0641d4, 0x10000 }, /* 117 */ + { 0x2e0641d8, 0x80200 }, /* 118 */ + { 0x2e064400, 0x4f0 }, /* 256 */ + { 0x2e064408, 0x1030200 }, /* 258 */ + { 0x2e064414, 0x3000000 }, /* 261 */ + { 0x2e064418, 0x1000001 }, /* 262 */ + { 0x2e06441c, 0x3000400 }, /* 263 */ + { 0x2e064420, 0x1 }, /* 264 */ + { 0x2e064424, 0x1 }, /* 265 */ + { 0x2e064430, 0x10000 }, /* 268 */ + { 0x2e064438, 0xc00004 }, /* 270 */ + { 0x2e06443c, 0xcc0008 }, /* 271 */ + { 0x2e064440, 0x660601 }, /* 272 */ + { 0x2e064444, 0x3 }, /* 273 */ + { 0x2e06444c, 0x1 }, /* 275 */ + { 0x2e064450, 0xaaaa }, /* 276 */ + { 0x2e064454, 0x5555 }, /* 277 */ + { 0x2e064458, 0xb5b5 }, /* 278 */ + { 0x2e06445c, 0x4a4a }, /* 279 */ + { 0x2e064460, 0x5656 }, /* 280 */ + { 0x2e064464, 0xa9a9 }, /* 281 */ + { 0x2e064468, 0xb7b7 }, /* 282 */ + { 0x2e06446c, 0x4848 }, /* 283 */ + { 0x2e064478, 0x8000000 }, /* 286 */ + { 0x2e06447c, 0x4010008 }, /* 287 */ + { 0x2e064480, 0x408 }, /* 288 */ + { 0x2e064484, 0x3102000 }, /* 289 */ + { 0x2e064488, 0xc0020 }, /* 290 */ + { 0x2e06448c, 0x10000 }, /* 291 */ + { 0x2e064490, 0x55555555 }, /* 292 */ + { 0x2e064494, 0xaaaaaaaa }, /* 293 */ + { 0x2e064498, 0x55555555 }, /* 294 */ + { 0x2e06449c, 0xaaaaaaaa }, /* 295 */ + { 0x2e0644a0, 0x5555 }, /* 296 */ + { 0x2e0644a4, 0x1000100 }, /* 297 */ + { 0x2e0644a8, 0x800180 }, /* 298 */ + { 0x2e064500, 0x4 }, /* 320 */ + { 0x2e06451c, 0x41f07ff }, /* 327 */ + { 0x2e064520, 0x1 }, /* 328 */ + { 0x2e064524, 0x1cc0800 }, /* 329 */ + { 0x2e064528, 0x3003cc08 }, /* 330 */ + { 0x2e06452c, 0x2000014e }, /* 331 */ + { 0x2e064530, 0x7ff0200 }, /* 332 */ + { 0x2e064534, 0x301 }, /* 333 */ + { 0x2e064540, 0x30000 }, /* 336 */ + { 0x2e064554, 0x2000000 }, /* 341 */ + { 0x2e064558, 0x51515042 }, /* 342 */ + { 0x2e06455c, 0x31c06000 }, /* 343 */ + { 0x2e064560, 0x6bf000a }, /* 344 */ + { 0x2e064564, 0xc0c000 }, /* 345 */ + { 0x2e064568, 0x1000000 }, /* 346 */ + { 0x2e06456c, 0x10001000 }, /* 347 */ + { 0x2e064570, 0xc043242 }, /* 348 */ + { 0x2e064574, 0xf0c0e01 }, /* 349 */ + { 0x2e064578, 0x1000140 }, /* 350 */ + { 0x2e06457c, 0xc000120 }, /* 351 */ + { 0x2e064580, 0x118 }, /* 352 */ + { 0x2e064584, 0x1000203 }, /* 353 */ + { 0x2e064588, 0x30217465 }, /* 354 */ + { 0x2e06458c, 0x8 }, /* 355 */ + { 0x2e064590, 0x2980298 }, /* 356 */ + { 0x2e064594, 0x2980298 }, /* 357 */ + { 0x2e064598, 0x2980298 }, /* 358 */ + { 0x2e06459c, 0x2980298 }, /* 359 */ + { 0x2e0645a0, 0x298 }, /* 360 */ + { 0x2e0645a4, 0x8000 }, /* 361 */ + { 0x2e0645a8, 0x800080 }, /* 362 */ + { 0x2e0645ac, 0x800080 }, /* 363 */ + { 0x2e0645b0, 0x800080 }, /* 364 */ + { 0x2e0645b4, 0x800080 }, /* 365 */ + { 0x2e0645b8, 0x800080 }, /* 366 */ + { 0x2e0645bc, 0x800080 }, /* 367 */ + { 0x2e0645c0, 0x800080 }, /* 368 */ + { 0x2e0645c4, 0x800080 }, /* 369 */ + { 0x2e0645c8, 0x1940080 }, /* 370 */ + { 0x2e0645cc, 0x1a00001 }, /* 371 */ + { 0x2e0645d4, 0x10000 }, /* 373 */ + { 0x2e0645d8, 0x80200 }, /* 374 */ + { 0x2e064800, 0x4f0 }, /* 512 */ + { 0x2e064808, 0x1030200 }, /* 514 */ + { 0x2e064814, 0x3000000 }, /* 517 */ + { 0x2e064818, 0x1000001 }, /* 518 */ + { 0x2e06481c, 0x3000400 }, /* 519 */ + { 0x2e064820, 0x1 }, /* 520 */ + { 0x2e064824, 0x1 }, /* 521 */ + { 0x2e064830, 0x10000 }, /* 524 */ + { 0x2e064838, 0xc00004 }, /* 526 */ + { 0x2e06483c, 0xcc0008 }, /* 527 */ + { 0x2e064840, 0x660601 }, /* 528 */ + { 0x2e064844, 0x3 }, /* 529 */ + { 0x2e06484c, 0x1 }, /* 531 */ + { 0x2e064850, 0xaaaa }, /* 532 */ + { 0x2e064854, 0x5555 }, /* 533 */ + { 0x2e064858, 0xb5b5 }, /* 534 */ + { 0x2e06485c, 0x4a4a }, /* 535 */ + { 0x2e064860, 0x5656 }, /* 536 */ + { 0x2e064864, 0xa9a9 }, /* 537 */ + { 0x2e064868, 0xb7b7 }, /* 538 */ + { 0x2e06486c, 0x4848 }, /* 539 */ + { 0x2e064878, 0x8000000 }, /* 542 */ + { 0x2e06487c, 0x4010008 }, /* 543 */ + { 0x2e064880, 0x408 }, /* 544 */ + { 0x2e064884, 0x3102000 }, /* 545 */ + { 0x2e064888, 0xc0020 }, /* 546 */ + { 0x2e06488c, 0x10000 }, /* 547 */ + { 0x2e064890, 0x55555555 }, /* 548 */ + { 0x2e064894, 0xaaaaaaaa }, /* 549 */ + { 0x2e064898, 0x55555555 }, /* 550 */ + { 0x2e06489c, 0xaaaaaaaa }, /* 551 */ + { 0x2e0648a0, 0x5555 }, /* 552 */ + { 0x2e0648a4, 0x1000100 }, /* 553 */ + { 0x2e0648a8, 0x800180 }, /* 554 */ + { 0x2e0648ac, 0x1 }, /* 555 */ + { 0x2e064900, 0x4 }, /* 576 */ + { 0x2e06491c, 0x41f07ff }, /* 583 */ + { 0x2e064920, 0x1 }, /* 584 */ + { 0x2e064924, 0x1cc0800 }, /* 585 */ + { 0x2e064928, 0x3003cc08 }, /* 586 */ + { 0x2e06492c, 0x2000014e }, /* 587 */ + { 0x2e064930, 0x7ff0200 }, /* 588 */ + { 0x2e064934, 0x301 }, /* 589 */ + { 0x2e064940, 0x30000 }, /* 592 */ + { 0x2e064954, 0x2000000 }, /* 597 */ + { 0x2e064958, 0x51515042 }, /* 598 */ + { 0x2e06495c, 0x31c06000 }, /* 599 */ + { 0x2e064960, 0x6bf000a }, /* 600 */ + { 0x2e064964, 0xc0c000 }, /* 601 */ + { 0x2e064968, 0x1000000 }, /* 602 */ + { 0x2e06496c, 0x10001000 }, /* 603 */ + { 0x2e064970, 0xc043242 }, /* 604 */ + { 0x2e064974, 0xf0c0e01 }, /* 605 */ + { 0x2e064978, 0x1000140 }, /* 606 */ + { 0x2e06497c, 0xc000120 }, /* 607 */ + { 0x2e064980, 0x118 }, /* 608 */ + { 0x2e064984, 0x1000203 }, /* 609 */ + { 0x2e064988, 0x75436012 }, /* 610 */ + { 0x2e06498c, 0x8 }, /* 611 */ + { 0x2e064990, 0x2980298 }, /* 612 */ + { 0x2e064994, 0x2980298 }, /* 613 */ + { 0x2e064998, 0x2980298 }, /* 614 */ + { 0x2e06499c, 0x2980298 }, /* 615 */ + { 0x2e0649a0, 0x298 }, /* 616 */ + { 0x2e0649a4, 0x8000 }, /* 617 */ + { 0x2e0649a8, 0x800080 }, /* 618 */ + { 0x2e0649ac, 0x800080 }, /* 619 */ + { 0x2e0649b0, 0x800080 }, /* 620 */ + { 0x2e0649b4, 0x800080 }, /* 621 */ + { 0x2e0649b8, 0x800080 }, /* 622 */ + { 0x2e0649bc, 0x800080 }, /* 623 */ + { 0x2e0649c0, 0x800080 }, /* 624 */ + { 0x2e0649c4, 0x800080 }, /* 625 */ + { 0x2e0649c8, 0x1940080 }, /* 626 */ + { 0x2e0649cc, 0x1a00001 }, /* 627 */ + { 0x2e0649d4, 0x10000 }, /* 629 */ + { 0x2e0649d8, 0x80200 }, /* 630 */ + { 0x2e064c00, 0x4f0 }, /* 768 */ + { 0x2e064c08, 0x1030200 }, /* 770 */ + { 0x2e064c14, 0x3000000 }, /* 773 */ + { 0x2e064c18, 0x1000001 }, /* 774 */ + { 0x2e064c1c, 0x3000400 }, /* 775 */ + { 0x2e064c20, 0x1 }, /* 776 */ + { 0x2e064c24, 0x1 }, /* 777 */ + { 0x2e064c30, 0x10000 }, /* 780 */ + { 0x2e064c38, 0xc00004 }, /* 782 */ + { 0x2e064c3c, 0xcc0008 }, /* 783 */ + { 0x2e064c40, 0x660601 }, /* 784 */ + { 0x2e064c44, 0x3 }, /* 785 */ + { 0x2e064c4c, 0x1 }, /* 787 */ + { 0x2e064c50, 0xaaaa }, /* 788 */ + { 0x2e064c54, 0x5555 }, /* 789 */ + { 0x2e064c58, 0xb5b5 }, /* 790 */ + { 0x2e064c5c, 0x4a4a }, /* 791 */ + { 0x2e064c60, 0x5656 }, /* 792 */ + { 0x2e064c64, 0xa9a9 }, /* 793 */ + { 0x2e064c68, 0xb7b7 }, /* 794 */ + { 0x2e064c6c, 0x4848 }, /* 795 */ + { 0x2e064c78, 0x8000000 }, /* 798 */ + { 0x2e064c7c, 0x4010008 }, /* 799 */ + { 0x2e064c80, 0x408 }, /* 800 */ + { 0x2e064c84, 0x3102000 }, /* 801 */ + { 0x2e064c88, 0xc0020 }, /* 802 */ + { 0x2e064c8c, 0x10000 }, /* 803 */ + { 0x2e064c90, 0x55555555 }, /* 804 */ + { 0x2e064c94, 0xaaaaaaaa }, /* 805 */ + { 0x2e064c98, 0x55555555 }, /* 806 */ + { 0x2e064c9c, 0xaaaaaaaa }, /* 807 */ + { 0x2e064ca0, 0x5555 }, /* 808 */ + { 0x2e064ca4, 0x1000100 }, /* 809 */ + { 0x2e064ca8, 0x800180 }, /* 810 */ + { 0x2e064d00, 0x4 }, /* 832 */ + { 0x2e064d1c, 0x41f07ff }, /* 839 */ + { 0x2e064d20, 0x1 }, /* 840 */ + { 0x2e064d24, 0x1cc0800 }, /* 841 */ + { 0x2e064d28, 0x3003cc08 }, /* 842 */ + { 0x2e064d2c, 0x2000014e }, /* 843 */ + { 0x2e064d30, 0x7ff0200 }, /* 844 */ + { 0x2e064d34, 0x301 }, /* 845 */ + { 0x2e064d40, 0x30000 }, /* 848 */ + { 0x2e064d54, 0x2000000 }, /* 853 */ + { 0x2e064d58, 0x51515042 }, /* 854 */ + { 0x2e064d5c, 0x31c06000 }, /* 855 */ + { 0x2e064d60, 0x6bf000a }, /* 856 */ + { 0x2e064d64, 0xc0c000 }, /* 857 */ + { 0x2e064d68, 0x1000000 }, /* 858 */ + { 0x2e064d6c, 0x10001000 }, /* 859 */ + { 0x2e064d70, 0xc043242 }, /* 860 */ + { 0x2e064d74, 0xf0c0e01 }, /* 861 */ + { 0x2e064d78, 0x1000140 }, /* 862 */ + { 0x2e064d7c, 0xc000120 }, /* 863 */ + { 0x2e064d80, 0x118 }, /* 864 */ + { 0x2e064d84, 0x1000203 }, /* 865 */ + { 0x2e064d88, 0x32017465 }, /* 866 */ + { 0x2e064d8c, 0x8 }, /* 867 */ + { 0x2e064d90, 0x2980298 }, /* 868 */ + { 0x2e064d94, 0x2980298 }, /* 869 */ + { 0x2e064d98, 0x2980298 }, /* 870 */ + { 0x2e064d9c, 0x2980298 }, /* 871 */ + { 0x2e064da0, 0x298 }, /* 872 */ + { 0x2e064da4, 0x8000 }, /* 873 */ + { 0x2e064da8, 0x800080 }, /* 874 */ + { 0x2e064dac, 0x800080 }, /* 875 */ + { 0x2e064db0, 0x800080 }, /* 876 */ + { 0x2e064db4, 0x800080 }, /* 877 */ + { 0x2e064db8, 0x800080 }, /* 878 */ + { 0x2e064dbc, 0x800080 }, /* 879 */ + { 0x2e064dc0, 0x800080 }, /* 880 */ + { 0x2e064dc4, 0x800080 }, /* 881 */ + { 0x2e064dc8, 0x1940080 }, /* 882 */ + { 0x2e064dcc, 0x1a00001 }, /* 883 */ + { 0x2e064dd4, 0x10000 }, /* 885 */ + { 0x2e064dd8, 0x80200 }, /* 886 */ + { 0x2e065014, 0x100 }, /* 1029 */ + { 0x2e065018, 0x201 }, /* 1030 */ + { 0x2e06502c, 0x400000 }, /* 1035 */ + { 0x2e065030, 0x80 }, /* 1036 */ + { 0x2e065034, 0xdcba98 }, /* 1037 */ + { 0x2e065038, 0x3000000 }, /* 1038 */ + { 0x2e06504c, 0x2a }, /* 1043 */ + { 0x2e065050, 0x15 }, /* 1044 */ + { 0x2e065054, 0x15 }, /* 1045 */ + { 0x2e065058, 0x2a }, /* 1046 */ + { 0x2e06505c, 0x33 }, /* 1047 */ + { 0x2e065060, 0xc }, /* 1048 */ + { 0x2e065064, 0xc }, /* 1049 */ + { 0x2e065068, 0x33 }, /* 1050 */ + { 0x2e06506c, 0x543210 }, /* 1051 */ + { 0x2e065070, 0x3f0000 }, /* 1052 */ + { 0x2e065074, 0xf013f }, /* 1053 */ + { 0x2e065078, 0xf }, /* 1054 */ + { 0x2e06507c, 0x3cc }, /* 1055 */ + { 0x2e065080, 0x30000 }, /* 1056 */ + { 0x2e065084, 0x300 }, /* 1057 */ + { 0x2e065088, 0x300 }, /* 1058 */ + { 0x2e06508c, 0x300 }, /* 1059 */ + { 0x2e065090, 0x300 }, /* 1060 */ + { 0x2e065094, 0x300 }, /* 1061 */ + { 0x2e065098, 0x42080010 }, /* 1062 */ + { 0x2e06509c, 0x332 }, /* 1063 */ + { 0x2e0650a0, 0x2 }, /* 1064 */ + { 0x2e065414, 0x100 }, /* 1285 */ + { 0x2e065418, 0x201 }, /* 1286 */ + { 0x2e06542c, 0x400000 }, /* 1291 */ + { 0x2e065430, 0x80 }, /* 1292 */ + { 0x2e065434, 0xdcba98 }, /* 1293 */ + { 0x2e065438, 0x3000000 }, /* 1294 */ + { 0x2e06544c, 0x2a }, /* 1299 */ + { 0x2e065450, 0x15 }, /* 1300 */ + { 0x2e065454, 0x15 }, /* 1301 */ + { 0x2e065458, 0x2a }, /* 1302 */ + { 0x2e06545c, 0x33 }, /* 1303 */ + { 0x2e065460, 0xc }, /* 1304 */ + { 0x2e065464, 0xc }, /* 1305 */ + { 0x2e065468, 0x33 }, /* 1306 */ + { 0x2e06546c, 0x543210 }, /* 1307 */ + { 0x2e065470, 0x3f0000 }, /* 1308 */ + { 0x2e065474, 0xf013f }, /* 1309 */ + { 0x2e065478, 0xf }, /* 1310 */ + { 0x2e06547c, 0x3cc }, /* 1311 */ + { 0x2e065480, 0x30000 }, /* 1312 */ + { 0x2e065484, 0x300 }, /* 1313 */ + { 0x2e065488, 0x300 }, /* 1314 */ + { 0x2e06548c, 0x300 }, /* 1315 */ + { 0x2e065490, 0x300 }, /* 1316 */ + { 0x2e065494, 0x300 }, /* 1317 */ + { 0x2e065498, 0x42080010 }, /* 1318 */ + { 0x2e06549c, 0x332 }, /* 1319 */ + { 0x2e0654a0, 0x2 }, /* 1320 */ + { 0x2e065804, 0x100 }, /* 1537 */ + { 0x2e065814, 0x50000 }, /* 1541 */ + { 0x2e065818, 0x4000100 }, /* 1542 */ + { 0x2e06581c, 0x55 }, /* 1543 */ + { 0x2e06582c, 0xf0001 }, /* 1547 */ + { 0x2e065830, 0x280040 }, /* 1548 */ + { 0x2e065834, 0x5002 }, /* 1549 */ + { 0x2e065838, 0x10101 }, /* 1550 */ + { 0x2e065840, 0x90e0000 }, /* 1552 */ + { 0x2e065844, 0x101010f }, /* 1553 */ + { 0x2e065848, 0x10f0004 }, /* 1554 */ + { 0x2e065854, 0x64 }, /* 1557 */ + { 0x2e06585c, 0x1000000 }, /* 1559 */ + { 0x2e065860, 0x8040201 }, /* 1560 */ + { 0x2e065864, 0x2010201 }, /* 1561 */ + { 0x2e065868, 0xf0f0f }, /* 1562 */ + { 0x2e06586c, 0x241342 }, /* 1563 */ + { 0x2e065874, 0x1020000 }, /* 1565 */ + { 0x2e065878, 0x10701 }, /* 1566 */ + { 0x2e06587c, 0x54 }, /* 1567 */ + { 0x2e065880, 0x4102000 }, /* 1568 */ + { 0x2e065884, 0x24410 }, /* 1569 */ + { 0x2e065888, 0x4410 }, /* 1570 */ + { 0x2e06588c, 0x4410 }, /* 1571 */ + { 0x2e065890, 0x4410 }, /* 1572 */ + { 0x2e065894, 0x4410 }, /* 1573 */ + { 0x2e065898, 0x4410 }, /* 1574 */ + { 0x2e06589c, 0x4410 }, /* 1575 */ + { 0x2e0658a0, 0x4410 }, /* 1576 */ + { 0x2e0658a4, 0x4410 }, /* 1577 */ + { 0x2e0658b0, 0x60000 }, /* 1580 */ + { 0x2e0658b8, 0x64 }, /* 1582 */ + { 0x2e0658bc, 0x10000 }, /* 1583 */ + { 0x2e0658c0, 0x8 }, /* 1584 */ + { 0x2e0658d8, 0x3000000 }, /* 1590 */ + { 0x2e0658e8, 0x4102006 }, /* 1594 */ + { 0x2e0658ec, 0x41020 }, /* 1595 */ + { 0x2e0658f0, 0x1c98c98 }, /* 1596 */ + { 0x2e0658f4, 0x3f400000 }, /* 1597 */ + { 0x2e0658f8, 0x3f3f1f3f }, /* 1598 */ + { 0x2e0658fc, 0x1f }, /* 1599 */ + { 0x2e06590c, 0x1 }, /* 1603 */ + { 0x2e06591c, 0x1 }, /* 1607 */ + { 0x2e065920, 0x76543210 }, /* 1608 */ + { 0x2e065924, 0x10198 }, /* 1609 */ + { 0x2e065934, 0x40700 }, /* 1613 */ + { 0x2e06594c, 0x2 }, /* 1619 */ + { 0x2e065958, 0xf3c3 }, /* 1622 */ + { 0x2e065964, 0x11742 }, /* 1625 */ + { 0x2e065968, 0x3020600 }, /* 1626 */ + { 0x2e06596c, 0x30000 }, /* 1627 */ + { 0x2e065970, 0x3000300 }, /* 1628 */ + { 0x2e065974, 0x3000300 }, /* 1629 */ + { 0x2e065978, 0x3000300 }, /* 1630 */ + { 0x2e06597c, 0x3000300 }, /* 1631 */ + { 0x2e065980, 0x300 }, /* 1632 */ + { 0x2e065984, 0x300 }, /* 1633 */ + { 0x2e065988, 0x300 }, /* 1634 */ + { 0x2e06598c, 0x337cc }, /* 1635 */ + { 0x2e065990, 0x8 }, /* 1636 */ + { 0x2e065994, 0x1b7 }, /* 1637 */ + { 0x2e06599c, 0x1b7 }, /* 1639 */ + { 0x2e0659a4, 0x1b700 }, /* 1641 */ + { 0x2e0659a8, 0x1980000 }, /* 1642 */ + { 0x2e0659ac, 0x1b7cc }, /* 1643 */ + { 0x2e0659b4, 0x1b700 }, /* 1645 */ + { 0x2e0659b8, 0x1980000 }, /* 1646 */ + { 0x2e0659bc, 0x1b700 }, /* 1647 */ + { 0x2e0659c0, 0x1980000 }, /* 1648 */ + { 0x2e0659c4, 0x1b700 }, /* 1649 */ + { 0x2e0659c8, 0x1980000 }, /* 1650 */ + { 0x2e0659cc, 0x1b700 }, /* 1651 */ + { 0x2e0659d0, 0x1980000 }, /* 1652 */ + { 0x2e0659d4, 0x20040003 }, /* 1653 */ +}; + +/** PHY_F2 settings **/ +struct dram_cfg_param ddr_phy_f2_cfg[] = { + { 0x2e064168, 0x3020000 }, /* 90 */ + { 0x2e064170, 0xc043e42 }, /* 92 */ + { 0x2e064174, 0xf0c1701 }, /* 93 */ + { 0x2e064180, 0x187 }, /* 96 */ + { 0x2e064184, 0x3200203 }, /* 97 */ + { 0x2e064190, 0x3070307 }, /* 100 */ + { 0x2e064194, 0x3070307 }, /* 101 */ + { 0x2e064198, 0x3070307 }, /* 102 */ + { 0x2e06419c, 0x3070307 }, /* 103 */ + { 0x2e0641a0, 0x307 }, /* 104 */ + { 0x2e0641c8, 0x1bd0080 }, /* 114 */ + { 0x2e064568, 0x3020000 }, /* 346 */ + { 0x2e064570, 0xc043e42 }, /* 348 */ + { 0x2e064574, 0xf0c1701 }, /* 349 */ + { 0x2e064580, 0x187 }, /* 352 */ + { 0x2e064584, 0x3200203 }, /* 353 */ + { 0x2e064590, 0x3070307 }, /* 356 */ + { 0x2e064594, 0x3070307 }, /* 357 */ + { 0x2e064598, 0x3070307 }, /* 358 */ + { 0x2e06459c, 0x3070307 }, /* 359 */ + { 0x2e0645a0, 0x307 }, /* 360 */ + { 0x2e0645c8, 0x1bd0080 }, /* 370 */ + { 0x2e064968, 0x3020000 }, /* 602 */ + { 0x2e064970, 0xc043e42 }, /* 604 */ + { 0x2e064974, 0xf0c1701 }, /* 605 */ + { 0x2e064980, 0x187 }, /* 608 */ + { 0x2e064984, 0x3200203 }, /* 609 */ + { 0x2e064990, 0x3070307 }, /* 612 */ + { 0x2e064994, 0x3070307 }, /* 613 */ + { 0x2e064998, 0x3070307 }, /* 614 */ + { 0x2e06499c, 0x3070307 }, /* 615 */ + { 0x2e0649a0, 0x307 }, /* 616 */ + { 0x2e0649c8, 0x1bd0080 }, /* 626 */ + { 0x2e064d68, 0x3020000 }, /* 858 */ + { 0x2e064d70, 0xc043e42 }, /* 860 */ + { 0x2e064d74, 0xf0c1701 }, /* 861 */ + { 0x2e064d80, 0x187 }, /* 864 */ + { 0x2e064d84, 0x3200203 }, /* 865 */ + { 0x2e064d90, 0x3070307 }, /* 868 */ + { 0x2e064d94, 0x3070307 }, /* 869 */ + { 0x2e064d98, 0x3070307 }, /* 870 */ + { 0x2e064d9c, 0x3070307 }, /* 871 */ + { 0x2e064da0, 0x307 }, /* 872 */ + { 0x2e064dc8, 0x1bd0080 }, /* 882 */ + { 0x2e06509c, 0x33e }, /* 1063 */ + { 0x2e06549c, 0x33e }, /* 1319 */ + { 0x2e065878, 0x10703 }, /* 1566 */ + { 0x2e065964, 0x1342 }, /* 1625 */ +}; + +/* ddr timing config params */ +struct dram_timing_info2 dram_timing = { + .ctl_cfg = ddr_ctl_cfg, + .ctl_cfg_num = ARRAY_SIZE(ddr_ctl_cfg), + .pi_cfg = ddr_pi_cfg, + .pi_cfg_num = ARRAY_SIZE(ddr_pi_cfg), + .phy_f1_cfg = ddr_phy_f1_cfg, + .phy_f1_cfg_num = ARRAY_SIZE(ddr_phy_f1_cfg), + .phy_f2_cfg = ddr_phy_f2_cfg, + .phy_f2_cfg_num = ARRAY_SIZE(ddr_phy_f2_cfg), + .fsp_table = { 96, 192, 1056 }, +}; diff --git a/board/nxp/imx8ulp_evk/lpddr4_timing_266.c b/board/nxp/imx8ulp_evk/lpddr4_timing_266.c new file mode 100644 index 00000000000..79457601461 --- /dev/null +++ b/board/nxp/imx8ulp_evk/lpddr4_timing_266.c @@ -0,0 +1,1109 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2021 NXP + * + * Generated code from MX8ULP_DDR_tool + */ + +#include +#include + +/** CTL settings **/ +struct dram_cfg_param ddr_ctl_cfg[] = { + { 0x2e060000, 0xb00 }, /* 0 */ + { 0x2e060028, 0x258100 }, /* 10 */ + { 0x2e06002c, 0x17702 }, /* 11 */ + { 0x2e060030, 0x5 }, /* 12 */ + { 0x2e060034, 0x61 }, /* 13 */ + { 0x2e060038, 0xce3f }, /* 14 */ + { 0x2e06003c, 0x80e70 }, /* 15 */ + { 0x2e060040, 0x5 }, /* 16 */ + { 0x2e060044, 0x210 }, /* 17 */ + { 0x2e060048, 0x19c7d }, /* 18 */ + { 0x2e06004c, 0x101cdf }, /* 19 */ + { 0x2e060050, 0x5 }, /* 20 */ + { 0x2e060054, 0x420 }, /* 21 */ + { 0x2e060058, 0x1010000 }, /* 22 */ + { 0x2e06005c, 0x1011001 }, /* 23 */ + { 0x2e060060, 0x10000 }, /* 24 */ + { 0x2e060064, 0x102 }, /* 25 */ + { 0x2e060068, 0xa }, /* 26 */ + { 0x2e06006c, 0x19 }, /* 27 */ + { 0x2e060078, 0x2020200 }, /* 30 */ + { 0x2e06007c, 0x160b }, /* 31 */ + { 0x2e060090, 0x10 }, /* 36 */ + { 0x2e0600a4, 0x40c040c }, /* 41 */ + { 0x2e0600a8, 0x8040614 }, /* 42 */ + { 0x2e0600ac, 0x604 }, /* 43 */ + { 0x2e0600b0, 0x3090003 }, /* 44 */ + { 0x2e0600b4, 0x40002 }, /* 45 */ + { 0x2e0600b8, 0xc0011 }, /* 46 */ + { 0x2e0600bc, 0xb0509 }, /* 47 */ + { 0x2e0600c0, 0x2106 }, /* 48 */ + { 0x2e0600c4, 0xa090017 }, /* 49 */ + { 0x2e0600c8, 0x8200016 }, /* 50 */ + { 0x2e0600cc, 0xa0a }, /* 51 */ + { 0x2e0600d0, 0x4000694 }, /* 52 */ + { 0x2e0600d4, 0xa0a0804 }, /* 53 */ + { 0x2e0600d8, 0x4002432 }, /* 54 */ + { 0x2e0600dc, 0xa0a0804 }, /* 55 */ + { 0x2e0600e0, 0x4004864 }, /* 56 */ + { 0x2e0600e4, 0x2030404 }, /* 57 */ + { 0x2e0600e8, 0x5040400 }, /* 58 */ + { 0x2e0600ec, 0x80b0a06 }, /* 59 */ + { 0x2e0600f0, 0x7010100 }, /* 60 */ + { 0x2e0600f4, 0x4150b }, /* 61 */ + { 0x2e0600fc, 0x1010000 }, /* 63 */ + { 0x2e060100, 0x1000000 }, /* 64 */ + { 0x2e060104, 0xe0403 }, /* 65 */ + { 0x2e060108, 0xb3 }, /* 66 */ + { 0x2e06010c, 0x4a }, /* 67 */ + { 0x2e060110, 0x3fd }, /* 68 */ + { 0x2e060114, 0x94 }, /* 69 */ + { 0x2e060118, 0x803 }, /* 70 */ + { 0x2e06011c, 0x5 }, /* 71 */ + { 0x2e060120, 0x70000 }, /* 72 */ + { 0x2e060124, 0x25000f }, /* 73 */ + { 0x2e060128, 0x4a0078 }, /* 74 */ + { 0x2e06012c, 0x4000f9 }, /* 75 */ + { 0x2e060130, 0x120103 }, /* 76 */ + { 0x2e060134, 0x50005 }, /* 77 */ + { 0x2e060138, 0x8070005 }, /* 78 */ + { 0x2e06013c, 0x505010d }, /* 79 */ + { 0x2e060140, 0x101030a }, /* 80 */ + { 0x2e060144, 0x30a0505 }, /* 81 */ + { 0x2e060148, 0x5050101 }, /* 82 */ + { 0x2e06014c, 0x1030a }, /* 83 */ + { 0x2e060150, 0xe000e }, /* 84 */ + { 0x2e060154, 0x4c004c }, /* 85 */ + { 0x2e060158, 0x980098 }, /* 86 */ + { 0x2e06015c, 0x3050505 }, /* 87 */ + { 0x2e060160, 0x3010403 }, /* 88 */ + { 0x2e060164, 0x4050505 }, /* 89 */ + { 0x2e060168, 0x3010403 }, /* 90 */ + { 0x2e06016c, 0x8050505 }, /* 91 */ + { 0x2e060170, 0x3010403 }, /* 92 */ + { 0x2e060174, 0x3010000 }, /* 93 */ + { 0x2e060178, 0x10000 }, /* 94 */ + { 0x2e060180, 0x1000000 }, /* 96 */ + { 0x2e060184, 0x80104002 }, /* 97 */ + { 0x2e060188, 0x40003 }, /* 98 */ + { 0x2e06018c, 0x40005 }, /* 99 */ + { 0x2e060190, 0x30000 }, /* 100 */ + { 0x2e060194, 0x50004 }, /* 101 */ + { 0x2e060198, 0x4 }, /* 102 */ + { 0x2e06019c, 0x40003 }, /* 103 */ + { 0x2e0601a0, 0x40005 }, /* 104 */ + { 0x2e0601a8, 0x2cc0 }, /* 106 */ + { 0x2e0601ac, 0x2cc0 }, /* 107 */ + { 0x2e0601b0, 0x2cc0 }, /* 108 */ + { 0x2e0601b4, 0x2cc0 }, /* 109 */ + { 0x2e0601b8, 0x2cc0 }, /* 110 */ + { 0x2e0601c0, 0x4e5 }, /* 112 */ + { 0x2e0601c4, 0xff40 }, /* 113 */ + { 0x2e0601c8, 0xff40 }, /* 114 */ + { 0x2e0601cc, 0xff40 }, /* 115 */ + { 0x2e0601d0, 0xff40 }, /* 116 */ + { 0x2e0601d4, 0xff40 }, /* 117 */ + { 0x2e0601dc, 0x1beb }, /* 119 */ + { 0x2e0601e0, 0x200c0 }, /* 120 */ + { 0x2e0601e4, 0x200c0 }, /* 121 */ + { 0x2e0601e8, 0x200c0 }, /* 122 */ + { 0x2e0601ec, 0x200c0 }, /* 123 */ + { 0x2e0601f0, 0x200c0 }, /* 124 */ + { 0x2e0601f8, 0x3815 }, /* 126 */ + { 0x2e06021c, 0x5000000 }, /* 135 */ + { 0x2e060220, 0x5030503 }, /* 136 */ + { 0x2e060224, 0x3 }, /* 137 */ + { 0x2e060228, 0x7010a09 }, /* 138 */ + { 0x2e06022c, 0xe0a09 }, /* 139 */ + { 0x2e060230, 0x10a0900 }, /* 140 */ + { 0x2e060234, 0xe0a0907 }, /* 141 */ + { 0x2e060238, 0xa090000 }, /* 142 */ + { 0x2e06023c, 0xa090701 }, /* 143 */ + { 0x2e060240, 0x101000e }, /* 144 */ + { 0x2e060244, 0x40003 }, /* 145 */ + { 0x2e060248, 0x7 }, /* 146 */ + { 0x2e060264, 0x4040100 }, /* 153 */ + { 0x2e060268, 0x1000000 }, /* 154 */ + { 0x2e06026c, 0x100000c0 }, /* 155 */ + { 0x2e060270, 0x100000c0 }, /* 156 */ + { 0x2e060274, 0x100000c0 }, /* 157 */ + { 0x2e06027c, 0x1600 }, /* 159 */ + { 0x2e060284, 0x1 }, /* 161 */ + { 0x2e060288, 0x2 }, /* 162 */ + { 0x2e06028c, 0x100e }, /* 163 */ + { 0x2e0602a4, 0xa0000 }, /* 169 */ + { 0x2e0602a8, 0xd0005 }, /* 170 */ + { 0x2e0602ac, 0x404 }, /* 171 */ + { 0x2e0602b0, 0xd }, /* 172 */ + { 0x2e0602b4, 0x1b0035 }, /* 173 */ + { 0x2e0602b8, 0x4040042 }, /* 174 */ + { 0x2e0602bc, 0x42 }, /* 175 */ + { 0x2e0602c0, 0x35006a }, /* 176 */ + { 0x2e0602c4, 0x4040084 }, /* 177 */ + { 0x2e0602c8, 0x84 }, /* 178 */ + { 0x2e0602d8, 0x40004 }, /* 182 */ + { 0x2e0602dc, 0x30000914 }, /* 183 */ + { 0x2e0602e0, 0x3030 }, /* 184 */ + { 0x2e0602e4, 0x44440000 }, /* 185 */ + { 0x2e0602e8, 0x19191944 }, /* 186 */ + { 0x2e0602ec, 0x19191908 }, /* 187 */ + { 0x2e0602f0, 0x4000000 }, /* 188 */ + { 0x2e0602f4, 0x40404 }, /* 189 */ + { 0x2e0602f8, 0x9140004 }, /* 190 */ + { 0x2e0602fc, 0x30303000 }, /* 191 */ + { 0x2e060304, 0x19444444 }, /* 193 */ + { 0x2e060308, 0x19081919 }, /* 194 */ + { 0x2e06030c, 0x1919 }, /* 195 */ + { 0x2e060310, 0x4040400 }, /* 196 */ + { 0x2e060314, 0x1010120 }, /* 197 */ + { 0x2e060318, 0x1000100 }, /* 198 */ + { 0x2e06031c, 0x1 }, /* 199 */ + { 0x2e060324, 0x1000000 }, /* 201 */ + { 0x2e060328, 0x1 }, /* 202 */ + { 0x2e060354, 0x11000000 }, /* 213 */ + { 0x2e060358, 0x40c1815 }, /* 214 */ + { 0x2e060390, 0x30000 }, /* 228 */ + { 0x2e060394, 0x1000200 }, /* 229 */ + { 0x2e060398, 0x310040 }, /* 230 */ + { 0x2e06039c, 0x20002 }, /* 231 */ + { 0x2e0603a0, 0x400100 }, /* 232 */ + { 0x2e0603a4, 0x80108 }, /* 233 */ + { 0x2e0603a8, 0x1000200 }, /* 234 */ + { 0x2e0603ac, 0x2100040 }, /* 235 */ + { 0x2e0603b0, 0x10 }, /* 236 */ + { 0x2e0603b4, 0xe0003 }, /* 237 */ + { 0x2e0603b8, 0x100001b }, /* 238 */ + { 0x2e0603d8, 0xffff0b00 }, /* 246 */ + { 0x2e0603dc, 0x1010001 }, /* 247 */ + { 0x2e0603e0, 0x1010101 }, /* 248 */ + { 0x2e0603e4, 0x10b0101 }, /* 249 */ + { 0x2e0603e8, 0x10000 }, /* 250 */ + { 0x2e0603ec, 0x4010101 }, /* 251 */ + { 0x2e0603f0, 0x1010000 }, /* 252 */ + { 0x2e0603f4, 0x4 }, /* 253 */ + { 0x2e0603fc, 0x3030101 }, /* 255 */ + { 0x2e060400, 0x103 }, /* 256 */ + { 0x2e0604a4, 0x2020101 }, /* 297 */ + { 0x2e0604a8, 0x10100 }, /* 298 */ + { 0x2e0604ac, 0x1000101 }, /* 299 */ + { 0x2e0604b0, 0x1010101 }, /* 300 */ + { 0x2e0604b4, 0x4030300 }, /* 301 */ + { 0x2e0604b8, 0x8080505 }, /* 302 */ + { 0x2e0604bc, 0x8020808 }, /* 303 */ + { 0x2e0604c0, 0x8020e00 }, /* 304 */ + { 0x2e0604c4, 0xa020e00 }, /* 305 */ + { 0x2e0604c8, 0x8000f00 }, /* 306 */ + { 0x2e0604cc, 0xa08 }, /* 307 */ + { 0x2e0604d0, 0x1010101 }, /* 308 */ + { 0x2e0604d4, 0x01000102 }, /* 309 */ + { 0x2e0604d8, 0x00000101 }, /* 310 */ + { 0x2e0604dc, 0x40400 }, /* 311 */ + { 0x2e0604e0, 0x4040000 }, /* 312 */ + { 0x2e0604e4, 0x4000000 }, /* 313 */ + { 0x2e0604e8, 0x10004 }, /* 314 */ + { 0x2e0604f0, 0xfffff }, /* 316 */ + { 0x2e0604f8, 0xfffff }, /* 318 */ + { 0x2e060500, 0xfffff }, /* 320 */ + { 0x2e060508, 0xfffff }, /* 322 */ + { 0x2e060510, 0xfffff }, /* 324 */ + { 0x2e060518, 0xfffff }, /* 326 */ + { 0x2e060520, 0xfffff }, /* 328 */ + { 0x2e060528, 0xfffff }, /* 330 */ + { 0x2e060530, 0xfffff }, /* 332 */ + { 0x2e060538, 0xfffff }, /* 334 */ + { 0x2e060540, 0xfffff }, /* 336 */ + { 0x2e060548, 0xfffff }, /* 338 */ + { 0x2e060550, 0xfffff }, /* 340 */ + { 0x2e060558, 0xfffff }, /* 342 */ + { 0x2e060560, 0xfffff }, /* 344 */ + { 0x2e060568, 0xfffff }, /* 346 */ + { 0x2e060570, 0xfffff }, /* 348 */ + { 0x2e060578, 0xfffff }, /* 350 */ + { 0x2e060580, 0xfffff }, /* 352 */ + { 0x2e060588, 0xfffff }, /* 354 */ + { 0x2e060590, 0xfffff }, /* 356 */ + { 0x2e060598, 0xfffff }, /* 358 */ + { 0x2e0605a0, 0xfffff }, /* 360 */ + { 0x2e0605a8, 0xfffff }, /* 362 */ + { 0x2e0605b0, 0xfffff }, /* 364 */ + { 0x2e0605b8, 0xfffff }, /* 366 */ + { 0x2e0605c0, 0xfffff }, /* 368 */ + { 0x2e0605c8, 0xfffff }, /* 370 */ + { 0x2e0605d0, 0xfffff }, /* 372 */ + { 0x2e0605d8, 0xfffff }, /* 374 */ + { 0x2e0605e0, 0xfffff }, /* 376 */ + { 0x2e0605e8, 0xfffff }, /* 378 */ + { 0x2e0605f0, 0xfffff }, /* 380 */ + { 0x2e0605f8, 0xfffff }, /* 382 */ + { 0x2e060600, 0xfffff }, /* 384 */ + { 0x2e060608, 0xfffff }, /* 386 */ + { 0x2e060610, 0xfffff }, /* 388 */ + { 0x2e060618, 0xfffff }, /* 390 */ + { 0x2e060620, 0xfffff }, /* 392 */ + { 0x2e060628, 0xfffff }, /* 394 */ + { 0x2e060630, 0xfffff }, /* 396 */ + { 0x2e060638, 0xfffff }, /* 398 */ + { 0x2e060640, 0xfffff }, /* 400 */ + { 0x2e060648, 0xfffff }, /* 402 */ + { 0x2e060650, 0xfffff }, /* 404 */ + { 0x2e060658, 0xfffff }, /* 406 */ + { 0x2e060660, 0xfffff }, /* 408 */ + { 0x2e060668, 0xfffff }, /* 410 */ + { 0x2e060670, 0xfffff }, /* 412 */ + { 0x2e060678, 0xfffff }, /* 414 */ + { 0x2e060680, 0xfffff }, /* 416 */ + { 0x2e060688, 0xfffff }, /* 418 */ + { 0x2e060690, 0xfffff }, /* 420 */ + { 0x2e060698, 0xfffff }, /* 422 */ + { 0x2e0606a0, 0xfffff }, /* 424 */ + { 0x2e0606a8, 0xfffff }, /* 426 */ + { 0x2e0606b0, 0xfffff }, /* 428 */ + { 0x2e0606b8, 0xfffff }, /* 430 */ + { 0x2e0606c0, 0xfffff }, /* 432 */ + { 0x2e0606c8, 0xfffff }, /* 434 */ + { 0x2e0606d0, 0xfffff }, /* 436 */ + { 0x2e0606d8, 0xfffff }, /* 438 */ + { 0x2e0606e0, 0xfffff }, /* 440 */ + { 0x2e0606e8, 0x30fffff }, /* 442 */ + { 0x2e0606ec, 0xffffffff }, /* 443 */ + { 0x2e0606f0, 0x30f0f }, /* 444 */ + { 0x2e0606f4, 0xffffffff }, /* 445 */ + { 0x2e0606f8, 0x30f0f }, /* 446 */ + { 0x2e0606fc, 0xffffffff }, /* 447 */ + { 0x2e060700, 0x30f0f }, /* 448 */ + { 0x2e060704, 0xffffffff }, /* 449 */ + { 0x2e060708, 0x30f0f }, /* 450 */ + { 0x2e06070c, 0xffffffff }, /* 451 */ + { 0x2e060710, 0x30f0f }, /* 452 */ + { 0x2e060714, 0xffffffff }, /* 453 */ + { 0x2e060718, 0x30f0f }, /* 454 */ + { 0x2e06071c, 0xffffffff }, /* 455 */ + { 0x2e060720, 0x30f0f }, /* 456 */ + { 0x2e060724, 0xffffffff }, /* 457 */ + { 0x2e060728, 0x30f0f }, /* 458 */ + { 0x2e06072c, 0xffffffff }, /* 459 */ + { 0x2e060730, 0x30f0f }, /* 460 */ + { 0x2e060734, 0xffffffff }, /* 461 */ + { 0x2e060738, 0x30f0f }, /* 462 */ + { 0x2e06073c, 0xffffffff }, /* 463 */ + { 0x2e060740, 0x30f0f }, /* 464 */ + { 0x2e060744, 0xffffffff }, /* 465 */ + { 0x2e060748, 0x30f0f }, /* 466 */ + { 0x2e06074c, 0xffffffff }, /* 467 */ + { 0x2e060750, 0x30f0f }, /* 468 */ + { 0x2e060754, 0xffffffff }, /* 469 */ + { 0x2e060758, 0x30f0f }, /* 470 */ + { 0x2e06075c, 0xffffffff }, /* 471 */ + { 0x2e060760, 0x30f0f }, /* 472 */ + { 0x2e060764, 0xffffffff }, /* 473 */ + { 0x2e060768, 0x30f0f }, /* 474 */ + { 0x2e06076c, 0xffffffff }, /* 475 */ + { 0x2e060770, 0x30f0f }, /* 476 */ + { 0x2e060774, 0xffffffff }, /* 477 */ + { 0x2e060778, 0x30f0f }, /* 478 */ + { 0x2e06077c, 0xffffffff }, /* 479 */ + { 0x2e060780, 0x30f0f }, /* 480 */ + { 0x2e060784, 0xffffffff }, /* 481 */ + { 0x2e060788, 0x30f0f }, /* 482 */ + { 0x2e06078c, 0xffffffff }, /* 483 */ + { 0x2e060790, 0x30f0f }, /* 484 */ + { 0x2e060794, 0xffffffff }, /* 485 */ + { 0x2e060798, 0x30f0f }, /* 486 */ + { 0x2e06079c, 0xffffffff }, /* 487 */ + { 0x2e0607a0, 0x30f0f }, /* 488 */ + { 0x2e0607a4, 0xffffffff }, /* 489 */ + { 0x2e0607a8, 0x30f0f }, /* 490 */ + { 0x2e0607ac, 0xffffffff }, /* 491 */ + { 0x2e0607b0, 0x30f0f }, /* 492 */ + { 0x2e0607b4, 0xffffffff }, /* 493 */ + { 0x2e0607b8, 0x30f0f }, /* 494 */ + { 0x2e0607bc, 0xffffffff }, /* 495 */ + { 0x2e0607c0, 0x30f0f }, /* 496 */ + { 0x2e0607c4, 0xffffffff }, /* 497 */ + { 0x2e0607c8, 0x30f0f }, /* 498 */ + { 0x2e0607cc, 0xffffffff }, /* 499 */ + { 0x2e0607d0, 0x30f0f }, /* 500 */ + { 0x2e0607d4, 0xffffffff }, /* 501 */ + { 0x2e0607d8, 0x30f0f }, /* 502 */ + { 0x2e0607dc, 0xffffffff }, /* 503 */ + { 0x2e0607e0, 0x30f0f }, /* 504 */ + { 0x2e0607e4, 0xffffffff }, /* 505 */ + { 0x2e0607e8, 0x30f0f }, /* 506 */ + { 0x2e0607ec, 0xffffffff }, /* 507 */ + { 0x2e0607f0, 0x30f0f }, /* 508 */ + { 0x2e0607f4, 0xffffffff }, /* 509 */ + { 0x2e0607f8, 0x30f0f }, /* 510 */ + { 0x2e0607fc, 0xffffffff }, /* 511 */ + { 0x2e060800, 0x30f0f }, /* 512 */ + { 0x2e060804, 0xffffffff }, /* 513 */ + { 0x2e060808, 0x30f0f }, /* 514 */ + { 0x2e06080c, 0xffffffff }, /* 515 */ + { 0x2e060810, 0x30f0f }, /* 516 */ + { 0x2e060814, 0xffffffff }, /* 517 */ + { 0x2e060818, 0x30f0f }, /* 518 */ + { 0x2e06081c, 0xffffffff }, /* 519 */ + { 0x2e060820, 0x30f0f }, /* 520 */ + { 0x2e060824, 0xffffffff }, /* 521 */ + { 0x2e060828, 0x30f0f }, /* 522 */ + { 0x2e06082c, 0xffffffff }, /* 523 */ + { 0x2e060830, 0x30f0f }, /* 524 */ + { 0x2e060834, 0xffffffff }, /* 525 */ + { 0x2e060838, 0x30f0f }, /* 526 */ + { 0x2e06083c, 0xffffffff }, /* 527 */ + { 0x2e060840, 0x30f0f }, /* 528 */ + { 0x2e060844, 0xffffffff }, /* 529 */ + { 0x2e060848, 0x30f0f }, /* 530 */ + { 0x2e06084c, 0xffffffff }, /* 531 */ + { 0x2e060850, 0x30f0f }, /* 532 */ + { 0x2e060854, 0xffffffff }, /* 533 */ + { 0x2e060858, 0x30f0f }, /* 534 */ + { 0x2e06085c, 0xffffffff }, /* 535 */ + { 0x2e060860, 0x30f0f }, /* 536 */ + { 0x2e060864, 0xffffffff }, /* 537 */ + { 0x2e060868, 0x30f0f }, /* 538 */ + { 0x2e06086c, 0xffffffff }, /* 539 */ + { 0x2e060870, 0x30f0f }, /* 540 */ + { 0x2e060874, 0xffffffff }, /* 541 */ + { 0x2e060878, 0x30f0f }, /* 542 */ + { 0x2e06087c, 0xffffffff }, /* 543 */ + { 0x2e060880, 0x30f0f }, /* 544 */ + { 0x2e060884, 0xffffffff }, /* 545 */ + { 0x2e060888, 0x30f0f }, /* 546 */ + { 0x2e06088c, 0xffffffff }, /* 547 */ + { 0x2e060890, 0x30f0f }, /* 548 */ + { 0x2e060894, 0xffffffff }, /* 549 */ + { 0x2e060898, 0x30f0f }, /* 550 */ + { 0x2e06089c, 0xffffffff }, /* 551 */ + { 0x2e0608a0, 0x30f0f }, /* 552 */ + { 0x2e0608a4, 0xffffffff }, /* 553 */ + { 0x2e0608a8, 0x30f0f }, /* 554 */ + { 0x2e0608ac, 0xffffffff }, /* 555 */ + { 0x2e0608b0, 0x30f0f }, /* 556 */ + { 0x2e0608b4, 0xffffffff }, /* 557 */ + { 0x2e0608b8, 0x30f0f }, /* 558 */ + { 0x2e0608bc, 0xffffffff }, /* 559 */ + { 0x2e0608c0, 0x30f0f }, /* 560 */ + { 0x2e0608c4, 0xffffffff }, /* 561 */ + { 0x2e0608c8, 0x30f0f }, /* 562 */ + { 0x2e0608cc, 0xffffffff }, /* 563 */ + { 0x2e0608d0, 0x30f0f }, /* 564 */ + { 0x2e0608d4, 0xffffffff }, /* 565 */ + { 0x2e0608d8, 0x30f0f }, /* 566 */ + { 0x2e0608dc, 0xffffffff }, /* 567 */ + { 0x2e0608e0, 0x30f0f }, /* 568 */ + { 0x2e0608e4, 0xffffffff }, /* 569 */ + { 0x2e0608e8, 0x32070f0f }, /* 570 */ + { 0x2e0608ec, 0x1320000 }, /* 571 */ + { 0x2e0608f0, 0x13200 }, /* 572 */ + { 0x2e0608f4, 0x132 }, /* 573 */ + { 0x2e0608fc, 0x1d1b0000 }, /* 575 */ + { 0x2e060900, 0x21 }, /* 576 */ + { 0x2e060904, 0xa }, /* 577 */ + { 0x2e060908, 0x166 }, /* 578 */ + { 0x2e06090c, 0x200 }, /* 579 */ + { 0x2e060910, 0x200 }, /* 580 */ + { 0x2e060914, 0x200 }, /* 581 */ + { 0x2e060918, 0x200 }, /* 582 */ + { 0x2e06091c, 0x432 }, /* 583 */ + { 0x2e060920, 0xdfc }, /* 584 */ + { 0x2e060924, 0x204 }, /* 585 */ + { 0x2e060928, 0x7fa }, /* 586 */ + { 0x2e06092c, 0x200 }, /* 587 */ + { 0x2e060930, 0x200 }, /* 588 */ + { 0x2e060934, 0x200 }, /* 589 */ + { 0x2e060938, 0x200 }, /* 590 */ + { 0x2e06093c, 0x17ee }, /* 591 */ + { 0x2e060940, 0x4fc4 }, /* 592 */ + { 0x2e060944, 0x204 }, /* 593 */ + { 0x2e060948, 0x1006 }, /* 594 */ + { 0x2e06094c, 0x200 }, /* 595 */ + { 0x2e060950, 0x200 }, /* 596 */ + { 0x2e060954, 0x200 }, /* 597 */ + { 0x2e060958, 0x200 }, /* 598 */ + { 0x2e06095c, 0x3012 }, /* 599 */ + { 0x2e060960, 0xa03c }, /* 600 */ + { 0x2e060964, 0x2020406 }, /* 601 */ + { 0x2e060968, 0x2030202 }, /* 602 */ + { 0x2e06096c, 0x1000202 }, /* 603 */ + { 0x2e060970, 0x3040100 }, /* 604 */ + { 0x2e060974, 0x10105 }, /* 605 */ + { 0x2e060978, 0x10101 }, /* 606 */ + { 0x2e06097c, 0x10101 }, /* 607 */ + { 0x2e060980, 0x10001 }, /* 608 */ + { 0x2e060984, 0x101 }, /* 609 */ + { 0x2e060988, 0x2000201 }, /* 610 */ + { 0x2e06098c, 0x2010000 }, /* 611 */ + { 0x2e060990, 0x6000200 }, /* 612 */ + { 0x2e060994, 0x3000a06 }, /* 613 */ + { 0x2e060998, 0x2000c06 }, /* 614 */ +}; + +/** PI settings **/ +struct dram_cfg_param ddr_pi_cfg[] = { + { 0x2e062000, 0xb00 }, /* 0 */ + { 0x2e062004, 0xbeedb66f }, /* 1 */ + { 0x2e062008, 0xabef6bd }, /* 2 */ + { 0x2e06200c, 0x1001387 }, /* 3 */ + { 0x2e062010, 0x1 }, /* 4 */ + { 0x2e062014, 0x10064 }, /* 5 */ + { 0x2e06202c, 0x101 }, /* 11 */ + { 0x2e062030, 0x3 }, /* 12 */ + { 0x2e062034, 0x50001 }, /* 13 */ + { 0x2e062038, 0x3030800 }, /* 14 */ + { 0x2e06203c, 0x1 }, /* 15 */ + { 0x2e062040, 0x5 }, /* 16 */ + { 0x2e062064, 0x1000000 }, /* 25 */ + { 0x2e062068, 0xa000001 }, /* 26 */ + { 0x2e06206c, 0x28 }, /* 27 */ + { 0x2e062070, 0x1 }, /* 28 */ + { 0x2e062074, 0x320005 }, /* 29 */ + { 0x2e062080, 0x10102 }, /* 32 */ + { 0x2e062084, 0x1 }, /* 33 */ + { 0x2e062088, 0xaa }, /* 34 */ + { 0x2e06208c, 0x55 }, /* 35 */ + { 0x2e062090, 0xb5 }, /* 36 */ + { 0x2e062094, 0x4a }, /* 37 */ + { 0x2e062098, 0x56 }, /* 38 */ + { 0x2e06209c, 0xa9 }, /* 39 */ + { 0x2e0620a0, 0xa9 }, /* 40 */ + { 0x2e0620a4, 0xb5 }, /* 41 */ + { 0x2e0620a8, 0x10000 }, /* 42 */ + { 0x2e0620ac, 0x100 }, /* 43 */ + { 0x2e0620b0, 0x5050000 }, /* 44 */ + { 0x2e0620b4, 0x13 }, /* 45 */ + { 0x2e0620b8, 0x7d0 }, /* 46 */ + { 0x2e0620bc, 0x300 }, /* 47 */ + { 0x2e0620c8, 0x1000000 }, /* 50 */ + { 0x2e0620cc, 0x10101 }, /* 51 */ + { 0x2e0620d8, 0x10003 }, /* 54 */ + { 0x2e0620dc, 0x170500 }, /* 55 */ + { 0x2e0620ec, 0xa140a01 }, /* 59 */ + { 0x2e0620f0, 0x204010a }, /* 60 */ + { 0x2e0620f4, 0x21010 }, /* 61 */ + { 0x2e0620f8, 0x40401 }, /* 62 */ + { 0x2e0620fc, 0x10e0005 }, /* 63 */ + { 0x2e062100, 0x5000001 }, /* 64 */ + { 0x2e062104, 0x204 }, /* 65 */ + { 0x2e062108, 0x34 }, /* 66 */ + { 0x2e062114, 0x1000000 }, /* 69 */ + { 0x2e062118, 0x1000000 }, /* 70 */ + { 0x2e06211c, 0x80200 }, /* 71 */ + { 0x2e062120, 0x2000200 }, /* 72 */ + { 0x2e062124, 0x1000100 }, /* 73 */ + { 0x2e062128, 0x1000000 }, /* 74 */ + { 0x2e06212c, 0x2000200 }, /* 75 */ + { 0x2e062130, 0x200 }, /* 76 */ + { 0x2e062164, 0x400 }, /* 89 */ + { 0x2e062168, 0x2010000 }, /* 90 */ + { 0x2e06216c, 0x80103 }, /* 91 */ + { 0x2e062174, 0x10008 }, /* 93 */ + { 0x2e06217c, 0xaa00 }, /* 95 */ + { 0x2e062188, 0x10000 }, /* 98 */ + { 0x2e0621ec, 0x8 }, /* 123 */ + { 0x2e062218, 0xf0000 }, /* 134 */ + { 0x2e06221c, 0xa }, /* 135 */ + { 0x2e062220, 0x19 }, /* 136 */ + { 0x2e062224, 0x100 }, /* 137 */ + { 0x2e062228, 0x100 }, /* 138 */ + { 0x2e062238, 0x1000000 }, /* 142 */ + { 0x2e06223c, 0x10003 }, /* 143 */ + { 0x2e062240, 0x2000101 }, /* 144 */ + { 0x2e062244, 0x1030001 }, /* 145 */ + { 0x2e062248, 0x10400 }, /* 146 */ + { 0x2e06224c, 0x6000105 }, /* 147 */ + { 0x2e062250, 0x1070001 }, /* 148 */ + { 0x2e062260, 0x10001 }, /* 152 */ + { 0x2e062274, 0x401 }, /* 157 */ + { 0x2e06227c, 0x10000 }, /* 159 */ + { 0x2e062284, 0x6010000 }, /* 161 */ + { 0x2e062288, 0xb }, /* 162 */ + { 0x2e06228c, 0x34 }, /* 163 */ + { 0x2e062290, 0x36 }, /* 164 */ + { 0x2e062294, 0x2003c }, /* 165 */ + { 0x2e062298, 0x2000200 }, /* 166 */ + { 0x2e06229c, 0xc040c04 }, /* 167 */ + { 0x2e0622a0, 0xe1406 }, /* 168 */ + { 0x2e0622a4, 0xb3 }, /* 169 */ + { 0x2e0622a8, 0x4a }, /* 170 */ + { 0x2e0622ac, 0x3fd }, /* 171 */ + { 0x2e0622b0, 0x94 }, /* 172 */ + { 0x2e0622b4, 0x4000803 }, /* 173 */ + { 0x2e0622b8, 0x1010404 }, /* 174 */ + { 0x2e0622bc, 0x1501 }, /* 175 */ + { 0x2e0622c0, 0x1a0018 }, /* 176 */ + { 0x2e0622c4, 0x1000100 }, /* 177 */ + { 0x2e0622c8, 0x100 }, /* 178 */ + { 0x2e0622d0, 0x5040303 }, /* 180 */ + { 0x2e0622d4, 0x1010805 }, /* 181 */ + { 0x2e0622d8, 0x1010101 }, /* 182 */ + { 0x2e0622e8, 0x2060404 }, /* 186 */ + { 0x2e0622ec, 0x2020402 }, /* 187 */ + { 0x2e0622f0, 0x3102 }, /* 188 */ + { 0x2e0622f4, 0x340009 }, /* 189 */ + { 0x2e0622f8, 0x36000c }, /* 190 */ + { 0x2e0622fc, 0x101000e }, /* 191 */ + { 0x2e062300, 0xd0101 }, /* 192 */ + { 0x2e062304, 0x1004201 }, /* 193 */ + { 0x2e062308, 0x1000084 }, /* 194 */ + { 0x2e06230c, 0xe000e }, /* 195 */ + { 0x2e062310, 0x430100 }, /* 196 */ + { 0x2e062314, 0x1000043 }, /* 197 */ + { 0x2e062318, 0x850085 }, /* 198 */ + { 0x2e06231c, 0x220f220f }, /* 199 */ + { 0x2e062320, 0x101220f }, /* 200 */ + { 0x2e062324, 0xa070601 }, /* 201 */ + { 0x2e062328, 0xa07060d }, /* 202 */ + { 0x2e06232c, 0xa07070d }, /* 203 */ + { 0x2e062330, 0xc00d }, /* 204 */ + { 0x2e062334, 0xc01000 }, /* 205 */ + { 0x2e062338, 0xc01000 }, /* 206 */ + { 0x2e06233c, 0x21000 }, /* 207 */ + { 0x2e062340, 0x11000d }, /* 208 */ + { 0x2e062344, 0x140042 }, /* 209 */ + { 0x2e062348, 0x190084 }, /* 210 */ + { 0x2e06234c, 0x220f0056 }, /* 211 */ + { 0x2e062350, 0x101 }, /* 212 */ + { 0x2e062354, 0x560019 }, /* 213 */ + { 0x2e062358, 0x101220f }, /* 214 */ + { 0x2e06235c, 0x1b00 }, /* 215 */ + { 0x2e062360, 0x220f0056 }, /* 216 */ + { 0x2e062364, 0x8000101 }, /* 217 */ + { 0x2e062368, 0x4090403 }, /* 218 */ + { 0x2e06236c, 0x5eb }, /* 219 */ + { 0x2e062370, 0x20010003 }, /* 220 */ + { 0x2e062374, 0x80a0a03 }, /* 221 */ + { 0x2e062378, 0x6090506 }, /* 222 */ + { 0x2e06237c, 0x2093 }, /* 223 */ + { 0x2e062380, 0x2001000c }, /* 224 */ + { 0x2e062384, 0x80a0a04 }, /* 225 */ + { 0x2e062388, 0xb090a0c }, /* 226 */ + { 0x2e06238c, 0x4126 }, /* 227 */ + { 0x2e062390, 0x20020017 }, /* 228 */ + { 0x2e062394, 0xa0a08 }, /* 229 */ + { 0x2e062398, 0x166 }, /* 230 */ + { 0x2e06239c, 0xdfc }, /* 231 */ + { 0x2e0623a0, 0x7fa }, /* 232 */ + { 0x2e0623a4, 0x4fc4 }, /* 233 */ + { 0x2e0623a8, 0x1006 }, /* 234 */ + { 0x2e0623ac, 0xa03c }, /* 235 */ + { 0x2e0623b0, 0x4c000e }, /* 236 */ + { 0x2e0623b4, 0x3030098 }, /* 237 */ + { 0x2e0623b8, 0x258103 }, /* 238 */ + { 0x2e0623bc, 0x17702 }, /* 239 */ + { 0x2e0623c0, 0x5 }, /* 240 */ + { 0x2e0623c4, 0x61 }, /* 241 */ + { 0x2e0623c8, 0xe }, /* 242 */ + { 0x2e0623cc, 0xce3f }, /* 243 */ + { 0x2e0623d0, 0x80e70 }, /* 244 */ + { 0x2e0623d4, 0x5 }, /* 245 */ + { 0x2e0623d8, 0x210 }, /* 246 */ + { 0x2e0623dc, 0x4c }, /* 247 */ + { 0x2e0623e0, 0x19c7d }, /* 248 */ + { 0x2e0623e4, 0x101cdf }, /* 249 */ + { 0x2e0623e8, 0x5 }, /* 250 */ + { 0x2e0623ec, 0x420 }, /* 251 */ + { 0x2e0623f0, 0x1000098 }, /* 252 */ + { 0x2e0623f4, 0x310040 }, /* 253 */ + { 0x2e0623f8, 0x10002 }, /* 254 */ + { 0x2e0623fc, 0x1080040 }, /* 255 */ + { 0x2e062400, 0x10008 }, /* 256 */ + { 0x2e062404, 0x2100040 }, /* 257 */ + { 0x2e062408, 0x310 }, /* 258 */ + { 0x2e06240c, 0x1b000e }, /* 259 */ + { 0x2e062410, 0x1010101 }, /* 260 */ + { 0x2e062414, 0x2020101 }, /* 261 */ + { 0x2e062418, 0x8080404 }, /* 262 */ + { 0x2e06241c, 0x5508 }, /* 263 */ + { 0x2e062420, 0x83c5a00 }, /* 264 */ + { 0x2e062424, 0x55 }, /* 265 */ + { 0x2e062428, 0x55083c5a }, /* 266 */ + { 0x2e06242c, 0x5a000000 }, /* 267 */ + { 0x2e062430, 0x55083c }, /* 268 */ + { 0x2e062434, 0x3c5a0000 }, /* 269 */ + { 0x2e062438, 0xf0e0d0c }, /* 270 */ + { 0x2e06243c, 0xb0a0908 }, /* 271 */ + { 0x2e062440, 0x7060504 }, /* 272 */ + { 0x2e062444, 0x3020100 }, /* 273 */ + { 0x2e06244c, 0x2020101 }, /* 275 */ + { 0x2e062450, 0x8080404 }, /* 276 */ + { 0x2e062454, 0x44300004 }, /* 277 */ + { 0x2e062458, 0x4041919 }, /* 278 */ + { 0x2e06245c, 0x19443000 }, /* 279 */ + { 0x2e062460, 0x9140419 }, /* 280 */ + { 0x2e062464, 0x19194430 }, /* 281 */ + { 0x2e062468, 0x30000404 }, /* 282 */ + { 0x2e06246c, 0x4191944 }, /* 283 */ + { 0x2e062470, 0x44300004 }, /* 284 */ + { 0x2e062474, 0x14041919 }, /* 285 */ + { 0x2e062478, 0x19443009 }, /* 286 */ + { 0x2e06247c, 0x40419 }, /* 287 */ + { 0x2e062480, 0x19194430 }, /* 288 */ + { 0x2e062484, 0x30000404 }, /* 289 */ + { 0x2e062488, 0x4191944 }, /* 290 */ + { 0x2e06248c, 0x44300914 }, /* 291 */ + { 0x2e062490, 0x44041919 }, /* 292 */ + { 0x2e062494, 0x19443000 }, /* 293 */ + { 0x2e062498, 0x40419 }, /* 294 */ + { 0x2e06249c, 0x19194430 }, /* 295 */ + { 0x2e0624a0, 0x30091404 }, /* 296 */ + { 0x2e0624a4, 0x4191944 }, /* 297 */ +}; + +/** PHY_F1 settings **/ +struct dram_cfg_param ddr_phy_f1_cfg[] = { + { 0x2e064000, 0x4f0 }, /* 0 */ + { 0x2e064008, 0x1030200 }, /* 2 */ + { 0x2e064014, 0x3000000 }, /* 5 */ + { 0x2e064018, 0x1000001 }, /* 6 */ + { 0x2e06401c, 0x3000400 }, /* 7 */ + { 0x2e064020, 0x1 }, /* 8 */ + { 0x2e064024, 0x1 }, /* 9 */ + { 0x2e064030, 0x10000 }, /* 12 */ + { 0x2e064038, 0xc00004 }, /* 14 */ + { 0x2e06403c, 0xcc0008 }, /* 15 */ + { 0x2e064040, 0x660601 }, /* 16 */ + { 0x2e064044, 0x3 }, /* 17 */ + { 0x2e06404c, 0x1 }, /* 19 */ + { 0x2e064050, 0xaaaa }, /* 20 */ + { 0x2e064054, 0x5555 }, /* 21 */ + { 0x2e064058, 0xb5b5 }, /* 22 */ + { 0x2e06405c, 0x4a4a }, /* 23 */ + { 0x2e064060, 0x5656 }, /* 24 */ + { 0x2e064064, 0xa9a9 }, /* 25 */ + { 0x2e064068, 0xb7b7 }, /* 26 */ + { 0x2e06406c, 0x4848 }, /* 27 */ + { 0x2e064078, 0x8000000 }, /* 30 */ + { 0x2e06407c, 0x4010008 }, /* 31 */ + { 0x2e064080, 0x408 }, /* 32 */ + { 0x2e064084, 0x3102000 }, /* 33 */ + { 0x2e064088, 0xc0020 }, /* 34 */ + { 0x2e06408c, 0x10000 }, /* 35 */ + { 0x2e064090, 0x55555555 }, /* 36 */ + { 0x2e064094, 0xaaaaaaaa }, /* 37 */ + { 0x2e064098, 0x55555555 }, /* 38 */ + { 0x2e06409c, 0xaaaaaaaa }, /* 39 */ + { 0x2e0640a0, 0x5555 }, /* 40 */ + { 0x2e0640a4, 0x1000100 }, /* 41 */ + { 0x2e0640a8, 0x800180 }, /* 42 */ + { 0x2e0640ac, 0x1 }, /* 43 */ + { 0x2e064100, 0x4 }, /* 64 */ + { 0x2e06411c, 0x41f07ff }, /* 71 */ + { 0x2e064120, 0x1 }, /* 72 */ + { 0x2e064124, 0x1cc0800 }, /* 73 */ + { 0x2e064128, 0x3003cc08 }, /* 74 */ + { 0x2e06412c, 0x2000014e }, /* 75 */ + { 0x2e064130, 0x7ff0200 }, /* 76 */ + { 0x2e064134, 0x301 }, /* 77 */ + { 0x2e064140, 0x30000 }, /* 80 */ + { 0x2e064154, 0x2000000 }, /* 85 */ + { 0x2e064158, 0x51515042 }, /* 86 */ + { 0x2e06415c, 0x31c06000 }, /* 87 */ + { 0x2e064160, 0x6bf000a }, /* 88 */ + { 0x2e064164, 0xc0c000 }, /* 89 */ + { 0x2e064168, 0x1000000 }, /* 90 */ + { 0x2e06416c, 0x10001000 }, /* 91 */ + { 0x2e064170, 0xc043242 }, /* 92 */ + { 0x2e064174, 0xf0c1201 }, /* 93 */ + { 0x2e064178, 0x1000140 }, /* 94 */ + { 0x2e06417c, 0xc000120 }, /* 95 */ + { 0x2e064180, 0x143 }, /* 96 */ + { 0x2e064184, 0x1000203 }, /* 97 */ + { 0x2e064188, 0x56417032 }, /* 98 */ + { 0x2e06418c, 0x8 }, /* 99 */ + { 0x2e064190, 0x2c302c3 }, /* 100 */ + { 0x2e064194, 0x2c302c3 }, /* 101 */ + { 0x2e064198, 0x2c302c3 }, /* 102 */ + { 0x2e06419c, 0x2c302c3 }, /* 103 */ + { 0x2e0641a0, 0x2c3 }, /* 104 */ + { 0x2e0641a4, 0x8000 }, /* 105 */ + { 0x2e0641a8, 0x800080 }, /* 106 */ + { 0x2e0641ac, 0x800080 }, /* 107 */ + { 0x2e0641b0, 0x800080 }, /* 108 */ + { 0x2e0641b4, 0x800080 }, /* 109 */ + { 0x2e0641b8, 0x800080 }, /* 110 */ + { 0x2e0641bc, 0x800080 }, /* 111 */ + { 0x2e0641c0, 0x800080 }, /* 112 */ + { 0x2e0641c4, 0x800080 }, /* 113 */ + { 0x2e0641c8, 0x6b0080 }, /* 114 */ + { 0x2e0641cc, 0x1a00001 }, /* 115 */ + { 0x2e0641d4, 0x10000 }, /* 117 */ + { 0x2e0641d8, 0x80200 }, /* 118 */ + { 0x2e064400, 0x4f0 }, /* 256 */ + { 0x2e064408, 0x1030200 }, /* 258 */ + { 0x2e064414, 0x3000000 }, /* 261 */ + { 0x2e064418, 0x1000001 }, /* 262 */ + { 0x2e06441c, 0x3000400 }, /* 263 */ + { 0x2e064420, 0x1 }, /* 264 */ + { 0x2e064424, 0x1 }, /* 265 */ + { 0x2e064430, 0x10000 }, /* 268 */ + { 0x2e064438, 0xc00004 }, /* 270 */ + { 0x2e06443c, 0xcc0008 }, /* 271 */ + { 0x2e064440, 0x660601 }, /* 272 */ + { 0x2e064444, 0x3 }, /* 273 */ + { 0x2e06444c, 0x1 }, /* 275 */ + { 0x2e064450, 0xaaaa }, /* 276 */ + { 0x2e064454, 0x5555 }, /* 277 */ + { 0x2e064458, 0xb5b5 }, /* 278 */ + { 0x2e06445c, 0x4a4a }, /* 279 */ + { 0x2e064460, 0x5656 }, /* 280 */ + { 0x2e064464, 0xa9a9 }, /* 281 */ + { 0x2e064468, 0xb7b7 }, /* 282 */ + { 0x2e06446c, 0x4848 }, /* 283 */ + { 0x2e064478, 0x8000000 }, /* 286 */ + { 0x2e06447c, 0x4010008 }, /* 287 */ + { 0x2e064480, 0x408 }, /* 288 */ + { 0x2e064484, 0x3102000 }, /* 289 */ + { 0x2e064488, 0xc0020 }, /* 290 */ + { 0x2e06448c, 0x10000 }, /* 291 */ + { 0x2e064490, 0x55555555 }, /* 292 */ + { 0x2e064494, 0xaaaaaaaa }, /* 293 */ + { 0x2e064498, 0x55555555 }, /* 294 */ + { 0x2e06449c, 0xaaaaaaaa }, /* 295 */ + { 0x2e0644a0, 0x5555 }, /* 296 */ + { 0x2e0644a4, 0x1000100 }, /* 297 */ + { 0x2e0644a8, 0x800180 }, /* 298 */ + { 0x2e064500, 0x4 }, /* 320 */ + { 0x2e06451c, 0x41f07ff }, /* 327 */ + { 0x2e064520, 0x1 }, /* 328 */ + { 0x2e064524, 0x1cc0800 }, /* 329 */ + { 0x2e064528, 0x3003cc08 }, /* 330 */ + { 0x2e06452c, 0x2000014e }, /* 331 */ + { 0x2e064530, 0x7ff0200 }, /* 332 */ + { 0x2e064534, 0x301 }, /* 333 */ + { 0x2e064540, 0x30000 }, /* 336 */ + { 0x2e064554, 0x2000000 }, /* 341 */ + { 0x2e064558, 0x51515042 }, /* 342 */ + { 0x2e06455c, 0x31c06000 }, /* 343 */ + { 0x2e064560, 0x6bf000a }, /* 344 */ + { 0x2e064564, 0xc0c000 }, /* 345 */ + { 0x2e064568, 0x1000000 }, /* 346 */ + { 0x2e06456c, 0x10001000 }, /* 347 */ + { 0x2e064570, 0xc043242 }, /* 348 */ + { 0x2e064574, 0xf0c1201 }, /* 349 */ + { 0x2e064578, 0x1000140 }, /* 350 */ + { 0x2e06457c, 0xc000120 }, /* 351 */ + { 0x2e064580, 0x143 }, /* 352 */ + { 0x2e064584, 0x1000203 }, /* 353 */ + { 0x2e064588, 0x30217465 }, /* 354 */ + { 0x2e06458c, 0x8 }, /* 355 */ + { 0x2e064590, 0x2c302c3 }, /* 356 */ + { 0x2e064594, 0x2c302c3 }, /* 357 */ + { 0x2e064598, 0x2c302c3 }, /* 358 */ + { 0x2e06459c, 0x2c302c3 }, /* 359 */ + { 0x2e0645a0, 0x2c3 }, /* 360 */ + { 0x2e0645a4, 0x8000 }, /* 361 */ + { 0x2e0645a8, 0x800080 }, /* 362 */ + { 0x2e0645ac, 0x800080 }, /* 363 */ + { 0x2e0645b0, 0x800080 }, /* 364 */ + { 0x2e0645b4, 0x800080 }, /* 365 */ + { 0x2e0645b8, 0x800080 }, /* 366 */ + { 0x2e0645bc, 0x800080 }, /* 367 */ + { 0x2e0645c0, 0x800080 }, /* 368 */ + { 0x2e0645c4, 0x800080 }, /* 369 */ + { 0x2e0645c8, 0x6b0080 }, /* 370 */ + { 0x2e0645cc, 0x1a00001 }, /* 371 */ + { 0x2e0645d4, 0x10000 }, /* 373 */ + { 0x2e0645d8, 0x80200 }, /* 374 */ + { 0x2e064800, 0x4f0 }, /* 512 */ + { 0x2e064808, 0x1030200 }, /* 514 */ + { 0x2e064814, 0x3000000 }, /* 517 */ + { 0x2e064818, 0x1000001 }, /* 518 */ + { 0x2e06481c, 0x3000400 }, /* 519 */ + { 0x2e064820, 0x1 }, /* 520 */ + { 0x2e064824, 0x1 }, /* 521 */ + { 0x2e064830, 0x10000 }, /* 524 */ + { 0x2e064838, 0xc00004 }, /* 526 */ + { 0x2e06483c, 0xcc0008 }, /* 527 */ + { 0x2e064840, 0x660601 }, /* 528 */ + { 0x2e064844, 0x3 }, /* 529 */ + { 0x2e06484c, 0x1 }, /* 531 */ + { 0x2e064850, 0xaaaa }, /* 532 */ + { 0x2e064854, 0x5555 }, /* 533 */ + { 0x2e064858, 0xb5b5 }, /* 534 */ + { 0x2e06485c, 0x4a4a }, /* 535 */ + { 0x2e064860, 0x5656 }, /* 536 */ + { 0x2e064864, 0xa9a9 }, /* 537 */ + { 0x2e064868, 0xb7b7 }, /* 538 */ + { 0x2e06486c, 0x4848 }, /* 539 */ + { 0x2e064878, 0x8000000 }, /* 542 */ + { 0x2e06487c, 0x4010008 }, /* 543 */ + { 0x2e064880, 0x408 }, /* 544 */ + { 0x2e064884, 0x3102000 }, /* 545 */ + { 0x2e064888, 0xc0020 }, /* 546 */ + { 0x2e06488c, 0x10000 }, /* 547 */ + { 0x2e064890, 0x55555555 }, /* 548 */ + { 0x2e064894, 0xaaaaaaaa }, /* 549 */ + { 0x2e064898, 0x55555555 }, /* 550 */ + { 0x2e06489c, 0xaaaaaaaa }, /* 551 */ + { 0x2e0648a0, 0x5555 }, /* 552 */ + { 0x2e0648a4, 0x1000100 }, /* 553 */ + { 0x2e0648a8, 0x800180 }, /* 554 */ + { 0x2e0648ac, 0x1 }, /* 555 */ + { 0x2e064900, 0x4 }, /* 576 */ + { 0x2e06491c, 0x41f07ff }, /* 583 */ + { 0x2e064920, 0x1 }, /* 584 */ + { 0x2e064924, 0x1cc0800 }, /* 585 */ + { 0x2e064928, 0x3003cc08 }, /* 586 */ + { 0x2e06492c, 0x2000014e }, /* 587 */ + { 0x2e064930, 0x7ff0200 }, /* 588 */ + { 0x2e064934, 0x301 }, /* 589 */ + { 0x2e064940, 0x30000 }, /* 592 */ + { 0x2e064954, 0x2000000 }, /* 597 */ + { 0x2e064958, 0x51515042 }, /* 598 */ + { 0x2e06495c, 0x31c06000 }, /* 599 */ + { 0x2e064960, 0x6bf000a }, /* 600 */ + { 0x2e064964, 0xc0c000 }, /* 601 */ + { 0x2e064968, 0x1000000 }, /* 602 */ + { 0x2e06496c, 0x10001000 }, /* 603 */ + { 0x2e064970, 0xc043242 }, /* 604 */ + { 0x2e064974, 0xf0c1201 }, /* 605 */ + { 0x2e064978, 0x1000140 }, /* 606 */ + { 0x2e06497c, 0xc000120 }, /* 607 */ + { 0x2e064980, 0x143 }, /* 608 */ + { 0x2e064984, 0x1000203 }, /* 609 */ + { 0x2e064988, 0x75436012 }, /* 610 */ + { 0x2e06498c, 0x8 }, /* 611 */ + { 0x2e064990, 0x2c302c3 }, /* 612 */ + { 0x2e064994, 0x2c302c3 }, /* 613 */ + { 0x2e064998, 0x2c302c3 }, /* 614 */ + { 0x2e06499c, 0x2c302c3 }, /* 615 */ + { 0x2e0649a0, 0x2c3 }, /* 616 */ + { 0x2e0649a4, 0x8000 }, /* 617 */ + { 0x2e0649a8, 0x800080 }, /* 618 */ + { 0x2e0649ac, 0x800080 }, /* 619 */ + { 0x2e0649b0, 0x800080 }, /* 620 */ + { 0x2e0649b4, 0x800080 }, /* 621 */ + { 0x2e0649b8, 0x800080 }, /* 622 */ + { 0x2e0649bc, 0x800080 }, /* 623 */ + { 0x2e0649c0, 0x800080 }, /* 624 */ + { 0x2e0649c4, 0x800080 }, /* 625 */ + { 0x2e0649c8, 0x6b0080 }, /* 626 */ + { 0x2e0649cc, 0x1a00001 }, /* 627 */ + { 0x2e0649d4, 0x10000 }, /* 629 */ + { 0x2e0649d8, 0x80200 }, /* 630 */ + { 0x2e064c00, 0x4f0 }, /* 768 */ + { 0x2e064c08, 0x1030200 }, /* 770 */ + { 0x2e064c14, 0x3000000 }, /* 773 */ + { 0x2e064c18, 0x1000001 }, /* 774 */ + { 0x2e064c1c, 0x3000400 }, /* 775 */ + { 0x2e064c20, 0x1 }, /* 776 */ + { 0x2e064c24, 0x1 }, /* 777 */ + { 0x2e064c30, 0x10000 }, /* 780 */ + { 0x2e064c38, 0xc00004 }, /* 782 */ + { 0x2e064c3c, 0xcc0008 }, /* 783 */ + { 0x2e064c40, 0x660601 }, /* 784 */ + { 0x2e064c44, 0x3 }, /* 785 */ + { 0x2e064c4c, 0x1 }, /* 787 */ + { 0x2e064c50, 0xaaaa }, /* 788 */ + { 0x2e064c54, 0x5555 }, /* 789 */ + { 0x2e064c58, 0xb5b5 }, /* 790 */ + { 0x2e064c5c, 0x4a4a }, /* 791 */ + { 0x2e064c60, 0x5656 }, /* 792 */ + { 0x2e064c64, 0xa9a9 }, /* 793 */ + { 0x2e064c68, 0xb7b7 }, /* 794 */ + { 0x2e064c6c, 0x4848 }, /* 795 */ + { 0x2e064c78, 0x8000000 }, /* 798 */ + { 0x2e064c7c, 0x4010008 }, /* 799 */ + { 0x2e064c80, 0x408 }, /* 800 */ + { 0x2e064c84, 0x3102000 }, /* 801 */ + { 0x2e064c88, 0xc0020 }, /* 802 */ + { 0x2e064c8c, 0x10000 }, /* 803 */ + { 0x2e064c90, 0x55555555 }, /* 804 */ + { 0x2e064c94, 0xaaaaaaaa }, /* 805 */ + { 0x2e064c98, 0x55555555 }, /* 806 */ + { 0x2e064c9c, 0xaaaaaaaa }, /* 807 */ + { 0x2e064ca0, 0x5555 }, /* 808 */ + { 0x2e064ca4, 0x1000100 }, /* 809 */ + { 0x2e064ca8, 0x800180 }, /* 810 */ + { 0x2e064d00, 0x4 }, /* 832 */ + { 0x2e064d1c, 0x41f07ff }, /* 839 */ + { 0x2e064d20, 0x1 }, /* 840 */ + { 0x2e064d24, 0x1cc0800 }, /* 841 */ + { 0x2e064d28, 0x3003cc08 }, /* 842 */ + { 0x2e064d2c, 0x2000014e }, /* 843 */ + { 0x2e064d30, 0x7ff0200 }, /* 844 */ + { 0x2e064d34, 0x301 }, /* 845 */ + { 0x2e064d40, 0x30000 }, /* 848 */ + { 0x2e064d54, 0x2000000 }, /* 853 */ + { 0x2e064d58, 0x51515042 }, /* 854 */ + { 0x2e064d5c, 0x31c06000 }, /* 855 */ + { 0x2e064d60, 0x6bf000a }, /* 856 */ + { 0x2e064d64, 0xc0c000 }, /* 857 */ + { 0x2e064d68, 0x1000000 }, /* 858 */ + { 0x2e064d6c, 0x10001000 }, /* 859 */ + { 0x2e064d70, 0xc043242 }, /* 860 */ + { 0x2e064d74, 0xf0c1201 }, /* 861 */ + { 0x2e064d78, 0x1000140 }, /* 862 */ + { 0x2e064d7c, 0xc000120 }, /* 863 */ + { 0x2e064d80, 0x143 }, /* 864 */ + { 0x2e064d84, 0x1000203 }, /* 865 */ + { 0x2e064d88, 0x32017465 }, /* 866 */ + { 0x2e064d8c, 0x8 }, /* 867 */ + { 0x2e064d90, 0x2c302c3 }, /* 868 */ + { 0x2e064d94, 0x2c302c3 }, /* 869 */ + { 0x2e064d98, 0x2c302c3 }, /* 870 */ + { 0x2e064d9c, 0x2c302c3 }, /* 871 */ + { 0x2e064da0, 0x2c3 }, /* 872 */ + { 0x2e064da4, 0x8000 }, /* 873 */ + { 0x2e064da8, 0x800080 }, /* 874 */ + { 0x2e064dac, 0x800080 }, /* 875 */ + { 0x2e064db0, 0x800080 }, /* 876 */ + { 0x2e064db4, 0x800080 }, /* 877 */ + { 0x2e064db8, 0x800080 }, /* 878 */ + { 0x2e064dbc, 0x800080 }, /* 879 */ + { 0x2e064dc0, 0x800080 }, /* 880 */ + { 0x2e064dc4, 0x800080 }, /* 881 */ + { 0x2e064dc8, 0x6b0080 }, /* 882 */ + { 0x2e064dcc, 0x1a00001 }, /* 883 */ + { 0x2e064dd4, 0x10000 }, /* 885 */ + { 0x2e064dd8, 0x80200 }, /* 886 */ + { 0x2e065014, 0x100 }, /* 1029 */ + { 0x2e065018, 0x201 }, /* 1030 */ + { 0x2e06502c, 0x400000 }, /* 1035 */ + { 0x2e065030, 0x80 }, /* 1036 */ + { 0x2e065034, 0xdcba98 }, /* 1037 */ + { 0x2e065038, 0x3000000 }, /* 1038 */ + { 0x2e06504c, 0x2a }, /* 1043 */ + { 0x2e065050, 0x15 }, /* 1044 */ + { 0x2e065054, 0x15 }, /* 1045 */ + { 0x2e065058, 0x2a }, /* 1046 */ + { 0x2e06505c, 0x33 }, /* 1047 */ + { 0x2e065060, 0xc }, /* 1048 */ + { 0x2e065064, 0xc }, /* 1049 */ + { 0x2e065068, 0x33 }, /* 1050 */ + { 0x2e06506c, 0x543210 }, /* 1051 */ + { 0x2e065070, 0x3f0000 }, /* 1052 */ + { 0x2e065074, 0xf013f }, /* 1053 */ + { 0x2e065078, 0xf }, /* 1054 */ + { 0x2e06507c, 0x3cc }, /* 1055 */ + { 0x2e065080, 0x30000 }, /* 1056 */ + { 0x2e065084, 0x300 }, /* 1057 */ + { 0x2e065088, 0x300 }, /* 1058 */ + { 0x2e06508c, 0x300 }, /* 1059 */ + { 0x2e065090, 0x300 }, /* 1060 */ + { 0x2e065094, 0x300 }, /* 1061 */ + { 0x2e065098, 0x42080010 }, /* 1062 */ + { 0x2e06509c, 0x332 }, /* 1063 */ + { 0x2e0650a0, 0x2 }, /* 1064 */ + { 0x2e065414, 0x100 }, /* 1285 */ + { 0x2e065418, 0x201 }, /* 1286 */ + { 0x2e06542c, 0x400000 }, /* 1291 */ + { 0x2e065430, 0x80 }, /* 1292 */ + { 0x2e065434, 0xdcba98 }, /* 1293 */ + { 0x2e065438, 0x3000000 }, /* 1294 */ + { 0x2e06544c, 0x2a }, /* 1299 */ + { 0x2e065450, 0x15 }, /* 1300 */ + { 0x2e065454, 0x15 }, /* 1301 */ + { 0x2e065458, 0x2a }, /* 1302 */ + { 0x2e06545c, 0x33 }, /* 1303 */ + { 0x2e065460, 0xc }, /* 1304 */ + { 0x2e065464, 0xc }, /* 1305 */ + { 0x2e065468, 0x33 }, /* 1306 */ + { 0x2e06546c, 0x543210 }, /* 1307 */ + { 0x2e065470, 0x3f0000 }, /* 1308 */ + { 0x2e065474, 0xf013f }, /* 1309 */ + { 0x2e065478, 0xf }, /* 1310 */ + { 0x2e06547c, 0x3cc }, /* 1311 */ + { 0x2e065480, 0x30000 }, /* 1312 */ + { 0x2e065484, 0x300 }, /* 1313 */ + { 0x2e065488, 0x300 }, /* 1314 */ + { 0x2e06548c, 0x300 }, /* 1315 */ + { 0x2e065490, 0x300 }, /* 1316 */ + { 0x2e065494, 0x300 }, /* 1317 */ + { 0x2e065498, 0x42080010 }, /* 1318 */ + { 0x2e06549c, 0x332 }, /* 1319 */ + { 0x2e0654a0, 0x2 }, /* 1320 */ + { 0x2e065804, 0x100 }, /* 1537 */ + { 0x2e065814, 0x50000 }, /* 1541 */ + { 0x2e065818, 0x4000100 }, /* 1542 */ + { 0x2e06581c, 0x55 }, /* 1543 */ + { 0x2e06582c, 0xf0001 }, /* 1547 */ + { 0x2e065830, 0x280040 }, /* 1548 */ + { 0x2e065834, 0x5002 }, /* 1549 */ + { 0x2e065838, 0x10101 }, /* 1550 */ + { 0x2e065840, 0x90e0000 }, /* 1552 */ + { 0x2e065844, 0x101010f }, /* 1553 */ + { 0x2e065848, 0x10f0004 }, /* 1554 */ + { 0x2e065854, 0x64 }, /* 1557 */ + { 0x2e06585c, 0x1000000 }, /* 1559 */ + { 0x2e065860, 0x8040201 }, /* 1560 */ + { 0x2e065864, 0x2010201 }, /* 1561 */ + { 0x2e065868, 0xf0f0f }, /* 1562 */ + { 0x2e06586c, 0x241342 }, /* 1563 */ + { 0x2e065874, 0x1020000 }, /* 1565 */ + { 0x2e065878, 0x701 }, /* 1566 */ + { 0x2e06587c, 0x54 }, /* 1567 */ + { 0x2e065880, 0x4102000 }, /* 1568 */ + { 0x2e065884, 0x24410 }, /* 1569 */ + { 0x2e065888, 0x4410 }, /* 1570 */ + { 0x2e06588c, 0x4410 }, /* 1571 */ + { 0x2e065890, 0x4410 }, /* 1572 */ + { 0x2e065894, 0x4410 }, /* 1573 */ + { 0x2e065898, 0x4410 }, /* 1574 */ + { 0x2e06589c, 0x4410 }, /* 1575 */ + { 0x2e0658a0, 0x4410 }, /* 1576 */ + { 0x2e0658a4, 0x4410 }, /* 1577 */ + { 0x2e0658b0, 0x60000 }, /* 1580 */ + { 0x2e0658b8, 0x66 }, /* 1582 */ + { 0x2e0658bc, 0x10000 }, /* 1583 */ + { 0x2e0658c0, 0x8 }, /* 1584 */ + { 0x2e0658d8, 0x3000000 }, /* 1590 */ + { 0x2e0658e8, 0x4102006 }, /* 1594 */ + { 0x2e0658ec, 0x41020 }, /* 1595 */ + { 0x2e0658f0, 0x1c98c98 }, /* 1596 */ + { 0x2e0658f4, 0x3f400000 }, /* 1597 */ + { 0x2e0658f8, 0x3f3f1f3f }, /* 1598 */ + { 0x2e0658fc, 0x1f }, /* 1599 */ + { 0x2e06590c, 0x1 }, /* 1603 */ + { 0x2e06591c, 0x1 }, /* 1607 */ + { 0x2e065920, 0x76543210 }, /* 1608 */ + { 0x2e065924, 0x10198 }, /* 1609 */ + { 0x2e065934, 0x40700 }, /* 1613 */ + { 0x2e06594c, 0x2 }, /* 1619 */ + { 0x2e065958, 0xf3c3 }, /* 1622 */ + { 0x2e065964, 0x11542 }, /* 1625 */ + { 0x2e065968, 0x30209bf }, /* 1626 */ + { 0x2e06596c, 0x30000 }, /* 1627 */ + { 0x2e065970, 0x3000300 }, /* 1628 */ + { 0x2e065974, 0x3000300 }, /* 1629 */ + { 0x2e065978, 0x3000300 }, /* 1630 */ + { 0x2e06597c, 0x3000300 }, /* 1631 */ + { 0x2e065980, 0x300 }, /* 1632 */ + { 0x2e065984, 0x300 }, /* 1633 */ + { 0x2e065988, 0x300 }, /* 1634 */ + { 0x2e06598c, 0x337cc }, /* 1635 */ + { 0x2e065990, 0x8 }, /* 1636 */ + { 0x2e065994, 0x1b7 }, /* 1637 */ + { 0x2e06599c, 0x1b7 }, /* 1639 */ + { 0x2e0659a4, 0x1b700 }, /* 1641 */ + { 0x2e0659a8, 0x1980000 }, /* 1642 */ + { 0x2e0659ac, 0x1b7cc }, /* 1643 */ + { 0x2e0659b4, 0x1b700 }, /* 1645 */ + { 0x2e0659b8, 0x1980000 }, /* 1646 */ + { 0x2e0659bc, 0x1b700 }, /* 1647 */ + { 0x2e0659c0, 0x1980000 }, /* 1648 */ + { 0x2e0659c4, 0x1b700 }, /* 1649 */ + { 0x2e0659c8, 0x1980000 }, /* 1650 */ + { 0x2e0659cc, 0x1b700 }, /* 1651 */ + { 0x2e0659d0, 0x1980000 }, /* 1652 */ + { 0x2e0659d4, 0x20040003 }, /* 1653 */ +}; + +/** PHY_F2 settings **/ +struct dram_cfg_param ddr_phy_f2_cfg[] = { +}; + +/* ddr timing config params */ +struct dram_timing_info2 dram_timing = { + .ctl_cfg = ddr_ctl_cfg, + .ctl_cfg_num = ARRAY_SIZE(ddr_ctl_cfg), + .pi_cfg = ddr_pi_cfg, + .pi_cfg_num = ARRAY_SIZE(ddr_pi_cfg), + .phy_f1_cfg = ddr_phy_f1_cfg, + .phy_f1_cfg_num = ARRAY_SIZE(ddr_phy_f1_cfg), + .phy_f2_cfg = ddr_phy_f2_cfg, + .phy_f2_cfg_num = ARRAY_SIZE(ddr_phy_f2_cfg), + .fsp_table = { 96, 528 }, +}; diff --git a/board/nxp/imx8ulp_evk/spl.c b/board/nxp/imx8ulp_evk/spl.c new file mode 100644 index 00000000000..fe637077928 --- /dev/null +++ b/board/nxp/imx8ulp_evk/spl.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_dram_init(void) +{ + /* Reboot in dual boot setting no need to init ddr again */ + bool ddr_enable = pcc_clock_is_enable(5, LPDDR4_PCC5_SLOT); + + if (!ddr_enable) { + init_clk_ddr(); + ddr_init(&dram_timing); + } else { + /* reinit pfd/pfddiv and lpavnic except pll4*/ + cgc2_pll4_init(false); + } +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOOTROM; +} + +int power_init_board(void) +{ + if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) { + /* Set buck3 to 0.9v LD */ + upower_pmic_i2c_write(0x22, 0x18); + } else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) { + /* Set buck3 to 1.0v ND */ + upower_pmic_i2c_write(0x22, 0x20); + } else { + /* Set buck3 to 1.1v OD */ + upower_pmic_i2c_write(0x22, 0x28); + } + + return 0; +} + +void display_ele_fw_version(void) +{ + u32 fw_version, sha1, res; + int ret; + + ret = ele_get_fw_version(&fw_version, &sha1, &res); + if (ret) { + printf("ele get firmware version failed %d, 0x%x\n", ret, res); + } else { + printf("ELE firmware version %u.%u.%u-%x", + (fw_version & (0x00ff0000)) >> 16, + (fw_version & (0x0000fff0)) >> 4, + (fw_version & (0x0000000f)), sha1); + ((fw_version & (0x80000000)) >> 31) == 1 ? puts("-dirty\n") : puts("\n"); + } +} + +void spl_board_init(void) +{ + u32 res; + int ret; + + ret = imx8ulp_dm_post_init(); + if (ret) + return; + + board_early_init_f(); + + preloader_console_init(); + + puts("Normal Boot\n"); + + display_ele_fw_version(); + + /* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */ + + /* Load the lposc fuse to work around ROM issue. The fuse depends on S400 to read. */ + if (is_soc_rev(CHIP_REV_1_0)) + load_lposc_fuse(); + + upower_init(); + + power_init_board(); + + clock_init_late(); + + /* This must place after upower init, so access to MDA and MRC are valid */ + /* Init XRDC MDA */ + xrdc_init_mda(); + + /* Init XRDC MRC for VIDEO, DSP domains */ + xrdc_init_mrc(); + + xrdc_init_pdac_msc(); + + /* DDR initialization */ + spl_dram_init(); + + /* Call it after PS16 power up */ + set_lpav_qos(); + + /* Enable A35 access to the CAAM */ + ret = ele_release_caam(0x7, &res); + if (ret) + printf("ele release caam failed %d, 0x%x\n", ret, res); + + /* + * RNG start only available on the A1 soc revision. + * Check some JTAG register for the SoC revision. + */ + if (!is_soc_rev(CHIP_REV_1_0)) { + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); + } +} + +void board_init_f(ulong dummy) +{ + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + board_init_r(NULL, 0); +} diff --git a/board/nxp/imx91_evk/Kconfig b/board/nxp/imx91_evk/Kconfig new file mode 100644 index 00000000000..07baf63932c --- /dev/null +++ b/board/nxp/imx91_evk/Kconfig @@ -0,0 +1,19 @@ +if TARGET_IMX91_11X11_EVK + +config SYS_BOARD + default "imx91_evk" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "imx91_evk" + +config IMX91_EVK_LPDDR4 + bool "Using LPDDR4 Timing and PMIC voltage" + default y + select IMX9_LPDDR4X + help + Select the LPDDR4 timing and 1.1V VDDQ + +endif diff --git a/board/nxp/imx91_evk/MAINTAINERS b/board/nxp/imx91_evk/MAINTAINERS new file mode 100644 index 00000000000..ed701dd6838 --- /dev/null +++ b/board/nxp/imx91_evk/MAINTAINERS @@ -0,0 +1,7 @@ +i.MX91 11x11 EVK BOARD +M: Peng Fan +S: Maintained +F: board/nxp/imx91_evk/ +F: include/configs/imx91_evk.h +F: configs/imx91_11x11_evk_defconfig +F: configs/imx91_11x11_evk_inline_ecc_defconfig diff --git a/board/nxp/imx91_evk/Makefile b/board/nxp/imx91_evk/Makefile new file mode 100644 index 00000000000..a96228af959 --- /dev/null +++ b/board/nxp/imx91_evk/Makefile @@ -0,0 +1,16 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx91_evk.o + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +ifdef CONFIG_IMX9_DRAM_INLINE_ECC +obj-$(CONFIG_IMX91_EVK_LPDDR4) += lpddr4_timing_2400mts_ecc.o lpddr4_timing_1600mts_ecc.o +else +obj-$(CONFIG_IMX91_EVK_LPDDR4) += lpddr4_timing_2400mts.o lpddr4_timing_1600mts.o +endif +endif diff --git a/board/nxp/imx91_evk/imx91_evk.c b/board/nxp/imx91_evk/imx91_evk.c new file mode 100644 index 00000000000..fca2521081b --- /dev/null +++ b/board/nxp/imx91_evk/imx91_evk.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +#include +#include +#include + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "11X11_EVK"); + env_set("board_rev", "iMX93"); +#endif + return 0; +} diff --git a/board/nxp/imx91_evk/imx91_evk.env b/board/nxp/imx91_evk/imx91_evk.env new file mode 100644 index 00000000000..6c10784cf61 --- /dev/null +++ b/board/nxp/imx91_evk/imx91_evk.env @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +boot_targets=mmc0 mmc1 +boot_fit=no +bootm_size=0x10000000 +cntr_addr=0x98000000 +cntr_file=os_cntr_signed.bin +console=ttyLP0,115200 earlycon +fdt_addr_r=0x83000000 +fdt_addr=0x83000000 +fdtfile=CONFIG_DEFAULT_FDT_FILE +image=Image +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk1p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} +prepare_mcore=setenv mcore_clk clk-imx93.mcore_booted +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} +auth_os=auth_cntr ${cntr_addr} +sec_boot=no +boot_os=booti ${loadaddr} - ${fdt_addr_r} +mmcboot= + echo Booting from mmc ...; + run mmcargs; + if test ${sec_boot} = yes; then + if run true; then + run boot_os; + else + echo ERR: failed to authenticate; + fi; + else + if run loadfdt; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; +netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot= + echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if test ${sec_boot} = yes; then + ${get_cmd} ${cntr_addr} ${cntr_file}; + if true; then + run boot_os; + else + echo ERR: failed to authenticate; + fi; + else + ${get_cmd} ${loadaddr} ${image}; + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; +bsp_bootcmd= + echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; + if mmc rescan; then + if run loadbootscript; then + run bootscript; + else + if test ${sec_boot} = yes; then + if run loadcntr; then + run mmcboot; + else + run netboot; + fi; + else + if run loadimage; then + run mmcboot; + else + run netboot; + fi; + fi; + fi; + fi; +scriptaddr=0x83500000 diff --git a/board/nxp/imx91_evk/lpddr4_timing_1600mts.c b/board/nxp/imx91_evk/lpddr4_timing_1600mts.c new file mode 100644 index 00000000000..45e19daa028 --- /dev/null +++ b/board/nxp/imx91_evk/lpddr4_timing_1600mts.c @@ -0,0 +1,1995 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2024 NXP + * + * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include +#include + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000ff}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000512}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x02121100}, + {0x4e300104, 0xF866000C}, + {0x4e300108, 0xF2FA8088}, + {0x4e30010C, 0x0061E1A0}, + {0x4e300124, 0x0C340000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30700000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x00000011}, + {0x4e300254, 0x00900090}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x0F220F09}, + {0x4e300304, 0x00901008}, + {0x4e300308, 0x063C061A}, + }, + { + {0x01, 0xA4}, + {0x02, 0x52}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00091000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x81820A48}, + {0x4e30010C, 0x00310110}, + {0x4e300124, 0x061A0000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30100000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000009}, + {0x4e300254, 0x00440044}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00061000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E62FA48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00340034}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 1, + }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0xb}, + {0x1200c5, 0x3}, + {0x2200c5, 0x7}, + {0x2002e, 0x1}, + {0x12002e, 0x1}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe3f}, + {0x10149, 0xe3f}, + {0x11049, 0xe3f}, + {0x11149, 0xe3f}, + {0x110049, 0xe3f}, + {0x110149, 0xe3f}, + {0x111049, 0xe3f}, + {0x111149, 0xe3f}, + {0x210049, 0xe3f}, + {0x210149, 0xe3f}, + {0x211049, 0xe3f}, + {0x211149, 0xe3f}, + {0x43, 0x7f}, + {0x1043, 0x7f}, + {0x2043, 0x7f}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x11}, + {0x2009b, 0x2}, + {0x20008, 0x190}, + {0x120008, 0xc8}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x41}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + 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{0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x640}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x3352}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x3352}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x320}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3309}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3309}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4800}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4800}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3309}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3309}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x640}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x3352}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x3352}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x1c2}, + {0x2000c, 0x64}, + {0x2000d, 0x3e8}, + {0x2000e, 0x2c}, + {0x12000b, 0xe1}, + {0x12000c, 0x32}, + {0x12000d, 0x1f4}, + {0x12000e, 0x10}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1600mts 1D */ + .drate = 1600, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 800mts 1D */ + .drate = 800, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 1600mts 2D */ + .drate = 1600, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_1600mts = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1600, 800, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/nxp/imx91_evk/lpddr4_timing_1600mts_ecc.c b/board/nxp/imx91_evk/lpddr4_timing_1600mts_ecc.c new file mode 100644 index 00000000000..4594ab68aa0 --- /dev/null +++ b/board/nxp/imx91_evk/lpddr4_timing_1600mts_ecc.c @@ -0,0 +1,1995 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2024 NXP + * + * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include +#include + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000ef}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000512}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1012}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30d00}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0xc0000000}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x02121100}, + {0x4e300104, 0xF866000C}, + {0x4e300108, 0xF2FA8088}, + {0x4e30010C, 0x0061E1A0}, + {0x4e300124, 0x0C340000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30700000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x00000011}, + {0x4e300254, 0x00900090}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x0F220F09}, + {0x4e300304, 0x00901008}, + {0x4e300308, 0x063C061A}, + }, + { + {0x01, 0xA4}, + {0x02, 0x52}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00091000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x81820A48}, + {0x4e30010C, 0x00310110}, + {0x4e300124, 0x061A0000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30100000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000009}, + {0x4e300254, 0x00440044}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00061000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E62FA48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00340034}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 1, + }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0xb}, + {0x1200c5, 0x3}, + {0x2200c5, 0x7}, + {0x2002e, 0x1}, + {0x12002e, 0x1}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe3f}, + {0x10149, 0xe3f}, + {0x11049, 0xe3f}, + {0x11149, 0xe3f}, + {0x110049, 0xe3f}, + {0x110149, 0xe3f}, + {0x111049, 0xe3f}, + {0x111149, 0xe3f}, + {0x210049, 0xe3f}, + {0x210149, 0xe3f}, + {0x211049, 0xe3f}, + {0x211149, 0xe3f}, + {0x43, 0x7f}, + {0x1043, 0x7f}, + {0x2043, 0x7f}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x11}, + {0x2009b, 0x2}, + {0x20008, 0x190}, + {0x120008, 0xc8}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x41}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90182, 0x0}, + {0x90183, 0x0}, + {0x90184, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x12000b, 0x0}, + {0x12000c, 0x0}, + {0x12000d, 0x0}, + {0x12000e, 0x0}, + {0x22000b, 0x0}, + {0x22000c, 0x0}, + {0x22000d, 0x0}, + {0x22000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x120010, 0x0}, + {0x120011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x140080, 0x0}, + {0x140081, 0x0}, + {0x140082, 0x0}, + {0x140083, 0x0}, + {0x140084, 0x0}, + {0x140085, 0x0}, + {0x240080, 0x0}, + {0x240081, 0x0}, + {0x240082, 0x0}, + {0x240083, 0x0}, + {0x240084, 0x0}, + {0x240085, 0x0}, + {0x400fd, 0x0}, + {0x400f1, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x640}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x3352}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x3352}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x320}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3309}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3309}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4800}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4800}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3309}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3309}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x640}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x3352}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x3352}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x1c2}, + {0x2000c, 0x64}, + {0x2000d, 0x3e8}, + {0x2000e, 0x2c}, + {0x12000b, 0xe1}, + {0x12000c, 0x32}, + {0x12000d, 0x1f4}, + {0x12000e, 0x10}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1600mts 1D */ + .drate = 1600, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 800mts 1D */ + .drate = 800, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 1600mts 2D */ + .drate = 1600, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_1600mts = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1600, 800, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/nxp/imx91_evk/lpddr4_timing_2400mts.c b/board/nxp/imx91_evk/lpddr4_timing_2400mts.c new file mode 100644 index 00000000000..e0e6f5da3d6 --- /dev/null +++ b/board/nxp/imx91_evk/lpddr4_timing_2400mts.c @@ -0,0 +1,1995 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2024 NXP + * + * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include +#include + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000ff}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000512}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x135C2110}, + {0x4e300104, 0xF8990011}, + {0x4e300108, 0x636E08CC}, + {0x4e30010C, 0x0061E070}, + {0x4e300124, 0x124E0000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x31D00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x0000001A}, + {0x4e300254, 0x00DC00DC}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x1633160D}, + {0x4e300304, 0x00DC180C}, + {0x4e300308, 0x0C3C0927}, + }, + { + {0x01, 0xC4}, + {0x02, 0x24}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x010D1100}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0xBABAC068}, + {0x4e30010C, 0x00610158}, + {0x4e300124, 0x09270000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30400000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x0000000D}, + {0x4e300254, 0x006A006A}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xA4}, + {0x02, 0x52}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00061000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E62FA48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00340034}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 1, + }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0xa}, + {0x1200c5, 0x2}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x1}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe3f}, + {0x10149, 0xe3f}, + {0x11049, 0xe3f}, + {0x11149, 0xe3f}, + {0x110049, 0xe3f}, + {0x110149, 0xe3f}, + {0x111049, 0xe3f}, + {0x111149, 0xe3f}, + {0x210049, 0xe3f}, + {0x210149, 0xe3f}, + {0x211049, 0xe3f}, + {0x211149, 0xe3f}, + {0x43, 0x7f}, + {0x1043, 0x7f}, + {0x2043, 0x7f}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x11}, + {0x2009b, 0x2}, + {0x20008, 0x258}, + {0x120008, 0x12c}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x41}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 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0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x3324}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x3324}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x4b0}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x3352}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x3352}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4800}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4800}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3309}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3309}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x3324}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x3324}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x2a3}, + {0x2000c, 0x96}, + {0x2000d, 0x5dc}, + {0x2000e, 0x2c}, + {0x12000b, 0x152}, + {0x12000c, 0x4b}, + {0x12000d, 0x2ee}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1200mts 1D */ + .drate = 1200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1200, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/nxp/imx91_evk/lpddr4_timing_2400mts_ecc.c b/board/nxp/imx91_evk/lpddr4_timing_2400mts_ecc.c new file mode 100644 index 00000000000..811687170c3 --- /dev/null +++ b/board/nxp/imx91_evk/lpddr4_timing_2400mts_ecc.c @@ -0,0 +1,1995 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2024 NXP + * + * Code generated with DDR Tool v3.3.0_1.9-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include +#include + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000ef}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000512}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1012}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30d00}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0xc0000000}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x135C2110}, + {0x4e300104, 0xF8990011}, + {0x4e300108, 0x636E08CC}, + {0x4e30010C, 0x0061E070}, + {0x4e300124, 0x124E0000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x31D00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x0000001A}, + {0x4e300254, 0x00DC00DC}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x1633160D}, + {0x4e300304, 0x00DC180C}, + {0x4e300308, 0x0C3C0927}, + }, + { + {0x01, 0xC4}, + {0x02, 0x24}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x010D1100}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0xBABAC068}, + {0x4e30010C, 0x00610158}, + {0x4e300124, 0x09270000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30400000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x0000000D}, + {0x4e300254, 0x006A006A}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xA4}, + {0x02, 0x52}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00061000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E62FA48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00340034}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 1, + }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0xa}, + {0x1200c5, 0x2}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x1}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe3f}, + {0x10149, 0xe3f}, + {0x11049, 0xe3f}, + {0x11149, 0xe3f}, + {0x110049, 0xe3f}, + {0x110149, 0xe3f}, + {0x111049, 0xe3f}, + {0x111149, 0xe3f}, + {0x210049, 0xe3f}, + {0x210149, 0xe3f}, + {0x211049, 0xe3f}, + {0x211149, 0xe3f}, + {0x43, 0x7f}, + {0x1043, 0x7f}, + {0x2043, 0x7f}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x11}, + {0x2009b, 0x2}, + {0x20008, 0x258}, + {0x120008, 0x12c}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x41}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90182, 0x0}, + {0x90183, 0x0}, + {0x90184, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x12000b, 0x0}, + {0x12000c, 0x0}, + {0x12000d, 0x0}, + {0x12000e, 0x0}, + {0x22000b, 0x0}, + {0x22000c, 0x0}, + {0x22000d, 0x0}, + {0x22000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x120010, 0x0}, + {0x120011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x140080, 0x0}, + {0x140081, 0x0}, + {0x140082, 0x0}, + {0x140083, 0x0}, + {0x140084, 0x0}, + {0x140085, 0x0}, + {0x240080, 0x0}, + {0x240081, 0x0}, + {0x240082, 0x0}, + {0x240083, 0x0}, + {0x240084, 0x0}, + {0x240085, 0x0}, + {0x400fd, 0x0}, + {0x400f1, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x3324}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x3324}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x4b0}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x3352}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x3352}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4800}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4800}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3309}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3309}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x3324}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x3324}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x2a3}, + {0x2000c, 0x96}, + {0x2000d, 0x5dc}, + {0x2000e, 0x2c}, + {0x12000b, 0x152}, + {0x12000c, 0x4b}, + {0x12000d, 0x2ee}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1200mts 1D */ + .drate = 1200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1200, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/nxp/imx91_evk/spl.c b/board/nxp/imx91_evk/spl.c new file mode 100644 index 00000000000..2aa63a61b74 --- /dev/null +++ b/board/nxp/imx91_evk/spl.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_board_init(void) +{ + int ret; + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); + + puts("Normal Boot\n"); +} + +extern struct dram_timing_info dram_timing_1600mts; +void spl_dram_init(void) +{ + struct dram_timing_info *ptiming = &dram_timing; + + if (is_voltage_mode(VOLT_LOW_DRIVE)) + ptiming = &dram_timing_1600mts; + + printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate); + ddr_init(ptiming); +} + +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int val = 0, buck_val; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("ERROR: Get PMIC PCA9451A failed!\n"); + return ret; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* enable DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + ret = pmic_reg_read(dev, PCA9450_PWR_CTRL); + if (ret < 0) + return ret; + + val = ret; + + if (is_voltage_mode(VOLT_LOW_DRIVE)) { + buck_val = 0x0c; /* 0.8V for Low drive mode */ + printf("PMIC: Low Drive Voltage Mode\n"); + } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) { + buck_val = 0x10; /* 0.85V for Nominal drive mode */ + printf("PMIC: Nominal Voltage Mode\n"); + } else { + buck_val = 0x14; /* 0.9V for Over drive mode */ + printf("PMIC: Over Drive Voltage Mode\n"); + } + + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val); + } else { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4); + } + + /* Set VDDQ to 1.1V from buck2 (buck2 not used for iMX91 EVK) */ + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28); + + /* set standby voltage to 0.65V */ + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); + + /* I2C_LT_EN*/ + pmic_reg_write(dev, 0xa, 0x3); + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + spl_early_init(); + + preloader_console_init(); + + ret = imx9_probe_mu(); + if (ret) { + printf("Fail to init ELE API\n"); + } else { + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + } + + clock_init_late(); + + power_init_board(); + + if (!is_voltage_mode(VOLT_LOW_DRIVE)) + set_arm_clk(get_cpu_speed_grade_hz()); + + /* Init power of mix */ + soc_power_init(); + + /* Setup TRDC for DDR access */ + trdc_init(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/board/nxp/imx91_frdm/Kconfig b/board/nxp/imx91_frdm/Kconfig new file mode 100644 index 00000000000..d536407531a --- /dev/null +++ b/board/nxp/imx91_frdm/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX91_11X11_FRDM + +config SYS_BOARD + default "imx91_frdm" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "imx91_frdm" + +endif diff --git a/board/nxp/imx91_frdm/MAINTAINERS b/board/nxp/imx91_frdm/MAINTAINERS new file mode 100644 index 00000000000..19e8b8421ec --- /dev/null +++ b/board/nxp/imx91_frdm/MAINTAINERS @@ -0,0 +1,7 @@ +FRDM-IMX91 BOARD +M: Joseph Guo +S: Maintained +F: board/nxp/imx91_frdm/ +F: include/configs/imx91_frdm.h +F: configs/imx91_11x11_frdm_defconfig +F: configs/imx91_11x11_frdm_inline_ecc_defconfig diff --git a/board/nxp/imx91_frdm/Makefile b/board/nxp/imx91_frdm/Makefile new file mode 100644 index 00000000000..75510b13b44 --- /dev/null +++ b/board/nxp/imx91_frdm/Makefile @@ -0,0 +1,16 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx91_frdm.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +ifdef CONFIG_IMX9_DRAM_INLINE_ECC +obj-y += lpddr4_2400mts_ecc_1gb_timing.o lpddr4_2400mts_ecc_2gb_timing.o +else +obj-y += lpddr4_2400mts_1gb_timing.o lpddr4_2400mts_2gb_timing.o +endif +endif diff --git a/board/nxp/imx91_frdm/imx91_frdm.c b/board/nxp/imx91_frdm/imx91_frdm.c new file mode 100644 index 00000000000..14ad464ded1 --- /dev/null +++ b/board/nxp/imx91_frdm/imx91_frdm.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include +#include +#include +#include + +#define TCPC_ALERT 0x10 +#define TCPC_ALERT_MASK 0x12 +#define TCPC_FAULT_STATUS_MASK 0x15 +#define USB_I2C_BUS 2 +#define USB_I2C_ADDR 0x50 + +/* + * Since tcpc driver is not upstream. PTN5110 interrupt will cause + * kernel panic because nobody cares the interrupt. So add workaround here. + * Clear PTN5110 USB Power Delivery controller alert status by + * masking interrupts and clearing pending alerts via I2C communication. + * This is typically called during board initialization to ensure the USB PD + * controller starts in a clean state without any stale alert conditions. + */ +static int clear_pd_alert(void) +{ + struct udevice *bus; + struct udevice *i2c_dev = NULL; + int ret; + u8 buffer_0[2] = {0, 0}; + u8 buffer_1[2] = {0xff, 0xff}; + + ret = uclass_get_device_by_seq(UCLASS_I2C, USB_I2C_BUS, &bus); + if (ret) { + printf("Failed to get I2C bus %d\n", USB_I2C_BUS); + return ret; + } + + ret = dm_i2c_probe(bus, USB_I2C_ADDR, 0, &i2c_dev); + if (ret) { + printf("Can't find USB PD device at 0x%02x\n", USB_I2C_ADDR); + return ret; + } + + /* Mask all alert status*/ + ret = dm_i2c_write(i2c_dev, TCPC_ALERT_MASK, buffer_0, 2); + if (ret) { + printf("%s dm_i2c_write failed: %d\n", __func__, ret); + return ret; + } + + ret = dm_i2c_write(i2c_dev, TCPC_FAULT_STATUS_MASK, buffer_0, 2); + if (ret) { + printf("%s dm_i2c_write failed: %d\n", __func__, ret); + return ret; + } + + ret = dm_i2c_write(i2c_dev, TCPC_ALERT, buffer_1, 2); + if (ret) { + printf("%s dm_i2c_write failed: %d\n", __func__, ret); + return ret; + } + + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + board_late_mmc_env_init(); + + env_set("sec_boot", "no"); + + if (IS_ENABLED(CONFIG_AHAB_BOOT)) + env_set("sec_boot", "yes"); + + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + env_set("board_name", "11X11_FRDM"); + env_set("board_rev", "iMX91"); + } + + clear_pd_alert(); + return 0; +} diff --git a/board/nxp/imx91_frdm/imx91_frdm.env b/board/nxp/imx91_frdm/imx91_frdm.env new file mode 100644 index 00000000000..b0450ff576c --- /dev/null +++ b/board/nxp/imx91_frdm/imx91_frdm.env @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +boot_targets=mmc0 mmc1 +boot_fit=no +bootm_size=0x10000000 +cntr_addr=0x98000000 +cntr_file=os_cntr_signed.bin +console=ttyLP0,115200 earlycon +fdt_addr_r=0x83000000 +fdt_addr=0x83000000 +fdtfile=CONFIG_DEFAULT_FDT_FILE +image=Image +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk1p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} +auth_os=auth_cntr ${cntr_addr} +sec_boot=no +boot_os=booti ${loadaddr} - ${fdt_addr_r} +mmcboot= + echo Booting from mmc ...; + run mmcargs; + if test ${sec_boot} = yes; then + if run true; then + run boot_os; + else + echo ERR: failed to authenticate; + fi; + else + if run loadfdt; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; +netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot= + echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if test ${sec_boot} = yes; then + ${get_cmd} ${cntr_addr} ${cntr_file}; + if true; then + run boot_os; + else + echo ERR: failed to authenticate; + fi; + else + ${get_cmd} ${loadaddr} ${image}; + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; +bsp_bootcmd= + echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; + if mmc rescan; then + if run loadbootscript; then + run bootscript; + else + if test ${sec_boot} = yes; then + if run loadcntr; then + run mmcboot; + else + run netboot; + fi; + else + if run loadimage; then + run mmcboot; + else + run netboot; + fi; + fi; + fi; + fi; +scriptaddr=0x83500000 diff --git a/board/nxp/imx91_frdm/lpddr4_2400mts_1gb_timing.c b/board/nxp/imx91_frdm/lpddr4_2400mts_1gb_timing.c new file mode 100644 index 00000000000..0a52cb9762f --- /dev/null +++ b/board/nxp/imx91_frdm/lpddr4_2400mts_1gb_timing.c @@ -0,0 +1,1996 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 NXP + * + * Code generated with DDR Tool v3.3.0_1.8-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include +#include + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000bf}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000412}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x13542110}, + {0x4e300104, 0xF8990011}, + {0x4e300108, 0x636E88CC}, + {0x4e30010C, 0x00614070}, + {0x4e300124, 0x124E0000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x31D00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x0000001A}, + {0x4e300254, 0x00A000A0}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x1633160D}, + {0x4e300304, 0x00A0180C}, + {0x4e300308, 0x0C280927}, + }, + { + {0x01, 0xC4}, + {0x02, 0x24}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x010A1100}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0xBABA0068}, + {0x4e30010C, 0x00610158}, + {0x4e300124, 0x09270000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30400000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x0000000D}, + {0x4e300254, 0x004C004C}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xA4}, + {0x02, 0x52}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00051000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E620A48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00240024}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 1, + }, + +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0xa}, + {0x1200c5, 0x2}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x1}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe3f}, + {0x10149, 0xe3f}, + {0x11049, 0xe3f}, + {0x11149, 0xe3f}, + {0x110049, 0xe3f}, + {0x110149, 0xe3f}, + {0x111049, 0xe3f}, + {0x111149, 0xe3f}, + {0x210049, 0xe3f}, + {0x210149, 0xe3f}, + {0x211049, 0xe3f}, + {0x211149, 0xe3f}, + {0x43, 0x7f}, + {0x1043, 0x7f}, + {0x2043, 0x7f}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x11}, + {0x2009b, 0x2}, + {0x20008, 0x258}, + {0x120008, 0x12c}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x41}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90182, 0x0}, + {0x90183, 0x0}, + {0x90184, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x12000b, 0x0}, + {0x12000c, 0x0}, + {0x12000d, 0x0}, + {0x12000e, 0x0}, + {0x22000b, 0x0}, + {0x22000c, 0x0}, + {0x22000d, 0x0}, + {0x22000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x120010, 0x0}, + {0x120011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x140080, 0x0}, + {0x140081, 0x0}, + {0x140082, 0x0}, + {0x140083, 0x0}, + {0x140084, 0x0}, + {0x140085, 0x0}, + {0x240080, 0x0}, + {0x240081, 0x0}, + {0x240082, 0x0}, + {0x240083, 0x0}, + {0x240084, 0x0}, + {0x240085, 0x0}, + {0x400fd, 0x0}, + {0x400f1, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x3324}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x3324}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x4b0}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x3352}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x3352}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4800}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4800}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3309}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3309}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x3324}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x3324}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x2a3}, + {0x2000c, 0x96}, + {0x2000d, 0x5dc}, + {0x2000e, 0x2c}, + {0x12000b, 0x152}, + {0x12000c, 0x4b}, + {0x12000d, 0x2ee}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1200mts 1D */ + .drate = 1200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_1GB = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1200, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/nxp/imx91_frdm/lpddr4_2400mts_2gb_timing.c b/board/nxp/imx91_frdm/lpddr4_2400mts_2gb_timing.c new file mode 100644 index 00000000000..017677fbbe9 --- /dev/null +++ b/board/nxp/imx91_frdm/lpddr4_2400mts_2gb_timing.c @@ -0,0 +1,1996 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 NXP + * + * Code generated with DDR Tool v3.3.0_1.8-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include +#include + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000ff}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000512}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x135C2110}, + {0x4e300104, 0xF8990011}, + {0x4e300108, 0x636E08CC}, + {0x4e30010C, 0x00614070}, + {0x4e300124, 0x124E0000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x31D00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x0000001A}, + {0x4e300254, 0x00DC00DC}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x1633160D}, + {0x4e300304, 0x00DC180C}, + {0x4e300308, 0x0C280927}, + }, + { + {0x01, 0xC4}, + {0x02, 0x24}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x010D1100}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0xBABAC068}, + {0x4e30010C, 0x00610158}, + {0x4e300124, 0x09270000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30400000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x0000000D}, + {0x4e300254, 0x006A006A}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xA4}, + {0x02, 0x52}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00061000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E62FA48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00340034}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 1, + }, + +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0xa}, + {0x1200c5, 0x2}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x1}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe3f}, + {0x10149, 0xe3f}, + {0x11049, 0xe3f}, + {0x11149, 0xe3f}, + {0x110049, 0xe3f}, + {0x110149, 0xe3f}, + {0x111049, 0xe3f}, + {0x111149, 0xe3f}, + {0x210049, 0xe3f}, + {0x210149, 0xe3f}, + {0x211049, 0xe3f}, + {0x211149, 0xe3f}, + {0x43, 0x7f}, + {0x1043, 0x7f}, + {0x2043, 0x7f}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x11}, + {0x2009b, 0x2}, + {0x20008, 0x258}, + {0x120008, 0x12c}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x41}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90182, 0x0}, + {0x90183, 0x0}, + {0x90184, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x12000b, 0x0}, + {0x12000c, 0x0}, + {0x12000d, 0x0}, + {0x12000e, 0x0}, + {0x22000b, 0x0}, + {0x22000c, 0x0}, + {0x22000d, 0x0}, + {0x22000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x120010, 0x0}, + {0x120011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x140080, 0x0}, + {0x140081, 0x0}, + {0x140082, 0x0}, + {0x140083, 0x0}, + {0x140084, 0x0}, + {0x140085, 0x0}, + {0x240080, 0x0}, + {0x240081, 0x0}, + {0x240082, 0x0}, + {0x240083, 0x0}, + {0x240084, 0x0}, + {0x240085, 0x0}, + {0x400fd, 0x0}, + {0x400f1, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x3324}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x3324}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x4b0}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x3352}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x3352}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4800}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4800}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3309}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3309}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x3324}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x3324}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x2a3}, + {0x2000c, 0x96}, + {0x2000d, 0x5dc}, + {0x2000e, 0x2c}, + {0x12000b, 0x152}, + {0x12000c, 0x4b}, + {0x12000d, 0x2ee}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1200mts 1D */ + .drate = 1200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_2GB = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1200, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/nxp/imx91_frdm/lpddr4_2400mts_ecc_1gb_timing.c b/board/nxp/imx91_frdm/lpddr4_2400mts_ecc_1gb_timing.c new file mode 100644 index 00000000000..d57e083557c --- /dev/null +++ b/board/nxp/imx91_frdm/lpddr4_2400mts_ecc_1gb_timing.c @@ -0,0 +1,1996 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 NXP + * + * Code generated with DDR Tool v3.3.0_1.8-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include +#include + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000b7}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000412}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1012}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30d00}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0xc0000000}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x13542110}, + {0x4e300104, 0xF8990011}, + {0x4e300108, 0x636E88CC}, + {0x4e30010C, 0x00614070}, + {0x4e300124, 0x124E0000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x31D00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x0000001A}, + {0x4e300254, 0x00A000A0}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x1633160D}, + {0x4e300304, 0x00A0180C}, + {0x4e300308, 0x0C280927}, + }, + { + {0x01, 0xC4}, + {0x02, 0x24}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x010A1100}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0xBABA0068}, + {0x4e30010C, 0x00610158}, + {0x4e300124, 0x09270000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30400000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x0000000D}, + {0x4e300254, 0x004C004C}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xA4}, + {0x02, 0x52}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00051000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E620A48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00240024}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 1, + }, + +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0xa}, + {0x1200c5, 0x2}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x1}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe3f}, + {0x10149, 0xe3f}, + {0x11049, 0xe3f}, + {0x11149, 0xe3f}, + {0x110049, 0xe3f}, + {0x110149, 0xe3f}, + {0x111049, 0xe3f}, + {0x111149, 0xe3f}, + {0x210049, 0xe3f}, + {0x210149, 0xe3f}, + {0x211049, 0xe3f}, + {0x211149, 0xe3f}, + {0x43, 0x7f}, + {0x1043, 0x7f}, + {0x2043, 0x7f}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x11}, + {0x2009b, 0x2}, + {0x20008, 0x258}, + {0x120008, 0x12c}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x41}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + 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{0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + 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{0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x3324}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x3324}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x4b0}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x3352}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x3352}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4800}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4800}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3309}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3309}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x3324}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x3324}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x2a3}, + {0x2000c, 0x96}, + {0x2000d, 0x5dc}, + {0x2000e, 0x2c}, + {0x12000b, 0x152}, + {0x12000c, 0x4b}, + {0x12000d, 0x2ee}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1200mts 1D */ + .drate = 1200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_1GB = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1200, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/nxp/imx91_frdm/lpddr4_2400mts_ecc_2gb_timing.c b/board/nxp/imx91_frdm/lpddr4_2400mts_ecc_2gb_timing.c new file mode 100644 index 00000000000..4859796be38 --- /dev/null +++ b/board/nxp/imx91_frdm/lpddr4_2400mts_ecc_2gb_timing.c @@ -0,0 +1,1996 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 NXP + * + * Code generated with DDR Tool v3.3.0_1.8-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include +#include + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000ef}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000512}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1012}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30d00}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0xc0000000}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x135C2110}, + {0x4e300104, 0xF8990011}, + {0x4e300108, 0x636E08CC}, + {0x4e30010C, 0x00614070}, + {0x4e300124, 0x124E0000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x31D00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x0000001A}, + {0x4e300254, 0x00DC00DC}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x1633160D}, + {0x4e300304, 0x00DC180C}, + {0x4e300308, 0x0C280927}, + }, + { + {0x01, 0xC4}, + {0x02, 0x24}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x010D1100}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0xBABAC068}, + {0x4e30010C, 0x00610158}, + {0x4e300124, 0x09270000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30400000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x0000000D}, + {0x4e300254, 0x006A006A}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xA4}, + {0x02, 0x52}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00061000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E62FA48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00340034}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 1, + }, + +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0xa}, + {0x1200c5, 0x2}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x1}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe3f}, + {0x10149, 0xe3f}, + {0x11049, 0xe3f}, + {0x11149, 0xe3f}, + {0x110049, 0xe3f}, + {0x110149, 0xe3f}, + {0x111049, 0xe3f}, + {0x111149, 0xe3f}, + {0x210049, 0xe3f}, + {0x210149, 0xe3f}, + {0x211049, 0xe3f}, + {0x211149, 0xe3f}, + {0x43, 0x7f}, + {0x1043, 0x7f}, + {0x2043, 0x7f}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x11}, + {0x2009b, 0x2}, + {0x20008, 0x258}, + {0x120008, 0x12c}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x41}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90182, 0x0}, + {0x90183, 0x0}, + {0x90184, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x12000b, 0x0}, + {0x12000c, 0x0}, + {0x12000d, 0x0}, + {0x12000e, 0x0}, + {0x22000b, 0x0}, + {0x22000c, 0x0}, + {0x22000d, 0x0}, + {0x22000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x120010, 0x0}, + {0x120011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x140080, 0x0}, + {0x140081, 0x0}, + {0x140082, 0x0}, + {0x140083, 0x0}, + {0x140084, 0x0}, + {0x140085, 0x0}, + {0x240080, 0x0}, + {0x240081, 0x0}, + {0x240082, 0x0}, + {0x240083, 0x0}, + {0x240084, 0x0}, + {0x240085, 0x0}, + {0x400fd, 0x0}, + {0x400f1, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x3324}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x3324}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x4b0}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x3352}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x3352}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4800}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4800}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3309}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3309}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x33}, + {0x5401b, 0x1146}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x33}, + {0x54021, 0x1146}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x3324}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x3324}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x2a3}, + {0x2000c, 0x96}, + {0x2000d, 0x5dc}, + {0x2000e, 0x2c}, + {0x12000b, 0x152}, + {0x12000c, 0x4b}, + {0x12000d, 0x2ee}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1200mts 1D */ + .drate = 1200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_2GB = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1200, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/nxp/imx91_frdm/lpddr4_timing.h b/board/nxp/imx91_frdm/lpddr4_timing.h new file mode 100644 index 00000000000..9b483bbc3ed --- /dev/null +++ b/board/nxp/imx91_frdm/lpddr4_timing.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 NXP + */ + +#ifndef __LPDDR4_TIMING_H__ +#define __LPDDR4_TIMING_H__ + +extern struct dram_timing_info dram_timing_1GB; +extern struct dram_timing_info dram_timing_2GB; + +#endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/nxp/imx91_frdm/spl.c b/board/nxp/imx91_frdm/spl.c new file mode 100644 index 00000000000..cd59479d3b3 --- /dev/null +++ b/board/nxp/imx91_frdm/spl.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include "lpddr4_timing.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define SRC_DDRC_SW_CTRL (0x44461020) +#define SRC_DDRPHY_SINGLE_RESET_SW_CTRL (0x44461424) + +static struct _drams { + u8 mr8; + struct dram_timing_info *pdram_timing; + char *name; +} frdm_drams[2] = { + {0x10, &dram_timing_1GB, "1GB DRAM" }, + {0x18, &dram_timing_2GB, "2GB DRAM" }, +}; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_board_init(void) +{ + int ret; + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); + + puts("Normal Boot\n"); +} + +void spl_dram_init(void) +{ + int i; + int ret; + + for (i = 0; i < ARRAY_SIZE(frdm_drams); i++) { + struct dram_timing_info *ptiming = frdm_drams[i].pdram_timing; + + printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate); + ret = ddr_init(ptiming); + if (ret == 0) { + if (lpddr4_mr_read(1, 8) == frdm_drams[i].mr8) { + printf("found DRAM %s matched\n", frdm_drams[i].name); + break; + } + + /* Power down and Power up DDR Mixer */ + + /* Clear PwrOkIn via DDRMIX register */ + setbits_32(SRC_DDRPHY_SINGLE_RESET_SW_CTRL, BIT(0)); + /* Power off the DDRMIX */ + setbits_32(SRC_DDRC_SW_CTRL, BIT(31)); + + udelay(50); + + /* Power up the DDRMIX */ + clrbits_32(SRC_DDRC_SW_CTRL, BIT(31)); + setbits_32(SRC_DDRC_SW_CTRL, BIT(0)); + udelay(10); + clrbits_32(SRC_DDRC_SW_CTRL, BIT(0)); + udelay(10); + } + } +} + +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int val = 0, buck_val; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("ERROR: Get PMIC PCA9451A failed!\n"); + return ret; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* enable DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + ret = pmic_reg_read(dev, PCA9450_PWR_CTRL); + if (ret < 0) + return ret; + + val = ret; + + if (is_voltage_mode(VOLT_LOW_DRIVE)) { + buck_val = 0x0c; /* 0.8V for Low drive mode */ + printf("PMIC: Low Drive Voltage Mode\n"); + } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) { + buck_val = 0x10; /* 0.85V for Nominal drive mode */ + printf("PMIC: Nominal Voltage Mode\n"); + } else { + buck_val = 0x14; /* 0.9V for Over drive mode */ + printf("PMIC: Over Drive Voltage Mode\n"); + } + + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val); + } else { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4); + } + + /* Set VDDQ to 1.1V from buck2 (buck2 not used for iMX91 EVK) */ + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28); + + /* set standby voltage to 0.65V */ + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); + + /* I2C_LT_EN*/ + pmic_reg_write(dev, 0xa, 0x3); + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + spl_early_init(); + + preloader_console_init(); + + ret = imx9_probe_mu(); + if (ret) { + printf("Fail to init ELE API\n"); + } else { + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + } + + clock_init_late(); + + power_init_board(); + + if (!is_voltage_mode(VOLT_LOW_DRIVE)) + set_arm_clk(get_cpu_speed_grade_hz()); + + /* Init power of mix */ + soc_power_init(); + + /* Setup TRDC for DDR access */ + trdc_init(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/board/nxp/imx93_evk/Kconfig b/board/nxp/imx93_evk/Kconfig new file mode 100644 index 00000000000..305c3963f06 --- /dev/null +++ b/board/nxp/imx93_evk/Kconfig @@ -0,0 +1,19 @@ +if TARGET_IMX93_11X11_EVK + +config SYS_BOARD + default "imx93_evk" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "imx93_evk" + +config IMX93_EVK_LPDDR4X + bool "Using LPDDR4X Timing and PMIC voltage" + default y + select IMX9_LPDDR4X + help + Select the LPDDR4X timing and 0.6V VDDQ + +endif diff --git a/board/nxp/imx93_evk/MAINTAINERS b/board/nxp/imx93_evk/MAINTAINERS new file mode 100644 index 00000000000..da0540307c6 --- /dev/null +++ b/board/nxp/imx93_evk/MAINTAINERS @@ -0,0 +1,7 @@ +i.MX93 EVK BOARD +M: Peng Fan +S: Maintained +F: board/nxp/imx93_evk/ +F: include/configs/imx93_evk.h +F: configs/imx93_11x11_evk_defconfig +F: configs/imx93_11x11_evk_ld_defconfig diff --git a/board/nxp/imx93_evk/Makefile b/board/nxp/imx93_evk/Makefile new file mode 100644 index 00000000000..b077acc70a5 --- /dev/null +++ b/board/nxp/imx93_evk/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx93_evk.o + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o lpddr4x_timing_1866mts.o +endif diff --git a/board/nxp/imx93_evk/imx93_evk.c b/board/nxp/imx93_evk/imx93_evk.c new file mode 100644 index 00000000000..70b07fa3c6f --- /dev/null +++ b/board/nxp/imx93_evk/imx93_evk.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include +#include +#include +#include + +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0xbc550d86, 0xda26, 0x4b70, 0xac, 0x05, \ + 0x2a, 0x44, 0x8e, 0xda, 0x6f, 0x21) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX93-11X11-EVK-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=flash-bin raw 0 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + +int board_late_init(void) +{ +#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) || CONFIG_IS_ENABLED(ENV_IS_NOWHERE) + board_late_mmc_env_init(); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "11X11_EVK"); + env_set("board_rev", "iMX93"); +#endif + return 0; +} diff --git a/board/nxp/imx93_evk/imx93_evk.env b/board/nxp/imx93_evk/imx93_evk.env new file mode 100644 index 00000000000..d5ed216f54b --- /dev/null +++ b/board/nxp/imx93_evk/imx93_evk.env @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +boot_targets=mmc0 mmc1 +boot_fit=no +bootm_size=0x10000000 +cntr_addr=0x98000000 +cntr_file=os_cntr_signed.bin +console=ttyLP0,115200 earlycon +fdt_addr_r=0x83000000 +fdt_addr=0x83000000 +fdtfile=CONFIG_DEFAULT_FDT_FILE +image=Image +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk1p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} +prepare_mcore=setenv mcore_clk clk-imx93.mcore_booted +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} +auth_os=auth_cntr ${cntr_addr} +sec_boot=no +boot_os=booti ${loadaddr} - ${fdt_addr_r} +mmcboot= + echo Booting from mmc ...; + run mmcargs; + if test ${sec_boot} = yes; then + if true; then + run boot_os; + else + echo ERR: failed to authenticate; + fi; + else + if run loadfdt; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; +netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot= + echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if test ${sec_boot} = yes; then + ${get_cmd} ${cntr_addr} ${cntr_file}; + if true; then + run boot_os; + else + echo ERR: failed to authenticate; + fi; + else + ${get_cmd} ${loadaddr} ${image}; + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; +bsp_bootcmd= + echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; + if mmc rescan; then + if run loadbootscript; then + run bootscript; + else + if test ${sec_boot} = yes; then + if run loadcntr; then + run mmcboot; + else + run netboot; + fi; + else + if run loadimage; then + run mmcboot; + else + run netboot; + fi; + fi; + fi; + fi; +scriptaddr=0x83500000 diff --git a/board/nxp/imx93_evk/lpddr4x_timing.c b/board/nxp/imx93_evk/lpddr4x_timing.c new file mode 100644 index 00000000000..ffdf96b739f --- /dev/null +++ b/board/nxp/imx93_evk/lpddr4x_timing.c @@ -0,0 +1,1994 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 NXP + * + * Code generated with DDR Tool v2.0.0_5.3. + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000ff}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000512}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x24AB321B}, + {0x4e300104, 0xF8EE001B}, + {0x4e300108, 0x2F2EE233}, + {0x4e30010C, 0x0005E18B}, + {0x4e300124, 0x1C770000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x35F00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x00000028}, + {0x4e300254, 0x015B015B}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x224F2213}, + {0x4e300304, 0x015B2213}, + {0x4e300308, 0x0A3C0E3C}, + }, + { + {0x01, 0xE4}, + {0x02, 0x36}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x12552100}, + {0x4e300104, 0xF877000E}, + {0x4e300108, 0x1816B4AA}, + {0x4e30010C, 0x005101E6}, + {0x4e300124, 0x0E3C0000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30900000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x00000014}, + {0x4e300254, 0x00AA00AA}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xB4}, + {0x02, 0x1B}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00061000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E62FA48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00340034}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 1, + } +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x5ff}, + {0x1015f, 0x5ff}, + {0x1105f, 0x5ff}, + {0x1115f, 0x5ff}, + {0x11005f, 0x5ff}, + {0x11015f, 0x5ff}, + {0x11105f, 0x5ff}, + {0x11115f, 0x5ff}, + {0x21005f, 0x5ff}, + {0x21015f, 0x5ff}, + {0x21105f, 0x5ff}, + {0x21115f, 0x5ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0x19}, + {0x1200c5, 0xb}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x2}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe00}, + {0x10149, 0xe00}, + {0x11049, 0xe00}, + {0x11149, 0xe00}, + {0x110049, 0xe00}, + {0x110149, 0xe00}, + {0x111049, 0xe00}, + {0x111149, 0xe00}, + {0x210049, 0xe00}, + {0x210149, 0xe00}, + {0x211049, 0xe00}, + {0x211149, 0xe00}, + {0x43, 0x60}, + {0x1043, 0x60}, + {0x2043, 0x60}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x2009b, 0x2}, + {0x20008, 0x3a5}, + {0x120008, 0x1d3}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x200ca, 0x24}, + {0x1200ca, 0x24} +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90182, 0x0}, + {0x90183, 0x0}, + {0x90184, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x12000b, 0x0}, + {0x12000c, 0x0}, + {0x12000d, 0x0}, + {0x12000e, 0x0}, + {0x22000b, 0x0}, + {0x22000c, 0x0}, + {0x22000d, 0x0}, + {0x22000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x120010, 0x0}, + {0x120011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x140080, 0x0}, + {0x140081, 0x0}, + {0x140082, 0x0}, + {0x140083, 0x0}, + {0x140084, 0x0}, + {0x140085, 0x0}, + {0x240080, 0x0}, + {0x240081, 0x0}, + {0x240082, 0x0}, + {0x240083, 0x0}, + {0x240084, 0x0}, + {0x240085, 0x0}, + {0x400fd, 0x0}, + {0x400f1, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x3236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x3236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x74a}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x1bb4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x1bb4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xb400}, + {0x54033, 0x321b}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xb400}, + {0x54039, 0x321b}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1100}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1100}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3209}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3209}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x3236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x3236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x41a}, + {0x2000c, 0xe9}, + {0x2000d, 0x91c}, + {0x2000e, 0x2c}, + {0x12000b, 0x20d}, + {0x12000c, 0x74}, + {0x12000d, 0x48e}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3733mts 2D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, 1866, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/nxp/imx93_evk/lpddr4x_timing_1866mts.c b/board/nxp/imx93_evk/lpddr4x_timing_1866mts.c new file mode 100644 index 00000000000..f4e910b2536 --- /dev/null +++ b/board/nxp/imx93_evk/lpddr4x_timing_1866mts.c @@ -0,0 +1,1995 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2024 NXP + * + * Code generated with DDR Tool v3.4.0_8.3-4e2b550a. + * DDR PHY FW2022.01 + */ + +#include +#include + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000ff}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000512}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x12552100}, + {0x4e300104, 0xF877000E}, + {0x4e300108, 0x1816B4AA}, + {0x4e30010C, 0x0051E1E6}, + {0x4e300124, 0x0E3A0000}, + {0x4e300160, 0x00009101}, + {0x4e30016C, 0x30900000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x00000014}, + {0x4e300254, 0x00AA00AA}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x11281109}, + {0x4e300304, 0x00AA140A}, + {0x4e300308, 0x063C071E}, + }, + { + {0x01, 0xB4}, + {0x02, 0x1B}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x010A1000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x9492AA58}, + {0x4e30010C, 0x00310113}, + {0x4e300124, 0x071E0000}, + {0x4e300160, 0x00009100}, + {0x4e30016C, 0x30200000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x0000000A}, + {0x4e300254, 0x00510051}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00061000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E62FA48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009100}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00340034}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 1, + }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x5ff}, + {0x1015f, 0x5ff}, + {0x1105f, 0x5ff}, + {0x1115f, 0x5ff}, + {0x11005f, 0x5ff}, + {0x11015f, 0x5ff}, + {0x11105f, 0x5ff}, + {0x11115f, 0x5ff}, + {0x21005f, 0x5ff}, + {0x21015f, 0x5ff}, + {0x21105f, 0x5ff}, + {0x21115f, 0x5ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0xb}, + {0x1200c5, 0x3}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x1}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe00}, + {0x10149, 0xe00}, + {0x11049, 0xe00}, + {0x11149, 0xe00}, + {0x110049, 0xe00}, + {0x110149, 0xe00}, + {0x111049, 0xe00}, + {0x111149, 0xe00}, + {0x210049, 0xe00}, + {0x210149, 0xe00}, + {0x211049, 0xe00}, + {0x211149, 0xe00}, + {0x43, 0x60}, + {0x1043, 0x60}, + {0x2043, 0x60}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x2009b, 0x2}, + {0x20008, 0x1d3}, + {0x120008, 0xe9}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x41}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 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{0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x74a}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x1bb4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x1bb4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xb400}, + {0x54033, 0x321b}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xb400}, + {0x54039, 0x321b}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x3a4}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3209}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3209}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1100}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1100}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3209}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3209}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x74a}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x1bb4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x1bb4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xb400}, + {0x54033, 0x321b}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xb400}, + {0x54039, 0x321b}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x20d}, + {0x2000c, 0x74}, + {0x2000d, 0x48e}, + {0x2000e, 0x2c}, + {0x12000b, 0x107}, + {0x12000c, 0x3a}, + {0x12000d, 0x246}, + {0x12000e, 0x21}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 933mts 1D */ + .drate = 933, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 1866mts 2D */ + .drate = 1866, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_1866mts = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1866, 933, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/nxp/imx93_evk/spl.c b/board/nxp/imx93_evk/spl.c new file mode 100644 index 00000000000..176d25a74a6 --- /dev/null +++ b/board/nxp/imx93_evk/spl.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_board_init(void) +{ + int ret; + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); + + puts("Normal Boot\n"); +} + +extern struct dram_timing_info dram_timing_1866mts; +void spl_dram_init(void) +{ + struct dram_timing_info *ptiming = &dram_timing; + + if (is_voltage_mode(VOLT_LOW_DRIVE)) + ptiming = &dram_timing_1866mts; + + printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate); + ddr_init(ptiming); +} + +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int val = 0, buck_val; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* enable DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + ret = pmic_reg_read(dev, PCA9450_PWR_CTRL); + if (ret < 0) + return ret; + + val = ret; + + if (is_voltage_mode(VOLT_LOW_DRIVE)) { + buck_val = 0x0c; /* 0.8v for Low drive mode */ + printf("PMIC: Low Drive Voltage Mode\n"); + } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) { + buck_val = 0x10; /* 0.85v for Nominal drive mode */ + printf("PMIC: Nominal Voltage Mode\n"); + } else { + buck_val = 0x14; /* 0.9v for Over drive mode */ + printf("PMIC: Over Drive Voltage Mode\n"); + } + + ele_volt_change_start_req(); + + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val); + } else { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4); + } + + ele_volt_change_finish_req(); + + /* set standby voltage to 0.65v */ + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); + + /* I2C_LT_EN*/ + pmic_reg_write(dev, 0xa, 0x3); + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + spl_early_init(); + + preloader_console_init(); + + ret = imx9_probe_mu(); + if (ret) { + printf("Fail to init Sentinel API\n"); + } else { + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + } + + clock_init_late(); + + power_init_board(); + + if (!is_voltage_mode(VOLT_LOW_DRIVE)) + set_arm_clk(get_cpu_speed_grade_hz()); + + /* Init power of mix */ + soc_power_init(); + + /* Setup TRDC for DDR access */ + trdc_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Put M33 into CPUWAIT for following kick */ + ret = m33_prepare(); + if (!ret) + printf("M33 prepare ok\n"); + + board_init_r(NULL, 0); +} diff --git a/board/nxp/imx93_frdm/Kconfig b/board/nxp/imx93_frdm/Kconfig new file mode 100644 index 00000000000..d0610bce77e --- /dev/null +++ b/board/nxp/imx93_frdm/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX93_FRDM + +config SYS_BOARD + default "imx93_frdm" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "imx93_frdm" + +endif diff --git a/board/nxp/imx93_frdm/MAINTAINERS b/board/nxp/imx93_frdm/MAINTAINERS new file mode 100644 index 00000000000..72b5daffb39 --- /dev/null +++ b/board/nxp/imx93_frdm/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX93 FRDM BOARD +M: Fabio Estevam +S: Maintained +F: board/nxp/imx93_frdm/ +F: include/configs/imx93_frdm.h +F: configs/imx93_frdm_defconfig diff --git a/board/nxp/imx93_frdm/Makefile b/board/nxp/imx93_frdm/Makefile new file mode 100644 index 00000000000..9612b1fa55b --- /dev/null +++ b/board/nxp/imx93_frdm/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx93_frdm.o + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o lpddr4x_1gb_timing.o lpddr4x_2gb_timing.o +endif diff --git a/board/nxp/imx93_frdm/imx93_frdm.c b/board/nxp/imx93_frdm/imx93_frdm.c new file mode 100644 index 00000000000..cfbcde2e1a5 --- /dev/null +++ b/board/nxp/imx93_frdm/imx93_frdm.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0xbc550d86, 0xda26, 0x4b70, 0xac, 0x05, \ + 0x2a, 0x44, 0x8e, 0xda, 0x6f, 0x21) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX93-11X11-FRDM-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=flash-bin raw 0 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + +#define TCPC_ALERT 0x10 +#define TCPC_ALERT_MASK 0x12 +#define TCPC_FAULT_STATUS_MASK 0x15 + +#define TCPC1_I2C_BUS 2 +#define TCPC1_I2C_ADDR 0x50 + +/* + * Mask all interrupts and clear alert status for the PTN5110 TCPC USB Power + * Delivery controller. This is required to avoid an interrupt storm on OS + * startup, since the interrupt line for the PTN5110 is shared also by the + * PCAL6524 I/O expander. + */ +static int clear_pd_alert(void) +{ + struct udevice *bus; + struct udevice *i2c_dev = NULL; + int ret; + u8 buffer_0[2] = {0, 0}; + u8 buffer_1[2] = {0xff, 0xff}; + + ret = uclass_get_device_by_seq(UCLASS_I2C, TCPC1_I2C_BUS, &bus); + if (ret) { + printf("Failed to get I2C bus %d\n", TCPC1_I2C_BUS); + return ret; + } + + ret = dm_i2c_probe(bus, TCPC1_I2C_ADDR, 0, &i2c_dev); + if (ret) { + printf("Can't find USB PD device at 0x%02x\n", TCPC1_I2C_ADDR); + return ret; + } + + /* Mask all alert status*/ + ret = dm_i2c_write(i2c_dev, TCPC_ALERT_MASK, buffer_0, 2); + if (ret) { + printf("%s dm_i2c_write failed: %d\n", __func__, ret); + return ret; + } + + ret = dm_i2c_write(i2c_dev, TCPC_FAULT_STATUS_MASK, buffer_0, 2); + if (ret) { + printf("%s dm_i2c_write failed: %d\n", __func__, ret); + return ret; + } + + /* Clear active alerts */ + ret = dm_i2c_write(i2c_dev, TCPC_ALERT, buffer_1, 2); + if (ret) { + printf("%s dm_i2c_write failed: %d\n", __func__, ret); + return ret; + } + + return 0; +} + +int board_early_init_f(void) +{ + return 0; +} + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC) || IS_ENABLED(CONFIG_ENV_IS_IN_NOWHERE)) + board_late_mmc_env_init(); + + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + env_set("board_name", "11X11_FRDM"); + env_set("board_rev", "iMX93"); + } + + if (get_boot_device() == USB_BOOT) { + printf("USB boot detected. Will enter fasboot mode\n"); + env_set_ulong("dofastboot", 1); + } + + clear_pd_alert(); + + return 0; +} diff --git a/board/nxp/imx93_frdm/imx93_frdm.env b/board/nxp/imx93_frdm/imx93_frdm.env new file mode 100644 index 00000000000..111f38ed72a --- /dev/null +++ b/board/nxp/imx93_frdm/imx93_frdm.env @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +boot_targets=mmc0 mmc1 +boot_fit=no +bootm_size=0x10000000 +cntr_addr=0x98000000 +cntr_file=os_cntr_signed.bin +console=ttyLP0,115200 +fdt_addr_r=0x83000000 +fdt_addr=0x83000000 +fdtfile=CONFIG_DEFAULT_FDT_FILE +image=Image +mmcdev=1 +mmcpart=1 +mmcroot=/dev/mmcblk${mmcdev}p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs console=${console} root=${mmcroot} +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +boot_os=booti ${loadaddr} - ${fdt_addr_r} +fastboot_partition_alias_all=0:0 +fastboot_partition_alias_bootloader=0.1 +emmc_dev=0 +sd_dev=1 +dofastboot=0 + +bsp_bootcmd= + if test ${dofastboot} = 1; then + fastboot 0; + fi; + echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; + run mmcargs; + run loadimage; + run loadfdt; + run boot_os; + +scriptaddr=0x83500000 diff --git a/board/nxp/imx93_frdm/lpddr4_timing.h b/board/nxp/imx93_frdm/lpddr4_timing.h new file mode 100644 index 00000000000..192bc9e1519 --- /dev/null +++ b/board/nxp/imx93_frdm/lpddr4_timing.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 Marek Vasut + */ + +#ifndef __LPDDR4_TIMING_H__ +#define __LPDDR4_TIMING_H__ + +extern struct dram_timing_info dram_timing_1GB; +extern struct dram_timing_info dram_timing_2GB; + +#endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/nxp/imx93_frdm/lpddr4x_1gb_timing.c b/board/nxp/imx93_frdm/lpddr4x_1gb_timing.c new file mode 100644 index 00000000000..17549206ee4 --- /dev/null +++ b/board/nxp/imx93_frdm/lpddr4x_1gb_timing.c @@ -0,0 +1,1996 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 NXP + * + * Code generated with DDR Tool v3.3.0_7.8-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include +#include + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000bf}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000412}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x24A0321B}, + {0x4e300104, 0xF8EE001B}, + {0x4e300108, 0x2F2E3233}, + {0x4e30010C, 0x0005C18B}, + {0x4e300124, 0x1C790000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x35F00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x00000028}, + {0x4e300254, 0x00FE00FE}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x224F2213}, + {0x4e300304, 0x00FE2213}, + {0x4e300308, 0x0A380E3D}, + }, + { + {0x01, 0xE4}, + {0x02, 0x36}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x124F2100}, + {0x4e300104, 0xF877000E}, + {0x4e300108, 0x1816E4AA}, + {0x4e30010C, 0x005101E6}, + {0x4e300124, 0x0E3C0000}, + {0x4e300160, 0x00009101}, + {0x4e30016C, 0x30900000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x00000014}, + {0x4e300254, 0x007B007B}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xB4}, + {0x02, 0x1B}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00051000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E620A48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009100}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00240024}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 1, + }, + +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x5ff}, + {0x1015f, 0x5ff}, + {0x1105f, 0x5ff}, + {0x1115f, 0x5ff}, + {0x11005f, 0x5ff}, + {0x11015f, 0x5ff}, + {0x11105f, 0x5ff}, + {0x11115f, 0x5ff}, + {0x21005f, 0x5ff}, + {0x21015f, 0x5ff}, + {0x21105f, 0x5ff}, + {0x21115f, 0x5ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0x19}, + {0x1200c5, 0xb}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x2}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe00}, + {0x10149, 0xe00}, + {0x11049, 0xe00}, + {0x11149, 0xe00}, + {0x110049, 0xe00}, + {0x110149, 0xe00}, + {0x111049, 0xe00}, + {0x111149, 0xe00}, + {0x210049, 0xe00}, + {0x210149, 0xe00}, + {0x211049, 0xe00}, + {0x211149, 0xe00}, + {0x43, 0x60}, + {0x1043, 0x60}, + {0x2043, 0x60}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x2009b, 0x2}, + {0x20008, 0x3a5}, + {0x120008, 0x1d3}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90182, 0x0}, + {0x90183, 0x0}, + {0x90184, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x12000b, 0x0}, + {0x12000c, 0x0}, + {0x12000d, 0x0}, + {0x12000e, 0x0}, + {0x22000b, 0x0}, + {0x22000c, 0x0}, + {0x22000d, 0x0}, + {0x22000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x120010, 0x0}, + {0x120011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x140080, 0x0}, + {0x140081, 0x0}, + {0x140082, 0x0}, + {0x140083, 0x0}, + {0x140084, 0x0}, + {0x140085, 0x0}, + {0x240080, 0x0}, + {0x240081, 0x0}, + {0x240082, 0x0}, + {0x240083, 0x0}, + {0x240084, 0x0}, + {0x240085, 0x0}, + {0x400fd, 0x0}, + {0x400f1, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x3236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x3236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x74a}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x1bb4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x1bb4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xb400}, + {0x54033, 0x321b}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xb400}, + {0x54039, 0x321b}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1100}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1100}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3209}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3209}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x3236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x3236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x41a}, + {0x2000c, 0xe9}, + {0x2000d, 0x91c}, + {0x2000e, 0x2c}, + {0x12000b, 0x20d}, + {0x12000c, 0x74}, + {0x12000d, 0x48e}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3733mts 2D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_1GB = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, 1866, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/nxp/imx93_frdm/lpddr4x_2gb_timing.c b/board/nxp/imx93_frdm/lpddr4x_2gb_timing.c new file mode 100644 index 00000000000..cd129e12959 --- /dev/null +++ b/board/nxp/imx93_frdm/lpddr4x_2gb_timing.c @@ -0,0 +1,1995 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 NXP + * + * Code generated with DDR Tool v3.4.0_8.3-4e2b550a. + * DDR PHY FW2022.01 + */ + +#include +#include + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000ff}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000512}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x24AB321B}, + {0x4e300104, 0xF8EE001B}, + {0x4e300108, 0x2F2EE233}, + {0x4e30010C, 0x0005E18B}, + {0x4e300124, 0x1C760000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x35F00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x00000028}, + {0x4e300254, 0x015B015B}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x224F2213}, + {0x4e300304, 0x015B2213}, + {0x4e300308, 0x0A3C0E3D}, + }, + { + {0x01, 0xE4}, + {0x02, 0x36}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x12552100}, + {0x4e300104, 0xF877000E}, + {0x4e300108, 0x1816B4AA}, + {0x4e30010C, 0x005101E6}, + {0x4e300124, 0x0E3C0000}, + {0x4e300160, 0x00009101}, + {0x4e30016C, 0x30900000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x00000014}, + {0x4e300254, 0x00AA00AA}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xB4}, + {0x02, 0x1B}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00061000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E62FA48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009100}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00340034}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 1, + }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x5ff}, + {0x1015f, 0x5ff}, + {0x1105f, 0x5ff}, + {0x1115f, 0x5ff}, + {0x11005f, 0x5ff}, + {0x11015f, 0x5ff}, + {0x11105f, 0x5ff}, + {0x11115f, 0x5ff}, + {0x21005f, 0x5ff}, + {0x21015f, 0x5ff}, + {0x21105f, 0x5ff}, + {0x21115f, 0x5ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0x19}, + {0x1200c5, 0xb}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x2}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe00}, + {0x10149, 0xe00}, + {0x11049, 0xe00}, + {0x11149, 0xe00}, + {0x110049, 0xe00}, + {0x110149, 0xe00}, + {0x111049, 0xe00}, + {0x111149, 0xe00}, + {0x210049, 0xe00}, + {0x210149, 0xe00}, + {0x211049, 0xe00}, + {0x211149, 0xe00}, + {0x43, 0x60}, + {0x1043, 0x60}, + {0x2043, 0x60}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x2009b, 0x2}, + {0x20008, 0x3a5}, + {0x120008, 0x1d3}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 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0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x3236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x3236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x74a}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x1bb4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x1bb4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xb400}, + {0x54033, 0x321b}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xb400}, + {0x54039, 0x321b}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1100}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1100}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3209}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3209}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x3236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x3236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x41a}, + {0x2000c, 0xe9}, + {0x2000d, 0x91c}, + {0x2000e, 0x2c}, + {0x12000b, 0x20d}, + {0x12000c, 0x74}, + {0x12000d, 0x48e}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3733mts 2D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_2GB = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, 1866, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/nxp/imx93_frdm/spl.c b/board/nxp/imx93_frdm/spl.c new file mode 100644 index 00000000000..006c752d071 --- /dev/null +++ b/board/nxp/imx93_frdm/spl.c @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include "lpddr4_timing.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define SRC_DDRC_SW_CTRL (0x44461020) +#define SRC_DDRPHY_SINGLE_RESET_SW_CTRL (0x44461424) + +static struct _drams { + u8 mr8; + struct dram_timing_info *pdram_timing; + char *name; +} frdm_drams[2] = { + {0x10, &dram_timing_1GB, "1GB DRAM" }, + {0x18, &dram_timing_2GB, "2GB DRAM" }, +}; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_board_init(void) +{ + int ret; + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); + + puts("Normal Boot\n"); +} + +void spl_dram_init(void) +{ + int i; + int ret; + + for (i = 0; i < ARRAY_SIZE(frdm_drams); i++) { + struct dram_timing_info *ptiming = frdm_drams[i].pdram_timing; + + printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate); + ret = ddr_init(ptiming); + if (ret == 0) { + if (lpddr4_mr_read(1, 8) == frdm_drams[i].mr8) { + printf("found DRAM %s matched\n", frdm_drams[i].name); + break; + } + + /* Power down and Power up DDR Mixer */ + + /* Clear PwrOkIn via DDRMIX register */ + setbits_32(SRC_DDRPHY_SINGLE_RESET_SW_CTRL, BIT(0)); + /* Power off the DDRMIX */ + setbits_32(SRC_DDRC_SW_CTRL, BIT(31)); + + udelay(50); + + /* Power up the DDRMIX */ + clrbits_32(SRC_DDRC_SW_CTRL, BIT(31)); + setbits_32(SRC_DDRC_SW_CTRL, BIT(0)); + udelay(10); + clrbits_32(SRC_DDRC_SW_CTRL, BIT(0)); + udelay(10); + } + } +} + +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int val = 0, buck_val; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* Enable DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + ret = pmic_reg_read(dev, PCA9450_PWR_CTRL); + if (ret < 0) + return ret; + + val = ret; + + if (is_voltage_mode(VOLT_LOW_DRIVE)) { + buck_val = 0x0c; /* 0.8V for Low drive mode */ + printf("PMIC: Low Drive Voltage Mode\n"); + } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) { + buck_val = 0x10; /* 0.85V for Nominal drive mode */ + printf("PMIC: Nominal Voltage Mode\n"); + } else { + buck_val = 0x14; /* 0.9V for Over drive mode */ + printf("PMIC: Over Drive Voltage Mode\n"); + } + + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val); + } else { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4); + } + + /* Set standby voltage to 0.65V */ + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); + + /* I2C_LT_EN*/ + pmic_reg_write(dev, 0xa, 0x3); + return 0; +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + board_early_init_f(); + + spl_early_init(); + + preloader_console_init(); + + ret = imx9_probe_mu(); + if (ret) { + printf("Fail to init Sentinel API\n"); + } else { + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + } + + clock_init_late(); + + power_init_board(); + + if (!is_voltage_mode(VOLT_LOW_DRIVE)) + set_arm_clk(get_cpu_speed_grade_hz()); + + /* Init power of mix */ + soc_power_init(); + + /* Setup TRDC for DDR access */ + trdc_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Put M33 into CPUWAIT for following kick */ + ret = m33_prepare(); + if (!ret) + printf("M33 prepare ok\n"); + + board_init_r(NULL, 0); +} diff --git a/board/nxp/imx93_qsb/Kconfig b/board/nxp/imx93_qsb/Kconfig new file mode 100644 index 00000000000..e619014a741 --- /dev/null +++ b/board/nxp/imx93_qsb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX93_9X9_QSB + +config SYS_BOARD + default "imx93_qsb" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "imx93_qsb" + +endif diff --git a/board/nxp/imx93_qsb/MAINTAINERS b/board/nxp/imx93_qsb/MAINTAINERS new file mode 100644 index 00000000000..11226c7ef8b --- /dev/null +++ b/board/nxp/imx93_qsb/MAINTAINERS @@ -0,0 +1,7 @@ +i.MX93 QSB BOARD +M: Peng Fan +S: Maintained +F: board/nxp/imx93_qsb/ +F: include/configs/imx93_qsb.h +F: configs/imx93_9x9_qsb_defconfig +F: configs/imx93_9x9_qsb_inline_ecc_defconfig diff --git a/board/nxp/imx93_qsb/Makefile b/board/nxp/imx93_qsb/Makefile new file mode 100644 index 00000000000..c94a6b2279d --- /dev/null +++ b/board/nxp/imx93_qsb/Makefile @@ -0,0 +1,16 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx93_qsb.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +ifdef CONFIG_IMX9_DRAM_INLINE_ECC +obj-$(CONFIG_TARGET_IMX93_9X9_QSB) += lpddr4_timing_ecc.o +else +obj-$(CONFIG_TARGET_IMX93_9X9_QSB) += lpddr4_timing.o +endif +endif diff --git a/board/nxp/imx93_qsb/imx93_qsb.c b/board/nxp/imx93_qsb/imx93_qsb.c new file mode 100644 index 00000000000..9de91758aa7 --- /dev/null +++ b/board/nxp/imx93_qsb/imx93_qsb.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +#include +#include +#include + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "9X9_QSB"); + env_set("board_rev", "iMX93"); +#endif + return 0; +} diff --git a/board/nxp/imx93_qsb/imx93_qsb.env b/board/nxp/imx93_qsb/imx93_qsb.env new file mode 100644 index 00000000000..6c10784cf61 --- /dev/null +++ b/board/nxp/imx93_qsb/imx93_qsb.env @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +boot_targets=mmc0 mmc1 +boot_fit=no +bootm_size=0x10000000 +cntr_addr=0x98000000 +cntr_file=os_cntr_signed.bin +console=ttyLP0,115200 earlycon +fdt_addr_r=0x83000000 +fdt_addr=0x83000000 +fdtfile=CONFIG_DEFAULT_FDT_FILE +image=Image +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk1p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} +prepare_mcore=setenv mcore_clk clk-imx93.mcore_booted +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} +auth_os=auth_cntr ${cntr_addr} +sec_boot=no +boot_os=booti ${loadaddr} - ${fdt_addr_r} +mmcboot= + echo Booting from mmc ...; + run mmcargs; + if test ${sec_boot} = yes; then + if run true; then + run boot_os; + else + echo ERR: failed to authenticate; + fi; + else + if run loadfdt; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; +netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot= + echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if test ${sec_boot} = yes; then + ${get_cmd} ${cntr_addr} ${cntr_file}; + if true; then + run boot_os; + else + echo ERR: failed to authenticate; + fi; + else + ${get_cmd} ${loadaddr} ${image}; + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; +bsp_bootcmd= + echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; + if mmc rescan; then + if run loadbootscript; then + run bootscript; + else + if test ${sec_boot} = yes; then + if run loadcntr; then + run mmcboot; + else + run netboot; + fi; + else + if run loadimage; then + run mmcboot; + else + run netboot; + fi; + fi; + fi; + fi; +scriptaddr=0x83500000 diff --git a/board/nxp/imx93_qsb/lpddr4_timing.c b/board/nxp/imx93_qsb/lpddr4_timing.c new file mode 100644 index 00000000000..c589c165720 --- /dev/null +++ b/board/nxp/imx93_qsb/lpddr4_timing.c @@ -0,0 +1,1995 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2024 NXP + * + * Code generated with DDR Tool v3.4.0_8.3-4e2b550a. + * DDR PHY FW2022.01 + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000ff}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000512}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x1465311B}, + {0x4e300104, 0xF8CC0017}, + {0x4e300108, 0xD4D68E00}, + {0x4e30010C, 0x0071E100}, + {0x4e300124, 0x18660000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x33F00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x00000022}, + {0x4e300254, 0x01280128}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x1D441D0D}, + {0x4e300304, 0x01281E10}, + {0x4e300308, 0x0C3C0C34}, + }, + { + {0x01, 0xD4}, + {0x02, 0x2D}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x48}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x02121100}, + {0x4e300104, 0xF866000C}, + {0x4e300108, 0xF2FA8088}, + {0x4e30010C, 0x006101A0}, + {0x4e300124, 0x0C340000}, + {0x4e300160, 0x00009101}, + {0x4e30016C, 0x30700000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x00000011}, + {0x4e300254, 0x00900090}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xA4}, + {0x02, 0x52}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x48}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00061000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E62FA48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009100}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00340034}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x48}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 1, + } +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0x19}, + {0x1200c5, 0xb}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x1}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe3f}, + {0x10149, 0xe3f}, + {0x11049, 0xe3f}, + {0x11149, 0xe3f}, + {0x110049, 0xe3f}, + {0x110149, 0xe3f}, + {0x111049, 0xe3f}, + {0x111149, 0xe3f}, + {0x210049, 0xe3f}, + {0x210149, 0xe3f}, + {0x211049, 0xe3f}, + {0x211149, 0xe3f}, + {0x43, 0x7f}, + {0x1043, 0x7f}, + {0x2043, 0x7f}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x11}, + {0x2009b, 0x2}, + {0x20008, 0x320}, + {0x120008, 0x190}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + 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{0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xc80}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x2dd4}, + {0x5401a, 0x33}, + {0x5401b, 0x4846}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x2dd4}, + {0x54020, 0x33}, + {0x54021, 0x4846}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xd400}, + {0x54033, 0x332d}, + {0x54034, 0x4600}, + {0x54035, 0x848}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xd400}, + {0x54039, 0x332d}, + {0x5403a, 0x4600}, + {0x5403b, 0x848}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x640}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x33}, + {0x5401b, 0x4846}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x33}, + {0x54021, 0x4846}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x3352}, + {0x54034, 0x4600}, + {0x54035, 0x848}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x3352}, + {0x5403a, 0x4600}, + {0x5403b, 0x848}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x33}, + {0x5401b, 0x4846}, + {0x5401c, 0x4800}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x33}, + {0x54021, 0x4846}, + {0x54022, 0x4800}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3309}, + {0x54034, 0x4600}, + {0x54035, 0x48}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3309}, + {0x5403a, 0x4600}, + {0x5403b, 0x48}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xc80}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x2dd4}, + {0x5401a, 0x33}, + {0x5401b, 0x4846}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x2dd4}, + {0x54020, 0x33}, + {0x54021, 0x4846}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xd400}, + {0x54033, 0x332d}, + {0x54034, 0x4600}, + {0x54035, 0x848}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xd400}, + {0x54039, 0x332d}, + {0x5403a, 0x4600}, + {0x5403b, 0x848}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x384}, + {0x2000c, 0xc8}, + {0x2000d, 0x7d0}, + {0x2000e, 0x2c}, + {0x12000b, 0x1c2}, + {0x12000c, 0x64}, + {0x12000d, 0x3e8}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1600mts 1D */ + .drate = 1600, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 1600, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/nxp/imx93_qsb/lpddr4_timing_ecc.c b/board/nxp/imx93_qsb/lpddr4_timing_ecc.c new file mode 100644 index 00000000000..60cd4908f4a --- /dev/null +++ b/board/nxp/imx93_qsb/lpddr4_timing_ecc.c @@ -0,0 +1,1995 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2024 NXP + * + * Code generated with DDR Tool v3.4.0_8.3-4e2b550a. + * DDR PHY FW2022.01 + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /* Initialize DDRC registers */ + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000ef}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000512}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1012}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30d00}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0xc0000000}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x1465311B}, + {0x4e300104, 0xF8CC0017}, + {0x4e300108, 0xD4D68E00}, + {0x4e30010C, 0x0071E100}, + {0x4e300124, 0x18660000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x33F00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x00000022}, + {0x4e300254, 0x01280128}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x1D441D0D}, + {0x4e300304, 0x01281E10}, + {0x4e300308, 0x0C3C0C34}, + }, + { + {0x01, 0xD4}, + {0x02, 0x2D}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x48}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x02121100}, + {0x4e300104, 0xF866000C}, + {0x4e300108, 0xF2FA8088}, + {0x4e30010C, 0x006101A0}, + {0x4e300124, 0x0C340000}, + {0x4e300160, 0x00009101}, + {0x4e30016C, 0x30700000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x00000011}, + {0x4e300254, 0x00900090}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xA4}, + {0x02, 0x52}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x48}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00061000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E62FA48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009100}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00340034}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x33}, + {0x0b, 0x46}, + {0x0c, 0x48}, + {0x0e, 0x48}, + {0x16, 0x04}, + }, + 1, + } +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0x19}, + {0x1200c5, 0xb}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x1}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe3f}, + {0x10149, 0xe3f}, + {0x11049, 0xe3f}, + {0x11149, 0xe3f}, + {0x110049, 0xe3f}, + {0x110149, 0xe3f}, + {0x111049, 0xe3f}, + {0x111149, 0xe3f}, + {0x210049, 0xe3f}, + {0x210149, 0xe3f}, + {0x211049, 0xe3f}, + {0x211149, 0xe3f}, + {0x43, 0x7f}, + {0x1043, 0x7f}, + {0x2043, 0x7f}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x11}, + {0x2009b, 0x2}, + {0x20008, 0x320}, + {0x120008, 0x190}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90182, 0x0}, + {0x90183, 0x0}, + {0x90184, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x12000b, 0x0}, + {0x12000c, 0x0}, + {0x12000d, 0x0}, + {0x12000e, 0x0}, + {0x22000b, 0x0}, + {0x22000c, 0x0}, + {0x22000d, 0x0}, + {0x22000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x120010, 0x0}, + {0x120011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x140080, 0x0}, + {0x140081, 0x0}, + {0x140082, 0x0}, + {0x140083, 0x0}, + {0x140084, 0x0}, + {0x140085, 0x0}, + {0x240080, 0x0}, + {0x240081, 0x0}, + {0x240082, 0x0}, + {0x240083, 0x0}, + {0x240084, 0x0}, + {0x240085, 0x0}, + {0x400fd, 0x0}, + {0x400f1, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xc80}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x2dd4}, + {0x5401a, 0x33}, + {0x5401b, 0x4846}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x2dd4}, + {0x54020, 0x33}, + {0x54021, 0x4846}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xd400}, + {0x54033, 0x332d}, + {0x54034, 0x4600}, + {0x54035, 0x848}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xd400}, + {0x54039, 0x332d}, + {0x5403a, 0x4600}, + {0x5403b, 0x848}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x640}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x33}, + {0x5401b, 0x4846}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x33}, + {0x54021, 0x4846}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x3352}, + {0x54034, 0x4600}, + {0x54035, 0x848}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x3352}, + {0x5403a, 0x4600}, + {0x5403b, 0x848}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x33}, + {0x5401b, 0x4846}, + {0x5401c, 0x4800}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x33}, + {0x54021, 0x4846}, + {0x54022, 0x4800}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3309}, + {0x54034, 0x4600}, + {0x54035, 0x48}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3309}, + {0x5403a, 0x4600}, + {0x5403b, 0x48}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xc80}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x2dd4}, + {0x5401a, 0x33}, + {0x5401b, 0x4846}, + {0x5401c, 0x4808}, + {0x5401e, 0x4}, + {0x5401f, 0x2dd4}, + {0x54020, 0x33}, + {0x54021, 0x4846}, + {0x54022, 0x4808}, + {0x54024, 0x4}, + {0x54032, 0xd400}, + {0x54033, 0x332d}, + {0x54034, 0x4600}, + {0x54035, 0x848}, + {0x54036, 0x48}, + {0x54037, 0x400}, + {0x54038, 0xd400}, + {0x54039, 0x332d}, + {0x5403a, 0x4600}, + {0x5403b, 0x848}, + {0x5403c, 0x48}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x384}, + {0x2000c, 0xc8}, + {0x2000d, 0x7d0}, + {0x2000e, 0x2c}, + {0x12000b, 0x1c2}, + {0x12000c, 0x64}, + {0x12000d, 0x3e8}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1600mts 1D */ + .drate = 1600, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 1600, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/nxp/imx93_qsb/spl.c b/board/nxp/imx93_qsb/spl.c new file mode 100644 index 00000000000..9e64714521b --- /dev/null +++ b/board/nxp/imx93_qsb/spl.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_board_init(void) +{ + int ret; + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); + + puts("Normal Boot\n"); +} + +void spl_dram_init(void) +{ + struct dram_timing_info *ptiming = &dram_timing; + + printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate); + ddr_init(ptiming); +} + +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int val = 0, buck_val; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* enable DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + ret = pmic_reg_read(dev, PCA9450_PWR_CTRL); + if (ret < 0) + return ret; + + val = ret; + + if (is_voltage_mode(VOLT_LOW_DRIVE)) { + buck_val = 0x0c; /* 0.8V for Low drive mode */ + printf("PMIC: Low Drive Voltage Mode\n"); + } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) { + buck_val = 0x10; /* 0.85V for Nominal drive mode */ + printf("PMIC: Nominal Voltage Mode\n"); + } else { + buck_val = 0x14; /* 0.9V for Over drive mode */ + printf("PMIC: Over Drive Voltage Mode\n"); + } + + ele_volt_change_start_req(); + + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val); + } else { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4); + } + + ele_volt_change_finish_req(); + + /* set standby voltage to 0.65v */ + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); + + /* 1.1v for LPDDR4 */ + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28); + + /* I2C_LT_EN*/ + pmic_reg_write(dev, 0xa, 0x3); + + /* set WDOG_B_CFG to cold reset */ + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + spl_early_init(); + + preloader_console_init(); + + ret = imx9_probe_mu(); + if (ret) { + printf("Fail to init ELE API\n"); + } else { + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + } + + clock_init_late(); + + power_init_board(); + + if (!is_voltage_mode(VOLT_LOW_DRIVE)) + set_arm_clk(get_cpu_speed_grade_hz()); + + /* Init power of mix */ + soc_power_init(); + + /* Setup TRDC for DDR access */ + trdc_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Put M33 into CPUWAIT for following kick */ + ret = m33_prepare(); + if (!ret) + printf("M33 prepare ok\n"); + + board_init_r(NULL, 0); +} diff --git a/board/nxp/imx94_evk/Kconfig b/board/nxp/imx94_evk/Kconfig new file mode 100644 index 00000000000..377b732c3e7 --- /dev/null +++ b/board/nxp/imx94_evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX943_EVK + +config SYS_BOARD + default "imx94_evk" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "imx94_evk" + +endif diff --git a/board/nxp/imx94_evk/MAINTAINERS b/board/nxp/imx94_evk/MAINTAINERS new file mode 100644 index 00000000000..a7aab5f3905 --- /dev/null +++ b/board/nxp/imx94_evk/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX94 EVK BOARD +M: Alice Guo +S: Maintained +F: board/nxp/imx94_evk/ +F: include/configs/imx94_evk.h +F: configs/imx943_evk_defconfig diff --git a/board/nxp/imx94_evk/Makefile b/board/nxp/imx94_evk/Makefile new file mode 100644 index 00000000000..ca31602f6ba --- /dev/null +++ b/board/nxp/imx94_evk/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx94_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/nxp/imx94_evk/imx94_evk.c b/board/nxp/imx94_evk/imx94_evk.c new file mode 100644 index 00000000000..588aa7548d4 --- /dev/null +++ b/board/nxp/imx94_evk/imx94_evk.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include +#include +#include +#include +#include + +int board_early_init_f(void) +{ + init_uart_clk(0); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + board_late_mmc_env_init(); + + env_set("sec_boot", "no"); + + if (IS_ENABLED(CONFIG_AHAB_BOOT)) + env_set("sec_boot", "yes"); + + return 0; +} + +int board_phys_sdram_size(phys_size_t *size) +{ + *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE; + + return 0; +} diff --git a/board/nxp/imx94_evk/imx94_evk.env b/board/nxp/imx94_evk/imx94_evk.env new file mode 100644 index 00000000000..2baf1bbadcb --- /dev/null +++ b/board/nxp/imx94_evk/imx94_evk.env @@ -0,0 +1,100 @@ +#ifdef CONFIG_AHAB_BOOT +sec_boot=yes +#else +sec_boot=no +#endif + +jh_root_dtb=imx943-evk-root.dtb +jh_mmcboot=setenv fdtfile ${jh_root_dtb}; + setenv jh_clk kvm.enable_virt_at_load=false cpuidle.off=1 clk_ignore_unused kvm-arm.mode=nvhe; + setenv jh_root_mem 0x60000000@0x90000000,0x100000000@0x100000000; + if run loadimage; then + run mmcboot; + else run jh_netboot; fi; +jh_netboot=setenv fdtfile ${jh_root_dtb}; + setenv jh_root_mem 0x60000000@0x90000000,0x100000000@0x100000000; + setenv jh_clk kvm.enable_virt_at_load=false cpuidle.off=1 clk_ignore_unused kvm-arm.mode=nvhe; run netboot; + +initrd_addr=0x93800000 +emmc_dev=0 +sd_dev=1 +scriptaddr=0x93500000 +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +image=Image +splashimage=0xA0000000 +console=ttyLP0,115200 earlycon +fdt_addr_r=0x93000000 +fdt_addr=0x93000000 +cntr_addr=0xA8000000 +cntr_file=os_cntr_signed.bin +boot_fit=no +fdtfile=CONFIG_DEFAULT_FDT_FILE +bootm_size=0x10000000 +mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcautodetect=yes +mmcargs=setenv bootargs ${jh_clk} ${mcore_args} console=${console} root=${mmcroot} +prepare_mcore=setenv mcore_args pd_ignore_unused; +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} +auth_os=booti ${cntr_addr} +boot_os=booti ${loadaddr} - ${fdt_addr_r}; +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${sec_boot} = yes; then + run auth_os; + else + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if run loadfdt; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; + fi; +netargs=setenv bootargs ${jh_clk} ${mcore_args} console=${console} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if test ${sec_boot} = yes; then + ${get_cmd} ${cntr_addr} ${cntr_file}; + run auth_os; + else + ${get_cmd} ${loadaddr} ${image}; + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; + fi; +bsp_bootcmd=echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; if mmc rescan; then + if run loadbootscript; then + run bootscript; + else + if test ${sec_boot} = yes; then + if run loadcntr; then + run mmcboot; + else run netboot; + fi; + else + if run loadimage; then + run mmcboot; + else run netboot; + fi; + fi; + fi; + fi; diff --git a/board/nxp/imx94_evk/spl.c b/board/nxp/imx94_evk/spl.c new file mode 100644 index 00000000000..797806a8d4d --- /dev/null +++ b/board/nxp/imx94_evk/spl.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + case QSPI_BOOT: + return BOOT_DEVICE_SPI; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_board_init(void) +{ + int ret; + + puts("Normal Boot\n"); + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); +} + +/* SCMI support by default */ +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + if (IS_ENABLED(CONFIG_SPL_RECOVER_DATA_SECTION) && + IS_ENABLED(CONFIG_SPL_BUILD)) + spl_save_restore_data(); + + timer_init(); + + spl_early_init(); + + /* Need enable SCMI drivers and ELE driver before enabling console */ + ret = imx9_probe_mu(); + if (ret) + hang(); /* if MU not probed, nothing can output, just hang here */ + + arch_cpu_init(); + + board_early_init_f(); + + preloader_console_init(); + + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + + get_reset_reason(true, false); + + board_init_r(NULL, 0); +} diff --git a/board/nxp/imx95_evk/Kconfig b/board/nxp/imx95_evk/Kconfig new file mode 100644 index 00000000000..fb255eda731 --- /dev/null +++ b/board/nxp/imx95_evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX95_19X19_EVK || TARGET_IMX95_15X15_EVK + +config SYS_BOARD + default "imx95_evk" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "imx95_evk" + +endif diff --git a/board/nxp/imx95_evk/MAINTAINERS b/board/nxp/imx95_evk/MAINTAINERS new file mode 100644 index 00000000000..e228b04d918 --- /dev/null +++ b/board/nxp/imx95_evk/MAINTAINERS @@ -0,0 +1,8 @@ +i.MX95 EVK BOARD +M: Alice Guo +S: Maintained +F: board/nxp/imx95_evk/ +F: include/configs/imx95_evk.h +F: configs/imx95_a0_19x19_evk_defconfig +F: configs/imx95_19x19_evk_defconfig +F: configs/imx95_15x15_evk_defconfig diff --git a/board/nxp/imx95_evk/Makefile b/board/nxp/imx95_evk/Makefile new file mode 100644 index 00000000000..0f5cec385c3 --- /dev/null +++ b/board/nxp/imx95_evk/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx95_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/nxp/imx95_evk/imx95_evk.c b/board/nxp/imx95_evk/imx95_evk.c new file mode 100644 index 00000000000..ca1d916deab --- /dev/null +++ b/board/nxp/imx95_evk/imx95_evk.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include +#include +#include + +int board_early_init_f(void) +{ + /* UART1: A55, UART2: M33, UART3: M7 */ + init_uart_clk(0); + + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + board_late_mmc_env_init(); + + return 0; +} + +int board_phys_sdram_size(phys_size_t *size) +{ + *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE; + + return 0; +} diff --git a/board/nxp/imx95_evk/imx95_evk.env b/board/nxp/imx95_evk/imx95_evk.env new file mode 100644 index 00000000000..a7309d734b0 --- /dev/null +++ b/board/nxp/imx95_evk/imx95_evk.env @@ -0,0 +1,91 @@ +sec_boot=no +initrd_addr=0x93800000 +emmc_dev=0 +sd_dev=1 +scriptaddr=0x93500000 +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +image=Image +splashimage=0xA0000000 +console=ttyLP0,115200 earlycon +fdt_addr_r=0x93000000 +fdt_addr=0x93000000 +cntr_addr=0xA8000000 +cntr_file=os_cntr_signed.bin +boot_fit=no +fdtfile=CONFIG_DEFAULT_FDT_FILE +bootm_size=0x10000000 +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcautodetect=yes +mmcargs=setenv bootargs console=${console} root=${mmcroot} +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} +auth_os=auth_cntr ${cntr_addr} +boot_os=booti ${loadaddr} - ${fdt_addr_r}; +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${sec_boot} = yes; then + if run auth_os; then + run boot_os; + else + echo ERR: failed to authenticate; + fi; + else + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if run loadfdt; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; + fi; +netargs=setenv bootargs console=${console} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if test ${sec_boot} = yes; then + ${get_cmd} ${cntr_addr} ${cntr_file}; + if run auth_os; then + run boot_os; + else + echo ERR: failed to authenticate; + fi; + else + ${get_cmd} ${loadaddr} ${image}; + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; + fi; +bsp_bootcmd=echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; if mmc rescan; then + if run loadbootscript; then + run bootscript; + else + if test ${sec_boot} = yes; then + if run loadcntr; then + run mmcboot; + else run netboot; + fi; + else + if run loadimage; then + run mmcboot; + else run netboot; + fi; + fi; + fi; + fi; diff --git a/board/nxp/imx95_evk/spl.c b/board/nxp/imx95_evk/spl.c new file mode 100644 index 00000000000..752d7f916b6 --- /dev/null +++ b/board/nxp/imx95_evk/spl.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_board_init(void) +{ + int ret; + + puts("Normal Boot\n"); + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + +#ifdef CONFIG_SPL_RECOVER_DATA_SECTION + if (IS_ENABLED(CONFIG_SPL_BUILD)) + spl_save_restore_data(); +#endif + + timer_init(); + + /* Need dm_init() to run before any SCMI calls can be made. */ + spl_early_init(); + + /* Need enable SCMI drivers and ELE driver before enabling console */ + ret = imx9_probe_mu(); + if (ret) + hang(); /* if MU not probed, nothing can output, just hang here */ + + arch_cpu_init(); + + board_early_init_f(); + + preloader_console_init(); + + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + + get_reset_reason(true, false); + + board_init_r(NULL, 0); +} diff --git a/board/nxp/imxrt1020-evk/Kconfig b/board/nxp/imxrt1020-evk/Kconfig new file mode 100644 index 00000000000..d5b7702b686 --- /dev/null +++ b/board/nxp/imxrt1020-evk/Kconfig @@ -0,0 +1,18 @@ +if TARGET_IMXRT1020_EVK + +config SYS_BOARD + default "imxrt1020-evk" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "imxrt1020" + +config SYS_CONFIG_NAME + default "imxrt1020-evk" + +config IMX_CONFIG + default "board/nxp/imxrt1020-evk/imximage.cfg" + +endif diff --git a/board/nxp/imxrt1020-evk/MAINTAINERS b/board/nxp/imxrt1020-evk/MAINTAINERS new file mode 100644 index 00000000000..a587e5d0f68 --- /dev/null +++ b/board/nxp/imxrt1020-evk/MAINTAINERS @@ -0,0 +1,6 @@ +IMXRT1020 EVALUATION KIT +M: Giulio Benetti +S: Maintained +F: board/nxp/imxrt1020-evk +F: include/configs/imxrt1020-evk.h +F: configs/imxrt1020-evk_defconfig diff --git a/board/nxp/imxrt1020-evk/Makefile b/board/nxp/imxrt1020-evk/Makefile new file mode 100644 index 00000000000..807dc7c35e1 --- /dev/null +++ b/board/nxp/imxrt1020-evk/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 +# Author(s): Giulio Benetti + +obj-y := imxrt1020-evk.o diff --git a/board/nxp/imxrt1020-evk/imximage.cfg b/board/nxp/imxrt1020-evk/imximage.cfg new file mode 100644 index 00000000000..0ed71479a60 --- /dev/null +++ b/board/nxp/imxrt1020-evk/imximage.cfg @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 + * Author(s): Giulio Benetti + */ + +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Set all FlexRAM as OCRAM(01b) */ +DATA 4 0x400AC044 0x00005555 +/* Use FLEXRAM_BANK_CFG to config FlexRAM */ +SET_BIT 4 0x400AC040 0x4 diff --git a/board/nxp/imxrt1020-evk/imxrt1020-evk.c b/board/nxp/imxrt1020-evk/imxrt1020-evk.c new file mode 100644 index 00000000000..11dbef84688 --- /dev/null +++ b/board/nxp/imxrt1020-evk/imxrt1020-evk.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 + * Author(s): Giulio Benetti + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ +#ifndef CONFIG_SUPPORT_SPL + int rv; + struct udevice *dev; + + rv = uclass_get_device(UCLASS_RAM, 0, &dev); + if (rv) { + debug("DRAM init failed: %d\n", rv); + return rv; + } + +#endif + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +#ifdef CONFIG_XPL_BUILD +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + debug("SPL: booting kernel\n"); + /* break into full u-boot on 'c' */ + return serial_tstc() && serial_getc() == 'c'; +} +#endif + +int spl_dram_init(void) +{ + struct udevice *dev; + int rv; + + rv = uclass_get_device(UCLASS_RAM, 0, &dev); + if (rv) + debug("DRAM init failed: %d\n", rv); + return rv; +} + +void spl_board_init(void) +{ + preloader_console_init(); + spl_dram_init(); + arch_cpu_init(); /* to configure mpu for sdram rw permissions */ +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} +#endif + +int board_init(void) +{ + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + + return 0; +} diff --git a/board/nxp/imxrt1050-evk/Kconfig b/board/nxp/imxrt1050-evk/Kconfig new file mode 100644 index 00000000000..8dd7511c0c8 --- /dev/null +++ b/board/nxp/imxrt1050-evk/Kconfig @@ -0,0 +1,18 @@ +if TARGET_IMXRT1050_EVK + +config SYS_BOARD + default "imxrt1050-evk" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "imxrt1050" + +config SYS_CONFIG_NAME + default "imxrt1050-evk" + +config IMX_CONFIG + default "board/nxp/imxrt1050-evk/imximage.cfg" + +endif diff --git a/board/nxp/imxrt1050-evk/MAINTAINERS b/board/nxp/imxrt1050-evk/MAINTAINERS new file mode 100644 index 00000000000..9c0e6cfb3bb --- /dev/null +++ b/board/nxp/imxrt1050-evk/MAINTAINERS @@ -0,0 +1,7 @@ +IMXRT1050 EVALUATION KIT +M: Giulio Benetti +S: Maintained +F: board/nxp/imxrt1050-evk +F: include/configs/imxrt1050-evk.h +F: configs/imxrt1050-evk_defconfig +F: configs/imxrt1050-evk_fspi_defconfig diff --git a/board/nxp/imxrt1050-evk/Makefile b/board/nxp/imxrt1050-evk/Makefile new file mode 100644 index 00000000000..0e984d1d7a8 --- /dev/null +++ b/board/nxp/imxrt1050-evk/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 +# Author(s): Giulio Benetti + +obj-y := imxrt1050-evk.o diff --git a/board/nxp/imxrt1050-evk/imximage-nor.cfg b/board/nxp/imxrt1050-evk/imximage-nor.cfg new file mode 100644 index 00000000000..829be6cbe2b --- /dev/null +++ b/board/nxp/imxrt1050-evk/imximage-nor.cfg @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2024 + * Author(s): Jesse Taube + */ + +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM nor + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * 0x400AC044 is used to configure the flexram. + * Unfortunately setting all to OCRAM only works for MMC + * and setting all to DTCM only works for FLEXSPI NOR. + * This configuration fortunately works for both SPI and MMC. +*/ +/* Set first two banks FlexRAM as OCRAM(01b) and the rest to DTCM(10b) */ +DATA 4 0x400AC044 0x55aaaaaa +/* Use FLEXRAM_BANK_CFG to config FlexRAM */ +SET_BIT 4 0x400AC040 0x4 diff --git a/board/nxp/imxrt1050-evk/imximage.cfg b/board/nxp/imxrt1050-evk/imximage.cfg new file mode 100644 index 00000000000..b30d8521947 --- /dev/null +++ b/board/nxp/imxrt1050-evk/imximage.cfg @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * 0x400AC044 is used to configure the flexram. + * Unfortunately setting all to OCRAM only works for MMC + * and setting all to DTCM only works for FLEXSPI NOR. + * This configuration fortunately works for both SPI and MMC. +*/ +/* Set first two banks FlexRAM as OCRAM(01b) and the rest to DTCM(10b) */ +DATA 4 0x400AC044 0x55aaaaaa +/* Use FLEXRAM_BANK_CFG to config FlexRAM */ +SET_BIT 4 0x400AC040 0x4 diff --git a/board/nxp/imxrt1050-evk/imxrt1050-evk-nor.env b/board/nxp/imxrt1050-evk/imxrt1050-evk-nor.env new file mode 100644 index 00000000000..c61e9e3c00a --- /dev/null +++ b/board/nxp/imxrt1050-evk/imxrt1050-evk-nor.env @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* environment for imxrt1050-evk */ + +#ifdef CONFIG_VIDEO +stdin=serial +stdout=serial,vidconsole +stderr=serial,vidconsole +#endif + +fdt_addr_r=0x80800000 +kernel_addr_r=0x80000000 +boot_targets=nor diff --git a/board/nxp/imxrt1050-evk/imxrt1050-evk.c b/board/nxp/imxrt1050-evk/imxrt1050-evk.c new file mode 100644 index 00000000000..056489932ac --- /dev/null +++ b/board/nxp/imxrt1050-evk/imxrt1050-evk.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ +#ifndef CONFIG_SUPPORT_SPL + int rv; + struct udevice *dev; + + rv = uclass_get_device(UCLASS_RAM, 0, &dev); + if (rv) { + debug("DRAM init failed: %d\n", rv); + return rv; + } + +#endif + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +#ifdef CONFIG_XPL_BUILD +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + debug("SPL: booting kernel\n"); + /* break into full u-boot on 'c' */ + return serial_tstc() && serial_getc() == 'c'; +} +#endif + +int spl_dram_init(void) +{ + struct udevice *dev; + int rv; + + rv = uclass_get_device(UCLASS_RAM, 0, &dev); + if (rv) + debug("DRAM init failed: %d\n", rv); + return rv; +} + +void spl_board_init(void) +{ + preloader_console_init(); + spl_dram_init(); + arch_cpu_init(); /* to configure mpu for sdram rw permissions */ +} + +u32 spl_boot_device(void) +{ + /* There is no way to find the boot device so look if there is a valid IVT in RAM for MMC */ + u32 nor_ivt = *(u32 *)(CONFIG_SYS_LOAD_ADDR - 0xC00); + + if (nor_ivt == 0x402000d1) + return BOOT_DEVICE_MMC1; + return BOOT_DEVICE_NOR; +} +#endif + +int board_init(void) +{ + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + + return 0; +} diff --git a/board/nxp/imxrt1050-evk/imxrt1050-evk.env b/board/nxp/imxrt1050-evk/imxrt1050-evk.env new file mode 100644 index 00000000000..1c5cbc29d53 --- /dev/null +++ b/board/nxp/imxrt1050-evk/imxrt1050-evk.env @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +/* environment for imxrt1050-evk */ + +#ifdef CONFIG_VIDEO +stdin=serial +stdout=serial,vidconsole +stderr=serial,vidconsole +#endif + +fdt_addr_r=0x80800000 +kernel_addr_r=0x80000000 +boot_targets=mmc diff --git a/board/nxp/imxrt1170-evk/Kconfig b/board/nxp/imxrt1170-evk/Kconfig new file mode 100644 index 00000000000..6f804c10893 --- /dev/null +++ b/board/nxp/imxrt1170-evk/Kconfig @@ -0,0 +1,18 @@ +if TARGET_IMXRT1170_EVK + +config SYS_BOARD + default "imxrt1170-evk" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "imxrt1170" + +config SYS_CONFIG_NAME + default "imxrt1170-evk" + +config IMX_CONFIG + default "board/nxp/imxrt1170-evk/imximage.cfg" + +endif diff --git a/board/nxp/imxrt1170-evk/MAINTAINERS b/board/nxp/imxrt1170-evk/MAINTAINERS new file mode 100644 index 00000000000..239cda84b74 --- /dev/null +++ b/board/nxp/imxrt1170-evk/MAINTAINERS @@ -0,0 +1,7 @@ +IMXRT1170 EVALUATION KIT +M: Giulio Benetti +M: Jesse Taube +S: Maintained +F: board/nxp/imxrt1170-evk +F: include/configs/imxrt1170-evk.h +F: configs/imxrt1170-evk_defconfig diff --git a/board/nxp/imxrt1170-evk/Makefile b/board/nxp/imxrt1170-evk/Makefile new file mode 100644 index 00000000000..857a168b09d --- /dev/null +++ b/board/nxp/imxrt1170-evk/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 +# Author(s): Giulio Benetti + +obj-y := imxrt1170-evk.o diff --git a/board/nxp/imxrt1170-evk/imximage.cfg b/board/nxp/imxrt1170-evk/imximage.cfg new file mode 100644 index 00000000000..57583d04ce6 --- /dev/null +++ b/board/nxp/imxrt1170-evk/imximage.cfg @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 + * Author(s): Jesse Taube + * Giulio Benetti + */ + +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ diff --git a/board/nxp/imxrt1170-evk/imxrt1170-evk.c b/board/nxp/imxrt1170-evk/imxrt1170-evk.c new file mode 100644 index 00000000000..047aea8181a --- /dev/null +++ b/board/nxp/imxrt1170-evk/imxrt1170-evk.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ +#ifndef CONFIG_SUPPORT_SPL + int rv; + struct udevice *dev; + + rv = uclass_get_device(UCLASS_RAM, 0, &dev); + if (rv) { + debug("DRAM init failed: %d\n", rv); + return rv; + } + +#endif + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +#ifdef CONFIG_XPL_BUILD +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + debug("SPL: booting kernel\n"); + /* break into full u-boot on 'c' */ + return serial_tstc() && serial_getc() == 'c'; +} +#endif + +int spl_dram_init(void) +{ + struct udevice *dev; + int rv; + + rv = uclass_get_device(UCLASS_RAM, 0, &dev); + if (rv) + debug("DRAM init failed: %d\n", rv); + return rv; +} + +void spl_board_init(void) +{ + preloader_console_init(); + spl_dram_init(); + arch_cpu_init(); /* to configure mpu for sdram rw permissions */ +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} +#endif + +int board_init(void) +{ + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + + return 0; +} diff --git a/board/nxp/ls1012afrdm/Kconfig b/board/nxp/ls1012afrdm/Kconfig new file mode 100644 index 00000000000..26856f2d4e4 --- /dev/null +++ b/board/nxp/ls1012afrdm/Kconfig @@ -0,0 +1,80 @@ +if TARGET_LS1012AFRDM + +config SYS_BOARD + default "ls1012afrdm" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012afrdm" + +config SYS_LS_PFE_FW_ADDR + hex "Flash address of PFE firmware" + default 0x40a00000 + +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x40000 + +endif + +if FSL_PFE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select PHYLIB + imply PHY_REALTEK + imply PHY_ATHEROS + +config DDR_PFE_PHYS_BASEADDR + hex "PFE DDR physical base address" + default 0x03800000 + +config DDR_PFE_BASEADDR + hex "PFE DDR base address" + default 0x83800000 + +config PFE_EMAC1_PHY_ADDR + hex "PFE DDR base address" + default 0x2 + +config PFE_EMAC2_PHY_ADDR + hex "PFE DDR base address" + default 0x1 + +endif + +if TARGET_LS1012AFRWY + +config SYS_BOARD + default "ls1012afrdm" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012afrwy" + +config SYS_LS_PFE_FW_ADDR + hex "Flash address of PFE firmware" + default 0x40020000 + +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x40000 + +config SYS_LS_PFE_ESBC_ADDR + hex "PFE Firmware HDR Addr" + default 0x401f8000 + +config SYS_LS_PFE_ESBC_LENGTH + hex "length of PFE Firmware HDR" + default 0xc00 +endif diff --git a/board/nxp/ls1012afrdm/MAINTAINERS b/board/nxp/ls1012afrdm/MAINTAINERS new file mode 100644 index 00000000000..a69c268e53b --- /dev/null +++ b/board/nxp/ls1012afrdm/MAINTAINERS @@ -0,0 +1,17 @@ +LS1012AFRDM BOARD +M: Pramod Kumar +S: Maintained +F: board/nxp/ls1012afrdm/ +F: include/configs/ls1012afrdm.h +F: configs/ls1012afrdm_qspi_defconfig +F: configs/ls1012afrdm_tfa_defconfig +F: configs/ls1012afrwy_tfa_defconfig +F: configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig + +LS1012AFRWY BOARD +M: Pramod Kumar +S: Maintained +F: board/nxp/ls1012afrwy/ +F: include/configs/ls1012afrwy.h +F: configs/ls1012afrwy_qspi_defconfig +F: configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig diff --git a/board/nxp/ls1012afrdm/Makefile b/board/nxp/ls1012afrdm/Makefile new file mode 100644 index 00000000000..1e53c967304 --- /dev/null +++ b/board/nxp/ls1012afrdm/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1012afrdm.o +obj-$(CONFIG_FSL_PFE) += eth.o diff --git a/board/nxp/ls1012afrdm/README b/board/nxp/ls1012afrdm/README new file mode 100644 index 00000000000..e60ed606ec1 --- /dev/null +++ b/board/nxp/ls1012afrdm/README @@ -0,0 +1,58 @@ +Overview +-------- +QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development +platform, with a complete debugging environment. The LS1012AFRDM board +supports the QorIQ LS1012A processor and is optimized to support the +high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. + +LS1012A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A +SoC overview. + + LS1012AFRDM board Overview + ----------------------- + - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s + - 2 SGMII 1G PHYs + - DDR Controller + - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s + operating at 1.35 V + - QSPI + - Onboard 512 Mbit QSPI flash memory running at speed up + to 108/54 MHz + - One high-speed USB 2.0/3.0 port, one USB 2.0 port + - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a + Micro-AB connector. + - USB 2.0 port is a debug port (CMSIS DAP) and is configured + as a Micro-AB device. + - I2C controller + - One I2C bus with connectivity to Arduino headers + - UART + - UART (Console): UART1 (Without flow control) for console + - ARM JTAG support + - ARM Cortex® 10-pin JTAG connector for LS1012A + - CMSIS DAP through K20 microcontroller + - SAI Audio interface + - One SAI port, SAI 2 with full duplex support + - Clocks + - 25 MHz crystal for LS1012A + - 8 MHz Crystal for K20 + - 24 MHz for SC16IS740IPW SPI to Dual UART bridge + - Power Supplies + - 5 V input supply from USB + - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and + other board interfaces + +Booting Options +--------------- +QSPI Flash 1 + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-Boot | 1MB | 0x4010_0000 +U-Boot Env | 1MB | 0x4020_0000 +PPA FIT image | 2MB | 0x4050_0000 +Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/nxp/ls1012afrdm/eth.c b/board/nxp/ls1012afrdm/eth.c new file mode 100644 index 00000000000..c431e5e611b --- /dev/null +++ b/board/nxp/ls1012afrdm/eth.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" +#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1" + +#define MASK_ETH_PHY_RST 0x00000100 + +static inline void ls1012afrdm_reset_phy(void) +{ + unsigned int val; + struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR); + + setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST); + + val = in_be32(&pgpio->gpdat); + setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST); + mdelay(10); + + val = in_be32(&pgpio->gpdat); + setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST); + mdelay(50); +} + +int pfe_eth_board_init(struct udevice *dev) +{ + static int init_done; + struct mii_dev *bus; + struct pfe_mdio_info mac_mdio_info; + struct pfe_eth_dev *priv = dev_get_priv(dev); + + if (!init_done) { + ls1012afrdm_reset_phy(); + + mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; + mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME; + + bus = pfe_mdio_init(&mac_mdio_info); + if (!bus) { + printf("Failed to register mdio\n"); + return -1; + } + + init_done = 1; + } + + if (priv->gemac_port) { + mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR; + mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME; + bus = pfe_mdio_init(&mac_mdio_info); + if (!bus) { + printf("Failed to register mdio\n"); + return -1; + } + } + + pfe_set_mdio(priv->gemac_port, + miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); + if (!priv->gemac_port) + /* MAC1 */ + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC1_PHY_ADDR, + PHY_INTERFACE_MODE_SGMII); + else + /* MAC2 */ + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC2_PHY_ADDR, + PHY_INTERFACE_MODE_SGMII); + return 0; +} + +static struct pfe_eth_pdata pfe_pdata0 = { + .pfe_eth_pdata_mac = { + .iobase = (phys_addr_t)EMAC1_BASE_ADDR, + .phy_interface = 0, + }, + + .pfe_ddr_addr = { + .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, + .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, + }, +}; + +static struct pfe_eth_pdata pfe_pdata1 = { + .pfe_eth_pdata_mac = { + .iobase = (phys_addr_t)EMAC2_BASE_ADDR, + .phy_interface = 1, + }, + + .pfe_ddr_addr = { + .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, + .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, + }, +}; + +U_BOOT_DRVINFO(ls1012a_pfe0) = { + .name = "pfe_eth", + .plat = &pfe_pdata0, +}; + +U_BOOT_DRVINFO(ls1012a_pfe1) = { + .name = "pfe_eth", + .plat = &pfe_pdata1, +}; diff --git a/board/nxp/ls1012afrdm/ls1012afrdm.c b/board/nxp/ls1012afrdm/ls1012afrdm.c new file mode 100644 index 00000000000..f157e75e385 --- /dev/null +++ b/board/nxp/ls1012afrdm/ls1012afrdm.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018, 2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static inline int get_board_version(void) +{ + uint32_t val; +#ifdef CONFIG_TARGET_LS1012AFRDM + val = 0; +#else + struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR); + + val = in_be32(&pgpio->gpdat) & BOARD_REV_MASK;/*Get GPIO2 11,12,14*/ + +#endif + return val; +} + +int checkboard(void) +{ +#ifdef CONFIG_TARGET_LS1012AFRDM + puts("Board: LS1012AFRDM "); +#else + int rev; + + rev = get_board_version(); + + puts("Board: FRWY-LS1012A "); + + puts("Version"); + + switch (rev) { + case BOARD_REV_A_B: + puts(": RevA/B "); + break; + case BOARD_REV_C: + puts(": RevC "); + break; + default: + puts(": unknown"); + break; + } +#endif + + return 0; +} + +#ifdef CONFIG_TARGET_LS1012AFRWY +int esdhc_status_fixup(void *blob, const char *compat) +{ + char esdhc0_path[] = "/soc/esdhc@1560000"; + char esdhc1_path[] = "/soc/esdhc@1580000"; + + do_fixup_by_path(blob, esdhc0_path, "status", "okay", + sizeof("okay"), 1); + + do_fixup_by_path(blob, esdhc1_path, "status", "disabled", + sizeof("disabled"), 1); + return 0; +} +#endif + +#ifdef CONFIG_TFABOOT +int dram_init(void) +{ +#ifdef CONFIG_TARGET_LS1012AFRWY + int board_rev; +#endif + + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) { +#ifdef CONFIG_TARGET_LS1012AFRWY + board_rev = get_board_version(); + + if (board_rev & BOARD_REV_C) + gd->ram_size = SYS_SDRAM_SIZE_1024; + else + gd->ram_size = SYS_SDRAM_SIZE_512; +#else + gd->ram_size = CFG_SYS_SDRAM_SIZE; +#endif + } + return 0; +} +#else +int dram_init(void) +{ +#ifdef CONFIG_TARGET_LS1012AFRWY + int board_rev; +#endif + struct fsl_mmdc_info mparam = { + 0x04180000, /* mdctl */ + 0x00030035, /* mdpdc */ + 0x12554000, /* mdotc */ + 0xbabf7954, /* mdcfg0 */ + 0xdb328f64, /* mdcfg1 */ + 0x01ff00db, /* mdcfg2 */ + 0x00001680, /* mdmisc */ + 0x0f3c8000, /* mdref */ + 0x00002000, /* mdrwd */ + 0x00bf1023, /* mdor */ + 0x0000003f, /* mdasp */ + 0x0000022a, /* mpodtctrl */ + 0xa1390003, /* mpzqhwctrl */ + }; + +#ifdef CONFIG_TARGET_LS1012AFRWY + board_rev = get_board_version(); + + if (board_rev == BOARD_REV_C) { + mparam.mdctl = 0x05180000; + gd->ram_size = SYS_SDRAM_SIZE_1024; + } else { + gd->ram_size = SYS_SDRAM_SIZE_512; + } +#else + gd->ram_size = CFG_SYS_SDRAM_SIZE; +#endif + mmdc_init(&mparam); + +#if !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif + + return 0; +} +#endif + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + + CONFIG_SYS_CCI400_OFFSET); + + /* + * Set CCI-400 control override register to enable barrier + * transaction + */ + if (current_el() == 3) + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + + return 0; +} + +#ifdef CONFIG_FSL_PFE +void board_quiesce_devices(void) +{ + pfe_command_stop(0, NULL); +} +#endif + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + arch_fixup_fdt(blob); + + ft_cpu_setup(blob, bd); + + return 0; +} diff --git a/board/nxp/ls1012aqds/Kconfig b/board/nxp/ls1012aqds/Kconfig new file mode 100644 index 00000000000..51751fc96fc --- /dev/null +++ b/board/nxp/ls1012aqds/Kconfig @@ -0,0 +1,72 @@ +if TARGET_LS1012AQDS + +config SYS_BOARD + default "ls1012aqds" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012aqds" + +if CHAIN_OF_TRUST +config SYS_LS_PFE_ESBC_ADDR + hex "PFE Firmware HDR Addr" + default 0x40700000 + +config SYS_LS_PFE_ESBC_LENGTH + hex "length of PFE Firmware HDR" + default 0xc00 +endif + +if FSL_PFE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select PHYLIB + imply PHY_VITESSE + imply PHY_REALTEK + imply PHY_AQUANTIA + imply PHYLIB_10G + +config PFE_RGMII_RESET_WA + def_bool y + +config SYS_LS_PFE_FW_ADDR + hex "Flash address of PFE firmware" + default 0x40a00000 + +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x300000 + +config DDR_PFE_PHYS_BASEADDR + hex "PFE DDR physical base address" + default 0x03800000 + +config DDR_PFE_BASEADDR + hex "PFE DDR base address" + default 0x83800000 + +config PFE_EMAC1_PHY_ADDR + hex "PFE DDR base address" + default 0x1e + +config PFE_EMAC2_PHY_ADDR + hex "PFE DDR base address" + default 0x1 + +config PFE_SGMII_2500_PHY1_ADDR + hex "PFE DDR base address" + default 0x1 + +config PFE_SGMII_2500_PHY2_ADDR + hex "PFE DDR base address" + default 0x2 + +endif + +endif diff --git a/board/nxp/ls1012aqds/MAINTAINERS b/board/nxp/ls1012aqds/MAINTAINERS new file mode 100644 index 00000000000..2178df90992 --- /dev/null +++ b/board/nxp/ls1012aqds/MAINTAINERS @@ -0,0 +1,8 @@ +LS1012AQDS BOARD +M: Pramod Kumar +S: Maintained +F: board/nxp/ls1012aqds/ +F: include/configs/ls1012aqds.h +F: configs/ls1012aqds_qspi_defconfig +F: configs/ls1012aqds_tfa_defconfig +F: configs/ls1012aqds_tfa_SECURE_BOOT_defconfig diff --git a/board/nxp/ls1012aqds/Makefile b/board/nxp/ls1012aqds/Makefile new file mode 100644 index 00000000000..5aba9caf927 --- /dev/null +++ b/board/nxp/ls1012aqds/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1012aqds.o +obj-$(CONFIG_FSL_PFE) += eth.o diff --git a/board/nxp/ls1012aqds/README b/board/nxp/ls1012aqds/README new file mode 100644 index 00000000000..e9b80cad506 --- /dev/null +++ b/board/nxp/ls1012aqds/README @@ -0,0 +1,59 @@ +Overview +-------- +QorIQ LS1012A Development System (LS1012AQDS) is a high-performance +development platform, with a complete debugging environment. +The LS1012AQDS board supports the QorIQ LS1012A processor and is +optimized to support the high-bandwidth DDR3L memory and +a full complement of high-speed SerDes ports. + +LS1012A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A +SoC overview. + +LS1012AQDS board Overview +----------------------- + - SERDES Connections, 4 lanes supporting: + - PCI Express - 3.0 + - SGMII, SGMII 2.5 + - SATA 3.0 + - DDR Controller + - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s + - QSPI Controller + - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select + signals to QSPI NOR flash memory (2 virtual banks) and the QSPI + emulator + - USB 3.0 + - One USB 3.0 controller with integrated PHY + - One high-speed USB 3.0 port + - USB 2.0 + - One USB 2.0 controller with ULPI interface + - Two enhanced secure digital host controllers: + - SDHC1 controller can be connected to onboard SDHC connector + - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices + - 2 I2C controllers + - One SATA onboard connectors + - UART + - 5 SAI + - One SAI port with audio codec SGTL5000: + • Provides MIC bias + • Provides headphone and line output + - One SAI port terminated at 2x6 header + - Three SAI Tx/Rx ports terminated at 2x3 headers + - ARM JTAG support + +Booting Options +--------------- +a) QSPI Flash Emu Boot +b) QSPI Flash 1 +c) QSPI Flash 2 + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-Boot | 1MB | 0x4010_0000 +U-Boot Env | 1MB | 0x4020_0000 +PPA FIT image | 2MB | 0x4050_0000 +Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/nxp/ls1012aqds/eth.c b/board/nxp/ls1012aqds/eth.c new file mode 100644 index 00000000000..d5e87c5393b --- /dev/null +++ b/board/nxp/ls1012aqds/eth.c @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/qixis.h" +#include +#include +#include "ls1012aqds_qixis.h" + +#define EMI_NONE 0xFF +#define EMI1_RGMII 1 +#define EMI1_SLOT1 2 +#define EMI1_SLOT2 3 + +#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" +#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1" + +static const char * const mdio_names[] = { + "NULL", + "LS1012AQDS_MDIO_RGMII", + "LS1012AQDS_MDIO_SLOT1", + "LS1012AQDS_MDIO_SLOT2", + "NULL", +}; + +static const char *ls1012aqds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct ls1012aqds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static void ls1012aqds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + + if (muxval < 7) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int ls1012aqds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct ls1012aqds_mdio *priv = bus->priv; + + ls1012aqds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int ls1012aqds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct ls1012aqds_mdio *priv = bus->priv; + + ls1012aqds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int ls1012aqds_mdio_reset(struct mii_dev *bus) +{ + struct ls1012aqds_mdio *priv = bus->priv; + + if (priv->realbus->reset) + return priv->realbus->reset(priv->realbus); + else + return -1; +} + +static int ls1012aqds_mdio_init(char *realbusname, u8 muxval) +{ + struct ls1012aqds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate ls1012aqds MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate ls1012aqds private data\n"); + free(bus); + return -1; + } + + bus->read = ls1012aqds_mdio_read; + bus->write = ls1012aqds_mdio_write; + bus->reset = ls1012aqds_mdio_reset; + sprintf(bus->name, ls1012aqds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + return mdio_register(bus); +} + +int pfe_eth_board_init(struct udevice *dev) +{ + static int init_done; + struct mii_dev *bus; + static const char *mdio_name; + struct pfe_mdio_info mac_mdio_info; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; + u8 data8; + struct pfe_eth_dev *priv = dev_get_priv(dev); + + int srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + ls1012aqds_mux_mdio(EMI1_SLOT1); + + if (!init_done) { + mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; + mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME; + + bus = pfe_mdio_init(&mac_mdio_info); + if (!bus) { + printf("Failed to register mdio\n"); + return -1; + } + init_done = 1; + } + + if (priv->gemac_port) { + mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR; + mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME; + + bus = pfe_mdio_init(&mac_mdio_info); + if (!bus) { + printf("Failed to register mdio\n"); + return -1; + } + } + + switch (srds_s1) { + case 0x3508: + printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1); +#ifdef CONFIG_PFE_RGMII_RESET_WA + /* + * Work around for FPGA registers initialization + * This is needed for RGMII to work. + */ + printf("Reset RGMII WA....\n"); + data8 = QIXIS_READ(rst_frc[0]); + data8 |= 0x2; + QIXIS_WRITE(rst_frc[0], data8); + data8 = QIXIS_READ(rst_frc[0]); + + data8 = QIXIS_READ(res8[6]); + data8 |= 0xff; + QIXIS_WRITE(res8[6], data8); + data8 = QIXIS_READ(res8[6]); +#endif + if (priv->gemac_port) { + mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII); + if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_RGMII) + < 0) { + printf("Failed to register mdio for %s\n", mdio_name); + } + + /* MAC2 */ + mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII); + bus = miiphy_get_dev_by_name(mdio_name); + pfe_set_mdio(priv->gemac_port, bus); + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC2_PHY_ADDR, + PHY_INTERFACE_MODE_RGMII); + + } else { + mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1); + if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1) + < 0) { + printf("Failed to register mdio for %s\n", mdio_name); + } + + /* MAC1 */ + mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1); + bus = miiphy_get_dev_by_name(mdio_name); + pfe_set_mdio(priv->gemac_port, bus); + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC1_PHY_ADDR, + PHY_INTERFACE_MODE_SGMII); + } + + break; + + case 0x2205: + printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1); + /* + * Work around for FPGA registers initialization + * This is needed for RGMII to work. + */ + printf("Reset SLOT1 SLOT2....\n"); + data8 = QIXIS_READ(rst_frc[2]); + data8 |= 0xc0; + QIXIS_WRITE(rst_frc[2], data8); + mdelay(100); + data8 = QIXIS_READ(rst_frc[2]); + data8 &= 0x3f; + QIXIS_WRITE(rst_frc[2], data8); + + if (priv->gemac_port) { + mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2); + if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT2) + < 0) { + printf("Failed to register mdio for %s\n", mdio_name); + } + /* MAC2 */ + mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2); + bus = miiphy_get_dev_by_name(mdio_name); + pfe_set_mdio(1, bus); + pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR, + PHY_INTERFACE_MODE_2500BASEX); + + data8 = QIXIS_READ(brdcfg[12]); + data8 |= 0x20; + QIXIS_WRITE(brdcfg[12], data8); + + } else { + mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1); + if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1) + < 0) { + printf("Failed to register mdio for %s\n", mdio_name); + } + + /* MAC1 */ + mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1); + bus = miiphy_get_dev_by_name(mdio_name); + pfe_set_mdio(0, bus); + pfe_set_phy_address_mode(0, + CONFIG_PFE_SGMII_2500_PHY1_ADDR, + PHY_INTERFACE_MODE_2500BASEX); + } + break; + + default: + printf("ls1012aqds:unsupported SerDes PRCTL= %d\n", srds_s1); + break; + } + return 0; +} + +static struct pfe_eth_pdata pfe_pdata0 = { + .pfe_eth_pdata_mac = { + .iobase = (phys_addr_t)EMAC1_BASE_ADDR, + .phy_interface = 0, + }, + + .pfe_ddr_addr = { + .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, + .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, + }, +}; + +static struct pfe_eth_pdata pfe_pdata1 = { + .pfe_eth_pdata_mac = { + .iobase = (phys_addr_t)EMAC2_BASE_ADDR, + .phy_interface = 1, + }, + + .pfe_ddr_addr = { + .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, + .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, + }, +}; + +U_BOOT_DRVINFO(ls1012a_pfe0) = { + .name = "pfe_eth", + .plat = &pfe_pdata0, +}; + +U_BOOT_DRVINFO(ls1012a_pfe1) = { + .name = "pfe_eth", + .plat = &pfe_pdata1, +}; diff --git a/board/nxp/ls1012aqds/ls1012aqds.c b/board/nxp/ls1012aqds/ls1012aqds.c new file mode 100644 index 00000000000..b21c4d917d0 --- /dev/null +++ b/board/nxp/ls1012aqds/ls1012aqds.c @@ -0,0 +1,287 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/qixis.h" +#include "ls1012aqds_qixis.h" +#include "ls1012aqds_pfe.h" +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + char buf[64]; + u8 sw; + + sw = QIXIS_READ(arch); + printf("Board Arch: V%d, ", sw >> 4); + printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); + + sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); + + if (sw & QIXIS_LBMAP_ALTBANK) + printf("flash: 2\n"); + else + printf("flash: 1\n"); + + printf("FPGA: v%d (%s), build %d", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + + /* the timestamp string contains "\n" at the end */ + printf(" on %s", qixis_read_time(buf)); + return 0; +} + +#ifdef CONFIG_TFABOOT +int dram_init(void) +{ + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) + gd->ram_size = CFG_SYS_SDRAM_SIZE; + + return 0; +} +#else +int dram_init(void) +{ + static const struct fsl_mmdc_info mparam = { + 0x05180000, /* mdctl */ + 0x00030035, /* mdpdc */ + 0x12554000, /* mdotc */ + 0xbabf7954, /* mdcfg0 */ + 0xdb328f64, /* mdcfg1 */ + 0x01ff00db, /* mdcfg2 */ + 0x00001680, /* mdmisc */ + 0x0f3c8000, /* mdref */ + 0x00002000, /* mdrwd */ + 0x00bf1023, /* mdor */ + 0x0000003f, /* mdasp */ + 0x0000022a, /* mpodtctrl */ + 0xa1390003, /* mpzqhwctrl */ + }; + + mmdc_init(&mparam); + gd->ram_size = CFG_SYS_SDRAM_SIZE; +#if !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif + + return 0; +} +#endif + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + u8 mux_sdhc_cd = 0x80; + int bus_num = 0; + +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_FPGA_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1); +#else + i2c_set_bus_num(bus_num); + + i2c_write(CFG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); +#endif + + return 0; +} +#endif + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + + CONFIG_SYS_CCI400_OFFSET); + + /* Set CCI-400 control override register to enable barrier + * transaction */ + if (current_el() == 3) + out_le32(&cci->ctrl_ord, + CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + + return 0; +} + +#ifdef CONFIG_FSL_PFE +void board_quiesce_devices(void) +{ + pfe_command_stop(0, NULL); +} +#endif + +int esdhc_status_fixup(void *blob, const char *compat) +{ + char esdhc0_path[] = "/soc/esdhc@1560000"; + char esdhc1_path[] = "/soc/esdhc@1580000"; + u8 card_id; + + do_fixup_by_path(blob, esdhc0_path, "status", "okay", + sizeof("okay"), 1); + + /* + * The Presence Detect 2 register detects the installation + * of cards in various PCI Express or SGMII slots. + * + * STAT_PRS2[7:5]: Specifies the type of card installed in the + * SDHC2 Adapter slot. 0b111 indicates no adapter is installed. + */ + card_id = (QIXIS_READ(present2) & 0xe0) >> 5; + + /* If no adapter is installed in SDHC2, disable SDHC2 */ + if (card_id == 0x7) + do_fixup_by_path(blob, esdhc1_path, "status", "disabled", + sizeof("disabled"), 1); + else + do_fixup_by_path(blob, esdhc1_path, "status", "okay", + sizeof("okay"), 1); + return 0; +} + +static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val, + char *enet_path, char *mdio_path) +{ + do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id", + &prop_val.busid, PFE_PROP_LEN, 1); + do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id", + &prop_val.phyid, PFE_PROP_LEN, 1); + do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val", + &prop_val.mux_val, PFE_PROP_LEN, 1); + do_fixup_by_path(set_blob, enet_path, "phy-mode", + prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1); + do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask", + &prop_val.phy_mask, PFE_PROP_LEN, 1); + return 0; +} + +static void fdt_fsl_fixup_of_pfe(void *blob) +{ + int i = 0; + struct pfe_prop_val prop_val; + void *l_blob = blob; + + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; + unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + for (i = 0; i < NUM_ETH_NODE; i++) { + switch (srds_s1) { + case SERDES_1_G_PROTOCOL: + if (i == 0) { + prop_val.busid = cpu_to_fdt32( + ETH_1_1G_BUS_ID); + prop_val.phyid = cpu_to_fdt32( + ETH_1_1G_PHY_ID); + prop_val.mux_val = cpu_to_fdt32( + ETH_1_1G_MDIO_MUX); + prop_val.phy_mask = cpu_to_fdt32( + ETH_1G_MDIO_PHY_MASK); + prop_val.phy_mode = "sgmii"; + pfe_set_properties(l_blob, prop_val, ETH_1_PATH, + ETH_1_MDIO); + } else { + prop_val.busid = cpu_to_fdt32( + ETH_2_1G_BUS_ID); + prop_val.phyid = cpu_to_fdt32( + ETH_2_1G_PHY_ID); + prop_val.mux_val = cpu_to_fdt32( + ETH_2_1G_MDIO_MUX); + prop_val.phy_mask = cpu_to_fdt32( + ETH_1G_MDIO_PHY_MASK); + prop_val.phy_mode = "rgmii"; + pfe_set_properties(l_blob, prop_val, ETH_2_PATH, + ETH_2_MDIO); + } + break; + case SERDES_2_5_G_PROTOCOL: + if (i == 0) { + prop_val.busid = cpu_to_fdt32( + ETH_1_2_5G_BUS_ID); + prop_val.phyid = cpu_to_fdt32( + ETH_1_2_5G_PHY_ID); + prop_val.mux_val = cpu_to_fdt32( + ETH_1_2_5G_MDIO_MUX); + prop_val.phy_mask = cpu_to_fdt32( + ETH_2_5G_MDIO_PHY_MASK); + prop_val.phy_mode = "2500base-x"; + pfe_set_properties(l_blob, prop_val, ETH_1_PATH, + ETH_1_MDIO); + } else { + prop_val.busid = cpu_to_fdt32( + ETH_2_2_5G_BUS_ID); + prop_val.phyid = cpu_to_fdt32( + ETH_2_2_5G_PHY_ID); + prop_val.mux_val = cpu_to_fdt32( + ETH_2_2_5G_MDIO_MUX); + prop_val.phy_mask = cpu_to_fdt32( + ETH_2_5G_MDIO_PHY_MASK); + prop_val.phy_mode = "2500base-x"; + pfe_set_properties(l_blob, prop_val, ETH_2_PATH, + ETH_2_MDIO); + } + break; + default: + printf("serdes:[%d]\n", srds_s1); + } + } +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + arch_fixup_fdt(blob); + + ft_cpu_setup(blob, bd); + fdt_fsl_fixup_of_pfe(blob); + + return 0; +} +#endif diff --git a/board/nxp/ls1012aqds/ls1012aqds_pfe.h b/board/nxp/ls1012aqds/ls1012aqds_pfe.h new file mode 100644 index 00000000000..5ab283ce8d5 --- /dev/null +++ b/board/nxp/ls1012aqds/ls1012aqds_pfe.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + */ + +#define ETH_1_1G_BUS_ID 0x1 +#define ETH_1_1G_PHY_ID 0x1e +#define ETH_1_1G_MDIO_MUX 0x2 +#define ETH_1G_MDIO_PHY_MASK 0xBFFFFFFD +#define ETH_1_1G_PHY_MODE "sgmii" +#define ETH_2_1G_BUS_ID 0x1 +#define ETH_2_1G_PHY_ID 0x1 +#define ETH_2_1G_MDIO_MUX 0x1 +#define ETH_2_1G_PHY_MODE "rgmii" + +#define ETH_1_2_5G_BUS_ID 0x0 +#define ETH_1_2_5G_PHY_ID 0x1 +#define ETH_1_2_5G_MDIO_MUX 0x2 +#define ETH_2_5G_MDIO_PHY_MASK 0xFFFFFFF9 +#define ETH_2_5G_PHY_MODE "2500base-x" +#define ETH_2_2_5G_BUS_ID 0x1 +#define ETH_2_2_5G_PHY_ID 0x2 +#define ETH_2_2_5G_MDIO_MUX 0x3 + +#define SERDES_1_G_PROTOCOL 0x3508 +#define SERDES_2_5_G_PROTOCOL 0x2205 + +#define PFE_PROP_LEN 4 + +#define ETH_1_PATH "/pfe@04000000/ethernet@0" +#define ETH_1_MDIO ETH_1_PATH "/mdio@0" + +#define ETH_2_PATH "/pfe@04000000/ethernet@1" +#define ETH_2_MDIO ETH_2_PATH "/mdio@0" + +#define NUM_ETH_NODE 2 + +struct pfe_prop_val { + int busid; + int phyid; + int mux_val; + int phy_mask; + char *phy_mode; +}; diff --git a/board/nxp/ls1012aqds/ls1012aqds_qixis.h b/board/nxp/ls1012aqds/ls1012aqds_qixis.h new file mode 100644 index 00000000000..19f522d9eaa --- /dev/null +++ b/board/nxp/ls1012aqds/ls1012aqds_qixis.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + */ + +#ifndef __LS1043AQDS_QIXIS_H__ +#define __LS1043AQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for LS1043AQDS */ + +/* BRDCFG4[4:7] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xe0 +#define BRDCFG4_EMISEL_SHIFT 6 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +/* BRDCFG2 - SD clock*/ +#define QIXIS_SDCLK1_100 0x0 +#define QIXIS_SDCLK1_125 0x1 +#define QIXIS_SDCLK1_165 0x2 +#define QIXIS_SDCLK1_100_SP 0x3 + +#endif diff --git a/board/nxp/ls1012ardb/Kconfig b/board/nxp/ls1012ardb/Kconfig new file mode 100644 index 00000000000..bbe5ce21109 --- /dev/null +++ b/board/nxp/ls1012ardb/Kconfig @@ -0,0 +1,108 @@ +if TARGET_LS1012ARDB + +config SYS_BOARD + default "ls1012ardb" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012ardb" + +if CHAIN_OF_TRUST +config SYS_LS_PFE_ESBC_ADDR + hex "PFE Firmware HDR Addr" + default 0x40640000 + +config SYS_LS_PFE_ESBC_LENGTH + hex "length of PFE Firmware HDR" + default 0xc00 +endif + +if FSL_PFE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select PHYLIB + imply PHY_REALTEK + +config SYS_LS_PFE_FW_ADDR + hex "Flash address of PFE firmware" + default 0x40a00000 + +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x300000 + +config DDR_PFE_PHYS_BASEADDR + hex "PFE DDR physical base address" + default 0x03800000 + +config DDR_PFE_BASEADDR + hex "PFE DDR base address" + default 0x83800000 + +config PFE_EMAC1_PHY_ADDR + hex "PFE DDR base address" + default 0x2 + +config PFE_EMAC2_PHY_ADDR + hex "PFE DDR base address" + default 0x1 + +endif + +endif + +if TARGET_LS1012A2G5RDB + +config SYS_BOARD + default "ls1012ardb" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012a2g5rdb" + +if FSL_PFE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select PHYLIB + imply PHYLIB_10G + imply PHY_AQUANTIA + +config SYS_LS_PFE_FW_ADDR + hex "Flash address of PFE firmware" + default 0x40a00000 + +config SYS_LS_PFE_FW_LENGTH + hex "length of PFE firmware" + default 0x300000 + +config DDR_PFE_PHYS_BASEADDR + hex "PFE DDR physical base address" + default 0x03800000 + +config DDR_PFE_BASEADDR + hex "PFE DDR base address" + default 0x83800000 + +config PFE_EMAC1_PHY_ADDR + hex "PFE DDR base address" + default 0x2 + +config PFE_EMAC2_PHY_ADDR + hex "PFE DDR base address" + default 0x1 + +endif + +endif diff --git a/board/nxp/ls1012ardb/MAINTAINERS b/board/nxp/ls1012ardb/MAINTAINERS new file mode 100644 index 00000000000..5dd2858a86c --- /dev/null +++ b/board/nxp/ls1012ardb/MAINTAINERS @@ -0,0 +1,17 @@ +LS1012ARDB BOARD +M: Pramod Kumar +S: Maintained +F: board/nxp/ls1012ardb/ +F: include/configs/ls1012ardb.h +F: configs/ls1012ardb_qspi_defconfig +F: configs/ls1012ardb_tfa_defconfig +F: configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +F: configs/ls1012a2g5rdb_tfa_defconfig +F: configs/ls1012ardb_qspi_SECURE_BOOT_defconfig + +LS1012A2G5RDB BOARD +M: Pramod Kumar +S: Maintained +F: board/nxp/ls1012ardb/ +F: include/configs/ls1012a2g5rdb.h +F: configs/ls1012a2g5rdb_qspi_defconfig diff --git a/board/nxp/ls1012ardb/Makefile b/board/nxp/ls1012ardb/Makefile new file mode 100644 index 00000000000..70c7b33273d --- /dev/null +++ b/board/nxp/ls1012ardb/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1012ardb.o +obj-$(CONFIG_FSL_PFE) += eth.o diff --git a/board/nxp/ls1012ardb/README b/board/nxp/ls1012ardb/README new file mode 100644 index 00000000000..26b0485a7f8 --- /dev/null +++ b/board/nxp/ls1012ardb/README @@ -0,0 +1,97 @@ +Overview +-------- +QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance +development platform, with a complete debugging environment. +The LS1012ARDB board supports the QorIQ LS1012A processor and is +optimized to support the high-bandwidth DDR3L memory and +a full complement of high-speed SerDes ports. + +LS1012A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A +SoC overview. + +LS1012ARDB board Overview +----------------------- + - SERDES Connections, 4 lanes supporting: + - PCI Express - 3.0 + - SGMII, SGMII 2.5 + - SATA 3.0 + - DDR Controller + - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s + -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select + signals to + - QSPI NOR flash memory (2 virtual banks) + - the QSPI emulator.s + - USB 3.0 + - one high-speed USB 2.0/3.0 port. + - Two enhanced secure digital host controllers: + - SDHC1 controller can be connected to onboard SDHC connector + - SDHC2 controller: Three dual 1:4 mux/demux devices, + 74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC, + SDIO WiFi, SPI, and Ardiuno shield + - 2 I2C controllers + - One SATA onboard connectors + - UART + - The LS1012A processor consists of two UART controllers, + out of which only UART1 is used on RDB. + - ARM JTAG support + +Booting Options +--------------- +a) QSPI Flash Emu Boot +b) QSPI Flash 1 +c) QSPI Flash 2 + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-Boot | 1MB | 0x4010_0000 +U-Boot Env | 1MB | 0x4020_0000 +PPA FIT image | 2MB | 0x4050_0000 +Linux ITB | ~53MB | 0x40A0_0000 + +LS1012A2G5RDB board Overview +----------------------- + - SERDES Connections, 3 lanes supporting: + - SGMII, SGMII 2.5 + - SATA 3.0 + - DDR Controller + - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s + -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select + signals to + - QSPI NOR flash memory + - USB 3.0 + - one high-speed USB 2.0/3.0 port. + - SDIO WiFi, SPI + - 2 I2C controllers + - One SATA onboard connectors + - UART + - The LS1012A processor consists of two UART controllers, + out of which only UART1 is used on 2G5RDB. + - ARM JTAG support + +Major Difference between LS1012ARDB and LS1012A-2G5RDB +------------------------------------------------------ +1. LS1012A-2G5RDB has Type C USB connector unlike USB Type A/B of LS1012ARDB +2. LS1012A-2G5RDB has 2 2.5G AQR PHY unlike 2 1G Realtek RTL8211FS PHYs + of LS1012ARDB +3. LS1012A-2G5RDB is not having Arduino header +4. LS1012A-2G5RDB doesn't have PCI slot + +Booting Options +--------------- +QSPI Flash + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-Boot | 1MB | 0x4010_0000 +U-Boot Env | 1MB | 0x4030_0000 +PPA FIT image | 2MB | 0x4040_0000 +PFE firmware | 20K | 0x00a0_0000 +Linux ITB | ~53MB | 0x4100_0000 diff --git a/board/nxp/ls1012ardb/eth.c b/board/nxp/ls1012ardb/eth.c new file mode 100644 index 00000000000..71cb2988a56 --- /dev/null +++ b/board/nxp/ls1012ardb/eth.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" + +static inline void ls1012ardb_reset_phy(void) +{ +#ifdef CONFIG_TARGET_LS1012ARDB + /* Through reset IO expander reset both RGMII and SGMII PHYs */ +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + int ret; + + /* + * The I2C IO-expander PCAL9555A is mouted on I2C1 bus(bus number is 0). + */ + ret = i2c_get_chip_for_busnum(0, I2C_MUX_IO2_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + 0); + return; + } + /* Config port 0 + * - config pin IOXP_RST_ETH1_B and IOXP_RST_ETH2_B + * are enabled as an output. + */ + dm_i2c_reg_write(dev, 6, __PHY_MASK); + + /* + * Set port 0 output a value to reset ETH2 interface + * - pin IOXP_RST_ETH2_B output 0b0 + */ + dm_i2c_reg_write(dev, 2, __PHY_ETH2_MASK); + mdelay(10); + dm_i2c_reg_write(dev, 2, __PHY_ETH1_MASK); + /* + * Set port 0 output a value to reset ETH1 interface + * - pin IOXP_RST_ETH1_B output 0b0 + */ + mdelay(10); + dm_i2c_reg_write(dev, 2, 0xFF); +#else + i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK); + i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK); + mdelay(10); + i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK); + mdelay(10); + i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF); +#endif + mdelay(50); +#endif +} + +int pfe_eth_board_init(struct udevice *dev) +{ + static int init_done; + struct mii_dev *bus; + struct pfe_mdio_info mac_mdio_info; + struct pfe_eth_dev *priv = dev_get_priv(dev); + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; + + int srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + if (!init_done) { + ls1012ardb_reset_phy(); + mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; + mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME; + + bus = pfe_mdio_init(&mac_mdio_info); + if (!bus) { + printf("Failed to register mdio\n"); + return -1; + } + init_done = 1; + } + + pfe_set_mdio(priv->gemac_port, + miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); + + switch (srds_s1) { + case 0x3508: + if (!priv->gemac_port) { + /* MAC1 */ + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC1_PHY_ADDR, + PHY_INTERFACE_MODE_SGMII); + } else { + /* MAC2 */ + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC2_PHY_ADDR, + PHY_INTERFACE_MODE_RGMII_ID); + } + break; + case 0x2208: + if (!priv->gemac_port) { + /* MAC1 */ + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC1_PHY_ADDR, + PHY_INTERFACE_MODE_2500BASEX); + } else { + /* MAC2 */ + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC2_PHY_ADDR, + PHY_INTERFACE_MODE_2500BASEX); + } + break; + default: + printf("unsupported SerDes PRCTL= %d\n", srds_s1); + break; + } + return 0; +} + +static struct pfe_eth_pdata pfe_pdata0 = { + .pfe_eth_pdata_mac = { + .iobase = (phys_addr_t)EMAC1_BASE_ADDR, + .phy_interface = 0, + }, + + .pfe_ddr_addr = { + .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, + .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, + }, +}; + +static struct pfe_eth_pdata pfe_pdata1 = { + .pfe_eth_pdata_mac = { + .iobase = (phys_addr_t)EMAC2_BASE_ADDR, + .phy_interface = 1, + }, + + .pfe_ddr_addr = { + .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR, + .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR, + }, +}; + +U_BOOT_DRVINFO(ls1012a_pfe0) = { + .name = "pfe_eth", + .plat = &pfe_pdata0, +}; + +U_BOOT_DRVINFO(ls1012a_pfe1) = { + .name = "pfe_eth", + .plat = &pfe_pdata1, +}; diff --git a/board/nxp/ls1012ardb/ls1012ardb.c b/board/nxp/ls1012ardb/ls1012ardb.c new file mode 100644 index 00000000000..ab69eab8408 --- /dev/null +++ b/board/nxp/ls1012ardb/ls1012ardb.c @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define BOOT_FROM_UPPER_BANK 0x2 +#define BOOT_FROM_LOWER_BANK 0x1 + +int checkboard(void) +{ +#ifdef CONFIG_TARGET_LS1012ARDB + u8 in1; + int ret, bus_num = 0; + + puts("Board: LS1012ARDB "); + + /* Initialize i2c early for Serial flash bank information */ +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return -ENXIO; + } + ret = dm_i2c_read(dev, I2C_MUX_IO_1, &in1, 1); +#else /* Non DM I2C support - will be removed */ + i2c_set_bus_num(bus_num); + ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1); +#endif + if (ret < 0) { + printf("Error reading i2c boot information!\n"); + return 0; /* Don't want to hang() on this error */ + } + + puts("Version"); + switch (in1 & SW_REV_MASK) { + case SW_REV_A: + puts(": RevA"); + break; + case SW_REV_B: + puts(": RevB"); + break; + case SW_REV_C: + puts(": RevC"); + break; + case SW_REV_C1: + puts(": RevC1"); + break; + case SW_REV_C2: + puts(": RevC2"); + break; + case SW_REV_D: + puts(": RevD"); + break; + case SW_REV_E: + puts(": RevE"); + break; + default: + puts(": unknown"); + break; + } + + printf(", boot from QSPI"); + if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU) + puts(": emu\n"); + else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1) + puts(": bank1\n"); + else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2) + puts(": bank2\n"); + else + puts("unknown\n"); +#else + + puts("Board: LS1012A2G5RDB "); +#endif + return 0; +} + +#ifdef CONFIG_TFABOOT +int dram_init(void) +{ + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) + gd->ram_size = CFG_SYS_SDRAM_SIZE; + + return 0; +} +#else +int dram_init(void) +{ +#ifndef CONFIG_TFABOOT + static const struct fsl_mmdc_info mparam = { + 0x05180000, /* mdctl */ + 0x00030035, /* mdpdc */ + 0x12554000, /* mdotc */ + 0xbabf7954, /* mdcfg0 */ + 0xdb328f64, /* mdcfg1 */ + 0x01ff00db, /* mdcfg2 */ + 0x00001680, /* mdmisc */ + 0x0f3c8000, /* mdref */ + 0x00002000, /* mdrwd */ + 0x00bf1023, /* mdor */ + 0x0000003f, /* mdasp */ + 0x0000022a, /* mpodtctrl */ + 0xa1390003, /* mpzqhwctrl */ + }; + + mmdc_init(&mparam); +#endif + + gd->ram_size = CFG_SYS_SDRAM_SIZE; +#if !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif + + return 0; +} +#endif + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + + CONFIG_SYS_CCI400_OFFSET); + /* + * Set CCI-400 control override register to enable barrier + * transaction + */ + if (current_el() == 3) + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + + return 0; +} + +#ifdef CONFIG_FSL_PFE +void board_quiesce_devices(void) +{ + pfe_command_stop(0, NULL); +} +#endif + +#ifdef CONFIG_TARGET_LS1012ARDB +int esdhc_status_fixup(void *blob, const char *compat) +{ + char esdhc1_path[] = "/soc/esdhc@1580000"; + bool sdhc2_en = false; + u8 mux_sdhc2; + u8 io = 0; + int ret, bus_num = 0; + +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return -ENXIO; + } + ret = dm_i2c_read(dev, I2C_MUX_IO_1, &io, 1); +#else + i2c_set_bus_num(bus_num); + /* IO1[7:3] is the field of board revision info. */ + ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1); +#endif + if (ret < 0) { + printf("Error reading i2c boot information!\n"); + return 0; + } + + /* hwconfig method is used for RevD and later versions. */ + if ((io & SW_REV_MASK) <= SW_REV_D) { +#ifdef CONFIG_HWCONFIG + if (hwconfig("esdhc1")) + sdhc2_en = true; +#endif + } else { + /* + * The I2C IO-expander for mux select is used to control + * the muxing of various onboard interfaces. + * + * IO0[3:2] indicates SDHC2 interface demultiplexer + * select lines. + * 00 - SDIO wifi + * 01 - GPIO (to Arduino) + * 10 - eMMC Memory + * 11 - SPI + */ +#if CONFIG_IS_ENABLED(DM_I2C) + ret = dm_i2c_read(dev, I2C_MUX_IO_0, &io, 1); +#else + ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1); +#endif + if (ret < 0) { + printf("Error reading i2c boot information!\n"); + return 0; + } + + mux_sdhc2 = (io & 0x0c) >> 2; + /* Enable SDHC2 only when use SDIO wifi and eMMC */ + if (mux_sdhc2 == 2 || mux_sdhc2 == 0) + sdhc2_en = true; + } + if (sdhc2_en) + do_fixup_by_path(blob, esdhc1_path, "status", "okay", + sizeof("okay"), 1); + else + do_fixup_by_path(blob, esdhc1_path, "status", "disabled", + sizeof("disabled"), 1); + return 0; +} +#endif + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + arch_fixup_fdt(blob); + + ft_cpu_setup(blob, bd); + + return 0; +} + +static int switch_to_bank1(void) +{ + u8 data = 0xf4, chip_addr = 0x24, offset_addr = 0x03; + int ret, bus_num = 0; + +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, chip_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return -ENXIO; + } + /* + * -------------------------------------------------------------------- + * |bus |I2C address| Device | Notes | + * -------------------------------------------------------------------- + * |I2C1|0x24, 0x25,| IO expander (CFG,| Provides 16bits of General | + * | |0x26 | RESET, and INT/ | Purpose parallel Input/Output| + * | | | KW41GPIO) - NXP | (GPIO) expansion for the | + * | | | PCAL9555AHF | I2C bus | + * ----- -------------------------------------------------------------- + * - mount three IO expander(PCAL9555AHF) on I2C1 + * + * PCAL9555A device address + * slave address + * -------------------------------------- + * | 0 | 1 | 0 | 0 | A2 | A1 | A0 | R/W | + * -------------------------------------- + * | fixed | hardware selectable| + * + * Output port 1(Pinter register bits = 0x03) + * + * P1_[7~0] = 0xf4 + * P1_0 <---> CFG_MUX_QSPI_S0 + * P1_1 <---> CFG_MUX_QSPI_S1 + * CFG_MUX_QSPI_S[1:0] = 0b00 + * + * QSPI chip-select demultiplexer select + * --------------------------------------------------------------------- + * CFG_MUX_QSPI_S1|CFG_MUX_QSPI_S0| Values + * --------------------------------------------------------------------- + * 0 | 0 |CS routed to SPI memory bank1(default) + * --------------------------------------------------------------------- + * 0 | 1 |CS routed to SPI memory bank2 + * --------------------------------------------------------------------- + * + */ + ret = dm_i2c_write(dev, offset_addr, &data, 1); +#else /* Non DM I2C support - will be removed */ + i2c_set_bus_num(bus_num); + ret = i2c_write(chip_addr, offset_addr, 1, &data, 1); +#endif + + if (ret) { + printf("i2c write error to chip : %u, addr : %u, data : %u\n", + chip_addr, offset_addr, data); + } + + return ret; +} + +static int switch_to_bank2(void) +{ + u8 data[2] = {0xfc, 0xf5}, offset_addr[2] = {0x7, 0x3}; + u8 chip_addr = 0x24; + int ret, i, bus_num = 0; + +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, chip_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return -ENXIO; + } +#else /* Non DM I2C support - will be removed */ + i2c_set_bus_num(bus_num); +#endif + + /* + * 1th step: config port 1 + * - the port 1 pin is enabled as an output + * 2th step: output port 1 + * - P1_[7:0] output 0xf5, + * then CFG_MUX_QSPI_S[1:0] equal to 0b01, + * CS routed to SPI memory bank2 + */ + for (i = 0; i < sizeof(data); i++) { +#if CONFIG_IS_ENABLED(DM_I2C) + ret = dm_i2c_write(dev, offset_addr[i], &data[i], 1); +#else /* Non DM I2C support - will be removed */ + ret = i2c_write(chip_addr, offset_addr[i], 1, &data[i], 1); +#endif + if (ret) { + printf("i2c write error to chip : %u, addr : %u, data : %u\n", + chip_addr, offset_addr[i], data[i]); + goto err; + } + } + +err: + return ret; +} + +static int convert_flash_bank(int bank) +{ + int ret = 0; + + switch (bank) { + case BOOT_FROM_UPPER_BANK: + ret = switch_to_bank2(); + break; + case BOOT_FROM_LOWER_BANK: + ret = switch_to_bank1(); + break; + default: + ret = CMD_RET_USAGE; + break; + }; + + return ret; +} + +static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + if (strcmp(argv[1], "1") == 0) + convert_flash_bank(BOOT_FROM_LOWER_BANK); + else if (strcmp(argv[1], "2") == 0) + convert_flash_bank(BOOT_FROM_UPPER_BANK); + else + return CMD_RET_USAGE; + + return 0; +} + +U_BOOT_CMD( + boot_bank, 2, 0, flash_bank_cmd, + "Flash bank Selection Control", + "bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)" +); diff --git a/board/nxp/ls1021aiot/Kconfig b/board/nxp/ls1021aiot/Kconfig new file mode 100644 index 00000000000..52e6e73f3b6 --- /dev/null +++ b/board/nxp/ls1021aiot/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1021AIOT + +config SYS_BOARD + default "ls1021aiot" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "ls102xa" + +config SYS_CONFIG_NAME + default "ls1021aiot" + +endif diff --git a/board/nxp/ls1021aiot/MAINTAINERS b/board/nxp/ls1021aiot/MAINTAINERS new file mode 100644 index 00000000000..db7a90b07e9 --- /dev/null +++ b/board/nxp/ls1021aiot/MAINTAINERS @@ -0,0 +1,7 @@ +LS1021AIOT BOARD +M: Alison Wang +S: Maintained +F: board/nxp/ls1021aiot/ +F: include/configs/ls1021aiot.h +F: configs/ls1021aiot_sdcard_defconfig +F: configs/ls1021aiot_qspi_defconfig diff --git a/board/nxp/ls1021aiot/Makefile b/board/nxp/ls1021aiot/Makefile new file mode 100644 index 00000000000..587bbd79ddf --- /dev/null +++ b/board/nxp/ls1021aiot/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2016 Freescale Semiconductor, Inc. + +obj-y += ls1021aiot.o +obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/nxp/ls1021aiot/README b/board/nxp/ls1021aiot/README new file mode 100644 index 00000000000..08b0268b9bd --- /dev/null +++ b/board/nxp/ls1021aiot/README @@ -0,0 +1,58 @@ +Overview +-------- +The LS1021A-IOT is a Freescale reference board that hosts +the LS1021A SoC. + +LS1021AIOT board Overview +------------------------- + - DDR Controller + - Supports 1GB un-buffered DDR3L SDRAM discrete + devices(32-bit bus) with 4 bit ECC + - DDR power supplies 1.35V to all devices with + automatic tracking of VTT + - Soldered DDR chip + - Supprot one fixed speed + - Ethernet + - Two on-board SGMII 10/100/1G ethernet ports + - One Gbit Etherent RGMII interface to 4-ports switch + with 4x 10/100/1000 RJ145 ports + - CPLD + - 8-bit registers in CPLD for system configuration + - connected to IFC_AD[0:7] + - Power Supplies + - 12V@5A DC + - SDHC + - SDHC port connects directly to a full 8-bit SD/MMC slot + - Support for SDIO devices + - USB + - Two on-board USB 3.0 + - One on-board USB k22 + - PCIe + - Two MiniPCIe Solts + - SATA + - Support SATA Connector + - AUDIO + - AUDIO in and out + - I/O Expansion + - Arduino Shield Connector + - Port0 - CAN/GPIO/Flextimer + - Port1 - GPIO/CPLD Expansion + - Port2 - SPI/I2C/UART + +Memory map +----------- +The addresses in brackets are physical addresses. + +Start Address End Address Description Size +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_4000_0000 0x00_43FF_FFFF QSPI(Chip select 0) 64MB +0x00_4400_0000 0x00_47FF_FFFF QSPI(Chip select 1) 64MB +0x00_6000_0000 0x00_6000_FFFF CPLD 64K +0x00_8000_0000 0x00_BFFF_FFFF DDR 1GB + +Boot description +----------------- +LS1021A-IOT support two ways of boot: +Qspi boot and SD boot +The board doesn't support boot from another +source without changing any switch/jumper. diff --git a/board/nxp/ls1021aiot/ls1021aiot.c b/board/nxp/ls1021aiot/ls1021aiot.c new file mode 100644 index 00000000000..52a3c3abdb4 --- /dev/null +++ b/board/nxp/ls1021aiot/ls1021aiot.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "../common/sleep.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define DDR_SIZE 0x40000000 + +int checkboard(void) +{ + puts("Board: LS1021AIOT\n"); + +#ifndef CONFIG_QSPI_BOOT + struct ccsr_gur *dcfg = (struct ccsr_gur *)CFG_SYS_FSL_GUTS_ADDR; + u32 cpldrev; + + cpldrev = in_be32(&dcfg->gpporcr1); + + printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) & + 0xf)); +#endif + return 0; +} + +void ddrmc_init(void) +{ + struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR; + u32 temp_sdram_cfg, tmp; + + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); + + out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); + out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); + + out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); + out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); + out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); + out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); + out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); + out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); + + out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); + out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); + + out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); + out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); + + out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); + + out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); + + out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); + out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); + + out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); + + out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); + out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); + + out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); + + /* DDR erratum A-009942 */ + tmp = in_be32(&ddr->debug[28]); + out_be32(&ddr->debug[28], tmp | 0x0070006f); + + udelay(500); + + temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); + + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); +} + +int dram_init(void) +{ +#if (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)) + ddrmc_init(); +#endif + + erratum_a008850_post(); + + gd->ram_size = DDR_SIZE; + return 0; +} + +int board_early_init_f(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; + +#ifdef CONFIG_TSEC_ENET + /* clear BD & FR bits for BE BD's and frame data */ + clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); + +#endif + +#ifdef CONFIG_FSL_IFC + init_early_memctl_regs(); +#endif + + arch_soc_init(); + + return 0; +} + +#ifdef CONFIG_XPL_BUILD +void board_init_f(ulong dummy) +{ + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + get_clocks(); + + preloader_console_init(); + + dram_init(); + + /* Allow OCRAM access permission as R/W */ + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + + board_init_r(NULL, 0); +} +#endif + +int board_init(void) +{ +#ifndef CONFIG_SYS_FSL_NO_SERDES + fsl_serdes_init(); +#endif + + ls102xa_smmu_stream_id_init(); + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + return 0; +} +#endif + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ +#ifdef CONFIG_FSL_DEVICE_DISABLE + device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); + +#endif + return 0; +} +#endif + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + + return 0; +} + +void flash_write16(u16 val, void *addr) +{ + u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); + + __raw_writew(shftval, addr); +} + +u16 flash_read16(void *addr) +{ + u16 val = __raw_readw(addr); + + return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); +} diff --git a/board/nxp/ls1021aiot/ls102xa_pbi.cfg b/board/nxp/ls1021aiot/ls102xa_pbi.cfg new file mode 100644 index 00000000000..b5ac5e27e9d --- /dev/null +++ b/board/nxp/ls1021aiot/ls102xa_pbi.cfg @@ -0,0 +1,14 @@ +#PBI commands + +09570200 ffffffff +09570158 00000300 +8940007c 21f47300 + +#Configure Scratch register +09ee0200 10000000 +#Configure alternate space +09570158 00001000 +#Flush PBL data +096100c0 000FFFFF + +09ea085c 00502880 diff --git a/board/nxp/ls1021aiot/ls102xa_rcw_sd.cfg b/board/nxp/ls1021aiot/ls102xa_rcw_sd.cfg new file mode 100644 index 00000000000..a1984c713d5 --- /dev/null +++ b/board/nxp/ls1021aiot/ls102xa_rcw_sd.cfg @@ -0,0 +1,27 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# serdes protocol + +#Default with 2 x SGMII (no SATA) +0608000a 00000000 00000000 00000000 +20000000 08407900 60025a00 21046000 +00000000 00000000 00000000 20038000 +20024800 881b1340 00000000 00000000 + +#SATA set-up +#0608000a 00000000 00000000 00000000 +#70000000 08007900 60025a00 21046000 +#00000000 00000000 00000000 20038000 +#20024800 881b1340 00000000 00000000 + +#HDMI set-up +#0608000a 00000000 00000000 00000000 +#20000000 08407900 60025a00 21046000 +#00000000 00000000 00000000 20038000 +#00000000 881b1340 00000000 00000000 + +#QE testing +#0608000a 00000000 00000000 00000000 +#20000000 08407900 60025a00 21046000 +#00000000 00000000 00000000 00038000 +#20094800 881b1340 00000000 00000000 diff --git a/board/nxp/ls1021aiot/psci.S b/board/nxp/ls1021aiot/psci.S new file mode 100644 index 00000000000..d0106ba3905 --- /dev/null +++ b/board/nxp/ls1021aiot/psci.S @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 NXP Semiconductor. + * Author: Feng Li + */ + +#include +#include + +#include +#include + + .pushsection ._secure.text, "ax" + + .arch_extension sec + + .align 5 + +.globl psci_system_off +psci_system_off: +1: wfi + b 1b + +.globl psci_text_end +psci_text_end: + nop + .popsection diff --git a/board/nxp/ls1021aqds/Kconfig b/board/nxp/ls1021aqds/Kconfig new file mode 100644 index 00000000000..e14140aee33 --- /dev/null +++ b/board/nxp/ls1021aqds/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1021AQDS + +config SYS_BOARD + default "ls1021aqds" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "ls102xa" + +config SYS_CONFIG_NAME + default "ls1021aqds" + +endif diff --git a/board/nxp/ls1021aqds/MAINTAINERS b/board/nxp/ls1021aqds/MAINTAINERS new file mode 100644 index 00000000000..4575dbd0ef2 --- /dev/null +++ b/board/nxp/ls1021aqds/MAINTAINERS @@ -0,0 +1,14 @@ +LS1021AQDS BOARD +M: Alison Wang +S: Maintained +F: board/nxp/ls1021aqds/ +F: include/configs/ls1021aqds.h +F: configs/ls1021aqds_nor_defconfig +F: configs/ls1021aqds_ddr4_nor_defconfig +F: configs/ls1021aqds_ddr4_nor_lpuart_defconfig +F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig +F: configs/ls1021aqds_nor_lpuart_defconfig +F: configs/ls1021aqds_sdcard_ifc_defconfig +F: configs/ls1021aqds_sdcard_qspi_defconfig +F: configs/ls1021aqds_qspi_defconfig +F: configs/ls1021aqds_nand_defconfig diff --git a/board/nxp/ls1021aqds/Makefile b/board/nxp/ls1021aqds/Makefile new file mode 100644 index 00000000000..8cbf33fa0ce --- /dev/null +++ b/board/nxp/ls1021aqds/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021aqds.o +obj-y += ddr.o +obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/nxp/ls1021aqds/README b/board/nxp/ls1021aqds/README new file mode 100644 index 00000000000..e2ce00165bd --- /dev/null +++ b/board/nxp/ls1021aqds/README @@ -0,0 +1,117 @@ +Overview +-------- +The LS1021AQDS is a Freescale reference board that hosts the LS1021A SoC. + +LS1021A SoC Overview +------------------ +The QorIQ LS1 family, which includes the LS1021A communications processor, +is built on Layerscape architecture, the industry's first software-aware, +core-agnostic networking architecture to offer unprecedented efficiency +and scale. + +A member of the value-performance tier, the QorIQ LS1021A processor provides +extensive integration and power efficiency for fanless, small form factor +enterprise networking applications. Incorporating dual ARM Cortex-A7 cores +running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark +performance of over 6,000, as well as virtualization support, advanced +security features and the broadest array of high-speed interconnects and +optimized peripheral features ever offered in a sub-3 W processor. + +The QorIQ LS1021A processor features an integrated LCD controller, +CAN controller for implementing industrial protocols, DDR3L/4 running +up to 1600 MHz, integrated security engine and QUICC Engine, and ECC +protection on both L1 and L2 caches. The LS1021A processor is pin- and +software-compatible with the QorIQ LS1020A and LS1022A processors. + +The LS1021A SoC includes the following function and features: + + - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture + - Dual high-preformance ARM Cortex-A7 cores, each core includes: + - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection) + - 512 Kbyte shared coherent L2 Cache (with ECC protection) + - NEON Co-processor (per core) + - 40-bit physical addressing + - Vector floating-point support + - ARM Core-Link CCI-400 Cache Coherent Interconnect + - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration + supporting speeds up to 1600Mtps + - ECC and interleaving support + - VeTSEC Ethernet complex + - Up to 3x virtualized 10/100/1000 Ethernet controllers + - MII, RMII, RGMII, and SGMII support + - QoS, lossless flow control, and IEEE 1588 support + - 4-lane 6GHz SerDes + - High speed interconnect (4 SerDes lanes with are muxed for these protocol) + - Two PCI Express Gen2 controllers running at up to 5 GHz + - One Serial ATA 3.0 supporting 6 GT/s operation + - Two SGMII interfaces supporting 1000 Mbps + - Additional peripheral interfaces + - One high-speed USB 3.0 controller with integrated PHY and one high-speed + USB 2.00 controller with ULPI + - Integrated flash controller (IFC) with 16-bit interface + - Quad SPI NOR Flash + - One enhanced Secure digital host controller + - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface) + - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power + UARTs + - Three I2C controllers + - Eight FlexTimers four supporting PWM and four FlexCAN ports + - Four GPIO controllers supporting up to 109 general purpose I/O signals + - Integrated advanced audio block: + - Four synchronous audio interfaces (SAI) + - Sony/Philips Digital Interconnect Format (SPDIF) + - Asynchronous Sample Rate Converter (ASRC) + - Hardware based crypto offload engine + - IPSec forwarding at up to 1Gbps + - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported + - Public key hardware accelerator + - True Random Number Generator (NIST Certified) + - Advanced Encryption Standard Accelerators (AESA) + - Data Encryption Standard Accelerators + - QUICC Engine ULite block + - Two universal communication controllers (TDM and HDLC) supporting 64 + multichannels, each running at 64 Kbps + - Support for 256 channels of HDLC + - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported + +LS1021AQDS board Overview +------------------------- + - DDR Controller + - Supports rates of up to 1600 MHz data-rate + - Supports one DDR3LP UDIMM, of single-, dual- types. + - IFC/Local Bus + - NAND flash: 512M 8-bit NAND flash + - NOR: 128MB 16-bit NOR Flash + - Ethernet + - Three on-board RGMII 10/100/1G ethernet ports. + - FPGA + - Clocks + - System and DDR clock (SYSCLK, DDRCLK) + - SERDES clocks + - Power Supplies + - SDHC + - SDHC/SDXC connector + - Other IO + - Two Serial ports + - Three I2C ports + +Memory map +----------- +The addresses in brackets are physical addresses. + +Start Address End Address Description Size +0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB +0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB +0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB +0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB +0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB +0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB + +LS1021a rev1.0 Soc specific Options/Settings +-------------------------------------------- +If the LS1021a Soc is rev1.0, you need modify the configuration and enable +CONFIG_SPL_SKIP_LOWLEVEL_INIT in menuconfig or similar. diff --git a/board/nxp/ls1021aqds/ddr.c b/board/nxp/ls1021aqds/ddr.c new file mode 100644 index 00000000000..fd897e832c8 --- /dev/null +++ b/board/nxp/ls1021aqds/ddr.c @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 3) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->cpo_override = pbsp->cpo_override; + popts->write_data_delay = + pbsp->write_data_delay; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + + /* force DDR bus width to 32 bits */ + popts->data_bus_width = 1; + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 1; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else + popts->cswl_override = DDR_CSWL_CS0; + + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x58; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif +} + +#ifdef CONFIG_SYS_DDR_RAW_TIMING +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 1071, + .caslat_x = 0xfe << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 7800000, + .tfaw_ps = 37500, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + static const char dimm_model[] = "Fixed DDR on board"; + + if (((controller_number == 0) && (dimm_number == 0)) || + ((controller_number == 1) && (dimm_number == 0))) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} +#endif + +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void) +{ + void __iomem *qixis_base = (void *)QIXIS_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(qixis_base + 0x21, 0x2); + udelay(1); +} +#endif + +int fsl_initdram(void) +{ + phys_size_t dram_size; + +#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_SPL) + puts("Initializing DDR....using SPD\n"); + dram_size = fsl_ddr_sdram(); +#else + dram_size = fsl_ddr_sdram_size(); +#endif + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD) + fsl_dp_resume(); +#endif + + erratum_a008850_post(); + + gd->ram_size = dram_size; + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} diff --git a/board/nxp/ls1021aqds/ddr.h b/board/nxp/ls1021aqds/ddr.h new file mode 100644 index 00000000000..58a88384367 --- /dev/null +++ b/board/nxp/ls1021aqds/ddr.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __DDR_H__ +#define __DDR_H__ + +void erratum_a008850_post(void); + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; + u32 cpo_override; + u32 write_data_delay; + u32 force_2t; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ +#ifdef CONFIG_SYS_FSL_DDR4 + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 8, 8, 0x090A0B0B, 0x0C0D0E0C,}, + {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, + {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,}, +#elif defined(CONFIG_SYS_FSL_DDR3) + {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, +#else +#error DDR type not defined +#endif + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +#endif diff --git a/board/nxp/ls1021aqds/ls1021aqds.c b/board/nxp/ls1021aqds/ls1021aqds.c new file mode 100644 index 00000000000..0bdd468d9a7 --- /dev/null +++ b/board/nxp/ls1021aqds/ls1021aqds.c @@ -0,0 +1,456 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2019, 2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/i2c_mux.h" +#include "../common/sleep.h" +#include "../common/qixis.h" +#include "ls1021aqds_qixis.h" +#ifdef CONFIG_U_QE +#include +#endif + +#define PIN_MUX_SEL_CAN 0x03 +#define PIN_MUX_SEL_IIC2 0xa0 +#define PIN_MUX_SEL_RGMII 0x00 +#define PIN_MUX_SEL_SAI 0x0c +#define PIN_MUX_SEL_SDHC 0x00 + +#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value) +#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value) +enum { + MUX_TYPE_CAN, + MUX_TYPE_IIC2, + MUX_TYPE_RGMII, + MUX_TYPE_SAI, + MUX_TYPE_SDHC, + MUX_TYPE_SD_PCI4, + MUX_TYPE_SD_PC_SA_SG_SG, + MUX_TYPE_SD_PC_SA_PC_SG, + MUX_TYPE_SD_PC_SG_SG, +}; + +enum { + GE0_CLK125, + GE2_CLK125, + GE1_CLK125, +}; + +int checkboard(void) +{ +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) + char buf[64]; +#endif +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) + u8 sw; +#endif + + puts("Board: LS1021AQDS\n"); + +#ifdef CONFIG_SD_BOOT + puts("SD\n"); +#elif CONFIG_QSPI_BOOT + puts("QSPI\n"); +#else + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("PromJet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else if (sw == 0x15) + printf("IFCCard\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); +#endif + +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) + printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", + QIXIS_READ(id), QIXIS_READ(arch)); + + printf("FPGA: v%d (%s), build %d\n", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); +#endif + + return 0; +} + +#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0f) { + case QIXIS_SYSCLK_64: + return 64000000; + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} +#endif + +#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} +#endif + +int dram_init(void) +{ + /* + * When resuming from deep sleep, the I2C channel may not be + * in the default channel. So, switch to the default channel + * before accessing DDR SPD. + * + * PCA9547(0x77) mount on I2C1 bus + */ + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); + return fsl_initdram(); +} + +int board_early_init_f(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; + +#ifdef CONFIG_TSEC_ENET + /* clear BD & FR bits for BE BD's and frame data */ + clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); +#endif + +#ifdef CONFIG_FSL_IFC + init_early_memctl_regs(); +#endif + + arch_soc_init(); + +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + return 0; +} + +#ifdef CONFIG_XPL_BUILD +void board_init_f(ulong dummy) +{ +#ifdef CONFIG_NAND_BOOT + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; + u32 porsr1, pinctl; + + /* + * There is LS1 SoC issue where NOR, FPGA are inaccessible during + * NAND boot because IFC signals > IFC_AD7 are not enabled. + * This workaround changes RCW source to make all signals enabled. + */ + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | + DCFG_CCSR_PORSR1_RCW_SRC_I2C); + out_be32((unsigned int *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), + pinctl); +#endif + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + +#ifdef CONFIG_FSL_IFC + init_early_memctl_regs(); +#endif + + get_clocks(); + +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + preloader_console_init(); + +#ifdef CONFIG_SPL_I2C + i2c_init_all(); +#endif + + timer_init(); + dram_init(); + + /* Allow OCRAM access permission as R/W */ +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + + board_init_r(NULL, 0); +} +#endif + +void config_etseccm_source(int etsec_gtx_125_mux) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; + + switch (etsec_gtx_125_mux) { + case GE0_CLK125: + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125); + debug("etseccm set to GE0_CLK125\n"); + break; + + case GE2_CLK125: + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); + debug("etseccm set to GE2_CLK125\n"); + break; + + case GE1_CLK125: + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125); + debug("etseccm set to GE1_CLK125\n"); + break; + + default: + printf("Error! trying to set etseccm to invalid value\n"); + break; + } +} + +int config_board_mux(int ctrl_type) +{ + u8 reg12, reg14; + + reg12 = QIXIS_READ(brdcfg[12]); + reg14 = QIXIS_READ(brdcfg[14]); + + switch (ctrl_type) { + case MUX_TYPE_CAN: + config_etseccm_source(GE2_CLK125); + reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN); + break; + case MUX_TYPE_IIC2: + reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2); + break; + case MUX_TYPE_RGMII: + reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII); + break; + case MUX_TYPE_SAI: + config_etseccm_source(GE2_CLK125); + reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI); + break; + case MUX_TYPE_SDHC: + reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC); + break; + case MUX_TYPE_SD_PCI4: + reg12 = 0x38; + break; + case MUX_TYPE_SD_PC_SA_SG_SG: + reg12 = 0x01; + break; + case MUX_TYPE_SD_PC_SA_PC_SG: + reg12 = 0x01; + break; + case MUX_TYPE_SD_PC_SG_SG: + reg12 = 0x21; + break; + default: + printf("Wrong mux interface type\n"); + return -1; + } + + QIXIS_WRITE(brdcfg[12], reg12); + QIXIS_WRITE(brdcfg[14], reg14); + + return 0; +} + +int config_serdes_mux(void) +{ + struct ccsr_gur *gur = (struct ccsr_gur *)CFG_SYS_FSL_GUTS_ADDR; + u32 cfg; + + cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; + cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; + + switch (cfg) { + case 0x0: + config_board_mux(MUX_TYPE_SD_PCI4); + break; + case 0x30: + config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG); + break; + case 0x60: + config_board_mux(MUX_TYPE_SD_PC_SG_SG); + break; + case 0x70: + config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG); + break; + default: + printf("SRDS1 prtcl:0x%x\n", cfg); + break; + } + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_CHAIN_OF_TRUST + fsl_setenv_chain_of_trust(); +#endif + + return 0; +} +#endif + +int misc_init_r(void) +{ + int conflict_flag; + + /* some signals can not enable simultaneous*/ + conflict_flag = 0; + if (hwconfig("sdhc")) + conflict_flag++; + if (hwconfig("iic2")) + conflict_flag++; + if (conflict_flag > 1) { + printf("WARNING: pin conflict !\n"); + return 0; + } + + conflict_flag = 0; + if (hwconfig("rgmii")) + conflict_flag++; + if (hwconfig("can")) + conflict_flag++; + if (hwconfig("sai")) + conflict_flag++; + if (conflict_flag > 1) { + printf("WARNING: pin conflict !\n"); + return 0; + } + + if (hwconfig("can")) + config_board_mux(MUX_TYPE_CAN); + else if (hwconfig("rgmii")) + config_board_mux(MUX_TYPE_RGMII); + else if (hwconfig("sai")) + config_board_mux(MUX_TYPE_SAI); + + if (hwconfig("iic2")) + config_board_mux(MUX_TYPE_IIC2); + else if (hwconfig("sdhc")) + config_board_mux(MUX_TYPE_SDHC); + +#ifdef CONFIG_FSL_DEVICE_DISABLE + device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); +#endif + return 0; +} + +int board_init(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + erratum_a009942_check_cpo(); +#endif + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); + +#ifndef CONFIG_SYS_FSL_NO_SERDES + fsl_serdes_init(); + config_serdes_mux(); +#endif + + ls102xa_smmu_stream_id_init(); + +#ifdef CONFIG_U_QE + u_qe_init(); +#endif + + return 0; +} + +#if defined(CONFIG_DEEP_SLEEP) +void board_sleep_prepare(void) +{ +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif +} +#endif + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + + return 0; +} + +u8 flash_read8(void *addr) +{ + return __raw_readb(addr + 1); +} + +void flash_write16(u16 val, void *addr) +{ + u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); + + __raw_writew(shftval, addr); +} + +u16 flash_read16(void *addr) +{ + u16 val = __raw_readw(addr); + + return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); +} diff --git a/board/nxp/ls1021aqds/ls1021aqds_qixis.h b/board/nxp/ls1021aqds/ls1021aqds_qixis.h new file mode 100644 index 00000000000..7ad08a54ea6 --- /dev/null +++ b/board/nxp/ls1021aqds/ls1021aqds_qixis.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __LS1021AQDS_QIXIS_H__ +#define __LS1021AQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for LS1021AQDS */ + +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xe0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 +#define QIXIS_SYSCLK_64 0x8 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +#define QIXIS_SRDS1CLK_100 0x0 + +#define QIXIS_DCU_BRDCFG5 0x55 + +#endif diff --git a/board/nxp/ls1021aqds/ls102xa_pbi.cfg b/board/nxp/ls1021aqds/ls102xa_pbi.cfg new file mode 100644 index 00000000000..f1a1b63ab77 --- /dev/null +++ b/board/nxp/ls1021aqds/ls102xa_pbi.cfg @@ -0,0 +1,12 @@ +#PBI commands + +09570200 ffffffff +09570158 00000300 +8940007c 21f47300 + +#Configure Scratch register +09ee0200 10000000 +#Configure alternate space +09570158 00001000 +#Flush PBL data +096100c0 000FFFFF diff --git a/board/nxp/ls1021aqds/ls102xa_rcw_nand.cfg b/board/nxp/ls1021aqds/ls102xa_rcw_nand.cfg new file mode 100644 index 00000000000..d76e9132e35 --- /dev/null +++ b/board/nxp/ls1021aqds/ls102xa_rcw_nand.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# serdes protocol +0608000c 00000000 00000000 00000000 +60000000 00407900 e0106a00 21046000 +00000000 00000000 00000000 00038000 +00000000 001b7200 00000000 00000000 diff --git a/board/nxp/ls1021aqds/ls102xa_rcw_sd_ifc.cfg b/board/nxp/ls1021aqds/ls102xa_rcw_sd_ifc.cfg new file mode 100644 index 00000000000..f0cf9c2b38d --- /dev/null +++ b/board/nxp/ls1021aqds/ls102xa_rcw_sd_ifc.cfg @@ -0,0 +1,14 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 + +#enable IFC, disable QSPI and DSPI +0608000c 00000000 00000000 00000000 +60000000 00407900 60040a00 21046000 +00000000 00000000 00000000 00038000 +00000000 001b7200 00000000 00000000 + +#disable IFC, enable QSPI and DSPI +#0608000c 00000000 00000000 00000000 +#60000000 00407900 60040a00 21046000 +#00000000 00000000 00000000 00038000 +#20024800 001b7200 00000000 00000000 diff --git a/board/nxp/ls1021aqds/ls102xa_rcw_sd_qspi.cfg b/board/nxp/ls1021aqds/ls102xa_rcw_sd_qspi.cfg new file mode 100644 index 00000000000..10cc4a9ab0b --- /dev/null +++ b/board/nxp/ls1021aqds/ls102xa_rcw_sd_qspi.cfg @@ -0,0 +1,14 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 + +#enable IFC, disable QSPI and DSPI +#0608000c 00000000 00000000 00000000 +#60000000 00407900 60040a00 21046000 +#00000000 00000000 00000000 00038000 +#00000000 001b7200 00000000 00000000 + +#disable IFC, enable QSPI and DSPI +0608000c 00000000 00000000 00000000 +60000000 00407900 60040a00 21046000 +00000000 00000000 00000000 00038000 +20024800 001b7200 00000000 00000000 diff --git a/board/nxp/ls1021aqds/psci.S b/board/nxp/ls1021aqds/psci.S new file mode 100644 index 00000000000..0f38c934ddf --- /dev/null +++ b/board/nxp/ls1021aqds/psci.S @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 NXP Semiconductor. + * Author: Wang Dongsheng + */ + +#include +#include + +#include +#include + + .pushsection ._secure.text, "ax" + + .arch_extension sec + + .align 5 + +.globl psci_system_off +psci_system_off: + @ Get QIXIS base address + movw r1, #(QIXIS_BASE & 0xffff) + movt r1, #(QIXIS_BASE >> 16) + + ldrb r2, [r1, #QIXIS_PWR_CTL] + orr r2, r2, #QIXIS_PWR_CTL_POWEROFF + strb r2, [r1, #QIXIS_PWR_CTL] + +1: wfi + b 1b + + .popsection diff --git a/board/nxp/ls1021atsn/Kconfig b/board/nxp/ls1021atsn/Kconfig new file mode 100644 index 00000000000..1b20c643a6d --- /dev/null +++ b/board/nxp/ls1021atsn/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0 +if TARGET_LS1021ATSN + +config SYS_BOARD + default "ls1021atsn" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "ls102xa" + +config SYS_CONFIG_NAME + default "ls1021atsn" + +endif diff --git a/board/nxp/ls1021atsn/MAINTAINERS b/board/nxp/ls1021atsn/MAINTAINERS new file mode 100644 index 00000000000..eda36823ddc --- /dev/null +++ b/board/nxp/ls1021atsn/MAINTAINERS @@ -0,0 +1,8 @@ +NXP LS1021A-TSN Board +M: Vladimir Oltean +S: Maintained +F: arch/arm/dts/ls1021a-tsn.dts +F: board/nxp/ls1021atsn/ +F: include/configs/ls1021atsn.h +F: configs/ls1021atsn_qspi_defconfig +F: configs/ls1021atsn_sdcard_defconfig diff --git a/board/nxp/ls1021atsn/Makefile b/board/nxp/ls1021atsn/Makefile new file mode 100644 index 00000000000..b4808f05e8e --- /dev/null +++ b/board/nxp/ls1021atsn/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-y += ls1021atsn.o +obj-$(CONFIG_ARMV7_PSCI) += ../ls1021atwr/psci.o diff --git a/board/nxp/ls1021atsn/README.rst b/board/nxp/ls1021atsn/README.rst new file mode 100644 index 00000000000..cd12291d8aa --- /dev/null +++ b/board/nxp/ls1021atsn/README.rst @@ -0,0 +1,97 @@ +.. SPDX-License-Identifier: GPL-2.0 + +LS1021A-TSN Board Overview +========================== + + - 1GB DDR3 at 800 MHz + - Spansion/Cypress 64 MB (Rev. A) / 32 MB (Rev. B and C) QSPI NOR flash + - Ethernet + - 2 SGMII 10/100/1G Ethernet ports (Atheros AR8031) + - One SJA1105T switch with 4 Ethernet ports (Broadcom BCM5464R) + - One internal RGMII port connected to the switch + - SDHC + - microSDHC/SDXC connector + - Other I/O + - One Serial port + - Arduino and expansion headers + - mPCIE slot + - SATA port + - USB3.0 port + +LS1021A Memory map +================== + +The addresses in brackets are physical addresses. + +============== ============== ============================== ======= +Start Address End Address Description Size +============== ============== ============================== ======= +0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB +0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB +0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB +0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB +============== ============== ============================== ======= + +Compiling and flashing +====================== + +The LS1021A-TSN board comes along with a microSD card with OpenIL U-Boot that +can be used to update its internal QSPI flash (which is empty out of the +factory). + +To compile and flash an SD card image:: + + make ls1021atsn_sdcard_defconfig && make -j 8 && sudo cp u-boot-with-spl-pbl.bin /srv/tftpboot/ + => tftp 0x82000000 u-boot-with-spl-pbl.bin && mmc rescan && mmc erase 8 0x1100 && mmc write 0x82000000 8 0x1100 + +For the QSPI flash, first obtain the Reset Configuration Word binary for +bootimg from the QSPI flash from the rcw project +(https://github.com/nxp-qoriq/rcw):: + + make -j 8 && sudo cp ls1021atsn/SSR_PNS_30/rcw_1200_qspiboot.bin.swapped /srv/tftpboot/ + +The above RCW binary takes care of swapping the QSPI AMBA memory, so that the +U-Boot binary does not need to be swapped when flashing it. + +To compile and flash a U-Boot image for QSPI:: + + make ls1021atsn_qspi_defconfig && make -j 8 && sudo cp u-boot.bin /srv/tftpboot/ + +Then optionally create a custom uboot-env.txt file (although the default +environment already supports distro boot) and convert it to binary format:: + + mkenvimage -s 2M -o /srv/tftpboot/uboot-env.bin uboot-env.txt + +To program the QSPI flash with the images:: + + => tftp 0x82000000 rcw_1200_qspiboot.bin.swapped && sf probe && sf erase 0x0 +${filesize} && sf write 0x82000000 0x0 ${filesize} + => tftp 0x82000000 u-boot.bin && sf probe && sf erase 0x100000 +${filesize} && sf write 0x82000000 0x100000 ${filesize} + => tftp 0x82000000 uboot-env.bin && sf probe && sf erase 0x400000 +${filesize} && sf write 0x82000000 0x400000 ${filesize} + +The boards contain an AT24 I2C EEPROM that is supposed to hold the MAC +addresses of the Ethernet interfaces, however the EEPROM comes blank out of +the factory, and the MAC addresses are printed on a label on the bottom of +the boards. + +To write the MAC addresses to the EEPROM, the following needs to be done once:: + + => mac id + => mac 0 00:1F:7B:xx:xx:xx + => mac 1 00:1F:7B:xx:xx:xx + => mac 2 00:1F:7B:xx:xx:xx + => mac save + +The switch ports do not have their own MAC address - they inherit it from the +master enet2 port. + +Known issues and limitations +============================ + +- The 4 SJA1105 switch ports are not functional in U-Boot for now. +- Since the IFC pins are multiplexed with QSPI on LS1021A, currently there is + no way to talk to the CPLD for e.g. running the "qixis_reset" command, or + turning the fan on, etc. diff --git a/board/nxp/ls1021atsn/ls1021atsn.c b/board/nxp/ls1021atsn/ls1021atsn.c new file mode 100644 index 00000000000..c92430c0896 --- /dev/null +++ b/board/nxp/ls1021atsn/ls1021atsn.c @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright 2016-2019, 2021 NXP + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/sleep.h" +#include +#include +#include +#include +#include +#ifdef CONFIG_U_QE +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static void ddrmc_init(void) +{ +#if (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)) + struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR; + u32 temp_sdram_cfg, tmp; + + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); + + out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); + out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); + + out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); + out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); + out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); + out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); + out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); + out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); + +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + out_be32(&ddr->sdram_cfg_2, + DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT); + out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); + out_be32(&ddr->init_ext_addr, (1 << 31)); + + /* DRAM VRef will not be trained */ + out_be32(&ddr->ddr_cdr2, + DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN); + } else +#endif + { + out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); + out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); + } + + out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); + out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); + + out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); + + out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); + + out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); + out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); + + out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); + + out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); + out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); + + out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); + + /* DDR erratum A-009942 */ + tmp = in_be32(&ddr->debug[28]); + out_be32(&ddr->debug[28], tmp | 0x0070006f); + + udelay(1); + +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* enter self-refresh */ + temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); + temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; + out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); + + temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI); + } else +#endif + temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); + + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); + +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* exit self-refresh */ + temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); + temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; + out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); + } +#endif +#endif /* !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD) */ +} + +int dram_init(void) +{ + ddrmc_init(); + + erratum_a008850_post(); + + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD) + fsl_dp_resume(); +#endif + + return 0; +} + +int board_eth_init(struct bd_info *bis) +{ + return pci_eth_init(bis); +} + +int board_early_init_f(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; + +#ifdef CONFIG_TSEC_ENET + /* + * Clear BD & FR bits for big endian BD's and frame data (aka set + * correct eTSEC endianness). This is crucial in ensuring that it does + * not report Data Parity Errors in its RX/TX FIFOs when attempting to + * send traffic. + */ + clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); + /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */ + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); +#endif + + arch_soc_init(); + +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) { + timer_init(); + dram_init(); + } +#endif + + return 0; +} + +#ifdef CONFIG_XPL_BUILD +void board_init_f(ulong dummy) +{ + void (*second_uboot)(void); + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + get_clocks(); + + if (CONFIG_IS_ENABLED(DEEP_SLEEP)) + if (is_warm_boot()) + fsl_dp_disable_console(); + + preloader_console_init(); + + dram_init(); + + /* Allow OCRAM access permission as R/W */ +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); + enable_layerscape_ns_access(); +#endif + + /* + * if it is woken up from deep sleep, then jump to second + * stage U-Boot and continue executing without recopying + * it from SD since it has already been reserved in memory + * in last boot. + */ + if (CONFIG_IS_ENABLED(DEEP_SLEEP)) { + if (is_warm_boot()) { + second_uboot = (void (*)(void))CONFIG_TEXT_BASE; + second_uboot(); + } + } + + board_init_r(NULL, 0); +} +#endif + +int board_init(void) +{ +#ifndef CONFIG_SYS_FSL_NO_SERDES + fsl_serdes_init(); +#endif + ls102xa_smmu_stream_id_init(); + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + +#ifdef CONFIG_U_QE + u_qe_init(); +#endif + + return 0; +} + +#if defined(CONFIG_XPL_BUILD) +void spl_board_init(void) +{ + ls102xa_smmu_stream_id_init(); +} +#endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_CHAIN_OF_TRUST + fsl_setenv_chain_of_trust(); +#endif + + return 0; +} +#endif + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ +#ifdef CONFIG_FSL_DEVICE_DISABLE + device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); +#endif + return 0; +} +#endif + +#if defined(CONFIG_DEEP_SLEEP) +void board_sleep_prepare(void) +{ +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif +} +#endif + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + + return 0; +} diff --git a/board/nxp/ls1021atsn/ls102xa_pbi.cfg b/board/nxp/ls1021atsn/ls102xa_pbi.cfg new file mode 100644 index 00000000000..ba1499b2644 --- /dev/null +++ b/board/nxp/ls1021atsn/ls102xa_pbi.cfg @@ -0,0 +1,15 @@ +# PBI commands + +09570200 ffffffff +09570158 00000300 +8940007c 21f47300 + +# Configure Scratch register +09ee0200 10000000 +# Configure alternate space +09570158 00001000 +# Flush PBL data +096100c0 000FFFFF + +09ea085c 00502880 +09ea0560 80800000 diff --git a/board/nxp/ls1021atsn/ls102xa_rcw_sd.cfg b/board/nxp/ls1021atsn/ls102xa_rcw_sd.cfg new file mode 100644 index 00000000000..a6fc91436f2 --- /dev/null +++ b/board/nxp/ls1021atsn/ls102xa_rcw_sd.cfg @@ -0,0 +1,8 @@ +# PBL preamble and RCW header +aa55aa55 01ee0100 + +# Disable IFC, enable QSPI and DSPI +0608000c 00000000 00000000 00000000 +30000000 08007900 40105a00 21046000 +00000000 00000000 00000000 10002000 +20124801 8804b340 00000000 00000000 diff --git a/board/nxp/ls1021atwr/Kconfig b/board/nxp/ls1021atwr/Kconfig new file mode 100644 index 00000000000..4c99d999d99 --- /dev/null +++ b/board/nxp/ls1021atwr/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1021ATWR + +config SYS_BOARD + default "ls1021atwr" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "ls102xa" + +config SYS_CONFIG_NAME + default "ls1021atwr" + +endif diff --git a/board/nxp/ls1021atwr/MAINTAINERS b/board/nxp/ls1021atwr/MAINTAINERS new file mode 100644 index 00000000000..f70b06da5df --- /dev/null +++ b/board/nxp/ls1021atwr/MAINTAINERS @@ -0,0 +1,12 @@ +LS1021ATWR BOARD +M: Alison Wang +S: Maintained +F: board/nxp/ls1021atwr/ +F: include/configs/ls1021atwr.h +F: configs/ls1021atwr_nor_defconfig +F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig +F: configs/ls1021atwr_nor_lpuart_defconfig +F: configs/ls1021atwr_sdcard_ifc_defconfig +F: configs/ls1021atwr_sdcard_qspi_defconfig +F: configs/ls1021atwr_qspi_defconfig +F: configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig diff --git a/board/nxp/ls1021atwr/Makefile b/board/nxp/ls1021atwr/Makefile new file mode 100644 index 00000000000..cfa6c0c8540 --- /dev/null +++ b/board/nxp/ls1021atwr/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021atwr.o +obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/nxp/ls1021atwr/README b/board/nxp/ls1021atwr/README new file mode 100644 index 00000000000..a4639cd7476 --- /dev/null +++ b/board/nxp/ls1021atwr/README @@ -0,0 +1,114 @@ +Overview +-------- +The LS1021ATWR is a Freescale reference board that hosts the LS1021A SoC. + +LS1021A SoC Overview +------------------ +The QorIQ LS1 family, which includes the LS1021A communications processor, +is built on Layerscape architecture, the industry's first software-aware, +core-agnostic networking architecture to offer unprecedented efficiency +and scale. + +A member of the value-performance tier, the QorIQ LS1021A processor provides +extensive integration and power efficiency for fanless, small form factor +enterprise networking applications. Incorporating dual ARM Cortex-A7 cores +running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark +performance of over 6,000, as well as virtualization support, advanced +security features and the broadest array of high-speed interconnects and +optimized peripheral features ever offered in a sub-3 W processor. + +The QorIQ LS1021A processor features an integrated LCD controller, +CAN controller for implementing industrial protocols, DDR3L/4 running +up to 1600 MHz, integrated security engine and QUICC Engine, and ECC +protection on both L1 and L2 caches. The LS1021A processor is pin- and +software-compatible with the QorIQ LS1020A and LS1022A processors. + +The LS1021A SoC includes the following function and features: + + - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture + - Dual high-preformance ARM Cortex-A7 cores, each core includes: + - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection) + - 512 Kbyte shared coherent L2 Cache (with ECC protection) + - NEON Co-processor (per core) + - 40-bit physical addressing + - Vector floating-point support + - ARM Core-Link CCI-400 Cache Coherent Interconnect + - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration + supporting speeds up to 1600Mtps + - ECC and interleaving support + - VeTSEC Ethernet complex + - Up to 3x virtualized 10/100/1000 Ethernet controllers + - MII, RMII, RGMII, and SGMII support + - QoS, lossless flow control, and IEEE 1588 support + - 4-lane 6GHz SerDes + - High speed interconnect (4 SerDes lanes with are muxed for these protocol) + - Two PCI Express Gen2 controllers running at up to 5 GHz + - One Serial ATA 3.0 supporting 6 GT/s operation + - Two SGMII interfaces supporting 1000 Mbps + - Additional peripheral interfaces + - One high-speed USB 3.0 controller with integrated PHY and one high-speed + USB 2.00 controller with ULPI + - Integrated flash controller (IFC) with 16-bit interface + - Quad SPI NOR Flash + - One enhanced Secure digital host controller + - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface) + - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power + UARTs + - Three I2C controllers + - Eight FlexTimers four supporting PWM and four FlexCAN ports + - Four GPIO controllers supporting up to 109 general purpose I/O signals + - Integrated advanced audio block: + - Four synchronous audio interfaces (SAI) + - Sony/Philips Digital Interconnect Format (SPDIF) + - Asynchronous Sample Rate Converter (ASRC) + - Hardware based crypto offload engine + - IPSec forwarding at up to 1Gbps + - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported + - Public key hardware accelerator + - True Random Number Generator (NIST Certified) + - Advanced Encryption Standard Accelerators (AESA) + - Data Encryption Standard Accelerators + - QUICC Engine ULite block + - Two universal communication controllers (TDM and HDLC) supporting 64 + multichannels, each running at 64 Kbps + - Support for 256 channels of HDLC + - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported + +LS1021ATWR board Overview +------------------------- + - DDR Controller + - Supports rates of up to 1600 MHz data-rate + - Supports one DDR3LP SDRAM. + - IFC/Local Bus + - NOR: 128MB 16-bit NOR Flash + - Ethernet + - Three on-board RGMII 10/100/1G ethernet ports. + - CPLD + - Clocks + - System and DDR clock (SYSCLK, DDRCLK) + - SERDES clocks + - Power Supplies + - SDHC + - SDHC/SDXC connector + - Other IO + - One Serial port + - Three I2C ports + +Memory map +----------- +The addresses in brackets are physical addresses. + +Start Address End Address Description Size +0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB +0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB +0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB +0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB + +LS1021a rev1.0 Soc specific Options/Settings +-------------------------------------------- +If the LS1021a Soc is rev1.0, you need modify the configuration and enable +CONFIG_SPL_SKIP_LOWLEVEL_INIT in menuconfig or similar. diff --git a/board/nxp/ls1021atwr/ls1021atwr.c b/board/nxp/ls1021atwr/ls1021atwr.c new file mode 100644 index 00000000000..0758e5eae25 --- /dev/null +++ b/board/nxp/ls1021atwr/ls1021atwr.c @@ -0,0 +1,753 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2019, 2021-2022 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/sleep.h" +#ifdef CONFIG_U_QE +#include +#endif +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define VERSION_MASK 0x00FF +#define BANK_MASK 0x0001 +#define CFG_RESET 0x1 +#define INIT_RESET 0x1 + +#define CPLD_SET_MUX_SERDES 0x20 +#define CPLD_SET_BOOT_BANK 0x40 + +#define BOOT_FROM_UPPER_BANK 0x0 +#define BOOT_FROM_LOWER_BANK 0x1 + +#define LANEB_SATA (0x01) +#define LANEB_SGMII1 (0x02) +#define LANEC_SGMII1 (0x04) +#define LANEC_PCIEX1 (0x08) +#define LANED_PCIEX2 (0x10) +#define LANED_SGMII2 (0x20) + +#define MASK_LANE_B 0x1 +#define MASK_LANE_C 0x2 +#define MASK_LANE_D 0x4 +#define MASK_SGMII 0x8 + +#define KEEP_STATUS 0x0 +#define NEED_RESET 0x1 + +#define SOFT_MUX_ON_I2C3_IFC 0x2 +#define SOFT_MUX_ON_CAN3_USB2 0x8 +#define SOFT_MUX_ON_QE_LCD 0x10 + +#define PIN_I2C3_IFC_MUX_I2C3 0x0 +#define PIN_I2C3_IFC_MUX_IFC 0x1 +#define PIN_CAN3_USB2_MUX_USB2 0x0 +#define PIN_CAN3_USB2_MUX_CAN3 0x1 +#define PIN_QE_LCD_MUX_LCD 0x0 +#define PIN_QE_LCD_MUX_QE 0x1 + +struct cpld_data { + u8 cpld_ver; /* cpld revision */ + u8 cpld_ver_sub; /* cpld sub revision */ + u8 pcba_ver; /* pcb revision number */ + u8 system_rst; /* reset system by cpld */ + u8 soft_mux_on; /* CPLD override physical switches Enable */ + u8 cfg_rcw_src1; /* Reset config word 1 */ + u8 cfg_rcw_src2; /* Reset config word 2 */ + u8 vbank; /* Flash bank selection Control */ + u8 gpio; /* GPIO for TWR-ELEV */ + u8 i2c3_ifc_mux; + u8 mux_spi2; + u8 can3_usb2_mux; /* CAN3 and USB2 Selection */ + u8 qe_lcd_mux; /* QE and LCD Selection */ + u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */ + u8 global_rst; /* reset with init CPLD reg to default */ + u8 rev1; /* Reserved */ + u8 rev2; /* Reserved */ +}; + +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +static void cpld_show(void) +{ + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); + + printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n", + in_8(&cpld_data->cpld_ver) & VERSION_MASK, + in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK, + in_8(&cpld_data->pcba_ver) & VERSION_MASK, + in_8(&cpld_data->vbank) & BANK_MASK); + +#ifdef DEBUG + printf("soft_mux_on =%x\n", + in_8(&cpld_data->soft_mux_on)); + printf("cfg_rcw_src1 =%x\n", + in_8(&cpld_data->cfg_rcw_src1)); + printf("cfg_rcw_src2 =%x\n", + in_8(&cpld_data->cfg_rcw_src2)); + printf("vbank =%x\n", + in_8(&cpld_data->vbank)); + printf("gpio =%x\n", + in_8(&cpld_data->gpio)); + printf("i2c3_ifc_mux =%x\n", + in_8(&cpld_data->i2c3_ifc_mux)); + printf("mux_spi2 =%x\n", + in_8(&cpld_data->mux_spi2)); + printf("can3_usb2_mux =%x\n", + in_8(&cpld_data->can3_usb2_mux)); + printf("qe_lcd_mux =%x\n", + in_8(&cpld_data->qe_lcd_mux)); + printf("serdes_mux =%x\n", + in_8(&cpld_data->serdes_mux)); +#endif +} +#endif + +int checkboard(void) +{ + puts("Board: LS1021ATWR\n"); +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) + cpld_show(); +#endif + + return 0; +} + +void ddrmc_init(void) +{ + struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR; + u32 temp_sdram_cfg, tmp; + + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); + + out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); + out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); + + out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); + out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); + out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); + out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); + out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); + out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); + +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + out_be32(&ddr->sdram_cfg_2, + DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT); + out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); + out_be32(&ddr->init_ext_addr, (1 << 31)); + + /* DRAM VRef will not be trained */ + out_be32(&ddr->ddr_cdr2, + DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN); + } else +#endif + { + out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); + out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); + } + + out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); + out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); + + out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); + + out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); + + out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); + out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); + + out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); + + out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); + out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); + + out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); + + /* DDR erratum A-009942 */ + tmp = in_be32(&ddr->debug[28]); + out_be32(&ddr->debug[28], tmp | 0x0070006f); + + udelay(1); + +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* enter self-refresh */ + temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); + temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; + out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); + + temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI); + } else +#endif + temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); + + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); + +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* exit self-refresh */ + temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); + temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; + out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); + } +#endif +} + +int dram_init(void) +{ +#if (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)) + ddrmc_init(); +#endif + + erratum_a008850_post(); + + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD) + fsl_dp_resume(); +#endif + + return 0; +} + +int board_eth_init(struct bd_info *bis) +{ + return pci_eth_init(bis); +} + +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +static void convert_serdes_mux(int type, int need_reset) +{ + char current_serdes; + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); + + current_serdes = cpld_data->serdes_mux; + + switch (type) { + case LANEB_SATA: + current_serdes &= ~MASK_LANE_B; + break; + case LANEB_SGMII1: + current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C); + break; + case LANEC_SGMII1: + current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C); + break; + case LANED_SGMII2: + current_serdes |= MASK_LANE_D; + break; + case LANEC_PCIEX1: + current_serdes |= MASK_LANE_C; + break; + case (LANED_PCIEX2 | LANEC_PCIEX1): + current_serdes |= MASK_LANE_C; + current_serdes &= ~MASK_LANE_D; + break; + default: + printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type); + return; + } + + cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES; + cpld_data->serdes_mux = current_serdes; + + if (need_reset == 1) { + printf("Reset board to enable configuration\n"); + cpld_data->system_rst = CFG_RESET; + } +} + +int config_serdes_mux(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; + + protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT; + switch (protocol) { + case 0x10: + convert_serdes_mux(LANEB_SATA, KEEP_STATUS); + convert_serdes_mux(LANED_PCIEX2 | + LANEC_PCIEX1, KEEP_STATUS); + break; + case 0x20: + convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS); + convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); + convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); + break; + case 0x30: + convert_serdes_mux(LANEB_SATA, KEEP_STATUS); + convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS); + convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); + break; + case 0x70: + convert_serdes_mux(LANEB_SATA, KEEP_STATUS); + convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); + convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); + break; + } + + return 0; +} +#endif + +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +int config_board_mux(void) +{ + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); + int conflict_flag; + + conflict_flag = 0; + if (hwconfig("i2c3")) { + conflict_flag++; + cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC; + cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3; + } + + if (hwconfig("ifc")) { + conflict_flag++; + /* some signals can not enable simultaneous*/ + if (conflict_flag > 1) + goto conflict; + cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC; + cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC; + } + + conflict_flag = 0; + if (hwconfig("usb2")) { + conflict_flag++; + cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2; + cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2; + } + + if (hwconfig("can3")) { + conflict_flag++; + /* some signals can not enable simultaneous*/ + if (conflict_flag > 1) + goto conflict; + cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2; + cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3; + } + + conflict_flag = 0; + if (hwconfig("lcd")) { + conflict_flag++; + cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD; + cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD; + } + + if (hwconfig("qe")) { + conflict_flag++; + /* some signals can not enable simultaneous*/ + if (conflict_flag > 1) + goto conflict; + cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD; + cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE; + } + + return 0; + +conflict: + printf("WARNING: pin conflict! MUX setting may failed!\n"); + return 0; +} +#endif + +int board_early_init_f(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; + +#ifdef CONFIG_TSEC_ENET + /* clear BD & FR bits for BE BD's and frame data */ + clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); +#endif + +#ifdef CONFIG_FSL_IFC + init_early_memctl_regs(); +#endif + + arch_soc_init(); + +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) { + timer_init(); + dram_init(); + } +#endif + + return 0; +} + +#ifdef CONFIG_XPL_BUILD +void board_init_f(ulong dummy) +{ + void (*second_uboot)(void); + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + get_clocks(); + + if (CONFIG_IS_ENABLED(DEEP_SLEEP)) + if (is_warm_boot()) + fsl_dp_disable_console(); + + preloader_console_init(); + + timer_init(); + dram_init(); + + /* Allow OCRAM access permission as R/W */ +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + + /* + * if it is woken up from deep sleep, then jump to second + * stage uboot and continue executing without recopying + * it from SD since it has already been reserved in memeory + * in last boot. + */ + if (CONFIG_IS_ENABLED(DEEP_SLEEP)) { + if (is_warm_boot()) { + second_uboot = (void (*)(void))CONFIG_TEXT_BASE; + second_uboot(); + } + } + + board_init_r(NULL, 0); +} +#endif + +#ifdef CONFIG_DEEP_SLEEP +/* program the regulator (MC34VR500) to support deep sleep */ +void ls1twr_program_regulator(void) +{ + u8 i2c_device_id; + +#define LS1TWR_I2C_BUS_MC34VR500 1 +#define MC34VR500_ADDR 0x8 +#define MC34VR500_DEVICEID 0x4 +#define MC34VR500_DEVICEID_MASK 0x0f +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(LS1TWR_I2C_BUS_MC34VR500, MC34VR500_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + LS1TWR_I2C_BUS_MC34VR500); + return; + } + i2c_device_id = dm_i2c_reg_read(dev, 0x0) & + MC34VR500_DEVICEID_MASK; + if (i2c_device_id != MC34VR500_DEVICEID) { + printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n"); + return; + } + + dm_i2c_reg_write(dev, 0x31, 0x4); + dm_i2c_reg_write(dev, 0x4d, 0x4); + dm_i2c_reg_write(dev, 0x6d, 0x38); + dm_i2c_reg_write(dev, 0x6f, 0x37); + dm_i2c_reg_write(dev, 0x71, 0x30); +#else + unsigned int i2c_bus; + i2c_bus = i2c_get_bus_num(); + i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500); + i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) & + MC34VR500_DEVICEID_MASK; + if (i2c_device_id != MC34VR500_DEVICEID) { + printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n"); + return; + } + + i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4); + i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4); + i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38); + i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37); + i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30); + + i2c_set_bus_num(i2c_bus); +#endif +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + +#ifndef CONFIG_SYS_FSL_NO_SERDES + fsl_serdes_init(); +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) + config_serdes_mux(); +#endif +#endif + + ls102xa_smmu_stream_id_init(); + +#ifdef CONFIG_U_QE + u_qe_init(); +#endif + +#ifdef CONFIG_DEEP_SLEEP + ls1twr_program_regulator(); +#endif + return 0; +} + +#if defined(CONFIG_XPL_BUILD) +void spl_board_init(void) +{ + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize caam_jr: %d\n", ret); + } + + ls102xa_smmu_stream_id_init(); +} +#endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_CHAIN_OF_TRUST + fsl_setenv_chain_of_trust(); +#endif + + return 0; +} +#endif + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ +#ifdef CONFIG_FSL_DEVICE_DISABLE + device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); +#endif +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) + config_board_mux(); +#endif + return 0; +} +#endif + +#if defined(CONFIG_DEEP_SLEEP) +void board_sleep_prepare(void) +{ +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif +} +#endif + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + + return 0; +} + +u8 flash_read8(void *addr) +{ + return __raw_readb(addr + 1); +} + +void flash_write16(u16 val, void *addr) +{ + u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); + + __raw_writew(shftval, addr); +} + +u16 flash_read16(void *addr) +{ + u16 val = __raw_readw(addr); + + return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); +} + +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \ + && !defined(CONFIG_XPL_BUILD) +static void convert_flash_bank(char bank) +{ + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); + + printf("Now switch to boot from flash bank %d.\n", bank); + cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK; + cpld_data->vbank = bank; + + printf("Reset board to enable configuration.\n"); + cpld_data->system_rst = CFG_RESET; +} + +static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + if (strcmp(argv[1], "0") == 0) + convert_flash_bank(BOOT_FROM_UPPER_BANK); + else if (strcmp(argv[1], "1") == 0) + convert_flash_bank(BOOT_FROM_LOWER_BANK); + else + return CMD_RET_USAGE; + + return 0; +} + +U_BOOT_CMD( + boot_bank, 2, 0, flash_bank_cmd, + "Flash bank Selection Control", + "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)" +); + +static int cpld_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); + + if (argc > 2) + return CMD_RET_USAGE; + if ((argc == 1) || (strcmp(argv[1], "conf") == 0)) + cpld_data->system_rst = CFG_RESET; + else if (strcmp(argv[1], "init") == 0) + cpld_data->global_rst = INIT_RESET; + else + return CMD_RET_USAGE; + + return 0; +} + +U_BOOT_CMD( + cpld_reset, 2, 0, cpld_reset_cmd, + "Reset via CPLD", + "conf\n" + " -reset with current CPLD configuration\n" + "init\n" + " -reset and initial CPLD configuration with default value" + +); + +static void print_serdes_mux(void) +{ + char current_serdes; + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); + + current_serdes = cpld_data->serdes_mux; + + printf("Serdes Lane B: "); + if ((current_serdes & MASK_LANE_B) == 0) + printf("SATA,\n"); + else + printf("SGMII 1,\n"); + + printf("Serdes Lane C: "); + if ((current_serdes & MASK_LANE_C) == 0) + printf("SGMII 1,\n"); + else + printf("PCIe,\n"); + + printf("Serdes Lane D: "); + if ((current_serdes & MASK_LANE_D) == 0) + printf("PCIe,\n"); + else + printf("SGMII 2,\n"); + + printf("SGMII 1 is on lane "); + if ((current_serdes & MASK_SGMII) == 0) + printf("C.\n"); + else + printf("B.\n"); +} + +static int serdes_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + if (strcmp(argv[1], "sata") == 0) { + printf("Set serdes lane B to SATA.\n"); + convert_serdes_mux(LANEB_SATA, NEED_RESET); + } else if (strcmp(argv[1], "sgmii1b") == 0) { + printf("Set serdes lane B to SGMII 1.\n"); + convert_serdes_mux(LANEB_SGMII1, NEED_RESET); + } else if (strcmp(argv[1], "sgmii1c") == 0) { + printf("Set serdes lane C to SGMII 1.\n"); + convert_serdes_mux(LANEC_SGMII1, NEED_RESET); + } else if (strcmp(argv[1], "sgmii2") == 0) { + printf("Set serdes lane D to SGMII 2.\n"); + convert_serdes_mux(LANED_SGMII2, NEED_RESET); + } else if (strcmp(argv[1], "pciex1") == 0) { + printf("Set serdes lane C to PCIe X1.\n"); + convert_serdes_mux(LANEC_PCIEX1, NEED_RESET); + } else if (strcmp(argv[1], "pciex2") == 0) { + printf("Set serdes lane C & lane D to PCIe X2.\n"); + convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET); + } else if (strcmp(argv[1], "show") == 0) { + print_serdes_mux(); + } else { + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + lane_bank, 2, 0, serdes_mux_cmd, + "Multiplexed function setting for SerDes Lanes", + "sata\n" + " -change lane B to sata\n" + "lane_bank sgmii1b\n" + " -change lane B to SGMII1\n" + "lane_bank sgmii1c\n" + " -change lane C to SGMII1\n" + "lane_bank sgmii2\n" + " -change lane D to SGMII2\n" + "lane_bank pciex1\n" + " -change lane C to PCIeX1\n" + "lane_bank pciex2\n" + " -change lane C & lane D to PCIeX2\n" + "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n" +); +#endif diff --git a/board/nxp/ls1021atwr/ls102xa_pbi.cfg b/board/nxp/ls1021atwr/ls102xa_pbi.cfg new file mode 100644 index 00000000000..f1a1b63ab77 --- /dev/null +++ b/board/nxp/ls1021atwr/ls102xa_pbi.cfg @@ -0,0 +1,12 @@ +#PBI commands + +09570200 ffffffff +09570158 00000300 +8940007c 21f47300 + +#Configure Scratch register +09ee0200 10000000 +#Configure alternate space +09570158 00001000 +#Flush PBL data +096100c0 000FFFFF diff --git a/board/nxp/ls1021atwr/ls102xa_rcw_sd_ifc.cfg b/board/nxp/ls1021atwr/ls102xa_rcw_sd_ifc.cfg new file mode 100644 index 00000000000..f94997d5384 --- /dev/null +++ b/board/nxp/ls1021atwr/ls102xa_rcw_sd_ifc.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 + +#enable IFC, disable QSPI and DSPI +0608000c 00000000 00000000 00000000 +30000000 00007900 60040a00 21046000 +00000000 00000000 00000000 20000000 +00080000 881b7340 00000000 00000000 diff --git a/board/nxp/ls1021atwr/ls102xa_rcw_sd_qspi.cfg b/board/nxp/ls1021atwr/ls102xa_rcw_sd_qspi.cfg new file mode 100644 index 00000000000..541b604cffc --- /dev/null +++ b/board/nxp/ls1021atwr/ls102xa_rcw_sd_qspi.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 + +#disable IFC, enable QSPI and DSPI +0608000c 00000000 00000000 00000000 +30000000 00007900 60040a00 21046000 +00000000 00000000 00000000 20000000 +20024800 881b7340 00000000 00000000 diff --git a/board/nxp/ls1021atwr/psci.S b/board/nxp/ls1021atwr/psci.S new file mode 100644 index 00000000000..3c093aa33cb --- /dev/null +++ b/board/nxp/ls1021atwr/psci.S @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 NXP Semiconductor. + * Author: Wang Dongsheng + */ + +#include +#include + +#include +#include + + .pushsection ._secure.text, "ax" + + .arch_extension sec + + .align 5 + +.globl psci_system_off +psci_system_off: +1: wfi + b 1b + + .popsection diff --git a/board/nxp/ls1028a/Kconfig b/board/nxp/ls1028a/Kconfig new file mode 100644 index 00000000000..d14eac2720e --- /dev/null +++ b/board/nxp/ls1028a/Kconfig @@ -0,0 +1,47 @@ +if TARGET_LS1028AQDS + +config SYS_BOARD + default "ls1028a" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1028aqds" + +config EMMC_BOOT + bool "Support for booting from EMMC" + +config TEXT_BASE + default 0x96000000 if SD_BOOT || EMMC_BOOT + default 0x82000000 if TFABOOT + default 0x20100000 + +endif + +if TARGET_LS1028ARDB + +config SYS_BOARD + default "ls1028a" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1028ardb" + +config EMMC_BOOT + bool "Support for booting from EMMC" + +config TEXT_BASE + default 0x96000000 if SD_BOOT || EMMC_BOOT + default 0x82000000 if TFABOOT + default 0x20100000 + +endif diff --git a/board/nxp/ls1028a/MAINTAINERS b/board/nxp/ls1028a/MAINTAINERS new file mode 100644 index 00000000000..fcaf7eddc51 --- /dev/null +++ b/board/nxp/ls1028a/MAINTAINERS @@ -0,0 +1,26 @@ +LS1028AQDS BOARD +M: Tang Yuantian +S: Maintained +F: board/nxp/ls1028a/ +F: include/configs/ls1028a_common.h +F: include/configs/ls1028aqds.h +F: configs/ls1028aqds_tfa_defconfig +F: configs/ls1028aqds_tfa_lpuart_defconfig + +LS1028ARDB BOARD +M: Tang Yuantian +S: Maintained +F: board/nxp/ls1028a/ +F: include/configs/ls1028a_common.h +F: include/configs/ls1028ardb.h +F: configs/ls1028ardb_tfa_defconfig + +LS1028AQDS_SECURE_BOOT BOARD +M: Tang Yuantian +S: Maintained +F: configs/ls1028aqds_tfa_SECURE_BOOT_defconfig + +LS1028ARDB_SECURE_BOOT BOARD +M: Tang Yuantian +S: Maintained +F: configs/ls1028ardb_tfa_SECURE_BOOT_defconfig diff --git a/board/nxp/ls1028a/Makefile b/board/nxp/ls1028a/Makefile new file mode 100644 index 00000000000..9bc144cbfea --- /dev/null +++ b/board/nxp/ls1028a/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2019 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1028a.o +obj-y += ddr.o diff --git a/board/nxp/ls1028a/README b/board/nxp/ls1028a/README new file mode 100644 index 00000000000..323881faa50 --- /dev/null +++ b/board/nxp/ls1028a/README @@ -0,0 +1,164 @@ +Overview +-------- +The LS1028A Reference Design (RDB) is a high-performance computing, +evaluation, and development platform that supports ARM SoC LS1028A and its +derivatives. + +LS1028A SoC Overview +-------------------------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc + +RDB Default Switch Settings (1: ON; 0: OFF) +------------------------------------------- +For XSPI NOR boot (default) +SW2: 1111_1000 +SW3: 1111_0000 +SW5: 0011_1001 + +For SD Boot +SW2: 1000_1000 +SW3: 1111_0000 +SW5: 0011_1001 + +For eMMC Boot +SW2: 1001_1000 +SW3: 1111_0000 +SW5: 0011_1001 + +LS1028ARDB board Overview +------------------------- +Processor + Two Arm Cortex- A72 processor cores: + - Based on 64-bit ARMv8 architecture + - Up to 1.3 GHz operation + - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1 + data cache + - Arranged as a single cluster of two cores sharing a single 1 MB L2 + cache +DDR memory + - Five onboard 1G x8 discrete memory modules (Four data byte lanes + ECC) + - 32-bit data and 4-bit ECC + - One chip select + - Data transfer rates of up to 1.6 GT/s + - Single-bit error correction and double-bit error detection ECC (4-bit + check word across 32-bit data) +High-speed serial ports(SerDes) + - Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the + Qualcomm AR8033 PHY + - Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected + through the NXP F104S8A PHY + - Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3 + (8 Gbit/s) cards + - Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2 Key-B + slot through a register mux to support either PCIe Gen 3 (8 Gbit/s) or + SATA Gen 3 cards (6 Gbit/s) at a time +eSDHC + - eSDHC1, eSDHC2 +SPI + - Connects to two mikroBUS sockets to support mikro-click modules, + such as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near + field communications (NFC) controller +Octal SPI (XSPI) + - One 256 MB onboard XSPI serial NOR flash memory + - One 512 MB onboard XSPI serial NAND flash memory + - Supports a QSPI emulator for offboard QSPI emulation +I2C + - All system devices are accessed via I2C1, which is multiplexed on + I2C multiplexer PCA9848 to isolate address conflicts and reduce + capacitive load + - I2C1 is used for EEPROMs, RTC, INA220 current-power sensor, + thermal monitor, PCIe/SATA M.2 connectors and mikro-click modules + 1 and 2 +CAN + - The two CAN DB9 ports can support CAN FD fast phase at data rates of + up to 5 Mbit/s +Serial audio interface(SAI) + - Audio codec SGTL5000 provides headphone and audio LINEOUT for + stereo speakers + - IEEE1588 interface to support audio on SAI4 + +QDS Default Switch Settings (1: ON; 0: OFF) +------------------------------------------- +For SD Boot +SW1 : 1000_0000 +SW2 : 1110_0110 +SW3 : 0000_0010 +SW4 : 0000_0000 +SW5 : 0000_0000 +SW6 : 0000_0000 +SW7 : 1111_0011 +SW8 : 1110_0000 +SW9 : 1000_0001 +SW10: 1110_0000 + +For XSPI Boot +SW1 : 1111_0000 +SW2 : 0000_0110 +SW3 : 0000_0010 +SW4 : 0000_0000 +SW5 : 0110_0000 +SW6 : 0101_0000 +SW7 : 1111_0011 +SW8 : 1110_0000 +SW9 : 1000_0000 +SW10: 1110_0000 + +LS1028AQDS board Overview +------------------------- +Processor + Two Arm Cortex- A72 processor cores: + - Based on 64-bit ARMv8 architecture + - Up to 1.3 GHz operation + - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1 + data cache + - Arranged as a single cluster of two cores sharing a single 1 MB L2 + cache +DDR memory + - Supports data rates of up to 1.6 GT/s for both, DDR4 and DDR3L + - Supports a single- or dual-ranked SODIMM or UDIMM connector + - 32-bit data and 4-bit ECC + - Supports x8/x16 devices + - Supports ECC error detection and correction + - 1.35 V or 1.2 V DDR power supply, with automatic tracking of VTT, to + all devices in case of DDR3L or DDR4, respectively. Power can + switch to 1.35 V or 1.2 V, based on the switch settings for DDR3L or + DDR4 devices, respectively +SerDes (Serializer/Deserializer) + - Four-lane (0-3) SerDes: + - Lane 0: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 10 + Gbit SXGMII, 1 Gbit SGMII + - Lane 1: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit + SGMII, 10 Gbit QXGMII, 5 Gbit QSGMII, 1 Gbit SGMII + - Lane 2: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit + SGMII + - Lane 3: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit + SGMII, SATA 2.0/3.0 + - Four slots on SerDes lanes support PCIe Gen1/2/3, 1 Gbit SGMII + add-in cards + - Lane 1 connects to a 2x10 connector with SFP+ through a retimer; + lane 2 (TX lines) connects to an SMA connector + Lane 3 connects to 1x7 header to support SATA devices +eSDHC + - eSDHC1, eSDHC2 +SPI + - SPI1 and SPI2 support three onboard SPI flash memory devices: + 512 Mbit high-speed flash (with speed of up to 108/54 MHz) + memory for storage + 4 Mbit low-speed flash memory (with speed of up to 40 MHz) + 64 Mbit high-speed flash memory (with speed of up to 104/80 + MHz) + - SPI3 supports one onboard 64 Mbit SPI flash memory (with speed of + up to 104/80 MHz) + - All memories operate at 1.8 V + - A header is provided on SPI1 to test SPI slave mode +I2C + - LS1028A supports eight I2C controllers +Serial audio interface(SAI) + Two SAI ports with audio codec SGTL5000: + - Include stereo LINEIN with support for external analog input + - Provide headphone and line output +Display + - DisplayPort connector to connect the DP data to a 4K display device + (computer monitor) + - eDP connector to connect the DP data to a 4K display panel diff --git a/board/nxp/ls1028a/ddr.c b/board/nxp/ls1028a/ddr.c new file mode 100644 index 00000000000..c406f2436d1 --- /dev/null +++ b/board/nxp/ls1028a/ddr.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} diff --git a/board/nxp/ls1028a/ls1028a.c b/board/nxp/ls1028a/ls1028a.c new file mode 100644 index 00000000000..db94d9c1fa8 --- /dev/null +++ b/board/nxp/ls1028a/ls1028a.c @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019-2022 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "../common/qixis.h" +#include "../drivers/net/fsl_enetc.h" + +DECLARE_GLOBAL_DATA_PTR; + +int config_board_mux(void) +{ +#ifndef CONFIG_LPUART +#if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS) + u8 reg; + + reg = QIXIS_READ(brdcfg[13]); + /* Field| Function + * 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3): + * I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}. + * 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4): + * I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}. + */ + reg &= ~(0xf0); + reg |= 0xb0; + QIXIS_WRITE(brdcfg[13], reg); + + reg = QIXIS_READ(brdcfg[15]); + /* Field| Function + * 7 | Controls the CAN1 transceiver (net CFG_CAN1_STBY): + * CAN1 | 0= CAN #1 transceiver enabled + * 6 | Controls the CAN2 transceiver (net CFG_CAN2_STBY): + * CAN2 | 0= CAN #2 transceiver enabled + */ + reg &= ~(0xc0); + QIXIS_WRITE(brdcfg[15], reg); +#endif +#endif + + return 0; +} + +#ifdef CONFIG_LPUART +u32 get_lpuart_clk(void) +{ + return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV; +} +#endif + +int board_init(void) +{ +#ifndef CONFIG_SYS_EARLY_PCI_INIT + pci_init(); +#endif + +#if defined(CONFIG_TARGET_LS1028ARDB) + u8 val = I2C_MUX_CH_DEFAULT; + +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1); +#else + struct udevice *dev; + + if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev)) + dm_i2c_write(dev, 0x0b, &val, 1); +#endif +#endif + +#if defined(CONFIG_TARGET_LS1028ARDB) + u8 reg; + + reg = QIXIS_READ(brdcfg[4]); + /* + * Field | Function + * 3 | DisplayPort Power Enable (net DP_PWR_EN): + * DPPWR | 0= DP_PWR is enabled. + */ + reg &= ~(DP_PWD_EN_DEFAULT_MASK); + QIXIS_WRITE(brdcfg[4], reg); +#endif + return 0; +} + +int board_eth_init(struct bd_info *bis) +{ + return pci_eth_init(bis); +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + config_board_mux(); + + return 0; +} +#endif + +int board_early_init_f(void) +{ +#ifdef CONFIG_LPUART + u8 uart; +#endif + +#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_XPL_BUILD) + i2c_early_init_f(); +#endif + + fsl_lsch3_early_init_f(); + +#ifdef CONFIG_LPUART + /* + * Field| Function + * -------------------------------------------------------------- + * 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3): + * I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}. + * -------------------------------------------------------------- + * 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4): + * I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}. + */ + /* use lpuart0 as system console */ + uart = QIXIS_READ(brdcfg[13]); + uart &= ~CFG_LPUART_MUX_MASK; + uart |= CFG_LPUART_EN; + QIXIS_WRITE(brdcfg[13], uart); +#endif + + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); + print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_ddr_info(0); +} + +int esdhc_status_fixup(void *blob, const char *compat) +{ + void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE; + char esdhc1_path[] = "/soc/mmc@2140000"; + char esdhc2_path[] = "/soc/mmc@2150000"; + char dspi1_path[] = "/soc/spi@2100000"; + char dspi2_path[] = "/soc/spi@2110000"; + u32 mux_sdhc1, mux_sdhc2; + u32 io = 0; + + /* + * The PMUX IO-expander for mux select is used to control + * the muxing of various onboard interfaces. + */ + + io = in_le32(dcfg_ccsr + DCFG_RCWSR12); + mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK; + + /* Disable esdhc1/dspi1 if not selected. */ + if (mux_sdhc1 != 0) + do_fixup_by_path(blob, esdhc1_path, "status", "disabled", + sizeof("disabled"), 1); + if (mux_sdhc1 != 2) + do_fixup_by_path(blob, dspi1_path, "status", "disabled", + sizeof("disabled"), 1); + + io = in_le32(dcfg_ccsr + DCFG_RCWSR13); + mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK; + + /* Disable esdhc2/dspi2 if not selected. */ + if (mux_sdhc2 != 0) + do_fixup_by_path(blob, esdhc2_path, "status", "disabled", + sizeof("disabled"), 1); + if (mux_sdhc2 != 2) + do_fixup_by_path(blob, dspi2_path, "status", "disabled", + sizeof("disabled"), 1); + + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + ft_cpu_setup(blob, bd); + + /* fixup DT for the two GPP DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + +#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; +#endif + + fdt_fixup_memory_banks(blob, base, size, 2); + + fdt_fixup_icid(blob); + +#ifdef CONFIG_FSL_ENETC + fdt_fixup_enetc_mac(blob); +#endif + + return 0; +} +#endif + +#ifdef CONFIG_FSL_QIXIS +int checkboard(void) +{ +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); +#endif + u8 sw; + + int clock; + char *board; + char buf[64] = {0}; + static const char *freq[6] = {"100.00", "125.00", "156.25", + "161.13", "322.26", "100.00 SS"}; + + cpu_name(buf); + /* find the board details */ + sw = QIXIS_READ(id); + + switch (sw) { + case 0x46: + board = "QDS"; + break; + case 0x47: + board = "RDB"; + break; + case 0x49: + board = "HSSI"; + break; + default: + board = "unknown"; + break; + } + + sw = QIXIS_READ(arch); + printf("Board: %s-%s, Version: %c, boot from ", + buf, board, (sw & 0xf) + 'A' - 1); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + +#ifdef CONFIG_TFABOOT + if (src == BOOT_SOURCE_SD_MMC) { + puts("SD\n"); + } else if (src == BOOT_SOURCE_SD_MMC2) { + puts("eMMC\n"); + } else { +#endif +#ifdef CONFIG_SD_BOOT + puts("SD\n"); +#elif defined(CONFIG_EMMC_BOOT) + puts("eMMC\n"); +#else + switch (sw) { + case 0: + case 4: + printf("NOR\n"); + break; + case 1: + printf("NAND\n"); + break; + default: + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); + break; + } +#endif +#ifdef CONFIG_TFABOOT + } +#endif + + printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board); + puts("SERDES1 Reference : "); + + sw = QIXIS_READ(brdcfg[2]); +#ifdef CONFIG_TARGET_LS1028ARDB + clock = (sw >> 6) & 3; +#else + clock = (sw >> 4) & 0xf; +#endif + + printf("Clock1 = %sMHz ", freq[clock]); +#ifdef CONFIG_TARGET_LS1028ARDB + clock = (sw >> 4) & 3; +#else + clock = sw & 0xf; +#endif + printf("Clock2 = %sMHz\n", freq[clock]); + + return 0; +} +#endif + +void *video_hw_init(void) +{ + return NULL; +} diff --git a/board/nxp/ls1043aqds/Kconfig b/board/nxp/ls1043aqds/Kconfig new file mode 100644 index 00000000000..7261a270f9a --- /dev/null +++ b/board/nxp/ls1043aqds/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1043AQDS + +config SYS_BOARD + default "ls1043aqds" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1043aqds" + +endif diff --git a/board/nxp/ls1043aqds/MAINTAINERS b/board/nxp/ls1043aqds/MAINTAINERS new file mode 100644 index 00000000000..daea64483d2 --- /dev/null +++ b/board/nxp/ls1043aqds/MAINTAINERS @@ -0,0 +1,14 @@ +LS1043AQDS BOARD +M: Mingkai Hu +S: Maintained +F: board/nxp/ls1043aqds/ +F: include/configs/ls1043aqds.h +F: configs/ls1043aqds_defconfig +F: configs/ls1043aqds_nor_ddr3_defconfig +F: configs/ls1043aqds_nand_defconfig +F: configs/ls1043aqds_sdcard_ifc_defconfig +F: configs/ls1043aqds_sdcard_qspi_defconfig +F: configs/ls1043aqds_qspi_defconfig +F: configs/ls1043aqds_lpuart_defconfig +F: configs/ls1043aqds_tfa_defconfig +F: configs/ls1043aqds_tfa_SECURE_BOOT_defconfig diff --git a/board/nxp/ls1043aqds/Makefile b/board/nxp/ls1043aqds/Makefile new file mode 100644 index 00000000000..ff830788fd7 --- /dev/null +++ b/board/nxp/ls1043aqds/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ddr.o +ifndef CONFIG_XPL_BUILD +obj-y += eth.o +endif +obj-y += ls1043aqds.o diff --git a/board/nxp/ls1043aqds/README b/board/nxp/ls1043aqds/README new file mode 100644 index 00000000000..f5aa51da87e --- /dev/null +++ b/board/nxp/ls1043aqds/README @@ -0,0 +1,64 @@ +Overview +-------- +The LS1043A Development System (QDS) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS1043A +LayerScape Architecture processor. The LS1043AQDS provides SW development +platform for the Freescale LS1043A processor series, with a complete +debugging environment. + +LS1043A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A +SoC overview. + + LS1043AQDS board Overview + ----------------------- + - SERDES Connections, 4 lanes supporting: + - PCI Express - 3.0 + - SGMII, SGMII 2.5 + - QSGMII + - SATA 3.0 + - 10GBase-R + - DDR Controller + - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s + -IFC/Local Bus + - One in-socket 128 MB NOR flash 16-bit data bus + - One 512 MB NAND flash with ECC support + - PromJet Port + - FPGA connection + - USB 3.0 + - Three high speed USB 3.0 ports + - First USB 3.0 port configured as Host with Type-A connector + - The other two USB 3.0 ports configured as OTG with micro-AB connector + - SDHC port connects directly to an adapter card slot, featuring: + - Optional clock feedback paths, and optional high-speed voltage translation assistance + - SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC + - eMMC memory devices + - DSPI: Onboard support for three SPI flash memory devices + - 4 I2C controllers + - One SATA onboard connectors + - UART + - Two 4-pin serial ports at up to 115.2 Kbit/s + - Two DB9 D-Type connectors supporting one Serial port each + - ARM JTAG support + +Memory map from core's view +---------------------------- +Start Address End Address Description Size +0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB +0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB +0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB +0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB +0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB + +Booting Options +--------------- +a) Promjet Boot +b) NOR boot +c) NAND boot +d) SD boot +e) QSPI boot diff --git a/board/nxp/ls1043aqds/ddr.c b/board/nxp/ls1043aqds/ddr.c new file mode 100644 index 00000000000..137ad7395ad --- /dev/null +++ b/board/nxp/ls1043aqds/ddr.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#include +#include +#ifdef CONFIG_FSL_DEEP_SLEEP +#include +#endif +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 3) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->cpo_override = pbsp->cpo_override; + popts->write_data_delay = + pbsp->write_data_delay; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + + /* force DDR bus width to 32 bits */ + popts->data_bus_width = 1; + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + popts->bstopre = 0; /* enable auto precharge */ + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 1; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ + + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x59; +#else + popts->cswl_override = DDR_CSWL_CS0; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif +} + +#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} +#else +int fsl_initdram(void) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +#else + puts("Initializing DDR....using SPD\n"); + + dram_size = fsl_ddr_sdram(); +#endif + erratum_a008850_post(); + +#ifdef CONFIG_FSL_DEEP_SLEEP + fsl_dp_ddr_restore(); +#endif + + gd->ram_size = dram_size; + + return 0; +} +#endif diff --git a/board/nxp/ls1043aqds/ddr.h b/board/nxp/ls1043aqds/ddr.h new file mode 100644 index 00000000000..65b0250d370 --- /dev/null +++ b/board/nxp/ls1043aqds/ddr.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __DDR_H__ +#define __DDR_H__ + +extern void erratum_a008850_post(void); + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; + u32 cpo_override; + u32 write_data_delay; + u32 force_2t; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ +#ifdef CONFIG_SYS_FSL_DDR4 + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E0A,}, + {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, + {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,}, +#elif defined(CONFIG_SYS_FSL_DDR3) + {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, +#else +#error DDR type not defined +#endif + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +#endif diff --git a/board/nxp/ls1043aqds/eth.c b/board/nxp/ls1043aqds/eth.c new file mode 100644 index 00000000000..5a8ca27b327 --- /dev/null +++ b/board/nxp/ls1043aqds/eth.c @@ -0,0 +1,501 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/qixis.h" +#include "../common/fman.h" +#include "ls1043aqds_qixis.h" + +#define EMI_NONE 0xFF +#define EMI1_RGMII1 0 +#define EMI1_RGMII2 1 +#define EMI1_SLOT1 2 +#define EMI1_SLOT2 3 +#define EMI1_SLOT3 4 +#define EMI1_SLOT4 5 +#define EMI2 6 + +static const char * const mdio_names[] = { + "LS1043AQDS_MDIO_RGMII1", + "LS1043AQDS_MDIO_RGMII2", + "LS1043AQDS_MDIO_SLOT1", + "LS1043AQDS_MDIO_SLOT2", + "LS1043AQDS_MDIO_SLOT3", + "LS1043AQDS_MDIO_SLOT4", + "NULL", +}; + +/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */ +#ifdef CONFIG_FMAN_ENET +static int mdio_mux[NUM_FM_PORTS]; + +static u8 lane_to_slot[] = {1, 2, 3, 4}; +#endif + +static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name; + + if (muxval > EMI2) + return NULL; + + name = ls1043aqds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +#ifdef CONFIG_FMAN_ENET +struct ls1043aqds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static void ls1043aqds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + + if (muxval < 7) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct ls1043aqds_mdio *priv = bus->priv; + + ls1043aqds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct ls1043aqds_mdio *priv = bus->priv; + + ls1043aqds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, + regnum, value); +} + +static int ls1043aqds_mdio_reset(struct mii_dev *bus) +{ + struct ls1043aqds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int ls1043aqds_mdio_init(char *realbusname, u8 muxval) +{ + struct ls1043aqds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate ls1043aqds MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate ls1043aqds private data\n"); + free(bus); + return -1; + } + + bus->read = ls1043aqds_mdio_read; + bus->write = ls1043aqds_mdio_write; + bus->reset = ls1043aqds_mdio_reset; + strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + return mdio_register(bus); +} + +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + struct fixed_link f_link; + + if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + if (port == FM1_DTSEC9) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii-riser-s1-p1"); + } else if (port == FM1_DTSEC2) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii-riser-s2-p1"); + } else if (port == FM1_DTSEC5) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii-riser-s3-p1"); + } else if (port == FM1_DTSEC6) { + fdt_set_phy_handle(fdt, compat, addr, + "sgmii-riser-s4-p1"); + } + } else if (fm_info_get_enet_if(port) == + PHY_INTERFACE_MODE_2500BASEX) { + /* 2.5G SGMII interface */ + f_link.phy_id = cpu_to_fdt32(port); + f_link.duplex = cpu_to_fdt32(1); + f_link.link_speed = cpu_to_fdt32(1000); + f_link.pause = 0; + f_link.asym_pause = 0; + /* no PHY for 2.5G SGMII */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); + fdt_setprop_string(fdt, offset, "phy-connection-type", + "2500base-x"); + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { + switch (mdio_mux[port]) { + case EMI1_SLOT1: + switch (port) { + case FM1_DTSEC1: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii-s1-p1"); + break; + case FM1_DTSEC2: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii-s1-p2"); + break; + case FM1_DTSEC5: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii-s1-p3"); + break; + case FM1_DTSEC6: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii-s1-p4"); + break; + default: + break; + } + break; + case EMI1_SLOT2: + switch (port) { + case FM1_DTSEC1: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii-s2-p1"); + break; + case FM1_DTSEC2: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii-s2-p2"); + break; + case FM1_DTSEC5: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii-s2-p3"); + break; + case FM1_DTSEC6: + fdt_set_phy_handle(fdt, compat, addr, + "qsgmii-s2-p4"); + break; + default: + break; + } + break; + default: + break; + } + fdt_delprop(fdt, offset, "phy-connection-type"); + fdt_setprop_string(fdt, offset, "phy-connection-type", + "qsgmii"); + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && + port == FM1_10GEC1) { + /* 10GBase-R interface */ + f_link.phy_id = cpu_to_fdt32(port); + f_link.duplex = cpu_to_fdt32(1); + f_link.link_speed = cpu_to_fdt32(10000); + f_link.pause = 0; + f_link.asym_pause = 0; + /* no PHY for 10GBase-R */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); + fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + int i; + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + switch (mdio_mux[i]) { + case EMI1_SLOT1: + fdt_status_okay_by_alias(fdt, "emi1-slot1"); + break; + case EMI1_SLOT2: + fdt_status_okay_by_alias(fdt, "emi1-slot2"); + break; + case EMI1_SLOT3: + fdt_status_okay_by_alias(fdt, "emi1-slot3"); + break; + case EMI1_SLOT4: + fdt_status_okay_by_alias(fdt, "emi1-slot4"); + break; + default: + break; + } + break; + case PHY_INTERFACE_MODE_XGMII: + break; + default: + break; + } + } +} + +int board_eth_init(struct bd_info *bis) +{ + int i, idx, lane, slot, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Register the muxing front-ends to the MDIO buses */ + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); + ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); + ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); + + switch (srds_s1) { + case 0x2555: + /* 2.5G SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, 9); + break; + case 0x4555: + case 0x4558: + /* QSGMII on lane A, MAC 1/2/5/6 */ + fm_info_set_phy_address(FM1_DTSEC1, + QSGMII_CARD_PORT1_PHY_ADDR_S1); + fm_info_set_phy_address(FM1_DTSEC2, + QSGMII_CARD_PORT2_PHY_ADDR_S1); + fm_info_set_phy_address(FM1_DTSEC5, + QSGMII_CARD_PORT3_PHY_ADDR_S1); + fm_info_set_phy_address(FM1_DTSEC6, + QSGMII_CARD_PORT4_PHY_ADDR_S1); + break; + case 0x1355: + /* SGMII on lane B, MAC 2*/ + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x2355: + /* 2.5G SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, 9); + /* SGMII on lane B, MAC 2*/ + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x3335: + /* SGMII on lane C, MAC 5 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); + case 0x3355: + case 0x3358: + /* SGMII on lane B, MAC 2 */ + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + case 0x3555: + case 0x3558: + /* SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + break; + case 0x1455: + /* QSGMII on lane B, MAC 1/2/5/6 */ + fm_info_set_phy_address(FM1_DTSEC1, + QSGMII_CARD_PORT1_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC2, + QSGMII_CARD_PORT2_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC5, + QSGMII_CARD_PORT3_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC6, + QSGMII_CARD_PORT4_PHY_ADDR_S2); + break; + case 0x2455: + /* 2.5G SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, 9); + /* QSGMII on lane B, MAC 1/2/5/6 */ + fm_info_set_phy_address(FM1_DTSEC1, + QSGMII_CARD_PORT1_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC2, + QSGMII_CARD_PORT2_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC5, + QSGMII_CARD_PORT3_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC6, + QSGMII_CARD_PORT4_PHY_ADDR_S2); + break; + case 0x2255: + /* 2.5G SGMII on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, 9); + /* 2.5G SGMII on lane B, MAC 2 */ + fm_info_set_phy_address(FM1_DTSEC2, 2); + break; + case 0x3333: + /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */ + fm_info_set_phy_address(FM1_DTSEC9, + SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, + SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, + SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, + SGMII_CARD_PORT1_PHY_ADDR); + break; + default: + printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n", + srds_s1); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_QSGMII: + if (interface == PHY_INTERFACE_MODE_SGMII) { + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + } else if (interface == PHY_INTERFACE_MODE_2500BASEX) { + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_2500_FM1_DTSEC1 + idx); + } else { + lane = serdes_get_first_lane(FSL_SRDS_1, + QSGMII_FM1_A); + } + + if (lane < 0) + break; + + slot = lane_to_slot[lane]; + debug("FM1@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 4: + mdio_mux[i] = EMI1_SLOT4; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + default: + break; + } + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: + if (i == FM1_DTSEC3) + mdio_mux[i] = EMI1_RGMII1; + else if (i == FM1_DTSEC4) + mdio_mux[i] = EMI1_RGMII2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + cpu_eth_init(bis); + + return pci_eth_init(bis); +} +#endif /* CONFIG_FMAN_ENET */ diff --git a/board/nxp/ls1043aqds/ls1043aqds.c b/board/nxp/ls1043aqds/ls1043aqds.c new file mode 100644 index 00000000000..f043599fbb8 --- /dev/null +++ b/board/nxp/ls1043aqds/ls1043aqds.c @@ -0,0 +1,595 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2019-2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/i2c_mux.h" + +#include "../common/qixis.h" +#include "ls1043aqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +enum { + MUX_TYPE_GPIO, +}; + +/* LS1043AQDS serdes mux */ +#define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */ +#define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */ +#define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */ +#define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */ +#define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */ +#define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */ +#define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */ +#define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */ +#define CFG_UART_MUX_MASK 0x6 +#define CFG_UART_MUX_SHIFT 1 +#define CFG_LPUART_EN 0x1 + +#ifdef CONFIG_TFABOOT +struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nor0", + CFG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, + { + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 + }, + + }, + { + "nor1", + CFG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR_EXT, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, + { + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 + }, + }, + { + "nand", + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, + { + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 + }, + }, + { + "fpga", + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, + { + CFG_SYS_FPGA_FTIM0, + CFG_SYS_FPGA_FTIM1, + CFG_SYS_FPGA_FTIM2, + CFG_SYS_FPGA_FTIM3 + }, + } +}; + +struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nand", + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, + { + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 + }, + }, + { + "nor0", + CFG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, + { + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 + }, + }, + { + "nor1", + CFG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR_EXT, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, + { + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 + }, + }, + { + "fpga", + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, + { + CFG_SYS_FPGA_FTIM0, + CFG_SYS_FPGA_FTIM1, + CFG_SYS_FPGA_FTIM2, + CFG_SYS_FPGA_FTIM3 + }, + } +}; + +void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) +{ + enum boot_src src = get_boot_src(); + + if (src == BOOT_SOURCE_IFC_NAND) + regs_info->regs = ifc_cfg_nand_boot; + else + regs_info->regs = ifc_cfg_nor_boot; + regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; +} +#endif + +int checkboard(void) +{ +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); +#endif + char buf[64]; +#ifndef CONFIG_SD_BOOT + u8 sw; +#endif + + puts("Board: LS1043AQDS, boot from "); + +#ifdef CONFIG_TFABOOT + if (src == BOOT_SOURCE_SD_MMC) + puts("SD\n"); + else { +#endif + +#ifdef CONFIG_SD_BOOT + puts("SD\n"); +#else + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("PromJet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else if (sw == 0xF) + printf("QSPI\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); +#endif + +#ifdef CONFIG_TFABOOT + } +#endif + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", + QIXIS_READ(id), QIXIS_READ(arch)); + + printf("FPGA: v%d (%s), build %d\n", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + + return 0; +} + +bool if_board_diff_clk(void) +{ + u8 diff_conf = QIXIS_READ(brdcfg[11]); + + return diff_conf & 0x40; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0f) { + case QIXIS_SYSCLK_64: + return 64000000; + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + if (if_board_diff_clk()) + return get_board_sys_clk(); + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + + return 66666666; +} + +int dram_init(void) +{ + /* + * When resuming from deep sleep, the I2C channel may not be + * in the default channel. So, switch to the default channel + * before accessing DDR SPD. + * + * PCA9547 mount on I2C1 bus + */ + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); + fsl_initdram(); +#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ + defined(CONFIG_XPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif + + return 0; +} + +int i2c_multiplexer_select_vid_channel(u8 channel) +{ + return select_i2c_ch_pca9547(channel, 0); +} + +void board_retimer_init(void) +{ + u8 reg; + int bus_num = 0; + + /* Retimer is connected to I2C1_CH7_CH5 */ + select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num); + reg = I2C_MUX_CH5; +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return; + } + dm_i2c_write(dev, 0, ®, 1); + + /* Access to Control/Shared register */ + ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return; + } + + reg = 0x0; + dm_i2c_write(dev, 0xff, ®, 1); + + /* Read device revision and ID */ + dm_i2c_read(dev, 1, ®, 1); + debug("Retimer version id = 0x%x\n", reg); + + /* Enable Broadcast. All writes target all channel register sets */ + reg = 0x0c; + dm_i2c_write(dev, 0xff, ®, 1); + + /* Reset Channel Registers */ + dm_i2c_read(dev, 0, ®, 1); + reg |= 0x4; + dm_i2c_write(dev, 0, ®, 1); + + /* Enable override divider select and Enable Override Output Mux */ + dm_i2c_read(dev, 9, ®, 1); + reg |= 0x24; + dm_i2c_write(dev, 9, ®, 1); + + /* Select VCO Divider to full rate (000) */ + dm_i2c_read(dev, 0x18, ®, 1); + reg &= 0x8f; + dm_i2c_write(dev, 0x18, ®, 1); + + /* Selects active PFD MUX Input as Re-timed Data (001) */ + dm_i2c_read(dev, 0x1e, ®, 1); + reg &= 0x3f; + reg |= 0x20; + dm_i2c_write(dev, 0x1e, ®, 1); + + /* Set data rate as 10.3125 Gbps */ + reg = 0x0; + dm_i2c_write(dev, 0x60, ®, 1); + reg = 0xb2; + dm_i2c_write(dev, 0x61, ®, 1); + reg = 0x90; + dm_i2c_write(dev, 0x62, ®, 1); + reg = 0xb3; + dm_i2c_write(dev, 0x63, ®, 1); + reg = 0xcd; + dm_i2c_write(dev, 0x64, ®, 1); +#else + i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); + + /* Access to Control/Shared register */ + reg = 0x0; + i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); + + /* Read device revision and ID */ + i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); + debug("Retimer version id = 0x%x\n", reg); + + /* Enable Broadcast. All writes target all channel register sets */ + reg = 0x0c; + i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); + + /* Reset Channel Registers */ + i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); + reg |= 0x4; + i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); + + /* Enable override divider select and Enable Override Output Mux */ + i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1); + reg |= 0x24; + i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1); + + /* Select VCO Divider to full rate (000) */ + i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); + reg &= 0x8f; + i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); + + /* Selects active PFD MUX Input as Re-timed Data (001) */ + i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); + reg &= 0x3f; + reg |= 0x20; + i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); + + /* Set data rate as 10.3125 Gbps */ + reg = 0x0; + i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); + reg = 0xb2; + i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); + reg = 0x90; + i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); + reg = 0xb3; + i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); + reg = 0xcd; + i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); +#endif + + /* Return the default channel */ + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num); +} + +int board_early_init_f(void) +{ + u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR; +#ifdef CONFIG_HAS_FSL_XHCI_USB + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; + u32 usb_pwrfault; +#endif +#ifdef CONFIG_LPUART + u8 uart; +#endif + + /* + * Enable secure system counter for timer + */ + out_le32(cntcr, 0x1); + +#if defined(CONFIG_SYS_I2C_EARLY_INIT) + i2c_early_init_f(); +#endif + fsl_lsch2_early_init_f(); + +#ifdef CONFIG_HAS_FSL_XHCI_USB + out_be32(&scfg->rcwpmuxcr0, 0x3333); + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); + usb_pwrfault = + (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT); + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); +#endif + +#ifdef CONFIG_LPUART + /* We use lpuart0 as system console */ + uart = QIXIS_READ(brdcfg[14]); + uart &= ~CFG_UART_MUX_MASK; + uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; + QIXIS_WRITE(brdcfg[14], uart); +#endif + + return 0; +} + +#ifdef CONFIG_FSL_DEEP_SLEEP +/* determine if it is a warm boot */ +bool is_warm_boot(void) +{ +#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; + + if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) + return 1; + + return 0; +} +#endif + +int config_board_mux(int ctrl_type) +{ + u8 reg14; + + reg14 = QIXIS_READ(brdcfg[14]); + + switch (ctrl_type) { + case MUX_TYPE_GPIO: + reg14 = (reg14 & (~0x30)) | 0x20; + break; + default: + puts("Unsupported mux interface type\n"); + return -1; + } + + QIXIS_WRITE(brdcfg[14], reg14); + + return 0; +} + +int config_serdes_mux(void) +{ + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + if (hwconfig("gpio")) + config_board_mux(MUX_TYPE_GPIO); + + return 0; +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); + board_retimer_init(); + +#ifdef CFG_SYS_FSL_SERDES + config_serdes_mux(); +#endif + + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + u8 reg; + + /* fixup DT for the two DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_FMAN_ENET + fdt_fixup_board_enet(blob); +#endif + + fdt_fixup_icid(blob); + + reg = QIXIS_READ(brdcfg[0]); + reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + /* Disable IFC if QSPI is enabled */ + if (reg == 0xF) + do_fixup_by_compat(blob, "fsl,ifc", + "status", "disabled", 8 + 1, 1); + + return 0; +} +#endif + +u8 flash_read8(void *addr) +{ + return __raw_readb(addr + 1); +} + +void flash_write16(u16 val, void *addr) +{ + u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); + + __raw_writew(shftval, addr); +} + +u16 flash_read16(void *addr) +{ + u16 val = __raw_readw(addr); + + return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); +} + +#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) +void *env_sf_get_env_addr(void) +{ + return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); +} +#endif diff --git a/board/nxp/ls1043aqds/ls1043aqds_pbi.cfg b/board/nxp/ls1043aqds/ls1043aqds_pbi.cfg new file mode 100644 index 00000000000..f072274f474 --- /dev/null +++ b/board/nxp/ls1043aqds/ls1043aqds_pbi.cfg @@ -0,0 +1,14 @@ +#Configure Scratch register +09570600 00000000 +09570604 10000000 +#Alt base register +09570158 00001000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009e +0957041c 0000009e +09570420 0000009e +#flush PBI data +096100c0 000fffff diff --git a/board/nxp/ls1043aqds/ls1043aqds_qixis.h b/board/nxp/ls1043aqds/ls1043aqds_qixis.h new file mode 100644 index 00000000000..bba494ae413 --- /dev/null +++ b/board/nxp/ls1043aqds/ls1043aqds_qixis.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __LS1043AQDS_QIXIS_H__ +#define __LS1043AQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for LS1043AQDS */ + +/* BRDCFG4[4:7] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xe0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 +#define QIXIS_SYSCLK_64 0x8 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +/* BRDCFG2 - SD clock*/ +#define QIXIS_SDCLK1_100 0x0 +#define QIXIS_SDCLK1_125 0x1 +#define QIXIS_SDCLK1_165 0x2 +#define QIXIS_SDCLK1_100_SP 0x3 + +#endif diff --git a/board/nxp/ls1043aqds/ls1043aqds_rcw_nand.cfg b/board/nxp/ls1043aqds/ls1043aqds_rcw_nand.cfg new file mode 100644 index 00000000000..d87058b7efe --- /dev/null +++ b/board/nxp/ls1043aqds/ls1043aqds_rcw_nand.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# serdes protocol +08100010 0a000000 00000000 00000000 +14550002 80004012 e0106000 c1002000 +00000000 00000000 00000000 00038800 +00000000 00001100 00000096 00000001 diff --git a/board/nxp/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg b/board/nxp/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg new file mode 100644 index 00000000000..b6b5e0b1018 --- /dev/null +++ b/board/nxp/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +# Enable IFC; disable QSPI +08100010 0a000000 00000000 00000000 +14550002 80004012 60040000 c1002000 +00000000 00000000 00000000 00038800 +00000000 00001100 00000096 00000001 diff --git a/board/nxp/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg b/board/nxp/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg new file mode 100644 index 00000000000..7783521b95b --- /dev/null +++ b/board/nxp/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +# Enable QSPI; disable IFC +08100010 0a000000 00000000 00000000 +14550002 80004012 60040000 c1002000 +00000000 00000000 00000000 00038800 +20124000 00001100 00000096 00000001 diff --git a/board/nxp/ls1043ardb/Kconfig b/board/nxp/ls1043ardb/Kconfig new file mode 100644 index 00000000000..92b55496c62 --- /dev/null +++ b/board/nxp/ls1043ardb/Kconfig @@ -0,0 +1,16 @@ + +if TARGET_LS1043ARDB + +config SYS_BOARD + default "ls1043ardb" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1043ardb" + +endif diff --git a/board/nxp/ls1043ardb/MAINTAINERS b/board/nxp/ls1043ardb/MAINTAINERS new file mode 100644 index 00000000000..4df5940ab71 --- /dev/null +++ b/board/nxp/ls1043ardb/MAINTAINERS @@ -0,0 +1,13 @@ +LS1043A BOARD +M: Mingkai Hu +S: Maintained +F: board/nxp/ls1043ardb/ +F: include/configs/ls1043ardb.h +F: configs/ls1043ardb_defconfig +F: configs/ls1043ardb_nand_defconfig +F: configs/ls1043ardb_sdcard_defconfig +F: configs/ls1043ardb_tfa_defconfig +F: configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +F: configs/ls1043ardb_SECURE_BOOT_defconfig +F: configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +F: configs/ls1043ardb_nand_SECURE_BOOT_defconfig diff --git a/board/nxp/ls1043ardb/Makefile b/board/nxp/ls1043ardb/Makefile new file mode 100644 index 00000000000..95745bf3a9c --- /dev/null +++ b/board/nxp/ls1043ardb/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2015 Freescale Semiconductor + +obj-y += ddr.o +obj-y += ls1043ardb.o +ifndef CONFIG_XPL_BUILD +obj-$(CONFIG_NET) += eth.o +obj-y += cpld.o +endif diff --git a/board/nxp/ls1043ardb/README b/board/nxp/ls1043ardb/README new file mode 100644 index 00000000000..66ee578e99d --- /dev/null +++ b/board/nxp/ls1043ardb/README @@ -0,0 +1,54 @@ +Overview +-------- +The LS1043A Reference Design Board (RDB) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS1043A +LayerScape Architecture processor. The LS1043ARDB provides SW development +platform for the Freescale LS1043A processor series, with a complete +debugging environment. The LS1043A RDB is lead-free and RoHS-compliant. + +LS1043A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A +SoC overview. + + LS1043ARDB board Overview + ----------------------- + - SERDES Connections, 4 lanes supporting: + - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and + standard PCIe card + - QSGMII with x4 RJ45 connector + - 10GBase-R with x1 RJ45 connector + - DDR Controller + - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s + -IFC/Local Bus + - One 128MB NOR flash 16-bit data bus + - One 512 MB NAND flash with ECC support + - CPLD connection + - USB 3.0 + - Two super speed USB 3.0 Type A ports + - SDHC: connects directly to a full SD/MMC slot + - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz) + - 4 I2C controllers + - UART + - Two 4-pin serial ports at up to 115.2 Kbit/s + - Two DB9 D-Type connectors supporting one Serial port each + - ARM JTAG support + +Memory map from core's view +---------------------------- +Start Address End Address Description Size +0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB +0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB +0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB +0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB +0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB + +Booting Options +--------------- +a) NOR boot +b) NAND boot +c) SD boot diff --git a/board/nxp/ls1043ardb/cpld.c b/board/nxp/ls1043ardb/cpld.c new file mode 100644 index 00000000000..39b6c6449cf --- /dev/null +++ b/board/nxp/ls1043ardb/cpld.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Freescale Semiconductor + * + * Freescale LS1043ARDB board-specific CPLD controlling supports. + */ + +#include +#include +#include +#include +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CFG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CFG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/* Set the boot bank to the alternate bank */ +void cpld_set_altbank(void) +{ + u16 reg = CPLD_CFG_RCW_SRC_NOR; + u8 reg4 = CPLD_READ(soft_mux_on); + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); + u8 reg7 = CPLD_READ(vbank); + + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); + + reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; + CPLD_WRITE(vbank, reg7); + + CPLD_WRITE(system_rst, 1); +} + +/* Set the boot bank to the default bank */ +void cpld_set_defbank(void) +{ + u16 reg = CPLD_CFG_RCW_SRC_NOR; + u8 reg4 = CPLD_READ(soft_mux_on); + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); + + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); + + CPLD_WRITE(vbank, 0); + + CPLD_WRITE(system_rst, 1); +} + +void cpld_set_nand(void) +{ + u16 reg = CPLD_CFG_RCW_SRC_NAND; + + if (CPLD_READ(cpld_ver) > 0x2) + reg = CPLD_CFG_RCW_SRC_NAND_4K; + + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); + + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); + + CPLD_WRITE(system_rst, 1); +} + +void cpld_set_sd(void) +{ + u16 reg = CPLD_CFG_RCW_SRC_SD; + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); + + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); + + CPLD_WRITE(system_rst, 1); +} +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("cpld_ver = %x\n", CPLD_READ(cpld_ver)); + printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub)); + printf("pcba_ver = %x\n", CPLD_READ(pcba_ver)); + printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on)); + printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1)); + printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2)); + printf("vbank = %x\n", CPLD_READ(vbank)); + printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel)); + printf("uart_sel = %x\n", CPLD_READ(uart_sel)); + printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel)); + printf("tdmclk_mux_sel = %x\n", CPLD_READ(tdmclk_mux_sel)); + printf("sdhc_spics_sel = %x\n", CPLD_READ(sdhc_spics_sel)); + printf("status_led = %x\n", CPLD_READ(status_led)); + putc('\n'); +} +#endif + +void cpld_rev_bit(unsigned char *value) +{ + u8 rev_val, val; + int i; + + val = *value; + rev_val = val & 1; + for (i = 1; i <= 7; i++) { + val >>= 1; + rev_val <<= 1; + rev_val |= val & 1; + } + + *value = rev_val; +} + +int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else if (strcmp(argv[2], "nand") == 0) + cpld_set_nand(); + else if (strcmp(argv[2], "sd") == 0) + cpld_set_sd(); + else + cpld_set_defbank(); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else { + rc = cmd_usage(cmdtp); + } + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset: reset to default bank\n" + "cpld reset altbank: reset to alternate bank\n" + "cpld reset nand: reset to boot from NAND flash\n" + "cpld reset sd: reset to boot from SD card\n" +#ifdef DEBUG + "cpld dump - display the CPLD registers\n" +#endif +); diff --git a/board/nxp/ls1043ardb/cpld.h b/board/nxp/ls1043ardb/cpld.h new file mode 100644 index 00000000000..eed34d63546 --- /dev/null +++ b/board/nxp/ls1043ardb/cpld.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor + */ + +#ifndef __CPLD_H__ +#define __CPLD_H__ + +/* + * CPLD register set of LS1043ARDB board-specific. + */ +struct cpld_data { + u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ + u8 pcba_ver; /* 0x2 - PCBA Revision Register */ + u8 system_rst; /* 0x3 - system reset register */ + u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */ + u8 cfg_rcw_src1; /* 0x5 - Reset config word 1 */ + u8 cfg_rcw_src2; /* 0x6 - Reset config word 1 */ + u8 vbank; /* 0x7 - Flash bank selection Control */ + u8 sysclk_sel; /* 0x8 - */ + u8 uart_sel; /* 0x9 - */ + u8 sd1refclk_sel; /* 0xA - */ + u8 tdmclk_mux_sel; /* 0xB - */ + u8 sdhc_spics_sel; /* 0xC - */ + u8 status_led; /* 0xD - */ + u8 global_rst; /* 0xE - */ +}; + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); +void cpld_rev_bit(unsigned char *value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value) \ + cpld_write(offsetof(struct cpld_data, reg), value) + +/* CPLD on IFC */ +#define CPLD_SW_MUX_BANK_SEL 0x40 +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_SEL_ALTBANK 0x04 +#define CPLD_CFG_RCW_SRC_NOR 0x025 +#define CPLD_CFG_RCW_SRC_NAND 0x106 +#define CPLD_CFG_RCW_SRC_NAND_4K 0x118 +#define CPLD_CFG_RCW_SRC_SD 0x040 +#endif diff --git a/board/nxp/ls1043ardb/ddr.c b/board/nxp/ls1043ardb/ddr.c new file mode 100644 index 00000000000..231b60d1b3d --- /dev/null +++ b/board/nxp/ls1043ardb/ddr.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include "ddr.h" +#include +#include +#ifdef CONFIG_FSL_DEEP_SLEEP +#include +#endif +#include + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->cpo_override = pbsp->cpo_override; + popts->write_data_delay = + pbsp->write_data_delay; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + + /* force DDR bus width to 32 bits */ + popts->data_bus_width = 1; + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 1; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x46; + + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +} + +/* DDR model number: MT40A512M8HX-093E */ +#ifdef CONFIG_SYS_DDR_RAW_TIMING +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 2147483648u, + .capacity = 2147483648u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .bank_addr_bits = 2, + .bank_group_bits = 2, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 938, + .tckmax_ps = 1500, + .caslat_x = 0x000DFA00, + .taa_ps = 13500, + .trcd_ps = 13500, + .trp_ps = 13500, + .tras_ps = 33000, + .trc_ps = 46500, + .trfc1_ps = 260000, + .trfc2_ps = 160000, + .trfc4_ps = 110000, + .tfaw_ps = 21000, + .trrds_ps = 3700, + .trrdl_ps = 5300, + .tccdl_ps = 5355, + .refresh_rate_ps = 7800000, + .dq_mapping[0] = 0x0, + .dq_mapping[1] = 0x0, + .dq_mapping[2] = 0x0, + .dq_mapping[3] = 0x0, + .dq_mapping[4] = 0x0, + .dq_mapping[5] = 0x0, + .dq_mapping[6] = 0x0, + .dq_mapping[7] = 0x0, + .dq_mapping[8] = 0x0, + .dq_mapping[9] = 0x0, + .dq_mapping[10] = 0x0, + .dq_mapping[11] = 0x0, + .dq_mapping[12] = 0x0, + .dq_mapping[13] = 0x0, + .dq_mapping[14] = 0x0, + .dq_mapping[15] = 0x0, + .dq_mapping[16] = 0x0, + .dq_mapping[17] = 0x0, + .dq_mapping_ors = 0, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + static const char dimm_model[] = "Fixed DDR on board"; + + if (((controller_number == 0) && (dimm_number == 0)) || + ((controller_number == 1) && (dimm_number == 0))) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} +#else + +phys_size_t fixed_sdram(void) +{ + int i; + char buf[32]; + fsl_ddr_cfg_regs_t ddr_cfg_regs; + phys_size_t ddr_size; + ulong ddr_freq, ddr_freq_mhz; + + ddr_freq = get_ddr_freq(0); + ddr_freq_mhz = ddr_freq / 1000000; + + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { + if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && + (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { + memcpy(&ddr_cfg_regs, + fixed_ddr_parm_0[i].ddr_settings, + sizeof(ddr_cfg_regs)); + break; + } + } + + if (fixed_ddr_parm_0[i].max_freq == 0) + panic("Unsupported DDR data rate %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + ddr_size = (phys_size_t)2048 * 1024 * 1024; + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); + + return ddr_size; +} +#endif + +#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) +#ifdef CONFIG_SYS_DDR_RAW_TIMING + gd->ram_size = fsl_ddr_sdram_size(); +#else + gd->ram_size = 0x80000000; +#endif + return 0; +} +#else +int fsl_initdram(void) +{ + phys_size_t dram_size; + +#ifdef CONFIG_SYS_DDR_RAW_TIMING +#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_SPL) + puts("Initializing DDR....\n"); + dram_size = fsl_ddr_sdram(); +#else + dram_size = fsl_ddr_sdram_size(); +#endif +#else +#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_SPL) + puts("Initialzing DDR using fixed setting\n"); + dram_size = fixed_sdram(); +#else + gd->ram_size = 0x80000000; + + return 0; +#endif +#endif + erratum_a008850_post(); + +#ifdef CONFIG_FSL_DEEP_SLEEP + fsl_dp_ddr_restore(); +#endif + + gd->ram_size = dram_size; + + return 0; +} +#endif diff --git a/board/nxp/ls1043ardb/ddr.h b/board/nxp/ls1043ardb/ddr.h new file mode 100644 index 00000000000..85ed920ca6d --- /dev/null +++ b/board/nxp/ls1043ardb/ddr.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __DDR_H__ +#define __DDR_H__ + +extern void erratum_a008850_post(void); + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; + u32 cpo_override; + u32 write_data_delay; + u32 force_2t; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ +#ifdef CONFIG_SYS_FSL_DDR4 + {1, 1666, 0, 12, 7, 0x07090800, 0x00000000,}, + {1, 1900, 0, 12, 7, 0x07090800, 0x00000000,}, + {1, 2200, 0, 12, 7, 0x07090800, 0x00000000,}, +#endif + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +#ifndef CONFIG_SYS_DDR_RAW_TIMING +fsl_ddr_cfg_regs_t ddr_cfg_regs_1600 = { + .cs[0].bnds = 0x0000007F, + .cs[1].bnds = 0, + .cs[2].bnds = 0, + .cs[3].bnds = 0, + .cs[0].config = 0x80040322, + .cs[0].config_2 = 0, + .cs[1].config = 0, + .cs[1].config_2 = 0, + .cs[2].config = 0, + .cs[3].config = 0, + .timing_cfg_3 = 0x010C1000, + .timing_cfg_0 = 0x91550018, + .timing_cfg_1 = 0xBBB48C42, + .timing_cfg_2 = 0x0048C111, + .ddr_sdram_cfg = 0xC50C0008, + .ddr_sdram_cfg_2 = 0x00401100, + .ddr_sdram_cfg_3 = 0, + .ddr_sdram_mode = 0x03010210, + .ddr_sdram_mode_2 = 0, + .ddr_sdram_mode_3 = 0x00010210, + .ddr_sdram_mode_4 = 0, + .ddr_sdram_mode_5 = 0x00010210, + .ddr_sdram_mode_6 = 0, + .ddr_sdram_mode_7 = 0x00010210, + .ddr_sdram_mode_8 = 0, + .ddr_sdram_mode_9 = 0x00000500, + .ddr_sdram_mode_10 = 0x04000000, + .ddr_sdram_mode_11 = 0x00000400, + .ddr_sdram_mode_12 = 0x04000000, + .ddr_sdram_mode_13 = 0x00000400, + .ddr_sdram_mode_14 = 0x04000000, + .ddr_sdram_mode_15 = 0x00000400, + .ddr_sdram_mode_16 = 0x04000000, + .ddr_sdram_interval = 0x18600618, + .ddr_data_init = 0xDEADBEEF, + .ddr_sdram_clk_cntl = 0x03000000, + .ddr_init_addr = 0, + .ddr_init_ext_addr = 0, + .timing_cfg_4 = 0x00000002, + .timing_cfg_5 = 0x03401400, + .timing_cfg_6 = 0, + .timing_cfg_7 = 0x13300000, + .timing_cfg_8 = 0x02115600, + .timing_cfg_9 = 0, + .ddr_zq_cntl = 0x8A090705, + .ddr_wrlvl_cntl = 0x8675F607, + .ddr_wrlvl_cntl_2 = 0x07090800, + .ddr_wrlvl_cntl_3 = 0, + .ddr_sr_cntr = 0, + .ddr_sdram_rcw_1 = 0, + .ddr_sdram_rcw_2 = 0, + .ddr_cdr1 = 0x80040000, + .ddr_cdr2 = 0x0000A181, + .dq_map_0 = 0, + .dq_map_1 = 0, + .dq_map_2 = 0, + .dq_map_3 = 0, + .debug[28] = 0x00700046, + +}; + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {1550, 1650, &ddr_cfg_regs_1600}, + {0, 0, NULL} +}; + +#endif +#endif diff --git a/board/nxp/ls1043ardb/eth.c b/board/nxp/ls1043ardb/eth.c new file mode 100644 index 00000000000..cacc49c0584 --- /dev/null +++ b/board/nxp/ls1043ardb/eth.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/fman.h" + +int board_eth_init(struct bd_info *bis) +{ +#ifdef CONFIG_FMAN_ENET + int i; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + struct mii_dev *dev; + u32 srds_s1; + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); + + /* QSGMII on lane B, MAC 1/2/5/6 */ + fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR); + + switch (srds_s1) { + case 0x1455: + break; + default: + printf("Invalid SerDes protocol 0x%x for LS1043ARDB\n", + srds_s1); + break; + } + + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) + fm_info_set_mdio(i, dev); + + /* 10GBase-R on lane A, MAC 9 */ + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(FM1_10GEC1, dev); + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} diff --git a/board/nxp/ls1043ardb/ls1043ardb.c b/board/nxp/ls1043ardb/ls1043ardb.c new file mode 100644 index 00000000000..bba041065b5 --- /dev/null +++ b/board/nxp/ls1043ardb/ls1043ardb.c @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2021-2022 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cpld.h" +#ifdef CONFIG_U_QE +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_TFABOOT +struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nor", + CFG_SYS_NOR_CSPR, + CFG_SYS_NOR_CSPR_EXT, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, + { + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 + }, + + }, + { + "nand", + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, + { + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 + }, + }, + { + "cpld", + CFG_SYS_CPLD_CSPR, + CFG_SYS_CPLD_CSPR_EXT, + CFG_SYS_CPLD_AMASK, + CFG_SYS_CPLD_CSOR, + { + CFG_SYS_CPLD_FTIM0, + CFG_SYS_CPLD_FTIM1, + CFG_SYS_CPLD_FTIM2, + CFG_SYS_CPLD_FTIM3 + }, + } +}; + +struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nand", + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, + { + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 + }, + }, + { + "nor", + CFG_SYS_NOR_CSPR, + CFG_SYS_NOR_CSPR_EXT, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, + { + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 + }, + }, + { + "cpld", + CFG_SYS_CPLD_CSPR, + CFG_SYS_CPLD_CSPR_EXT, + CFG_SYS_CPLD_AMASK, + CFG_SYS_CPLD_CSOR, + { + CFG_SYS_CPLD_FTIM0, + CFG_SYS_CPLD_FTIM1, + CFG_SYS_CPLD_FTIM2, + CFG_SYS_CPLD_FTIM3 + }, + } +}; + +void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) +{ + enum boot_src src = get_boot_src(); + + if (src == BOOT_SOURCE_IFC_NAND) + regs_info->regs = ifc_cfg_nand_boot; + else + regs_info->regs = ifc_cfg_nor_boot; + regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; +} + +#endif +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +#ifndef CONFIG_XPL_BUILD + +int checkboard(void) +{ +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); +#endif + static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; +#ifndef CONFIG_SD_BOOT + u8 cfg_rcw_src1, cfg_rcw_src2; + u16 cfg_rcw_src; +#endif + u8 sd1refclk_sel; + + printf("Board: LS1043ARDB, boot from "); + +#ifdef CONFIG_TFABOOT + if (src == BOOT_SOURCE_SD_MMC) + puts("SD\n"); + else { +#endif + +#ifdef CONFIG_SD_BOOT + puts("SD\n"); +#else + cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); + cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); + cpld_rev_bit(&cfg_rcw_src1); + cfg_rcw_src = cfg_rcw_src1; + cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; + + if (cfg_rcw_src == 0x25) + printf("vBank %d\n", CPLD_READ(vbank)); + else if ((cfg_rcw_src == 0x106) || (cfg_rcw_src == 0x118)) + puts("NAND\n"); + else + printf("Invalid setting of SW4\n"); +#endif + +#ifdef CONFIG_TFABOOT + } +#endif + printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), + CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); + + puts("SERDES Reference Clocks:\n"); + sd1refclk_sel = CPLD_READ(sd1refclk_sel); + printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); + + return 0; +} + +int board_init(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 + erratum_a010315(); +#endif + +#ifdef CONFIG_FSL_IFC + init_final_memctl_regs(); +#endif + +#ifdef CONFIG_NXP_ESBC + /* In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + u32 val; + val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +#endif + +#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) + pci_init(); +#endif + +#ifdef CONFIG_U_QE + u_qe_init(); +#endif + /* invert AQR105 IRQ pins polarity */ + out_be32(&scfg->intpcr, AQR105_IRQ_MASK); + + return 0; +} + +int config_board_mux(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; + u32 usb_pwrfault; + + if (hwconfig("qe-hdlc")) { + out_be32(&scfg->rcwpmuxcr0, + (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600); + printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n", + in_be32(&scfg->rcwpmuxcr0)); + } else { +#ifdef CONFIG_HAS_FSL_XHCI_USB + out_be32(&scfg->rcwpmuxcr0, 0x3333); + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); + usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << + SCFG_USBPWRFAULT_USB1_SHIFT); + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); +#endif + } + return 0; +} + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ + config_board_mux(); + return 0; +} +#endif + +void fdt_del_qe(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "fsl,qe")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} + +/* Update the address of the Aquantia PHY on the MDIO bus for boards revision + * v7.0 and up. Also rename the PHY node to align with the address change. + */ +void fdt_fixup_phy_addr(void *blob) +{ + const char phy_path[] = + "/soc/fman@1a00000/mdio@fd000/ethernet-phy@1"; + int ret, offset, new_addr = AQR113C_PHY_ADDR; + char new_name[] = "ethernet-phy@00"; + + if (CPLD_READ(pcba_ver) < 0x7) + return; + + offset = fdt_path_offset(blob, phy_path); + if (offset < 0) { + printf("ethernet-phy@1 node not found in the dts\n"); + return; + } + + ret = fdt_setprop_u32(blob, offset, "reg", new_addr); + if (ret < 0) { + printf("Unable to set 'reg' for node ethernet-phy@1: %s\n", + fdt_strerror(ret)); + return; + } + + sprintf(new_name, "ethernet-phy@%x", new_addr); + ret = fdt_set_name(blob, offset, new_name); + if (ret < 0) + printf("Unable to rename node ethernet-phy@1: %s\n", + fdt_strerror(ret)); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + /* fixup DT for the two DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN +#ifndef CONFIG_DM_ETH + fdt_fixup_fman_ethernet(blob); +#endif + fdt_fixup_phy_addr(blob); +#endif + + fdt_fixup_icid(blob); + + /* + * qe-hdlc and usb multi-use the pins, + * when set hwconfig to qe-hdlc, delete usb node. + */ + if (hwconfig("qe-hdlc")) +#ifdef CONFIG_HAS_FSL_XHCI_USB + fdt_del_node_and_alias(blob, "usb1"); +#endif + /* + * qe just support qe-uart and qe-hdlc, + * if qe-uart and qe-hdlc are not set in hwconfig, + * delete qe node. + */ + if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc")) + fdt_del_qe(blob); + + return 0; +} + +void nand_fixup(void) +{ + u32 csor = 0; + + if (CPLD_READ(pcba_ver) < 0x7) + return; + + /* Change NAND Flash PGS/SPRZ configuration */ + csor = CFG_SYS_NAND_CSOR; + if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) + csor = (csor & ~(CSOR_NAND_PGS_MASK)) | CSOR_NAND_PGS_4K; + + if ((csor & CSOR_NAND_SPRZ_MASK) == CSOR_NAND_SPRZ_64) + csor = (csor & ~(CSOR_NAND_SPRZ_MASK)) | CSOR_NAND_SPRZ_224; + + if (IS_ENABLED(CONFIG_TFABOOT)) { + u8 cfg_rcw_src1, cfg_rcw_src2; + u16 cfg_rcw_src; + + cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); + cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); + cpld_rev_bit(&cfg_rcw_src1); + cfg_rcw_src = cfg_rcw_src1; + cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; + + if (cfg_rcw_src == 0x25) + set_ifc_csor(IFC_CS1, csor); + else if (cfg_rcw_src == 0x118) + set_ifc_csor(IFC_CS0, csor); + else + printf("Invalid setting\n"); + } else { + if (IS_ENABLED(CONFIG_NAND_BOOT)) + set_ifc_csor(IFC_CS0, csor); + else + set_ifc_csor(IFC_CS1, csor); + } +} + +#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) +int board_fix_fdt(void *blob) +{ + /* nand driver fix up */ + nand_fixup(); + + /* fdt fix up */ + fdt_fixup_phy_addr(blob); + + return 0; +} +#endif + +u8 flash_read8(void *addr) +{ + return __raw_readb(addr + 1); +} + +void flash_write16(u16 val, void *addr) +{ + u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); + + __raw_writew(shftval, addr); +} + +u16 flash_read16(void *addr) +{ + u16 val = __raw_readw(addr); + + return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); +} + +#endif diff --git a/board/nxp/ls1043ardb/ls1043ardb_pbi.cfg b/board/nxp/ls1043ardb/ls1043ardb_pbi.cfg new file mode 100644 index 00000000000..f072274f474 --- /dev/null +++ b/board/nxp/ls1043ardb/ls1043ardb_pbi.cfg @@ -0,0 +1,14 @@ +#Configure Scratch register +09570600 00000000 +09570604 10000000 +#Alt base register +09570158 00001000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009e +0957041c 0000009e +09570420 0000009e +#flush PBI data +096100c0 000fffff diff --git a/board/nxp/ls1043ardb/ls1043ardb_rcw_nand.cfg b/board/nxp/ls1043ardb/ls1043ardb_rcw_nand.cfg new file mode 100644 index 00000000000..d87058b7efe --- /dev/null +++ b/board/nxp/ls1043ardb/ls1043ardb_rcw_nand.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# serdes protocol +08100010 0a000000 00000000 00000000 +14550002 80004012 e0106000 c1002000 +00000000 00000000 00000000 00038800 +00000000 00001100 00000096 00000001 diff --git a/board/nxp/ls1043ardb/ls1043ardb_rcw_sd.cfg b/board/nxp/ls1043ardb/ls1043ardb_rcw_sd.cfg new file mode 100644 index 00000000000..e2ee34b7dfc --- /dev/null +++ b/board/nxp/ls1043ardb/ls1043ardb_rcw_sd.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +08100010 0a000000 00000000 00000000 +14550002 80004012 60040000 c1002000 +00000000 00000000 00000000 00038800 +00000000 00001100 00000096 00000001 diff --git a/board/nxp/ls1046afrwy/Kconfig b/board/nxp/ls1046afrwy/Kconfig new file mode 100644 index 00000000000..0f73485af7e --- /dev/null +++ b/board/nxp/ls1046afrwy/Kconfig @@ -0,0 +1,16 @@ + +if TARGET_LS1046AFRWY + +config SYS_BOARD + default "ls1046afrwy" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1046afrwy" + +endif diff --git a/board/nxp/ls1046afrwy/MAINTAINERS b/board/nxp/ls1046afrwy/MAINTAINERS new file mode 100644 index 00000000000..abfd3e937b5 --- /dev/null +++ b/board/nxp/ls1046afrwy/MAINTAINERS @@ -0,0 +1,8 @@ +LS1046AFRWY BOARD +M: Pramod Kumar +S: Maintained +F: board/nxp/ls1046afrwy/ +F: board/nxp/ls1046afrwy/ls1046afrwy.c +F: include/configs/ls1046afrwy.h +F: configs/ls1046afrwy_tfa_defconfig +F: configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig diff --git a/board/nxp/ls1046afrwy/Makefile b/board/nxp/ls1046afrwy/Makefile new file mode 100644 index 00000000000..c70f5cda797 --- /dev/null +++ b/board/nxp/ls1046afrwy/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 NXP + +obj-y += ddr.o +obj-y += ls1046afrwy.o +obj-$(CONFIG_NET) += eth.o diff --git a/board/nxp/ls1046afrwy/README b/board/nxp/ls1046afrwy/README new file mode 100644 index 00000000000..2c7c797a879 --- /dev/null +++ b/board/nxp/ls1046afrwy/README @@ -0,0 +1,76 @@ +Overview +-------- +The LS1046A Freeway Board (iFRWY) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS1046A +LayerScape Architecture processor. The FRWY-LS1046A provides SW development +platform for the Freescale LS1046A processor series, with a complete +debugging environment. The FRWY-LS1046A is lead-free and RoHS-compliant. + +LS1046A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A +SoC overview. + + FRWY-LS1046A board Overview + ----------------------- + - SERDES1 Connections, 4 lanes supporting: + - Lane0: Unused + - Lane1: Unused + - Lane2: QSGMII + - Lane3: Unused + - SERDES2 Connections, 4 lanes supporting: + - Lane0: Unused + - Lane1: PCIe3 with PCIe x1 slot + - Lane2: Unused + - Lane3: PCIe3 with PCIe x1 slot + - DDR Controller + - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s + -IFC/Local Bus + - One 512 MB NAND flash with ECC support + - USB 3.0 + - Two Type A port + - SDHC: connects directly to a full microSD slot + - QSPI: 64 MB high-speed flash Memory for boot code and storage + - 4 I2C controllers + - UART + - Two 4-pin serial ports at up to 115.2 Kbit/s + - Two DB9 D-Type connectors supporting one Serial port each + - ARM JTAG support + +Memory map from core's view +---------------------------- +Start Address End Address Description Size +0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB +0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB +0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB +0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB +0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M +0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M +0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB +0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G +0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G +0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G + +QSPI flash map: +Start Address End Address Description Size +0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI + BL2 1MB +0x00_4010_0000 - 0x00_404F_FFFF FIP Image + (Bl31 + BL32(optee. + bin) + Bl33(uboot) + + headers for secure + boot) 4MB +0x00_4050_0000 - 0x00_405F_FFFF Boot Firmware Env 1MB +0x00_4060_0000 - 0x00_408F_FFFF Secure boot headers 3MB +0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB +0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB +0x00_409C_0000 - 0x00_409F_FFFF Reserved 256KB +0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB + +Booting Options +--------------- +a) QSPI boot +b) microSD boot diff --git a/board/nxp/ls1046afrwy/ddr.c b/board/nxp/ls1046afrwy/ddr.c new file mode 100644 index 00000000000..b08caee1d97 --- /dev/null +++ b/board/nxp/ls1046afrwy/ddr.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} diff --git a/board/nxp/ls1046afrwy/eth.c b/board/nxp/ls1046afrwy/eth.c new file mode 100644 index 00000000000..8efc7f68424 --- /dev/null +++ b/board/nxp/ls1046afrwy/eth.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/fman.h" + +int board_eth_init(struct bd_info *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info dtsec_mdio_info; + struct mii_dev *dev; + u32 srds_s1; + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + /* QSGMII on lane B, MAC 6/5/10/1 */ + fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR); + + switch (srds_s1) { + case 0x3040: + break; + default: + printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n", + srds_s1); + break; + } + + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(FM1_DTSEC6, dev); + fm_info_set_mdio(FM1_DTSEC5, dev); + fm_info_set_mdio(FM1_DTSEC10, dev); + fm_info_set_mdio(FM1_DTSEC1, dev); + + fm_disable_port(FM1_DTSEC9); + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} + +#ifdef CONFIG_FMAN_ENET +int fdt_update_ethernet_dt(void *blob) +{ + u32 srds_s1; + int i, prop; + int offset, nodeoff; + const char *path; + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + /* Cycle through all aliases */ + for (prop = 0; ; prop++) { + const char *name; + + /* FDT might have been edited, recompute the offset */ + offset = fdt_first_property_offset(blob, + fdt_path_offset(blob, + "/aliases") + ); + /* Select property number 'prop' */ + for (i = 0; i < prop; i++) + offset = fdt_next_property_offset(blob, offset); + + if (offset < 0) + break; + + path = fdt_getprop_by_offset(blob, offset, &name, NULL); + nodeoff = fdt_path_offset(blob, path); + + switch (srds_s1) { + case 0x3040: + if (!strcmp(name, "ethernet1")) + fdt_status_disabled(blob, nodeoff); + if (!strcmp(name, "ethernet2")) + fdt_status_disabled(blob, nodeoff); + if (!strcmp(name, "ethernet3")) + fdt_status_disabled(blob, nodeoff); + if (!strcmp(name, "ethernet6")) + fdt_status_disabled(blob, nodeoff); + break; + default: + printf("%s:Invalid SerDes prtcl 0x%x for LS1046AFRWY\n", + __func__, srds_s1); + break; + } + } + + return 0; +} +#endif diff --git a/board/nxp/ls1046afrwy/ls1046afrwy.c b/board/nxp/ls1046afrwy/ls1046afrwy.c new file mode 100644 index 00000000000..8889c24f1f0 --- /dev/null +++ b/board/nxp/ls1046afrwy/ls1046afrwy.c @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019, 2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/i2c_mux.h" + +#define LS1046A_PORSR1_REG 0x1EE0000 +#define BOOT_SRC_SD 0x20000000 +#define BOOT_SRC_MASK 0xFF800000 +#define BOARD_REV_GPIO_SHIFT 17 +#define BOARD_REV_MASK 0x03 +#define USB2_SEL_MASK 0x00000100 + +#define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \ +(((word) & 0x00ff0000) >> 8) | \ +(((word) & 0x0000ff00) << 8) | \ +(((word) & 0x000000ff) << 24)) +#define SPI_MCR_REG 0x2100000 + +DECLARE_GLOBAL_DATA_PTR; + +static inline void demux_select_usb2(void) +{ + u32 val; + struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR); + + val = in_be32(&pgpio->gpdir); + val |= USB2_SEL_MASK; + out_be32(&pgpio->gpdir, val); + + val = in_be32(&pgpio->gpdat); + val |= USB2_SEL_MASK; + out_be32(&pgpio->gpdat, val); +} + +static inline void set_spi_cs_signal_inactive(void) +{ + /* default: all CS signals inactive state is high */ + uint mcr_val; + uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK | + DSPI_MCR_CRXF | DSPI_MCR_CTXF; + + mcr_val = in_be32(SPI_MCR_REG); + mcr_val |= DSPI_MCR_HALT; + out_be32(SPI_MCR_REG, mcr_val); + out_be32(SPI_MCR_REG, mcr_cfg_val); + mcr_val = in_be32(SPI_MCR_REG); + mcr_val &= ~DSPI_MCR_HALT; + out_be32(SPI_MCR_REG, mcr_val); +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +static inline uint8_t get_board_version(void) +{ + struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR); + + /* GPIO 13 and GPIO 14 are used for Board Rev */ + u32 gpio_val = ((in_be32(&pgpio->gpdat) >> BOARD_REV_GPIO_SHIFT)) + & BOARD_REV_MASK; + + /* GPIOs' are 0..31 in Big Endiness, swap GPIO 13 and GPIO 14 */ + u8 val = ((gpio_val >> 1) | (gpio_val << 1)) & BOARD_REV_MASK; + + return val; +} + +int checkboard(void) +{ + static const char *freq[2] = {"100.00MHZ", "100.00MHZ"}; + u32 boot_src; + u8 rev; + + rev = get_board_version(); + switch (rev) { + case 0x00: + puts("Board: LS1046AFRWY, Rev: A, boot from "); + break; + case 0x01: + puts("Board: LS1046AFRWY, Rev: B, boot from "); + break; + default: + puts("Board: LS1046AFRWY, Rev: Unknown, boot from "); + break; + } + boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG)); + + if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD) + puts("SD\n"); + else + puts("QSPI\n"); + printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]); + + return 0; +} + +int board_init(void) +{ +#ifdef CONFIG_NXP_ESBC + /* + * In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + u32 val; +val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +#endif + + if (!IS_ENABLED(CONFIG_SYS_EARLY_PCI_INIT)) + pci_init(); + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); + return 0; +} + +int board_setup_core_volt(u32 vdd) +{ + return 0; +} + +void config_board_mux(void) +{ +#ifdef CONFIG_HAS_FSL_XHCI_USB + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; + u32 usb_pwrfault; + /* + * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT + * USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA + */ + out_be32(&scfg->rcwpmuxcr0, 0x3300); +#ifdef CONFIG_HAS_FSL_IIC3 + /* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */ + out_be32(&scfg->rcwpmuxcr0, 0x0000); +#endif + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); + usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << + SCFG_USBPWRFAULT_USB1_SHIFT); + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); +#ifndef CONFIG_HAS_FSL_IIC3 + /* + * LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input + * to select I2C3_USB2_SEL_IO + * I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to + * I2C3 header (default) + * I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to + * USB2 port + * programmed to select USB2 by setting GPIO3_23 output to one + */ + demux_select_usb2(); +#endif +#endif + set_spi_cs_signal_inactive(); +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + config_board_mux(); + return 0; +} +#endif + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + /* fixup DT for the two DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN +#ifndef CONFIG_DM_ETH + fdt_fixup_fman_ethernet(blob); +#endif +#endif + + fdt_fixup_icid(blob); + + return 0; +} diff --git a/board/nxp/ls1046aqds/Kconfig b/board/nxp/ls1046aqds/Kconfig new file mode 100644 index 00000000000..b886c55576a --- /dev/null +++ b/board/nxp/ls1046aqds/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1046AQDS + +config SYS_BOARD + default "ls1046aqds" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1046aqds" + +endif diff --git a/board/nxp/ls1046aqds/MAINTAINERS b/board/nxp/ls1046aqds/MAINTAINERS new file mode 100644 index 00000000000..792531f7f3a --- /dev/null +++ b/board/nxp/ls1046aqds/MAINTAINERS @@ -0,0 +1,14 @@ +LS1046AQDS BOARD +M: Mingkai Hu +S: Maintained +F: board/nxp/ls1046aqds/ +F: include/configs/ls1046aqds.h +F: configs/ls1046aqds_defconfig +F: configs/ls1046aqds_nand_defconfig +F: configs/ls1046aqds_sdcard_ifc_defconfig +F: configs/ls1046aqds_sdcard_qspi_defconfig +F: configs/ls1046aqds_qspi_defconfig +F: configs/ls1046aqds_lpuart_defconfig +F: configs/ls1046aqds_tfa_defconfig +F: configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +F: configs/ls1046aqds_SECURE_BOOT_defconfig diff --git a/board/nxp/ls1046aqds/Makefile b/board/nxp/ls1046aqds/Makefile new file mode 100644 index 00000000000..365247d92bc --- /dev/null +++ b/board/nxp/ls1046aqds/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ddr.o +ifndef CONFIG_XPL_BUILD +obj-y += eth.o +endif +obj-y += ls1046aqds.o diff --git a/board/nxp/ls1046aqds/README b/board/nxp/ls1046aqds/README new file mode 100644 index 00000000000..cb694735a46 --- /dev/null +++ b/board/nxp/ls1046aqds/README @@ -0,0 +1,70 @@ +Overview +-------- +The LS1046A Development System (QDS) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS1046A +LayerScape Architecture processor. The LS1046AQDS provides SW development +platform for the Freescale LS1046A processor series, with a complete +debugging environment. + +LS1046A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A +SoC overview. + + LS1046AQDS board Overview + ----------------------- + - SERDES Connections, 8 lanes supporting: + - PCI Express - 3.0 + - SGMII, SGMII 2.5 + - QSGMII + - SATA 3.0 + - 10GBase-R + - DDR Controller + - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s + -IFC/Local Bus + - One in-socket 128 MB NOR flash 16-bit data bus + - One 512 MB NAND flash with ECC support + - PromJet Port + - FPGA connection + - USB 3.0 + - Three high speed USB 3.0 ports + - First USB 3.0 port configured as Host with Type-A connector + - The other two USB 3.0 ports configured as OTG with micro-AB connector + - SDHC port connects directly to an adapter card slot, featuring: + - Optional clock feedback paths, and optional high-speed voltage translation assistance + - SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC + - eMMC memory devices + - DSPI: Onboard support for three SPI flash memory devices + - 4 I2C controllers + - One SATA onboard connectors + - UART + - Two 4-pin serial ports at up to 115.2 Kbit/s + - Two DB9 D-Type connectors supporting one Serial port each + - ARM JTAG support + +Memory map from core's view +---------------------------- +Start Address End Address Description Size +0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB +0x00_6000_0000 - 0x00_67FF_FFFF IFC - NOR Flash 128MB +0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB +0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - FPGA 4KB +0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB +0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M +0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M +0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB +0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G +0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G +0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G + +Booting Options +--------------- +a) Promjet Boot +b) NOR boot +c) NAND boot +d) SD boot +e) QSPI boot diff --git a/board/nxp/ls1046aqds/ddr.c b/board/nxp/ls1046aqds/ddr.c new file mode 100644 index 00000000000..57790335f0a --- /dev/null +++ b/board/nxp/ls1046aqds/ddr.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + */ + +#include +#include +#ifdef CONFIG_FSL_DEEP_SLEEP +#include +#endif +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 3) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + + popts->data_bus_width = 0; /* 64b data bus */ + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + popts->bstopre = 0; /* enable auto precharge */ + + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; + + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x70; +} + +#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} +#else +int fsl_initdram(void) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +#else + puts("Initializing DDR....using SPD\n"); + + dram_size = fsl_ddr_sdram(); +#endif + +#ifdef CONFIG_FSL_DEEP_SLEEP + fsl_dp_ddr_restore(); +#endif + + erratum_a008850_post(); + + gd->ram_size = dram_size; + + return 0; +} +#endif diff --git a/board/nxp/ls1046aqds/ddr.h b/board/nxp/ls1046aqds/ddr.h new file mode 100644 index 00000000000..e55446f2b29 --- /dev/null +++ b/board/nxp/ls1046aqds/ddr.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + */ + +#ifndef __DDR_H__ +#define __DDR_H__ + +void erratum_a008850_post(void); + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2300, 0, 8, 9, 0x0A0C0D11, 0x1214150E,}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +#endif diff --git a/board/nxp/ls1046aqds/eth.c b/board/nxp/ls1046aqds/eth.c new file mode 100644 index 00000000000..cd3500c2e96 --- /dev/null +++ b/board/nxp/ls1046aqds/eth.c @@ -0,0 +1,431 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2018-2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/qixis.h" +#include "../common/fman.h" +#include "ls1046aqds_qixis.h" + +#define EMI_NONE 0xFF +#define EMI1_RGMII1 0 +#define EMI1_RGMII2 1 +#define EMI1_SLOT1 2 +#define EMI1_SLOT2 3 +#define EMI1_SLOT4 4 + +static const char * const mdio_names[] = { + "LS1046AQDS_MDIO_RGMII1", + "LS1046AQDS_MDIO_RGMII2", + "LS1046AQDS_MDIO_SLOT1", + "LS1046AQDS_MDIO_SLOT2", + "LS1046AQDS_MDIO_SLOT4", + "NULL", +}; + +/* Map SerDes 1 & 2 lanes to default slot. */ +#ifdef CONFIG_FMAN_ENET +static int mdio_mux[NUM_FM_PORTS]; + +static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0}; +#endif + +static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name; + + if (muxval > EMI1_SLOT4) + return NULL; + + name = ls1046aqds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +#ifdef CONFIG_FMAN_ENET +struct ls1046aqds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static void ls1046aqds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + + if (muxval < 7) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct ls1046aqds_mdio *priv = bus->priv; + + ls1046aqds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct ls1046aqds_mdio *priv = bus->priv; + + ls1046aqds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, + regnum, value); +} + +static int ls1046aqds_mdio_reset(struct mii_dev *bus) +{ + struct ls1046aqds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int ls1046aqds_mdio_init(char *realbusname, u8 muxval) +{ + struct ls1046aqds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate ls1046aqds MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate ls1046aqds private data\n"); + free(bus); + return -1; + } + + bus->read = ls1046aqds_mdio_read; + bus->write = ls1046aqds_mdio_write; + bus->reset = ls1046aqds_mdio_reset; + sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + return mdio_register(bus); +} + +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + struct fixed_link f_link; + const char *phyconn; + + if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + switch (port) { + case FM1_DTSEC9: + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p1"); + break; + case FM1_DTSEC10: + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p2"); + break; + case FM1_DTSEC5: + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p3"); + break; + case FM1_DTSEC6: + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p4"); + break; + case FM1_DTSEC2: + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s4-p1"); + break; + default: + break; + } + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) { + /* 2.5G SGMII interface */ + f_link.phy_id = cpu_to_fdt32(port); + f_link.duplex = cpu_to_fdt32(1); + f_link.link_speed = cpu_to_fdt32(1000); + f_link.pause = 0; + f_link.asym_pause = 0; + /* no PHY for 2.5G SGMII on QDS */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); + fdt_setprop_string(fdt, offset, "phy-connection-type", + "2500base-x"); + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { + switch (port) { + case FM1_DTSEC1: + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p4"); + break; + case FM1_DTSEC5: + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p2"); + break; + case FM1_DTSEC6: + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p1"); + break; + case FM1_DTSEC10: + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p3"); + break; + default: + break; + } + fdt_delprop(fdt, offset, "phy-connection-type"); + fdt_setprop_string(fdt, offset, "phy-connection-type", + "qsgmii"); + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && + (port == FM1_10GEC1 || port == FM1_10GEC2)) { + phyconn = fdt_getprop(fdt, offset, "phy-connection-type", NULL); + if (is_backplane_mode(phyconn)) { + /* Backplane KR mode: skip fixups */ + printf("Interface %d in backplane KR mode\n", port); + } else { + /* 10GBase-R interface */ + f_link.phy_id = cpu_to_fdt32(port); + f_link.duplex = cpu_to_fdt32(1); + f_link.link_speed = cpu_to_fdt32(10000); + f_link.pause = 0; + f_link.asym_pause = 0; + /* no PHY for 10GBase-R */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, + sizeof(f_link)); + fdt_setprop_string(fdt, offset, "phy-connection-type", + "xgmii"); + } + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + int i; + + for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + switch (mdio_mux[i]) { + case EMI1_SLOT1: + fdt_status_okay_by_alias(fdt, "emi1-slot1"); + break; + case EMI1_SLOT2: + fdt_status_okay_by_alias(fdt, "emi1-slot2"); + break; + case EMI1_SLOT4: + fdt_status_okay_by_alias(fdt, "emi1-slot4"); + break; + default: + break; + } + break; + default: + break; + } + } +} + +int board_eth_init(struct bd_info *bis) +{ + int i, idx, lane, slot, interface; + struct memac_mdio_info dtsec_mdio_info; + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + u32 srds_s1, srds_s2; + u8 brdcfg12; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + srds_s2 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; + srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT; + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + /* Register the muxing front-ends to the MDIO buses */ + ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); + ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); + ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); + + switch (srds_s1) { + case 0x3333: + /* SGMII on slot 1, MAC 9 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + case 0x1333: + case 0x2333: + /* SGMII on slot 1, MAC 10 */ + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + case 0x1133: + case 0x2233: + /* SGMII on slot 1, MAC 5/6 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); + break; + case 0x1040: + case 0x2040: + /* QSGMII on lane B, MAC 6/5/10/1 */ + fm_info_set_phy_address(FM1_DTSEC6, + QSGMII_CARD_PORT1_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC5, + QSGMII_CARD_PORT2_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC10, + QSGMII_CARD_PORT3_PHY_ADDR_S2); + fm_info_set_phy_address(FM1_DTSEC1, + QSGMII_CARD_PORT4_PHY_ADDR_S2); + break; + case 0x3363: + /* SGMII on slot 1, MAC 9/10 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + case 0x1163: + case 0x2263: + case 0x2223: + /* SGMII on slot 1, MAC 6 */ + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); + break; + default: + printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n", + srds_s1); + break; + } + + if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06) + /* SGMII on slot 4, MAC 2 */ + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + if (interface == PHY_INTERFACE_MODE_SGMII) { + if (i == FM1_DTSEC5) { + /* route lane 2 to slot1 so to have + * one sgmii riser card supports + * MAC5 and MAC6. + */ + brdcfg12 = QIXIS_READ(brdcfg[12]); + QIXIS_WRITE(brdcfg[12], + brdcfg12 | 0x80); + } + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + } else { + /* clear the bit 7 to route lane B on slot2. */ + brdcfg12 = QIXIS_READ(brdcfg[12]); + QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f); + + lane = serdes_get_first_lane(FSL_SRDS_1, + QSGMII_FM1_A); + lane_to_slot[lane] = 2; + } + + if (i == FM1_DTSEC2) + lane = 5; + + if (lane < 0) + break; + + slot = lane_to_slot[lane]; + debug("FM1@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 4: + mdio_mux[i] = EMI1_SLOT4; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + default: + break; + } + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: + if (i == FM1_DTSEC3) + mdio_mux[i] = EMI1_RGMII1; + else if (i == FM1_DTSEC4) + mdio_mux[i] = EMI1_RGMII2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + cpu_eth_init(bis); + + return pci_eth_init(bis); +} +#endif /* CONFIG_FMAN_ENET */ diff --git a/board/nxp/ls1046aqds/ls1046aqds.c b/board/nxp/ls1046aqds/ls1046aqds.c new file mode 100644 index 00000000000..7df12550868 --- /dev/null +++ b/board/nxp/ls1046aqds/ls1046aqds.c @@ -0,0 +1,479 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2019-2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/i2c_mux.h" + +#include "../common/vid.h" +#include "../common/qixis.h" +#include "ls1046aqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_TFABOOT +struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nor0", + CFG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, + { + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 + }, + + }, + { + "nor1", + CFG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR_EXT, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, + { + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 + }, + }, + { + "nand", + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, + { + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 + }, + }, + { + "fpga", + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, + { + CFG_SYS_FPGA_FTIM0, + CFG_SYS_FPGA_FTIM1, + CFG_SYS_FPGA_FTIM2, + CFG_SYS_FPGA_FTIM3 + }, + } +}; + +struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nand", + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, + { + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 + }, + }, + { + "nor0", + CFG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, + { + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 + }, + }, + { + "nor1", + CFG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR_EXT, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, + { + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 + }, + }, + { + "fpga", + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, + { + CFG_SYS_FPGA_FTIM0, + CFG_SYS_FPGA_FTIM1, + CFG_SYS_FPGA_FTIM2, + CFG_SYS_FPGA_FTIM3 + }, + } +}; + +void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) +{ + enum boot_src src = get_boot_src(); + + if (src == BOOT_SOURCE_IFC_NAND) + regs_info->regs = ifc_cfg_nand_boot; + else + regs_info->regs = ifc_cfg_nor_boot; + regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; +} + +#endif + +enum { + MUX_TYPE_GPIO, +}; + +int checkboard(void) +{ +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); +#endif + char buf[64]; +#ifndef CONFIG_SD_BOOT + u8 sw; +#endif + + puts("Board: LS1046AQDS, boot from "); + +#ifdef CONFIG_TFABOOT + if (src == BOOT_SOURCE_SD_MMC) + puts("SD\n"); + else { +#endif + +#ifdef CONFIG_SD_BOOT + puts("SD\n"); +#else + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("PromJet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else if (sw == 0xF) + printf("QSPI\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); +#endif + +#ifdef CONFIG_TFABOOT + } +#endif + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", + QIXIS_READ(id), QIXIS_READ(arch)); + + printf("FPGA: v%d (%s), build %d\n", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + + return 0; +} + +bool if_board_diff_clk(void) +{ + u8 diff_conf = QIXIS_READ(brdcfg[11]); + + return diff_conf & 0x40; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0f) { + case QIXIS_SYSCLK_64: + return 64000000; + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + if (if_board_diff_clk()) + return get_board_sys_clk(); + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + + return 66666666; +} + +#ifdef CONFIG_LPUART +u32 get_lpuart_clk(void) +{ + return gd->bus_clk; +} +#endif + +int dram_init(void) +{ + /* + * When resuming from deep sleep, the I2C channel may not be + * in the default channel. So, switch to the default channel + * before accessing DDR SPD. + * + * PCA9547 mount on I2C1 bus + */ + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); + fsl_initdram(); +#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ + defined(CONFIG_XPL_BUILD) + /* This will break-before-make MMU for DDR */ + update_early_mmu_table(); +#endif + + return 0; +} + +int i2c_multiplexer_select_vid_channel(u8 channel) +{ + return select_i2c_ch_pca9547(channel, 0); +} + +int board_early_init_f(void) +{ + u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR; +#ifdef CONFIG_HAS_FSL_XHCI_USB + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; + u32 usb_pwrfault; +#endif +#ifdef CONFIG_LPUART + u8 uart; +#endif + + /* + * Enable secure system counter for timer + */ + out_le32(cntcr, 0x1); + +#if defined(CONFIG_SYS_I2C_EARLY_INIT) + i2c_early_init_f(); +#endif + fsl_lsch2_early_init_f(); + +#ifdef CONFIG_HAS_FSL_XHCI_USB + out_be32(&scfg->rcwpmuxcr0, 0x3333); + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); + usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << + SCFG_USBPWRFAULT_USB1_SHIFT); + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); +#endif + +#ifdef CONFIG_LPUART + /* We use lpuart0 as system console */ + uart = QIXIS_READ(brdcfg[14]); + uart &= ~CFG_UART_MUX_MASK; + uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; + QIXIS_WRITE(brdcfg[14], uart); +#endif + + return 0; +} + +#ifdef CONFIG_FSL_DEEP_SLEEP +/* determine if it is a warm boot */ +bool is_warm_boot(void) +{ +#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; + + if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) + return 1; + + return 0; +} +#endif + +int config_board_mux(int ctrl_type) +{ + u8 reg14; + + reg14 = QIXIS_READ(brdcfg[14]); + + switch (ctrl_type) { + case MUX_TYPE_GPIO: + reg14 = (reg14 & (~0x6)) | 0x2; + break; + default: + puts("Unsupported mux interface type\n"); + return -1; + } + + QIXIS_WRITE(brdcfg[14], reg14); + + return 0; +} + +int config_serdes_mux(void) +{ + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + if (hwconfig("gpio")) + config_board_mux(MUX_TYPE_GPIO); + + return 0; +} +#endif + +int board_init(void) +{ + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); + +#ifdef CFG_SYS_FSL_SERDES + config_serdes_mux(); +#endif + + if (adjust_vdd(0)) + printf("Warning: Adjusting core voltage failed.\n"); + +#ifdef CONFIG_NXP_ESBC + /* + * In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + u32 val; + val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +#endif + + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + u8 reg; + + /* fixup DT for the two DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_FMAN_ENET + fdt_fixup_board_enet(blob); +#endif + + fdt_fixup_icid(blob); + + reg = QIXIS_READ(brdcfg[0]); + reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + /* Disable IFC if QSPI is enabled */ + if (reg == 0xF) + do_fixup_by_compat(blob, "fsl,ifc", + "status", "disabled", 8 + 1, 1); + + return 0; +} +#endif + +u8 flash_read8(void *addr) +{ + return __raw_readb(addr + 1); +} + +void flash_write16(u16 val, void *addr) +{ + u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); + + __raw_writew(shftval, addr); +} + +u16 flash_read16(void *addr) +{ + u16 val = __raw_readw(addr); + + return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); +} + +#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) +void *env_sf_get_env_addr(void) +{ + return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); +} +#endif diff --git a/board/nxp/ls1046aqds/ls1046aqds_pbi.cfg b/board/nxp/ls1046aqds/ls1046aqds_pbi.cfg new file mode 100644 index 00000000000..5a6b7b84a4c --- /dev/null +++ b/board/nxp/ls1046aqds/ls1046aqds_pbi.cfg @@ -0,0 +1,17 @@ +#Configure Scratch register +09570600 00000000 +09570604 10000000 +#Alt base register +09570158 00001000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009e +0957041c 0000009e +09570420 0000009e +#Serdes SATA +09eb1300 80104e20 +09eb08dc 00502880 +#flush PBI data +096100c0 000fffff diff --git a/board/nxp/ls1046aqds/ls1046aqds_qixis.h b/board/nxp/ls1046aqds/ls1046aqds_qixis.h new file mode 100644 index 00000000000..f371056e37a --- /dev/null +++ b/board/nxp/ls1046aqds/ls1046aqds_qixis.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + */ + +#ifndef __LS1046AQDS_QIXIS_H__ +#define __LS1046AQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for LS1046AQDS */ + +/* BRDCFG4[4:7] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xe0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 +#define QIXIS_SYSCLK_64 0x8 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +/* BRDCFG2 - SD clock*/ +#define QIXIS_SDCLK1_100 0x0 +#define QIXIS_SDCLK1_125 0x1 +#define QIXIS_SDCLK1_165 0x2 +#define QIXIS_SDCLK1_100_SP 0x3 + +#endif diff --git a/board/nxp/ls1046aqds/ls1046aqds_rcw_nand.cfg b/board/nxp/ls1046aqds/ls1046aqds_rcw_nand.cfg new file mode 100644 index 00000000000..b5fc08ce2ab --- /dev/null +++ b/board/nxp/ls1046aqds/ls1046aqds_rcw_nand.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# serdes protocol +0c150010 0e000000 00000000 00000000 +11335559 40005012 e0116000 c1000000 +00000000 00000000 00000000 00038800 +00000000 01001101 00000096 00000001 diff --git a/board/nxp/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg b/board/nxp/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg new file mode 100644 index 00000000000..59d24d67908 --- /dev/null +++ b/board/nxp/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +# Enable IFC; disable QSPI +0c150010 0e000000 00000000 00000000 +11335559 40005012 60040000 c1000000 +00000000 00000000 00000000 00038800 +00000000 01001101 00000096 00000001 diff --git a/board/nxp/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg b/board/nxp/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg new file mode 100644 index 00000000000..9401a6f0f4f --- /dev/null +++ b/board/nxp/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +# Enable QSPI; disable IFC +0c150010 0e000000 00000000 00000000 +11335559 40005012 60040000 c1000000 +00000000 00000000 00000000 00038800 +20124000 01001101 00000096 00000001 diff --git a/board/nxp/ls1046ardb/Kconfig b/board/nxp/ls1046ardb/Kconfig new file mode 100644 index 00000000000..7cb7e0eb01e --- /dev/null +++ b/board/nxp/ls1046ardb/Kconfig @@ -0,0 +1,16 @@ + +if TARGET_LS1046ARDB + +config SYS_BOARD + default "ls1046ardb" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1046ardb" + +endif diff --git a/board/nxp/ls1046ardb/MAINTAINERS b/board/nxp/ls1046ardb/MAINTAINERS new file mode 100644 index 00000000000..bb5f6a64d7b --- /dev/null +++ b/board/nxp/ls1046ardb/MAINTAINERS @@ -0,0 +1,16 @@ +LS1046A BOARD +M: Mingkai Hu +S: Maintained +F: board/nxp/ls1046ardb/ +F: board/nxp/ls1046ardb/ls1046ardb.c +F: include/configs/ls1046ardb.h +F: configs/ls1046ardb_qspi_defconfig +F: configs/ls1046ardb_qspi_spl_defconfig +F: configs/ls1046ardb_sdcard_defconfig +F: configs/ls1046ardb_emmc_defconfig +F: configs/ls1046ardb_tfa_defconfig +F: configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +F: configs/ls1046ardb_SECURE_BOOT_defconfig +F: configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +F: configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +F: doc/board/nxp/ls1046ardb.rst diff --git a/board/nxp/ls1046ardb/Makefile b/board/nxp/ls1046ardb/Makefile new file mode 100644 index 00000000000..9e5d24f53c8 --- /dev/null +++ b/board/nxp/ls1046ardb/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2016 Freescale Semiconductor + +obj-y += ddr.o +obj-y += ls1046ardb.o +ifndef CONFIG_XPL_BUILD +obj-$(CONFIG_NET) += eth.o +obj-y += cpld.o +endif diff --git a/board/nxp/ls1046ardb/cpld.c b/board/nxp/ls1046ardb/cpld.c new file mode 100644 index 00000000000..26a5962bd6e --- /dev/null +++ b/board/nxp/ls1046ardb/cpld.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 Freescale Semiconductor + * + * Freescale LS1046ARDB board-specific CPLD controlling supports. + */ + +#include +#include +#include +#include +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CFG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CFG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/* Set the boot bank to the alternate bank */ +void cpld_set_altbank(void) +{ + u16 reg = CPLD_CFG_RCW_SRC_QSPI; + u8 reg4 = CPLD_READ(soft_mux_on); + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); + u8 reg7 = CPLD_READ(vbank); + + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); + + reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; + CPLD_WRITE(vbank, reg7); + + CPLD_WRITE(system_rst, 1); +} + +/* Set the boot bank to the default bank */ +void cpld_set_defbank(void) +{ + u16 reg = CPLD_CFG_RCW_SRC_QSPI; + u8 reg4 = CPLD_READ(soft_mux_on); + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); + + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); + + CPLD_WRITE(vbank, 0); + + CPLD_WRITE(system_rst, 1); +} + +void cpld_set_sd(void) +{ + u16 reg = CPLD_CFG_RCW_SRC_SD; + u8 reg5 = (u8)(reg >> 1); + u8 reg6 = (u8)(reg & 1); + + cpld_rev_bit(®5); + + CPLD_WRITE(soft_mux_on, 1); + + CPLD_WRITE(cfg_rcw_src1, reg5); + CPLD_WRITE(cfg_rcw_src2, reg6); + + CPLD_WRITE(system_rst, 1); +} + +void cpld_select_core_volt(bool en_0v9) +{ + u8 reg17 = en_0v9; + + CPLD_WRITE(vdd_en, 1); + CPLD_WRITE(vdd_sel, reg17); +} + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("cpld_ver = %x\n", CPLD_READ(cpld_ver)); + printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub)); + printf("pcba_ver = %x\n", CPLD_READ(pcba_ver)); + printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on)); + printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1)); + printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2)); + printf("vbank = %x\n", CPLD_READ(vbank)); + printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel)); + printf("uart_sel = %x\n", CPLD_READ(uart_sel)); + printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel)); + printf("rgmii_1588_sel = %x\n", CPLD_READ(rgmii_1588_sel)); + printf("1588_clk_sel = %x\n", CPLD_READ(reg_1588_clk_sel)); + printf("status_led = %x\n", CPLD_READ(status_led)); + printf("sd_emmc = %x\n", CPLD_READ(sd_emmc)); + printf("vdd_en = %x\n", CPLD_READ(vdd_en)); + printf("vdd_sel = %x\n", CPLD_READ(vdd_sel)); + putc('\n'); +} +#endif + +void cpld_rev_bit(unsigned char *value) +{ + u8 rev_val, val; + int i; + + val = *value; + rev_val = val & 1; + for (i = 1; i <= 7; i++) { + val >>= 1; + rev_val <<= 1; + rev_val |= val & 1; + } + + *value = rev_val; +} + +int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else if (strcmp(argv[2], "sd") == 0) + cpld_set_sd(); + else + cpld_set_defbank(); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else { + rc = cmd_usage(cmdtp); + } + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset: reset to default bank\n" + "cpld reset altbank: reset to alternate bank\n" + "cpld reset sd: reset to boot from SD card\n" +#ifdef DEBUG + "cpld dump - display the CPLD registers\n" +#endif +); diff --git a/board/nxp/ls1046ardb/cpld.h b/board/nxp/ls1046ardb/cpld.h new file mode 100644 index 00000000000..e87044f5c0d --- /dev/null +++ b/board/nxp/ls1046ardb/cpld.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Freescale Semiconductor + */ + +#ifndef __CPLD_H__ +#define __CPLD_H__ + +/* + * CPLD register set of LS1046ARDB board-specific. + * CPLD Revision: V2.1 + */ +struct cpld_data { + u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ + u8 pcba_ver; /* 0x2 - PCBA Revision Register */ + u8 system_rst; /* 0x3 - system reset register */ + u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */ + u8 cfg_rcw_src1; /* 0x5 - RCW Source Location POR Regsiter 1 */ + u8 cfg_rcw_src2; /* 0x6 - RCW Source Location POR Regsiter 2 */ + u8 vbank; /* 0x7 - QSPI Flash Bank Setting Register */ + u8 sysclk_sel; /* 0x8 - System clock POR Register */ + u8 uart_sel; /* 0x9 - UART1 Connection Control Register */ + u8 sd1refclk_sel; /* 0xA - */ + u8 rgmii_1588_sel; /* 0xB - */ + u8 reg_1588_clk_sel; /* 0xC - */ + u8 status_led; /* 0xD - */ + u8 global_rst; /* 0xE - */ + u8 sd_emmc; /* 0xF - SD/EMMC Interface Control Regsiter */ + u8 vdd_en; /* 0x10 - VDD Voltage Control Enable Register */ + u8 vdd_sel; /* 0x11 - VDD Voltage Control Register */ +}; + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); +void cpld_rev_bit(unsigned char *value); +void cpld_select_core_volt(bool en_0v9); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value) \ + cpld_write(offsetof(struct cpld_data, reg), value) + +/* CPLD on IFC */ +#define CPLD_SW_MUX_BANK_SEL 0x40 +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_SEL_ALTBANK 0x04 +#define CPLD_CFG_RCW_SRC_QSPI 0x044 +#define CPLD_CFG_RCW_SRC_SD 0x040 +#endif diff --git a/board/nxp/ls1046ardb/ddr.c b/board/nxp/ls1046ardb/ddr.c new file mode 100644 index 00000000000..4170666c420 --- /dev/null +++ b/board/nxp/ls1046ardb/ddr.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include "ddr.h" +#ifdef CONFIG_FSL_DEEP_SLEEP +#include +#endif +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + if (popts->registered_dimm_en) + pbsp = rdimms[0]; + else + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + + popts->data_bus_width = 0; /* 64-bit data bus */ + popts->bstopre = 0; /* enable auto precharge */ + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; + + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x61; +} + +#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} +#else +int fsl_initdram(void) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +#else + puts("Initializing DDR....using SPD\n"); + + dram_size = fsl_ddr_sdram(); +#endif + + erratum_a008850_post(); + + gd->ram_size = dram_size; + + return 0; +} +#endif diff --git a/board/nxp/ls1046ardb/ddr.h b/board/nxp/ls1046ardb/ddr.h new file mode 100644 index 00000000000..05baef232ab --- /dev/null +++ b/board/nxp/ls1046ardb/ddr.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + */ + +#ifndef __DDR_H__ +#define __DDR_H__ + +void erratum_a008850_post(void); + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2300, 0, 8, 7, 0x08090A0E, 0x1011120C,}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 1666, 0, 0x8, 0x0D, 0x0C0B0A08, 0x0A0B0C08,}, + {2, 1900, 0, 0x8, 0x0E, 0x0D0C0B09, 0x0B0C0D09,}, + {2, 2300, 0, 0xa, 0x12, 0x100F0D0C, 0x0E0F100C,}, + {1, 1666, 0, 0x8, 0x0D, 0x0C0B0A08, 0x0A0B0C08,}, + {1, 1900, 0, 0x8, 0x0E, 0x0D0C0B09, 0x0B0C0D09,}, + {1, 2300, 0, 0xa, 0x12, 0x100F0D0C, 0x0E0F100C,}, + {} +}; + +static const struct board_specific_parameters *rdimms[] = { + rdimm0, +}; + +#endif diff --git a/board/nxp/ls1046ardb/eth.c b/board/nxp/ls1046ardb/eth.c new file mode 100644 index 00000000000..fee8e0e21d4 --- /dev/null +++ b/board/nxp/ls1046ardb/eth.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/fman.h" + +int board_eth_init(struct bd_info *bis) +{ +#ifdef CONFIG_FMAN_ENET + int i; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + struct mii_dev *dev; + u32 srds_s1; + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); + + /* Set the two on-board SGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR); + + /* Set the on-board AQ PHY address */ + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + + switch (srds_s1) { + case 0x1133: + break; + default: + printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n", + srds_s1); + break; + } + + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) + fm_info_set_mdio(i, dev); + + /* 10GBase-R on lane A, MAC 9 */ + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(FM1_10GEC1, dev); + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} + +#ifdef CONFIG_FMAN_ENET +int fdt_update_ethernet_dt(void *blob) +{ + u32 srds_s1; + int i, prop; + int offset, nodeoff; + const char *path; + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + /* Cycle through all aliases */ + for (prop = 0; ; prop++) { + const char *name; + + /* FDT might have been edited, recompute the offset */ + offset = fdt_first_property_offset(blob, + fdt_path_offset(blob, + "/aliases") + ); + /* Select property number 'prop' */ + for (i = 0; i < prop; i++) + offset = fdt_next_property_offset(blob, offset); + + if (offset < 0) + break; + + path = fdt_getprop_by_offset(blob, offset, &name, NULL); + nodeoff = fdt_path_offset(blob, path); + + switch (srds_s1) { + case 0x1133: + if (!strcmp(name, "ethernet0")) + fdt_status_disabled(blob, nodeoff); + + if (!strcmp(name, "ethernet1")) + fdt_status_disabled(blob, nodeoff); + break; + default: + printf("%s: Invalid SerDes prtcl 0x%x for LS1046ARDB\n", + __func__, srds_s1); + break; + } + } + + return 0; +} +#endif diff --git a/board/nxp/ls1046ardb/ls1046ardb.c b/board/nxp/ls1046ardb/ls1046ardb.c new file mode 100644 index 00000000000..83b280f7646 --- /dev/null +++ b/board/nxp/ls1046ardb/ls1046ardb.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cpld.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct serial_device *default_serial_console(void) +{ +#if IS_ENABLED(CONFIG_SEMIHOSTING_SERIAL) + if (semihosting_enabled()) + return &serial_smh_device; +#endif + return &eserial1_device; +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +#ifndef CONFIG_XPL_BUILD +int checkboard(void) +{ + static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; + u8 cfg_rcw_src1, cfg_rcw_src2; + u16 cfg_rcw_src; + u8 sd1refclk_sel; + + puts("Board: LS1046ARDB, boot from "); + + cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); + cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); + cpld_rev_bit(&cfg_rcw_src1); + cfg_rcw_src = cfg_rcw_src1; + cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; + + if (cfg_rcw_src == 0x44) + printf("QSPI vBank %d\n", CPLD_READ(vbank)); + else if (cfg_rcw_src == 0x40) + puts("SD\n"); + else + puts("Invalid setting of SW5\n"); + + printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), + CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); + + puts("SERDES Reference Clocks:\n"); + sd1refclk_sel = CPLD_READ(sd1refclk_sel); + printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); + + return 0; +} + +int board_init(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; + +#ifdef CONFIG_NXP_ESBC + /* + * In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + u32 val; + val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +#endif + +#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) + pci_init(); +#endif + + /* invert AQR105 IRQ pins polarity */ + out_be32(&scfg->intpcr, AQR105_IRQ_MASK); + + return 0; +} + +int board_setup_core_volt(u32 vdd) +{ + bool en_0v9; + + en_0v9 = (vdd == 900) ? true : false; + cpld_select_core_volt(en_0v9); + + return 0; +} + +int get_serdes_volt(void) +{ + return mc34vr500_get_sw_volt(SW4); +} + +int set_serdes_volt(int svdd) +{ + return mc34vr500_set_sw_volt(SW4, svdd); +} + +int power_init_board(void) +{ + int ret; + + ret = power_mc34vr500_init(0); + if (ret) + return ret; + + setup_chip_volt(); + + return 0; +} + +void config_board_mux(void) +{ +#ifdef CONFIG_HAS_FSL_XHCI_USB + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; + u32 usb_pwrfault; + + /* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */ + out_be32(&scfg->rcwpmuxcr0, 0x3300); + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); + usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << + SCFG_USBPWRFAULT_USB1_SHIFT); + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); +#endif +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + config_board_mux(); + return 0; +} +#endif + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + /* fixup DT for the two DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN +#ifndef CONFIG_DM_ETH + fdt_fixup_fman_ethernet(blob); +#endif +#endif + + fdt_fixup_icid(blob); + + return 0; +} +#endif diff --git a/board/nxp/ls1046ardb/ls1046ardb_pbi.cfg b/board/nxp/ls1046ardb/ls1046ardb_pbi.cfg new file mode 100644 index 00000000000..5478217524d --- /dev/null +++ b/board/nxp/ls1046ardb/ls1046ardb_pbi.cfg @@ -0,0 +1,22 @@ +#Configure Scratch register +09570600 00000000 +09570604 10000000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009e +0957041c 0000009e +09570420 0000009e +#Serdes SATA +09eb1300 80104e20 +09eb08dc 00502880 +#PEX gen3 link +09570158 00000300 +89400890 01048000 +89500890 01048000 +89600890 01048000 +#Alt base register +09570158 00001000 +#flush PBI data +096100c0 000fffff diff --git a/board/nxp/ls1046ardb/ls1046ardb_qspi_pbi.cfg b/board/nxp/ls1046ardb/ls1046ardb_qspi_pbi.cfg new file mode 100644 index 00000000000..735d46c9f9b --- /dev/null +++ b/board/nxp/ls1046ardb/ls1046ardb_qspi_pbi.cfg @@ -0,0 +1,26 @@ +#QSPI clk +0957015c 40100000 +#Configure Scratch register +09570600 00000000 +09570604 10000000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009e +0957041c 0000009e +09570420 0000009e +#Serdes SATA +09eb1300 80104e20 +09eb08dc 00502880 +#PEX gen3 link +09570158 00000300 +89400890 01048000 +89500890 01048000 +89600890 01048000 +#Alt base register +09570158 00001000 +#flush PBI data +096100c0 000fffff +#Change endianness +09550000 000f400c diff --git a/board/nxp/ls1046ardb/ls1046ardb_rcw_emmc.cfg b/board/nxp/ls1046ardb/ls1046ardb_rcw_emmc.cfg new file mode 100644 index 00000000000..ccedf87e849 --- /dev/null +++ b/board/nxp/ls1046ardb/ls1046ardb_rcw_emmc.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +0c150012 0e000000 00000000 00000000 +11335559 40000012 60040000 c1000000 +00000000 00000000 00000000 00238800 +20124000 00003000 00000096 00000001 diff --git a/board/nxp/ls1046ardb/ls1046ardb_rcw_qspi.cfg b/board/nxp/ls1046ardb/ls1046ardb_rcw_qspi.cfg new file mode 100644 index 00000000000..7b9be0ad3f8 --- /dev/null +++ b/board/nxp/ls1046ardb/ls1046ardb_rcw_qspi.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +0c150010 0e000000 00000000 00000000 +11335559 40005012 40025000 c1000000 +00000000 00000000 00000000 00238800 +20124000 00003101 00000096 00000001 diff --git a/board/nxp/ls1046ardb/ls1046ardb_rcw_sd.cfg b/board/nxp/ls1046ardb/ls1046ardb_rcw_sd.cfg new file mode 100644 index 00000000000..d3b152282f2 --- /dev/null +++ b/board/nxp/ls1046ardb/ls1046ardb_rcw_sd.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +0c150012 0e000000 00000000 00000000 +11335559 40005012 60040000 c1000000 +00000000 00000000 00000000 00238800 +20124000 00003101 00000096 00000001 diff --git a/board/nxp/ls1088a/Kconfig b/board/nxp/ls1088a/Kconfig new file mode 100644 index 00000000000..976fd3ae748 --- /dev/null +++ b/board/nxp/ls1088a/Kconfig @@ -0,0 +1,31 @@ +if TARGET_LS1088AQDS + +config SYS_BOARD + default "ls1088a" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1088aqds" + +endif + +if TARGET_LS1088ARDB + +config SYS_BOARD + default "ls1088a" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1088ardb" + +endif diff --git a/board/nxp/ls1088a/MAINTAINERS b/board/nxp/ls1088a/MAINTAINERS new file mode 100644 index 00000000000..85f38fcf0c7 --- /dev/null +++ b/board/nxp/ls1088a/MAINTAINERS @@ -0,0 +1,35 @@ +LS1088ARDB BOARD +M: Ashish Kumar +S: Maintained +F: board/nxp/ls1088a/ +F: include/configs/ls1088ardb.h +F: configs/ls1088ardb_qspi_defconfig +F: configs/ls1088ardb_sdcard_qspi_defconfig +F: configs/ls1088ardb_tfa_defconfig +F: configs/ls1088ardb_tfa_SECURE_BOOT_defconfig + +LS1088AQDS BOARD +M: Ashish Kumar +S: Maintained +F: board/nxp/ls1088a/ +F: include/configs/ls1088aqds.h +F: configs/ls1088aqds_qspi_defconfig +F: configs/ls1088aqds_sdcard_qspi_defconfig +F: configs/ls1088aqds_defconfig +F: configs/ls1088aqds_sdcard_ifc_defconfig +F: configs/ls1088aqds_tfa_defconfig + +LS1088AQDS_QSPI_SECURE_BOOT BOARD +M: Udit Agarwal +S: Maintained +F: configs/ls1088aqds_qspi_SECURE_BOOT_defconfig + +LS1088ARDB_QSPI_SECURE_BOOT BOARD +M: Udit Agarwal +S: Maintained +F: configs/ls1088ardb_qspi_SECURE_BOOT_defconfig + +LS1088ARDB_SD_SECURE_BOOT BOARD +M: Udit Agarwal +S: Maintained +F: configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig diff --git a/board/nxp/ls1088a/Makefile b/board/nxp/ls1088a/Makefile new file mode 100644 index 00000000000..e54d6cad9e1 --- /dev/null +++ b/board/nxp/ls1088a/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2017 NXP + +obj-y += ls1088a.o +obj-y += ddr.o +ifndef CONFIG_XPL_BUILD +obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o +obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o +endif diff --git a/board/nxp/ls1088a/README b/board/nxp/ls1088a/README new file mode 100644 index 00000000000..5315909defc --- /dev/null +++ b/board/nxp/ls1088a/README @@ -0,0 +1,145 @@ +Overview +-------- +The LS1088A Reference Design (RDB) is a high-performance computing, +evaluation, and development platform that supports ARM SoC LS1088A and its +derivatives. + + +LS1088A SoC Overview +-------------------------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc + +RDB Default Switch Settings (1: ON; 0: OFF) +------------------------------------------- + +For QSPI Boot +SW1 0011 0001 +SW2 x100 0000 +SW3 1111 0010 +SW4 1001 0011 +SW5 1111 0000 + +For SD Boot +SW1 0010 0000 +SW2 0100 0000 +SW3 1111 0010 +SW4 1001 0011 +SW5 1111 0000 + +For eMMC Boot +SW1 0010 0000 +SW2 1100 0000 +SW3 1111 0010 +SW4 1001 0011 +SW5 1111 0000 + +Alternately you can use this command to switch from QSPI to SD + +=> i2c mw 66 0x60 0x20; i2c mw 66 10 10;i2c mw 66 10 21 + + LS1088ARDB board Overview + ------------------------- + - SERDES Connections, 16 lanes supporting: + - PCI Express - 3.0 + - SATA 3.0 + - 10GBase-R + - QSGMII + - DDR Controller + - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four + chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default + with FSL refernce software is 2100MT/s + - 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB + - IFC/Local Bus + - One 2 GB NAND flash with ECC support, not as boot source + - CPLD of size 2K + - USB 3.0 + - Two high speed USB 3.0 ports + - First USB 3.0 port configured as Host with Type-A connector + - Second USB 3.0 port configured as OTG with micro-AB connector + - SDHC/eMMC + - SDHC slot and onboard eMMC are muxed together + - 4 I2C controllers + - Two SATA onboard connectors + - 2 UART + - JTAG support + - QSPI emulator support + - TDM riser support + +QDS Default Switch Settings (1: ON; 0: OFF) +------------------------------------------- + +For 16b IFC-NOR +SW1 0001 0010 +SW2 x110 1111 + +For QSPI Boot +SW1 0011 0001 +SW2 0110 1111 + +For SD Boot +SW1 0010 0000 +SW2 0110 1111 + +For eMMC Boot +SW1 0010 0000 +SW2 1110 1111 + +For I2C (ext. addr.) +SW1 0010 0100 +SW2 1110 1111 + +SW3 to SW12 are identical for all boot source + +SW3 0010 0100 +SW4 0010 0000 +SW5 1110 0111 +SW6 1110 1000 +SW7 0001 1101 +SW8 0000 1101 +SW9 1100 1010 +SW10 1110 1000 +SW11 1111 0100 +SW12 1111 1111 + + LS1088AQDS board Overview + ------------------------- + - SERDES Connections, 16 lanes supporting: + - PCI Express - 3.0 + - SATA 3.0 + - 2 10GBase-R + - QSGMII, SGMII with help for Riser card + - 2 RGMII + - 5 slot for Riser card or PCIe NIC + - DDR Controller + - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four + chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default + with FSL refernce software is 2100MT/s + - 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB + - IFC/Local Bus + - One 2 GB NAND flash with ECC support, not as boot source + - CPLD of size 2K + - USB 3.0 + - Two high speed USB 3.0 ports + - First USB 3.0 port configured as Host with Type-A connector + - Second USB 3.0 port configured as OTG with micro-AB connector + - SDHC/eMMC + - SDHC/eMMC slot via adaptor + - 4 I2C controllers + - Two SATA onboard connectors + - 2 UART + - JTAG support + - DSPI + - PROMJET support + - QSPI emulator support + - TDM riser support + +QSPI flash memory map valid for both QDS and RDB + Image Flash Offset + RCW+PBI 0x00000000 + Boot firmware (U-Boot) 0x00100000 + Boot firmware Environment 0x00300000 + PPA firmware 0x00400000 + DPAA2 MC 0x00A00000 + DPAA2 DPL 0x00D00000 + DPAA2 DPC 0x00E00000 + Kernel.itb 0x01000000 diff --git a/board/nxp/ls1088a/ddr.c b/board/nxp/ls1088a/ddr.c new file mode 100644 index 00000000000..cd590af9534 --- /dev/null +++ b/board/nxp/ls1088a/ddr.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 NXP + */ + +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)) +static void fsl_ddr_setup_0v9_volt(memctl_options_t *popts) +{ + int vdd; + + vdd = get_core_volt_from_fuse(); + /* Nothing to do for silicons doesn't support VID */ + if (vdd < 0) + return; + + if (vdd == 900) { + popts->ddr_cdr1 |= DDR_CDR1_V0PT9_EN; + debug("VID: configure DDR to support 900 mV\n"); + } +} +#endif + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + /* + * we use identical timing for all slots. If needed, change the code + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; + */ + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* Enable DDR hashing */ + popts->addr_hash = 1; + + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); +#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)) + fsl_ddr_setup_0v9_volt(popts); +#endif + + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | + DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; +} + +#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} +#else +int fsl_initdram(void) +{ + puts("Initializing DDR....using SPD\n"); + +#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) + gd->ram_size = fsl_ddr_sdram_size(); +#else + gd->ram_size = fsl_ddr_sdram(); +#endif + return 0; +} +#endif /* CONFIG_TFABOOT */ diff --git a/board/nxp/ls1088a/ddr.h b/board/nxp/ls1088a/ddr.h new file mode 100644 index 00000000000..b35c4ae2dad --- /dev/null +++ b/board/nxp/ls1088a/ddr.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + */ + +#ifndef __LS1088A_DDR_H__ +#define __LS1088A_DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ +#if defined(CONFIG_TARGET_LS1088ARDB) + + {2, 1666, 0, 8, 8, 0x090A0B0E, 0x0F10110D,}, + {2, 1900, 0, 8, 9, 0x0A0B0C10, 0x1112140E,}, + {2, 2300, 0, 8, 9, 0x0A0C0E11, 0x1214160F,}, + {} +#elif defined(CONFIG_TARGET_LS1088AQDS) + {2, 1666, 0, 8, 8, 0x0A0A0C0E, 0x0F10110C,}, + {2, 1900, 0, 8, 9, 0x0A0B0C10, 0x1112140E,}, + {2, 2300, 0, 4, 9, 0x0A0C0D11, 0x1214150E,}, + {} + +#endif +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; +#endif diff --git a/board/nxp/ls1088a/eth_ls1088aqds.c b/board/nxp/ls1088a/eth_ls1088aqds.c new file mode 100644 index 00000000000..e6033d251c5 --- /dev/null +++ b/board/nxp/ls1088a/eth_ls1088aqds.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 NXP + */ + +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_RESET_PHY_R) +void reset_phy(void) +{ + mc_env_boot(); +} +#endif /* CONFIG_RESET_PHY_R */ + +#if defined(CONFIG_MULTI_DTB_FIT) + +/* Structure to hold SERDES protocols supported (network interfaces are + * described in the DTS). + * + * @serdes_block: the index of the SERDES block + * @serdes_protocol: the decimal value of the protocol supported + * @dts_needed: DTS notes describing the current configuration are needed + * + * When dts_needed is true, the board_fit_config_name_match() function + * will try to exactly match the current configuration of the block with a DTS + * name provided. + */ +static struct serdes_configuration { + u8 serdes_block; + u32 serdes_protocol; + bool dts_needed; +} supported_protocols[] = { + /* Serdes block #1 */ + {1, 21, true}, + {1, 29, true}, +}; + +#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) + +static bool protocol_supported(u8 serdes_block, u32 protocol) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) + return true; + } + + return false; +} + +static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) { + if (serdes_conf.dts_needed == true) + sprintf(str, "%u", protocol); + else + sprintf(str, "x"); + return; + } + } +} + +int board_fit_config_name_match(const char *name) +{ + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + char expected_dts[100]; + char srds_s1_str[2]; + u32 srds_s1, cfg; + + cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & + FSL_CHASSIS3_SRDS1_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; + srds_s1 = serdes_get_number(FSL_SRDS_1, cfg); + + /* Check for supported protocols. The default DTS will be used + * in this case + */ + if (!protocol_supported(1, srds_s1)) + return -1; + + get_str_protocol(1, srds_s1, srds_s1_str); + + sprintf(expected_dts, "fsl-ls1088a-qds-%s-x", srds_s1_str); + + if (!strcmp(name, expected_dts)) + return 0; + + return -1; +} +#endif diff --git a/board/nxp/ls1088a/eth_ls1088ardb.c b/board/nxp/ls1088a/eth_ls1088ardb.c new file mode 100644 index 00000000000..fb6f9c1a813 --- /dev/null +++ b/board/nxp/ls1088a/eth_ls1088ardb.c @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 NXP + */ + +#include + +#if defined(CONFIG_RESET_PHY_R) +void reset_phy(void) +{ + mc_env_boot(); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/nxp/ls1088a/ls1088a.c b/board/nxp/ls1088a/ls1088a.c new file mode 100644 index 00000000000..51ec055be63 --- /dev/null +++ b/board/nxp/ls1088a/ls1088a.c @@ -0,0 +1,1041 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2022 NXP + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/i2c_mux.h" + +#include "../common/qixis.h" +#include "ls1088a_qixis.h" +#include "../common/vid.h" +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_TARGET_LS1088AQDS +#ifdef CONFIG_TFABOOT +struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nor0", + CFG_SYS_NOR0_CSPR_EARLY, + CFG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, + { + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 + }, + 0, + CFG_SYS_NOR0_CSPR, + 0, + }, + { + "nor1", + CFG_SYS_NOR1_CSPR_EARLY, + CFG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR_AMASK_EARLY, + CFG_SYS_NOR_CSOR, + { + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 + }, + 0, + CFG_SYS_NOR1_CSPR, + CFG_SYS_NOR_AMASK, + }, + { + "nand", + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, + { + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 + }, + }, + { + "fpga", + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, + { + SYS_FPGA_CS_FTIM0, + SYS_FPGA_CS_FTIM1, + SYS_FPGA_CS_FTIM2, + SYS_FPGA_CS_FTIM3 + }, + 0, + SYS_FPGA_CSPR_FINAL, + 0, + } +}; + +struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { + { + "nand", + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, + { + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 + }, + }, + { + "reserved", + }, + { + "fpga", + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, + { + SYS_FPGA_CS_FTIM0, + SYS_FPGA_CS_FTIM1, + SYS_FPGA_CS_FTIM2, + SYS_FPGA_CS_FTIM3 + }, + 0, + SYS_FPGA_CSPR_FINAL, + 0, + } +}; + +void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) +{ + enum boot_src src = get_boot_src(); + + if (src == BOOT_SOURCE_QSPI_NOR) + regs_info->regs = ifc_cfg_qspi_nor_boot; + else + regs_info->regs = ifc_cfg_ifc_nor_boot; + + regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; +} +#endif /* CONFIG_TFABOOT */ +#endif /* CONFIG_TARGET_LS1088AQDS */ + +int board_early_init_f(void) +{ +#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS) + i2c_early_init_f(); +#endif + fsl_lsch3_early_init_f(); + return 0; +} + +#ifdef CONFIG_FSL_QIXIS +unsigned long long get_qixis_addr(void) +{ + unsigned long long addr; + + if (gd->flags & GD_FLG_RELOC) + addr = QIXIS_BASE_PHYS; + else + addr = QIXIS_BASE_PHYS_EARLY; + + /* + * IFC address under 256MB is mapped to 0x30000000, any address above + * is mapped to 0x5_10000000 up to 4GB. + */ + addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; + + return addr; +} +#endif + +#if defined(CONFIG_VID) +static int setup_core_voltage(void) +{ + if (adjust_vdd(0) < 0) + printf("core voltage not adjusted\n"); + + return 0; +} +EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, setup_core_voltage); + +u16 soc_get_fuse_vid(int vid_index) +{ + static const u16 vdd[32] = { + 10250, + 9875, + 9750, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 9000, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 10000, /* 1.0000V */ + 10125, + 10250, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + }; + + return vdd[vid_index]; +}; +#endif + +int is_pb_board(void) +{ + u8 board_id; + + board_id = QIXIS_READ(id); + if (board_id == LS1088ARDB_PB_BOARD) + return 1; + else + return 0; +} + +int fixup_ls1088ardb_pb_banner(void *fdt) +{ + fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board"); + + return 0; +} + +#if !defined(CONFIG_XPL_BUILD) +int checkboard(void) +{ +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); +#endif + char buf[64]; + u8 sw; + static const char *const freq[] = {"100", "125", "156.25", + "100 separate SSCG"}; + int clock; + +#ifdef CONFIG_TARGET_LS1088AQDS + printf("Board: LS1088A-QDS, "); +#else + if (is_pb_board()) + printf("Board: LS1088ARDB-PB, "); + else + printf("Board: LS1088A-RDB, "); +#endif + + sw = QIXIS_READ(arch); + printf("Board Arch: V%d, ", sw >> 4); + +#ifdef CONFIG_TARGET_LS1088AQDS + printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); +#else + printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); +#endif + + memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + +#ifdef CONFIG_TFABOOT + if (src == BOOT_SOURCE_SD_MMC) + puts("SD card\n"); +#else +#ifdef CONFIG_SD_BOOT + puts("SD card\n"); +#endif +#endif /* CONFIG_TFABOOT */ + switch (sw) { +#ifdef CONFIG_TARGET_LS1088AQDS + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + printf("vBank: %d\n", sw); + break; + case 8: + puts("PromJet\n"); + break; + case 15: + puts("IFCCard\n"); + break; + case 14: +#else + case 0: +#endif + puts("QSPI:"); + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT; + if (sw == 0 || sw == 4) + puts("0\n"); + else if (sw == 1) + puts("1\n"); + else + puts("EMU\n"); + break; + + default: + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); + break; + } + +#ifdef CONFIG_TARGET_LS1088AQDS + printf("FPGA: v%d (%s), build %d", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + /* the timestamp string contains "\n" at the end */ + printf(" on %s", qixis_read_time(buf)); +#else + printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); +#endif + + /* + * Display the actual SERDES reference clocks as configured by the + * dip switches on the board. Note that the SWx registers could + * technically be set to force the reference clocks to match the + * values that the SERDES expects (or vice versa). For now, however, + * we just display both values and hope the user notices when they + * don't match. + */ + puts("SERDES1 Reference : "); + sw = QIXIS_READ(brdcfg[2]); + clock = (sw >> 6) & 3; + printf("Clock1 = %sMHz ", freq[clock]); + clock = (sw >> 4) & 3; + printf("Clock2 = %sMHz", freq[clock]); + + puts("\nSERDES2 Reference : "); + clock = (sw >> 2) & 3; + printf("Clock1 = %sMHz ", freq[clock]); + clock = (sw >> 0) & 3; + printf("Clock2 = %sMHz\n", freq[clock]); + + return 0; +} +#endif + +bool if_board_diff_clk(void) +{ +#ifdef CONFIG_TARGET_LS1088AQDS + u8 diff_conf = QIXIS_READ(brdcfg[11]); + return diff_conf & 0x40; +#else + u8 diff_conf = QIXIS_READ(dutcfg[11]); + return diff_conf & 0x80; +#endif +} + +#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0f) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + + return 66666666; +} +#endif + +#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + if (if_board_diff_clk()) + return get_board_sys_clk(); + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + + return 66666666; +} +#endif + +#if !defined(CONFIG_XPL_BUILD) +void board_retimer_init(void) +{ + u8 reg; + + /* Retimer is connected to I2C1_CH5 */ + select_i2c_ch_pca9547(I2C_MUX_CH5, 0); + + /* Access to Control/Shared register */ + reg = 0x0; +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); +#else + struct udevice *dev; + + i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev); + dm_i2c_write(dev, 0xff, ®, 1); +#endif + + /* Read device revision and ID */ +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); +#else + dm_i2c_read(dev, 1, ®, 1); +#endif + debug("Retimer version id = 0x%x\n", reg); + + /* Enable Broadcast. All writes target all channel register sets */ + reg = 0x0c; +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); +#else + dm_i2c_write(dev, 0xff, ®, 1); +#endif + + /* Reset Channel Registers */ +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); +#else + dm_i2c_read(dev, 0, ®, 1); +#endif + reg |= 0x4; +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); +#else + dm_i2c_write(dev, 0, ®, 1); +#endif + + /* Set data rate as 10.3125 Gbps */ + reg = 0x90; +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); +#else + dm_i2c_write(dev, 0x60, ®, 1); +#endif + reg = 0xb3; +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); +#else + dm_i2c_write(dev, 0x61, ®, 1); +#endif + reg = 0x90; +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); +#else + dm_i2c_write(dev, 0x62, ®, 1); +#endif + reg = 0xb3; +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); +#else + dm_i2c_write(dev, 0x63, ®, 1); +#endif + reg = 0xcd; +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); +#else + dm_i2c_write(dev, 0x64, ®, 1); +#endif + + /* Select VCO Divider to full rate (000) */ +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); +#else + dm_i2c_read(dev, 0x2F, ®, 1); +#endif + reg &= 0x0f; + reg |= 0x70; +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1); +#else + dm_i2c_write(dev, 0x2F, ®, 1); +#endif + +#ifdef CONFIG_TARGET_LS1088AQDS + /* Retimer is connected to I2C1_CH5 */ + select_i2c_ch_pca9547(I2C_MUX_CH5, 0); + + /* Access to Control/Shared register */ + reg = 0x0; +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); +#else + i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev); + dm_i2c_write(dev, 0xff, ®, 1); +#endif + + /* Read device revision and ID */ +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1); +#else + dm_i2c_read(dev, 1, ®, 1); +#endif + debug("Retimer version id = 0x%x\n", reg); + + /* Enable Broadcast. All writes target all channel register sets */ + reg = 0x0c; +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1); +#else + dm_i2c_write(dev, 0xff, ®, 1); +#endif + + /* Reset Channel Registers */ +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1); +#else + dm_i2c_read(dev, 0, ®, 1); +#endif + reg |= 0x4; +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1); +#else + dm_i2c_write(dev, 0, ®, 1); +#endif + + /* Set data rate as 10.3125 Gbps */ + reg = 0x90; +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1); +#else + dm_i2c_write(dev, 0x60, ®, 1); +#endif + reg = 0xb3; +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1); +#else + dm_i2c_write(dev, 0x61, ®, 1); +#endif + reg = 0x90; +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1); +#else + dm_i2c_write(dev, 0x62, ®, 1); +#endif + reg = 0xb3; +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1); +#else + dm_i2c_write(dev, 0x63, ®, 1); +#endif + reg = 0xcd; +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1); +#else + dm_i2c_write(dev, 0x64, ®, 1); +#endif + + /* Select VCO Divider to full rate (000) */ +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); +#else + dm_i2c_read(dev, 0x2F, ®, 1); +#endif + reg &= 0x0f; + reg |= 0x70; +#if !CONFIG_IS_ENABLED(DM_I2C) + i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1); +#else + dm_i2c_write(dev, 0x2F, ®, 1); +#endif + +#endif + /*return the default channel*/ + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_TARGET_LS1088ARDB + u8 brdcfg5; + + if (hwconfig("esdhc-force-sd")) { + brdcfg5 = QIXIS_READ(brdcfg[5]); + brdcfg5 &= ~BRDCFG5_SPISDHC_MASK; + brdcfg5 |= BRDCFG5_FORCE_SD; + QIXIS_WRITE(brdcfg[5], brdcfg5); + } +#endif + +#ifdef CONFIG_TARGET_LS1088AQDS + u8 brdcfg4, brdcfg5; + + if (hwconfig("dspi-on-board")) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_USBOSC_MASK; + brdcfg4 |= BRDCFG4_SPI; + QIXIS_WRITE(brdcfg[4], brdcfg4); + + brdcfg5 = QIXIS_READ(brdcfg[5]); + brdcfg5 &= ~BRDCFG5_SPR_MASK; + brdcfg5 |= BRDCFG5_SPI_ON_BOARD; + QIXIS_WRITE(brdcfg[5], brdcfg5); + } else if (hwconfig("dspi-off-board")) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_USBOSC_MASK; + brdcfg4 |= BRDCFG4_SPI; + QIXIS_WRITE(brdcfg[4], brdcfg4); + + brdcfg5 = QIXIS_READ(brdcfg[5]); + brdcfg5 &= ~BRDCFG5_SPR_MASK; + brdcfg5 |= BRDCFG5_SPI_OFF_BOARD; + QIXIS_WRITE(brdcfg[5], brdcfg5); + } +#endif + return 0; +} +#endif +#endif + +int i2c_multiplexer_select_vid_channel(u8 channel) +{ + return select_i2c_ch_pca9547(channel, 0); +} + +#ifdef CONFIG_TARGET_LS1088AQDS +/* read the current value(SVDD) of the LTM Regulator Voltage */ +int get_serdes_volt(void) +{ + int ret, vcode = 0; + u8 chan = PWM_CHANNEL0; + + /* Select the PAGE 0 using PMBus commands PAGE for VDD */ +#if !CONFIG_IS_ENABLED(DM_I2C) + ret = i2c_write(I2C_SVDD_MONITOR_ADDR, + PMBUS_CMD_PAGE, 1, &chan, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, + &chan, 1); +#endif + + if (ret) { + printf("VID: failed to select VDD Page 0\n"); + return ret; + } + + /* Read the output voltage using PMBus command READ_VOUT */ +#if !CONFIG_IS_ENABLED(DM_I2C) + ret = i2c_read(I2C_SVDD_MONITOR_ADDR, + PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); +#else + dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2); +#endif + if (ret) { + printf("VID: failed to read the voltage\n"); + return ret; + } + + return vcode; +} + +int set_serdes_volt(int svdd) +{ + int ret, vdd_last; + u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, + svdd & 0xFF, (svdd & 0xFF00) >> 8}; + + /* Write the desired voltage code to the SVDD regulator */ +#if !CONFIG_IS_ENABLED(DM_I2C) + ret = i2c_write(I2C_SVDD_MONITOR_ADDR, + PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE, + (void *)&buff, 5); +#endif + if (ret) { + printf("VID: I2C failed to write to the voltage regulator\n"); + return -1; + } + + /* Wait for the voltage to get to the desired value */ + do { + vdd_last = get_serdes_volt(); + if (vdd_last < 0) { + printf("VID: Couldn't read sensor abort VID adjust\n"); + return -1; + } + } while (vdd_last != svdd); + + return 1; +} +#else +int get_serdes_volt(void) +{ + return 0; +} + +int set_serdes_volt(int svdd) +{ + int ret; + u8 brdcfg4; + + printf("SVDD changing of RDB\n"); + + /* Read the BRDCFG54 via CLPD */ +#if !CONFIG_IS_ENABLED(DM_I2C) + ret = i2c_read(CFG_SYS_I2C_FPGA_ADDR, + QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET, + (void *)&brdcfg4, 1); +#endif + + if (ret) { + printf("VID: I2C failed to read the CPLD BRDCFG4\n"); + return -1; + } + + brdcfg4 = brdcfg4 | 0x08; + + /* Write to the BRDCFG4 */ +#if !CONFIG_IS_ENABLED(DM_I2C) + ret = i2c_write(CFG_SYS_I2C_FPGA_ADDR, + QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); +#else + ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET, + (void *)&brdcfg4, 1); +#endif + + if (ret) { + debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n"); + return -1; + } + + /* Wait for the voltage to get to the desired value */ + udelay(10000); + + return 1; +} +#endif + +/* this function disables the SERDES, changes the SVDD Voltage and enables it*/ +int board_adjust_vdd(int vdd) +{ + int ret = 0; + + debug("%s: vdd = %d\n", __func__, vdd); + + /* Special settings to be performed when voltage is 900mV */ + if (vdd == 900) { + ret = setup_serdes_volt(vdd); + if (ret < 0) { + ret = -1; + goto exit; + } + } +exit: + return ret; +} + +#if !defined(CONFIG_XPL_BUILD) +int board_init(void) +{ + init_final_memctl_regs(); +#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) + u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; +#endif + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); + board_retimer_init(); + +#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET) + /* invert AQR105 IRQ pins polarity */ + out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK); +#endif + +#if !defined(CONFIG_SYS_EARLY_PCI_INIT) + pci_init(); +#endif + + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); + print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_ddr_info(0); +} + +#ifdef CONFIG_FSL_MC_ENET +void board_quiesce_devices(void) +{ + fsl_mc_ldpaa_exit(gd->bd); +} + +void fdt_fixup_board_enet(void *fdt) +{ + int offset; + + offset = fdt_path_offset(fdt, "/fsl-mc"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/soc/fsl-mc"); + + if (offset < 0) { + printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", + __func__, offset); + return; + } + + if (get_mc_boot_status() == 0 && + (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) + fdt_status_okay(fdt, offset); + else + fdt_status_fail(fdt, offset); +} +#endif + +#ifdef CONFIG_OF_BOARD_SETUP +void fsl_fdt_fixup_flash(void *fdt) +{ + int offset; +#ifdef CONFIG_TFABOOT + u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; + u32 val; +#endif + +/* + * IFC-NOR and QSPI are muxed on SoC. + * So disable IFC node in dts if QSPI is enabled or + * disable QSPI node in dts in case QSPI is not enabled. + */ + +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); + bool disable_ifc = false; + + switch (src) { + case BOOT_SOURCE_IFC_NOR: + disable_ifc = false; + break; + case BOOT_SOURCE_QSPI_NOR: + disable_ifc = true; + break; + default: + val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4); + if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3)) + disable_ifc = true; + break; + } + + if (disable_ifc) { + offset = fdt_path_offset(fdt, "/soc/memory-controller/nor"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/memory-controller/nor"); + } else { + offset = fdt_path_offset(fdt, "/soc/quadspi"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/quadspi"); + } + +#else +#ifdef CONFIG_FSL_QSPI + offset = fdt_path_offset(fdt, "/soc/memory-controller/nor"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/memory-controller/nor"); +#else + offset = fdt_path_offset(fdt, "/soc/quadspi"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/quadspi"); +#endif +#endif + if (offset < 0) + return; + + fdt_status_disabled(fdt, offset); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + int i; + u16 mc_memory_bank = 0; + + u64 *base; + u64 *size; + u64 mc_memory_base = 0; + u64 mc_memory_size = 0; + u16 total_memory_banks; + + ft_cpu_setup(blob, bd); + + fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); + + if (mc_memory_base != 0) + mc_memory_bank++; + + total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; + + base = calloc(total_memory_banks, sizeof(u64)); + if (!base) + return -ENOMEM; + + size = calloc(total_memory_banks, sizeof(u64)); + if (!size) { + free(base); + return -ENOMEM; + } + + /* fixup DT for the two GPP DDR banks */ + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + base[i] = gd->bd->bi_dram[i].start; + size[i] = gd->bd->bi_dram[i].size; + } + +#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; +#endif + + if (mc_memory_base != 0) { + for (i = 0; i <= total_memory_banks; i++) { + if (base[i] == 0 && size[i] == 0) { + base[i] = mc_memory_base; + size[i] = mc_memory_size; + break; + } + } + } + + fdt_fixup_memory_banks(blob, base, size, total_memory_banks); + + fdt_fsl_mc_fixup_iommu_map_entry(blob); + + fsl_fdt_fixup_flash(blob); + +#ifdef CONFIG_FSL_MC_ENET + fdt_fixup_board_enet(blob); + fdt_reserve_mc_mem(blob, 0x300); +#endif + + fdt_fixup_icid(blob); + + if (is_pb_board()) + fixup_ls1088ardb_pb_banner(blob); + + return 0; +} +#endif +#endif /* defined(CONFIG_XPL_BUILD) */ + +#ifdef CONFIG_TFABOOT +#ifdef CONFIG_MTD_NOR_FLASH +int is_flash_available(void) +{ + char *env_hwconfig = env_get("hwconfig"); + enum boot_src src = get_boot_src(); + int is_nor_flash_available = 1; + + switch (src) { + case BOOT_SOURCE_IFC_NOR: + is_nor_flash_available = 1; + break; + case BOOT_SOURCE_QSPI_NOR: + is_nor_flash_available = 0; + break; + /* + * In Case of SD boot,if qspi is defined in env_hwconfig + * disable nor flash probe. + */ + default: + if (hwconfig_f("qspi", env_hwconfig)) + is_nor_flash_available = 0; + break; + } + return is_nor_flash_available; +} +#endif + +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH +void *env_sf_get_env_addr(void) +{ + return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); +} +#endif +#endif diff --git a/board/nxp/ls1088a/ls1088a_qixis.h b/board/nxp/ls1088a/ls1088a_qixis.h new file mode 100644 index 00000000000..e3502eb1d19 --- /dev/null +++ b/board/nxp/ls1088a/ls1088a_qixis.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + */ + +#ifndef __LS1088AQDS_QIXIS_H__ +#define __LS1088AQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for LS1088AQDS */ + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +/* BRDCFG2 - SD clock*/ +#define QIXIS_SDCLK1_100 0x0 +#define QIXIS_SDCLK1_125 0x1 +#define QIXIS_SDCLK1_165 0x2 +#define QIXIS_SDCLK1_100_SP 0x3 + +#define BRDCFG4_EMISEL_MASK 0xE0 +#define BRDCFG4_EMISEL_SHIFT 5 +#define BRDCFG9_SFPTX_MASK 0x10 +#define BRDCFG9_SFPTX_SHIFT 4 + +/* Definitions of QIXIS Registers for LS1088ARDB */ + +/* BRDCFG5 */ +#define BRDCFG5_SPISDHC_MASK 0x0C +#define BRDCFG5_FORCE_SD 0x08 + +/* Definitions of QIXIS Registers for LS1088AQDS */ + +/* BRDCFG4 */ +#define BRDCFG4_USBOSC_MASK 0x01 +#define BRDCFG4_SPI 0x01 + +/* BRDCFG5 */ +#define BRDCFG5_SPR_MASK 0x0f +#define BRDCFG5_SPI_ON_BOARD 0x0a +#define BRDCFG5_SPI_OFF_BOARD 0x0f + +#endif diff --git a/board/nxp/ls2080aqds/Kconfig b/board/nxp/ls2080aqds/Kconfig new file mode 100644 index 00000000000..dc2a5f83134 --- /dev/null +++ b/board/nxp/ls2080aqds/Kconfig @@ -0,0 +1,16 @@ + +if TARGET_LS2080AQDS + +config SYS_BOARD + default "ls2080aqds" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls2080aqds" + +endif diff --git a/board/nxp/ls2080aqds/MAINTAINERS b/board/nxp/ls2080aqds/MAINTAINERS new file mode 100644 index 00000000000..3659cec4cd8 --- /dev/null +++ b/board/nxp/ls2080aqds/MAINTAINERS @@ -0,0 +1,13 @@ +LS2080A BOARD +M: Priyanka Jain +M: Wasim Khan +S: Maintained +F: board/nxp/ls2080aqds/ +F: board/nxp/ls2080a/ls2080aqds.c +F: include/configs/ls2080aqds.h +F: configs/ls2080aqds_defconfig +F: configs/ls2080aqds_nand_defconfig +F: configs/ls2080aqds_qspi_defconfig +F: configs/ls2080aqds_sdcard_defconfig +F: configs/ls2088aqds_tfa_defconfig +F: configs/ls2080aqds_SECURE_BOOT_defconfig diff --git a/board/nxp/ls2080aqds/Makefile b/board/nxp/ls2080aqds/Makefile new file mode 100644 index 00000000000..efc51b4a34d --- /dev/null +++ b/board/nxp/ls2080aqds/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2015 Freescale Semiconductor + +obj-y += ls2080aqds.o +obj-y += ddr.o +obj-y += eth.o diff --git a/board/nxp/ls2080aqds/README b/board/nxp/ls2080aqds/README new file mode 100644 index 00000000000..a4cb1a6cac4 --- /dev/null +++ b/board/nxp/ls2080aqds/README @@ -0,0 +1,215 @@ +Overview +-------- +The LS2080A Development System (QDS) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS2080A +and LS2088A Layerscape Architecture processor. The LS2080AQDS provides +validation and SW development platform for the Freescale LS2080A, LS2088A +processor series, with a complete debugging environment. + +LS2080A, LS2088A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A, +LS2088A SoC overview. + + LS2080AQDS board Overview + ----------------------- + - SERDES Connections, 16 lanes supporting: + - PCI Express - 3.0 + - SGMII, SGMII 2.5 + - QSGMII + - SATA 3.0 + - XAUI + - 10GBase-R + - DDR Controller + - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four + chip-selects and two DIMM connectors. Support is up to 2133MT/s. + - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects + and two DIMM connectors. Support is up to 1600MT/s. + -IFC/Local Bus + - IFC rev. 2.0 implementation supporting Little Endian connection scheme. + - One in-socket 128 MB NOR flash 16-bit data bus + - One 512 MB NAND flash with ECC support + - IFC Test Port + - PromJet Port + - FPGA connection + - USB 3.0 + - Two high speed USB 3.0 ports + - First USB 3.0 port configured as Host with Type-A connector + - Second USB 3.0 port configured as OTG with micro-AB connector + - SDHC: PCIe x1 Right Angle connector for supporting following cards + - 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only + - 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only + - 4-bit eMMC Card Rev 4.4 (1.8V only) + - 8-bit eMMC Card Rev 4.5 (1.8V only) + - SD Card Rev 2.0 and Rev 3.0 + - DSPI: 3 high-speed flash Memory for storage + - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz) + - 8 MB high-speed flash Memory (up to 104 MHz) + - 512 MB low-speed flash Memory (up to 40 MHz) + - QSPI: via NAND/QSPI Card + - 4 I2C controllers + - Two SATA onboard connectors + - UART + - Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s + - Two DB9 D-Type connectors supporting one Serial port each + - ARM JTAG support + +Memory map from core's view +---------------------------- +0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom +0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR +0x00_1800_0000 .. 0x00_181F_FFFF OCRAM +0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1 +0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1 +0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 +0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 + +Other addresses are either reserved, or not used directly by U-Boot. +This list should be updated when more addresses are used. + +IFC region map from core's view +------------------------------- +During boot i.e. IFC Region #1:- + 0x30000000 - 0x37ffffff : 128MB : NOR flash + 0x38000000 - 0x3BFFFFFF : 64MB : Promjet + 0x3C000000 - 0x40000000 : 64MB : FPGA etc + +After relocate to DDR i.e. IFC Region #2:- + 0x5_1000_0000..0x5_1fff_ffff Memory Hole + 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) + 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB + 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) + 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) + +Booting Options +--------------- +a) Promjet Boot +b) NOR boot +c) NAND boot +d) SD boot +e) QSPI boot + +Memory map for NOR boot +------------------------- +Image Flash Offset +RCW+PBI 0x00000000 +Boot firmware (U-Boot) 0x00100000 +Boot firmware Environment 0x00300000 +PPA firmware 0x00400000 +Secure Headers 0x00600000 +DPAA2 MC 0x00A00000 +DPAA2 DPL 0x00D00000 +DPAA2 DPC 0x00E00000 +Kernel.itb 0x01000000 + +Memory map for SD boot +------------------------- +Image Flash Offset SD Card + Start Block No. +RCW+PBI 0x00000000 0x00008 +Boot firmware (U-Boot) 0x00100000 0x00800 +Boot firmware Environment 0x00300000 0x01800 +PPA firmware 0x00400000 0x02000 +DPAA2 MC 0x00A00000 0x05000 +DPAA2 DPL 0x00D00000 0x06800 +DPAA2 DPC 0x00E00000 0x07000 +Kernel.itb 0x01000000 0x08000 + +Environment Variables +--------------------- +- mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined + the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. + +- mcmemsize: MC DRAM block size. If this variable is not defined + the value CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. + +Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) +------------------------------------------------------------------- +One needs to use appropriate bootargs to boot Linux flavors which do +not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown +below: + +=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram + earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m + hugepages=16 mem=2048M' + + +X-QSGMII-16PORT riser card +---------------------------- +The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes +interfaces implemented in PCIe form factor board. +It supports following: + - Card can operate with up to 4 QSGMII lane simultaneously + - Card can operate with up to 8 SGMII lane simultaneously + +Supported card configuration + - CSEL : ON ON ON ON + - MSEL1 : ON ON ON ON OFF OFF OFF OFF + - MSEL2 : OFF OFF OFF OFF ON ON ON ON + +To enable this card: modify hwconfig to add "xqsgmii" variable. + +Supported PHY addresses during SGMII: +#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 +#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 +#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 +#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 +#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 +#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa +#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc +#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe + +Mapping DPMACx to PHY during SGMII +DPMAC1 -> PHY1-P0 +DPMAC2 -> PHY2-P0 +DPMAC3 -> PHY3-P0 +DPMAC4 -> PHY4-P0 +DPMAC5 -> PHY3-P2 +DPMAC6 -> PHY1-P2 +DPMAC7 -> PHY4-P1 +DPMAC8 -> PHY2-P2 +DPMAC9 -> PHY1-P0 +DPMAC10 -> PHY2-P0 +DPMAC11 -> PHY3-P0 +DPMAC12 -> PHY4-P0 +DPMAC13 -> PHY3-P2 +DPMAC14 -> PHY1-P2 +DPMAC15 -> PHY4-P1 +DPMAC16 -> PHY2-P2 + + +Supported PHY address during QSGMII +#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 +#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 +#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 +#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 +#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 +#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 +#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 +#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 +#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 +#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 +#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa +#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb +#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc +#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd +#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe +#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf + +Mapping DPMACx to PHY during QSGMII +DPMAC1 -> PHY1-P3 +DPMAC2 -> PHY1-P2 +DPMAC3 -> PHY1-P1 +DPMAC4 -> PHY1-P0 +DPMAC5 -> PHY2-P3 +DPMAC6 -> PHY2-P2 +DPMAC7 -> PHY2-P1 +DPMAC8 -> PHY2-P0 +DPMAC9 -> PHY3-P0 +DPMAC10 -> PHY3-P1 +DPMAC11 -> PHY3-P2 +DPMAC12 -> PHY3-P3 +DPMAC13 -> PHY4-P0 +DPMAC14 -> PHY4-P1 +DPMAC15 -> PHY4-P2 +DPMAC16 -> PHY4-P3 diff --git a/board/nxp/ls2080aqds/ddr.c b/board/nxp/ls2080aqds/ddr.c new file mode 100644 index 00000000000..31ed72c949b --- /dev/null +++ b/board/nxp/ls2080aqds/ddr.c @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR + u8 dq_mapping_0, dq_mapping_2, dq_mapping_3; +#endif + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + int slot; + + if (ctrl_num > 2) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + + for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) { + if (pdimm[slot].n_ranks) + break; + } + + if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR) + return; + + /* + * we use identical timing for all slots. If needed, change the code + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; + */ + if (popts->registered_dimm_en) + pbsp = rdimms[ctrl_num]; + else + pbsp = udimms[ctrl_num]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(ctrl_num) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm[slot].n_ranks && + (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for data rate %lu MT/s\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR + if (ctrl_num == CONFIG_DP_DDR_CTRL) { + /* force DDR bus width to 32 bits */ + popts->data_bus_width = 1; + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + popts->bstopre = 0; /* enable auto precharge */ + /* + * Layout optimization results byte mapping + * Byte 0 -> Byte ECC + * Byte 1 -> Byte 3 + * Byte 2 -> Byte 2 + * Byte 3 -> Byte 1 + * Byte ECC -> Byte 0 + */ + dq_mapping_0 = pdimm[slot].dq_mapping[0]; + dq_mapping_2 = pdimm[slot].dq_mapping[2]; + dq_mapping_3 = pdimm[slot].dq_mapping[3]; + pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8]; + pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9]; + pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6]; + pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7]; + pdimm[slot].dq_mapping[6] = dq_mapping_2; + pdimm[slot].dq_mapping[7] = dq_mapping_3; + pdimm[slot].dq_mapping[8] = dq_mapping_0; + pdimm[slot].dq_mapping[9] = 0; + pdimm[slot].dq_mapping[10] = 0; + pdimm[slot].dq_mapping[11] = 0; + pdimm[slot].dq_mapping[12] = 0; + pdimm[slot].dq_mapping[13] = 0; + pdimm[slot].dq_mapping[14] = 0; + pdimm[slot].dq_mapping[15] = 0; + pdimm[slot].dq_mapping[16] = 0; + pdimm[slot].dq_mapping[17] = 0; + } +#endif + /* To work at higher than 1333MT/s */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0x0; /* 32 clocks */ + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + if (ddr_freq < 2350) { + if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) { + /* four chip-selects */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | + DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm); + popts->twot_en = 1; /* enable 2T timing */ + } else { + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | + DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | + DDR_CDR2_VREF_RANGE_2; + } + } else { + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | + DDR_CDR1_ODT(DDR_CDR_ODT_100ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) | + DDR_CDR2_VREF_RANGE_2; + } +} + +#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} +#else +int fsl_initdram(void) +{ +#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) + gd->ram_size = fsl_ddr_sdram_size(); +#else + puts("Initializing DDR....using SPD\n"); + + gd->ram_size = fsl_ddr_sdram(); +#endif + + return 0; +} +#endif /* CONFIG_TFABOOT */ diff --git a/board/nxp/ls2080aqds/ddr.h b/board/nxp/ls2080aqds/ddr.h new file mode 100644 index 00000000000..465155e56bf --- /dev/null +++ b/board/nxp/ls2080aqds/ddr.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2300, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, + {} +}; + +/* DP-DDR DIMM */ +static const struct board_specific_parameters udimm2[] = { + /* + * memory controller 2 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, + {2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, + {2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, + {2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, + {} +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, + {} +}; + +/* DP-DDR DIMM */ +static const struct board_specific_parameters rdimm2[] = { + /* + * memory controller 2 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, + udimm0, + udimm2, +}; + +static const struct board_specific_parameters *rdimms[] = { + rdimm0, + rdimm0, + rdimm2, +}; + +#endif diff --git a/board/nxp/ls2080aqds/eth.c b/board/nxp/ls2080aqds/eth.c new file mode 100644 index 00000000000..b47e2ec5a79 --- /dev/null +++ b/board/nxp/ls2080aqds/eth.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include + +#define MC_BOOT_ENV_VAR "mcinitcmd" + +#if defined(CONFIG_RESET_PHY_R) +void reset_phy(void) +{ + mc_env_boot(); +} +#endif /* CONFIG_RESET_PHY_R */ + +#if defined(CONFIG_MULTI_DTB_FIT) + +/* Structure to hold SERDES protocols supported (network interfaces are + * described in the DTS). + * + * @serdes_block: the index of the SERDES block + * @serdes_protocol: the decimal value of the protocol supported + * @dts_needed: DTS notes describing the current configuration are needed + * + * When dts_needed is true, the board_fit_config_name_match() function + * will try to exactly match the current configuration of the block with a DTS + * name provided. + */ +static struct serdes_configuration { + u8 serdes_block; + u32 serdes_protocol; + bool dts_needed; +} supported_protocols[] = { + /* Serdes block #1 */ + {1, 42, true}, + + /* Serdes block #2 */ + {2, 65, false}, +}; + +#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) + +static bool protocol_supported(u8 serdes_block, u32 protocol) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) + return true; + } + + return false; +} + +static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) { + if (serdes_conf.dts_needed == true) + sprintf(str, "%u", protocol); + else + sprintf(str, "x"); + return; + } + } +} + +int board_fit_config_name_match(const char *name) +{ + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + u32 rcw_status = in_le32(&gur->rcwsr[28]); + char srds_s1_str[2], srds_s2_str[2]; + u32 srds_s1, srds_s2; + char expected_dts[100]; + + srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + + /* Check for supported protocols. The default DTS will be used + * in this case + */ + if (!protocol_supported(1, srds_s1) || + !protocol_supported(2, srds_s2)) + return -1; + + get_str_protocol(1, srds_s1, srds_s1_str); + get_str_protocol(2, srds_s2, srds_s2_str); + + printf("expected_dts %s\n", expected_dts); + sprintf(expected_dts, "fsl-ls2080a-qds-%s-%s", + srds_s1_str, srds_s2_str); + + if (!strcmp(name, expected_dts)) + return 0; + + printf("this is not!\n"); + return -1; +} + +#endif diff --git a/board/nxp/ls2080aqds/ls2080aqds.c b/board/nxp/ls2080aqds/ls2080aqds.c new file mode 100644 index 00000000000..aba0560181a --- /dev/null +++ b/board/nxp/ls2080aqds/ls2080aqds.c @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Freescale Semiconductor + * Copyright 2021 NXP + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/i2c_mux.h" + +#include "../common/qixis.h" +#include "ls2080aqds_qixis.h" +#include "../common/vid.h" + +#define PIN_MUX_SEL_SDHC 0x00 +#define PIN_MUX_SEL_DSPI 0x0a +#define SCFG_QSPICLKCTRL_DIV_20 (5 << 27) + +#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) + +DECLARE_GLOBAL_DATA_PTR; + +enum { + MUX_TYPE_SDHC, + MUX_TYPE_DSPI, +}; + +unsigned long long get_qixis_addr(void) +{ + unsigned long long addr; + + if (gd->flags & GD_FLG_RELOC) + addr = QIXIS_BASE_PHYS; + else + addr = QIXIS_BASE_PHYS_EARLY; + + /* + * IFC address under 256MB is mapped to 0x30000000, any address above + * is mapped to 0x5_10000000 up to 4GB. + */ + addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; + + return addr; +} + +int checkboard(void) +{ + char buf[64]; + u8 sw; + static const char *const freq[] = {"100", "125", "156.25", + "100 separate SSCG"}; + int clock; + + cpu_name(buf); + printf("Board: %s-QDS, ", buf); + + sw = QIXIS_READ(arch); + printf("Board Arch: V%d, ", sw >> 4); + printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); + + memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("PromJet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else if (sw == 0xf) + puts("QSPI\n"); + else if (sw == 0x15) + printf("IFCCard\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); + + printf("FPGA: v%d (%s), build %d", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + /* the timestamp string contains "\n" at the end */ + printf(" on %s", qixis_read_time(buf)); + + /* + * Display the actual SERDES reference clocks as configured by the + * dip switches on the board. Note that the SWx registers could + * technically be set to force the reference clocks to match the + * values that the SERDES expects (or vice versa). For now, however, + * we just display both values and hope the user notices when they + * don't match. + */ + puts("SERDES1 Reference : "); + sw = QIXIS_READ(brdcfg[2]); + clock = (sw >> 6) & 3; + printf("Clock1 = %sMHz ", freq[clock]); + clock = (sw >> 4) & 3; + printf("Clock2 = %sMHz", freq[clock]); + + puts("\nSERDES2 Reference : "); + clock = (sw >> 2) & 3; + printf("Clock1 = %sMHz ", freq[clock]); + clock = (sw >> 0) & 3; + printf("Clock2 = %sMHz\n", freq[clock]); + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +int config_board_mux(int ctrl_type) +{ + u8 reg5; + + reg5 = QIXIS_READ(brdcfg[5]); + + switch (ctrl_type) { + case MUX_TYPE_SDHC: + reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); + break; + case MUX_TYPE_DSPI: + reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); + break; + default: + printf("Wrong mux interface type\n"); + return -1; + } + + QIXIS_WRITE(brdcfg[5], reg5); + + return 0; +} + +int board_init(void) +{ + char *env_hwconfig; + u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; + u32 val; + + init_final_memctl_regs(); + + val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); + + env_hwconfig = env_get("hwconfig"); + + if (hwconfig_f("dspi", env_hwconfig) && + DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) + config_board_mux(MUX_TYPE_DSPI); + else + config_board_mux(MUX_TYPE_SDHC); + +#if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_FSL_QSPI) + val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4); + + if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3)) + QIXIS_WRITE(brdcfg[9], + (QIXIS_READ(brdcfg[9]) & 0xf8) | + FSL_QIXIS_BRDCFG9_QSPI); +#endif + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); + +#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT +#if CONFIG_IS_ENABLED(DM_I2C) + rtc_enable_32khz_output(0, CFG_SYS_I2C_RTC_ADDR); +#else + rtc_enable_32khz_output(); +#endif +#endif + +#if !defined(CONFIG_SYS_EARLY_PCI_INIT) + pci_init(); +#endif + + return 0; +} + +int board_early_init_f(void) +{ +#if defined(CONFIG_SYS_I2C_EARLY_INIT) + i2c_early_init_f(); +#endif + fsl_lsch3_early_init_f(); +#ifdef CONFIG_FSL_QSPI + /* input clk: 1/2 platform clk, output: input/20 */ + out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20); +#endif + return 0; +} + +int misc_init_r(void) +{ + if (adjust_vdd(0)) + printf("Warning: Adjusting core voltage failed.\n"); + + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); + print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_ddr_info(0); +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR + if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { + puts("\nDP-DDR "); + print_size(gd->bd->bi_dram[2].size, ""); + print_ddr_info(CONFIG_DP_DDR_CTRL); + } +#endif +} + +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) +void fdt_fixup_board_enet(void *fdt) +{ + int offset; + + offset = fdt_path_offset(fdt, "/soc/fsl-mc"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/fsl-mc"); + + if (offset < 0) { + printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", + __func__, offset); + return; + } + + if (get_mc_boot_status() == 0 && + (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) + fdt_status_okay(fdt, offset); + else + fdt_status_fail(fdt, offset); +} + +void board_quiesce_devices(void) +{ + fsl_mc_ldpaa_exit(gd->bd); +} +#endif + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + ft_cpu_setup(blob, bd); + + /* fixup DT for the two GPP DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + +#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; +#endif + + fdt_fixup_memory_banks(blob, base, size, 2); + + fdt_fsl_mc_fixup_iommu_map_entry(blob); + + fsl_fdt_fixup_dr_usb(blob, bd); + +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) + fdt_fixup_board_enet(blob); + fdt_reserve_mc_mem(blob, 0x300); +#endif + + fdt_fixup_icid(blob); + + return 0; +} +#endif + +void qixis_dump_switch(void) +{ + int i, nr_of_cfgsw; + + QIXIS_WRITE(cms[0], 0x00); + nr_of_cfgsw = QIXIS_READ(cms[1]); + + puts("DIP switch settings dump:\n"); + for (i = 1; i <= nr_of_cfgsw; i++) { + QIXIS_WRITE(cms[0], i); + printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); + } +} diff --git a/board/nxp/ls2080aqds/ls2080aqds_qixis.h b/board/nxp/ls2080aqds/ls2080aqds_qixis.h new file mode 100644 index 00000000000..7b2607b8daa --- /dev/null +++ b/board/nxp/ls2080aqds/ls2080aqds_qixis.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __LS2_QDS_QIXIS_H__ +#define __LS2_QDS_QIXIS_H__ + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +#define BRDCFG4_EMISEL_MASK 0xE0 +#define BRDCFG4_EMISEL_SHIFT 5 +#define BRDCFG9_SFPTX_MASK 0x10 +#define BRDCFG9_SFPTX_SHIFT 4 +#endif /*__LS2_QDS_QIXIS_H__*/ diff --git a/board/nxp/ls2080ardb/Kconfig b/board/nxp/ls2080ardb/Kconfig new file mode 100644 index 00000000000..1f057a7690b --- /dev/null +++ b/board/nxp/ls2080ardb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS2080ARDB || TARGET_LS2081ARDB + +config SYS_BOARD + default "ls2080ardb" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls2080ardb" + +endif diff --git a/board/nxp/ls2080ardb/MAINTAINERS b/board/nxp/ls2080ardb/MAINTAINERS new file mode 100644 index 00000000000..867ebe99cac --- /dev/null +++ b/board/nxp/ls2080ardb/MAINTAINERS @@ -0,0 +1,32 @@ +LS2080A BOARD +M: Priyanka Jain +M: Wasim Khan +S: Maintained +F: board/nxp/ls2080ardb/ +F: board/nxp/ls2080a/ls2080ardb.c +F: include/configs/ls2080ardb.h +F: configs/ls2080ardb_defconfig +F: configs/ls2080ardb_nand_defconfig + +LS2088A_QSPI-boot BOARD +M: Priyanka Jain +M: Wasim Khan +S: Maintained +F: configs/ls2088ardb_qspi_defconfig +F: configs/ls2088ardb_tfa_defconfig +F: configs/ls2088ardb_tfa_SECURE_BOOT_defconfig + +LS2081ARDB BOARD +M: Priyanka Jain +S: Maintained +F: configs/ls2081ardb_defconfig + +LS2080A_SECURE_BOOT BOARD +M: Udit Agarwal +S: Maintained +F: configs/ls2080ardb_SECURE_BOOT_defconfig + +LS2088A_QSPI_SECURE_BOOT BOARD +M: Udit Agarwal +S: Maintained +F: configs/ls2088ardb_qspi_SECURE_BOOT_defconfig diff --git a/board/nxp/ls2080ardb/Makefile b/board/nxp/ls2080ardb/Makefile new file mode 100644 index 00000000000..ed44d459f01 --- /dev/null +++ b/board/nxp/ls2080ardb/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2015 Freescale Semiconductor + +obj-y += ls2080ardb.o eth_ls2080rdb.o +obj-y += ddr.o diff --git a/board/nxp/ls2080ardb/README b/board/nxp/ls2080ardb/README new file mode 100644 index 00000000000..4c1c36ea3a5 --- /dev/null +++ b/board/nxp/ls2080ardb/README @@ -0,0 +1,134 @@ +Overview +-------- +The LS2080A Reference Design (RDB) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS2080A, LS2088A +Layerscape Architecture processor. + +The LS2081A Reference Design (RDB) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS2081A +Layerscape Architecture processor.More details in below sections + +LS2080A, LS2088A, LS2081A SoC Overview +-------------------------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A, +LS2081A, LS2088A SoC overview. + + LS2080ARDB board Overview + ----------------------- + - SERDES Connections, 16 lanes supporting: + - PCI Express - 3.0 + - SATA 3.0 + - 10GBase-R + - DDR Controller + - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four + chip-selects and two DIMM connectors. Support is up to 2133MT/s. + - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects + and two DIMM connectors. Support is up to 1600MT/s. + -IFC/Local Bus + - IFC rev. 2.0 implementation supporting Little Endian connection scheme. + - 128 MB NOR flash 16-bit data bus + - One 2 GB NAND flash with ECC support + - CPLD connection + - USB 3.0 + - Two high speed USB 3.0 ports + - First USB 3.0 port configured as Host with Type-A connector + - Second USB 3.0 port configured as OTG with micro-AB connector + - SDHC adapter + - SD Card Rev 2.0 and Rev 3.0 + - DSPI + - 128 MB high-speed flash Memory for boot code and storage (up to 108MHz) + - 4 I2C controllers + - Two SATA onboard connectors + - UART + - ARM JTAG support + + LS2081ARDB board Overview + ------------------------- + LS2081ARDB board is similar to LS2080ARDB board + with few differences like + - Hosts LS2081A SoC + - Default boot source is QSPI-boot + - Does not have IFC interface + - RTC and QSPI flash devices are different + - Provides QIXIS access via I2C + +Memory map from core's view +---------------------------- +0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom +0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR +0x00_1800_0000 .. 0x00_181F_FFFF OCRAM +0x00_2000_0000 .. 0x00_2FFF_FFFF QSPI region #1 +0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1 +0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1 +0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 +0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2 + +Other addresses are either reserved, or not used directly by U-Boot. +This list should be updated when more addresses are used. + +IFC region map from core's view +------------------------------- +During boot i.e. IFC Region #1:- + 0x30000000 - 0x37ffffff : 128MB : NOR flash + 0x3C000000 - 0x40000000 : 64MB : CPLD + +After relocate to DDR i.e. IFC Region #2:- + 0x5_1000_0000..0x5_1fff_ffff Memory Hole + 0x5_2000_0000..0x5_3fff_ffff IFC CSx (CPLD, NAND and others 512MB) + 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB + 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) + 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) + +Booting Options +--------------- +a) NOR boot +b) NAND boot +c) QSPI boot + +Memory map for NOR boot +------------------------- +Image Flash Offset +RCW+PBI 0x00000000 +Boot firmware (U-Boot) 0x00100000 +Boot firmware Environment 0x00300000 +PPA firmware 0x00400000 +Secure Headers 0x00600000 +Cortina PHY firmware 0x00980000 +DPAA2 MC 0x00A00000 +DPAA2 DPL 0x00D00000 +DPAA2 DPC 0x00E00000 +Kernel.itb 0x01000000 + +cfg_rcw_src switches needs to be changed for booting from different option. +Refer to board documentation for correct switch setting. + +QSPI boot details +=================== +Supported only for + LS2088ARDB RevF board with LS2088A SoC. + +Images needs to be copied to QSPI flash +as per memory map given below. + +Memory map for QSPI flash +------------------------- +Image Flash Offset +RCW+PBI 0x00000000 +Boot firmware (U-Boot) 0x00100000 +Boot firmware Environment 0x00300000 +PPA firmware 0x00400000 +Cortina PHY firmware 0x00980000 +DPAA2 MC 0x00A00000 +DPAA2 DPL 0x00D00000 +DPAA2 DPC 0x00E00000 +Kernel.itb 0x01000000 + +Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) +------------------------------------------------------------------- +One needs to use appropriate bootargs to boot Linux flavors which do +not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown +below: + +=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram + earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m + hugepages=16 mem=2048M' diff --git a/board/nxp/ls2080ardb/ddr.c b/board/nxp/ls2080ardb/ddr.c new file mode 100644 index 00000000000..e56667c846f --- /dev/null +++ b/board/nxp/ls2080ardb/ddr.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR + u8 dq_mapping_0, dq_mapping_2, dq_mapping_3; +#endif + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + int slot; + + if (ctrl_num > 2) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + + for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) { + if (pdimm[slot].n_ranks) + break; + } + + if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR) + return; + + /* + * we use identical timing for all slots. If needed, change the code + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; + */ + if (popts->registered_dimm_en) + pbsp = rdimms[ctrl_num]; + else + pbsp = udimms[ctrl_num]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(ctrl_num) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm[slot].n_ranks && + (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for data rate %lu MT/s\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR + if (ctrl_num == CONFIG_DP_DDR_CTRL) { + if (popts->registered_dimm_en) + printf("WARN: RDIMM not supported.\n"); + /* force DDR bus width to 32 bits */ + popts->data_bus_width = 1; + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + popts->bstopre = 0; /* enable auto precharge */ + /* + * Layout optimization results byte mapping + * Byte 0 -> Byte ECC + * Byte 1 -> Byte 3 + * Byte 2 -> Byte 2 + * Byte 3 -> Byte 1 + * Byte ECC -> Byte 0 + */ + dq_mapping_0 = pdimm[slot].dq_mapping[0]; + dq_mapping_2 = pdimm[slot].dq_mapping[2]; + dq_mapping_3 = pdimm[slot].dq_mapping[3]; + pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8]; + pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9]; + pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6]; + pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7]; + pdimm[slot].dq_mapping[6] = dq_mapping_2; + pdimm[slot].dq_mapping[7] = dq_mapping_3; + pdimm[slot].dq_mapping[8] = dq_mapping_0; + pdimm[slot].dq_mapping[9] = 0; + pdimm[slot].dq_mapping[10] = 0; + pdimm[slot].dq_mapping[11] = 0; + pdimm[slot].dq_mapping[12] = 0; + pdimm[slot].dq_mapping[13] = 0; + pdimm[slot].dq_mapping[14] = 0; + pdimm[slot].dq_mapping[15] = 0; + pdimm[slot].dq_mapping[16] = 0; + pdimm[slot].dq_mapping[17] = 0; + } +#endif + /* To work at higher than 1333MT/s */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0x0; /* 32 clocks */ + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x6e; + + if (ddr_freq < 2350) { + if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) { + /* four chip-selects */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | + DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm); + popts->twot_en = 1; /* enable 2T timing */ + } else { + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | + DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | + DDR_CDR2_VREF_RANGE_2; + } + } else { + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | + DDR_CDR1_ODT(DDR_CDR_ODT_100ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) | + DDR_CDR2_VREF_RANGE_2; + } +} + +#ifdef CONFIG_TFABOOT +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} +#else +int fsl_initdram(void) +{ +#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) + gd->ram_size = fsl_ddr_sdram_size(); +#else + puts("Initializing DDR....using SPD\n"); + + gd->ram_size = fsl_ddr_sdram(); +#endif + + return 0; +} +#endif /* CONFIG_TFABOOT */ diff --git a/board/nxp/ls2080ardb/ddr.h b/board/nxp/ls2080ardb/ddr.h new file mode 100644 index 00000000000..43301dc72a3 --- /dev/null +++ b/board/nxp/ls2080ardb/ddr.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 10, 9, 0x090A0B0E, 0x0F11110C,}, + {2, 1900, 0, 12, 0xA, 0x0B0C0E11, 0x1214140F,}, + {2, 2300, 0, 12, 0xB, 0x0C0D0F12, 0x14161610,}, + {} +}; + +/* DP-DDR DIMM */ +static const struct board_specific_parameters udimm2[] = { + /* + * memory controller 2 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, + {2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, + {2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, + {2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, + {} +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 1666, 0, 8, 0x0F, 0x0D0C0A09, 0x0B0C0E08,}, + {2, 1900, 0, 8, 0x10, 0x0F0D0B0A, 0x0B0E0F09,}, + {2, 2200, 0, 8, 0x13, 0x120F0E0B, 0x0D10110B,}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, + udimm0, + udimm2, +}; + +static const struct board_specific_parameters *rdimms[] = { + rdimm0, + rdimm0, + udimm2, /* DP-DDR doesn't support RDIMM */ +}; + +#endif diff --git a/board/nxp/ls2080ardb/eth_ls2080rdb.c b/board/nxp/ls2080ardb/eth_ls2080rdb.c new file mode 100644 index 00000000000..7d5beb32417 --- /dev/null +++ b/board/nxp/ls2080ardb/eth_ls2080rdb.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_eth_init(struct bd_info *bis) +{ + +#if defined(CONFIG_PHY_AQUANTIA) && !defined(CONFIG_XPL_BUILD) + /* + * Export functions to be used by AQ firmware + * upload application + */ + gd->jt->strcpy = strcpy; + gd->jt->mdelay = mdelay; + gd->jt->mdio_get_current_dev = mdio_get_current_dev; + gd->jt->phy_find_by_mask = phy_find_by_mask; + gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; + gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; +#endif + + return 0; +} + +#if defined(CONFIG_RESET_PHY_R) +void reset_phy(void) +{ + mc_env_boot(); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/nxp/ls2080ardb/ls2080ardb.c b/board/nxp/ls2080ardb/ls2080ardb.c new file mode 100644 index 00000000000..6f824f57c47 --- /dev/null +++ b/board/nxp/ls2080ardb/ls2080ardb.c @@ -0,0 +1,571 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Freescale Semiconductor + * Copyright 2017, 2021 NXP + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/i2c_mux.h" + +#ifdef CONFIG_FSL_QIXIS +#include "../common/qixis.h" +#include "ls2080ardb_qixis.h" +#endif +#include "../common/vid.h" + +#define CORTINA_FW_ADDR_IFCNOR 0x580980000 +#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0x584980000 +#define CORTINA_FW_ADDR_QSPI 0x980000 +#define PIN_MUX_SEL_SDHC 0x00 +#define PIN_MUX_SEL_DSPI 0x0a + +#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) +DECLARE_GLOBAL_DATA_PTR; + +enum { + MUX_TYPE_SDHC, + MUX_TYPE_DSPI, +}; + +#ifdef CONFIG_VID +u16 soc_get_fuse_vid(int vid_index) +{ + static const u16 vdd[32] = { + 10500, + 0, /* reserved */ + 9750, + 0, /* reserved */ + 9500, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 9000, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 10000, /* 1.0000V */ + 0, /* reserved */ + 10250, + 0, /* reserved */ + 10500, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + }; + + return vdd[vid_index]; +}; +#endif + +unsigned long long get_qixis_addr(void) +{ + unsigned long long addr; + + if (gd->flags & GD_FLG_RELOC) + addr = QIXIS_BASE_PHYS; + else + addr = QIXIS_BASE_PHYS_EARLY; + + /* + * IFC address under 256MB is mapped to 0x30000000, any address above + * is mapped to 0x5_10000000 up to 4GB. + */ + addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; + + return addr; +} + +int checkboard(void) +{ +#ifdef CONFIG_FSL_QIXIS + u8 sw; +#endif + char buf[15]; + + cpu_name(buf); + printf("Board: %s-RDB, ", buf); + +#ifdef CONFIG_TARGET_LS2081ARDB +#ifdef CONFIG_FSL_QIXIS + sw = QIXIS_READ(arch); + printf("Board version: %c, ", (sw & 0xf) + 'A'); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK; + switch (sw) { + case 0: + puts("boot from QSPI DEV#0\n"); + puts("QSPI_CSA_1 mapped to QSPI DEV#1\n"); + break; + case 1: + puts("boot from QSPI DEV#1\n"); + puts("QSPI_CSA_1 mapped to QSPI DEV#0\n"); + break; + case 2: + puts("boot from QSPI EMU\n"); + puts("QSPI_CSA_1 mapped to QSPI DEV#0\n"); + break; + case 3: + puts("boot from QSPI EMU\n"); + puts("QSPI_CSA_1 mapped to QSPI DEV#1\n"); + break; + case 4: + puts("boot from QSPI DEV#0\n"); + puts("QSPI_CSA_1 mapped to QSPI EMU\n"); + break; + default: + printf("invalid setting of SW%u\n", sw); + break; + } + printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); +#endif + puts("SERDES1 Reference : "); + printf("Clock1 = 100MHz "); + printf("Clock2 = 161.13MHz"); +#else +#ifdef CONFIG_FSL_QIXIS + sw = QIXIS_READ(arch); + printf("Board Arch: V%d, ", sw >> 4); + printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x9) + puts("NAND\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); + + printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); +#endif + puts("SERDES1 Reference : "); + printf("Clock1 = 156.25MHz "); + printf("Clock2 = 156.25MHz"); +#endif + + puts("\nSERDES2 Reference : "); + printf("Clock1 = 100MHz "); + printf("Clock2 = 100MHz\n"); + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ +#ifdef CONFIG_FSL_QIXIS + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } +#endif + return 100000000; +} + +int i2c_multiplexer_select_vid_channel(u8 channel) +{ + return select_i2c_ch_pca9547(channel, 0); +} + +int config_board_mux(int ctrl_type) +{ +#ifdef CONFIG_FSL_QIXIS + u8 reg5; + + reg5 = QIXIS_READ(brdcfg[5]); + + switch (ctrl_type) { + case MUX_TYPE_SDHC: + reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); + break; + case MUX_TYPE_DSPI: + reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); + break; + default: + printf("Wrong mux interface type\n"); + return -1; + } + + QIXIS_WRITE(brdcfg[5], reg5); +#endif + return 0; +} + +ulong *cs4340_get_fw_addr(void) +{ +#ifdef CONFIG_TFABOOT + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + u32 svr = gur_in32(&gur->svr); +#endif + ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR; + +#ifdef CONFIG_TFABOOT + /* LS2088A TFA boot */ + if (SVR_SOC_VER(svr) == SVR_LS2088A) { + enum boot_src src = get_boot_src(); + u8 sw; + + switch (src) { + case BOOT_SOURCE_IFC_NOR: + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & 0x0f); + if (sw == 0) + cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR; + else if (sw == 4) + cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK; + break; + case BOOT_SOURCE_QSPI_NOR: + /* Only one bank in QSPI */ + cortina_fw_addr = CORTINA_FW_ADDR_QSPI; + break; + default: + printf("WARNING: Boot source not found\n"); + } + } +#endif + return (ulong *)cortina_fw_addr; +} + +int board_init(void) +{ +#ifdef CONFIG_FSL_MC_ENET + u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; +#endif + + init_final_memctl_regs(); + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); + +#ifdef CONFIG_FSL_QIXIS + QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); +#endif + +#ifdef CONFIG_FSL_MC_ENET + /* invert AQR405 IRQ pins polarity */ + out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); +#endif + +#if !defined(CONFIG_SYS_EARLY_PCI_INIT) + pci_init(); +#endif + + return 0; +} + +int board_early_init_f(void) +{ +#if defined(CONFIG_SYS_I2C_EARLY_INIT) + i2c_early_init_f(); +#endif + fsl_lsch3_early_init_f(); + return 0; +} + +int misc_init_r(void) +{ + char *env_hwconfig; + u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; + u32 val; + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + u32 svr = gur_in32(&gur->svr); + + val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); + + env_hwconfig = env_get("hwconfig"); + + if (hwconfig_f("dspi", env_hwconfig) && + DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) + config_board_mux(MUX_TYPE_DSPI); + else + config_board_mux(MUX_TYPE_SDHC); + + /* + * LS2081ARDB RevF board has smart voltage translator + * which needs to be programmed to enable high speed SD interface + * by setting GPIO4_10 output to zero + */ +#ifdef CONFIG_TARGET_LS2081ARDB + out_le32(GPIO4_GPDIR_ADDR, (1 << 21 | + in_le32(GPIO4_GPDIR_ADDR))); + out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) & + in_le32(GPIO4_GPDAT_ADDR))); +#endif + if (hwconfig("sdhc")) + config_board_mux(MUX_TYPE_SDHC); + + if (adjust_vdd(0)) + printf("Warning: Adjusting core voltage failed.\n"); + /* + * Default value of board env is based on filename which is + * ls2080ardb. Modify board env for other supported SoCs + */ + if ((SVR_SOC_VER(svr) == SVR_LS2088A) || + (SVR_SOC_VER(svr) == SVR_LS2048A)) + env_set("board", "ls2088ardb"); + else if ((SVR_SOC_VER(svr) == SVR_LS2081A) || + (SVR_SOC_VER(svr) == SVR_LS2041A)) + env_set("board", "ls2081ardb"); + + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); + print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_ddr_info(0); +#ifdef CONFIG_SYS_FSL_HAS_DP_DDR + if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { + puts("\nDP-DDR "); + print_size(gd->bd->bi_dram[2].size, ""); + print_ddr_info(CONFIG_DP_DDR_CTRL); + } +#endif +} + +#ifdef CONFIG_FSL_MC_ENET +void fdt_fixup_board_enet(void *fdt) +{ + int offset; + + offset = fdt_path_offset(fdt, "/soc/fsl-mc"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/fsl-mc"); + + if (offset < 0) { + printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", + __func__, offset); + return; + } + + if (get_mc_boot_status() == 0 && + (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) + fdt_status_okay(fdt, offset); + else + fdt_status_fail(fdt, offset); +} + +void board_quiesce_devices(void) +{ + fsl_mc_ldpaa_exit(gd->bd); +} +#endif + +#ifdef CONFIG_OF_BOARD_SETUP +void fsl_fdt_fixup_flash(void *fdt) +{ + int offset; +#ifdef CONFIG_TFABOOT + u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; + u32 val; +#endif + +/* + * IFC and QSPI are muxed on board. + * So disable IFC node in dts if QSPI is enabled or + * disable QSPI node in dts in case QSPI is not enabled. + */ +#ifdef CONFIG_TFABOOT + enum boot_src src = get_boot_src(); + bool disable_ifc = false; + + switch (src) { + case BOOT_SOURCE_IFC_NOR: + disable_ifc = false; + break; + case BOOT_SOURCE_QSPI_NOR: + disable_ifc = true; + break; + default: + val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4); + if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3)) + disable_ifc = true; + break; + } + + if (disable_ifc) { + offset = fdt_path_offset(fdt, "/soc/ifc"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/ifc"); + } else { + offset = fdt_path_offset(fdt, "/soc/quadspi"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/quadspi"); + } + +#else +#ifdef CONFIG_FSL_QSPI + offset = fdt_path_offset(fdt, "/soc/ifc"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/ifc"); +#else + offset = fdt_path_offset(fdt, "/soc/quadspi"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/quadspi"); +#endif +#endif + + if (offset < 0) + return; + + fdt_status_disabled(fdt, offset); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + int i; + u16 mc_memory_bank = 0; + + u64 *base; + u64 *size; + u64 mc_memory_base = 0; + u64 mc_memory_size = 0; + u16 total_memory_banks; + + ft_cpu_setup(blob, bd); + + fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); + + if (mc_memory_base != 0) + mc_memory_bank++; + + total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; + + base = calloc(total_memory_banks, sizeof(u64)); + size = calloc(total_memory_banks, sizeof(u64)); + + /* fixup DT for the two GPP DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + +#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; +#endif + + if (mc_memory_base != 0) { + for (i = 0; i <= total_memory_banks; i++) { + if (base[i] == 0 && size[i] == 0) { + base[i] = mc_memory_base; + size[i] = mc_memory_size; + break; + } + } + } + + fdt_fixup_memory_banks(blob, base, size, total_memory_banks); + + fdt_fsl_mc_fixup_iommu_map_entry(blob); + + fsl_fdt_fixup_dr_usb(blob, bd); + + fsl_fdt_fixup_flash(blob); + +#ifdef CONFIG_FSL_MC_ENET + fdt_fixup_board_enet(blob); + fdt_reserve_mc_mem(blob, 0x300); +#endif + + fdt_fixup_icid(blob); + + return 0; +} +#endif + +void qixis_dump_switch(void) +{ +#ifdef CONFIG_FSL_QIXIS + int i, nr_of_cfgsw; + + QIXIS_WRITE(cms[0], 0x00); + nr_of_cfgsw = QIXIS_READ(cms[1]); + + puts("DIP switch settings dump:\n"); + for (i = 1; i <= nr_of_cfgsw; i++) { + QIXIS_WRITE(cms[0], i); + printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); + } +#endif +} + +/* + * Board rev C and earlier has duplicated I2C addresses for 2nd controller. + * Both slots has 0x54, resulting 2nd slot unusable. + */ +void update_spd_address(unsigned int ctrl_num, + unsigned int slot, + unsigned int *addr) +{ +#ifndef CONFIG_TARGET_LS2081ARDB +#ifdef CONFIG_FSL_QIXIS + u8 sw; + + sw = QIXIS_READ(arch); + if ((sw & 0xf) < 0x3) { + if (ctrl_num == 1 && slot == 0) + *addr = SPD_EEPROM_ADDRESS4; + else if (ctrl_num == 1 && slot == 1) + *addr = SPD_EEPROM_ADDRESS3; + } +#endif +#endif +} diff --git a/board/nxp/ls2080ardb/ls2080ardb_qixis.h b/board/nxp/ls2080ardb/ls2080ardb_qixis.h new file mode 100644 index 00000000000..db3c6dc2a2a --- /dev/null +++ b/board/nxp/ls2080ardb/ls2080ardb_qixis.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + */ + +#ifndef __LS2_RDB_QIXIS_H__ +#define __LS2_RDB_QIXIS_H__ + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 + +#endif /*__LS2_RDB_QIXIS_H__*/ diff --git a/board/nxp/lx2160a/Kconfig b/board/nxp/lx2160a/Kconfig new file mode 100644 index 00000000000..5764c83ab08 --- /dev/null +++ b/board/nxp/lx2160a/Kconfig @@ -0,0 +1,47 @@ +if TARGET_LX2160ARDB + +config SYS_BOARD + default "lx2160a" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "lx2160ardb" + +endif + +if TARGET_LX2160AQDS + +config SYS_BOARD + default "lx2160a" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "lx2160aqds" + +endif + +if TARGET_LX2162AQDS + +config SYS_BOARD + default "lx2160a" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "lx2162aqds" + +endif diff --git a/board/nxp/lx2160a/MAINTAINERS b/board/nxp/lx2160a/MAINTAINERS new file mode 100644 index 00000000000..abdac1372d2 --- /dev/null +++ b/board/nxp/lx2160a/MAINTAINERS @@ -0,0 +1,55 @@ +LX2160ARDB BOARD +M: Meenakshi Aggarwal +M: Priyanka Jain +M: Wasim Khan +S: Maintained +F: board/nxp/lx2160a/ +F: include/configs/lx2160a_common.h +F: include/configs/lx2160ardb.h +F: configs/lx2160ardb_tfa_defconfig +F: configs/lx2160ardb_tfa_stmm_defconfig +F: arch/arm/dts/fsl-lx2160a-rdb.dts + +LX2160ARDB_SECURE_BOOT BOARD +M: Udit Agarwal +S: Maintained +F: configs/lx2160ardb_tfa_SECURE_BOOT_defconfig + +LX2160AQDS BOARD +M: Meenakshi Aggarwal +M: Wasim Khan +S: Maintained +F: board/nxp/lx2160a/eth_lx2160aqds.h +F: include/configs/lx2160aqds.h +F: configs/lx2160aqds_tfa_defconfig +F: arch/arm/dts/fsl-lx2160a-qds.dts + +LX2160AQDS_SECURE_BOOT BOARD +M: Udit Agarwal +S: Maintained +F: configs/lx2160aqds_tfa_SECURE_BOOT_defconfig + +LX2162AQDS BOARD +M: Meenakshi Aggarwal +M: Wasim Khan +S: Maintained +F: board/nxp/lx2160a/eth_lx2162aqds.h +F: include/configs/lx2162aqds.h +F: configs/lx2162aqds_tfa_defconfig +F: arch/arm/dts/fsl-lx2162a-qds.dts +F: arch/arm/dts/fsl-lx2162a-qds-17-x.dts +F: arch/arm/dts/fsl-lx2162a-qds-18-x.dts +F: arch/arm/dts/fsl-lx2162a-qds-20-x.dts +F: arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi +F: arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi +F: arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi + +LX2162AQDS_SECURE_BOOT BOARD +M: Manish Tomar +S: Maintained +F: configs/lx2162aqds_tfa_SECURE_BOOT_defconfig + +LX2162AQDS_VERIFIED_BOOT BOARD +M: Manish Tomar +S: Maintained +F: configs/lx2162aqds_tfa_verified_boot_defconfig diff --git a/board/nxp/lx2160a/Makefile b/board/nxp/lx2160a/Makefile new file mode 100644 index 00000000000..c9561bfadea --- /dev/null +++ b/board/nxp/lx2160a/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2018 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += lx2160a.o +obj-y += ddr.o +obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o +obj-$(CONFIG_TARGET_LX2160AQDS) += eth_lx2160aqds.o +obj-$(CONFIG_TARGET_LX2162AQDS) += eth_lx2162aqds.o diff --git a/board/nxp/lx2160a/README b/board/nxp/lx2160a/README new file mode 100644 index 00000000000..7bca98dd3d7 --- /dev/null +++ b/board/nxp/lx2160a/README @@ -0,0 +1,329 @@ +Overview +-------- +The LX2160A Reference Design (RDB) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LX2160A +Layerscape Architecture processor and its personalities. + +LX2160A SoC Overview +-------------------------------------- +For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc + +LX2160ARDB board Overview +---------------------- +DDR Memory + Two ports of 72-bits (8-bits ECC) DDR4. + Each port supports four chip-selects and two DIMM + connectors. Data rate upto 3.2 GT/s. + +SERDES ports + Thress serdes controllers (24 lanes) + Serdes1: Supports two USXGMII connectors, each connected through + Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi + IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi + CS4223 phy. + + Serdes2: Supports one PCIe x4 (Gen1/2/3/4) connector, four SATA 3.0 + connectors + + Serdes3: Supports one PCIe x8 (Gen1/2/3/4) connector + +eSDHC + eSDHC1: Supports a SD connector for connecting SD cards + eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC + +Octal SPI (XSPI) + Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator + for off-board emulation + +I2C All system devices on I2C1 multiplexed using PCA9547 multiplexer + Serial Ports + +USB 3.0 + Two high speed USB 3.0 ports. First USB 3.0 port configured as + Host with Type-A connector, second USB 3.0 port configured as OTG + with micro-AB connector + +Serial Ports Two UART ports +Ethernet Two RGMII interfaces +Debug ARM JTAG support + +Booting Options +--------------- +a) Flexspi boot +b) SD boot + +Memory map for Flexspi flash +---------------------------- +Image Flash Offset +bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl) 0x00000000 +fip.bin (bl31 + bl33(u-boot) + + header for Secure-boot(secure-boot only)) 0x00100000 +Boot firmware Environment 0x00500000 +DDR PHY Firmware (fip_ddr_all.bin) 0x00800000 +DPAA2 MC Firmware 0x00A00000 +DPAA2 DPL 0x00D00000 +DPAA2 DPC 0x00E00000 +Kernel.itb 0x01000000 + +Memory map for sd card +---------------------------- +Image SD card Offset +bl2_sd.pbl (RCW+PBI+bl2.pbl) 0x00008 +fip.bin (bl31 + bl33(u-boot) + + header for Secure-boot(secure-boot only)) 0x00800 +Boot firmware Environment 0x02800 +DDR PHY Firmware (fip_ddr_all.bin) 0x04000 +DPAA2 MC Firmware 0x05000 +DPAA2 DPL 0x06800 +DPAA2 DPC 0x07000 +Kernel.itb 0x08000 + +LX2160AQDS board Overview +---------------------- +Various Mezzanine cards and their connection for different SERDES protocols is +as below: + +SERDES1 |CARDS +----------------------------------------------------------------------- +1 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) + |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111) + |Connect I/O cable to IO_SLOT2(J113) +------------------------------------------------------------------------ +3 |Mezzanine:X-M11-USXGMII (29828) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) + |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111) + |Connect I/O cable to IO_SLOT2(J113) +------------------------------------------------------------------------ +7 |Mezzanine:X-M11-USXGMII (29828) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) + |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111) + |Connect I/O cable to IO_SLOT2(J113) +------------------------------------------------------------------------ +8 |Mezzanine:X-M12-XFI (29829) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) + |Mezzanine:X-M12-XFI (29829) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111) + |Connect I/O cable to IO_SLOT2(J113) +------------------------------------------------------------------------ +13 |Mezzanine:X-M8-100G (29734) + |Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) + |Mezzanine:X-M8-100G (29734) + |Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT2(J111) + |Connect I/O cable to IO_SLOT2(J113) +------------------------------------------------------------------------ +15 |Mezzanine:X-M8-100G (29734) + |Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) + |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111) + |Connect I/O cable to IO_SLOT2(J113) +------------------------------------------------------------------------ +17 |Mezzanine:X-M13-25G (32133) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) + |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111) + |Connect I/O cable to IO_SLOT2(J113) +------------------------------------------------------------------------ +19 |Mezzanine:X-M11-USXGMII (29828), X-M13-25G (32133) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect M11 I/O cable to IO_SLOT1(J110), M13 I/O cable to IO_SLOT6(J125) + |Mezzanine:X-M7-40G (29738) + |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT2 (J111) + |Connect I/O cable to IO_SLOT2(J113) +------------------------------------------------------------------------ +20 |Mezzanine:X-M7-40G (29738) + |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J108) + |Mezzanine:X-M7-40G (29738) + |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT2 (J111) + |Connect I/O cable to IO_SLOT2(J113) +------------------------------------------------------------------------ + + +SERDES2 |CARDS +----------------------------------------------------------------------- +2 |Mezzanine:X-M6-PCIE-X8 (29737) * + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT3(J116) +------------------------------------------------------------------------ +3 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect I/O cable to IO_SLOT3(J116) + |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT4(J119) +------------------------------------------------------------------------ +5 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect I/O cable to IO_SLOT3(J116) + |Mezzanine:X-M5-SATA (29687) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT4(J119) +------------------------------------------------------------------------ +11 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect I/O cable to IO_SLOT7(J127) + |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT8(J131) +------------------------------------------------------------------------ + + +SERDES3 |CARDS +----------------------------------------------------------------------- +2 |Mezzanine:X-M6-PCIE-X8 (29737) * + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT5 (J120) + |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT6 (J123) + |Connect I/O cable to IO_SLOT5(J122) +------------------------------------------------------------------------- +3 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT5 (J120) + |Connect I/O cable to IO_SLOT5(J122) + |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT6 (J123) + |Connect I/O cable to IO_SLOT6(J125) +------------------------------------------------------------------------- + +LX2162A SoC Overview +-------------------------------------- +For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc + +LX2162AQDS board Overview +---------------------- +DDR Memory + One ports of 72-bits (8-bits ECC) DDR4. + Each port supports four chip-selects and two DIMM + connectors. Data rate upto 2.9 GT/s. + +SERDES ports + Two serdes controllers (12 lanes) + Serdes1: Supports two USXGMII connectors, each connected through + Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi + IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi + CS4223 phy. + + Serdes2: Supports two PCIe x4 (Gen3) and one PCIe x8 (Gen3) connector, + four SATA 3.0 connectors + +eSDHC + eSDHC1: Supports a SD connector for connecting SD cards + eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC + +Octal SPI (XSPI) + Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator + for off-board emulation + +I2C All system devices on I2C1 multiplexed using PCA9547 multiplexer + Serial Ports + +USB 3.0 + One high speed USB 3.0 ports. First USB 3.0 port configured as Host + with Type-A connector, second USB 3.0 port configured as OTG with + micro-AB connector + +Serial Ports Two UART ports +Ethernet Two RGMII interfaces +Debug ARM JTAG support + +Booting Options +--------------- +a) Flexspi boot +b) SD boot +c) eMMC boot + +Memory map for Flexspi flash +---------------------------- +Image Flash Offset +bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl) 0x00000000 +fip.bin (bl31 + bl33(u-boot) + + header for Secure-boot(secure-boot only)) 0x00100000 +Boot firmware Environment 0x00500000 +DDR PHY Firmware (fip_ddr_all.bin) 0x00800000 +DPAA2 MC Firmware 0x00A00000 +DPAA2 DPL 0x00D00000 +DPAA2 DPC 0x00E00000 +Kernel.itb 0x01000000 + +Memory map for sd/eMMC card +---------------------------- +Image SD/eMMC card Offset +bl2_sd.pbl (RCW+PBI+bl2.pbl) 0x00008 +fip.bin (bl31 + bl33(u-boot) + + header for Secure-boot(secure-boot only)) 0x00800 +Boot firmware Environment 0x02800 +DDR PHY Firmware (fip_ddr_all.bin) 0x04000 +DPAA2 MC Firmware 0x05000 +DPAA2 DPL 0x06800 +DPAA2 DPC 0x07000 +Kernel.itb 0x08000 + +Various Mezzanine cards and their connection for different SERDES protocols is +as below: + +SERDES1 |CARDS +----------------------------------------------------------------------- +1 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) +------------------------------------------------------------------------ +3 |Mezzanine:X-M11-USXGMII (29828) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) +------------------------------------------------------------------------ +15 |Mezzanine:X-M8-50G (29734) + |Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) +------------------------------------------------------------------------ +17 |Mezzanine:X-M13-25G (32133) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) +------------------------------------------------------------------------ +18 |Mezzanine:X-M11-USXGMII (29828), X-M13-25G (32133) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect M11 I/O cable to IO_SLOT1(J110), M13 I/O cable to IO_SLOT6(J125) +------------------------------------------------------------------------ +20 |Mezzanine:X-M7-40G (29738) + |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J108) +------------------------------------------------------------------------ + + +SERDES2 |CARDS +----------------------------------------------------------------------- +2 |Mezzanine:X-M6-PCIE-X8 (29737) * + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT3(J116) +------------------------------------------------------------------------ +3 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect I/O cable to IO_SLOT3(J116) + |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT4(J119) +------------------------------------------------------------------------ +5 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect I/O cable to IO_SLOT3(J116) + |Mezzanine:X-M5-SATA (29687) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT4(J119) +------------------------------------------------------------------------ +11 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect I/O cable to IO_SLOT7(J127) + |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT8(J131) +------------------------------------------------------------------------ diff --git a/board/nxp/lx2160a/ddr.c b/board/nxp/lx2160a/ddr.c new file mode 100644 index 00000000000..637e43a22be --- /dev/null +++ b/board/nxp/lx2160a/ddr.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} diff --git a/board/nxp/lx2160a/eth_lx2160aqds.c b/board/nxp/lx2160a/eth_lx2160aqds.c new file mode 100644 index 00000000000..9939bb6f89e --- /dev/null +++ b/board/nxp/lx2160a/eth_lx2160aqds.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2020 NXP + * + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_eth_init(struct bd_info *bis) +{ +#ifdef CONFIG_PHY_AQUANTIA + /* + * Export functions to be used by AQ firmware + * upload application + */ + gd->jt->strcpy = strcpy; + gd->jt->mdelay = mdelay; + gd->jt->mdio_get_current_dev = mdio_get_current_dev; + gd->jt->phy_find_by_mask = phy_find_by_mask; + gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; + gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; +#endif + + return 0; +} + +#if defined(CONFIG_RESET_PHY_R) +void reset_phy(void) +{ +#if defined(CONFIG_FSL_MC_ENET) + mc_env_boot(); +#endif +} +#endif /* CONFIG_RESET_PHY_R */ + +#if defined(CONFIG_MULTI_DTB_FIT) + +/* Structure to hold SERDES protocols supported (network interfaces are + * described in the DTS). + * + * @serdes_block: the index of the SERDES block + * @serdes_protocol: the decimal value of the protocol supported + * @dts_needed: DTS notes describing the current configuration are needed + * + * When dts_needed is true, the board_fit_config_name_match() function + * will try to exactly match the current configuration of the block with a DTS + * name provided. + */ +static struct serdes_configuration { + u8 serdes_block; + u32 serdes_protocol; + bool dts_needed; +} supported_protocols[] = { + /* Serdes block #1 */ + {1, 3, true}, + {1, 7, true}, + {1, 19, true}, + {1, 20, true}, + + /* Serdes block #2 */ + {2, 2, false}, + {2, 3, false}, + {2, 5, false}, + {2, 11, true}, + + /* Serdes block #3 */ + {3, 2, false}, + {3, 3, false}, +}; + +#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) + +static bool protocol_supported(u8 serdes_block, u32 protocol) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) + return true; + } + + return false; +} + +static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) { + if (serdes_conf.dts_needed == true) + sprintf(str, "%u", protocol); + else + sprintf(str, "x"); + return; + } + } +} + +int board_fit_config_name_match(const char *name) +{ + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + u32 rcw_status = in_le32(&gur->rcwsr[28]); + char srds_s1_str[2], srds_s2_str[2], srds_s3_str[2]; + u32 srds_s1, srds_s2, srds_s3; + char expected_dts[100]; + + srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + + srds_s3 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK; + srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT; + + /* Check for supported protocols. The default DTS will be used + * in this case + */ + if (!protocol_supported(1, srds_s1) || + !protocol_supported(2, srds_s2) || + !protocol_supported(3, srds_s3)) + return -1; + + get_str_protocol(1, srds_s1, srds_s1_str); + get_str_protocol(2, srds_s2, srds_s2_str); + get_str_protocol(3, srds_s3, srds_s3_str); + + sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s-%s", + srds_s1_str, srds_s2_str, srds_s3_str); + + if (!strcmp(name, expected_dts)) + return 0; + + return -1; +} +#endif diff --git a/board/nxp/lx2160a/eth_lx2160ardb.c b/board/nxp/lx2160a/eth_lx2160ardb.c new file mode 100644 index 00000000000..90e7c9100e1 --- /dev/null +++ b/board/nxp/lx2160a/eth_lx2160ardb.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018, 2020 NXP + * + */ + +#include +#include +#include +#include "lx2160a.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_eth_init(struct bd_info *bis) +{ +#ifdef CONFIG_PHY_AQUANTIA + /* + * Export functions to be used by AQ firmware + * upload application + */ + gd->jt->strcpy = strcpy; + gd->jt->mdelay = mdelay; + gd->jt->mdio_get_current_dev = mdio_get_current_dev; + gd->jt->phy_find_by_mask = phy_find_by_mask; + gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; + gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; +#endif + return pci_eth_init(bis); +} + +#if defined(CONFIG_RESET_PHY_R) +void reset_phy(void) +{ +#if defined(CONFIG_FSL_MC_ENET) + mc_env_boot(); +#endif +} +#endif /* CONFIG_RESET_PHY_R */ + +static int fdt_get_dpmac_node(void *fdt, int dpmac_id) +{ + char dpmac_str[11] = "dpmacs@00"; + int offset, dpmacs_offset; + + /* get the dpmac offset */ + dpmacs_offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs"); + if (dpmacs_offset < 0) + dpmacs_offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs"); + + if (dpmacs_offset < 0) { + printf("dpmacs node not found in device tree\n"); + return dpmacs_offset; + } + + sprintf(dpmac_str, "dpmac@%x", dpmac_id); + offset = fdt_subnode_offset(fdt, dpmacs_offset, dpmac_str); + if (offset < 0) { + sprintf(dpmac_str, "ethernet@%x", dpmac_id); + offset = fdt_subnode_offset(fdt, dpmacs_offset, dpmac_str); + if (offset < 0) { + printf("dpmac@%x/ethernet@%x node not found in device tree\n", + dpmac_id, dpmac_id); + return offset; + } + } + + return offset; +} + +static int fdt_update_phy_addr(void *fdt, int dpmac_id, int phy_addr) +{ + char dpmac_str[] = "dpmacs@00"; + const u32 *phyhandle; + int offset; + int err; + + /* get the dpmac offset */ + offset = fdt_get_dpmac_node(fdt, dpmac_id); + if (offset < 0) + return offset; + + /* get dpmac phy-handle */ + sprintf(dpmac_str, "dpmac@%x", dpmac_id); + phyhandle = (u32 *)fdt_getprop(fdt, offset, "phy-handle", NULL); + if (!phyhandle) { + printf("%s node not found in device tree\n", dpmac_str); + return offset; + } + + offset = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*phyhandle)); + if (offset < 0) { + printf("Could not get the ph node offset for dpmac %d\n", + dpmac_id); + return offset; + } + + phy_addr = cpu_to_fdt32(phy_addr); + err = fdt_setprop(fdt, offset, "reg", &phy_addr, sizeof(phy_addr)); + if (err < 0) { + printf("Could not set phy node's reg for dpmac %d: %s.\n", + dpmac_id, fdt_strerror(err)); + return err; + } + + return 0; +} + +static int fdt_delete_phy_handle(void *fdt, int dpmac_id) +{ + const u32 *phyhandle; + int offset; + + /* get the dpmac offset */ + offset = fdt_get_dpmac_node(fdt, dpmac_id); + if (offset < 0) + return offset; + + /* verify if the node has a phy-handle */ + phyhandle = (u32 *)fdt_getprop(fdt, offset, "phy-handle", NULL); + if (!phyhandle) + return 0; + + return fdt_delprop(fdt, offset, "phy-handle"); +} + +int fdt_fixup_board_phy_revc(void *fdt) +{ + int ret; + + if (get_board_rev() < 'C') + return 0; + + /* DPMACs 3,4 have their Aquantia PHYs at new addresses */ + ret = fdt_update_phy_addr(fdt, 3, AQR113C_PHY_ADDR1); + if (ret) + return ret; + + ret = fdt_update_phy_addr(fdt, 4, AQR113C_PHY_ADDR2); + if (ret) + return ret; + + /* There is no PHY for the DPMAC2, so remove the phy-handle */ + return fdt_delete_phy_handle(fdt, 2); +} diff --git a/board/nxp/lx2160a/eth_lx2162aqds.c b/board/nxp/lx2160a/eth_lx2162aqds.c new file mode 100644 index 00000000000..805aa705be9 --- /dev/null +++ b/board/nxp/lx2160a/eth_lx2162aqds.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + * + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_eth_init(struct bd_info *bis) +{ +#ifdef CONFIG_PHY_AQUANTIA + /* + * Export functions to be used by AQ firmware + * upload application + */ + gd->jt->strcpy = strcpy; + gd->jt->mdelay = mdelay; + gd->jt->mdio_get_current_dev = mdio_get_current_dev; + gd->jt->phy_find_by_mask = phy_find_by_mask; + gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; + gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; +#endif + + return 0; +} + +#if defined(CONFIG_RESET_PHY_R) +void reset_phy(void) +{ +#if defined(CONFIG_FSL_MC_ENET) + mc_env_boot(); +#endif +} +#endif /* CONFIG_RESET_PHY_R */ + +#if defined(CONFIG_MULTI_DTB_FIT) + +/* Structure to hold SERDES protocols supported (network interfaces are + * described in the DTS). + * + * @serdes_block: the index of the SERDES block + * @serdes_protocol: the decimal value of the protocol supported + * @dts_needed: DTS notes describing the current configuration are needed + * + * When dts_needed is true, the board_fit_config_name_match() function + * will try to exactly match the current configuration of the block with a DTS + * name provided. + */ +static struct serdes_configuration { + u8 serdes_block; + u32 serdes_protocol; + bool dts_needed; +} supported_protocols[] = { + /* Serdes block #1 */ + {1, 2, true}, + {1, 3, true}, + {1, 15, true}, + {1, 17, true}, + {1, 18, true}, + {1, 20, true}, + + /* Serdes block #2 */ + {2, 2, false}, + {2, 3, false}, + {2, 5, false}, + {2, 10, false}, + {2, 11, true}, + {2, 12, true}, +}; + +#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) + +static bool protocol_supported(u8 serdes_block, u32 protocol) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) + return true; + } + + return false; +} + +static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) { + if (serdes_conf.dts_needed == true) + sprintf(str, "%u", protocol); + else + sprintf(str, "x"); + return; + } + } +} + +int board_fit_config_name_match(const char *name) +{ + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + u32 rcw_status = in_le32(&gur->rcwsr[28]); + char srds_s1_str[2], srds_s2_str[2]; + u32 srds_s1, srds_s2; + char expected_dts[100]; + + srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + + /* Check for supported protocols. The default DTS will be used + * in this case + */ + if (!protocol_supported(1, srds_s1) || + !protocol_supported(2, srds_s2)) + return -1; + + get_str_protocol(1, srds_s1, srds_s1_str); + get_str_protocol(2, srds_s2, srds_s2_str); + + sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s", + srds_s1_str, srds_s2_str); + + if (!strcmp(name, expected_dts)) + return 0; + + return -1; +} +#endif diff --git a/board/nxp/lx2160a/lx2160a.c b/board/nxp/lx2160a/lx2160a.c new file mode 100644 index 00000000000..341f82ce724 --- /dev/null +++ b/board/nxp/lx2160a/lx2160a.c @@ -0,0 +1,864 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/i2c_mux.h" + +#include "../common/qixis.h" +#include "../common/vid.h" +#include +#include +#include "lx2160a.h" + +#ifdef CONFIG_EMC2305 +#include "../common/emc2305.h" +#endif + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +#define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value) +#define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f) +#define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value) +#define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value) +#define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value) +#define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value) +#define SDHC1_BASE_PMUX_DSPI 2 +#define SDHC2_BASE_PMUX_DSPI 2 +#define IIC5_PMUX_SPI3 3 +#endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */ + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ +#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_XPL_BUILD) + i2c_early_init_f(); +#endif + +#ifdef CONFIG_EMC2305 + select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305, 0); + emc2305_init(I2C_EMC2305_ADDR); + set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); +#endif + + fsl_lsch3_early_init_f(); + return 0; +} + +#ifdef CONFIG_OF_BOARD_FIXUP +int board_fix_fdt(void *fdt) +{ + char *reg_names, *reg_name; + int names_len, old_name_len, new_name_len, remaining_names_len; + struct str_map { + char *old_str; + char *new_str; + } reg_names_map[] = { + { "ccsr", "dbi" }, + { "pf_ctrl", "ctrl" } + }; + int off = -1, i = 0; + + if (IS_SVR_REV(get_svr(), 1, 0)) + return 0; + + fdt_for_each_node_by_compatible(off, fdt, -1, "fsl,lx2160a-pcie") { + fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie", + strlen("fsl,ls-pcie") + 1); + + reg_names = (char *)fdt_getprop(fdt, off, "reg-names", + &names_len); + if (!reg_names) + continue; + + reg_name = reg_names; + remaining_names_len = names_len - (reg_name - reg_names); + i = 0; + while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) { + old_name_len = strlen(reg_names_map[i].old_str); + new_name_len = strlen(reg_names_map[i].new_str); + if (memcmp(reg_name, reg_names_map[i].old_str, + old_name_len) == 0) { + /* first only leave required bytes for new_str + * and copy rest of the string after it + */ + memcpy(reg_name + new_name_len, + reg_name + old_name_len, + remaining_names_len - old_name_len); + /* Now copy new_str */ + memcpy(reg_name, reg_names_map[i].new_str, + new_name_len); + names_len -= old_name_len; + names_len += new_name_len; + i++; + } + + reg_name = memchr(reg_name, '\0', remaining_names_len); + if (!reg_name) + break; + + reg_name += 1; + + remaining_names_len = names_len - + (reg_name - reg_names); + } + + fdt_setprop(fdt, off, "reg-names", reg_names, names_len); + } + + /* Fixup u-boot's DTS in case this is a revC board and + * we're using DM_ETH. + */ + if (IS_ENABLED(CONFIG_TARGET_LX2160ARDB) && IS_ENABLED(CONFIG_DM_ETH)) + fdt_fixup_board_phy_revc(fdt); + return 0; +} +#endif + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +void esdhc_dspi_status_fixup(void *blob) +{ + const char esdhc0_path[] = "/soc/esdhc@2140000"; + const char esdhc1_path[] = "/soc/esdhc@2150000"; + const char dspi0_path[] = "/soc/spi@2100000"; + const char dspi1_path[] = "/soc/spi@2110000"; + const char dspi2_path[] = "/soc/spi@2120000"; + + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + u32 sdhc1_base_pmux; + u32 sdhc2_base_pmux; + u32 iic5_pmux; + + /* Check RCW field sdhc1_base_pmux to enable/disable + * esdhc0/dspi0 DT node + */ + sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) + & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK; + sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT; + + if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) { + do_fixup_by_path(blob, dspi0_path, "status", "okay", + sizeof("okay"), 1); + do_fixup_by_path(blob, esdhc0_path, "status", "disabled", + sizeof("disabled"), 1); + } else { + do_fixup_by_path(blob, esdhc0_path, "status", "okay", + sizeof("okay"), 1); + do_fixup_by_path(blob, dspi0_path, "status", "disabled", + sizeof("disabled"), 1); + } + + /* Check RCW field sdhc2_base_pmux to enable/disable + * esdhc1/dspi1 DT node + */ + sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1]) + & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK; + sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT; + + if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) { + do_fixup_by_path(blob, dspi1_path, "status", "okay", + sizeof("okay"), 1); + do_fixup_by_path(blob, esdhc1_path, "status", "disabled", + sizeof("disabled"), 1); + } else { + do_fixup_by_path(blob, esdhc1_path, "status", "okay", + sizeof("okay"), 1); + do_fixup_by_path(blob, dspi1_path, "status", "disabled", + sizeof("disabled"), 1); + } + + /* Check RCW field IIC5 to enable dspi2 DT node */ + iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) + & FSL_CHASSIS3_IIC5_PMUX_MASK; + iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT; + + if (iic5_pmux == IIC5_PMUX_SPI3) + do_fixup_by_path(blob, dspi2_path, "status", "okay", + sizeof("okay"), 1); + else + do_fixup_by_path(blob, dspi2_path, "status", "disabled", + sizeof("disabled"), 1); +} +#endif + +int esdhc_status_fixup(void *blob, const char *compat) +{ +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) + /* Enable esdhc and dspi DT nodes based on RCW fields */ + esdhc_dspi_status_fixup(blob); +#else + /* Enable both esdhc DT nodes for LX2160ARDB */ + do_fixup_by_compat(blob, compat, "status", "okay", + sizeof("okay"), 1); +#endif + return 0; +} + +#if defined(CONFIG_VID) +int i2c_multiplexer_select_vid_channel(u8 channel) +{ + return select_i2c_ch_pca9547(channel, 0); +} + +int init_func_vid(void) +{ + int set_vid; + + if (IS_SVR_REV(get_svr(), 1, 0)) + set_vid = adjust_vdd(800); + else + set_vid = adjust_vdd(0); + + if (set_vid < 0) + printf("core voltage not adjusted\n"); + + return 0; +} +#endif +EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, init_func_vid); + +int checkboard(void) +{ + enum boot_src src = get_boot_src(); + char buf[64]; + u8 sw; +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) + int clock; + static const char *const freq[] = {"100", "125", "156.25", + "161.13", "322.26", "", "", "", + "", "", "", "", "", "", "", + "100 separate SSCG"}; +#endif + + cpu_name(buf); +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) + printf("Board: %s-QDS, ", buf); +#else + printf("Board: %s-RDB, ", buf); +#endif + + sw = QIXIS_READ(arch); + printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A'); + + if (src == BOOT_SOURCE_SD_MMC) { + puts("SD\n"); + } else if (src == BOOT_SOURCE_SD_MMC2) { + puts("eMMC\n"); + } else { + sw = QIXIS_READ(brdcfg[0]); + sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK; + switch (sw) { + case 0: + case 4: + puts("FlexSPI DEV#0\n"); + break; + case 1: + puts("FlexSPI DEV#1\n"); + break; + case 2: + case 3: + puts("FlexSPI EMU\n"); + break; + default: + printf("invalid setting, xmap: %d\n", sw); + break; + } + } +#if defined(CONFIG_TARGET_LX2160ARDB) + printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); + + puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n"); + puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); + puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); +#else + printf("FPGA: v%d (%s), build %d", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + /* the timestamp string contains "\n" at the end */ + printf(" on %s", qixis_read_time(buf)); + + puts("SERDES1 Reference : "); + sw = QIXIS_READ(brdcfg[2]); + clock = sw >> 4; + printf("Clock1 = %sMHz ", freq[clock]); +#if defined(CONFIG_TARGET_LX2160AQDS) + clock = sw & 0x0f; + printf("Clock2 = %sMHz", freq[clock]); +#endif + sw = QIXIS_READ(brdcfg[3]); + puts("\nSERDES2 Reference : "); + clock = sw >> 4; + printf("Clock1 = %sMHz ", freq[clock]); + clock = sw & 0x0f; + printf("Clock2 = %sMHz\n", freq[clock]); +#if defined(CONFIG_TARGET_LX2160AQDS) + sw = QIXIS_READ(brdcfg[12]); + puts("SERDES3 Reference : "); + clock = sw >> 4; + printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]); +#endif +#endif + return 0; +} + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +static void esdhc_adapter_card_ident(void) +{ + u8 card_id, val; + + val = QIXIS_READ(sdhc1); + card_id = val & QIXIS_SDID_MASK; + + switch (card_id) { + case QIXIS_ESDHC_ADAPTER_TYPE_SD: + /* Power cycle to card */ + val &= ~QIXIS_SDHC1_S1V3; + QIXIS_WRITE(sdhc1, val); + mdelay(1); + val |= QIXIS_SDHC1_S1V3; + QIXIS_WRITE(sdhc1, val); + /* Route to SDHC1_VS */ + val = QIXIS_READ(brdcfg[11]); + val |= QIXIS_SDHC1_VS; + QIXIS_WRITE(brdcfg[11], val); + break; + default: + break; + } +} + +int config_board_mux(void) +{ + u8 reg11, reg5, reg13; + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + u32 sdhc1_base_pmux; + u32 sdhc2_base_pmux; + u32 iic5_pmux; + + /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}. + * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}. + * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}. + * Qixis and remote systems are isolated from the I2C1 bus. + * Processor connections are still available. + * SPI2 CS2_B controls EN25S64 SPI memory device. + * SPI3 CS2_B controls EN25S64 SPI memory device. + * EC2 connects to PHY #2 using RGMII protocol. + * CLK_OUT connects to FPGA for clock measurement. + */ + + reg5 = QIXIS_READ(brdcfg[5]); + reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40); + QIXIS_WRITE(brdcfg[5], reg5); + + /* Check RCW field sdhc1_base_pmux + * esdhc0 : sdhc1_base_pmux = 0 + * dspi0 : sdhc1_base_pmux = 2 + */ + sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) + & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK; + sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT; + + if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) { + reg11 = QIXIS_READ(brdcfg[11]); + reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40); + QIXIS_WRITE(brdcfg[11], reg11); + } else { + /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot. + * {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot. + * {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot. + */ + reg11 = QIXIS_READ(brdcfg[11]); + reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11); + QIXIS_WRITE(brdcfg[11], reg11); + } + + /* Check RCW field sdhc2_base_pmux + * esdhc1 : sdhc2_base_pmux = 0 (default) + * dspi1 : sdhc2_base_pmux = 2 + */ + sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1]) + & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK; + sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT; + + if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) { + reg13 = QIXIS_READ(brdcfg[13]); + reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01); + QIXIS_WRITE(brdcfg[13], reg13); + } else { + reg13 = QIXIS_READ(brdcfg[13]); + reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00); + QIXIS_WRITE(brdcfg[13], reg13); + } + + /* Check RCW field IIC5 to enable dspi2 DT nodei + * dspi2: IIC5 = 3 + */ + iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) + & FSL_CHASSIS3_IIC5_PMUX_MASK; + iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT; + + if (iic5_pmux == IIC5_PMUX_SPI3) { + /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */ + reg11 = QIXIS_READ(brdcfg[11]); + reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10); + QIXIS_WRITE(brdcfg[11], reg11); + + /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere. + * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }. + * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}. + */ + reg11 = QIXIS_READ(brdcfg[11]); + reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01); + QIXIS_WRITE(brdcfg[11], reg11); + } else { + /* + * If {SDHC1_DAT4} has been configured to route to SDHC1_VS, + * do not change it. + * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot. + */ + reg11 = QIXIS_READ(brdcfg[11]); + if ((reg11 & 0x30) != 0x30) { + reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00); + QIXIS_WRITE(brdcfg[11], reg11); + } + + /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot. + * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot. + * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot. + */ + reg11 = QIXIS_READ(brdcfg[11]); + reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00); + QIXIS_WRITE(brdcfg[11], reg11); + } + + return 0; +} + +int board_early_init_r(void) +{ + esdhc_adapter_card_ident(); + return 0; +} +#elif defined(CONFIG_TARGET_LX2160ARDB) +int config_board_mux(void) +{ + u8 brdcfg; + + brdcfg = QIXIS_READ(brdcfg[4]); + /* The BRDCFG4 register controls general board configuration. + *|-------------------------------------------| + *|Field | Function | + *|-------------------------------------------| + *|5 | CAN I/O Enable (net CFG_CAN_EN_B):| + *|CAN_EN | 0= CAN transceivers are disabled. | + *| | 1= CAN transceivers are enabled. | + *|-------------------------------------------| + */ + brdcfg |= BIT_MASK(5); + QIXIS_WRITE(brdcfg[4], brdcfg); + + return 0; +} +#else +int config_board_mux(void) +{ + return 0; +} +#endif + +#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB) +u8 get_board_rev(void) +{ + u8 board_rev = (QIXIS_READ(arch) & 0xf) - 1 + 'A'; + + return board_rev; +} +#endif + +unsigned long get_board_sys_clk(void) +{ +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x03) { + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + } + return 100000000; +#else + return 100000000; +#endif +} + +unsigned long get_board_ddr_clk(void) +{ +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 100000000; +#else + return 100000000; +#endif +} + +int board_init(void) +{ +#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB) + u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; +#endif + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); + +#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB) + /* invert AQR107 IRQ pins polarity */ + out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK); +#endif + +#if !defined(CONFIG_SYS_EARLY_PCI_INIT) + pci_init(); +#endif + return 0; +} + +void detail_board_ddr_info(void) +{ + int i; + u64 ddr_size = 0; + + puts("\nDDR "); + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + ddr_size += gd->bd->bi_dram[i].size; + print_size(ddr_size, ""); + print_ddr_info(0); +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + config_board_mux(); + + return 0; +} +#endif + +#ifdef CONFIG_VID +u16 soc_get_fuse_vid(int vid_index) +{ + static const u16 vdd[32] = { + 8250, + 7875, + 7750, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 8000, + 8125, + 8250, + 0, /* reserved */ + 8500, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + }; + + return vdd[vid_index]; +}; +#endif + +#ifdef CONFIG_FSL_MC_ENET + +void fdt_fixup_board_enet(void *fdt) +{ + int offset; + + offset = fdt_path_offset(fdt, "/soc/fsl-mc"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/fsl-mc"); + + if (offset < 0) { + printf("%s: fsl-mc node not found in device tree (error %d)\n", + __func__, offset); + return; + } + + if (get_mc_boot_status() == 0 && + (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) { + fdt_status_okay(fdt, offset); + if (IS_ENABLED(CONFIG_TARGET_LX2160ARDB)) + fdt_fixup_board_phy_revc(fdt); + } else { + fdt_status_fail(fdt, offset); + } +} + +void board_quiesce_devices(void) +{ + fsl_mc_ldpaa_exit(gd->bd); +} +#endif + +#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB) +int fdt_fixup_add_thermal(void *blob, int mux_node, int channel, int reg) +{ + int err; + int noff; + int offset; + char channel_node_name[50]; + char thermal_node_name[50]; + u32 phandle; + + snprintf(channel_node_name, sizeof(channel_node_name), + "i2c@%x", channel); + debug("channel_node_name = %s\n", channel_node_name); + + snprintf(thermal_node_name, sizeof(thermal_node_name), + "temperature-sensor@%x", reg); + debug("thermal_node_name = %s\n", thermal_node_name); + + err = fdt_increase_size(blob, 200); + if (err) { + printf("fdt_increase_size: err=%s\n", fdt_strerror(err)); + return err; + } + + noff = fdt_subnode_offset(blob, mux_node, (const char *) + channel_node_name); + if (noff < 0) { + /* channel node not found - create it */ + noff = fdt_add_subnode(blob, mux_node, channel_node_name); + if (noff < 0) { + printf("fdt_add_subnode: err=%s\n", fdt_strerror(err)); + return err; + } + fdt_setprop_u32 (blob, noff, "#address-cells", 1); + fdt_setprop_u32 (blob, noff, "#size-cells", 0); + fdt_setprop_u32 (blob, noff, "reg", channel); + } + + /* Create thermal node*/ + offset = fdt_add_subnode(blob, noff, thermal_node_name); + fdt_setprop(blob, offset, "compatible", "nxp,sa56004", + strlen("nxp,sa56004") + 1); + fdt_setprop_u32 (blob, offset, "reg", reg); + + /* fixup phandle*/ + noff = fdt_node_offset_by_compatible(blob, -1, "regulator-fixed"); + if (noff < 0) { + printf("%s : failed to get phandle\n", __func__); + return noff; + } + phandle = fdt_get_phandle(blob, noff); + fdt_setprop_u32 (blob, offset, "vcc-supply", phandle); + + return 0; +} + +void fdt_fixup_delete_thermal(void *blob, int mux_node, int channel, int reg) +{ + int node; + int value; + int err; + int subnode; + + fdt_for_each_subnode(subnode, blob, mux_node) { + value = fdtdec_get_uint(blob, subnode, "reg", -1); + if (value == channel) { + /* delete thermal node */ + fdt_for_each_subnode(node, blob, subnode) { + value = fdtdec_get_uint(blob, node, "reg", -1); + err = fdt_node_check_compatible(blob, node, + "nxp,sa56004"); + if (!err && value == reg) { + fdt_del_node(blob, node); + break; + } + } + } + } +} + +void fdt_fixup_i2c_thermal_node(void *blob) +{ + int i2coffset; + int mux_node; + int reg; + int err; + + i2coffset = fdt_node_offset_by_compat_reg(blob, "fsl,vf610-i2c", + 0x2000000); + if (i2coffset != -FDT_ERR_NOTFOUND) { + fdt_for_each_subnode(mux_node, blob, i2coffset) { + reg = fdtdec_get_uint(blob, mux_node, "reg", -1); + err = fdt_node_check_compatible(blob, mux_node, + "nxp,pca9547"); + if (!err && reg == 0x77) { + fdt_fixup_delete_thermal(blob, mux_node, + 0x3, 0x4d); + err = fdt_fixup_add_thermal(blob, mux_node, + 0x3, 0x48); + if (err) + printf("%s: Add thermal node failed\n", + __func__); + } + } + } else { + printf("%s: i2c node not found\n", __func__); + } +} +#endif + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + int i; + u16 mc_memory_bank = 0; + + u64 *base; + u64 *size; + u64 mc_memory_base = 0; + u64 mc_memory_size = 0; + u16 total_memory_banks; + int err; + + err = fdt_increase_size(blob, 512); + if (err) { + printf("%s fdt_increase_size: err=%s\n", __func__, + fdt_strerror(err)); + return err; + } + + ft_cpu_setup(blob, bd); + + fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); + + if (mc_memory_base != 0) + mc_memory_bank++; + + total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; + + base = calloc(total_memory_banks, sizeof(u64)); + size = calloc(total_memory_banks, sizeof(u64)); + + /* fixup DT for the three GPP DDR banks */ + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + base[i] = gd->bd->bi_dram[i].start; + size[i] = gd->bd->bi_dram[i].size; + } + +#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; + else if (gd->arch.resv_ram >= base[2] && + gd->arch.resv_ram < base[2] + size[2]) + size[2] = gd->arch.resv_ram - base[2]; +#endif + + if (mc_memory_base != 0) { + for (i = 0; i <= total_memory_banks; i++) { + if (base[i] == 0 && size[i] == 0) { + base[i] = mc_memory_base; + size[i] = mc_memory_size; + break; + } + } + } + + fdt_fixup_memory_banks(blob, base, size, total_memory_banks); + +#ifdef CONFIG_USB_HOST + fsl_fdt_fixup_dr_usb(blob, bd); +#endif + +#ifdef CONFIG_FSL_MC_ENET + fdt_fsl_mc_fixup_iommu_map_entry(blob); + fdt_fixup_board_enet(blob); + fdt_reserve_mc_mem(blob, 0x4000); +#endif + fdt_fixup_icid(blob); + +#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB) + if (get_board_rev() == 'C') + fdt_fixup_i2c_thermal_node(blob); +#endif + + return 0; +} +#endif + +void qixis_dump_switch(void) +{ + int i, nr_of_cfgsw; + + QIXIS_WRITE(cms[0], 0x00); + nr_of_cfgsw = QIXIS_READ(cms[1]); + + puts("DIP switch settings dump:\n"); + for (i = 1; i <= nr_of_cfgsw; i++) { + QIXIS_WRITE(cms[0], i); + printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); + } +} diff --git a/board/nxp/lx2160a/lx2160a.h b/board/nxp/lx2160a/lx2160a.h new file mode 100644 index 00000000000..61a8bb95906 --- /dev/null +++ b/board/nxp/lx2160a/lx2160a.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __LX2160_H +#define __LX2160_H + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +/* SYSCLK */ +#define QIXIS_SYSCLK_100 0x0 +#define QIXIS_SYSCLK_125 0x1 +#define QIXIS_SYSCLK_133 0x2 + +/* DDRCLK */ +#define QIXIS_DDRCLK_100 0x0 +#define QIXIS_DDRCLK_125 0x1 +#define QIXIS_DDRCLK_133 0x2 + +#define BRDCFG4_EMI1SEL_MASK 0xF8 +#define BRDCFG4_EMI1SEL_SHIFT 3 +#define BRDCFG4_EMI2SEL_MASK 0x07 +#define BRDCFG4_EMI2SEL_SHIFT 0 +#endif + +#define QIXIS_XMAP_SHIFT 5 + +/* RTC */ +#define I2C_MUX_CH_RTC 0xB + +/* MAC/PHY configuration */ +#if defined(CONFIG_FSL_MC_ENET) +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +#define AQ_PHY_ADDR1 0x00 +#define AQ_PHY_ADDR2 0x01 +#define AQ_PHY_ADDR3 0x02 +#define AQ_PHY_ADDR4 0x03 +#endif + +#ifdef CONFIG_TARGET_LX2160ARDB +#define AQR107_PHY_ADDR1 0x04 +#define AQR107_PHY_ADDR2 0x05 +#define AQR107_IRQ_MASK 0x0C +#endif + +#define CORTINA_PHY_ADDR1 0x0 +#define INPHI_PHY_ADDR1 0x0 + +#define RGMII_PHY_ADDR1 0x01 +#define RGMII_PHY_ADDR2 0x02 + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +#define INPHI_PHY_ADDR2 0x1 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F +#endif +#endif + +#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB) +u8 get_board_rev(void); +int fdt_fixup_board_phy_revc(void *fdt); +#else +static inline u8 get_board_rev(void) +{ + return 0; +} + +static inline int fdt_fixup_board_phy_revc(void *fdt) +{ + return 0; +} +#endif + +#endif /* __LX2160_H */ diff --git a/board/nxp/m5208evbe/Kconfig b/board/nxp/m5208evbe/Kconfig new file mode 100644 index 00000000000..a87b57222df --- /dev/null +++ b/board/nxp/m5208evbe/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M5208EVBE + +config SYS_CPU + default "mcf52x2" + +config SYS_BOARD + default "m5208evbe" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "M5208EVBE" + +endif diff --git a/board/nxp/m5208evbe/MAINTAINERS b/board/nxp/m5208evbe/MAINTAINERS new file mode 100644 index 00000000000..77fd91fe126 --- /dev/null +++ b/board/nxp/m5208evbe/MAINTAINERS @@ -0,0 +1,6 @@ +M5208EVBE BOARD +M: Angelo Dureghello +S: Maintained +F: board/nxp/m5208evbe/ +F: include/configs/M5208EVBE.h +F: configs/M5208EVBE_defconfig diff --git a/board/nxp/m5208evbe/Makefile b/board/nxp/m5208evbe/Makefile new file mode 100644 index 00000000000..b7a7c3e6471 --- /dev/null +++ b/board/nxp/m5208evbe/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y = m5208evbe.o diff --git a/board/nxp/m5208evbe/m5208evbe.c b/board/nxp/m5208evbe/m5208evbe.c new file mode 100644 index 00000000000..b202b8094d9 --- /dev/null +++ b/board/nxp/m5208evbe/m5208evbe.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale M5208EVBe\n"); + return 0; +}; + +int dram_init(void) +{ + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); + u32 dramsize, i; + + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; + + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); +#ifdef CFG_SYS_SDRAM_BASE1 + out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i); +#endif + out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2); + + udelay(500); + + /* Issue PALL */ + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); + asm("nop"); + + /* Perform two refresh cycles */ + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + asm("nop"); + + /* Issue LEMR */ + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE); + asm("nop"); + out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); + asm("nop"); + + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); + asm("nop"); + + out_be32(&sdram->ctrl, + (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00); + asm("nop"); + + udelay(100); + + gd->ram_size = dramsize; + + return 0; +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/nxp/m5235evb/Kconfig b/board/nxp/m5235evb/Kconfig new file mode 100644 index 00000000000..dd1bbea92eb --- /dev/null +++ b/board/nxp/m5235evb/Kconfig @@ -0,0 +1,18 @@ +if TARGET_M5235EVB + +config SYS_CPU + default "mcf523x" + +config SYS_BOARD + default "m5235evb" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "M5235EVB" + +config NORFLASH_PS32BIT + bool "Board has 32bit CFI flash" + +endif diff --git a/board/nxp/m5235evb/MAINTAINERS b/board/nxp/m5235evb/MAINTAINERS new file mode 100644 index 00000000000..9716b78c36d --- /dev/null +++ b/board/nxp/m5235evb/MAINTAINERS @@ -0,0 +1,7 @@ +M5235EVB BOARD +M: TsiChung Liew +S: Maintained +F: board/nxp/m5235evb/ +F: include/configs/M5235EVB.h +F: configs/M5235EVB_defconfig +F: configs/M5235EVB_Flash32_defconfig diff --git a/board/nxp/m5235evb/Makefile b/board/nxp/m5235evb/Makefile new file mode 100644 index 00000000000..b7067e4581b --- /dev/null +++ b/board/nxp/m5235evb/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y = m5235evb.o diff --git a/board/nxp/m5235evb/m5235evb.c b/board/nxp/m5235evb/m5235evb.c new file mode 100644 index 00000000000..65cde56fb2d --- /dev/null +++ b/board/nxp/m5235evb/m5235evb.c @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale M5235 EVB\n"); + return 0; +}; + +int dram_init(void) +{ + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); + gpio_t *gpio = (gpio_t *)(MMAP_GPIO); + u32 dramsize, i, dramclk; + + /* + * When booting from external Flash, the port-size is less than + * the port-size of SDRAM. In this case it is necessary to enable + * Data[15:0] on Port Address/Data. + */ + out_8(&gpio->par_ad, + GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 | + GPIO_PAR_AD_DATAL); + + /* Initialize PAR to enable SDRAM signals */ + out_8(&gpio->par_sdram, + GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | + GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE | + GPIO_PAR_SDRAM_SDCS(3)); + + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) { + dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ); + + /* Initialize DRAM Control Register: DCR */ + out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS | + SDRAMC_DCR_RTIM_6CLKS | + SDRAMC_DCR_RC((15 * dramclk) >> 4)); + + /* Initialize DACR0 */ + out_be32(&sdram->dacr0, + SDRAMC_DARCn_BA(CFG_SYS_SDRAM_BASE) | + SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 | + SDRAMC_DARCn_PS_32); + asm("nop"); + + /* Initialize DMR0 */ + out_be32(&sdram->dmr0, + ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V); + asm("nop"); + + /* Set IP (bit 3) in DACR */ + setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP); + + /* Wait 30ns to allow banks to precharge */ + for (i = 0; i < 5; i++) { + asm("nop"); + } + + /* Write to this block to initiate precharge */ + *(u32 *) (CFG_SYS_SDRAM_BASE) = 0xA5A59696; + + /* Set RE (bit 15) in DACR */ + setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE); + + /* Wait for at least 8 auto refresh cycles to occur */ + for (i = 0; i < 0x2000; i++) { + asm("nop"); + } + + /* Finish the configuration by issuing the MRS. */ + setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS); + asm("nop"); + + /* Write to the SDRAM Mode Register */ + *(u32 *) (CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; + } + + gd->ram_size = dramsize; + + return 0; +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/nxp/m5249evb/Kconfig b/board/nxp/m5249evb/Kconfig new file mode 100644 index 00000000000..2757e411936 --- /dev/null +++ b/board/nxp/m5249evb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M5249EVB + +config SYS_CPU + default "mcf52x2" + +config SYS_BOARD + default "m5249evb" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "M5249EVB" + +endif diff --git a/board/nxp/m5249evb/MAINTAINERS b/board/nxp/m5249evb/MAINTAINERS new file mode 100644 index 00000000000..126fb27a848 --- /dev/null +++ b/board/nxp/m5249evb/MAINTAINERS @@ -0,0 +1,6 @@ +M5249EVB BOARD +M: Angelo Dureghello +S: Maintained +F: board/nxp/m5249evb/ +F: include/configs/M5249EVB.h +F: configs/M5249EVB_defconfig diff --git a/board/nxp/m5249evb/Makefile b/board/nxp/m5249evb/Makefile new file mode 100644 index 00000000000..497bc722908 --- /dev/null +++ b/board/nxp/m5249evb/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y = m5249evb.o diff --git a/board/nxp/m5249evb/m5249evb.c b/board/nxp/m5249evb/m5249evb.c new file mode 100644 index 00000000000..68524e5e682 --- /dev/null +++ b/board/nxp/m5249evb/m5249evb.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard (void) { + ulong val; + uchar val8; + + puts ("Board: "); + puts("Freescale M5249EVB"); + val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf; + printf(" (Switch=%1X)\n", val8); + + /* + * Set LED on + */ + val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_SYS_GPIO1_LED; + mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */ + + return 0; +}; + +int dram_init(void) +{ + unsigned long junk = 0xa5a59696; + + /* + * Note: + * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1 + */ + +#ifdef CFG_SYS_FAST_CLK + /* + * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K) + * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39 + */ + mbar_writeShort(MCFSIM_DCR, 0x8239); +#elif CFG_SYS_PLL_BYPASS + /* + * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K) + * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02 + */ + mbar_writeShort(MCFSIM_DCR, 0x8202); +#else + /* + * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K) + * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles) + */ + mbar_writeShort(MCFSIM_DCR, 0x8222); +#endif + + /* + * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port), + * PM=1 (continuous page mode) + */ + + /* RE=0 (keep auto-refresh disabled while setting up registers) */ + mbar_writeLong(MCFSIM_DACR0, 0x00003324); + + /* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */ + mbar_writeLong(MCFSIM_DMR0, 0x01fc0001); + + /** Precharge sequence **/ + mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */ + *((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */ + udelay(0x10); /* Allow several Precharge cycles */ + + /** Refresh Sequence **/ + mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */ + udelay(0x7d0); /* Allow gobs of refresh cycles */ + + /** Mode Register initialization **/ + mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ + *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */ + + gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; + + return 0; +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf ("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/nxp/m5253demo/Kconfig b/board/nxp/m5253demo/Kconfig new file mode 100644 index 00000000000..987bcf9f3b0 --- /dev/null +++ b/board/nxp/m5253demo/Kconfig @@ -0,0 +1,19 @@ +if TARGET_M5253DEMO + +config FLASH_CFI_LEGACY + depends on SYS_FLASH_CFI + def_bool y + +config SYS_CPU + default "mcf52x2" + +config SYS_BOARD + default "m5253demo" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "M5253DEMO" + +endif diff --git a/board/nxp/m5253demo/MAINTAINERS b/board/nxp/m5253demo/MAINTAINERS new file mode 100644 index 00000000000..dfc12012e79 --- /dev/null +++ b/board/nxp/m5253demo/MAINTAINERS @@ -0,0 +1,6 @@ +M5253DEMO BOARD +M: TsiChung Liew +S: Maintained +F: board/nxp/m5253demo/ +F: include/configs/M5253DEMO.h +F: configs/M5253DEMO_defconfig diff --git a/board/nxp/m5253demo/Makefile b/board/nxp/m5253demo/Makefile new file mode 100644 index 00000000000..00d395d1a3c --- /dev/null +++ b/board/nxp/m5253demo/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y = m5253demo.o flash.o diff --git a/board/nxp/m5253demo/flash.c b/board/nxp/m5253demo/flash.c new file mode 100644 index 00000000000..ab5d2ebff64 --- /dev/null +++ b/board/nxp/m5253demo/flash.c @@ -0,0 +1,440 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + */ + +#include +#include +#include +#include +#include + +#include + +#ifndef CONFIG_SYS_FLASH_CFI +typedef unsigned short FLASH_PORT_WIDTH; +typedef volatile unsigned short FLASH_PORT_WIDTHV; + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define FLASH_CYCLE1 0x5555 +#define FLASH_CYCLE2 0x2aaa + +#define SYNC __asm__("nop") + +/*----------------------------------------------------------------------- + * Functions + */ + +ulong flash_get_size(FPWV * addr, flash_info_t * info); +int flash_get_offsets(ulong base, flash_info_t * info); +int write_word(flash_info_t * info, FPWV * dest, u16 data); +static inline void spin_wheel(void); + +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; + +ulong flash_init(void) +{ + ulong size = 0; + ulong fbase = 0; + + fbase = (ulong) CFG_SYS_FLASH_BASE; + flash_get_size((FPWV *) fbase, &flash_info[0]); + flash_get_offsets((ulong) fbase, &flash_info[0]); + fbase += flash_info[0].size; + size += flash_info[0].size; + + /* Protect monitor and environment sectors */ + flash_protect(FLAG_PROTECT_SET, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); + + return size; +} + +int flash_get_offsets(ulong base, flash_info_t * info) +{ + int i; + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + + info->start[0] = base; + info->protect[0] = 0; + for (i = 1; i < CFG_SYS_SST_SECT; i++) { + info->start[i] = info->start[i - 1] + + CFG_SYS_SST_SECTSZ; + info->protect[i] = 0; + } + } + + return FL_ERR_OK; +} + +void flash_print_info(flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_SST: + printf("SST "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_SST6401B: + printf("SST39VF6401B\n"); + break; + default: + printf("Unknown Chip Type\n"); + return; + } + + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf("\n"); +} + +/* + * The following code cannot be run from FLASH! + */ +ulong flash_get_size(FPWV * addr, flash_info_t * info) +{ + u16 value; + + addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */ + addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */ + addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */ + + switch (addr[0] & 0xffff) { + case (u8) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + value = addr[1]; + break; + default: + printf("Unknown Flash\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + + *addr = (FPW) 0x00F000F0; + return (0); /* no or unknown flash */ + } + + switch (value) { + case (u16) SST_ID_xF6401B: + info->flash_id += FLASH_SST6401B; + break; + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + info->sector_count = 0; + info->size = 0; + info->sector_count = CFG_SYS_SST_SECT; + info->size = CFG_SYS_SST_SECT * CFG_SYS_SST_SECTSZ; + + /* reset ID mode */ + *addr = (FPWV) 0x00F000F0; + + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { + printf("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; + } + + return (info->size); +} + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + FPWV *addr; + int flag, prot, sect, count; + ulong type, start; + int rcode = 0, flashtype = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + + switch (type) { + case FLASH_MAN_SST: + flashtype = 1; + break; + default: + type = (info->flash_id & FLASH_VENDMASK); + printf("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + else + printf("\n"); + + flag = disable_interrupts(); + + start = get_timer(0); + + if ((s_last - s_first) == (CFG_SYS_SST_SECT - 1)) { + if (prot == 0) { + addr = (FPWV *) info->start[0]; + + addr[FLASH_CYCLE1] = 0x00AA; /* unlock */ + addr[FLASH_CYCLE2] = 0x0055; /* unlock */ + addr[FLASH_CYCLE1] = 0x0080; /* erase mode */ + addr[FLASH_CYCLE1] = 0x00AA; /* unlock */ + addr[FLASH_CYCLE2] = 0x0055; /* unlock */ + *addr = 0x0030; /* erase chip */ + + count = 0; + start = get_timer(0); + + while ((*addr & 0x0080) != 0x0080) { + if (count++ > 0x10000) { + spin_wheel(); + count = 0; + } + + /* check timeout, 1000ms */ + if (get_timer(start) > 1000) { + printf("Timeout\n"); + *addr = 0x00F0; /* reset to read mode */ + + return 1; + } + } + + *addr = 0x00F0; /* reset to read mode */ + + printf("\b. done\n"); + + if (flag) + enable_interrupts(); + + return 0; + } else if (prot == CFG_SYS_SST_SECT) { + return 1; + } + } + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + + addr = (FPWV *) (info->start[sect]); + + printf("."); + + /* arm simple, non interrupt dependent timer */ + start = get_timer(0); + + switch (flashtype) { + case 1: + { + FPWV *base; /* first address in bank */ + + flag = disable_interrupts(); + + base = (FPWV *) (CFG_SYS_FLASH_BASE); /* First sector */ + + base[FLASH_CYCLE1] = 0x00AA; /* unlock */ + base[FLASH_CYCLE2] = 0x0055; /* unlock */ + base[FLASH_CYCLE1] = 0x0080; /* erase mode */ + base[FLASH_CYCLE1] = 0x00AA; /* unlock */ + base[FLASH_CYCLE2] = 0x0055; /* unlock */ + *addr = 0x0050; /* erase sector */ + + if (flag) + enable_interrupts(); + + while ((*addr & 0x0080) != 0x0080) { + /* check timeout, 1000ms */ + if (get_timer(start) > 1000) { + printf("Timeout\n"); + *addr = 0x00F0; /* reset to read mode */ + + rcode = 1; + break; + } + } + + *addr = 0x00F0; /* reset to read mode */ + break; + } + } /* switch (flashtype) */ + } + } + printf(" done\n"); + + if (flag) + enable_interrupts(); + + return rcode; +} + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp, count; + u16 data; + int rc; + + if (info->flash_id == FLASH_UNKNOWN) + return 4; + + /* get lower word aligned address */ + wp = addr; + + /* handle unaligned start bytes */ + if (wp & 1) { + data = *((FPWV *) wp); + data = (data << 8) | *src; + + if ((rc = write_word(info, (FPWV *) wp, data)) != 0) + return (rc); + + wp++; + cnt -= 1; + src++; + } + + while (cnt >= 2) { + /* + * handle word aligned part + */ + count = 0; + data = *((FPWV *) src); + + if ((rc = write_word(info, (FPWV *) wp, data)) != 0) + return (rc); + + wp += 2; + src += 2; + cnt -= 2; + + if (count++ > 0x800) { + spin_wheel(); + count = 0; + } + } + /* handle word aligned part */ + if (cnt) { + /* handle word aligned part */ + count = 0; + data = *((FPWV *) wp); + + data = (data & 0x00FF) | (*src << 8); + + if ((rc = write_word(info, (FPWV *) wp, data)) != 0) + return (rc); + + wp++; + src++; + cnt -= 1; + if (count++ > 0x800) { + spin_wheel(); + count = 0; + } + } + + if (cnt == 0) + return FL_ERR_OK; + + return FL_ERR_OK; +} + +/*----------------------------------------------------------------------- + * Write a word to Flash + * A word is 16 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_word(flash_info_t * info, FPWV * dest, u16 data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & (u8) data) != (u8) data) { + return (2); + } + + base = (FPWV *) (CFG_SYS_FLASH_BASE); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (u8) 0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + + /* data polling for D7 */ + while (res == 0 + && (*dest & (u8) 0x00800080) != (data & (u8) 0x00800080)) { + /* check timeout, 500ms */ + if (get_timer(start) > 500) { + *dest = (u8) 0x00F000F0; /* reset bank */ + res = 1; + } + } + + *dest++ = (u8) 0x00F000F0; /* reset bank */ + + return (res); +} + +static inline void spin_wheel(void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} + +#endif diff --git a/board/nxp/m5253demo/m5253demo.c b/board/nxp/m5253demo/m5253demo.c new file mode 100644 index 00000000000..50c5320b55c --- /dev/null +++ b/board/nxp/m5253demo/m5253demo.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. + * Hayden Fraser (Hayden.Fraser@freescale.com) + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale MCF5253 DEMO\n"); + return 0; +}; + +int dram_init(void) +{ + u32 dramsize = 0; + + /* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ + if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { + u32 RC, temp; + + RC = (CFG_SYS_CLK / 1000000) >> 1; + RC = (RC * 15) >> 4; + + /* Initialize DRAM Control Register: DCR */ + mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); + __asm__("nop"); + + mbar_writeLong(MCFSIM_DACR0, 0x00003224); + __asm__("nop"); + + /* Initialize DMR0 */ + dramsize = (CFG_SYS_SDRAM_SIZE << 20); + temp = (dramsize - 1) & 0xFFFC0000; + mbar_writeLong(MCFSIM_DMR0, temp | 1); + __asm__("nop"); + + mbar_writeLong(MCFSIM_DACR0, 0x0000322c); + mb(); + __asm__("nop"); + + /* Write to this block to initiate precharge */ + *(u32 *) (CFG_SYS_SDRAM_BASE) = 0xa5a5a5a5; + mb(); + __asm__("nop"); + + /* Set RE bit in DACR */ + mbar_writeLong(MCFSIM_DACR0, + mbar_readLong(MCFSIM_DACR0) | 0x8000); + __asm__("nop"); + + /* Wait for at least 8 auto refresh cycles to occur */ + udelay(500); + + /* Finish the configuration by issuing the MRS */ + mbar_writeLong(MCFSIM_DACR0, + mbar_readLong(MCFSIM_DACR0) | 0x0040); + __asm__("nop"); + + *(u32 *) (CFG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; + mb(); + } + + gd->ram_size = dramsize; + + return 0; +} + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} + +#ifdef CONFIG_IDE +#include +#include +void ide_set_reset(int idereset) +{ + atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; + long period; + /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ + int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ + {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ + {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ + {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ + {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */ + }; + + if (idereset) { + /* control reset */ + out_8(&ata->cr, 0); + udelay(100); + } else { + mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); + +#define CALC_TIMING(t) (t + period - 1) / period + period = 1000000000 / (CFG_SYS_CLK / 2); /* period in ns */ + + /*ata->ton = CALC_TIMING (180); */ + out_8(&ata->t1, CALC_TIMING(piotms[2][0])); + out_8(&ata->t2w, CALC_TIMING(piotms[2][1])); + out_8(&ata->t2r, CALC_TIMING(piotms[2][1])); + out_8(&ata->ta, CALC_TIMING(piotms[2][8])); + out_8(&ata->trd, CALC_TIMING(piotms[2][7])); + out_8(&ata->t4, CALC_TIMING(piotms[2][3])); + out_8(&ata->t9, CALC_TIMING(piotms[2][6])); + + /* IORDY enable */ + out_8(&ata->cr, 0x40); + udelay(2000); + /* IORDY enable */ + setbits_8(&ata->cr, 0x01); + } +} +#endif /* CONFIG_IDE */ + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(struct bd_info *bis) +{ + return dm9000_initialize(bis); +} +#endif diff --git a/board/nxp/m5272c3/Kconfig b/board/nxp/m5272c3/Kconfig new file mode 100644 index 00000000000..7a5a0f29085 --- /dev/null +++ b/board/nxp/m5272c3/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M5272C3 + +config SYS_CPU + default "mcf52x2" + +config SYS_BOARD + default "m5272c3" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "M5272C3" + +endif diff --git a/board/nxp/m5272c3/MAINTAINERS b/board/nxp/m5272c3/MAINTAINERS new file mode 100644 index 00000000000..723f6db1716 --- /dev/null +++ b/board/nxp/m5272c3/MAINTAINERS @@ -0,0 +1,6 @@ +M5272C3 BOARD +M: Angelo Dureghello +S: Maintained +F: board/nxp/m5272c3/ +F: include/configs/M5272C3.h +F: configs/M5272C3_defconfig diff --git a/board/nxp/m5272c3/Makefile b/board/nxp/m5272c3/Makefile new file mode 100644 index 00000000000..1df8f7003e4 --- /dev/null +++ b/board/nxp/m5272c3/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y = m5272c3.o diff --git a/board/nxp/m5272c3/m5272c3.c b/board/nxp/m5272c3/m5272c3.c new file mode 100644 index 00000000000..d1286badc61 --- /dev/null +++ b/board/nxp/m5272c3/m5272c3.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard (void) { + puts ("Board: "); + puts ("Freescale MCF5272C3 EVB\n"); + return 0; + }; + +int dram_init(void) +{ + sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM); + + out_be16(&sdp->sdram_sdtr, 0xf539); + out_be16(&sdp->sdram_sdcr, 0x4211); + + /* Dummy write to start SDRAM */ + *((volatile unsigned long *)0) = 0; + + gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; + + return 0; + }; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf ("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/nxp/m5275evb/Kconfig b/board/nxp/m5275evb/Kconfig new file mode 100644 index 00000000000..99c9f192769 --- /dev/null +++ b/board/nxp/m5275evb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M5275EVB + +config SYS_CPU + default "mcf52x2" + +config SYS_BOARD + default "m5275evb" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "M5275EVB" + +endif diff --git a/board/nxp/m5275evb/MAINTAINERS b/board/nxp/m5275evb/MAINTAINERS new file mode 100644 index 00000000000..61a4cf3e324 --- /dev/null +++ b/board/nxp/m5275evb/MAINTAINERS @@ -0,0 +1,6 @@ +M5275EVB BOARD +M: Angelo Dureghello +S: Maintained +F: board/nxp/m5275evb/ +F: include/configs/M5275EVB.h +F: configs/M5275EVB_defconfig diff --git a/board/nxp/m5275evb/Makefile b/board/nxp/m5275evb/Makefile new file mode 100644 index 00000000000..83e3b10f0ed --- /dev/null +++ b/board/nxp/m5275evb/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y = m5275evb.o diff --git a/board/nxp/m5275evb/m5275evb.c b/board/nxp/m5275evb/m5275evb.c new file mode 100644 index 00000000000..8b986d42425 --- /dev/null +++ b/board/nxp/m5275evb/m5275evb.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com) + * + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define PERIOD 13 /* system bus period in ns */ +#define SDRAM_TREFI 7800 /* in ns */ + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale MCF5275 EVB\n"); + return 0; +}; + +int dram_init(void) +{ + sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM); + gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO); + + /* Enable SDRAM */ + out_be16(&gpio_reg->par_sdram, 0x3FF); + + /* Set up chip select */ + out_be32(&sdp->sdbar0, CFG_SYS_SDRAM_BASE); + out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V); + + /* Set up timing */ + out_be32(&sdp->sdcfg1, 0x83711630); + out_be32(&sdp->sdcfg2, 0x46770000); + + /* Enable clock */ + out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE); + + /* Set precharge */ + setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); + + /* Dummy write to start SDRAM */ + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; + + /* Send LEMR */ + setbits_be32(&sdp->sdmr, + MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) | + MCF_SDRAMC_SDMR_CMD); + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; + + /* Send LMR */ + out_be32(&sdp->sdmr, 0x058d0000); + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; + + /* Stop sending commands */ + clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD); + + /* Set precharge */ + setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; + + /* Stop manual precharge, send 2 IREF */ + clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); + setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF); + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; + + out_be32(&sdp->sdmr, 0x018d0000); + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; + + /* Stop sending commands */ + clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD); + clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN); + + /* Turn on auto refresh, lock SDMR */ + out_be32(&sdp->sdcr, + MCF_SDRAMC_SDCR_CKE + | MCF_SDRAMC_SDCR_REF + | MCF_SDRAMC_SDCR_MUX(1) + /* 1 added to round up */ + | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1) + | MCF_SDRAMC_SDCR_DQS_OE(0x3)); + + gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; + + return 0; +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/nxp/m5282evb/Kconfig b/board/nxp/m5282evb/Kconfig new file mode 100644 index 00000000000..06e43400ac4 --- /dev/null +++ b/board/nxp/m5282evb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M5282EVB + +config SYS_CPU + default "mcf52x2" + +config SYS_BOARD + default "m5282evb" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "M5282EVB" + +endif diff --git a/board/nxp/m5282evb/MAINTAINERS b/board/nxp/m5282evb/MAINTAINERS new file mode 100644 index 00000000000..8306581d3f0 --- /dev/null +++ b/board/nxp/m5282evb/MAINTAINERS @@ -0,0 +1,6 @@ +M5282EVB BOARD +M: Angelo Dureghello +S: Maintained +F: board/nxp/m5282evb/ +F: include/configs/M5282EVB.h +F: configs/M5282EVB_defconfig diff --git a/board/nxp/m5282evb/Makefile b/board/nxp/m5282evb/Makefile new file mode 100644 index 00000000000..e898f39330b --- /dev/null +++ b/board/nxp/m5282evb/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y = m5282evb.o diff --git a/board/nxp/m5282evb/m5282evb.c b/board/nxp/m5282evb/m5282evb.c new file mode 100644 index 00000000000..81da6e2abd4 --- /dev/null +++ b/board/nxp/m5282evb/m5282evb.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard (void) +{ + puts ("Board: Freescale M5282EVB Evaluation Board\n"); + return 0; +} + +int dram_init(void) +{ + u32 dramsize, i, dramclk; + + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE)) + { + dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ); + + /* Initialize DRAM Control Register: DCR */ + MCFSDRAMC_DCR = (0 + | MCFSDRAMC_DCR_RTIM_6 + | MCFSDRAMC_DCR_RC((15 * dramclk)>>4)); + asm("nop"); + + /* Initialize DACR0 */ + MCFSDRAMC_DACR0 = (0 + | MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE) + | MCFSDRAMC_DACR_CASL(1) + | MCFSDRAMC_DACR_CBM(3) + | MCFSDRAMC_DACR_PS_32); + asm("nop"); + + /* Initialize DMR0 */ + MCFSDRAMC_DMR0 = (0 + | ((dramsize - 1) & 0xFFFC0000) + | MCFSDRAMC_DMR_V); + asm("nop"); + + /* Set IP (bit 3) in DACR */ + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; + asm("nop"); + + /* Wait 30ns to allow banks to precharge */ + for (i = 0; i < 5; i++) { + asm ("nop"); + } + + /* Write to this block to initiate precharge */ + *(u32 *)(CFG_SYS_SDRAM_BASE) = 0xA5A59696; + asm("nop"); + + /* Set RE (bit 15) in DACR */ + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; + asm("nop"); + + /* Wait for at least 8 auto refresh cycles to occur */ + for (i = 0; i < 2000; i++) { + asm(" nop"); + } + + /* Finish the configuration by issuing the IMRS. */ + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; + asm("nop"); + + /* Write to the SDRAM Mode Register */ + *(u32 *)(CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; + } + gd->ram_size = dramsize; + + return 0; +} diff --git a/board/nxp/m53017evb/Kconfig b/board/nxp/m53017evb/Kconfig new file mode 100644 index 00000000000..3650134e742 --- /dev/null +++ b/board/nxp/m53017evb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M53017EVB + +config SYS_CPU + default "mcf532x" + +config SYS_BOARD + default "m53017evb" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "M53017EVB" + +endif diff --git a/board/nxp/m53017evb/MAINTAINERS b/board/nxp/m53017evb/MAINTAINERS new file mode 100644 index 00000000000..d07c409bc49 --- /dev/null +++ b/board/nxp/m53017evb/MAINTAINERS @@ -0,0 +1,6 @@ +M53017EVB BOARD +M: TsiChung Liew +S: Maintained +F: board/nxp/m53017evb/ +F: include/configs/M53017EVB.h +F: configs/M53017EVB_defconfig diff --git a/board/nxp/m53017evb/Makefile b/board/nxp/m53017evb/Makefile new file mode 100644 index 00000000000..4eeb3a860b9 --- /dev/null +++ b/board/nxp/m53017evb/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y = m53017evb.o diff --git a/board/nxp/m53017evb/README b/board/nxp/m53017evb/README new file mode 100644 index 00000000000..25831629266 --- /dev/null +++ b/board/nxp/m53017evb/README @@ -0,0 +1,178 @@ +Freescale MCF53017EVB ColdFire Development Board +================================================ + +TsiChung Liew(Tsi-Chung.Liew@freescale.com) +Created 10/22/08 +=========================================== + + +Changed files: +============== + +- board/nxp/m53017evb/m53017evb.c Dram setup +- board/nxp/m53017evb/mii.c Mii access +- board/nxp/m53017evb/Makefile Makefile +- board/nxp/m53017evb/config.mk config make +- board/nxp/m53017evb/u-boot.lds Linker description + +- arch/m68k/cpu/mcf532x/cpu.c cpu specific code +- arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs +- arch/m68k/cpu/mcf532x/interrupts.c cpu specific interrupt support +- arch/m68k/cpu/mcf532x/speed.c system, flexbus, and cpu clock +- arch/m68k/cpu/mcf532x/Makefile Makefile +- arch/m68k/cpu/mcf532x/config.mk config make +- arch/m68k/cpu/mcf532x/start.S start up assembly code + +- board/nxp/m53017evb/README his readme file + +- drivers/net/mcffec.c ColdFire common FEC driver +- drivers/net/mcfmii.c ColdFire common Mii driver +- drivers/serial/mcfuart.c ColdFire common UART driver +- drivers/rtc/mcfrtc.c Realtime clock Driver + +- include/asm-m68k/bitops.h Bit operation function export +- include/asm-m68k/byteorder.h Byte order functions +- include/asm-m68k/fec.h FEC structure and definition +- include/asm-m68k/fsl_i2c.h I2C structure and definition +- include/asm-m68k/global_data.h Global data structure +- include/asm-m68k/immap.h ColdFire specific header file and driver macros +- include/asm-m68k/immap_5301x.h mcf5301x specific header file +- include/asm-m68k/io.h io functions +- include/asm-m68k/m532x.h mcf5301x specific header file +- include/asm-m68k/posix_types.h Posix +- include/asm-m68k/processor.h header file +- include/asm-m68k/ptrace.h Exception structure +- include/asm-m68k/rtc.h Realtime clock header file +- include/asm-m68k/string.h String function export +- include/asm-m68k/timer.h Timer structure and definition +- include/asm-m68k/types.h Data types definition +- include/asm-m68k/uart.h Uart structure and definition +- include/asm-m68k/u-boot.h U-Boot structure + +- include/configs/M53017EVB.h Board specific configuration file + +- arch/m68k/lib/board.c board init function +- arch/m68k/lib/cache.c +- arch/m68k/lib/interrupts Coldfire common interrupt functions +- arch/m68k/lib/m68k_linux.c +- arch/m68k/lib/time.c Timer functions (Dma timer and PIT) +- arch/m68k/lib/traps.c Exception init code + +1 MCF5301x specific Options/Settings +==================================== +1.1 pre-loader is no longer suppoer in thie coldfire family + +1.2 Configuration settings for M53017EVB Development Board +CONFIG_MCF5301x -- define for all MCF5301x CPUs +CONFIG_M53015 -- define for MCF53015 CPUs +CONFIG_M53017EVB -- define for M53017EVB board + +CONFIG_MCFUART -- define to use common CF Uart driver +CFG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 +CONFIG_BAUDRATE -- define UART baudrate + +CONFIG_MCFRTC -- define to use common CF RTC driver +CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h +CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency +RTC_DEBUG -- define to show RTC debug message +CONFIG_CMD_DATE -- enable to use date feature in U-Boot + +CONFIG_MCFFEC -- define to use common CF FEC driver +CONFIG_MII -- enable to use MII driver +CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c +CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery +CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer +CONFIG_SYS_FAULT_ECHO_LINK_DOWN -- +CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration +CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register +MCFFEC_TOUT_LOOP -- set FEC timeout loop + +CONFIG_MCFTMR -- define to use DMA timer + +CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver +CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged +CONFIG_SYS_I2C_SPEED -- define for I2C speed +CONFIG_SYS_I2C_SLAVE -- define for I2C slave address +CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset +CONFIG_SYS_IMMR -- define for MBAR offset + +CFG_SYS_MBAR -- define MBAR offset + +CONFIG_MONITOR_IS_IN_RAM -- Not support + +CFG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM + +CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register +CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register +CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register + +CFG_SYS_SDRAM_BASE -- defines the DRAM Base + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. System memory map: + Flash: 0x00000000-0x3FFFFFFF (1024MB) + DDR: 0x40000000-0x7FFFFFFF (1024MB) + SRAM: 0x80000000-0x8FFFFFFF (256MB) + IP: 0xFC000000-0xFFFFFFFF (256MB) + +2.2. For the initial bringup, we adopted a consistent memory scheme between U-Boot and + linux kernel, you can customize it based on your system requirements: + Flash0: 0x00000000-0x00FFFFFF (16MB) + DDR: 0x40000000-0x4FFFFFFF (256MB) + SRAM: 0x80000000-0x80007FFF (32KB) + IP: 0xFC000000-0xFC0FFFFF (64KB) + +3. COMPILATION +============== +3.1 To create U-Boot the gcc-4.x-xx compiler set (ColdFire ELF or +uClinux version) from codesourcery.com was used. Download it from: +http://www.codesourcery.com/gnu_toolchains/coldfire/download.html + +3.2 Compilation + export CROSS_COMPILE=cross-compile-prefix + cd u-boot + make distclean + make M53017EVB_config + make + +4. SCREEN DUMP +============== +4.1 M53017EVB Development board + (NOTE: May not show exactly the same) + +U-Boot 2008.10 (Oct 22 2007 - 11:07:57) + +CPU: Freescale MCF53015 (Mask:76 Version:0) + CPU CLK 240 Mhz BUS CLK 80 Mhz +Board: Freescale M53017EVB +I2C: ready +DRAM: 64 MB +FLASH: 16 MB +In: serial +Out: serial +Err: serial +NAND: 16 MiB +Net: FEC0, FEC1 +-> print +bootdelay=1 +baudrate=115200 +ethaddr=00:e0:0c:bc:e5:60 +hostname=M53017EVB +netdev=eth0 +loadaddr=40010000 +u-boot=u-boot.bin +load=tftp ${loadaddr) ${u-boot} +upd=run load; run prog +prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save +gatewayip=192.168.1.1 +netmask=255.255.255.0 +ipaddr=192.168.1.3 +serverip=192.168.1.2 +stdin=serial +stdout=serial +stderr=serial +mem=65024k + +Environment size: 437/4092 bytes +-> diff --git a/board/nxp/m53017evb/m53017evb.c b/board/nxp/m53017evb/m53017evb.c new file mode 100644 index 00000000000..196d56dc17d --- /dev/null +++ b/board/nxp/m53017evb/m53017evb.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale M53017EVB\n"); + return 0; +}; + +int dram_init(void) +{ + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); + u32 dramsize, i; + + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; + + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); +#ifdef CFG_SYS_SDRAM_BASE1 + out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i); +#endif + out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2); + + udelay(500); + + /* Issue PALL */ + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); + asm("nop"); + + /* Perform two refresh cycles */ + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + asm("nop"); + + /* Issue LEMR */ + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE); + asm("nop"); + out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); + asm("nop"); + + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); + asm("nop"); + + out_be32(&sdram->ctrl, + (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); + asm("nop"); + + udelay(100); + + gd->ram_size = dramsize; + + return 0; +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/nxp/m5329evb/Kconfig b/board/nxp/m5329evb/Kconfig new file mode 100644 index 00000000000..73e4b42b201 --- /dev/null +++ b/board/nxp/m5329evb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M5329EVB + +config SYS_CPU + default "mcf532x" + +config SYS_BOARD + default "m5329evb" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "M5329EVB" + +endif diff --git a/board/nxp/m5329evb/MAINTAINERS b/board/nxp/m5329evb/MAINTAINERS new file mode 100644 index 00000000000..b9b07545156 --- /dev/null +++ b/board/nxp/m5329evb/MAINTAINERS @@ -0,0 +1,7 @@ +M5329EVB BOARD +M: TsiChung Liew +S: Maintained +F: board/nxp/m5329evb/ +F: include/configs/M5329EVB.h +F: configs/M5329AFEE_defconfig +F: configs/M5329BFEE_defconfig diff --git a/board/nxp/m5329evb/Makefile b/board/nxp/m5329evb/Makefile new file mode 100644 index 00000000000..19796c213fb --- /dev/null +++ b/board/nxp/m5329evb/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y = m5329evb.o nand.o diff --git a/board/nxp/m5329evb/m5329evb.c b/board/nxp/m5329evb/m5329evb.c new file mode 100644 index 00000000000..26d5f3bf58c --- /dev/null +++ b/board/nxp/m5329evb/m5329evb.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale FireEngine 5329 EVB\n"); + return 0; +}; + +int dram_init(void) +{ + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); + u32 dramsize, i; + + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; + + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2); + + /* Issue PALL */ + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); + + /* Issue LEMR */ + out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000); + + udelay(500); + + /* Issue PALL */ + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); + + /* Perform two refresh cycles */ + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE); + + out_be32(&sdram->ctrl, + (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); + + udelay(100); + + gd->ram_size = dramsize; + + return 0; +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/nxp/m5329evb/nand.c b/board/nxp/m5329evb/nand.c new file mode 100644 index 00000000000..a250d61ef36 --- /dev/null +++ b/board/nxp/m5329evb/nand.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + */ + +#include +#include +#include + +#if defined(CONFIG_CMD_NAND) +#include +#include +#include + +#define SET_CLE 0x10 +#define SET_ALE 0x08 + +static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd_to_nand(mtdinfo); + volatile u16 *nCE = (u16 *) CFG_SYS_LATCH_ADDR; + + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + IO_ADDR_W &= ~(SET_ALE | SET_CLE); + + if (ctrl & NAND_NCE) + *nCE &= 0xFFFB; + else + *nCE |= 0x0004; + + if (ctrl & NAND_CLE) + IO_ADDR_W |= SET_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= SET_ALE; + + this->IO_ADDR_W = (void *)IO_ADDR_W; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +int board_nand_init(struct nand_chip *nand) +{ + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* + * set up pin configuration - enabled 2nd output buffer's signals + * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) + * to use nCE signal + */ + clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3); + setbits_8(&gpio->pddr_timer, 0x08); + setbits_8(&gpio->ppd_timer, 0x08); + out_8(&gpio->pclrr_timer, 0); + out_8(&gpio->podr_timer, 0); + + nand->chip_delay = 60; + nand->ecc.mode = NAND_ECC_SOFT; + nand->cmd_ctrl = nand_hwcontrol; + + return 0; +} +#endif diff --git a/board/nxp/m5373evb/Kconfig b/board/nxp/m5373evb/Kconfig new file mode 100644 index 00000000000..5ac013771f1 --- /dev/null +++ b/board/nxp/m5373evb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_M5373EVB + +config SYS_CPU + default "mcf532x" + +config SYS_BOARD + default "m5373evb" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "M5373EVB" + +endif diff --git a/board/nxp/m5373evb/MAINTAINERS b/board/nxp/m5373evb/MAINTAINERS new file mode 100644 index 00000000000..5a185d1220a --- /dev/null +++ b/board/nxp/m5373evb/MAINTAINERS @@ -0,0 +1,6 @@ +M5373EVB BOARD +M: TsiChung Liew +S: Maintained +F: board/nxp/m5373evb/ +F: include/configs/M5373EVB.h +F: configs/M5373EVB_defconfig diff --git a/board/nxp/m5373evb/Makefile b/board/nxp/m5373evb/Makefile new file mode 100644 index 00000000000..20efa7b8432 --- /dev/null +++ b/board/nxp/m5373evb/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y = m5373evb.o nand.o diff --git a/board/nxp/m5373evb/README b/board/nxp/m5373evb/README new file mode 100644 index 00000000000..c7130b32251 --- /dev/null +++ b/board/nxp/m5373evb/README @@ -0,0 +1,324 @@ +Freescale MCF5373EVB ColdFire Development Board +================================================ + +TsiChung Liew(Tsi-Chung.Liew@freescale.com) +Created 11/08/07 +=========================================== + + +Changed files: +============== + +- board/nxp/m5373evb/m5373evb.c Dram setup +- board/nxp/m5373evb/mii.c Mii access +- board/nxp/m5373evb/Makefile Makefile +- board/nxp/m5373evb/config.mk config make +- board/nxp/m5373evb/u-boot.lds Linker description + +- arch/m68k/cpu/mcf532x/cpu.c cpu specific code +- arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs +- arch/m68k/cpu/mcf532x/interrupts.c cpu specific interrupt support +- arch/m68k/cpu/mcf532x/speed.c system, pci, flexbus, and cpu clock +- arch/m68k/cpu/mcf532x/Makefile Makefile +- arch/m68k/cpu/mcf532x/config.mk config make +- arch/m68k/cpu/mcf532x/start.S start up assembly code + +- board/nxp/m5373evb/README This readme file + +- drivers/net/mcffec.c ColdFire common FEC driver +- drivers/serial/mcfuart.c ColdFire common UART driver +- drivers/rtc/mcfrtc.c Realtime clock Driver + +- include/asm-m68k/bitops.h Bit operation function export +- include/asm-m68k/byteorder.h Byte order functions +- include/asm-m68k/fec.h FEC structure and definition +- include/asm-m68k/fsl_i2c.h I2C structure and definition +- include/asm-m68k/global_data.h Global data structure +- include/asm-m68k/immap.h ColdFire specific header file and driver macros +- include/asm-m68k/immap_532x.h mcf532x specific header file +- include/asm-m68k/io.h io functions +- include/asm-m68k/m532x.h mcf532x specific header file +- include/asm-m68k/posix_types.h Posix +- include/asm-m68k/processor.h header file +- include/asm-m68k/ptrace.h Exception structure +- include/asm-m68k/rtc.h Realtime clock header file +- include/asm-m68k/string.h String function export +- include/asm-m68k/timer.h Timer structure and definition +- include/asm-m68k/types.h Data types definition +- include/asm-m68k/uart.h Uart structure and definition +- include/asm-m68k/u-boot.h U-Boot structure + +- include/configs/M5373EVB.h Board specific configuration file + +- arch/m68k/lib/board.c board init function +- arch/m68k/lib/cache.c +- arch/m68k/lib/interrupts Coldfire common interrupt functions +- arch/m68k/lib/m68k_linux.c +- arch/m68k/lib/time.c Timer functions (Dma timer and PIT) +- arch/m68k/lib/traps.c Exception init code + +1 MCF5373 specific Options/Settings +==================================== +1.1 pre-loader is no longer suppoer in thie coldfire family + +1.2 Configuration settings for M5373EVB Development Board +CONFIG_MCF532x -- define for all MCF532x CPUs +CONFIG_M5373 -- define for all Freescale MCF5373 CPUs +CONFIG_M5373EVB -- define for M5373EVB board + +CONFIG_MCFUART -- define to use common CF Uart driver +CFG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 +CONFIG_BAUDRATE -- define UART baudrate + +CONFIG_MCFRTC -- define to use common CF RTC driver +CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h +CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency +RTC_DEBUG -- define to show RTC debug message +CONFIG_CMD_DATE -- enable to use date feature in U-Boot + +CONFIG_MCFFEC -- define to use common CF FEC driver +CONFIG_MII -- enable to use MII driver +CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c +CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery +CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer +CONFIG_SYS_FAULT_ECHO_LINK_DOWN-- +CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration +CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register +MCFFEC_TOUT_LOOP -- set FEC timeout loop + +CONFIG_MCFTMR -- define to use DMA timer + +CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver +CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged +CONFIG_SYS_I2C_SPEED -- define for I2C speed +CONFIG_SYS_I2C_SLAVE -- define for I2C slave address +CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset +CONFIG_SYS_IMMR -- define for MBAR offset + +CFG_SYS_MBAR -- define MBAR offset + +CONFIG_MONITOR_IS_IN_RAM -- Not support + +CFG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5373 internal SRAM + +CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register +CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register +CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register + +CFG_SYS_SDRAM_BASE -- defines the DRAM Base + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. System memory map: + Flash: 0x00000000-0x3FFFFFFF (1024MB) + DDR: 0x40000000-0x7FFFFFFF (1024MB) + SRAM: 0x80000000-0x8FFFFFFF (256MB) + IP: 0xF0000000-0xFFFFFFFF (256MB) + +2.2. For the initial bringup, we adopted a consistent memory scheme between U-Boot and + linux kernel, you can customize it based on your system requirements: + Flash0: 0x00000000-0x00FFFFFF (16MB) + + DDR: 0x40000000-0x4FFFFFFF (256MB) + SRAM: 0x80000000-0x80007FFF (32KB) + IP: 0xFC000000-0xFC0FFFFF (64KB) + +3. COMPILATION +============== +3.1 To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or +uClinux version) from codesourcery.com was used. Download it from: +http://www.codesourcery.com/gnu_toolchains/coldfire/download.html + +3.2 Compilation + export CROSS_COMPILE=cross-compile-prefix + cd u-boot-1.x.x + make distclean + make M5373EVB_config + make + +4. SCREEN DUMP +============== +4.1 M5373EVB Development board + (NOTE: May not show exactly the same) + +U-Boot 1.3.0 (Nov 8 2007 - 12:44:08) + +CPU: Freescale MCF5373 (Mask:65 Version:1) + CPU CLK 240 Mhz BUS CLK 80 Mhz +Board: Freescale FireEngine 5373 EVB +I2C: ready +DRAM: 32 MB +FLASH: 2 MB +In: serial +Out: serial +Err: serial +NAND: 16 MiB +Net: FEC0 +-> print +bootdelay=1 +baudrate=115200 +ethaddr=00:e0:0c:bc:e5:60 +hostname=M5373EVB +netdev=eth0 +loadaddr=40010000 +load=tftp ${loadaddr) ${u-boot} +upd=run load; run prog +prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save +ethact=FEC0 +u-boot=u-boot.bin +gatewayip=192.168.1.1 +netmask=255.255.255.0 +ipaddr=192.168.1.3 +serverip=192.168.1.2 +stdin=serial +stdout=serial +stderr=serial +mem=261632k + +Environment size: 401/8188 bytes +-> bdinfo +memstart = 0x40000000 +memsize = 0x02000000 +flashstart = 0x00000000 +flashsize = 0x00200000 +flashoffset = 0x00000000 +sramstart = 0x80000000 +sramsize = 0x00008000 +mbar = 0xFC000000 +busfreq = 80 MHz +ethaddr = 00:E0:0C:BC:E5:60 +ip_addr = 192.168.1.3 +baudrate = 115200 bps +-> +-> help +? - alias for 'help' +base - print or set address offset +bdinfo - print Board Info structure +boot - boot default, i.e., run 'bootcmd' +bootd - boot default, i.e., run 'bootcmd' +bootelf - Boot from an ELF image in memory +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +bootvx - Boot vxWorks from an ELF image +cmp - memory compare +coninfo - print console devices and information +cp - memory copy +crc32 - checksum calculation +date - get/set/reset date & time +dcache - enable or disable data cache +echo - echo args to console +erase - erase FLASH memory +flinfo - print FLASH memory information +go - start application at address 'addr' +help - print online help +i2c - I2C sub-system +icache - enable or disable instruction cache +iminfo - print header information for application image +imls - list all images found in flash +itest - return true/false on integer compare +loadb - load binary file over serial line (kermit mode) +loads - load S-Record file over serial line +loady - load binary file over serial line (ymodem mode) +loop - infinite loop on address range +ls - list files in a directory (default /) +md - memory display +mii - MII utility commands +mm - memory modify (auto-incrementing) +mtest - simple RAM test +mw - memory write (fill) +nand - NAND sub-system +nboot - boot from NAND device +nfs - boot image via network using NFS protocol +nm - memory modify (constant address) +ping - send ICMP ECHO_REQUEST to network host +printenv- print environment variables +protect - enable or disable FLASH write protection +rarpboot- boot image via network using RARP/TFTP protocol +reset - Perform RESET of the CPU +run - run commands in an environment variable +saveenv - save environment variables to persistent storage +setenv - set environment variables +sleep - delay execution for some time +source - run script from memory +tftpboot- boot image via network using TFTP protocol +version - print monitor version +-> tftp 0x40800000 uImage +Using FEC0 device +TFTP from server 192.168.1.3; our IP address is 192.168.1.3 Filename 'uImage'. +Load address: 0x40800000 +Loading: ################################################################# + ################################################################# + ########## +done +Bytes transferred = 2053270 (1f5496 hex) +-> bootm 0x40800000 +## Booting image at 40800000 ... + Image Name: Linux Kernel Image + Created: 2007-11-07 20:33:08 UTC + Image Type: M68K Linux Kernel Image (gzip compressed) + Data Size: 2053206 Bytes = 2 MB + Load Address: 40020000 + Entry Point: 40020000 + Verifying Checksum ... OK + Uncompressing Kernel Image ... OK +Linux version 2.6.22-uc1 (mattw@loa) (gcc version 4.2.1 (Sourcery G++ Lite 4.2-7 + + +uClinux/COLDFIRE(m537x) +COLDFIRE port done by Greg Ungerer, gerg@snapgear.com Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne Built 1 zonelists. Total pages: 8128 Kernel command line: rootfstype=romfs PID hash table entries: 128 (order: 7, 512 bytes) Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) Memory available: 28092k/32768k RAM, (1788k kernel code, 244k data) Mount-cache hash table entries: 512 +NET: Registered protocol family 16 +USB-MCF537x: (HOST module) EHCI device is registered +USB-MCF537x: (OTG module) EHCI device is registered +USB-MCF537x: (OTG module) UDC device is registered +usbcore: registered new interface driver usbfs +usbcore: registered new interface driver hub +usbcore: registered new device driver usb +NET: Registered protocol family 2 +IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 1024 (order: 1, 8192 bytes) TCP bind hash table entries: 1024 (order: 0, 4096 bytes) +TCP: Hash tables configured (established 1024 bind 1024) TCP reno registered +JFFS2 version 2.2. (NAND) © 2001-2006 Red Hat, Inc. +io scheduler noop registered +io scheduler cfq registered (default) +ColdFire internal UART serial driver version 1.00 ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART +ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART +ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize +loop: module loaded +nbd: registered device at major 43 +usbcore: registered new interface driver ub FEC ENET Version 0.2 +fec: PHY @ 0x1, ID 0x20005c90 -- DP83848 +eth0: ethernet 00:e0:0c:bc:e5:60 +uclinux[mtd]: RAM probe address=0x4021c22c size=0x22b000 Creating 1 MTD partitions on "RAM": +0x00000000-0x0022b000 : "ROMfs" +uclinux[mtd]: set ROMfs to be root filesystem NAND device: Manufacturer ID: 0x20, Chip ID: 0x73 (ST Micro NAND 16MiB 3,3V 8-b) Scanning device for bad blocks Creating 1 MTD partitions on "NAND 16MiB 3,3V 8-bit": +0x00000000-0x01000000 : "M53xx flash partition 1" +QSPI: spi->max_speed_hz 300000 +QSPI: Baud set to 255 +SPI: Coldfire master initialized +M537x - Disable UART1 when using Audio +udc: Freescale MCF53xx UDC driver version 27 October 2006 init +udc: MCF53xx USB Device is found. ID=0x5 Rev=0x41 i2c /dev entries driver +usbcore: registered new interface driver usbhid +drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver TCP cubic registered +NET: Registered protocol family 1 +NET: Registered protocol family 17 +VFS: Mounted root (romfs filesystem) readonly. +Freeing unused kernel memory: 64k freed (0x401f5000 - 0x40204000) init started: BusyBox v1.00 (2007.11.07-19:57+0000) multi-call binary?Setting e Mounting filesystems +mount: Mounting devpts on /dev/pts failed: No such device +mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory Starting syslogd and klogd Setting up networking on loopback device: +Setting up networking on eth0: +info, udhcpc (v0.9.9-pre) started +eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX. +debug, Sending discover... +debug, Sending discover... +debug, Sending select for 172.27.0.130... +info, Lease of 172.27.0.130 obtained, lease time 43200 deleting routers +route: SIOC[ADD|DEL]RT: No such process +adding dns 172.27.0.1 +Starting the boa webserver: +Setting time from ntp server: ntp.cs.strath.ac.uk +ntp.cs.strath.ac.uk: Unknown host + + +BusyBox v1.00 (2007.11.07-19:57+0000) Built-in shell (msh) Enter 'help' for a list of built-in commands. + +# diff --git a/board/nxp/m5373evb/m5373evb.c b/board/nxp/m5373evb/m5373evb.c new file mode 100644 index 00000000000..d6fdf41bab4 --- /dev/null +++ b/board/nxp/m5373evb/m5373evb.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale FireEngine 5373 EVB\n"); + return 0; +}; + +int dram_init(void) +{ + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); + u32 dramsize, i; + + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; + + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2); + + /* Issue PALL */ + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); + + /* Issue LEMR */ + out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000); + + udelay(500); + + /* Issue PALL */ + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); + + /* Perform two refresh cycles */ + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE); + + out_be32(&sdram->ctrl, + (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); + + udelay(100); + + gd->ram_size = dramsize; + + return 0; +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/nxp/m5373evb/nand.c b/board/nxp/m5373evb/nand.c new file mode 100644 index 00000000000..e7c08d22e6b --- /dev/null +++ b/board/nxp/m5373evb/nand.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + */ + +#include +#include +#include + +#if defined(CONFIG_CMD_NAND) +#include +#include +#include + +#define SET_CLE 0x10 +#define SET_ALE 0x08 + +static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd_to_nand(mtdinfo); + volatile u16 *nCE = (u16 *) CFG_SYS_LATCH_ADDR; + + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + IO_ADDR_W &= ~(SET_ALE | SET_CLE); + + if (ctrl & NAND_NCE) + *nCE &= 0xFFFB; + else + *nCE |= 0x0004; + + if (ctrl & NAND_CLE) + IO_ADDR_W |= SET_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= SET_ALE; + + this->IO_ADDR_W = (void *)IO_ADDR_W; + + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +int board_nand_init(struct nand_chip *nand) +{ + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + + clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP); + + /* + * set up pin configuration - enabled 2nd output buffer's signals + * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) + * to use nCE signal + */ + clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3); + setbits_8(&gpio->pddr_timer, 0x08); + setbits_8(&gpio->ppd_timer, 0x08); + out_8(&gpio->pclrr_timer, 0); + out_8(&gpio->podr_timer, 0); + + nand->chip_delay = 60; + nand->ecc.mode = NAND_ECC_SOFT; + nand->cmd_ctrl = nand_hwcontrol; + + return 0; +} +#endif diff --git a/board/nxp/mpc837xerdb/Kconfig b/board/nxp/mpc837xerdb/Kconfig new file mode 100644 index 00000000000..f11f6f5bfea --- /dev/null +++ b/board/nxp/mpc837xerdb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MPC837XERDB + +config PCIE + def_bool y + +config SYS_BOARD + default "mpc837xerdb" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "MPC837XERDB" + +endif diff --git a/board/nxp/mpc837xerdb/MAINTAINERS b/board/nxp/mpc837xerdb/MAINTAINERS new file mode 100644 index 00000000000..9b05a6ad421 --- /dev/null +++ b/board/nxp/mpc837xerdb/MAINTAINERS @@ -0,0 +1,7 @@ +MPC837XERDB BOARD +M: Sinan Akman +S: Maintained +F: board/nxp/mpc837xerdb/ +F: include/configs/MPC837XERDB.h +F: configs/MPC837XERDB_defconfig +F: configs/MPC837XERDB_SLAVE_defconfig diff --git a/board/nxp/mpc837xerdb/Makefile b/board/nxp/mpc837xerdb/Makefile new file mode 100644 index 00000000000..4661e4cf232 --- /dev/null +++ b/board/nxp/mpc837xerdb/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y += mpc837xerdb.o diff --git a/board/nxp/mpc837xerdb/README b/board/nxp/mpc837xerdb/README new file mode 100644 index 00000000000..12df2f2e756 --- /dev/null +++ b/board/nxp/mpc837xerdb/README @@ -0,0 +1,97 @@ +Freescale MPC837xE-RDB Board +----------------------------------------- + +1. Board Description + + The MPC837xE-RDB are reference boards featuring the Freescale MPC8377E, + MPC8378E, and the MPC8379E processors in a Mini-ITX form factor. + + The MPC837xE-RDB's have the following common features: + + A) 256-MBytes on-board DDR2 unbuffered SDRAM + B) 8-Mbytes NOR Flash + C) 32-MBytes NAND Flash + D) 1 Secure Digital High Speed Card (SDHC) Interface + E) 1 Gigabit Ethernet + F) 5-port Ethernet switch (Vitesse 7385) + G) 1 32-bit, 3.3 V, PCI slot + H) 1 32-bit, 3.3 V, Mini-PCI slot + I) 4-port USB 2.0 Hub + J) 1-port OTG USB + K) 2 serial ports (top main console) + L) on board Oscillator: 66M + + The MPC837xE-RDB's have the following differences: + + MPC8377E-RDB MPC8378E-RDB MPC8379E-RDB + SATA controllers 2 0 4 + PCI-Express (mini) 2 2 0 + SGMII Ports 0 2 0 + + +2. Memory Map + +2.1. The memory map should look pretty much like this: + + Address Range Device Size Port Size + (Bytes) (Bits) + =========================== ================= ======= ========= + 0x0000_0000 0x0fff_ffff DDR 256M 64 + 0x1000_0000 0x7fff_ffff Empty 1.75G - + 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M 32 + 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M 32 + 0xe030_0000 0xe03f_ffff PCI I/O space 1M 32 + 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M - + 0xe060_0000 0xe060_7fff NAND Flash 32K 8 + 0xfe00_0000 0xfe7f_ffff NOR Flash on CS0 8M 16 + + +3. Definitions + +3.1 Explanation of NEW definitions in: + + include/configs/MPC837XERDB.h + + CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360 + CONFIG_MPC837x MPC837x specific + CONFIG_MPC837XERDB MPC837xE-RDB board specific + + +4. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make MPC837XERDB_config + make + + +5. Downloading and Flashing Images + +5.0 Download over serial line using Kermit: + + loadb $loadaddr + [Drop to kermit: + ^\c + send + c + ] + + + Or via tftp: + + tftp $loadaddr u-boot.bin + +5.1 Reflash U-Boot Image using U-Boot + + tftp $loadaddr u-boot.bin + protect off fe000000 fe0fffff + erase fe000000 fe0fffff + cp.b $loadaddr fe000000 $filesize + + +6. Additional Notes: + 1) The console is connected to the top RS-232 connector and the + baudrate for MPC837XE-RDB is 115200bps. diff --git a/board/nxp/mpc837xerdb/mpc837xerdb.c b/board/nxp/mpc837xerdb/mpc837xerdb.c new file mode 100644 index 00000000000..55299745a3c --- /dev/null +++ b/board/nxp/mpc837xerdb/mpc837xerdb.c @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Kevin Lam + * Joe D'Abbraccio + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CFG_SYS_DRAM_TEST) +int +testdram(void) +{ + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; + uint *p; + + printf("Testing DRAM from 0x%08x to 0x%08x\n", + CONFIG_SYS_MEMTEST_START, + CONFIG_SYS_MEMTEST_END); + + printf("DRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test passed.\n"); + return 0; +} +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +void ddr_enable_ecc(unsigned int dram_size); +#endif +int fixed_sdram(void); + +int dram_init(void) +{ + immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -ENXIO; + +#if defined(CONFIG_SPD_EEPROM) + msize = spd_sdram(); +#else + msize = fixed_sdram(); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* Initialize DDR ECC byte */ + ddr_enable_ecc(msize * 1024 * 1024); +#endif + /* return total bus DDR size(bytes) */ + gd->ram_size = msize * 1024 * 1024; + + return 0; +} + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msize = CFG_SYS_SDRAM_SIZE; + u32 msize_log2 = __ilog2(msize); + + im->sysconf.ddrlaw[0].bar = CFG_SYS_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); + + im->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE; + udelay(50000); + + im->ddr.sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL; + udelay(1000); + + im->ddr.csbnds[0].csbnds = CFG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CFG_SYS_DDR_CS0_CONFIG; + udelay(1000); + + im->ddr.timing_cfg_0 = CFG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CFG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CFG_SYS_DDR_INTERVAL; + sync(); + udelay(1000); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + udelay(2000); + return CFG_SYS_SDRAM_SIZE >> 20; +} +#endif /*!CONFIG_SYS_SPD_EEPROM */ + +int checkboard(void) +{ + puts("Board: Freescale MPC837xERDB\n"); + return 0; +} + +int board_early_init_f(void) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; +#ifdef CONFIG_FSL_SERDES + u32 spridr = in_be32(&immr->sysconf.spridr); + + /* we check only part num, and don't look for CPU revisions */ + switch (PARTID_NO_E(spridr)) { + case SPR_8377: + fsl_setup_serdes(CFG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + case SPR_8378: + fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + case SPR_8379: + fsl_setup_serdes(CFG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + break; + default: + printf("serdes not configured: unknown CPU part number: " + "%04x\n", spridr >> 16); + break; + } +#endif /* CONFIG_FSL_SERDES */ + +#ifdef CONFIG_FSL_ESDHC + clrsetbits_be32(&immr->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); + clrsetbits_be32(&immr->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD); +#endif + return 0; +} + +#ifdef CONFIG_FSL_ESDHC +#if !(CONFIG_IS_ENABLED(DM_MMC) || CONFIG_IS_ENABLED(DM_USB)) +int board_mmc_init(struct bd_info *bd) +{ + struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; + char buffer[HWCONFIG_BUFFER_SIZE] = {0}; + int esdhc_hwconfig_enabled = 0; + + if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0) + esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer); + + if (esdhc_hwconfig_enabled == 0) + return 0; + + clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); + clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD); + + return fsl_esdhc_mmc_init(bd); +} +#endif +#endif + +/* + * Miscellaneous late-boot configurations + * + * If a VSC7385 microcode image is present, then upload it. +*/ +int misc_init_r(void) +{ + int rc = 0; + +#ifdef CFG_VSC7385_IMAGE + if (vsc7385_upload_firmware((void *) CFG_VSC7385_IMAGE, + CFG_VSC7385_IMAGE_SIZE)) { + puts("Failure uploading VSC7385 microcode.\n"); + rc = 1; + } +#endif + + return rc; +} + +int board_late_init(void) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; +#ifdef CONFIG_USB_HOST + clrsetbits_be32(&immap->sysconf.sicrl, SICRL_USB_A, 0x40000000); +#endif + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) + +int ft_board_setup(void *blob, struct bd_info *bd) +{ +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); + fsl_fdt_fixup_dr_usb(blob, bd); + fdt_fixup_esdhc(blob, bd); + + return 0; +} +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/nxp/mpc8548cds/Kconfig b/board/nxp/mpc8548cds/Kconfig new file mode 100644 index 00000000000..e43c2030e00 --- /dev/null +++ b/board/nxp/mpc8548cds/Kconfig @@ -0,0 +1,24 @@ +if TARGET_MPC8548CDS + +config PCI1 + def_bool y + +config FSL_CADMUS + def_bool y + +config INTERRUPTS + def_bool y + +config SYS_BOARD + default "mpc8548cds" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "MPC8548CDS" + +config TARGET_MPC8548CDS_LEGACY + bool "Legacy platform support" + +endif diff --git a/board/nxp/mpc8548cds/MAINTAINERS b/board/nxp/mpc8548cds/MAINTAINERS new file mode 100644 index 00000000000..51e62a34365 --- /dev/null +++ b/board/nxp/mpc8548cds/MAINTAINERS @@ -0,0 +1,8 @@ +MPC8548CDS BOARD +M: Priyanka Jain +S: Maintained +F: board/nxp/mpc8548cds/ +F: include/configs/MPC8548CDS.h +F: configs/MPC8548CDS_defconfig +F: configs/MPC8548CDS_36BIT_defconfig +F: configs/MPC8548CDS_legacy_defconfig diff --git a/board/nxp/mpc8548cds/Makefile b/board/nxp/mpc8548cds/Makefile new file mode 100644 index 00000000000..5ed40e92eb9 --- /dev/null +++ b/board/nxp/mpc8548cds/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2004 Freescale Semiconductor. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y += mpc8548cds.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/nxp/mpc8548cds/ddr.c b/board/nxp/mpc8548cds/ddr.c new file mode 100644 index 00000000000..4b8ddcc3ae4 --- /dev/null +++ b/board/nxp/mpc8548cds/ddr.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2008 Freescale Semiconductor, Inc. + */ + +#include +#include + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 7; + + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 10; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/nxp/mpc8548cds/law.c b/board/nxp/mpc8548cds/law.c new file mode 100644 index 00000000000..2334870fda0 --- /dev/null +++ b/board/nxp/mpc8548cds/law.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2008,2010-2011 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#include +#include +#include + +struct law_entry law_table[] = { + /* LBC window - maps 256M */ + SET_LAW(CFG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/nxp/mpc8548cds/mpc8548cds.c b/board/nxp/mpc8548cds/mpc8548cds.c new file mode 100644 index 00000000000..7810010fd04 --- /dev/null +++ b/board/nxp/mpc8548cds/mpc8548cds.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc. + * + * (C) Copyright 2002 Scott McNutt + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/cadmus.h" +#include "../common/eeprom.h" +#include "../common/via.h" + +void local_bus_init(void); + +int checkboard (void) +{ + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR); + + /* PCI slot in USER bits CSR[6:7] by convention. */ + uint pci_slot = get_pci_slot (); + + uint cpu_board_rev = get_cpu_board_revision (); + + puts("Board: MPC8548CDS"); + printf(" Carrier Rev: 0x%02x, PCI Slot %d\n", + get_board_version(), pci_slot); + printf(" Daughtercard Rev: %d.%d (0x%04x)\n", + MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), + MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); + /* + * Initialize local bus. + */ + local_bus_init (); + + /* + * Hack TSEC 3 and 4 IO voltages. + */ + gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ + + ecm->eedr = 0xffffffff; /* clear ecm errors */ + ecm->eeer = 0xffffffff; /* enable ecm errors */ + return 0; +} + +/* + * Initialize Local Bus + */ +void +local_bus_init(void) +{ + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; + + uint clkdiv; + sys_info_t sysinfo; + + get_sys_info(&sysinfo); + clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; + + gur->lbiuiplldcr1 = 0x00078080; + if (clkdiv == 16) { + gur->lbiuiplldcr0 = 0x7c0f1bf0; + } else if (clkdiv == 8) { + gur->lbiuiplldcr0 = 0x6c0f1bf0; + } else if (clkdiv == 4) { + gur->lbiuiplldcr0 = 0x5c0f1bf0; + } + + lbc->lcrr |= 0x00030000; + + asm("sync;isync;msync"); + + lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ + lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ +} + +/* + * Initialize SDRAM memory on the Local Bus. + */ +void lbc_sdram_init(void) +{ +#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) + + uint idx; + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; + uint *sdram_addr = (uint *)CFG_SYS_LBC_SDRAM_BASE; + uint lsdmr_common; + + puts("LBC SDRAM: "); + print_size(CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, + "\n"); + + /* + * Setup SDRAM Base and Option Registers + */ + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); + lbc->lbcr = CFG_SYS_LBC_LBCR; + asm("msync"); + + lbc->lsrt = CFG_SYS_LBC_LSRT; + lbc->mrtpr = CFG_SYS_LBC_MRTPR; + asm("msync"); + + /* + * MPC8548 uses "new" 15-16 style addressing. + */ + lsdmr_common = CFG_SYS_LBC_LSDMR_COMMON; + lsdmr_common |= LSDMR_BSMA1516; + + /* + * Issue PRECHARGE ALL command. + */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue 8 AUTO REFRESH commands. + */ + for (idx = 0; idx < 8; idx++) { + lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + } + + /* + * Issue 8 MODE-set command. + */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue NORMAL OP command. + */ + lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(200); /* Overkill. Must wait > 200 bus cycles */ + +#endif /* enable SDRAM init */ +} diff --git a/board/nxp/mpc8548cds/tlb.c b/board/nxp/mpc8548cds/tlb.c new file mode 100644 index 00000000000..0b2afa8054d --- /dev/null +++ b/board/nxp/mpc8548cds/tlb.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2008, 2011 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#include +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* + * Entry 0: + * FLASH(cover boot page) 16M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_16M, 1), + + /* + * Entry 1: + * CCSRBAR 1M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* + * Entry 2: + * LBC SDRAM 64M Cacheable, non-guarded + */ + SET_TLB_ENTRY(1, CFG_SYS_LBC_SDRAM_BASE, + CFG_SYS_LBC_SDRAM_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 2, BOOKE_PAGESZ_64M, 1), + + /* + * Entry 3: + * CADMUS registers 1M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1M, 1), + + /* + * Entry 4: + * PCI and PCIe MEM 1G Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_VIRT, CFG_SYS_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_1G, 1), + + /* + * Entry 5: + * PCI1 IO 1M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CFG_SYS_PCI1_IO_VIRT, CFG_SYS_PCI1_IO_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_1M, 1), + + /* + * Entry 6: + * PCIe IO 1M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_1M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/nxp/mx23evk/Kconfig b/board/nxp/mx23evk/Kconfig new file mode 100644 index 00000000000..9f57590386b --- /dev/null +++ b/board/nxp/mx23evk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX23EVK + +config SYS_BOARD + default "mx23evk" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "mx23evk" + +endif diff --git a/board/nxp/mx23evk/MAINTAINERS b/board/nxp/mx23evk/MAINTAINERS new file mode 100644 index 00000000000..5ac8c3e8a86 --- /dev/null +++ b/board/nxp/mx23evk/MAINTAINERS @@ -0,0 +1,8 @@ +MX23EVK BOARD +M: Fabio Estevam +M: Otavio Salvador +S: Maintained +F: board/nxp/mx23evk/ +F: arch/arm/dts/imx23-evk.dts +F: include/configs/mx23evk.h +F: configs/mx23evk_defconfig diff --git a/board/nxp/mx23evk/Makefile b/board/nxp/mx23evk/Makefile new file mode 100644 index 00000000000..5cc99ab1836 --- /dev/null +++ b/board/nxp/mx23evk/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +ifndef CONFIG_XPL_BUILD +obj-y := mx23evk.o +else +obj-y := spl_boot.o +endif diff --git a/board/nxp/mx23evk/mx23evk.c b/board/nxp/mx23evk/mx23evk.c new file mode 100644 index 00000000000..fbc8fbdbf59 --- /dev/null +++ b/board/nxp/mx23evk/mx23evk.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Freescale MX23EVK board + * + * (C) Copyright 2013 O.S. Systems Software LTDA. + * + * Author: Otavio Salvador + * + * Based on m28evk.c: + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ +int board_early_init_f(void) +{ + /* IO0 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK0, 480000); + + /* SSP0 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); + + /* Power on LCD */ + gpio_direction_output(MX23_PAD_LCD_RESET__GPIO_1_18, 1); + + /* Set contrast to maximum */ + gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1); + + return 0; +} + +int dram_init(void) +{ + return mxs_dram_init(); +} + +int board_init(void) +{ + /* Adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} diff --git a/board/nxp/mx23evk/spl_boot.c b/board/nxp/mx23evk/spl_boot.c new file mode 100644 index 00000000000..a4c39a35221 --- /dev/null +++ b/board/nxp/mx23evk/spl_boot.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Freescale MX23EVK Boot setup + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ + +#include +#include +#include +#include +#include + +#define MUX_CONFIG_SSP1 (MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_LCD (MXS_PAD_4MA | MXS_PAD_NOPULL) + +const iomux_cfg_t iomux_setup[] = { + /* DUART */ + MX23_PAD_PWM0__DUART_RX, + MX23_PAD_PWM1__DUART_TX, + + /* EMI */ + MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI, + MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI, + + MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI, + MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI, + MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + + MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + + /* MMC 0 */ + MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP1, + MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP1, + MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP1, + MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP1, + MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP1, + MX23_PAD_SSP1_DETECT__SSP1_DETECT | MUX_CONFIG_SSP1, + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX23_PAD_SSP1_SCK__SSP1_SCK | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* Write Protect Pin */ + MX23_PAD_PWM4__GPIO_1_30 | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* Slot Power Enable */ + MX23_PAD_PWM3__GPIO_1_29 | + (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* LCD */ + MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX23_PAD_GPMI_D08__LCD_D18 | MUX_CONFIG_LCD, + MX23_PAD_GPMI_D09__LCD_D19 | MUX_CONFIG_LCD, + MX23_PAD_GPMI_D10__LCD_D20 | MUX_CONFIG_LCD, + MX23_PAD_GPMI_D11__LCD_D21 | MUX_CONFIG_LCD, + MX23_PAD_GPMI_D12__LCD_D22 | MUX_CONFIG_LCD, + MX23_PAD_GPMI_D13__LCD_D23 | MUX_CONFIG_LCD, + MX23_PAD_LCD_DOTCK__LCD_DOTCK | MUX_CONFIG_LCD, + MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, + MX23_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD, + MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, + MX23_PAD_LCD_RESET__GPIO_1_18 | MUX_CONFIG_LCD, /* LCD power */ + MX23_PAD_PWM2__GPIO_1_28 | MUX_CONFIG_LCD, /* LCD contrast */ +}; + +#define HW_DRAM_CTL14 (0x38 >> 2) +#define CS_MAP 0x3 +#define INTAREF 0x2 +#define HW_DRAM_CTL14_CONFIG (INTAREF << 8 | CS_MAP) + +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG; +} + +void board_init_ll(const uint32_t arg, const uint32_t *resptr) +{ + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); +} diff --git a/board/nxp/mx28evk/Kconfig b/board/nxp/mx28evk/Kconfig new file mode 100644 index 00000000000..1643196af86 --- /dev/null +++ b/board/nxp/mx28evk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX28EVK + +config SYS_BOARD + default "mx28evk" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "mx28evk" + +endif diff --git a/board/nxp/mx28evk/MAINTAINERS b/board/nxp/mx28evk/MAINTAINERS new file mode 100644 index 00000000000..4e6441a8bf5 --- /dev/null +++ b/board/nxp/mx28evk/MAINTAINERS @@ -0,0 +1,7 @@ +MX28EVK BOARD +M: Fabio Estevam +S: Maintained +F: board/nxp/mx28evk/ +F: arch/arm/dts/imx28-evk.dts +F: include/configs/mx28evk.h +F: configs/mx28evk_defconfig diff --git a/board/nxp/mx28evk/Makefile b/board/nxp/mx28evk/Makefile new file mode 100644 index 00000000000..1fd2a439f7a --- /dev/null +++ b/board/nxp/mx28evk/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +ifndef CONFIG_XPL_BUILD +obj-y := mx28evk.o +else +obj-y := iomux.o +endif diff --git a/board/nxp/mx28evk/README b/board/nxp/mx28evk/README new file mode 100644 index 00000000000..dfe83b7a7a7 --- /dev/null +++ b/board/nxp/mx28evk/README @@ -0,0 +1,62 @@ +FREESCALE MX28EVK +================== + +Supported hardware: MX28EVK rev C and D are supported in U-Boot. + +Files of the MX28EVK port +-------------------------- + +arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28 +arch/arm/include/asm/arch-mxs/ - Header files for the Freescale i.MX28 +board/nxp/mx28evk/ - MX28EVK board specific files +include/configs/mx28evk.h - MX28EVK configuration file + +Jumper configuration +--------------------- + +To boot MX28EVK from an SD card, set the boot mode DIP switches as: + + * Boot Mode Select: 1 0 0 1 (Boot from SD card Slot 0 - U42) + * JTAG PSWITCH RESET: To the right (reset disabled) + * Battery Source: Down + * Wall 5V: Up + * VDD 5V: To the left (off) + * Hold Button: Down (off) + +To boot MX28EVK from SPI NOR flash, set the boot mode DIP switches as: + + * Boot Mode Select: 0 0 1 0 (Boot from SSP2) + * JTAG PSWITCH RESET: To the right (reset disabled) + * Battery Source: Down + * Wall 5V: Up + * VDD 5V: To the left (off) + * Hold Button: Down (off) + +Environment Storage +------------------- + +There are three targets for mx28evk: + +"make mx28evk_config" - store environment variables into MMC + +or + +"make mx28evk_nand_config" - store environment variables into NAND flash + +or + +"make mx28evk_spi_config" - store environment variables into SPI NOR flash + +Choose the target accordingly. + +Note: The mx28evk board does not come with a NAND flash populated from the +factory. It comes with an empty slot (U23), which allows the insertion of a +48-pin TSOP flash device. + +mx28evk does not come with SPI NOR flash populated from the factory either. +It is possible to solder a SOIC memory on U49 or use a DIP8 on J89. +To get SPI communication to work R320, R321,R322 and C178 need to be populated. +Look in the schematics for the proper component values. + +Follow the instructions from doc/imx/common/mxs.txt to generate a bootable +SD card or to generate a binary to be flashed into SPI NOR. diff --git a/board/nxp/mx28evk/iomux.c b/board/nxp/mx28evk/iomux.c new file mode 100644 index 00000000000..b84b045bd1f --- /dev/null +++ b/board/nxp/mx28evk/iomux.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Freescale MX28EVK IOMUX setup + * + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ + +#include +#include +#include +#include +#include + +#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) + +const iomux_cfg_t iomux_setup[] = { + /* DUART */ + MX28_PAD_PWM0__DUART_RX, + MX28_PAD_PWM1__DUART_TX, + + /* MMC0 */ + MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_SSP0_SCK__SSP0_SCK | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* write protect */ + MX28_PAD_SSP1_SCK__GPIO_2_12, + /* MMC0 slot power enable */ + MX28_PAD_PWM3__GPIO_3_28 | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + +#ifdef CONFIG_NAND_MXS + /* GPMI NAND */ + MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDN__GPMI_RDN | + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), + MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, +#endif + + /* FEC0 */ + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, + /* FEC0 Enable */ + MX28_PAD_SSP1_DATA3__GPIO_2_15 | + (MXS_PAD_12MA | MXS_PAD_3V3), + /* FEC0 Reset */ + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + + /* FEC1 */ + MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, + + /* EMI */ + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, + + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + + /* SPI2 (for SPI flash) */ + MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_SS0__SSP2_D3 | + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), + /* I2C */ + MX28_PAD_I2C0_SCL__I2C0_SCL, + MX28_PAD_I2C0_SDA__I2C0_SDA, + + /* LCD */ + MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD, + MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD, + MX28_PAD_LCD_CS__LCD_ENABLE | MUX_CONFIG_LCD, + MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD, /* LCD power */ + MX28_PAD_PWM2__GPIO_3_18 | MUX_CONFIG_LCD, /* LCD contrast */ +}; + +#define HW_DRAM_CTL29 (0x74 >> 2) +#define CS_MAP 0xf +#define COLUMN_SIZE 0x2 +#define ADDR_PINS 0x1 +#define APREBIT 0xa + +#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \ + ADDR_PINS << 8 | APREBIT) + +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG; +} + +void board_init_ll(const uint32_t arg, const uint32_t *resptr) +{ + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); +} diff --git a/board/nxp/mx28evk/mx28evk.c b/board/nxp/mx28evk/mx28evk.c new file mode 100644 index 00000000000..ada572912da --- /dev/null +++ b/board/nxp/mx28evk/mx28evk.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Freescale MX28EVK board + * + * (C) Copyright 2011 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + * + * Based on m28evk.c: + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ +int board_early_init_f(void) +{ + /* IO0 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK0, 480000); + /* IO1 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK1, 480000); + + /* SSP0 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); + /* SSP2 clock at 160MHz */ + mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); + +#ifdef CONFIG_CMD_USB + mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); + mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 | + MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL); + gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1); +#endif + + /* Power on LCD */ + gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 1); + + /* Set contrast to maximum */ + gpio_direction_output(MX28_PAD_PWM2__GPIO_3_18, 1); + + return 0; +} + +int dram_init(void) +{ + return mxs_dram_init(); +} + +int board_init(void) +{ + /* Adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} diff --git a/board/nxp/mx51evk/Kconfig b/board/nxp/mx51evk/Kconfig new file mode 100644 index 00000000000..58f22cf77b0 --- /dev/null +++ b/board/nxp/mx51evk/Kconfig @@ -0,0 +1,18 @@ +if TARGET_MX51EVK + +config SYS_BOARD + default "mx51evk" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "mx51evk" + +config IMX_CONFIG + default "board/nxp/mx51evk/imximage.cfg" + +endif diff --git a/board/nxp/mx51evk/MAINTAINERS b/board/nxp/mx51evk/MAINTAINERS new file mode 100644 index 00000000000..1b44fc419dd --- /dev/null +++ b/board/nxp/mx51evk/MAINTAINERS @@ -0,0 +1,6 @@ +MX51EVK BOARD +M: Fabio Estevam +S: Maintained +F: board/nxp/mx51evk/ +F: include/configs/mx51evk.h +F: configs/mx51evk_defconfig diff --git a/board/nxp/mx51evk/Makefile b/board/nxp/mx51evk/Makefile new file mode 100644 index 00000000000..808e35015e8 --- /dev/null +++ b/board/nxp/mx51evk/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2007, Guennadi Liakhovetski +# +# (C) Copyright 2009 Freescale Semiconductor, Inc. + +obj-y += mx51evk.o diff --git a/board/nxp/mx51evk/imximage.cfg b/board/nxp/mx51evk/imximage.cfg new file mode 100644 index 00000000000..ff2ec4aa273 --- /dev/null +++ b/board/nxp/mx51evk/imximage.cfg @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C Copyright 2009 + * Stefano Babic DENX Software Engineering sbabic@denx.de. + * + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM spi + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Setting IOMUXC */ +DATA 4 0x73FA88a0 0x200 +DATA 4 0x73FA850c 0x20c5 +DATA 4 0x73FA8510 0x20c5 +DATA 4 0x73FA883c 0x2 +DATA 4 0x73FA8848 0x2 +DATA 4 0x73FA84b8 0xe7 +DATA 4 0x73FA84bc 0x45 +DATA 4 0x73FA84c0 0x45 +DATA 4 0x73FA84c4 0x45 +DATA 4 0x73FA84c8 0x45 +DATA 4 0x73FA8820 0x0 +DATA 4 0x73FA84a4 0x3 +DATA 4 0x73FA84a8 0x3 +DATA 4 0x73FA84ac 0xe3 +DATA 4 0x73FA84b0 0xe3 +DATA 4 0x73FA84b4 0xe3 +DATA 4 0x73FA84cc 0xe3 +DATA 4 0x73FA84d0 0xe2 + +DATA 4 0x73FA882c 0x6 +DATA 4 0x73FA88a4 0x6 +DATA 4 0x73FA88ac 0x6 +DATA 4 0x73FA88b8 0x6 + +/* + * Setting DDR for micron + * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model + * CAS=3 BL=4 + */ +/* ESDCTL_ESDCTL0 */ +DATA 4 0x83FD9000 0x82a20000 +/* ESDCTL_ESDCTL1 */ +DATA 4 0x83FD9008 0x82a20000 +/* ESDCTL_ESDMISC */ +DATA 4 0x83FD9010 0x000ad0d0 +/* ESDCTL_ESDCFG0 */ +DATA 4 0x83FD9004 0x333574aa +/* ESDCTL_ESDCFG1 */ +DATA 4 0x83FD900C 0x333574aa + +/* Init DRAM on CS0 */ +/* ESDCTL_ESDSCR */ +DATA 4 0x83FD9014 0x04008008 +DATA 4 0x83FD9014 0x0000801a +DATA 4 0x83FD9014 0x0000801b +DATA 4 0x83FD9014 0x00448019 +DATA 4 0x83FD9014 0x07328018 +DATA 4 0x83FD9014 0x04008008 +DATA 4 0x83FD9014 0x00008010 +DATA 4 0x83FD9014 0x00008010 +DATA 4 0x83FD9014 0x06328018 +DATA 4 0x83FD9014 0x03808019 +DATA 4 0x83FD9014 0x00408019 +DATA 4 0x83FD9014 0x00008000 + +/* Init DRAM on CS1 */ +DATA 4 0x83FD9014 0x0400800c +DATA 4 0x83FD9014 0x0000801e +DATA 4 0x83FD9014 0x0000801f +DATA 4 0x83FD9014 0x0000801d +DATA 4 0x83FD9014 0x0732801c +DATA 4 0x83FD9014 0x0400800c +DATA 4 0x83FD9014 0x00008014 +DATA 4 0x83FD9014 0x00008014 +DATA 4 0x83FD9014 0x0632801c +DATA 4 0x83FD9014 0x0380801d +DATA 4 0x83FD9014 0x0040801d +DATA 4 0x83FD9014 0x00008004 + +/* Write to CTL0 */ +DATA 4 0x83FD9000 0xb2a20000 +/* Write to CTL1 */ +DATA 4 0x83FD9008 0xb2a20000 +/* ESDMISC */ +DATA 4 0x83FD9010 0x000ad6d0 +/* ESDCTL_ESDCDLYGD */ +DATA 4 0x83FD9034 0x90000000 +DATA 4 0x83FD9014 0x00000000 diff --git a/board/nxp/mx51evk/mx51evk.c b/board/nxp/mx51evk/mx51evk.c new file mode 100644 index 00000000000..69456842302 --- /dev/null +++ b/board/nxp/mx51evk/mx51evk.c @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2009 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); + return 0; +} + +#ifdef CONFIG_REVISION_TAG +u32 get_board_rev(void) +{ + u32 rev = get_cpu_rev(); + if (!gpio_get_value(IMX_GPIO_NR(1, 22))) + rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET; + return rev; +} +#endif + +#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH) + +static void setup_iomux_uart(void) +{ + static const iomux_v3_cfg_t uart_pads[] = { + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); +} + +#ifdef CONFIG_MXC_SPI +static void setup_iomux_spi(void) +{ + static const iomux_v3_cfg_t spi_pads[] = { + NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS | + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS | + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, + MX51_GPIO_PAD_CTRL), + MX51_PAD_CSPI1_SS0__ECSPI1_SS0, + NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2), + NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS | + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), + }; + + imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); +} +#endif + +static void power_init(void) +{ + unsigned int val; + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; + struct pmic *p; + int ret; + + ret = pmic_init(CFG_FSL_PMIC_BUS); + if (ret) + return; + + p = pmic_get("FSL_PMIC"); + if (!p) + return; + + /* Write needed to Power Gate 2 register */ + pmic_reg_read(p, REG_POWER_MISC, &val); + val &= ~PWGT2SPIEN; + pmic_reg_write(p, REG_POWER_MISC, val); + + /* Externally powered */ + pmic_reg_read(p, REG_CHARGE, &val); + val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB; + pmic_reg_write(p, REG_CHARGE, val); + + /* power up the system first */ + pmic_reg_write(p, REG_POWER_MISC, PWUP); + + /* Set core voltage to 1.1V */ + pmic_reg_read(p, REG_SW_0, &val); + val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; + pmic_reg_write(p, REG_SW_0, val); + + /* Setup VCC (SW2) to 1.25 */ + pmic_reg_read(p, REG_SW_1, &val); + val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; + pmic_reg_write(p, REG_SW_1, val); + + /* Setup 1V2_DIG1 (SW3) to 1.25 */ + pmic_reg_read(p, REG_SW_2, &val); + val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; + pmic_reg_write(p, REG_SW_2, val); + udelay(50); + + /* Raise the core frequency to 800MHz */ + writel(0x0, &mxc_ccm->cacrr); + + /* Set switchers in Auto in NORMAL mode & STANDBY mode */ + /* Setup the switcher mode for SW1 & SW2*/ + pmic_reg_read(p, REG_SW_4, &val); + val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | + (SWMODE_MASK << SWMODE2_SHIFT))); + val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | + (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); + pmic_reg_write(p, REG_SW_4, val); + + /* Setup the switcher mode for SW3 & SW4 */ + pmic_reg_read(p, REG_SW_5, &val); + val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) | + (SWMODE_MASK << SWMODE4_SHIFT))); + val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) | + (SWMODE_AUTO_AUTO << SWMODE4_SHIFT); + pmic_reg_write(p, REG_SW_5, val); + + /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */ + pmic_reg_read(p, REG_SETTING_0, &val); + val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); + val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6; + pmic_reg_write(p, REG_SETTING_0, val); + + /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ + pmic_reg_read(p, REG_SETTING_1, &val); + val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); + val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775; + pmic_reg_write(p, REG_SETTING_1, val); + + /* Configure VGEN3 and VCAM regulators to use external PNP */ + val = VGEN3CONFIG | VCAMCONFIG; + pmic_reg_write(p, REG_MODE_1, val); + udelay(200); + + /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ + val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | + VVIDEOEN | VAUDIOEN | VSDEN; + pmic_reg_write(p, REG_MODE_1, val); + + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14, + NO_PAD_CTRL)); + gpio_request(IMX_GPIO_NR(2, 14), "gpio2_14"); + gpio_direction_output(IMX_GPIO_NR(2, 14), 0); + + udelay(500); + + gpio_set_value(IMX_GPIO_NR(2, 14), 1); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_iomux_lcd(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_MXC_SPI + setup_iomux_spi(); + power_init(); +#endif + + return 0; +} +#endif + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int checkboard(void) +{ + puts("Board: MX51EVK\n"); + + return 0; +} diff --git a/board/nxp/mx53loco/Kconfig b/board/nxp/mx53loco/Kconfig new file mode 100644 index 00000000000..e9f56cdc76a --- /dev/null +++ b/board/nxp/mx53loco/Kconfig @@ -0,0 +1,21 @@ +if TARGET_MX53LOCO + +config DIALOG_POWER + def_bool y + +config SYS_BOARD + default "mx53loco" + +config SYS_VENDOR + default "nxp" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "mx53loco" + +config IMX_CONFIG + default "board/nxp/mx53loco/imximage.cfg" + +endif diff --git a/board/nxp/mx53loco/MAINTAINERS b/board/nxp/mx53loco/MAINTAINERS new file mode 100644 index 00000000000..dbc85045a1c --- /dev/null +++ b/board/nxp/mx53loco/MAINTAINERS @@ -0,0 +1,7 @@ +MX53LOCO BOARD +M: Fabio Estevam +M: Jason Liu +S: Maintained +F: board/nxp/mx53loco/ +F: include/configs/mx53loco.h +F: configs/mx53loco_defconfig diff --git a/board/nxp/mx53loco/Makefile b/board/nxp/mx53loco/Makefile new file mode 100644 index 00000000000..9befe426957 --- /dev/null +++ b/board/nxp/mx53loco/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# Jason Liu + +obj-y += mx53loco.o diff --git a/board/nxp/mx53loco/imximage.cfg b/board/nxp/mx53loco/imximage.cfg new file mode 100644 index 00000000000..d12801d19f2 --- /dev/null +++ b/board/nxp/mx53loco/imximage.cfg @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu + * + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x53fa8554 0x00300000 +DATA 4 0x53fa8558 0x00300040 +DATA 4 0x53fa8560 0x00300000 +DATA 4 0x53fa8564 0x00300040 +DATA 4 0x53fa8568 0x00300040 +DATA 4 0x53fa8570 0x00300000 +DATA 4 0x53fa8574 0x00300000 +DATA 4 0x53fa8578 0x00300000 +DATA 4 0x53fa857c 0x00300040 +DATA 4 0x53fa8580 0x00300040 +DATA 4 0x53fa8584 0x00300000 +DATA 4 0x53fa8588 0x00300000 +DATA 4 0x53fa8590 0x00300040 +DATA 4 0x53fa8594 0x00300000 +DATA 4 0x53fa86f0 0x00300000 +DATA 4 0x53fa86f4 0x00000000 +DATA 4 0x53fa86fc 0x00000000 +DATA 4 0x53fa8714 0x00000000 +DATA 4 0x53fa8718 0x00300000 +DATA 4 0x53fa871c 0x00300000 +DATA 4 0x53fa8720 0x00300000 +DATA 4 0x53fa8724 0x04000000 +DATA 4 0x53fa8728 0x00300000 +DATA 4 0x53fa872c 0x00300000 +DATA 4 0x63fd9088 0x35343535 +DATA 4 0x63fd9090 0x4d444c44 +DATA 4 0x63fd907c 0x01370138 +DATA 4 0x63fd9080 0x013b013c +DATA 4 0x63fd9018 0x00011740 +DATA 4 0x63fd9000 0x83190000 +DATA 4 0x63fd900c 0x9f5152e3 +DATA 4 0x63fd9010 0xb68e8a63 +DATA 4 0x63fd9014 0x01ff00db +DATA 4 0x63fd902c 0x000026d2 +DATA 4 0x63fd9030 0x009f0e21 +DATA 4 0x63fd9008 0x12273030 +DATA 4 0x63fd9004 0x0002002d +DATA 4 0x63fd901c 0x00008032 +DATA 4 0x63fd901c 0x00008033 +DATA 4 0x63fd901c 0x00028031 +DATA 4 0x63fd901c 0x052080b0 +DATA 4 0x63fd901c 0x04008040 +DATA 4 0x63fd9000 0xc3190000 +DATA 4 0x63fd901c 0x0000803a +DATA 4 0x63fd901c 0x0000803b +DATA 4 0x63fd901c 0x00028039 +DATA 4 0x63fd901c 0x05208138 +DATA 4 0x63fd901c 0x04008048 +DATA 4 0x63fd9020 0x00005800 +DATA 4 0x63fd9040 0x05380003 +DATA 4 0x63fd9058 0x00022227 +DATA 4 0x63fd901c 0x00000000 diff --git a/board/nxp/mx53loco/mx53loco.c b/board/nxp/mx53loco/mx53loco.c new file mode 100644 index 00000000000..2d8f5da9906 --- /dev/null +++ b/board/nxp/mx53loco/mx53loco.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24) + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_REVISION_TAG +u32 get_board_rev(void) +{ + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + struct fuse_bank *bank = &iim->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + struct udevice *bus; + struct udevice *dev; + + int rev = readl(&fuse->gp[6]); + + ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); + if (ret) + return ret; + + if (!dm_i2c_probe(bus, CFG_SYS_DIALOG_PMIC_I2C_ADDR, 0, &dev)) + rev = 0; + + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; +} +#endif + +#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) + +static void setup_iomux_uart(void) +{ + static const iomux_v3_cfg_t uart_pads[] = { + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); +} + +static int power_init(void) +{ + unsigned int val; + int ret; + struct pmic *p; + struct udevice *bus; + struct udevice *dev; + + ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); + if (ret) + return ret; + + if (!dm_i2c_probe(bus, CFG_SYS_DIALOG_PMIC_I2C_ADDR, 0, &dev)) { + ret = pmic_dialog_init(I2C_PMIC); + if (ret) + return ret; + + p = pmic_get("DIALOG_PMIC"); + if (!p) + return -ENODEV; + + env_set("fdt_file", "imx53-qsb.dtb"); + + /* Set VDDA to 1.25V */ + val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; + ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); + if (ret) { + printf("Writing to BUCKCORE_REG failed: %d\n", ret); + return ret; + } + + pmic_reg_read(p, DA9053_SUPPLY_REG, &val); + val |= DA9052_SUPPLY_VBCOREGO; + ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val); + if (ret) { + printf("Writing to SUPPLY_REG failed: %d\n", ret); + return ret; + } + + /* Set Vcc peripheral to 1.30V */ + ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); + if (ret) { + printf("Writing to BUCKPRO_REG failed: %d\n", ret); + return ret; + } + + ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); + if (ret) { + printf("Writing to SUPPLY_REG failed: %d\n", ret); + return ret; + } + + return ret; + } + + if (!dm_i2c_probe(bus, CFG_SYS_FSL_PMIC_I2C_ADDR, 0, &dev)) { + ret = pmic_init(0); + if (ret) + return ret; + + p = pmic_get("FSL_PMIC"); + if (!p) + return -ENODEV; + + env_set("fdt_file", "imx53-qsrb.dtb"); + + /* Set VDDGP to 1.25V for 1GHz on SW1 */ + pmic_reg_read(p, REG_SW_0, &val); + val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708; + ret = pmic_reg_write(p, REG_SW_0, val); + if (ret) { + printf("Writing to REG_SW_0 failed: %d\n", ret); + return ret; + } + + /* Set VCC as 1.30V on SW2 */ + pmic_reg_read(p, REG_SW_1, &val); + val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708; + ret = pmic_reg_write(p, REG_SW_1, val); + if (ret) { + printf("Writing to REG_SW_1 failed: %d\n", ret); + return ret; + } + + /* Set global reset timer to 4s */ + pmic_reg_read(p, REG_POWER_CTL2, &val); + val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708; + ret = pmic_reg_write(p, REG_POWER_CTL2, val); + if (ret) { + printf("Writing to REG_POWER_CTL2 failed: %d\n", ret); + return ret; + } + + /* Set VUSBSEL and VUSBEN for USB PHY supply*/ + pmic_reg_read(p, REG_MODE_0, &val); + val |= (VUSBSEL_MC34708 | VUSBEN_MC34708); + ret = pmic_reg_write(p, REG_MODE_0, val); + if (ret) { + printf("Writing to REG_MODE_0 failed: %d\n", ret); + return ret; + } + + /* Set SWBST to 5V in auto mode */ + val = SWBST_AUTO; + ret = pmic_reg_write(p, SWBST_CTRL, val); + if (ret) { + printf("Writing to SWBST_CTRL failed: %d\n", ret); + return ret; + } + + return ret; + } + + return -1; +} + +static void clock_1GHz(void) +{ + int ret; + u32 ref_clk = MXC_HCLK; + /* + * After increasing voltage to 1.25V, we can switch + * CPU clock to 1GHz and DDR to 400MHz safely + */ + ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); + if (ret) + printf("CPU: Switch CPU clock to 1GHZ failed\n"); + + ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); + ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); + if (ret) + printf("CPU: Switch DDR clock to 400MHz failed\n"); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_iomux_lcd(); + + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + mxc_set_sata_internal_clock(); + + return 0; +} + +int board_late_init(void) +{ + if (!power_init()) + clock_1GHz(); + + return 0; +} + +int checkboard(void) +{ + puts("Board: MX53 LOCO\n"); + + return 0; +} diff --git a/board/nxp/mx6memcal/Kconfig b/board/nxp/mx6memcal/Kconfig new file mode 100644 index 00000000000..a6c39d5e4d1 --- /dev/null +++ b/board/nxp/mx6memcal/Kconfig @@ -0,0 +1,230 @@ +if TARGET_MX6MEMCAL + +config SYS_BOARD + default "mx6memcal" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "mx6memcal" + +menu "mx6memcal specifics" +choice + prompt "Serial console" + help + Either UART1 or UART2 will be used as the console for + displaying the calibration values or errors. + +config SERIAL_CONSOLE_UART1 + bool "UART1" + help + Select this if your board uses UART1 for its' console. + +config SERIAL_CONSOLE_UART2 + bool "UART2" + help + Select this if your board uses UART2 for its' console. + +endchoice + +choice + prompt "UART pads" + help + Select the RX and TX pads used for your serial console. + The choices below reflect the most commonly used options + for your UART. + + config UART2_EIM_D26_27 + bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)" + depends on SERIAL_CONSOLE_UART2 + help + Choose this configuration if you're using pads + EIM_D26 and D27 for a console on UART2. + This is typical for designs that are based on the + NXP SABRELite. + + config UART1_CSI0_DAT10_11 + bool "UART1 on CSI0_DAT10/11 (Wand, SabreSD)" + depends on SERIAL_CONSOLE_UART1 + help + Choose this configuration if you're using pads + CSI0_DAT10 and DAT11 for a console on UART1 as + is done on the i.MX6 Wand board and i.MX6 SabreSD. + + config UART1_UART1 + bool "UART1 on UART1 (i.MX6SL EVK, WaRP)" + depends on SERIAL_CONSOLE_UART1 + help + Choose this configuration if you're using pads + UART1_TXD/RXD for a console on UART1 as is done + on most i.MX6SL designs. + +endchoice + +config IMXIMAGE_OUTPUT + bool "Include output for imximage .cfg files" + default y + help + Say "Y" if you want output formatted for use in non-SPL + (DCD-style) configuration files. + +config DDRWIDTH + int "DDR bus width" + default 64 + help + Select either 32 or 64 to reflect the DDR bus width. + +config DDRCS + int "DDR chip selects" + default 2 + range 1 2 + help + Select the number of chip selects used in your board design + +choice + prompt "Memory type" + help + Select the type of DDR (DDR3 or LPDDR2) used on your design + +config DDR3 + bool "DDR3" + help + Select this if your board design uses DDR3. + +config LPDDR2 + bool "LPDDR2" + help + Select this if your board design uses LPDDR2. + +endchoice + +choice + prompt "Memory device" + +config MT41K512M16TNA + bool "Micron MT41K512M16TNA 512Mx16 (1GiB/chip)" + depends on DDR3 + +config MT41K128M16JT + bool "Micron MT41K128M16JT 128Mx16 (256 MiB/chip)" + depends on DDR3 + +config H5TQ4G63AFR + bool "Hynix H5TQ4G63AFR 256Mx16 (512 MiB/chip)" + depends on DDR3 + +config H5TQ2G63DFR + bool "Hynix H5TQ2G63DFR 128Mx16 (256 MiB/chip)" + depends on DDR3 + +config MT42L256M32D2LG + bool "Micron MT42L256M32D2LG LPDDR2 256Mx32 (1GiB/chip)" + depends on LPDDR2 + +config MT29PZZZ4D4BKESK + bool "Micron MT29PZZZ4D4BKESK multi-chip 512MiB LPDDR2/4GiB eMMC" + depends on LPDDR2 + +endchoice + +config DDR_ODT + int "DDR On-die-termination" + default 2 + range 0 7 + help + Enter the on-die termination value as an index defined for + IOMUX settings for PAD_DRAM_SDCLK0_P and others. + 0 == Disabled + 1 == 120 Ohm + 2 == 60 Ohm + 3 == 40 Ohm + 4 == 30 Ohm + 5 == 24 Ohm + 6 == 20 Ohm + 7 == 17 Ohm + Value will be applied to all clock and data lines + + +config DRAM_DRIVE_STRENGTH + int "DRAM Drive strength" + default 6 + range 0 7 + help + Enter drive strength as an index defined for IOMUX settings + for GRP_B1DS and others. + 0 == Hi Z + 6 == 40 Ohm (default) + 7 == 34 Ohm + Value will be applied to all clock and data lines + +config RTT_NOM + int "RTT_NOM" + default 1 + range 1 2 + help + Enter the RTT_NOM selector + 1 == RZQ/4 (60ohm) + 2 == RZQ/2 (120ohm) + +config RTT_WR + int "RTT_WR" + default 1 + range 0 2 + help + Enter the RTT_WR selector for MR2 + 0 == Dynamic ODT disabled + 1 == RZQ/4 (60ohm) + 2 == RZQ/2 (120ohm) + +config RALAT + int "Read additional latency" + default 5 + range 0 7 + help + Enter a latency in number of cycles. This will be added to + CAS and internal delays for which the MMDC will retrieve the + read data from the internal FIFO. + This is used to compensate for board/chip delays. + +config WALAT + int "Write additional latency" + default 0 + range 0 7 + help + Enter a latency in number of cycles. This will be added to + CAS and internal delays for which the MMDC will retrieve the + read data from the internal FIFO + This is used to compensate for board/chip delays. + +config REFSEL + int "Refresh period" + range 0 3 + default 1 + help + Select the DDR refresh period. + See the description of bitfield REF_SEL in the reference manual + for details. + 0 == disabled + 1 == 32 kHz + 2 == 64 kHz + 3 == fast counter + +config REFR + int "Number of refreshes" + range 0 7 + default 7 + help + This selects the number of refreshes (-1) during each period. + i.e.: + 0 == 1 refresh (tRFC) + 7 == 8 refreshes (tRFC*8) + See the description of MDREF[REFR] in the reference manual for + details. + +endmenu + +config IMX_CONFIG + default "arch/arm/mach-imx/spl_sd.cfg" + +endif diff --git a/board/nxp/mx6memcal/MAINTAINERS b/board/nxp/mx6memcal/MAINTAINERS new file mode 100644 index 00000000000..a5fbe62bb39 --- /dev/null +++ b/board/nxp/mx6memcal/MAINTAINERS @@ -0,0 +1,7 @@ +MX6MEMCAL BOARD +M: Eric Nelson +S: Maintained +F: board/nxp/mx6memcal/ +F: include/configs/mx6memcal.h +F: configs/mx6memcal_defconfig + diff --git a/board/nxp/mx6memcal/Makefile b/board/nxp/mx6memcal/Makefile new file mode 100644 index 00000000000..b4088b9f2ec --- /dev/null +++ b/board/nxp/mx6memcal/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2007, Guennadi Liakhovetski +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. + +ifdef CONFIG_XPL_BUILD +obj-y := spl.o +else +obj-y := mx6memcal.o +endif diff --git a/board/nxp/mx6memcal/README b/board/nxp/mx6memcal/README new file mode 100644 index 00000000000..9fe2fe2d043 --- /dev/null +++ b/board/nxp/mx6memcal/README @@ -0,0 +1,49 @@ +mx6memcal - a tool for calibrating DDR on i.MX6 boards. + +The mx6memcal board isn't a real board, but a tool for use in bring-up of +new i.MX6 board designs. + +It provides a similar function to the tool from NXP([1]) with a number +of advantages: + +1. It's open-source, so it's easier to change if needed. + Typical reasons for needing to change include the use of alternate + UARTs and PMIC initialization. +2. It produces an image that's directly loadable with imx_usb [2] or + SB_LOADER.exe [3]. + The NXP tool requires either a cumbersome JTAG connection that + makes running the DDR very slow or a working U-Boot image that + suffers from a chicken-and-egg problem (i.e. where do you get the + DDR parameters for U-Boot?). +3. It doesn't prompt for parameters, so it's much faster to gather + data from multiple boards. +4. Parameters to the calibration process can be chosen through + 'make menuconfig'. + +When booted, the mx6memcal board will run the DDR calibration +routines and display the result in a form suitable for cut and +paste into struct mx6_mmdc_calibration. It can also optionally +produce output in a form usable in a DCD-style .cfg file. + +Selections in Kconfig allow most system design settings to be chosen: + +1. The UART number and pad configuration for the UART. Options + include support for the most frequent reference designs on + i.MX6DQ/SDL (SABRE Lite and SABRESD designs). +2. The memory bus width (64 and 32-bit) +3. The number of chip-selects in use +4. The type of DDR (DDR3 or LPDDR2). Note that LPDDR2 support + is incomplete as of this writing. +5. The type of DDR chips in use. This selection allows re-use of common + parts and four DDR3 and two LPDDR2 parts are currently defined +6. The On-die termination value for the DRAM lines +7. The DRAM drive strength +8. The RTT_NOM and RTT_WR termination settings +9. RALAT/WALAT latency values + +References: +[1] - NXP DDR Stress Test Tool - https://community.nxp.com/docs/DOC-105652 +[2] - Boundary Devices imx_usb_loader + https://github.com/boundarydevices/imx_usb_loader +[3] - Use of SB_Loader.exe + https://boundarydevices.com/windows-users-and-unbricking diff --git a/board/nxp/mx6memcal/mx6memcal.c b/board/nxp/mx6memcal/mx6memcal.c new file mode 100644 index 00000000000..a58ab93f27d --- /dev/null +++ b/board/nxp/mx6memcal/mx6memcal.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * mx6memcal board support - provides a minimal, UART-only + * U-Boot that's capable of running a memory test. + * + * Copyright (C) 2016 Nelson Integration, LLC + * Author: Eric Nelson + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: mx6memcal\n"); + return 0; +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} diff --git a/board/nxp/mx6memcal/spl.c b/board/nxp/mx6memcal/spl.c new file mode 100644 index 00000000000..bc9c4259f07 --- /dev/null +++ b/board/nxp/mx6memcal/spl.c @@ -0,0 +1,457 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Nelson Integration, LLC + * Author: Eric Nelson + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart_pads[] = { +#ifdef CONFIG_UART2_EIM_D26_27 + IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +#elif defined(CONFIG_UART1_CSI0_DAT10_11) + IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +#elif defined(CONFIG_UART1_SD3_DAT6_7) + IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +#elif defined(CONFIG_UART1_UART1) + MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +#else +#error select UART console pads +#endif +}; + +#ifdef CONFIG_DDR3 +#define GRP_DDRTYPE 0x000C0000 +#else +#define GRP_DDRTYPE 0x00080000 +#endif + +/* all existing designs have this disabled */ +#define DDR_PKE 0 + +/* use Kconfig for ODT and DRIVE_STRENGTH */ +#define DDR_ODT \ + (CONFIG_DDR_ODT << 8) +#define DRAM_DRIVE_STRENGTH \ + (CONFIG_DRAM_DRIVE_STRENGTH << 3) + +/* configure MX6Q/DUAL mmdc DDR io registers */ +static struct mx6dq_iomux_ddr_regs const mx6dq_ddr_ioregs = { + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ + .dram_sdclk_0 = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_sdclk_1 = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_cas = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_ras = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_reset = DDR_ODT + DRAM_DRIVE_STRENGTH, + /* SDCKE[0:1]: 100k pull-up */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + /* SDBA2: pull-up disabled */ + .dram_sdba2 = 0x00000000, + /* SDODT[0:1]: 100k pull-up, 40 ohm */ + .dram_sdodt0 = 0x00003000 + DRAM_DRIVE_STRENGTH, + .dram_sdodt1 = 0x00003000 + DRAM_DRIVE_STRENGTH, + /* SDQS[0:7]: Differential input, 40 ohm */ + .dram_sdqs0 = DRAM_DRIVE_STRENGTH, + .dram_sdqs1 = DRAM_DRIVE_STRENGTH, + .dram_sdqs2 = DRAM_DRIVE_STRENGTH, + .dram_sdqs3 = DRAM_DRIVE_STRENGTH, + .dram_sdqs4 = DRAM_DRIVE_STRENGTH, + .dram_sdqs5 = DRAM_DRIVE_STRENGTH, + .dram_sdqs6 = DRAM_DRIVE_STRENGTH, + .dram_sdqs7 = DRAM_DRIVE_STRENGTH, + + /* DQM[0:7]: Differential input, 40 ohm */ + .dram_dqm0 = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_dqm1 = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_dqm2 = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_dqm3 = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_dqm4 = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_dqm5 = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_dqm6 = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_dqm7 = DDR_ODT + DRAM_DRIVE_STRENGTH, +}; + +/* configure MX6Q/DUAL mmdc GRP io registers */ +static struct mx6dq_iomux_grp_regs const mx6dq_grp_ioregs = { + /* DDR3 */ + .grp_ddr_type = GRP_DDRTYPE, + .grp_ddrmode_ctl = DDR_ODT, + /* disable DDR pullups */ + .grp_ddrpke = DDR_PKE, + /* ADDR[00:16], SDBA[0:1]: 40 ohm */ + .grp_addds = DRAM_DRIVE_STRENGTH, + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ + .grp_ctlds = DRAM_DRIVE_STRENGTH, + /* DATA[00:63]: Differential input, 40 ohm */ + .grp_ddrmode = DDR_ODT, + .grp_b0ds = DRAM_DRIVE_STRENGTH, + .grp_b1ds = DRAM_DRIVE_STRENGTH, + .grp_b2ds = DRAM_DRIVE_STRENGTH, + .grp_b3ds = DRAM_DRIVE_STRENGTH, + .grp_b4ds = DRAM_DRIVE_STRENGTH, + .grp_b5ds = DRAM_DRIVE_STRENGTH, + .grp_b6ds = DRAM_DRIVE_STRENGTH, + .grp_b7ds = DRAM_DRIVE_STRENGTH, +}; + +static struct mx6sdl_iomux_ddr_regs const mx6sdl_ddr_ioregs = { + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ + .dram_sdclk_0 = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_sdclk_1 = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_cas = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_ras = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_reset = DDR_ODT + DRAM_DRIVE_STRENGTH, + /* SDCKE[0:1]: 100k pull-up */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + /* SDBA2: pull-up disabled */ + .dram_sdba2 = 0x00000000, + /* SDODT[0:1]: 100k pull-up, 40 ohm */ + .dram_sdodt0 = 0x00003000 + DRAM_DRIVE_STRENGTH, + .dram_sdodt1 = 0x00003000 + DRAM_DRIVE_STRENGTH, + /* SDQS[0:7]: Differential input, 40 ohm */ + .dram_sdqs0 = DRAM_DRIVE_STRENGTH, + .dram_sdqs1 = DRAM_DRIVE_STRENGTH, + .dram_sdqs2 = DRAM_DRIVE_STRENGTH, + .dram_sdqs3 = DRAM_DRIVE_STRENGTH, + .dram_sdqs4 = DRAM_DRIVE_STRENGTH, + .dram_sdqs5 = DRAM_DRIVE_STRENGTH, + .dram_sdqs6 = DRAM_DRIVE_STRENGTH, + .dram_sdqs7 = DRAM_DRIVE_STRENGTH, + + /* DQM[0:7]: Differential input, 40 ohm */ + .dram_dqm0 = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_dqm1 = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_dqm2 = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_dqm3 = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_dqm4 = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_dqm5 = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_dqm6 = DDR_ODT + DRAM_DRIVE_STRENGTH, + .dram_dqm7 = DDR_ODT + DRAM_DRIVE_STRENGTH, +}; + +/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ +static struct mx6sdl_iomux_grp_regs const mx6sdl_grp_ioregs = { + /* DDR3 */ + .grp_ddr_type = GRP_DDRTYPE, + /* SDQS[0:7]: Differential input, 40 ohm */ + .grp_ddrmode_ctl = DDR_ODT, + /* disable DDR pullups */ + .grp_ddrpke = DDR_PKE, + /* ADDR[00:16], SDBA[0:1]: 40 ohm */ + .grp_addds = DRAM_DRIVE_STRENGTH, + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ + .grp_ctlds = DRAM_DRIVE_STRENGTH, + /* DATA[00:63]: Differential input, 40 ohm */ + .grp_ddrmode = DDR_ODT, + .grp_b0ds = DRAM_DRIVE_STRENGTH, + .grp_b1ds = DRAM_DRIVE_STRENGTH, + .grp_b2ds = DRAM_DRIVE_STRENGTH, + .grp_b3ds = DRAM_DRIVE_STRENGTH, + .grp_b4ds = DRAM_DRIVE_STRENGTH, + .grp_b5ds = DRAM_DRIVE_STRENGTH, + .grp_b6ds = DRAM_DRIVE_STRENGTH, + .grp_b7ds = DRAM_DRIVE_STRENGTH, +}; + +const struct mx6sl_iomux_ddr_regs mx6sl_ddr_ioregs = { + .dram_sdqs0 = DRAM_DRIVE_STRENGTH, + .dram_sdqs1 = DRAM_DRIVE_STRENGTH, + .dram_sdqs2 = DRAM_DRIVE_STRENGTH, + .dram_sdqs3 = DRAM_DRIVE_STRENGTH, + .dram_dqm0 = DRAM_DRIVE_STRENGTH, + .dram_dqm1 = DRAM_DRIVE_STRENGTH, + .dram_dqm2 = DRAM_DRIVE_STRENGTH, + .dram_dqm3 = DRAM_DRIVE_STRENGTH, + .dram_cas = DRAM_DRIVE_STRENGTH, + .dram_ras = DRAM_DRIVE_STRENGTH, + .dram_sdclk_0 = DRAM_DRIVE_STRENGTH, + .dram_reset = DRAM_DRIVE_STRENGTH, + .dram_sdba2 = 0x00020000, + .dram_odt0 = 0x00030000 + DRAM_DRIVE_STRENGTH, + .dram_odt1 = 0x00030000 + DRAM_DRIVE_STRENGTH, +}; + +const struct mx6sl_iomux_grp_regs mx6sl_grp_ioregs = { + .grp_b0ds = DRAM_DRIVE_STRENGTH, + .grp_b1ds = DRAM_DRIVE_STRENGTH, + .grp_b2ds = DRAM_DRIVE_STRENGTH, + .grp_b3ds = DRAM_DRIVE_STRENGTH, + .grp_addds = DRAM_DRIVE_STRENGTH, + .grp_ctlds = DRAM_DRIVE_STRENGTH, + .grp_ddrmode_ctl = DDR_ODT, + .grp_ddrpke = DDR_PKE, + .grp_ddrmode = DDR_ODT, + .grp_ddr_type = GRP_DDRTYPE, +}; + +static struct mx6_ddr_sysinfo const sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ +#if CONFIG_DDRWIDTH == 32 + .dsize = 1, +#elif CONFIG_DDRWIDTH == 64 + .dsize = 2, +#else +#error missing CONFIG_DDRWIDTH +#endif + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + + /* # of chip selects */ + .ncs = CONFIG_DDRCS, + .cs1_mirror = 0, + .bi_on = 1, /* Bank interleaving enabled */ + .rtt_nom = CONFIG_RTT_NOM, + .rtt_wr = CONFIG_RTT_WR, + .ralat = CONFIG_RALAT, /* Read additional latency */ + .walat = CONFIG_WALAT, /* Write additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ +#ifdef CONFIG_DDR3 + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .sde_to_rst = 0x10, /* JEDEC value for LPDDR2 - 200us */ + .pd_fast_exit = 0, /* immaterial for calibration */ + .ddr_type = DDR_TYPE_DDR3, +#else + .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ + .sde_to_rst = 0, /* LPDDR2 does not need this field */ + .pd_fast_exit = 0, /* immaterial for calibration */ + .ddr_type = DDR_TYPE_LPDDR2, +#endif + .refsel = CONFIG_REFSEL, + .refr = CONFIG_REFR, +}; + +#ifdef CONFIG_MT41K512M16TNA +/* Micron MT41K512M16TNA-125 */ +static struct mx6_ddr3_cfg const ddrtype = { + .mem_speed = 1600, + .density = 8, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 1, + .trcd = 1375, + .trcmin = 5062, + .trasmin = 3750, +}; +#elif defined(CONFIG_MT41K128M16JT) +/* Micron MT41K128M16JT-125 */ +static struct mx6_ddr3_cfg const ddrtype = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; +#elif defined(CONFIG_H5TQ4G63AFR) +/* Hynix H5TQ4G63AFR */ +static struct mx6_ddr3_cfg const ddrtype = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; +#elif defined CONFIG_H5TQ2G63DFR +/* Hynix H5TQ2G63DFR */ +static struct mx6_ddr3_cfg const ddrtype = { + .mem_speed = 1333, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1350, + .trcmin = 4950, + .trasmin = 3600, +}; +#elif defined(CONFIG_MT42L256M32D2LG) +/* Micron MT42L256M32D2LG */ +static struct mx6_lpddr2_cfg ddrtype = { + .mem_speed = 800, + .density = 4, + .width = 32, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .trcd_lp = 2000, + .trppb_lp = 2000, + .trpab_lp = 2250, + .trasmin = 4200, +}; +#elif defined(CONFIG_MT29PZZZ4D4BKESK) +/* Micron MT29PZZZ4D4BKESK */ +static struct mx6_lpddr2_cfg ddrtype = { + .mem_speed = 800, + .density = 4, + .width = 32, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .trcd_lp = 2000, + .trppb_lp = 2000, + .trpab_lp = 2250, + .trasmin = 4200, +}; +#else +#error please select DDR type using menuconfig +#endif + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* FIXME: these should probably be checked, especially + * for i.MX6SL, UL, ULL + */ + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void display_calibration(struct mx6_mmdc_calibration *calib) +{ + printf(".p0_mpdgctrl0\t= 0x%08X\n", calib->p0_mpdgctrl0); + printf(".p0_mpdgctrl1\t= 0x%08X\n", calib->p0_mpdgctrl1); + printf(".p0_mprddlctl\t= 0x%08X\n", calib->p0_mprddlctl); + printf(".p0_mpwrdlctl\t= 0x%08X\n", calib->p0_mpwrdlctl); + printf(".p0_mpwldectrl0\t= 0x%08X\n", calib->p0_mpwldectrl0); + printf(".p0_mpwldectrl1\t= 0x%08X\n", calib->p0_mpwldectrl1); + if (sysinfo.dsize == 2) { + printf(".p1_mpdgctrl0\t= 0x%08X\n", calib->p1_mpdgctrl0); + printf(".p1_mpdgctrl1\t= 0x%08X\n", calib->p1_mpdgctrl1); + printf(".p1_mprddlctl\t= 0x%08X\n", calib->p1_mprddlctl); + printf(".p1_mpwrdlctl\t= 0x%08X\n", calib->p1_mpwrdlctl); + printf(".p1_mpwldectrl0\t= 0x%08X\n", calib->p1_mpwldectrl0); + printf(".p1_mpwldectrl1\t= 0x%08X\n", calib->p1_mpwldectrl1); + } +#ifdef CONFIG_IMXIMAGE_OUTPUT + printf("DATA 4 MX6_MMDC_P0_MPDGCTRL0\t= 0x%08X\n", calib->p0_mpdgctrl0); + printf("DATA 4 MX6_MMDC_P0_MPDGCTRL1\t= 0x%08X\n", calib->p0_mpdgctrl1); + printf("DATA 4 MX6_MMDC_P0_MPRDDLCTL\t= 0x%08X\n", calib->p0_mprddlctl); + printf("DATA 4 MX6_MMDC_P0_MPWRDLCTL\t= 0x%08X\n", calib->p0_mpwrdlctl); + printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL0\t= 0x%08X\n", + calib->p0_mpwldectrl0); + printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL1\t= 0x%08X\n", + calib->p0_mpwldectrl1); + if (sysinfo.dsize == 2) { + printf("DATA 4 MX6_MMDC_P1_MPDGCTRL0\t= 0x%08X\n", + calib->p1_mpdgctrl0); + printf("DATA 4 MX6_MMDC_P1_MPDGCTRL1\t= 0x%08X\n", + calib->p1_mpdgctrl1); + printf("DATA 4 MX6_MMDC_P1_MPRDDLCTL\t= 0x%08X\n", + calib->p1_mprddlctl); + printf("DATA 4 MX6_MMDC_P1_MPWRDLCTL\t= 0x%08X\n", + calib->p1_mpwrdlctl); + printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL0\t= 0x%08X\n", + calib->p1_mpwldectrl0); + printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL1\t= 0x%08X\n", + calib->p1_mpwldectrl1); + } +#endif +} + +/* + * called from C runtime startup code (arch/arm/lib/crt0.S:_main) + * - we have a stack and a place to store GD, both in SRAM + * - no variable global data is available + */ +void board_init_f(ulong dummy) +{ + int errs; + struct mx6_mmdc_calibration calibration = {0}; + + memset((void *)gd, 0, sizeof(struct global_data)); + + /* write leveling calibration defaults */ + calibration.p0_mpwrdlctl = 0x40404040; + calibration.p1_mpwrdlctl = 0x40404040; + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + + SETUP_IOMUX_PADS(uart_pads); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + if (sysinfo.dsize != 1) { + if (is_cpu_type(MXC_CPU_MX6SX) || + is_cpu_type(MXC_CPU_MX6UL) || + is_cpu_type(MXC_CPU_MX6ULL) || + is_cpu_type(MXC_CPU_MX6SL)) { + printf("cpu type 0x%x doesn't support 64-bit bus\n", + get_cpu_type()); + reset_cpu(); + } + } +#ifdef CONFIG_MX6SL + mx6sl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sl_ddr_ioregs, + &mx6sl_grp_ioregs); +#else + if (is_cpu_type(MXC_CPU_MX6Q)) { + mx6dq_dram_iocfg(CONFIG_DDRWIDTH, &mx6dq_ddr_ioregs, + &mx6dq_grp_ioregs); + } else { + mx6sdl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sdl_ddr_ioregs, + &mx6sdl_grp_ioregs); + } +#endif + mx6_dram_cfg(&sysinfo, &calibration, &ddrtype); + + errs = mmdc_do_write_level_calibration(&sysinfo); + if (errs) { + printf("error %d from write level calibration\n", errs); + } else { + errs = mmdc_do_dqs_calibration(&sysinfo); + if (errs) { + printf("error %d from dqs calibration\n", errs); + } else { + printf("completed successfully\n"); + mmdc_read_calibration(&sysinfo, &calibration); + display_calibration(&calibration); + } + } +} diff --git a/board/nxp/mx6sabreauto/Kconfig b/board/nxp/mx6sabreauto/Kconfig new file mode 100644 index 00000000000..145ed6e2958 --- /dev/null +++ b/board/nxp/mx6sabreauto/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX6SABREAUTO + +config SYS_BOARD + default "mx6sabreauto" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "mx6sabreauto" + +endif diff --git a/board/nxp/mx6sabreauto/MAINTAINERS b/board/nxp/mx6sabreauto/MAINTAINERS new file mode 100644 index 00000000000..4942e4d5bca --- /dev/null +++ b/board/nxp/mx6sabreauto/MAINTAINERS @@ -0,0 +1,7 @@ +MX6SABREAUTO BOARD +M: Fabio Estevam +M: Peng Fan +S: Maintained +F: board/nxp/mx6sabreauto/ +F: include/configs/mx6sabreauto.h +F: configs/mx6sabreauto_defconfig diff --git a/board/nxp/mx6sabreauto/Makefile b/board/nxp/mx6sabreauto/Makefile new file mode 100644 index 00000000000..7ecdb6b4ad2 --- /dev/null +++ b/board/nxp/mx6sabreauto/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2007, Guennadi Liakhovetski +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. + +obj-y := mx6sabreauto.o diff --git a/board/nxp/mx6sabreauto/mx6sabreauto.c b/board/nxp/mx6sabreauto/mx6sabreauto.c new file mode 100644 index 00000000000..8ca57e0b2ac --- /dev/null +++ b/board/nxp/mx6sabreauto/mx6sabreauto.c @@ -0,0 +1,931 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_v3_cfg_t const uart4_pads[] = { + IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const port_exp[] = { + IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +#ifdef CONFIG_MTD_NOR_FLASH +static iomux_v3_cfg_t const eimnor_pads[] = { + IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static void eimnor_cs_setup(void) +{ + struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; + + writel(0x00020181, &weim_regs->cs0gcr1); + writel(0x00000001, &weim_regs->cs0gcr2); + writel(0x0a020000, &weim_regs->cs0rcr1); + writel(0x0000c000, &weim_regs->cs0rcr2); + writel(0x0804a240, &weim_regs->cs0wcr1); + writel(0x00000120, &weim_regs->wcr); + + set_chipselect_size(CS0_128); +} + +static void eim_clk_setup(void) +{ + struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int cscmr1, ccgr6; + + /* Turn off EIM clock */ + ccgr6 = readl(&imx_ccm->CCGR6); + ccgr6 &= ~(0x3 << 10); + writel(ccgr6, &imx_ccm->CCGR6); + + /* + * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root + * and aclk_eim_slow_podf = 01 --> divide by 2 + * so that we can have EIM at the maximum clock of 132MHz + */ + cscmr1 = readl(&imx_ccm->cscmr1); + cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK | + MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK); + cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET); + writel(cscmr1, &imx_ccm->cscmr1); + + /* Turn on EIM clock */ + ccgr6 |= (0x3 << 10); + writel(ccgr6, &imx_ccm->CCGR6); +} + +static void setup_iomux_eimnor(void) +{ + SETUP_IOMUX_PADS(eimnor_pads); + + gpio_direction_output(IMX_GPIO_NR(5, 4), 0); + + eimnor_cs_setup(); +} +#endif + +static iomux_v3_cfg_t const usdhc3_pads[] = { + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart4_pads); +} + +#ifdef CONFIG_FSL_ESDHC_IMX +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC3_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + gpio_direction_input(IMX_GPIO_NR(6, 15)); + return !gpio_get_value(IMX_GPIO_NR(6, 15)); +} + +int board_mmc_init(struct bd_info *bis) +{ + SETUP_IOMUX_PADS(usdhc3_pads); + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} +#endif + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t gpmi_pads[] = { + IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)), + IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1)), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + SETUP_IOMUX_PADS(gpmi_pads); + + setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_REVISION_TAG +u32 get_board_rev(void) +{ + int rev = nxp_board_rev(); + + return (get_cpu_rev() & ~(0xF << 8)) | rev; +} +#endif + +static int ar8031_phy_fixup(struct phy_device *phydev) +{ + unsigned short val; + + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + ar8031_phy_fixup(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +#if defined(CONFIG_VIDEO_IPUV3) +static void disable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + clrbits_le32(&iomux->gpr[2], + IOMUXC_GPR2_LVDS_CH0_MODE_MASK | + IOMUXC_GPR2_LVDS_CH1_MODE_MASK); +} + +static void do_enable_hdmi(struct display_info_t const *dev) +{ + disable_lvds(dev); + imx_enable_hdmi_phy(); +} + +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = NULL, + .enable = NULL, + .mode = { + .name = "Hannstar-XGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED, +} } }; +size_t display_count = ARRAY_SIZE(displays); + +iomux_v3_cfg_t const backlight_pads[] = { + IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL)), +}; + +static void setup_iomux_backlight(void) +{ + gpio_request(IMX_GPIO_NR(2, 9), "backlight"); + gpio_direction_output(IMX_GPIO_NR(2, 9), 1); + SETUP_IOMUX_PADS(backlight_pads); +} + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + setup_iomux_backlight(); + enable_ipu_clock(); + imx_setup_hdmi(); + + /* Turn on LDB_DI0 and LDB_DI1 clocks */ + reg = readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | + MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | + (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << + MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); + + reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW | + IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | + IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | + IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | + IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 | + IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | + IOMUXC_GPR3_HDMI_MUX_CTL_MASK); + reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) | + (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_MTD_NOR_FLASH + eim_clk_setup(); +#endif + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* I2C 3 Steer */ + gpio_request(IMX_GPIO_NR(5, 4), "steer logic"); + gpio_direction_output(IMX_GPIO_NR(5, 4), 1); + + gpio_request(IMX_GPIO_NR(1, 15), "expander en"); + gpio_direction_output(IMX_GPIO_NR(1, 15), 1); + SETUP_IOMUX_PADS(port_exp); + +#ifdef CONFIG_VIDEO_IPUV3 + setup_display(); +#endif + +#ifdef CONFIG_MTD_NOR_FLASH + setup_iomux_eimnor(); +#endif + return 0; +} + +#ifdef CONFIG_MXC_SPI +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; +} +#endif + +int power_init_board(void) +{ + struct udevice *dev; + unsigned int value; + int ret; + + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) + return 0; + + if (ret != 0) + return ret; + + if (is_mx6dqp()) { + /* set SW2 staby volatage 0.975V*/ + value = pmic_reg_read(dev, PFUZE100_SW2STBY); + value &= ~0x3f; + value |= 0x17; + pmic_reg_write(dev, PFUZE100_SW2STBY, value); + } + + return pfuze_mode_init(dev, APS_PFM); +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "SABREAUTO"); + + if (is_mx6dqp()) + env_set("board_rev", "MX6QP"); + else if (is_mx6dq()) + env_set("board_rev", "MX6Q"); + else if (is_mx6sdl()) + env_set("board_rev", "MX6DL"); +#endif + + return 0; +} + +int checkboard(void) +{ + printf("Board: MX6Q-Sabreauto rev%c\n", nxp_board_rev_string()); + + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + /* + * Set daisy chain for otg_pin_id on 6q. + * For 6dl, this bit is reserved. + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); + break; + case 1: + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + return 0; +} +#endif + +#ifdef CONFIG_XPL_BUILD +#include +#include +#include + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + return 0; +} +#endif + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static int mx6q_dcd_table[] = { + 0x020e0798, 0x000C0000, + 0x020e0758, 0x00000000, + 0x020e0588, 0x00000030, + 0x020e0594, 0x00000030, + 0x020e056c, 0x00000030, + 0x020e0578, 0x00000030, + 0x020e074c, 0x00000030, + 0x020e057c, 0x00000030, + 0x020e058c, 0x00000000, + 0x020e059c, 0x00000030, + 0x020e05a0, 0x00000030, + 0x020e078c, 0x00000030, + 0x020e0750, 0x00020000, + 0x020e05a8, 0x00000028, + 0x020e05b0, 0x00000028, + 0x020e0524, 0x00000028, + 0x020e051c, 0x00000028, + 0x020e0518, 0x00000028, + 0x020e050c, 0x00000028, + 0x020e05b8, 0x00000028, + 0x020e05c0, 0x00000028, + 0x020e0774, 0x00020000, + 0x020e0784, 0x00000028, + 0x020e0788, 0x00000028, + 0x020e0794, 0x00000028, + 0x020e079c, 0x00000028, + 0x020e07a0, 0x00000028, + 0x020e07a4, 0x00000028, + 0x020e07a8, 0x00000028, + 0x020e0748, 0x00000028, + 0x020e05ac, 0x00000028, + 0x020e05b4, 0x00000028, + 0x020e0528, 0x00000028, + 0x020e0520, 0x00000028, + 0x020e0514, 0x00000028, + 0x020e0510, 0x00000028, + 0x020e05bc, 0x00000028, + 0x020e05c4, 0x00000028, + 0x021b0800, 0xa1390003, + 0x021b080c, 0x001F001F, + 0x021b0810, 0x001F001F, + 0x021b480c, 0x001F001F, + 0x021b4810, 0x001F001F, + 0x021b083c, 0x43260335, + 0x021b0840, 0x031A030B, + 0x021b483c, 0x4323033B, + 0x021b4840, 0x0323026F, + 0x021b0848, 0x483D4545, + 0x021b4848, 0x44433E48, + 0x021b0850, 0x41444840, + 0x021b4850, 0x4835483E, + 0x021b081c, 0x33333333, + 0x021b0820, 0x33333333, + 0x021b0824, 0x33333333, + 0x021b0828, 0x33333333, + 0x021b481c, 0x33333333, + 0x021b4820, 0x33333333, + 0x021b4824, 0x33333333, + 0x021b4828, 0x33333333, + 0x021b08b8, 0x00000800, + 0x021b48b8, 0x00000800, + 0x021b0004, 0x00020036, + 0x021b0008, 0x09444040, + 0x021b000c, 0x8A8F7955, + 0x021b0010, 0xFF328F64, + 0x021b0014, 0x01FF00DB, + 0x021b0018, 0x00001740, + 0x021b001c, 0x00008000, + 0x021b002c, 0x000026d2, + 0x021b0030, 0x008F1023, + 0x021b0040, 0x00000047, + 0x021b0000, 0x841A0000, + 0x021b001c, 0x04088032, + 0x021b001c, 0x00008033, + 0x021b001c, 0x00048031, + 0x021b001c, 0x09408030, + 0x021b001c, 0x04008040, + 0x021b0020, 0x00005800, + 0x021b0818, 0x00011117, + 0x021b4818, 0x00011117, + 0x021b0004, 0x00025576, + 0x021b0404, 0x00011006, + 0x021b001c, 0x00000000, + 0x020c4068, 0x00C03F3F, + 0x020c406c, 0x0030FC03, + 0x020c4070, 0x0FFFC000, + 0x020c4074, 0x3FF00000, + 0x020c4078, 0xFFFFF300, + 0x020c407c, 0x0F0000F3, + 0x020c4080, 0x00000FFF, + 0x020e0010, 0xF00000CF, + 0x020e0018, 0x007F007F, + 0x020e001c, 0x007F007F, +}; + +static int mx6qp_dcd_table[] = { + 0x020e0798, 0x000C0000, + 0x020e0758, 0x00000000, + 0x020e0588, 0x00000030, + 0x020e0594, 0x00000030, + 0x020e056c, 0x00000030, + 0x020e0578, 0x00000030, + 0x020e074c, 0x00000030, + 0x020e057c, 0x00000030, + 0x020e058c, 0x00000000, + 0x020e059c, 0x00000030, + 0x020e05a0, 0x00000030, + 0x020e078c, 0x00000030, + 0x020e0750, 0x00020000, + 0x020e05a8, 0x00000030, + 0x020e05b0, 0x00000030, + 0x020e0524, 0x00000030, + 0x020e051c, 0x00000030, + 0x020e0518, 0x00000030, + 0x020e050c, 0x00000030, + 0x020e05b8, 0x00000030, + 0x020e05c0, 0x00000030, + 0x020e0774, 0x00020000, + 0x020e0784, 0x00000030, + 0x020e0788, 0x00000030, + 0x020e0794, 0x00000030, + 0x020e079c, 0x00000030, + 0x020e07a0, 0x00000030, + 0x020e07a4, 0x00000030, + 0x020e07a8, 0x00000030, + 0x020e0748, 0x00000030, + 0x020e05ac, 0x00000030, + 0x020e05b4, 0x00000030, + 0x020e0528, 0x00000030, + 0x020e0520, 0x00000030, + 0x020e0514, 0x00000030, + 0x020e0510, 0x00000030, + 0x020e05bc, 0x00000030, + 0x020e05c4, 0x00000030, + 0x021b0800, 0xa1390003, + 0x021b080c, 0x001b001e, + 0x021b0810, 0x002e0029, + 0x021b480c, 0x001b002a, + 0x021b4810, 0x0019002c, + 0x021b083c, 0x43240334, + 0x021b0840, 0x0324031a, + 0x021b483c, 0x43340344, + 0x021b4840, 0x03280276, + 0x021b0848, 0x44383A3E, + 0x021b4848, 0x3C3C3846, + 0x021b0850, 0x2e303230, + 0x021b4850, 0x38283E34, + 0x021b081c, 0x33333333, + 0x021b0820, 0x33333333, + 0x021b0824, 0x33333333, + 0x021b0828, 0x33333333, + 0x021b481c, 0x33333333, + 0x021b4820, 0x33333333, + 0x021b4824, 0x33333333, + 0x021b4828, 0x33333333, + 0x021b08c0, 0x24912492, + 0x021b48c0, 0x24912492, + 0x021b08b8, 0x00000800, + 0x021b48b8, 0x00000800, + 0x021b0004, 0x00020036, + 0x021b0008, 0x09444040, + 0x021b000c, 0x898E7955, + 0x021b0010, 0xFF328F64, + 0x021b0014, 0x01FF00DB, + 0x021b0018, 0x00001740, + 0x021b001c, 0x00008000, + 0x021b002c, 0x000026d2, + 0x021b0030, 0x008E1023, + 0x021b0040, 0x00000047, + 0x021b0400, 0x14420000, + 0x021b0000, 0x841A0000, + 0x00bb0008, 0x00000004, + 0x00bb000c, 0x2891E41A, + 0x00bb0038, 0x00000564, + 0x00bb0014, 0x00000040, + 0x00bb0028, 0x00000020, + 0x00bb002c, 0x00000020, + 0x021b001c, 0x04088032, + 0x021b001c, 0x00008033, + 0x021b001c, 0x00048031, + 0x021b001c, 0x09408030, + 0x021b001c, 0x04008040, + 0x021b0020, 0x00005800, + 0x021b0818, 0x00011117, + 0x021b4818, 0x00011117, + 0x021b0004, 0x00025576, + 0x021b0404, 0x00011006, + 0x021b001c, 0x00000000, + 0x020c4068, 0x00C03F3F, + 0x020c406c, 0x0030FC03, + 0x020c4070, 0x0FFFC000, + 0x020c4074, 0x3FF00000, + 0x020c4078, 0xFFFFF300, + 0x020c407c, 0x0F0000F3, + 0x020c4080, 0x00000FFF, + 0x020e0010, 0xF00000CF, + 0x020e0018, 0x77177717, + 0x020e001c, 0x77177717, +}; + +static int mx6dl_dcd_table[] = { + 0x020e0774, 0x000C0000, + 0x020e0754, 0x00000000, + 0x020e04ac, 0x00000030, + 0x020e04b0, 0x00000030, + 0x020e0464, 0x00000030, + 0x020e0490, 0x00000030, + 0x020e074c, 0x00000030, + 0x020e0494, 0x00000030, + 0x020e04a0, 0x00000000, + 0x020e04b4, 0x00000030, + 0x020e04b8, 0x00000030, + 0x020e076c, 0x00000030, + 0x020e0750, 0x00020000, + 0x020e04bc, 0x00000028, + 0x020e04c0, 0x00000028, + 0x020e04c4, 0x00000028, + 0x020e04c8, 0x00000028, + 0x020e04cc, 0x00000028, + 0x020e04d0, 0x00000028, + 0x020e04d4, 0x00000028, + 0x020e04d8, 0x00000028, + 0x020e0760, 0x00020000, + 0x020e0764, 0x00000028, + 0x020e0770, 0x00000028, + 0x020e0778, 0x00000028, + 0x020e077c, 0x00000028, + 0x020e0780, 0x00000028, + 0x020e0784, 0x00000028, + 0x020e078c, 0x00000028, + 0x020e0748, 0x00000028, + 0x020e0470, 0x00000028, + 0x020e0474, 0x00000028, + 0x020e0478, 0x00000028, + 0x020e047c, 0x00000028, + 0x020e0480, 0x00000028, + 0x020e0484, 0x00000028, + 0x020e0488, 0x00000028, + 0x020e048c, 0x00000028, + 0x021b0800, 0xa1390003, + 0x021b080c, 0x001F001F, + 0x021b0810, 0x001F001F, + 0x021b480c, 0x001F001F, + 0x021b4810, 0x001F001F, + 0x021b083c, 0x42190217, + 0x021b0840, 0x017B017B, + 0x021b483c, 0x4176017B, + 0x021b4840, 0x015F016C, + 0x021b0848, 0x4C4C4D4C, + 0x021b4848, 0x4A4D4C48, + 0x021b0850, 0x3F3F3F40, + 0x021b4850, 0x3538382E, + 0x021b081c, 0x33333333, + 0x021b0820, 0x33333333, + 0x021b0824, 0x33333333, + 0x021b0828, 0x33333333, + 0x021b481c, 0x33333333, + 0x021b4820, 0x33333333, + 0x021b4824, 0x33333333, + 0x021b4828, 0x33333333, + 0x021b08b8, 0x00000800, + 0x021b48b8, 0x00000800, + 0x021b0004, 0x00020025, + 0x021b0008, 0x00333030, + 0x021b000c, 0x676B5313, + 0x021b0010, 0xB66E8B63, + 0x021b0014, 0x01FF00DB, + 0x021b0018, 0x00001740, + 0x021b001c, 0x00008000, + 0x021b002c, 0x000026d2, + 0x021b0030, 0x006B1023, + 0x021b0040, 0x00000047, + 0x021b0000, 0x841A0000, + 0x021b001c, 0x04008032, + 0x021b001c, 0x00008033, + 0x021b001c, 0x00048031, + 0x021b001c, 0x05208030, + 0x021b001c, 0x04008040, + 0x021b0020, 0x00005800, + 0x021b0818, 0x00011117, + 0x021b4818, 0x00011117, + 0x021b0004, 0x00025565, + 0x021b0404, 0x00011006, + 0x021b001c, 0x00000000, + 0x020c4068, 0x00C03F3F, + 0x020c406c, 0x0030FC03, + 0x020c4070, 0x0FFFC000, + 0x020c4074, 0x3FF00000, + 0x020c4078, 0xFFFFF300, + 0x020c407c, 0x0F0000C3, + 0x020c4080, 0x00000FFF, + 0x020e0010, 0xF00000CF, + 0x020e0018, 0x007F007F, + 0x020e001c, 0x007F007F, +}; + +static void ddr_init(int *table, int size) +{ + int i; + + for (i = 0; i < size / 2 ; i++) + writel(table[2 * i + 1], table[2 * i]); +} + +static void spl_dram_init(void) +{ + if (is_mx6dq()) + ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table)); + else if (is_mx6dqp()) + ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table)); + else if (is_mx6sdl()) + ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); +} + +void board_init_f(ulong dummy) +{ + /* DDR initialization */ + spl_dram_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + if (is_mx6dq()) { + if (!strcmp(name, "imx6q-sabreauto")) + return 0; + } else if (is_mx6dqp()) { + if (!strcmp(name, "imx6qp-sabreauto")) + return 0; + } else if (is_mx6dl()) { + if (!strcmp(name, "imx6dl-sabreauto")) + return 0; + } + + return -1; +} +#endif diff --git a/board/nxp/mx6sabresd/Kconfig b/board/nxp/mx6sabresd/Kconfig new file mode 100644 index 00000000000..f657401c37e --- /dev/null +++ b/board/nxp/mx6sabresd/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX6SABRESD + +config SYS_BOARD + default "mx6sabresd" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "mx6sabresd" + +endif diff --git a/board/nxp/mx6sabresd/MAINTAINERS b/board/nxp/mx6sabresd/MAINTAINERS new file mode 100644 index 00000000000..3839dee1a17 --- /dev/null +++ b/board/nxp/mx6sabresd/MAINTAINERS @@ -0,0 +1,6 @@ +MX6SABRESD BOARD +M: Fabio Estevam +S: Maintained +F: board/nxp/mx6sabresd/ +F: include/configs/mx6sabresd.h +F: configs/mx6sabresd_defconfig diff --git a/board/nxp/mx6sabresd/Makefile b/board/nxp/mx6sabresd/Makefile new file mode 100644 index 00000000000..92e1ff72a4f --- /dev/null +++ b/board/nxp/mx6sabresd/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2007, Guennadi Liakhovetski +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. + +obj-y := mx6sabresd.o diff --git a/board/nxp/mx6sabresd/mx6sabresd.c b/board/nxp/mx6sabresd/mx6sabresd.c new file mode 100644 index 00000000000..dff3a9c33bf --- /dev/null +++ b/board/nxp/mx6sabresd/mx6sabresd.c @@ -0,0 +1,868 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define DISP0_PWR_EN IMX_GPIO_NR(1, 21) + +#define KEY_VOL_UP IMX_GPIO_NR(1, 4) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */ +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */ +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const ecspi1_pads[] = { + IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const rgb_pads[] = { + IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const bl_pads[] = { + IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static void enable_backlight(void) +{ + SETUP_IOMUX_PADS(bl_pads); + gpio_request(DISP0_PWR_EN, "Display Power Enable"); + gpio_direction_output(DISP0_PWR_EN, 1); +} + +static void enable_rgb(struct display_info_t const *dev) +{ + SETUP_IOMUX_PADS(rgb_pads); + enable_backlight(); +} + +static void enable_lvds(struct display_info_t const *dev) +{ + enable_backlight(); +} + +static void setup_spi(void) +{ + SETUP_IOMUX_PADS(ecspi1_pads); +} + +iomux_v3_cfg_t const di0_pads[] = { + IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */ + IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* DISP0_HSYNC */ + IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* DISP0_VSYNC */ +}; + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +#ifdef CONFIG_FSL_ESDHC_IMX +struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR}, + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) + +int board_mmc_get_env_dev(int devno) +{ + return devno - 1; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = 1; /* eMMC/uSDHC4 is always present */ + break; + } + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned reg = readl(&psrc->sbmr1) >> 11; + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1 + * 0x2 SD2 + * 0x3 SD4 + */ + + switch (reg & 0x3) { + case 0x1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 0x2: + SETUP_IOMUX_PADS(usdhc3_pads); + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 0x3: + SETUP_IOMUX_PADS(usdhc4_pads); + usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + } + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} +#endif + +#if defined(CONFIG_VIDEO_IPUV3) +static void disable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + int reg = readl(&iomux->gpr[2]); + + reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK | + IOMUXC_GPR2_LVDS_CH1_MODE_MASK); + + writel(reg, &iomux->gpr[2]); +} + +static void do_enable_hdmi(struct display_info_t const *dev) +{ + disable_lvds(dev); + imx_enable_hdmi_phy(); +} + +struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = NULL, + .enable = enable_lvds, + .mode = { + .name = "Hannstar-XGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15384, + .left_margin = 160, + .right_margin = 24, + .upper_margin = 29, + .lower_margin = 3, + .hsync_len = 136, + .vsync_len = 6, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15384, + .left_margin = 160, + .right_margin = 24, + .upper_margin = 29, + .lower_margin = 3, + .hsync_len = 136, + .vsync_len = 6, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 0, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = NULL, + .enable = enable_rgb, + .mode = { + .name = "SEIKO-WVGA", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ + SETUP_IOMUX_PADS(di0_pads); + + enable_ipu_clock(); + imx_setup_hdmi(); + + /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ + reg = readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED + | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK + | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +#ifdef CONFIG_USB_EHCI_MX6 +static void setup_usb(void) +{ + /* + * set daisy chain for otg_pin_id on 6q. + * for 6dl, this bit is reserved + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + + return 0; +} + +int power_init_board(void) +{ + struct udevice *dev; + unsigned int reg; + int ret; + + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) + return 0; + + if (ret != 0) + return ret; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + /* Increase VGEN3 from 2.5 to 2.8V */ + reg = pmic_reg_read(dev, PFUZE100_VGEN3VOL); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_2_80V; + pmic_reg_write(dev, PFUZE100_VGEN3VOL, reg); + + /* Increase VGEN5 from 2.8 to 3V */ + reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_3_00V; + pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); + + return 0; +} + +#ifdef CONFIG_MXC_SPI +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; +} +#endif + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + /* 8 bit bus width */ + {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "SABRESD"); + + if (is_mx6dqp()) + env_set("board_rev", "MX6QP"); + else if (is_mx6dq()) + env_set("board_rev", "MX6Q"); + else if (is_mx6sdl()) + env_set("board_rev", "MX6DL"); +#endif + + return 0; +} + +#ifdef CONFIG_XPL_BUILD +#include +#include +#include + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + gpio_request(KEY_VOL_UP, "KEY Volume UP"); + gpio_direction_input(KEY_VOL_UP); + + /* Only enter in Falcon mode if KEY_VOL_UP is pressed */ + return gpio_get_value(KEY_VOL_UP); +} +#endif + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static int mx6q_dcd_table[] = { + 0x020e0798, 0x000C0000, + 0x020e0758, 0x00000000, + 0x020e0588, 0x00000030, + 0x020e0594, 0x00000030, + 0x020e056c, 0x00000030, + 0x020e0578, 0x00000030, + 0x020e074c, 0x00000030, + 0x020e057c, 0x00000030, + 0x020e058c, 0x00000000, + 0x020e059c, 0x00000030, + 0x020e05a0, 0x00000030, + 0x020e078c, 0x00000030, + 0x020e0750, 0x00020000, + 0x020e05a8, 0x00000030, + 0x020e05b0, 0x00000030, + 0x020e0524, 0x00000030, + 0x020e051c, 0x00000030, + 0x020e0518, 0x00000030, + 0x020e050c, 0x00000030, + 0x020e05b8, 0x00000030, + 0x020e05c0, 0x00000030, + 0x020e0774, 0x00020000, + 0x020e0784, 0x00000030, + 0x020e0788, 0x00000030, + 0x020e0794, 0x00000030, + 0x020e079c, 0x00000030, + 0x020e07a0, 0x00000030, + 0x020e07a4, 0x00000030, + 0x020e07a8, 0x00000030, + 0x020e0748, 0x00000030, + 0x020e05ac, 0x00000030, + 0x020e05b4, 0x00000030, + 0x020e0528, 0x00000030, + 0x020e0520, 0x00000030, + 0x020e0514, 0x00000030, + 0x020e0510, 0x00000030, + 0x020e05bc, 0x00000030, + 0x020e05c4, 0x00000030, + 0x021b0800, 0xa1390003, + 0x021b080c, 0x001F001F, + 0x021b0810, 0x001F001F, + 0x021b480c, 0x001F001F, + 0x021b4810, 0x001F001F, + 0x021b083c, 0x43270338, + 0x021b0840, 0x03200314, + 0x021b483c, 0x431A032F, + 0x021b4840, 0x03200263, + 0x021b0848, 0x4B434748, + 0x021b4848, 0x4445404C, + 0x021b0850, 0x38444542, + 0x021b4850, 0x4935493A, + 0x021b081c, 0x33333333, + 0x021b0820, 0x33333333, + 0x021b0824, 0x33333333, + 0x021b0828, 0x33333333, + 0x021b481c, 0x33333333, + 0x021b4820, 0x33333333, + 0x021b4824, 0x33333333, + 0x021b4828, 0x33333333, + 0x021b08b8, 0x00000800, + 0x021b48b8, 0x00000800, + 0x021b0004, 0x00020036, + 0x021b0008, 0x09444040, + 0x021b000c, 0x555A7975, + 0x021b0010, 0xFF538F64, + 0x021b0014, 0x01FF00DB, + 0x021b0018, 0x00001740, + 0x021b001c, 0x00008000, + 0x021b002c, 0x000026d2, + 0x021b0030, 0x005A1023, + 0x021b0040, 0x00000027, + 0x021b0000, 0x831A0000, + 0x021b001c, 0x04088032, + 0x021b001c, 0x00008033, + 0x021b001c, 0x00048031, + 0x021b001c, 0x09408030, + 0x021b001c, 0x04008040, + 0x021b0020, 0x00005800, + 0x021b0818, 0x00011117, + 0x021b4818, 0x00011117, + 0x021b0004, 0x00025576, + 0x021b0404, 0x00011006, + 0x021b001c, 0x00000000, +}; + +static int mx6qp_dcd_table[] = { + 0x020e0798, 0x000c0000, + 0x020e0758, 0x00000000, + 0x020e0588, 0x00000030, + 0x020e0594, 0x00000030, + 0x020e056c, 0x00000030, + 0x020e0578, 0x00000030, + 0x020e074c, 0x00000030, + 0x020e057c, 0x00000030, + 0x020e058c, 0x00000000, + 0x020e059c, 0x00000030, + 0x020e05a0, 0x00000030, + 0x020e078c, 0x00000030, + 0x020e0750, 0x00020000, + 0x020e05a8, 0x00000030, + 0x020e05b0, 0x00000030, + 0x020e0524, 0x00000030, + 0x020e051c, 0x00000030, + 0x020e0518, 0x00000030, + 0x020e050c, 0x00000030, + 0x020e05b8, 0x00000030, + 0x020e05c0, 0x00000030, + 0x020e0774, 0x00020000, + 0x020e0784, 0x00000030, + 0x020e0788, 0x00000030, + 0x020e0794, 0x00000030, + 0x020e079c, 0x00000030, + 0x020e07a0, 0x00000030, + 0x020e07a4, 0x00000030, + 0x020e07a8, 0x00000030, + 0x020e0748, 0x00000030, + 0x020e05ac, 0x00000030, + 0x020e05b4, 0x00000030, + 0x020e0528, 0x00000030, + 0x020e0520, 0x00000030, + 0x020e0514, 0x00000030, + 0x020e0510, 0x00000030, + 0x020e05bc, 0x00000030, + 0x020e05c4, 0x00000030, + 0x021b0800, 0xa1390003, + 0x021b080c, 0x001b001e, + 0x021b0810, 0x002e0029, + 0x021b480c, 0x001b002a, + 0x021b4810, 0x0019002c, + 0x021b083c, 0x43240334, + 0x021b0840, 0x0324031a, + 0x021b483c, 0x43340344, + 0x021b4840, 0x03280276, + 0x021b0848, 0x44383A3E, + 0x021b4848, 0x3C3C3846, + 0x021b0850, 0x2e303230, + 0x021b4850, 0x38283E34, + 0x021b081c, 0x33333333, + 0x021b0820, 0x33333333, + 0x021b0824, 0x33333333, + 0x021b0828, 0x33333333, + 0x021b481c, 0x33333333, + 0x021b4820, 0x33333333, + 0x021b4824, 0x33333333, + 0x021b4828, 0x33333333, + 0x021b08c0, 0x24912249, + 0x021b48c0, 0x24914289, + 0x021b08b8, 0x00000800, + 0x021b48b8, 0x00000800, + 0x021b0004, 0x00020036, + 0x021b0008, 0x24444040, + 0x021b000c, 0x555A7955, + 0x021b0010, 0xFF320F64, + 0x021b0014, 0x01ff00db, + 0x021b0018, 0x00001740, + 0x021b001c, 0x00008000, + 0x021b002c, 0x000026d2, + 0x021b0030, 0x005A1023, + 0x021b0040, 0x00000027, + 0x021b0400, 0x14420000, + 0x021b0000, 0x831A0000, + 0x021b0890, 0x00400C58, + 0x00bb0008, 0x00000000, + 0x00bb000c, 0x2891E41A, + 0x00bb0038, 0x00000564, + 0x00bb0014, 0x00000040, + 0x00bb0028, 0x00000020, + 0x00bb002c, 0x00000020, + 0x021b001c, 0x04088032, + 0x021b001c, 0x00008033, + 0x021b001c, 0x00048031, + 0x021b001c, 0x09408030, + 0x021b001c, 0x04008040, + 0x021b0020, 0x00005800, + 0x021b0818, 0x00011117, + 0x021b4818, 0x00011117, + 0x021b0004, 0x00025576, + 0x021b0404, 0x00011006, + 0x021b001c, 0x00000000, +}; + +static int mx6dl_dcd_table[] = { + 0x020e0774, 0x000C0000, + 0x020e0754, 0x00000000, + 0x020e04ac, 0x00000030, + 0x020e04b0, 0x00000030, + 0x020e0464, 0x00000030, + 0x020e0490, 0x00000030, + 0x020e074c, 0x00000030, + 0x020e0494, 0x00000030, + 0x020e04a0, 0x00000000, + 0x020e04b4, 0x00000030, + 0x020e04b8, 0x00000030, + 0x020e076c, 0x00000030, + 0x020e0750, 0x00020000, + 0x020e04bc, 0x00000030, + 0x020e04c0, 0x00000030, + 0x020e04c4, 0x00000030, + 0x020e04c8, 0x00000030, + 0x020e04cc, 0x00000030, + 0x020e04d0, 0x00000030, + 0x020e04d4, 0x00000030, + 0x020e04d8, 0x00000030, + 0x020e0760, 0x00020000, + 0x020e0764, 0x00000030, + 0x020e0770, 0x00000030, + 0x020e0778, 0x00000030, + 0x020e077c, 0x00000030, + 0x020e0780, 0x00000030, + 0x020e0784, 0x00000030, + 0x020e078c, 0x00000030, + 0x020e0748, 0x00000030, + 0x020e0470, 0x00000030, + 0x020e0474, 0x00000030, + 0x020e0478, 0x00000030, + 0x020e047c, 0x00000030, + 0x020e0480, 0x00000030, + 0x020e0484, 0x00000030, + 0x020e0488, 0x00000030, + 0x020e048c, 0x00000030, + 0x021b0800, 0xa1390003, + 0x021b080c, 0x001F001F, + 0x021b0810, 0x001F001F, + 0x021b480c, 0x001F001F, + 0x021b4810, 0x001F001F, + 0x021b083c, 0x4220021F, + 0x021b0840, 0x0207017E, + 0x021b483c, 0x4201020C, + 0x021b4840, 0x01660172, + 0x021b0848, 0x4A4D4E4D, + 0x021b4848, 0x4A4F5049, + 0x021b0850, 0x3F3C3D31, + 0x021b4850, 0x3238372B, + 0x021b081c, 0x33333333, + 0x021b0820, 0x33333333, + 0x021b0824, 0x33333333, + 0x021b0828, 0x33333333, + 0x021b481c, 0x33333333, + 0x021b4820, 0x33333333, + 0x021b4824, 0x33333333, + 0x021b4828, 0x33333333, + 0x021b08b8, 0x00000800, + 0x021b48b8, 0x00000800, + 0x021b0004, 0x0002002D, + 0x021b0008, 0x00333030, + 0x021b000c, 0x3F435313, + 0x021b0010, 0xB66E8B63, + 0x021b0014, 0x01FF00DB, + 0x021b0018, 0x00001740, + 0x021b001c, 0x00008000, + 0x021b002c, 0x000026d2, + 0x021b0030, 0x00431023, + 0x021b0040, 0x00000027, + 0x021b0000, 0x831A0000, + 0x021b001c, 0x04008032, + 0x021b001c, 0x00008033, + 0x021b001c, 0x00048031, + 0x021b001c, 0x05208030, + 0x021b001c, 0x04008040, + 0x021b0020, 0x00005800, + 0x021b0818, 0x00011117, + 0x021b4818, 0x00011117, + 0x021b0004, 0x0002556D, + 0x021b0404, 0x00011006, + 0x021b001c, 0x00000000, +}; + +static void ddr_init(int *table, int size) +{ + int i; + + for (i = 0; i < size / 2 ; i++) + writel(table[2 * i + 1], table[2 * i]); +} + +static void spl_dram_init(void) +{ + if (is_mx6dq()) + ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table)); + else if (is_mx6dqp()) + ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table)); + else if (is_mx6sdl()) + ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); +} + +void board_init_f(ulong dummy) +{ + /* DDR initialization */ + spl_dram_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + if (is_mx6dq()) { + if (!strcmp(name, "imx6q-sabresd")) + return 0; + } else if (is_mx6dqp()) { + if (!strcmp(name, "imx6qp-sabresd")) + return 0; + } else if (is_mx6dl()) { + if (!strcmp(name, "imx6dl-sabresd")) + return 0; + } + + return -1; +} +#endif diff --git a/board/nxp/mx6slevk/Kconfig b/board/nxp/mx6slevk/Kconfig new file mode 100644 index 00000000000..862bc8396cd --- /dev/null +++ b/board/nxp/mx6slevk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6SLEVK + +config SYS_BOARD + default "mx6slevk" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "mx6slevk" + +config IMX_CONFIG + default "board/nxp/mx6slevk/imximage.cfg" + +endif diff --git a/board/nxp/mx6slevk/MAINTAINERS b/board/nxp/mx6slevk/MAINTAINERS new file mode 100644 index 00000000000..4410358ea08 --- /dev/null +++ b/board/nxp/mx6slevk/MAINTAINERS @@ -0,0 +1,9 @@ +MX6SLEVK BOARD +M: Fabio Estevam +M: Peng Fan +S: Maintained +F: board/nxp/mx6slevk/ +F: include/configs/mx6slevk.h +F: configs/mx6slevk_defconfig +F: configs/mx6slevk_spl_defconfig +F: configs/mx6slevk_spinor_defconfig diff --git a/board/nxp/mx6slevk/Makefile b/board/nxp/mx6slevk/Makefile new file mode 100644 index 00000000000..770f7aac6b9 --- /dev/null +++ b/board/nxp/mx6slevk/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2013 Freescale Semiconductor, Inc. + +obj-y := mx6slevk.o diff --git a/board/nxp/mx6slevk/imximage.cfg b/board/nxp/mx6slevk/imximage.cfg new file mode 100644 index 00000000000..64be101d6ec --- /dev/null +++ b/board/nxp/mx6slevk/imximage.cfg @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ + +BOOT_FROM sd + +/* + * Secure boot support + */ +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020c4018 0x00260324 + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020e0344 0x00003030 +DATA 4 0x020e0348 0x00003030 +DATA 4 0x020e034c 0x00003030 +DATA 4 0x020e0350 0x00003030 +DATA 4 0x020e030c 0x00000030 +DATA 4 0x020e0310 0x00000030 +DATA 4 0x020e0314 0x00000030 +DATA 4 0x020e0318 0x00000030 +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e031c 0x00000030 +DATA 4 0x020e0338 0x00000028 +DATA 4 0x020e0320 0x00000030 +DATA 4 0x020e032c 0x00000000 +DATA 4 0x020e033c 0x00000008 +DATA 4 0x020e0340 0x00000008 +DATA 4 0x020e05c4 0x00000030 +DATA 4 0x020e05cc 0x00000030 +DATA 4 0x020e05d4 0x00000030 +DATA 4 0x020e05d8 0x00000030 +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05c8 0x00000030 +DATA 4 0x020e05b0 0x00020000 +DATA 4 0x020e05b4 0x00000000 +DATA 4 0x020e05c0 0x00020000 +DATA 4 0x020e05d0 0x00080000 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b085c 0x1b4700c7 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b0890 0x00400000 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b082c 0xf3333333 +DATA 4 0x021b0830 0xf3333333 +DATA 4 0x021b0834 0xf3333333 +DATA 4 0x021b0838 0xf3333333 +DATA 4 0x021b0848 0x4241444a +DATA 4 0x021b0850 0x3030312b +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x00000000 +DATA 4 0x021b08c0 0x24911492 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b000c 0x33374133 +DATA 4 0x021b0004 0x00020024 +DATA 4 0x021b0010 0x00100A82 +DATA 4 0x021b0014 0x00000093 +DATA 4 0x021b0018 0x00001688 +DATA 4 0x021b002c 0x0f9f26d2 +DATA 4 0x021b0030 0x009f0e10 +DATA 4 0x021b0038 0x00190778 +DATA 4 0x021b0008 0x00000000 +DATA 4 0x021b0040 0x0000004f +DATA 4 0x021b0000 0xc3110000 +DATA 4 0x021b001c 0x003f8030 +DATA 4 0x021b001c 0xff0a8030 +DATA 4 0x021b001c 0x82018030 +DATA 4 0x021b001c 0x04028030 +DATA 4 0x021b001c 0x02038030 +DATA 4 0x021b001c 0xff0a8038 +DATA 4 0x021b001c 0x82018038 +DATA 4 0x021b001c 0x04028038 +DATA 4 0x021b001c 0x02038038 +DATA 4 0x021b0800 0xa1310003 +DATA 4 0x021b0020 0x00001800 +DATA 4 0x021b0818 0x00000000 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b0004 0x00025564 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 diff --git a/board/nxp/mx6slevk/mx6slevk.c b/board/nxp/mx6slevk/mx6slevk.c new file mode 100644 index 00000000000..fb145fa6aac --- /dev/null +++ b/board/nxp/mx6slevk/mx6slevk.c @@ -0,0 +1,390 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ + PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_FAST) + +#define ETH_PHY_POWER IMX_GPIO_NR(4, 21) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#ifdef CONFIG_XPL_BUILD +static iomux_v3_cfg_t const usdhc1_pads[] = { + /* 8 bit SD */ + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /*CD pin*/ + MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /*CD pin*/ + MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /*CD pin*/ + MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +#ifdef CONFIG_DM_PMIC_PFUZE100 +int power_init_board(void) +{ + struct udevice *dev; + int ret; + u32 dev_id, rev_id, i; + u32 switch_num = 6; + u32 offset = PFUZE100_SW1CMODE; + + ret = pmic_get("pfuze100@08", &dev); + if (ret == -ENODEV) + return 0; + + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* set SW1AB staby volatage 0.975V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); + + /* set SW1C staby volatage 0.975V */ + pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); + + /* Init mode to APS_PFM */ + pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM); + + for (i = 0; i < switch_num - 1; i++) + pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM); + + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC + +static int setup_fec(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* clear gpr1[14], gpr1[18:17] to select anatop clock */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); + + return enable_fec_anatop_clock(0, ENET_50MHZ); +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + return 0; +} + +int checkboard(void) +{ + puts("Board: MX6SLEVK\n"); + + return 0; +} + +#ifdef CONFIG_XPL_BUILD +#include +#include + +#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7) +#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0) +#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22) + +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC1_BASE_ADDR}, + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR, 0, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + gpio_request(USDHC1_CD_GPIO, "cd1_gpio"); + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC2_BASE_ADDR: + gpio_request(USDHC2_CD_GPIO, "cd2_gpio"); + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + gpio_request(USDHC3_CD_GPIO, "cd3_gpio"); + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u32 val; + u32 port; + + val = readl(&src_regs->sbmr1); + + /* Boot from USDHC */ + port = (val >> 11) & 0x3; + switch (port) { + case 0: + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, + ARRAY_SIZE(usdhc1_pads)); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, + ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, + ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + } + + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_sdqs0 = 0x00003030, + .dram_sdqs1 = 0x00003030, + .dram_sdqs2 = 0x00003030, + .dram_sdqs3 = 0x00003030, + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_dqm2 = 0x00000030, + .dram_dqm3 = 0x00000030, + .dram_cas = 0x00000030, + .dram_ras = 0x00000030, + .dram_sdclk_0 = 0x00000028, + .dram_reset = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_odt0 = 0x00000008, + .dram_odt1 = 0x00000008, +}; + +const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = { + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_addds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x00080000, +}; + +const struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpdgctrl0 = 0x20000000, + .p0_mpdgctrl1 = 0x00000000, + .p0_mprddlctl = 0x4241444a, + .p0_mpwrdlctl = 0x3030312b, + .mpzqlp2ctl = 0x1b4700c7, +}; + +static struct mx6_lpddr2_cfg mem_ddr = { + .mem_speed = 800, + .density = 4, + .width = 32, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .trcd_lp = 2000, + .trppb_lp = 2000, + .trpab_lp = 2250, + .trasmin = 4200, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + + writel(0x00260324, &ccm->cbcmr); +} + +static void spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + .dsize = mem_ddr.width / 32, + .cs_density = 20, + .ncs = 2, + .cs1_mirror = 0, + .walat = 0, + .ralat = 2, + .mif3_mode = 3, + .bi_on = 1, + .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */ + .rtt_nom = 0, + .sde_to_rst = 0, /* LPDDR2 does not need this field */ + .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ + .ddr_type = DDR_TYPE_LPDDR2, + .refsel = 0, /* Refresh cycles at 64KHz */ + .refr = 3, /* 4 refresh commands per refresh cycle */ + }; + mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif diff --git a/board/nxp/mx6sllevk/Kconfig b/board/nxp/mx6sllevk/Kconfig new file mode 100644 index 00000000000..a2bfaca9c29 --- /dev/null +++ b/board/nxp/mx6sllevk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6SLLEVK + +config SYS_BOARD + default "mx6sllevk" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "mx6sllevk" + +config IMX_CONFIG + default "board/nxp/mx6sllevk/imximage.cfg" + +endif diff --git a/board/nxp/mx6sllevk/MAINTAINERS b/board/nxp/mx6sllevk/MAINTAINERS new file mode 100644 index 00000000000..a11a5a6653e --- /dev/null +++ b/board/nxp/mx6sllevk/MAINTAINERS @@ -0,0 +1,7 @@ +MX6SLLEVK BOARD +M: Peng Fan +S: Maintained +F: board/nxp/mx6sllevk/ +F: include/configs/mx6sllevk.h +F: configs/mx6sllevk_defconfig +F: configs/mx6sllevk_plugin_defconfig diff --git a/board/nxp/mx6sllevk/Makefile b/board/nxp/mx6sllevk/Makefile new file mode 100644 index 00000000000..8f724ccfc92 --- /dev/null +++ b/board/nxp/mx6sllevk/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2016 Freescale Semiconductor, Inc. + +obj-y := mx6sllevk.o diff --git a/board/nxp/mx6sllevk/imximage.cfg b/board/nxp/mx6sllevk/imximage.cfg new file mode 100644 index 00000000000..7bb91015688 --- /dev/null +++ b/board/nxp/mx6sllevk/imximage.cfg @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/nxp/mx6sllevk/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E0550 0x00080000 +DATA 4 0x020E0534 0x00000000 +DATA 4 0x020E02AC 0x00000030 +DATA 4 0x020E0548 0x00000030 +DATA 4 0x020E052C 0x00000030 +DATA 4 0x020E0530 0x00020000 +DATA 4 0x020E02B0 0x00003030 +DATA 4 0x020E02B4 0x00003030 +DATA 4 0x020E02B8 0x00003030 +DATA 4 0x020E02BC 0x00003030 +DATA 4 0x020E0540 0x00020000 +DATA 4 0x020E0544 0x00000030 +DATA 4 0x020E054C 0x00000030 +DATA 4 0x020E0554 0x00000030 +DATA 4 0x020E0558 0x00000030 +DATA 4 0x020E0294 0x00000030 +DATA 4 0x020E0298 0x00000030 +DATA 4 0x020E029C 0x00000030 +DATA 4 0x020E02A0 0x00000030 +DATA 4 0x020E02C0 0x00082030 + +DATA 4 0x021B001C 0x00008000 + +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B085c 0x084700C7 +DATA 4 0x021B0890 0x00400000 +DATA 4 0x021B0848 0x3F393B3C +DATA 4 0x021B0850 0x262C3826 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B0824 0x33333333 +DATA 4 0x021B0828 0x33333333 + +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B0834 0xf3333333 +DATA 4 0x021B0838 0xf3333333 +DATA 4 0x021B08C0 0x24922492 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B0004 0x00020052 +DATA 4 0x021B000C 0x53574333 +DATA 4 0x021B0010 0x00100B22 +DATA 4 0x021B0038 0x00170778 +DATA 4 0x021B0014 0x00C700DB +DATA 4 0x021B0018 0x00201718 +DATA 4 0x021B002C 0x0F9F26D2 +DATA 4 0x021B0030 0x009F0E10 +DATA 4 0x021B0040 0x0000005F +DATA 4 0x021B0000 0xC4190000 + +DATA 4 0x021B083C 0x20000000 + +DATA 4 0x021B001C 0x00008050 +DATA 4 0x021B001C 0x00008058 +DATA 4 0x021B001C 0x003F8030 +DATA 4 0x021B001C 0x003F8038 +DATA 4 0x021B001C 0xFF0A8030 +DATA 4 0x021B001C 0xFF0A8038 +DATA 4 0x021B001C 0x04028030 +DATA 4 0x021B001C 0x04028038 +DATA 4 0x021B001C 0x83018030 +DATA 4 0x021B001C 0x83018038 +DATA 4 0x021B001C 0x01038030 +DATA 4 0x021B001C 0x01038038 + +DATA 4 0x021B0020 0x00001800 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B0004 0x00020052 +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif diff --git a/board/nxp/mx6sllevk/mx6sllevk.c b/board/nxp/mx6sllevk/mx6sllevk.c new file mode 100644 index 00000000000..9e39e39ac90 --- /dev/null +++ b/board/nxp/mx6sllevk/mx6sllevk.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_v3_cfg_t const wdog_pads[] = { + MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_DM_PMIC_PFUZE100 +int power_init_board(void) +{ + struct udevice *dev; + int ret; + u32 dev_id, rev_id, i; + u32 switch_num = 6; + u32 offset = PFUZE100_SW1CMODE; + + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) + return 0; + + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* Init mode to APS_PFM */ + pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM); + + for (i = 0; i < switch_num - 1; i++) + pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM); + + /* set SW1AB staby volatage 0.975V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); + + /* set SW1C staby volatage 0.975V */ + pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); + + return 0; +} +#endif + +int board_early_init_f(void) +{ + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int board_late_init(void) +{ + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + return 0; +} + +int checkboard(void) +{ + puts("Board: MX6SLL EVK\n"); + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int mmc_map_to_kernel_blk(int devno) +{ + return devno; +} diff --git a/board/nxp/mx6sllevk/plugin.S b/board/nxp/mx6sllevk/plugin.S new file mode 100644 index 00000000000..dcf5e14d48a --- /dev/null +++ b/board/nxp/mx6sllevk/plugin.S @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#include + +/* DDR script */ +.macro imx6sll_evk_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x550] + ldr r1, =0x00000000 + str r1, [r0, #0x534] + ldr r1, =0x00000030 + str r1, [r0, #0x2AC] + str r1, [r0, #0x548] + str r1, [r0, #0x52C] + ldr r1, =0x00020000 + str r1, [r0, #0x530] + ldr r1, =0x00003030 + str r1, [r0, #0x2B0] + str r1, [r0, #0x2B4] + str r1, [r0, #0x2B8] + str r1, [r0, #0x2BC] + + ldr r1, =0x00020000 + str r1, [r0, #0x540] + ldr r1, =0x00000030 + str r1, [r0, #0x544] + str r1, [r0, #0x54C] + str r1, [r0, #0x554] + str r1, [r0, #0x558] + str r1, [r0, #0x294] + str r1, [r0, #0x298] + str r1, [r0, #0x29C] + str r1, [r0, #0x2A0] + + ldr r1, =0x00082030 + str r1, [r0, #0x2C0] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x084700C7 + str r1, [r0, #0x85C] + ldr r1, =0x00400000 + str r1, [r0, #0x890] + + ldr r1, =0x3F393B3C + str r1, [r0, #0x848] + ldr r1, =0x262C3826 + str r1, [r0, #0x850] + + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + str r1, [r0, #0x824] + str r1, [r0, #0x828] + + ldr r1, =0xf3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + str r1, [r0, #0x834] + str r1, [r0, #0x838] + + ldr r1, =0x24922492 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + + ldr r1, =0x00020052 + str r1, [r0, #0x004] + ldr r1, =0x53574333 + str r1, [r0, #0x00C] + ldr r1, =0x00100B22 + str r1, [r0, #0x010] + ldr r1, =0x00170778 + str r1, [r0, #0x038] + ldr r1, =0x00C700DB + str r1, [r0, #0x014] + ldr r1, =0x00201718 + str r1, [r0, #0x018] + ldr r1, =0x0F9F26D2 + str r1, [r0, #0x02C] + ldr r1, =0x009F0E10 + str r1, [r0, #0x030] + ldr r1, =0x0000005F + str r1, [r0, #0x040] + ldr r1, =0xC4190000 + str r1, [r0, #0x000] + ldr r1, =0x20000000 + str r1, [r0, #0x83C] + + ldr r1, =0x00008050 + str r1, [r0, #0x01C] + ldr r1, =0x00008058 + str r1, [r0, #0x01C] + ldr r1, =0x003F8030 + str r1, [r0, #0x01C] + ldr r1, =0x003F8038 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8038 + str r1, [r0, #0x01C] + ldr r1, =0x04028030 + str r1, [r0, #0x01C] + ldr r1, =0x04028038 + str r1, [r0, #0x01C] + ldr r1, =0x83018030 + str r1, [r0, #0x01C] + ldr r1, =0x83018038 + str r1, [r0, #0x01C] + ldr r1, =0x01038030 + str r1, [r0, #0x01C] + ldr r1, =0x01038038 + str r1, [r0, #0x01C] + + ldr r1, =0x00001800 + str r1, [r0, #0x020] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00020052 + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + str r1, [r0, #0x06c] + str r1, [r0, #0x070] + str r1, [r0, #0x074] + str r1, [r0, #0x078] + str r1, [r0, #0x07c] + str r1, [r0, #0x080] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6sll_evk_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/nxp/mx6sxsabreauto/Kconfig b/board/nxp/mx6sxsabreauto/Kconfig new file mode 100644 index 00000000000..6d1ae40adb7 --- /dev/null +++ b/board/nxp/mx6sxsabreauto/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6SXSABREAUTO + +config SYS_BOARD + default "mx6sxsabreauto" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "mx6sxsabreauto" + +config IMX_CONFIG + default "board/nxp/mx6sxsabreauto/imximage.cfg" + +endif diff --git a/board/nxp/mx6sxsabreauto/MAINTAINERS b/board/nxp/mx6sxsabreauto/MAINTAINERS new file mode 100644 index 00000000000..70036f8e3d6 --- /dev/null +++ b/board/nxp/mx6sxsabreauto/MAINTAINERS @@ -0,0 +1,6 @@ +MX6SXSABREAUTO BOARD +M: Peng Fan +S: Maintained +F: board/nxp/mx6sxsabreauto/ +F: include/configs/mx6sxsabreauto.h +F: configs/mx6sxsabreauto_defconfig diff --git a/board/nxp/mx6sxsabreauto/Makefile b/board/nxp/mx6sxsabreauto/Makefile new file mode 100644 index 00000000000..50f29a9dd02 --- /dev/null +++ b/board/nxp/mx6sxsabreauto/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2014 Freescale Semiconductor, Inc. + +obj-y := mx6sxsabreauto.o diff --git a/board/nxp/mx6sxsabreauto/imximage.cfg b/board/nxp/mx6sxsabreauto/imximage.cfg new file mode 100644 index 00000000000..da703093aa6 --- /dev/null +++ b/board/nxp/mx6sxsabreauto/imximage.cfg @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + */ + +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +/* IOMUX - DDR IO Type */ +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000 + +/* Clock */ +DATA 4 0x020e032c 0x00000030 + +/* Address */ +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e02fc 0x00000030 +DATA 4 0x020e05f4 0x00000030 + +/* Control */ +DATA 4 0x020e0340 0x00000030 + +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000030 +DATA 4 0x020e0314 0x00000030 +DATA 4 0x020e0614 0x00000030 + +/* Data Strobe */ +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000030 +DATA 4 0x020e0334 0x00000030 +DATA 4 0x020e0338 0x00000030 +DATA 4 0x020e033c 0x00000030 + +/* Data */ +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000030 +DATA 4 0x020e0610 0x00000030 +DATA 4 0x020e061c 0x00000030 +DATA 4 0x020e0620 0x00000030 +DATA 4 0x020e02ec 0x00000030 +DATA 4 0x020e02f0 0x00000030 +DATA 4 0x020e02f4 0x00000030 +DATA 4 0x020e02f8 0x00000030 + +/* Calibrations - ZQ */ +DATA 4 0x021b0800 0xa1390003 + +/* Write leveling */ +DATA 4 0x021b080c 0x002C003D +DATA 4 0x021b0810 0x00110046 + +/* DQS Read Gate */ +DATA 4 0x021b083c 0x4160016C +DATA 4 0x021b0840 0x013C016C + +/* Read/Write Delay */ +DATA 4 0x021b0848 0x46424446 +DATA 4 0x021b0850 0x3A3C3C3A + +DATA 4 0x021b08c0 0x2492244A + +/* read data bit delay */ +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +/* Complete calibration by forced measurement */ +DATA 4 0x021b08b8 0x00000800 + +/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676b52f3 +DATA 4 0x021b0010 0xb66d8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000007f +DATA 4 0x021b0000 0x85190000 + +/* Initialize MT41K256M16HA-125 - MR2 */ +DATA 4 0x021b001c 0x04008032 +/* MR3 */ +DATA 4 0x021b001c 0x00008033 +/* MR1 */ +DATA 4 0x021b001c 0x00068031 +/* MR0 */ +DATA 4 0x021b001c 0x05208030 +/* DDR device ZQ calibration */ +DATA 4 0x021b001c 0x04008040 + +/* Final DDR setup, before operation start */ +DATA 4 0x021b0020 0x00000800 +DATA 4 0x021b0818 0x00022227 +DATA 4 0x021b0004 0x0002556d +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 diff --git a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c new file mode 100644 index 00000000000..d80cfd4ab27 --- /dev/null +++ b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * Author: Ye Li + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static int setup_fec(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); + + return enable_fec_anatop_clock(1, ENET_125MHZ); +} + +int board_eth_init(struct bd_info *bis) +{ + int ret; + + imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); + setup_fec(); + + ret = fecmxc_initialize_multi(bis, 1, + CFG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC%d MXC: %s:failed\n", 1, __func__); + + return ret; +} + +int board_phy_config(struct phy_device *phydev) +{ + /* + * Enable 1.8V(SEL_1P5_1P8_POS_REG) on + * Phy control debug reg 0 + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int power_init_board(void) +{ + struct udevice *dev; + int ret; + u32 dev_id, rev_id, i; + u32 switch_num = 6; + u32 offset = PFUZE100_SW1CMODE; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) + return 0; + + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* Init mode to APS_PFM */ + pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM); + + for (i = 0; i < switch_num - 1; i++) + pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM); + + /* set SW1AB staby volatage 0.975V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); + + /* set SW1C staby volatage 1.10V */ + pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); + + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + /* OGT1 */ + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + /* OTG2 */ + MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + +int board_early_init_f(void) +{ + return 0; +} + +#ifdef CONFIG_FSL_QSPI +int board_qspi_init(void) +{ + /* Set the clock */ + enable_qspi_clk(0); + + return 0; +} +#endif + +#ifdef CONFIG_NAND_MXS +iomux_v3_cfg_t gpmi_pads[] = { + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) | + MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3))); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +int board_init(void) +{ + struct gpio_desc desc; + int ret; + + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + ret = dm_gpio_lookup_name("gpio@30_4", &desc); + if (ret) + return ret; + + ret = dm_gpio_request(&desc, "cpu_per_rst_b"); + if (ret) + return ret; + /* Reset CPU_PER_RST_B signal for enet phy and PCIE */ + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + udelay(500); + dm_gpio_set_value(&desc, 1); + + ret = dm_gpio_lookup_name("gpio@32_2", &desc); + if (ret) + return ret; + + ret = dm_gpio_request(&desc, "steer_enet"); + if (ret) + return ret; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + udelay(500); + /* Set steering signal to L for selecting B0 */ + dm_gpio_set_value(&desc, 0); + +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + {"sda", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)}, + {"sdb", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, + {"nand", MAKE_CFGVAL(0x82, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + return 0; +} + +int checkboard(void) +{ + puts("Board: MX6SX SABRE AUTO\n"); + + return 0; +} diff --git a/board/nxp/mx6sxsabresd/Kconfig b/board/nxp/mx6sxsabresd/Kconfig new file mode 100644 index 00000000000..90f4978d24c --- /dev/null +++ b/board/nxp/mx6sxsabresd/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6SXSABRESD + +config SYS_BOARD + default "mx6sxsabresd" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "mx6sxsabresd" + +config IMX_CONFIG + default "board/nxp/mx6sxsabresd/imximage.cfg" + +endif diff --git a/board/nxp/mx6sxsabresd/MAINTAINERS b/board/nxp/mx6sxsabresd/MAINTAINERS new file mode 100644 index 00000000000..1dd21fc3c69 --- /dev/null +++ b/board/nxp/mx6sxsabresd/MAINTAINERS @@ -0,0 +1,6 @@ +MX6SXSABRESD BOARD +M: Fabio Estevam +S: Maintained +F: board/nxp/mx6sxsabresd/ +F: include/configs/mx6sxsabresd.h +F: configs/mx6sxsabresd_defconfig diff --git a/board/nxp/mx6sxsabresd/Makefile b/board/nxp/mx6sxsabresd/Makefile new file mode 100644 index 00000000000..266bd4ac495 --- /dev/null +++ b/board/nxp/mx6sxsabresd/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2014 Freescale Semiconductor, Inc. + +obj-y := mx6sxsabresd.o diff --git a/board/nxp/mx6sxsabresd/imximage.cfg b/board/nxp/mx6sxsabresd/imximage.cfg new file mode 100644 index 00000000000..313ab589505 --- /dev/null +++ b/board/nxp/mx6sxsabresd/imximage.cfg @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + */ + +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +/* + * Secure boot support + */ +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +/* IOMUX - DDR IO Type */ +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000 + +/* Clock */ +DATA 4 0x020e032c 0x00000030 + +/* Address */ +DATA 4 0x020e0300 0x00000020 +DATA 4 0x020e02fc 0x00000020 +DATA 4 0x020e05f4 0x00000020 + +/* Control */ +DATA 4 0x020e0340 0x00000020 + +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000020 +DATA 4 0x020e0314 0x00000020 +DATA 4 0x020e0614 0x00000020 + +/* Data Strobe */ +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000028 +DATA 4 0x020e0334 0x00000028 +DATA 4 0x020e0338 0x00000028 +DATA 4 0x020e033c 0x00000028 + +/* Data */ +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000028 +DATA 4 0x020e0610 0x00000028 +DATA 4 0x020e061c 0x00000028 +DATA 4 0x020e0620 0x00000028 +DATA 4 0x020e02ec 0x00000028 +DATA 4 0x020e02f0 0x00000028 +DATA 4 0x020e02f4 0x00000028 +DATA 4 0x020e02f8 0x00000028 + +/* Calibrations - ZQ */ +DATA 4 0x021b0800 0xa1390003 + +/* Write leveling */ +DATA 4 0x021b080c 0x00290025 +DATA 4 0x021b0810 0x00220022 + +/* DQS Read Gate */ +DATA 4 0x021b083c 0x41480144 +DATA 4 0x021b0840 0x01340130 + +/* Read/Write Delay */ +DATA 4 0x021b0848 0x3C3E4244 +DATA 4 0x021b0850 0x34363638 + +/* Read data bit delay */ +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +/* Complete calibration by forced measurement */ +DATA 4 0x021b08b8 0x00000800 + +/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676b52f3 +DATA 4 0x021b0010 0xb66d8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000005f +DATA 4 0x021b0000 0x84190000 + +/* Initialize MT41K256M16HA-125 - MR2 */ +DATA 4 0x021b001c 0x04008032 +/* MR3 */ +DATA 4 0x021b001c 0x00008033 +/* MR1 */ +DATA 4 0x021b001c 0x00048031 +/* MR0 */ +DATA 4 0x021b001c 0x05208030 +/* DDR device ZQ calibration */ +DATA 4 0x021b001c 0x04008040 + +/* Final DDR setup, before operation start */ +DATA 4 0x021b0020 0x00000800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b001c 0x00000000 diff --git a/board/nxp/mx6sxsabresd/mx6sxsabresd.c b/board/nxp/mx6sxsabresd/mx6sxsabresd.c new file mode 100644 index 00000000000..e3353feec68 --- /dev/null +++ b/board/nxp/mx6sxsabresd/mx6sxsabresd.c @@ -0,0 +1,328 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_b_pad = { + MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const peri_3v3_pads[] = { + MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const phy_control_pads[] = { + /* 25MHz Ethernet PHY Clock */ + MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + + /* ENET PHY Power */ + MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* AR8031 PHY Reset */ + MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static int setup_fec(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + int reg, ret; + + /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); + + ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) + return ret; + + imx_iomux_v3_setup_multiple_pads(phy_control_pads, + ARRAY_SIZE(phy_control_pads)); + + /* Enable the ENET power, active low */ + gpio_request(IMX_GPIO_NR(2, 6), "enet_rst"); + gpio_direction_output(IMX_GPIO_NR(2, 6) , 0); + + /* Reset AR8031 PHY */ + gpio_request(IMX_GPIO_NR(2, 7), "phy_rst"); + gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); + mdelay(10); + gpio_set_value(IMX_GPIO_NR(2, 7), 1); + + reg = readl(&anatop->pll_enet); + reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; + writel(reg, &anatop->pll_enet); + + return 0; +} + +int board_eth_init(struct bd_info *bis) +{ + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + setup_fec(); + + return cpu_eth_init(bis); +} + +int power_init_board(void) +{ + struct udevice *dev; + unsigned int reg; + int ret; + + dev = pfuze_common_init(); + if (!dev) + return -ENODEV; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + /* Enable power of VGEN5 3V3, needed for SD3 */ + reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); + reg &= ~LDO_VOL_MASK; + reg |= (LDOB_3_30V | (1 << LDO_EN)); + pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + /* + * Enable 1.8V(SEL_1P5_1P8_POS_REG) on + * Phy control debug reg 0 + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ + imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, + ARRAY_SIZE(peri_3v3_pads)); + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +#ifdef CONFIG_FSL_QSPI + +int board_qspi_init(void) +{ + /* Set the clock */ + enable_qspi_clk(1); + + return 0; +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static int setup_lcd(void) +{ + enable_lcdif_clock(LCDIF1_BASE_ADDR, 1); + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + /* Reset the LCD */ + gpio_request(IMX_GPIO_NR(3, 27), "lcd_rst"); + gpio_direction_output(IMX_GPIO_NR(3, 27) , 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(3, 27) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright"); + gpio_direction_output(IMX_GPIO_NR(6, 4) , 1); + + return 0; +} +#endif + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* + * Because kernel set WDOG_B mux before pad with the common pinctrl + * framwork now and wdog reset will be triggered once set WDOG_B mux + * with default pad setting, we set pad setting here to workaround this. + * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set + * as GPIO mux firstly here to workaround it. + */ + imx_iomux_v3_setup_pad(wdog_b_pad); + + /* Active high for ncp692 */ + gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en"); + gpio_direction_output(IMX_GPIO_NR(4, 16), 1); + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_VIDEO_MXS + setup_lcd(); +#endif + + return 0; +} + +static bool is_reva(void) +{ + return (nxp_board_rev() == 1); +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + if (is_reva()) + env_set("board_rev", "REVA"); +#endif + return 0; +} + +int checkboard(void) +{ +#ifdef CONFIG_NXP_BOARD_REVISION + printf("Board: MX6SX SABRE SDB rev%c\n", nxp_board_rev_string()); +#else + puts("Board: MX6SX SABRE SDB"); +#endif + return 0; +} diff --git a/board/nxp/mx6ul_14x14_evk/Kconfig b/board/nxp/mx6ul_14x14_evk/Kconfig new file mode 100644 index 00000000000..03b5318d5da --- /dev/null +++ b/board/nxp/mx6ul_14x14_evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX6UL_14X14_EVK || TARGET_MX6UL_9X9_EVK + +config SYS_BOARD + default "mx6ul_14x14_evk" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "mx6ul_14x14_evk" + +endif diff --git a/board/nxp/mx6ul_14x14_evk/MAINTAINERS b/board/nxp/mx6ul_14x14_evk/MAINTAINERS new file mode 100644 index 00000000000..4aa5e8e4702 --- /dev/null +++ b/board/nxp/mx6ul_14x14_evk/MAINTAINERS @@ -0,0 +1,7 @@ +MX6ULEVK BOARD +M: Peng Fan +S: Maintained +F: board/nxp/mx6ul_14x14_evk/ +F: include/configs/mx6ul_14x14_evk.h +F: configs/mx6ul_14x14_evk_defconfig +F: configs/mx6ul_9x9_evk_defconfig diff --git a/board/nxp/mx6ul_14x14_evk/Makefile b/board/nxp/mx6ul_14x14_evk/Makefile new file mode 100644 index 00000000000..272ada720e1 --- /dev/null +++ b/board/nxp/mx6ul_14x14_evk/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2015 Freescale Semiconductor, Inc. + +obj-y := mx6ul_14x14_evk.o diff --git a/board/nxp/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/nxp/mx6ul_14x14_evk/mx6ul_14x14_evk.c new file mode 100644 index 00000000000..fbb5a12212d --- /dev/null +++ b/board/nxp/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -0,0 +1,471 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#ifdef CONFIG_DM_PMIC +int power_init_board(void) +{ + struct udevice *dev; + int ret, dev_id, rev_id; + unsigned int reg; + + ret = pmic_get("pfuze3000", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* disable Low Power Mode during standby mode */ + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); + reg |= 0x1; + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); + + /* SW1B step ramp up time from 2us to 4us/25mV */ + pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40); + + /* SW1B mode to APS/PFM */ + pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc); + + /* SW1B standby voltage set to 0.975V */ + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb); + + return 0; +} +#endif + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_QSPI +static int board_qspi_init(void) +{ + /* Set the clock */ + enable_qspi_clk(0); + + return 0; +} +#endif + +#ifdef CONFIG_XPL_BUILD + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC2_BASE_ADDR, 0, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +int board_mmc_init(struct bd_info *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} +#endif + +#ifdef CONFIG_FEC_MXC +static int setup_fec(int fec_id) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + if (fec_id == 0) { + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + } else { + /* + * Use 50M anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + } + + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_VIDEO +static iomux_v3_cfg_t const lcd_pads[] = { + /* Use GPIO for Brightness adjustment, duty cycle = period. */ + MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static int setup_lcd(void) +{ + enable_lcdif_clock(LCDIF1_BASE_ADDR, 1); + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + /* Reset the LCD */ + gpio_request(IMX_GPIO_NR(5, 9), "lcd reset"); + gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 8), "backlight"); + gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); + + return 0; +} +#else +static inline int setup_lcd(void) { return 0; } +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(CFG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "EVK"); + + if (is_mx6ul_9x9_evk()) + env_set("board_rev", "9X9"); + else + env_set("board_rev", "14X14"); +#endif + + setup_lcd(); + + return 0; +} + +int checkboard(void) +{ + if (is_mx6ul_9x9_evk()) + puts("Board: MX6UL 9x9 EVK\n"); + else + puts("Board: MX6UL 14x14 EVK\n"); + + return 0; +} + +/* + * Backlight off and reset LCD before OS handover + */ +void board_preboot_os(void) +{ + gpio_set_value(IMX_GPIO_NR(1, 8), 0); + gpio_set_value(IMX_GPIO_NR(5, 9), 0); +} + +#ifdef CONFIG_XPL_BUILD +#include +#include +#include + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, +#ifdef CONFIG_TARGET_MX6UL_9X9_EVK + .grp_ddr_type = 0x00080000, +#else + .grp_ddr_type = 0x000c0000, +#endif +}; + +#ifdef CONFIG_TARGET_MX6UL_9X9_EVK +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000000, + .dram_odt1 = 0x00000000, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00003030, + .dram_sdqs1 = 0x00003030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpdgctrl0 = 0x20000000, + .p0_mprddlctl = 0x4040484f, + .p0_mpwrdlctl = 0x40405247, + .mpzqlp2ctl = 0x1b4700c7, +}; + +static struct mx6_lpddr2_cfg mem_ddr = { + .mem_speed = 800, + .density = 2, + .width = 16, + .banks = 4, + .rowaddr = 14, + .coladdr = 10, + .trcd_lp = 1500, + .trppb_lp = 1500, + .trpab_lp = 2000, + .trasmin = 4250, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, + .cs_density = 18, + .ncs = 1, + .cs1_mirror = 0, + .walat = 0, + .ralat = 5, + .mif3_mode = 3, + .bi_on = 1, + .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */ + .rtt_nom = 0, + .sde_to_rst = 0, /* LPDDR2 does not need this field */ + .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ + .ddr_type = DDR_TYPE_LPDDR2, + .refsel = 0, /* Refresh cycles at 64KHz */ + .refr = 3, /* 4 refresh commands per refresh cycle */ +}; + +#else +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpdgctrl0 = 0x41570155, + .p0_mprddlctl = 0x4040474A, + .p0_mpwrdlctl = 0x40405550, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, + .cs_density = 20, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ + .walat = 0, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 0, /* Refresh cycles at 64KHz */ + .refr = 1, /* 2 refresh commands per refresh cycle */ +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 800, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; +#endif + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + writel(0xFFFFFFFF, &ccm->CCGR7); +} + +static void spl_dram_init(void) +{ + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif diff --git a/board/nxp/mx6ullevk/Kconfig b/board/nxp/mx6ullevk/Kconfig new file mode 100644 index 00000000000..33b24577df5 --- /dev/null +++ b/board/nxp/mx6ullevk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6ULL_14X14_EVK + +config SYS_BOARD + default "mx6ullevk" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "mx6ullevk" + +config IMX_CONFIG + default "board/nxp/mx6ullevk/imximage.cfg" + +endif diff --git a/board/nxp/mx6ullevk/MAINTAINERS b/board/nxp/mx6ullevk/MAINTAINERS new file mode 100644 index 00000000000..c210c6f41e6 --- /dev/null +++ b/board/nxp/mx6ullevk/MAINTAINERS @@ -0,0 +1,8 @@ +MX6ULLEVK BOARD +M: Peng Fan +S: Maintained +F: board/nxp/mx6ullevk/ +F: include/configs/mx6ullevk.h +F: configs/mx6ull_14x14_evk_defconfig +F: configs/mx6ull_14x14_evk_plugin_defconfig +F: configs/mx6ulz_14x14_evk_defconfig diff --git a/board/nxp/mx6ullevk/Makefile b/board/nxp/mx6ullevk/Makefile new file mode 100644 index 00000000000..1ff03b5f1cd --- /dev/null +++ b/board/nxp/mx6ullevk/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2016 Freescale Semiconductor, Inc. + +obj-y := mx6ullevk.o diff --git a/board/nxp/mx6ullevk/imximage.cfg b/board/nxp/mx6ullevk/imximage.cfg new file mode 100644 index 00000000000..f1d532bcc55 --- /dev/null +++ b/board/nxp/mx6ullevk/imximage.cfg @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/nxp/mx6ullevk/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x000C0030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000004 +DATA 4 0x021B083C 0x41640158 +DATA 4 0x021B0848 0x40403237 +DATA 4 0x021B0850 0x40403C33 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00944009 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D0B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B0890 0x00400000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 + +#endif diff --git a/board/nxp/mx6ullevk/mx6ullevk.c b/board/nxp/mx6ullevk/mx6ullevk.c new file mode 100644 index 00000000000..189eddefea3 --- /dev/null +++ b/board/nxp/mx6ullevk/mx6ullevk.c @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int mmc_map_to_kernel_blk(int devno) +{ + return devno; +} + +int board_early_init_f(void) +{ + return 0; +} + +#ifdef CONFIG_FEC_MXC +static int setup_fec(int fec_id) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + if (fec_id == 0) { + /* + * Use 50MHz anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + } else { + /* + * Use 50MHz anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + } + + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(CFG_FEC_ENET_DEV); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + if (is_cpu_type(MXC_CPU_MX6ULZ)) + env_set("board_name", "ULZ-EVK"); + else + env_set("board_name", "EVK"); + env_set("board_rev", "14X14"); +#endif + + return 0; +} + +int checkboard(void) +{ + if (is_cpu_type(MXC_CPU_MX6ULZ)) + puts("Board: MX6ULZ 14x14 EVK\n"); + else + puts("Board: MX6ULL 14x14 EVK\n"); + + return 0; +} diff --git a/board/nxp/mx6ullevk/plugin.S b/board/nxp/mx6ullevk/plugin.S new file mode 100644 index 00000000000..1f631ff5e3e --- /dev/null +++ b/board/nxp/mx6ullevk/plugin.S @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#include + +/* DDR script */ +.macro imx6ull_ddr3_evk_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000C0000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + ldr r1, =0x00000030 + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + ldr r1, =0x000C0030 + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + + ldr r1, =0x00000030 + str r1, [r0, #0x260] + str r1, [r0, #0x264] + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00000030 + str r1, [r0, #0x280] + ldr r1, =0x00000030 + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00000004 + str r1, [r0, #0x80C] + ldr r1, =0x41640158 + str r1, [r0, #0x83C] + ldr r1, =0x40403237 + str r1, [r0, #0x848] + ldr r1, =0x40403C33 + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x00944009 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + ldr r1, =0x0002002D + str r1, [r0, #0x004] + ldr r1, =0x1B333030 + str r1, [r0, #0x008] + ldr r1, =0x676B52F3 + str r1, [r0, #0x00C] + ldr r1, =0xB66D0B63 + str r1, [r0, #0x010] + ldr r1, =0x01FF00DB + str r1, [r0, #0x014] + ldr r1, =0x00201740 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x000026D2 + str r1, [r0, #0x02C] + ldr r1, =0x006B1023 + str r1, [r0, #0x030] + ldr r1, =0x0000004F + str r1, [r0, #0x040] + ldr r1, =0x84180000 + str r1, [r0, #0x000] + ldr r1, =0x00400000 + str r1, [r0, #0x890] + ldr r1, =0x02008032 + str r1, [r0, #0x01C] + ldr r1, =0x00008033 + str r1, [r0, #0x01C] + ldr r1, =0x00048031 + str r1, [r0, #0x01C] + ldr r1, =0x15208030 + str r1, [r0, #0x01C] + ldr r1, =0x04008040 + str r1, [r0, #0x01C] + ldr r1, =0x00000800 + str r1, [r0, #0x020] + ldr r1, =0x00000227 + str r1, [r0, #0x818] + ldr r1, =0x0002552D + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xFFFFFFFF + str r1, [r0, #0x68] + str r1, [r0, #0x6C] + str r1, [r0, #0x70] + str r1, [r0, #0x74] + str r1, [r0, #0x78] + str r1, [r0, #0x7C] + str r1, [r0, #0x80] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6ull_ddr3_evk_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/nxp/mx7dsabresd/Kconfig b/board/nxp/mx7dsabresd/Kconfig new file mode 100644 index 00000000000..dcebe4cdb62 --- /dev/null +++ b/board/nxp/mx7dsabresd/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX7DSABRESD + +config SYS_BOARD + default "mx7dsabresd" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "mx7dsabresd" + +config IMX_CONFIG + default "board/nxp/mx7dsabresd/imximage.cfg" + +endif diff --git a/board/nxp/mx7dsabresd/MAINTAINERS b/board/nxp/mx7dsabresd/MAINTAINERS new file mode 100644 index 00000000000..5dea074f940 --- /dev/null +++ b/board/nxp/mx7dsabresd/MAINTAINERS @@ -0,0 +1,8 @@ +MX7DSABRESD BOARD +M: Adrian Alonso +M: Fabio Estevam +S: Maintained +F: board/nxp/mx7dsabresd +F: include/configs/mx7dsabresd.h +F: configs/mx7dsabresd_defconfig +F: configs/mx7dsabresd_qspi_defconfig diff --git a/board/nxp/mx7dsabresd/Makefile b/board/nxp/mx7dsabresd/Makefile new file mode 100644 index 00000000000..852b3d87ad5 --- /dev/null +++ b/board/nxp/mx7dsabresd/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2015 Freescale Semiconductor, Inc. + +obj-y := mx7dsabresd.o diff --git a/board/nxp/mx7dsabresd/imximage.cfg b/board/nxp/mx7dsabresd/imximage.cfg new file mode 100644 index 00000000000..59e66fbda16 --- /dev/null +++ b/board/nxp/mx7dsabresd/imximage.cfg @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : sd + */ + +BOOT_FROM sd + +/* + * Secure boot support + */ +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x01040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00400046 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00100004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x09081109 +DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x00000803 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00171717 +DATA 4 0x307a0214 0x04040404 +DATA 4 0x307a0218 0x0f040404 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e +DATA 4 0x3079009c 0x00000d6e +DATA 4 0x30790020 0x08080808 +DATA 4 0x30790030 0x08080808 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e407304 + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f + +CHECK_BITS_SET 4 0x307a0004 0x1 diff --git a/board/nxp/mx7dsabresd/mx7dsabresd.c b/board/nxp/mx7dsabresd/mx7dsabresd.c new file mode 100644 index 00000000000..bef4f901ff7 --- /dev/null +++ b/board/nxp/mx7dsabresd/mx7dsabresd.c @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_49OHM) + +#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define SPI_PAD_CTRL \ + (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST) + +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) + +#ifdef CONFIG_MXC_SPI +static iomux_v3_cfg_t const ecspi3_pads[] = { + MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1; +} + +static void setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads)); +} +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart1_pads[] = { + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const gpmi_pads[] = { + MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + /* NAND_USDHC_BUS_CLK is set in rom */ + set_clk_nand(); +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + + MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL), +}; + +static iomux_v3_cfg_t const pwm_pads[] = { + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static int setup_lcd(void) +{ + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); + + /* Reset LCD */ + gpio_request(IMX_GPIO_NR(3, 4), "lcd reset"); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 1), "lcd backlight"); + gpio_direction_output(IMX_GPIO_NR(1, 1) , 1); + + return 0; +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +int board_mmc_get_env_dev(int devno) +{ + if (devno == 2) + devno--; + + return devno; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + if (dev_no == 1) + dev_no++; + + return dev_no; +} + +#ifdef CONFIG_FEC_MXC +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); + + return set_clk_enet(ENET_125MHZ); +} + +int board_phy_config(struct phy_device *phydev) +{ + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +#ifdef CONFIG_FSL_QSPI +int board_qspi_init(void) +{ + /* Set the clock */ + set_clk_qspi(); + + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_VIDEO_MXS + setup_lcd(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + + return 0; +} + +#ifdef CONFIG_DM_PMIC +int power_init_board(void) +{ + struct udevice *dev; + int ret, dev_id, rev_id; + + ret = pmic_get("pmic@8", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); + + /* + * Set the voltage of VLDO4 output to 2.8V which feeds + * the MIPI DSI and MIPI CSI inputs. + */ + pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA); + + return 0; +} +#endif + +int board_late_init(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + unsigned char eth1addr[6]; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + /* + * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), + * since we use PMIC_PWRON to reset the board. + */ + clrsetbits_le16(&wdog->wcr, 0, 0x10); + + /* Get the second MAC address */ + imx_get_mac_from_fuse(1, eth1addr); + if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr)) + eth_env_set_enetaddr("eth1addr", eth1addr); + + return 0; +} + +int checkboard(void) +{ + char *mode; + + if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT)) + mode = "secure"; + else + mode = "non-secure"; + + printf("Board: i.MX7D SABRESD in %s mode\n", mode); + + return 0; +} diff --git a/board/nxp/mx7ulp_evk/Kconfig b/board/nxp/mx7ulp_evk/Kconfig new file mode 100644 index 00000000000..a2b3ad0e5b8 --- /dev/null +++ b/board/nxp/mx7ulp_evk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX7ULP_EVK + +config SYS_BOARD + default "mx7ulp_evk" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "mx7ulp_evk" + +config IMX_CONFIG + default "board/nxp/mx7ulp_evk/imximage.cfg" + +endif diff --git a/board/nxp/mx7ulp_evk/MAINTAINERS b/board/nxp/mx7ulp_evk/MAINTAINERS new file mode 100644 index 00000000000..37944d43d50 --- /dev/null +++ b/board/nxp/mx7ulp_evk/MAINTAINERS @@ -0,0 +1,7 @@ +MX7ULPEVK BOARD +M: Peng Fan +S: Maintained +F: board/nxp/mx7ulp_evk/ +F: include/configs/mx7ulp_evk.h +F: configs/mx7ulp_evk_defconfig +F: configs/mx7ulp_evk_plugin_defconfig diff --git a/board/nxp/mx7ulp_evk/Makefile b/board/nxp/mx7ulp_evk/Makefile new file mode 100644 index 00000000000..9f33c61f03b --- /dev/null +++ b/board/nxp/mx7ulp_evk/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2016 Freescale Semiconductor, Inc. + +obj-y := mx7ulp_evk.o diff --git a/board/nxp/mx7ulp_evk/imximage.cfg b/board/nxp/mx7ulp_evk/imximage.cfg new file mode 100644 index 00000000000..116e71c279a --- /dev/null +++ b/board/nxp/mx7ulp_evk/imximage.cfg @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/nxp/mx7ulp_evk/plugin.bin 0x2F020000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x403f00dc 0x00000000 +DATA 4 0x403e0040 0x01000020 +DATA 4 0x403e0500 0x01000000 +DATA 4 0x403e050c 0x80808080 +DATA 4 0x403e0508 0x00160002 +DATA 4 0x403E0510 0x00000001 +DATA 4 0x403E0514 0x00000014 +DATA 4 0x403e0500 0x00000001 +CHECK_BITS_SET 4 0x403e0500 0x01000000 +DATA 4 0x403e050c 0x8080801B +CHECK_BITS_SET 4 0x403e050c 0x00000040 +DATA 4 0x403E0030 0x00000001 +DATA 4 0x403e0040 0x11000020 +DATA 4 0x403f00dc 0x42000000 + +DATA 4 0x40B300AC 0x40000000 + +DATA 4 0x40AD0128 0x00040000 +DATA 4 0x40AD00F8 0x00000000 +DATA 4 0x40AD00D8 0x00000180 +DATA 4 0x40AD0108 0x00000180 +DATA 4 0x40AD0104 0x00000180 +DATA 4 0x40AD0124 0x00010000 +DATA 4 0x40AD0080 0x0000018C +DATA 4 0x40AD0084 0x0000018C +DATA 4 0x40AD0088 0x0000018C +DATA 4 0x40AD008C 0x0000018C + +DATA 4 0x40AD0120 0x00010000 +DATA 4 0x40AD010C 0x00000180 +DATA 4 0x40AD0110 0x00000180 +DATA 4 0x40AD0114 0x00000180 +DATA 4 0x40AD0118 0x00000180 +DATA 4 0x40AD0090 0x00000180 +DATA 4 0x40AD0094 0x00000180 +DATA 4 0x40AD0098 0x00000180 +DATA 4 0x40AD009C 0x00000180 + +DATA 4 0x40AD00E0 0x00040000 +DATA 4 0x40AD00E4 0x00040000 + +DATA 4 0x40AB001C 0x00008000 +DATA 4 0x40AB0800 0xA1390003 +DATA 4 0x40AB085C 0x0D3900A0 +DATA 4 0x40AB0890 0x00400000 + +DATA 4 0x40AB0848 0x40404040 +DATA 4 0x40AB0850 0x40404040 +DATA 4 0x40AB081C 0x33333333 +DATA 4 0x40AB0820 0x33333333 +DATA 4 0x40AB0824 0x33333333 +DATA 4 0x40AB0828 0x33333333 + +DATA 4 0x40AB08C0 0x24922492 +DATA 4 0x40AB08B8 0x00000800 + +DATA 4 0x40AB0004 0x00020052 +DATA 4 0x40AB000C 0x292C42F3 +DATA 4 0x40AB0010 0x00100A22 +DATA 4 0x40AB0038 0x00120556 +DATA 4 0x40AB0014 0x00C700DB +DATA 4 0x40AB0018 0x00211718 +DATA 4 0x40AB002C 0x0F9F26D2 +DATA 4 0x40AB0030 0x009F0E10 +DATA 4 0x40AB0040 0x0000003F +DATA 4 0x40AB0000 0xC3190000 + +DATA 4 0x40AB001C 0x00008010 +DATA 4 0x40AB001C 0x00008018 +DATA 4 0x40AB001C 0x003F8030 +DATA 4 0x40AB001C 0x003F8038 +DATA 4 0x40AB001C 0xFF0A8030 +DATA 4 0x40AB001C 0xFF0A8038 +DATA 4 0x40AB001C 0x04028030 +DATA 4 0x40AB001C 0x04028038 +DATA 4 0x40AB001C 0x83018030 +DATA 4 0x40AB001C 0x83018038 +DATA 4 0x40AB001C 0x01038030 +DATA 4 0x40AB001C 0x01038038 + +DATA 4 0x40AB083C 0x20000000 + +DATA 4 0x40AB0020 0x00001800 +DATA 4 0x40AB0800 0xA1310000 +DATA 4 0x40AB0004 0x00020052 +DATA 4 0x40AB0404 0x00011006 +DATA 4 0x40AB001C 0x00000000 +#endif diff --git a/board/nxp/mx7ulp_evk/mx7ulp_evk.c b/board/nxp/mx7ulp_evk/mx7ulp_evk.c new file mode 100644 index 00000000000..af68e57854e --- /dev/null +++ b/board/nxp/mx7ulp_evk/mx7ulp_evk.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_UP) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_cfg_t const lpuart4_pads[] = { + MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + mx7ulp_iomux_setup_multiple_pads(lpuart4_pads, + ARRAY_SIZE(lpuart4_pads)); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + const char *path; + int rc, nodeoff; + + if (get_boot_device() == USB_BOOT) { + path = fdt_get_alias(blob, "mmc0"); + if (!path) { + puts("Not found mmc0\n"); + return 0; + } + + nodeoff = fdt_path_offset(blob, path); + if (nodeoff < 0) + return 0; + + printf("Found usdhc0 node\n"); + if (fdt_get_property(blob, nodeoff, "vqmmc-supply", + NULL) != NULL) { + rc = fdt_delprop(blob, nodeoff, "vqmmc-supply"); + if (!rc) { + puts("Removed vqmmc-supply property\n"); +add: + rc = fdt_setprop(blob, nodeoff, + "no-1-8-v", NULL, 0); + if (rc == -FDT_ERR_NOSPACE) { + rc = fdt_increase_size(blob, 32); + if (!rc) + goto add; + } else if (rc) { + printf("Failed to add no-1-8-v property, %d\n", rc); + } else { + puts("Added no-1-8-v property\n"); + } + } else { + printf("Failed to remove vqmmc-supply property, %d\n", rc); + } + } + } + + return 0; +} +#endif diff --git a/board/nxp/mx7ulp_evk/plugin.S b/board/nxp/mx7ulp_evk/plugin.S new file mode 100644 index 00000000000..2cc93dbdd57 --- /dev/null +++ b/board/nxp/mx7ulp_evk/plugin.S @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + */ + +#include + +.macro imx7ulp_ddr_freq_decrease + ldr r2, =0x403f0000 + ldr r3, =0x00000000 + str r3, [r2, #0xdc] + + ldr r2, =0x403e0000 + ldr r3, =0x01000020 + str r3, [r2, #0x40] + ldr r3, =0x01000000 + str r3, [r2, #0x500] + + ldr r3, =0x80808080 + str r3, [r2, #0x50c] + ldr r3, =0x00160002 + str r3, [r2, #0x508] + ldr r3, =0x00000001 + str r3, [r2, #0x510] + ldr r3, =0x00000014 + str r3, [r2, #0x514] + ldr r3, =0x00000001 + str r3, [r2, #0x500] + + ldr r3, =0x01000000 +wait1: + ldr r4, [r2, #0x500] + and r4, r3 + cmp r4, r3 + bne wait1 + + ldr r3, =0x8080801B + str r3, [r2, #0x50c] + + ldr r3, =0x00000040 +wait2: + ldr r4, [r2, #0x50c] + and r4, r3 + cmp r4, r3 + bne wait2 + + ldr r3, =0x00000001 + str r3, [r2, #0x30] + ldr r3, =0x11000020 + str r3, [r2, #0x40] + + ldr r2, =0x403f0000 + ldr r3, =0x42000000 + str r3, [r2, #0xdc] + +.endm + +.macro imx7ulp_evk_ddr_setting + + imx7ulp_ddr_freq_decrease + + /* Enable MMDC PCC clock */ + ldr r2, =0x40b30000 + ldr r3, =0x40000000 + str r3, [r2, #0xac] + + /* Configure DDR pad */ + ldr r0, =0x40ad0000 + ldr r1, =0x00040000 + str r1, [r0, #0x128] + ldr r1, =0x0 + str r1, [r0, #0xf8] + ldr r1, =0x00000180 + str r1, [r0, #0xd8] + ldr r1, =0x00000180 + str r1, [r0, #0x108] + ldr r1, =0x00000180 + str r1, [r0, #0x104] + ldr r1, =0x00010000 + str r1, [r0, #0x124] + ldr r1, =0x0000018C + str r1, [r0, #0x80] + ldr r1, =0x0000018C + str r1, [r0, #0x84] + ldr r1, =0x0000018C + str r1, [r0, #0x88] + ldr r1, =0x0000018C + str r1, [r0, #0x8c] + + ldr r1, =0x00010000 + str r1, [r0, #0x120] + ldr r1, =0x00000180 + str r1, [r0, #0x10c] + ldr r1, =0x00000180 + str r1, [r0, #0x110] + ldr r1, =0x00000180 + str r1, [r0, #0x114] + ldr r1, =0x00000180 + str r1, [r0, #0x118] + ldr r1, =0x00000180 + str r1, [r0, #0x90] + ldr r1, =0x00000180 + str r1, [r0, #0x94] + ldr r1, =0x00000180 + str r1, [r0, #0x98] + ldr r1, =0x00000180 + str r1, [r0, #0x9c] + ldr r1, =0x00040000 + str r1, [r0, #0xe0] + ldr r1, =0x00040000 + str r1, [r0, #0xe4] + + ldr r0, =0x40ab0000 + ldr r1, =0x00008000 + str r1, [r0, #0x1c] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x0D3900A0 + str r1, [r0, #0x85c] + ldr r1, =0x00400000 + str r1, [r0, #0x890] + + ldr r1, =0x40404040 + str r1, [r0, #0x848] + ldr r1, =0x40404040 + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81c] + ldr r1, =0x33333333 + str r1, [r0, #0x820] + ldr r1, =0x33333333 + str r1, [r0, #0x824] + ldr r1, =0x33333333 + str r1, [r0, #0x828] + + ldr r1, =0x24922492 + str r1, [r0, #0x8c0] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + + ldr r1, =0x00020052 + str r1, [r0, #0x4] + ldr r1, =0x292C42F3 + str r1, [r0, #0xc] + ldr r1, =0x00100A22 + str r1, [r0, #0x10] + ldr r1, =0x00120556 + str r1, [r0, #0x38] + ldr r1, =0x00C700DB + str r1, [r0, #0x14] + ldr r1, =0x00211718 + str r1, [r0, #0x18] + + ldr r1, =0x0F9F26D2 + str r1, [r0, #0x2c] + ldr r1, =0x009F0E10 + str r1, [r0, #0x30] + ldr r1, =0x0000003F + str r1, [r0, #0x40] + ldr r1, =0xC3190000 + str r1, [r0, #0x0] + + ldr r1, =0x00008010 + str r1, [r0, #0x1c] + ldr r1, =0x00008018 + str r1, [r0, #0x1c] + ldr r1, =0x003F8030 + str r1, [r0, #0x1c] + ldr r1, =0x003F8038 + str r1, [r0, #0x1c] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x1c] + ldr r1, =0xFF0A8038 + str r1, [r0, #0x1c] + ldr r1, =0x04028030 + str r1, [r0, #0x1c] + ldr r1, =0x04028038 + str r1, [r0, #0x1c] + ldr r1, =0x83018030 + str r1, [r0, #0x1c] + ldr r1, =0x83018038 + str r1, [r0, #0x1c] + ldr r1, =0x01038030 + str r1, [r0, #0x1c] + ldr r1, =0x01038038 + str r1, [r0, #0x1c] + + ldr r1, =0x20000000 + str r1, [r0, #0x83c] + + ldr r1, =0x00001800 + str r1, [r0, #0x20] + ldr r1, =0xA1310000 + str r1, [r0, #0x800] + ldr r1, =0x00020052 + str r1, [r0, #0x4] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x1c] + +.endm + +.macro imx7ulp_clock_gating +.endm + +.macro imx7ulp_qos_setting +.endm + +.macro imx7ulp_ddr_setting + imx7ulp_evk_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/nxp/p1010rdb/Kconfig b/board/nxp/p1010rdb/Kconfig new file mode 100644 index 00000000000..fa376fc058c --- /dev/null +++ b/board/nxp/p1010rdb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB + +config SYS_BOARD + default "p1010rdb" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "P1010RDB" + +endif diff --git a/board/nxp/p1010rdb/MAINTAINERS b/board/nxp/p1010rdb/MAINTAINERS new file mode 100644 index 00000000000..f7543942754 --- /dev/null +++ b/board/nxp/p1010rdb/MAINTAINERS @@ -0,0 +1,21 @@ +P1010RDB BOARD +M: Qiang Zhao +S: Maintained +F: board/nxp/p1010rdb/ +F: include/configs/P1010RDB.h +F: configs/P1010RDB-PA_36BIT_NAND_defconfig +F: configs/P1010RDB-PA_36BIT_NOR_defconfig +F: configs/P1010RDB-PA_36BIT_SDCARD_defconfig +F: configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +F: configs/P1010RDB-PA_NAND_defconfig +F: configs/P1010RDB-PA_NOR_defconfig +F: configs/P1010RDB-PA_SDCARD_defconfig +F: configs/P1010RDB-PA_SPIFLASH_defconfig +F: configs/P1010RDB-PB_36BIT_NAND_defconfig +F: configs/P1010RDB-PB_36BIT_NOR_defconfig +F: configs/P1010RDB-PB_36BIT_SDCARD_defconfig +F: configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +F: configs/P1010RDB-PB_NAND_defconfig +F: configs/P1010RDB-PB_NOR_defconfig +F: configs/P1010RDB-PB_SDCARD_defconfig +F: configs/P1010RDB-PB_SPIFLASH_defconfig diff --git a/board/nxp/p1010rdb/Makefile b/board/nxp/p1010rdb/Makefile new file mode 100644 index 00000000000..df4e8001d38 --- /dev/null +++ b/board/nxp/p1010rdb/Makefile @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2010-2011 Freescale Semiconductor, Inc. + +MINIMAL= + +ifdef CONFIG_XPL_BUILD +ifndef CONFIG_TPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif +endif + +ifdef MINIMAL +obj-y += spl_minimal.o +else +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +endif +obj-y += p1010rdb.o +obj-y += ddr.o +endif + +obj-y += law.o +obj-y += tlb.o diff --git a/board/nxp/p1010rdb/README.P1010RDB-PA b/board/nxp/p1010rdb/README.P1010RDB-PA new file mode 100644 index 00000000000..0cb950d845e --- /dev/null +++ b/board/nxp/p1010rdb/README.P1010RDB-PA @@ -0,0 +1,207 @@ +Overview +========= +The P1010RDB is a Freescale reference design board that hosts the P1010 SoC. + +The P1010 is a cost-effective, low-power, highly integrated host processor +based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz), +that addresses the requirements of several routing, gateways, storage, consumer, +and industrial applications. Applications of interest include the main CPUs and +I/O processors in network attached storage (NAS), the voice over IP (VoIP) +router/gateway, and wireless LAN (WLAN) and industrial controllers. + +The P1010RDB board features are as follows: +Memory subsystem: + - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) + - 32 Mbyte NOR flash single-chip memory + - 32 Mbyte NAND flash memory + - 256 Kbit M24256 I2C EEPROM + - 16 Mbyte SPI memory + - I2C Board EEPROM 128x8 bit memory + - SD/MMC connector to interface with the SD memory card +Interfaces: + - PCIe: + - Lane0: x1 mini-PCIe slot + - Lane1: x1 PCIe standard slot + - SATA: + - 1 internal SATA connector to 2.5” 160G SATA2 HDD + - 1 eSATA connector to rear panel + - 10/100/1000 BaseT Ethernet ports: + - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO + - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221 + - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221 + - USB 2.0 port: + - x1 USB2.0 port via an external ULPI PHY to micro-AB connector + - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector + - FlexCAN ports: + - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B) + interface; + - DUART interface: + - DUART interface: supports two UARTs up to 115200 bps for + console display + - RJ45 connectors are used for these 2 UART ports. + - TDM + - 2 FXS ports connected via an external SLIC to the TDM interface. + SLIC is controllled via SPI. + - 1 FXO port connected via a relay to FXS for switchover to POTS +Board connectors: + - Mini-ITX power supply connector + - JTAG/COP for debugging +IEEE Std. 1588 signals for test and measurement +Real-time clock on I2C bus +POR + - support critical POR setting changed via switch on board +PCB + - 6-layer routing (4-layer signals, 2-layer power and ground) + + +Physical Memory Map on P1010RDB +=============================== +Address Start Address End Memory type Attributes +0x0000_0000 0x3fff_ffff DDR 1G Cacheable +0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable +0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable +0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable +0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable +0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable +0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0 +0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + + +Serial Port Configuration on P1010RDB +===================================== +Configure the serial port of the attached computer with the following values: + -Data rate: 115200 bps + -Number of data bits: 8 + -Parity: None + -Number of Stop bits: 1 + -Flow Control: Hardware/None + + +Settings of DIP-switch +====================== + SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash + SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash + SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash +Note: 1 stands for 'on', 0 stands for 'off' + + +Setting of hwconfig +=================== +If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or +"fsl_p1010mux:tdm_can=tdm" explicitly in u-boot prompt as below for example: +setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi" +By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection +is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM +instead of to CAN/UART1. + + +Build and burn U-Boot to NOR flash +================================== +1. Build u-boot.bin image + export CROSS_COMPILE=/your_path/powerpc-linux-gnu- + make P1010RDB_NOR + +2. Burn u-boot.bin into NOR flash + => tftp $loadaddr $uboot + => protect off eff40000 +$filesize + => erase eff40000 +$filesize + => cp.b $loadaddr eff40000 $filesize + +3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. + + +Alternate NOR bank +================== +1. Burn u-boot.bin into alternate NOR bank + => tftp $loadaddr $uboot + => protect off eef40000 +$filesize + => erase eef40000 +$filesize + => cp.b $loadaddr eef40000 $filesize + +2. Switch to alternate NOR bank + => mw.b ffb00009 1 + => reset + or set SW1[8]= ON + +SW1[8]= OFF: Upper bank used for booting start +SW1[8]= ON: Lower bank used for booting start +CPLD NOR bank selection register address 0xFFB00009 Bit[0]: +0 - boot from upper 4 sectors +1 - boot from lower 4 sectors + + +Build and burn U-Boot to NAND flash +=================================== +1. Build u-boot.bin image + export ARCH=powerpc + export CROSS_COMPILE=/your_path/powerpc-linux-gnu- + make P1010RDB_NAND + +2. Burn u-boot-nand.bin into NAND flash + => tftp $loadaddr $uboot-nand + => nand erase 0 $filesize + => nand write $loadaddr 0 $filesize + +3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on. + + +Build and burn U-Boot to SPI flash +================================== +1. Build u-boot-spi.bin image + make P1010RDB_SPIFLASH_config; make + Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb + Download u-boot.bin to linux and you can find some config files + under /usr/share such as config_xx.dat. Do below command: + boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \ + u-boot-spi.bin + to generate u-boot-spi.bin. + +2. Burn u-boot-spi.bin into SPI flash + => tftp $loadaddr $uboot-spi + => sf erase 0 100000 + => sf write $loadaddr 0 $filesize + +3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on. + + +CPLD POR setting registers +========================== +1. Set POR switch selection register (addr 0xFFB00011) to 0. +2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with + proper values. + If change boot ROM location to NOR or NAND flash, need write the IFC_CS0 + switch command by I2C. +3. Send reset command. + After reset, the new POR setting will be implemented. + +Two examples are given in below: +Switch from NOR to NAND boot with default frequency: + => i2c dev 0 + => i2c mw 18 1 f9 + => i2c mw 18 3 f0 + => mw.b ffb00011 0 + => mw.b ffb00017 1 + => reset +Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz): + => i2c dev 0 + => i2c mw 18 1 f1 + => i2c mw 18 3 f0 + => mw.b ffb00011 0 + => mw.b ffb00014 2 + => mw.b ffb00015 5 + => mw.b ffb00016 3 + => mw.b ffb00017 f + => reset + + +Boot Linux from network using TFTP on P1010RDB +============================================== +Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area. + => tftp 1000000 uImage + => tftp 2000000 p1010rdb.dtb + => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb + => bootm 1000000 3000000 2000000 + + +For more details, please refer to P1010RDB User Guide and access website +www.freescale.com diff --git a/board/nxp/p1010rdb/README.P1010RDB-PB b/board/nxp/p1010rdb/README.P1010RDB-PB new file mode 100644 index 00000000000..4a3b389877f --- /dev/null +++ b/board/nxp/p1010rdb/README.P1010RDB-PB @@ -0,0 +1,187 @@ +Overview +========= +The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC. +P1010RDB-PB is a variation of previous P1010RDB-PA board. + +The P1010 is a cost-effective, low-power, highly integrated host processor +based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that +addresses the requirements of several routing, gateways, storage, consumer, +and industrial applications. Applications of interest include the main CPUs and +I/O processors in network attached storage (NAS), the voice over IP (VoIP) +router/gateway, and wireless LAN (WLAN) and industrial controllers. + +The P1010RDB-PB board features are as following: +Memory subsystem: + - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus) + - 32M bytes NOR flash single-chip memory + - 2G bytes NAND flash memory + - 16M bytes SPI memory + - 256K bit M24256 I2C EEPROM + - I2C Board EEPROM 128x8 bit memory + - SD/MMC connector to interface with the SD memory card +Interfaces: + - Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII) + - PCIe 2.0: two x1 mini-PCIe slots + - SATA 2.0: two SATA interfaces + - USB 2.0: one USB interface + - FlexCAN: two FlexCAN interfaces (revision 2.0B) + - UART: one USB-to-Serial interface + - TDM: 2 FXS ports connected via an external SLIC to the TDM interface. + 1 FXO port connected via a relay to FXS for switchover to POTS + +Board connectors: + - Mini-ITX power supply connector + - JTAG/COP for debugging + +POR: support critical POR setting changed via switch on board +PCB: 6-layer routing (4-layer signals, 2-layer power and ground) + +Physical Memory Map on P1010RDB +=============================== +Address Start Address End Memory type Attributes +0x0000_0000 0x3fff_ffff DDR 1G Cacheable +0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable +0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable +0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable +0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable +0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable +0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0 +0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + + +Serial Port Configuration on P1010RDB +===================================== +Configure the serial port of the attached computer with the following values: + -Data rate: 115200 bps + -Number of data bits: 8 + -Parity: None + -Number of Stop bits: 1 + -Flow Control: Hardware/None + + +P1010RDB-PB default DIP-switch settings +======================================= +SW1[1:8]= 10101010 +SW2[1:8]= 11011000 +SW3[1:8]= 10010000 +SW4[1:4]= 1010 +SW5[1:8]= 11111010 + + +P1010RDB-PB boot mode settings via DIP-switch +============================================= +SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot +SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot +SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot +SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot +Note: 1 stands for 'on', 0 stands for 'off' + + +Switch P1010RDB-PB boot mode via software without setting DIP-switch +==================================================================== +=> run boot_bank0 (boot from NOR bank0) +=> run boot_bank1 (boot from NOR bank1) +=> run boot_nand (boot from NAND flash) +=> run boot_spi (boot from SPI flash) +=> run boot_sd (boot from SD card) + + +Frequency combination support on P1010RDB-PB +============================================= +SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s) +0101 1 1010 0 800 400 800 +1001 1 1010 0 800 400 667 +1010 1 1100 0 667 333 667 +1000 0 1010 0 533 266 667 +0101 1 1010 1 1000 400 800 +1001 1 1010 1 1000 400 667 + + +Setting of pin mux +================== +Since pins multiplexing, TDM and CAN are muxed with SPI flash. +SDHC is muxed with IFC. IFC and SPI flash are enabled by default. + +To enable TDM: +=> setenv hwconfig fsl_p1010mux:tdm_can=tdm +=> save;reset + +To enable FlexCAN: +=> setenv hwconfig fsl_p1010mux:tdm_can=can +=> save;reset + +To enable SDHC in case of NOR/NAND/SPI boot + a) For temporary use case in runtime without reboot system + run 'mux sdhc' in U-Boot to validate SDHC with invalidating IFC. + + b) For long-term use case + set 'esdhc' in hwconfig and save it. + +To enable IFC in case of SD boot + a) For temporary use case in runtime without reboot system + run 'mux ifc' in U-Boot to validate IFC with invalidating SDHC. + + b) For long-term use case + set 'ifc' in hwconfig and save it. + + +Build images for different boot mode +==================================== +First setup cross compile environment on build host + $ export CROSS_COMPILE=/powerpc-linux-gnu- + +1. For NOR boot + $ make P1010RDB-PB_NOR + +2. For NAND boot + $ make P1010RDB-PB_NAND + +3. For SPI boot + $ make P1010RDB-PB_SPIFLASH + +4. For SD boot + $ make P1010RDB-PB_SDCARD + + +Steps to program images to flash for different boot mode +======================================================== +1. NOR boot + => tftp 1000000 u-boot.bin + For bank0 + => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize + set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board + + For bank1 + => pro off all;era eef40000 eeffffff;cp.b 1000000 eef40000 $filesize + set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board + +2. NAND boot + => tftp 1000000 u-boot-nand.bin + => nand erase 0 $filesize; nand write $loadaddr 0 $filesize + Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board + +3. SPI boot + 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin + 2) => tftp 1000000 u-boot-spi-combined.bin + 3) => sf probe 0; sf erase 0 100000; sf write 1000000 0 100000 + set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board + +4. SD boot + 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin + 2) => tftp 1000000 u-boot-sd-combined.bin + 3) => mux sdhc + 4) => mmc write 1000000 0 1050 + set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board + + +Boot Linux from network using TFTP on P1010RDB-PB +================================================= +Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path. + => tftp 1000000 uImage + => tftp 2000000 p1010rdb.dtb + => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb + => bootm 1000000 3000000 2000000 + + +For more details, please refer to P1010RDB-PB User Guide and access website +www.freescale.com and Freescale QorIQ SDK Infocenter document. diff --git a/board/nxp/p1010rdb/ddr.c b/board/nxp/p1010rdb/ddr.c new file mode 100644 index 00000000000..43a0936bc9a --- /dev/null +++ b/board/nxp/p1010rdb/ddr.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Samsung K4B2G0846C-HCF8 + * The following timing are for "downshift" + * i.e. to use CL9 part as CL7 + * otherwise, tAA, tRCD, tRP will be 13500ps + * and tRC will be 49500ps + */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 1875, + .caslat_x = 0x1e << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 7800000, + .tfaw_ps = 37500, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR on board"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + struct cpu_type *cpu; + int i; + popts->clk_adjust = 6; + popts->cpo_override = 0x1f; + popts->write_data_delay = 2; + popts->half_strength_driver_enable = 1; + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x8; + popts->trwt_override = 1; + popts->trwt = 0; + + cpu = gd->arch.cpu; + /* P1014 and it's derivatives support max 16it DDR width */ + if (cpu->soc_ver == SVR_P1014) + popts->data_bus_width = DDR_DATA_BUS_WIDTH_16; + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; + } +} diff --git a/board/nxp/p1010rdb/law.c b/board/nxp/p1010rdb/law.c new file mode 100644 index 00000000000..a7d80f28521 --- /dev/null +++ b/board/nxp/p1010rdb/law.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/nxp/p1010rdb/p1010rdb.c b/board/nxp/p1010rdb/p1010rdb.c new file mode 100644 index 00000000000..9b4b6f34f46 --- /dev/null +++ b/board/nxp/p1010rdb/p1010rdb.c @@ -0,0 +1,679 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define GPIO4_PCIE_RESET_SET 0x08000000 +#define MUX_CPLD_CAN_UART 0x00 +#define MUX_CPLD_TDM 0x01 +#define MUX_CPLD_SPICS0_FLASH 0x00 +#define MUX_CPLD_SPICS0_SLIC 0x02 +#define PMUXCR1_IFC_MASK 0x00ffff00 +#define PMUXCR1_SDHC_MASK 0x00fff000 +#define PMUXCR1_SDHC_ENABLE 0x00555000 + +enum { + MUX_TYPE_IFC, + MUX_TYPE_SDHC, + MUX_TYPE_SPIFLASH, + MUX_TYPE_TDM, + MUX_TYPE_CAN, + MUX_TYPE_CS0_NOR, + MUX_TYPE_CS0_NAND, +}; + +enum { + I2C_READ_BANK, + I2C_READ_PCB_VER, +}; + +static uint sd_ifc_mux; + +struct cpld_data { + u8 cpld_ver; /* cpld revision */ +#if defined(CONFIG_TARGET_P1010RDB_PA) + u8 pcba_ver; /* pcb revision number */ + u8 twindie_ddr3; + u8 res1[6]; + u8 bank_sel; /* NOR Flash bank */ + u8 res2[5]; + u8 usb2_sel; + u8 res3[1]; + u8 porsw_sel; + u8 tdm_can_sel; + u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */ + u8 por0; /* POR Options */ + u8 por1; /* POR Options */ + u8 por2; /* POR Options */ + u8 por3; /* POR Options */ +#elif defined(CONFIG_TARGET_P1010RDB_PB) + u8 rom_loc; +#endif +}; + +int board_early_init_f(void) +{ + ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); + struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; + /* Clock configuration to access CPLD using IFC(GPCM) */ + setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); + /* + * Reset PCIe slots via GPIO4 + */ + setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET); + setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CFG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_16M, 1); + + set_tlb(1, flashbase + 0x1000000, + CFG_SYS_FLASH_BASE_PHYS + 0x1000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel+1, BOOKE_PAGESZ_16M, 1); + return 0; +} + +int config_board_mux(int ctrl_type) +{ + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + u8 tmp; + +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + int ret; +#if defined(CONFIG_TARGET_P1010RDB_PA) + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); + + ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, + I2C_PCA9557_ADDR1, 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", + __func__, I2C_PCA9557_BUS_NUM); + return ret; + } + switch (ctrl_type) { + case MUX_TYPE_IFC: + tmp = 0xf0; + dm_i2c_write(dev, 3, &tmp, 1); + tmp = 0x01; + dm_i2c_write(dev, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_IFC; + clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); + break; + case MUX_TYPE_SDHC: + tmp = 0xf0; + dm_i2c_write(dev, 3, &tmp, 1); + tmp = 0x05; + dm_i2c_write(dev, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_SDHC; + clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, + PMUXCR1_SDHC_ENABLE); + break; + case MUX_TYPE_SPIFLASH: + out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); + break; + case MUX_TYPE_TDM: + out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); + out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); + break; + case MUX_TYPE_CAN: + out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); + break; + default: + break; + } +#elif defined(CONFIG_TARGET_P1010RDB_PB) + ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, + I2C_PCA9557_ADDR2, 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", + __func__, I2C_PCA9557_BUS_NUM); + return ret; + } + switch (ctrl_type) { + case MUX_TYPE_IFC: + dm_i2c_read(dev, 0, &tmp, 1); + clrbits_8(&tmp, 0x04); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x04); + dm_i2c_write(dev, 3, &tmp, 1); + sd_ifc_mux = MUX_TYPE_IFC; + clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); + break; + case MUX_TYPE_SDHC: + dm_i2c_read(dev, 0, &tmp, 1); + setbits_8(&tmp, 0x04); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x04); + dm_i2c_write(dev, 3, &tmp, 1); + sd_ifc_mux = MUX_TYPE_SDHC; + clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, + PMUXCR1_SDHC_ENABLE); + break; + case MUX_TYPE_SPIFLASH: + dm_i2c_read(dev, 0, &tmp, 1); + clrbits_8(&tmp, 0x80); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x80); + dm_i2c_write(dev, 3, &tmp, 1); + break; + case MUX_TYPE_TDM: + dm_i2c_read(dev, 0, &tmp, 1); + setbits_8(&tmp, 0x82); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x82); + dm_i2c_write(dev, 3, &tmp, 1); + break; + case MUX_TYPE_CAN: + dm_i2c_read(dev, 0, &tmp, 1); + clrbits_8(&tmp, 0x02); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x02); + dm_i2c_write(dev, 3, &tmp, 1); + break; + case MUX_TYPE_CS0_NOR: + dm_i2c_read(dev, 0, &tmp, 1); + clrbits_8(&tmp, 0x08); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x08); + dm_i2c_write(dev, 3, &tmp, 1); + break; + case MUX_TYPE_CS0_NAND: + dm_i2c_read(dev, 0, &tmp, 1); + setbits_8(&tmp, 0x08); + dm_i2c_write(dev, 1, &tmp, 1); + dm_i2c_read(dev, 3, &tmp, 1); + clrbits_8(&tmp, 0x08); + dm_i2c_write(dev, 3, &tmp, 1); + break; + default: + break; + } +#endif +#else +#if defined(CONFIG_TARGET_P1010RDB_PA) + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); + + switch (ctrl_type) { + case MUX_TYPE_IFC: + i2c_set_bus_num(I2C_PCA9557_BUS_NUM); + tmp = 0xf0; + i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1); + tmp = 0x01; + i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_IFC; + clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); + break; + case MUX_TYPE_SDHC: + i2c_set_bus_num(I2C_PCA9557_BUS_NUM); + tmp = 0xf0; + i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1); + tmp = 0x05; + i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_SDHC; + clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, + PMUXCR1_SDHC_ENABLE); + break; + case MUX_TYPE_SPIFLASH: + out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); + break; + case MUX_TYPE_TDM: + out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); + out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); + break; + case MUX_TYPE_CAN: + out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); + break; + default: + break; + } +#elif defined(CONFIG_TARGET_P1010RDB_PB) + uint orig_bus = i2c_get_bus_num(); + i2c_set_bus_num(I2C_PCA9557_BUS_NUM); + + switch (ctrl_type) { + case MUX_TYPE_IFC: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + clrbits_8(&tmp, 0x04); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x04); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_IFC; + clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); + break; + case MUX_TYPE_SDHC: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + setbits_8(&tmp, 0x04); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x04); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + sd_ifc_mux = MUX_TYPE_SDHC; + clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, + PMUXCR1_SDHC_ENABLE); + break; + case MUX_TYPE_SPIFLASH: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + clrbits_8(&tmp, 0x80); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x80); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + case MUX_TYPE_TDM: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + setbits_8(&tmp, 0x82); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x82); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + case MUX_TYPE_CAN: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + clrbits_8(&tmp, 0x02); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x02); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + case MUX_TYPE_CS0_NOR: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + clrbits_8(&tmp, 0x08); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x08); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + case MUX_TYPE_CS0_NAND: + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); + setbits_8(&tmp, 0x08); + i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); + i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + clrbits_8(&tmp, 0x08); + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); + break; + default: + break; + } + i2c_set_bus_num(orig_bus); +#endif +#endif + return 0; +} + +#ifdef CONFIG_TARGET_P1010RDB_PB +int i2c_pca9557_read(int type) +{ + u8 val; + int bus_num = I2C_PCA9557_BUS_NUM; + +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", + __func__, bus_num); + return ret; + } + dm_i2c_read(dev, 0, &val, 1); +#else + i2c_set_bus_num(bus_num); + i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1); +#endif + + switch (type) { + case I2C_READ_BANK: + val = (val & 0x10) >> 4; + break; + case I2C_READ_PCB_VER: + val = ((val & 0x60) >> 5) + 1; + break; + default: + break; + } + + return val; +} +#endif + +int checkboard(void) +{ + struct cpu_type *cpu; + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); + u8 val; + + cpu = gd->arch.cpu; +#if defined(CONFIG_TARGET_P1010RDB_PA) + printf("Board: %sRDB-PA, ", cpu->name); +#elif defined(CONFIG_TARGET_P1010RDB_PB) + printf("Board: %sRDB-PB, ", cpu->name); +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + I2C_PCA9557_BUS_NUM); + return ret; + } + val = 0x0; /* no polarity inversion */ + dm_i2c_write(dev, 2, &val, 1); +#else + i2c_set_bus_num(I2C_PCA9557_BUS_NUM); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + val = 0x0; /* no polarity inversion */ + i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1); +#endif +#endif + +#ifdef CONFIG_SDCARD + /* switch to IFC to read info from CPLD */ + config_board_mux(MUX_TYPE_IFC); +#endif + +#if defined(CONFIG_TARGET_P1010RDB_PA) + val = (in_8(&cpld_data->pcba_ver) & 0xf); + printf("PCB: v%x.0\n", val); +#elif defined(CONFIG_TARGET_P1010RDB_PB) + val = in_8(&cpld_data->cpld_ver); + printf("CPLD: v%x.%x, ", val >> 4, val & 0xf); + printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER)); + val = in_8(&cpld_data->rom_loc) & 0xf; + puts("Boot from: "); + switch (val) { + case 0xf: + config_board_mux(MUX_TYPE_CS0_NOR); + printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK)); + break; + case 0xe: + puts("SDHC\n"); + val = 0x60; /* set pca9557 pin input/output */ +#if CONFIG_IS_ENABLED(DM_I2C) + dm_i2c_write(dev, 3, &val, 1); +#else + i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1); +#endif + break; + case 0x5: + config_board_mux(MUX_TYPE_IFC); + config_board_mux(MUX_TYPE_CS0_NAND); + puts("NAND\n"); + break; + case 0x6: + config_board_mux(MUX_TYPE_IFC); + puts("SPI\n"); + break; + default: + puts("unknown\n"); + break; + } +#endif + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void fdt_del_flexcan(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "fsl,p1010-flexcan")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} + +void fdt_del_spi_flash(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "spansion,s25sl12801")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} + +void fdt_del_spi_slic(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "zarlink,le88266")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} + +void fdt_del_tdm(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "fsl,starlite-tdm")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} + +void fdt_del_sdhc(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "fsl,esdhc")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} + +void fdt_del_ifc(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "fsl,ifc")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} + +void fdt_disable_uart1(void *blob) +{ + int nodeoff; + + nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550", + CFG_SYS_NS16550_COM2); + + if (nodeoff > 0) { + fdt_status_disabled(blob, nodeoff); + } else { + printf("WARNING unable to set status for fsl,ns16550 " + "uart1: %s\n", fdt_strerror(nodeoff)); + } +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + phys_addr_t base; + phys_size_t size; + struct cpu_type *cpu; + + cpu = gd->arch.cpu; + + ft_cpu_setup(blob, bd); + + base = env_get_bootm_low(); + size = env_get_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#if defined(CONFIG_HAS_FSL_DR_USB) + fsl_fdt_fixup_dr_usb(blob, bd); +#endif + + /* P1014 and it's derivatives don't support CAN and eTSEC3 */ + if (cpu->soc_ver == SVR_P1014) { + fdt_del_flexcan(blob); + fdt_del_node_and_alias(blob, "ethernet2"); + } + + /* Delete IFC node as IFC pins are multiplexing with SDHC */ + if (sd_ifc_mux != MUX_TYPE_IFC) + fdt_del_ifc(blob); + else + fdt_del_sdhc(blob); + + if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { + fdt_del_tdm(blob); + fdt_del_spi_slic(blob); + } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { + fdt_del_flexcan(blob); + fdt_del_spi_flash(blob); + fdt_disable_uart1(blob); + } else { + /* + * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm" + * explicitly, defaultly spi_cs_sel to spi-flash instead of + * to tdm/slic. + */ + fdt_del_tdm(blob); + fdt_del_flexcan(blob); + fdt_disable_uart1(blob); + } + + return 0; +} +#endif + +#ifdef CONFIG_SDCARD +int board_mmc_init(struct bd_info *bis) +{ + config_board_mux(MUX_TYPE_SDHC); + return -1; +} +#else +void board_reset(void) +{ + /* mux to IFC to enable CPLD for reset */ + if (sd_ifc_mux != MUX_TYPE_IFC) + config_board_mux(MUX_TYPE_IFC); +} +#endif + +int misc_init_r(void) +{ + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + + if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM | + MPC85xx_PMUXCR_CAN1_UART | + MPC85xx_PMUXCR_CAN2_TDM | + MPC85xx_PMUXCR_CAN2_UART); + config_board_mux(MUX_TYPE_CAN); + } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART | + MPC85xx_PMUXCR_CAN1_UART); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM | + MPC85xx_PMUXCR_CAN1_TDM); + clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO); + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM); + config_board_mux(MUX_TYPE_TDM); + } else { + /* defaultly spi_cs_sel to flash */ + config_board_mux(MUX_TYPE_SPIFLASH); + } + + if (hwconfig("esdhc")) + config_board_mux(MUX_TYPE_SDHC); + else if (hwconfig("ifc")) + config_board_mux(MUX_TYPE_IFC); + +#ifdef CONFIG_TARGET_P1010RDB_PB + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); +#endif + return 0; +} + +#ifndef CONFIG_XPL_BUILD +static int pin_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (argc < 2) + return CMD_RET_USAGE; + if (strcmp(argv[1], "ifc") == 0) + config_board_mux(MUX_TYPE_IFC); + else if (strcmp(argv[1], "sdhc") == 0) + config_board_mux(MUX_TYPE_SDHC); + else + return CMD_RET_USAGE; + return 0; +} + +U_BOOT_CMD( + mux, 2, 0, pin_mux_cmd, + "configure multiplexing pin for IFC/SDHC bus in runtime", + "bus_type (e.g. mux sdhc)" +); +#endif diff --git a/board/nxp/p1010rdb/spl.c b/board/nxp/p1010rdb/spl.c new file mode 100644 index 00000000000..fc26cef2cc8 --- /dev/null +++ b/board/nxp/p1010rdb/spl.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright 2013 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/spl.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L2_SIZE; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; + + console_init_f(); + + /* Clock configuration to access CPLD using IFC(GPCM) */ + setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); + +#ifdef CONFIG_TARGET_P1010RDB_PB + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); +#endif + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + gd->bus_clk = get_board_sys_clk() * plat_ratio; + + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, + gd->bus_clk / 16 / CONFIG_BAUDRATE); + +#ifdef CONFIG_SPL_MMC_BOOT + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI Flash boot...\n"); +#endif + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_VAL(RELOC_STACK), 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *)CONFIG_VAL(GD_ADDR); + struct bd_info *bd; + + memset(gd, 0, sizeof(gd_t)); + bd = (struct bd_info *)(CONFIG_VAL(GD_ADDR) + sizeof(gd_t)); + memset(bd, 0, sizeof(struct bd_info)); + gd->bd = bd; + + arch_cpu_init(); + get_clocks(); + mem_malloc_init(CONFIG_VAL(RELOC_MALLOC_ADDR), + CONFIG_VAL(RELOC_MALLOC_SIZE)); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; + +#ifndef CONFIG_SPL_NAND_BOOT + env_init(); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)SPL_ENV_ADDR); + gd->env_addr = (ulong)(SPL_ENV_ADDR); + gd->env_valid = ENV_VALID; +#else + env_relocate(); +#endif + + i2c_init_all(); + + dram_init(); +#ifdef CONFIG_SPL_NAND_BOOT + puts("\nTertiary program loader running in sram..."); +#else + puts("\nSecond program loader running in sram..."); +#endif + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + fsl_spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/nxp/p1010rdb/spl_minimal.c b/board/nxp/p1010rdb/spl_minimal.c new file mode 100644 index 00000000000..8cd79c6fb5f --- /dev/null +++ b/board/nxp/p1010rdb/spl_minimal.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + +#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM); +#endif + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + gd->bus_clk = get_board_sys_clk() * plat_ratio; + + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, + gd->bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot... "); + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + puts("\nSecond program loader running in sram..."); + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, '\r'); + + ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} diff --git a/board/nxp/p1010rdb/tlb.c b/board/nxp/p1010rdb/tlb.c new file mode 100644 index 00000000000..aa130ccf78b --- /dev/null +++ b/board/nxp/p1010rdb/tlb.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + */ + +#include +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#ifdef CONFIG_SPL_NAND_BOOT + SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +#ifndef CONFIG_XPL_BUILD + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_16M, 1), + + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE + 0x1000000, + CFG_SYS_FLASH_BASE_PHYS + 0x1000000, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 3, BOOKE_PAGESZ_16M, 1), + +#ifdef CONFIG_PCI + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256K, 1), +#endif +#endif + + /* *I*G - Board CPLD */ + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_1M, 1), + +#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR) + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 8, BOOKE_PAGESZ_1G, 1), +#endif + +#ifdef CFG_SYS_INIT_L2_ADDR + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR, CFG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1) +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/nxp/p1_p2_rdb_pc/Kconfig b/board/nxp/p1_p2_rdb_pc/Kconfig new file mode 100644 index 00000000000..2ab46d99434 --- /dev/null +++ b/board/nxp/p1_p2_rdb_pc/Kconfig @@ -0,0 +1,14 @@ +if TARGET_P1020RDB_PC || \ + TARGET_P1020RDB_PD || \ + TARGET_P2020RDB + +config SYS_BOARD + default "p1_p2_rdb_pc" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "p1_p2_rdb_pc" + +endif diff --git a/board/nxp/p1_p2_rdb_pc/MAINTAINERS b/board/nxp/p1_p2_rdb_pc/MAINTAINERS new file mode 100644 index 00000000000..1ce3501f379 --- /dev/null +++ b/board/nxp/p1_p2_rdb_pc/MAINTAINERS @@ -0,0 +1,25 @@ +P1_P2_RDB_PC BOARD +M: Priyanka Jain +S: Maintained +F: board/nxp/p1_p2_rdb_pc/ +F: include/configs/p1_p2_rdb_pc.h +F: configs/P1020RDB-PC_defconfig +F: configs/P1020RDB-PC_36BIT_defconfig +F: configs/P1020RDB-PC_36BIT_NAND_defconfig +F: configs/P1020RDB-PC_36BIT_SDCARD_defconfig +F: configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +F: configs/P1020RDB-PC_NAND_defconfig +F: configs/P1020RDB-PC_SDCARD_defconfig +F: configs/P1020RDB-PC_SPIFLASH_defconfig +F: configs/P1020RDB-PD_defconfig +F: configs/P1020RDB-PD_NAND_defconfig +F: configs/P1020RDB-PD_SDCARD_defconfig +F: configs/P1020RDB-PD_SPIFLASH_defconfig +F: configs/P2020RDB-PC_defconfig +F: configs/P2020RDB-PC_36BIT_defconfig +F: configs/P2020RDB-PC_36BIT_NAND_defconfig +F: configs/P2020RDB-PC_36BIT_SDCARD_defconfig +F: configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +F: configs/P2020RDB-PC_NAND_defconfig +F: configs/P2020RDB-PC_SDCARD_defconfig +F: configs/P2020RDB-PC_SPIFLASH_defconfig diff --git a/board/nxp/p1_p2_rdb_pc/Makefile b/board/nxp/p1_p2_rdb_pc/Makefile new file mode 100644 index 00000000000..8c13813e3b0 --- /dev/null +++ b/board/nxp/p1_p2_rdb_pc/Makefile @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2010-2011 Freescale Semiconductor, Inc. + +MINIMAL= + +ifdef CONFIG_XPL_BUILD +ifndef CONFIG_TPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif +endif + +ifdef MINIMAL +obj-y += spl_minimal.o +else +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +endif +obj-y += p1_p2_rdb_pc.o +obj-y += ddr.o +endif + +obj-y += law.o +obj-y += tlb.o diff --git a/board/nxp/p1_p2_rdb_pc/README b/board/nxp/p1_p2_rdb_pc/README new file mode 100644 index 00000000000..fd849bfc29a --- /dev/null +++ b/board/nxp/p1_p2_rdb_pc/README @@ -0,0 +1,64 @@ +Overview +-------- +P1_P2_RDB_PC represents a set of boards including + P1020MSBG-PC + P1020RDB-PC + P1020RDB-PD + P1021RDB-PC + P1024RDB + P2020RDB-PC + +They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC +has 64-bit DDR. All others have 32-bit DDR. + +Key features on these boards include: + * DDR3 + * NOR flash + * NAND flash (on RDB's only) + * SPI flash (on RDB's only) + * SDHC/MMC card slot + * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB) + * PCIE slot and mini-PCIE slots + +As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM +is used to store SPD data. In case of absent or corrupted SPD, falling back +to timing data embedded in the source code will be used. Raw timing data is +extracted from DDR chip datasheet. Different speeds of DDR are supported with +this approach. ODT option is forced to fit this set of boards, again because +they don't have regular DIMMs. + +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification +for writing timing. + +VSC firmware Address is defined by default in config file for eTSEC1. + +SD width is based off DIP switch. DIP switch is detected on the +board by reading i2c bus and setting the appropriate mux values. + +Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have +pins multiplexing. QE function needs to be disabled to access Nor Flash and +CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe" +in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to +enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below + +'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD. +'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD. + +Device tree support and how to enable it for different configs +-------------------------------------------------------------- +Device tree support is available for p1020rdb and p2020rdb for below mentioned boot, +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. CONFIG_DEFAULT_DEVICE_TREE="p1020rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CFG_RESET_VECTOR_ADDRESS - 0xffc + +If device tree support is enabled in defconfig, +1. use 'u-boot.bin' for NOR boot. +2. use 'u-boot-with-spl.bin' for other boot. diff --git a/board/nxp/p1_p2_rdb_pc/ddr.c b/board/nxp/p1_p2_rdb_pc/ddr.c new file mode 100644 index 00000000000..8622a5a610a --- /dev/null +++ b/board/nxp/p1_p2_rdb_pc/ddr.c @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SYS_DDR_RAW_TIMING +#if defined(CONFIG_P1020RDB_PROTO) +/* Micron MT41J256M8_187E */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 1870, + .caslat_x = 0x1e << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 7800000, + .tfaw_ps = 37500, +}; +#elif defined(CONFIG_TARGET_P2020RDB) +/* Micron MT41J128M16_15E */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 64, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 14, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 1500, + .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */ + .taa_ps = 13500, + .twr_ps = 15000, + .trcd_ps = 13500, + .trrd_ps = 6000, + .trp_ps = 13500, + .tras_ps = 36000, + .trc_ps = 49500, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 7800000, + .tfaw_ps = 30000, +}; +#elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) +/* Micron MT41J512M8_187E */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 2, + .rank_density = 1073741824u, + .capacity = 2147483648u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 1870, + .caslat_x = 0x1e << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 7800000, + .tfaw_ps = 37500, +}; +#elif defined(CONFIG_TARGET_P1020RDB_PC) +/* + * Samsung K4B2G0846C-HCF8 + * The following timing are for "downshift" + * i.e. to use CL9 part as CL7 + * otherwise, tAA, tRCD, tRP will be 13500ps + * and tRC will be 49500ps + */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 1875, + .caslat_x = 0x1e << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 7800000, + .tfaw_ps = 37500, +}; +#elif defined(CONFIG_TARGET_P1024RDB) +/* + * Samsung K4B2G0846C-HCH9 + * The following timing are for "downshift" + * i.e. to use CL9 part as CL7 + * otherwise, tAA, tRCD, tRP will be 13500ps + * and tRC will be 49500ps + */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 1500, + .caslat_x = 0x3e << 4, /* 5,6,7,8,9 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 6000, + .trp_ps = 13125, + .tras_ps = 36000, + .trc_ps = 49125, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 7800000, + .tfaw_ps = 30000, +}; +#else +#error Missing raw timing data for this board +#endif + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR on board"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} +#endif /* CONFIG_SYS_DDR_RAW_TIMING */ + +#ifdef CFG_SYS_DDR_CS0_BNDS +/* Fixed sdram init -- doesn't use serial presence detect. */ +phys_size_t fixed_sdram(void) +{ + sys_info_t sysinfo; + char buf[32]; + size_t ddr_size; + fsl_ddr_cfg_regs_t ddr_cfg_regs = { + .cs[0].bnds = CFG_SYS_DDR_CS0_BNDS, + .cs[0].config = CFG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CFG_SYS_DDR_CS0_CONFIG_2, +#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 + .cs[1].bnds = CFG_SYS_DDR_CS1_BNDS, + .cs[1].config = CFG_SYS_DDR_CS1_CONFIG, + .cs[1].config_2 = CFG_SYS_DDR_CS1_CONFIG_2, +#endif + .timing_cfg_3 = CFG_SYS_DDR_TIMING_3, + .timing_cfg_0 = CFG_SYS_DDR_TIMING_0, + .timing_cfg_1 = CFG_SYS_DDR_TIMING_1, + .timing_cfg_2 = CFG_SYS_DDR_TIMING_2, + .ddr_sdram_cfg = CFG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CFG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CFG_SYS_DDR_MODE_1, + .ddr_sdram_mode_2 = CFG_SYS_DDR_MODE_2, + .ddr_sdram_md_cntl = CFG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CFG_SYS_DDR_INTERVAL, + .ddr_data_init = 0xdeadbeef, /* Poison value */ + .ddr_sdram_clk_cntl = CFG_SYS_DDR_CLK_CTRL, + .ddr_init_addr = CFG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CFG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CFG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CFG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CFG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CFG_SYS_DDR_WRLVL_CONTROL, + .ddr_sr_cntr = CFG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CFG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CFG_SYS_DDR_RCW_2 + }; + + get_sys_info(&sysinfo); + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, sysinfo.freq_ddrbus)); + + ddr_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; + + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); + + if (set_ddr_laws(CFG_SYS_DDR_SDRAM_BASE, + ddr_size, LAW_TRGT_IF_DDR_1) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + }; + + return ddr_size; +} +#endif + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + int i; + popts->clk_adjust = 6; + popts->cpo_override = 0x1f; + popts->write_data_delay = 2; + popts->half_strength_driver_enable = 1; + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x8; + popts->trwt_override = 1; + popts->trwt = 0; + + if (pdimm->primary_sdram_width == 64) + popts->data_bus_width = 0; + else if (pdimm->primary_sdram_width == 32) + popts->data_bus_width = 1; + else + printf("Error in DDR bus width configuration!\n"); + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; + } +} diff --git a/board/nxp/p1_p2_rdb_pc/law.c b/board/nxp/p1_p2_rdb_pc/law.c new file mode 100644 index 00000000000..49594070b83 --- /dev/null +++ b/board/nxp/p1_p2_rdb_pc/law.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#ifdef CONFIG_VSC7385_ENET + SET_LAW(CFG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#endif + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/nxp/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/nxp/p1_p2_rdb_pc/p1_p2_rdb_pc.c new file mode 100644 index 00000000000..a19a98dd0d1 --- /dev/null +++ b/board/nxp/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -0,0 +1,481 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_QE + +#define GPIO_GETH_SW_PORT 1 +#define GPIO_GETH_SW_PIN 29 +#define GPIO_GETH_SW_DATA (1 << (31 - GPIO_GETH_SW_PIN)) + +#define GPIO_SLIC_PORT 1 +#define GPIO_SLIC_PIN 30 +#define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN)) + +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* GPIO */ + {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */ + {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */ + {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */ + {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */ + {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ +}; +#endif + +struct cpld_data { + u8 cpld_rev_major; + u8 pcba_rev; + u8 wd_cfg; + u8 rst_bps_sw; + u8 load_default_n; + u8 rst_bps_wd; + u8 bypass_enable; + u8 bps_led; + u8 status_led; /* offset: 0x8 */ + u8 fxo_led; /* offset: 0x9 */ + u8 fxs_led; /* offset: 0xa */ + u8 rev4[2]; + u8 system_rst; /* offset: 0xd */ + u8 bps_out; + u8 rev5[3]; + u8 cpld_rev_minor; +}; + +#define CPLD_WD_CFG 0x03 +#define CPLD_RST_BSW 0x00 +#define CPLD_RST_BWD 0x00 +#define CPLD_BYPASS_EN 0x03 +#define CPLD_STATUS_LED 0x01 +#define CPLD_FXO_LED 0x01 +#define CPLD_FXS_LED 0x0F +#define CPLD_SYS_RST 0x00 + +void board_reset_prepare(void) +{ + /* + * During reset preparation, turn off external watchdog. + * This ensures that external watchdog does not trigger + * another reset or possible infinite reset loop. + */ + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); + out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); + in_8(&cpld_data->wd_cfg); /* Read back to sync write */ +} + +void board_reset_last(void) +{ + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); + out_8(&cpld_data->system_rst, 1); +} + +void board_cpld_init(void) +{ + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); + u8 prev_wd_cfg = in_8(&cpld_data->wd_cfg); + + out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); + out_8(&cpld_data->status_led, CPLD_STATUS_LED); + out_8(&cpld_data->fxo_led, CPLD_FXO_LED); + out_8(&cpld_data->fxs_led, CPLD_FXS_LED); + + /* + * CPLD's system reset register on P1/P2 RDB boards is not autocleared + * after flipping it. If this register is set to one then CPLD triggers + * reset of CPU in few ms. + * + * CPLD does not trigger reset of CPU for 100ms after the last reset. + * + * This means that trying to reset board via CPLD system reset register + * cause reboot loop. To prevent this reboot loop, the only workaround + * is to try to clear CPLD's system reset register as early as possible + * and it has to be done in 100ms since the last start of reset. + */ + out_8(&cpld_data->system_rst, CPLD_SYS_RST); + + /* + * If watchdog timer was already set to non-disabled value then it means + * that watchdog timer was already activated, has already expired and + * caused CPU reset. If this happened then due to CPLD firmware bug, + * writing to wd_cfg register has no effect and therefore it is not + * possible to reactivate watchdog timer again. Also if CPU was reset + * via watchdog then some peripherals like i2c do not work. Watchdog and + * i2c start working again after CPU reset via non-watchdog method. + * + * So in case watchdog timer register in CPLD was already enabled then + * disable it in CPLD and reset CPU which cause new boot. Watchdog timer + * is disabled few lines above, after reading CPLD previous value. + * This logic (disabling timer before reset) prevents reboot loop. + */ + if (prev_wd_cfg != CPLD_WD_CFG) { + eieio(); + do_reset(NULL, 0, 0, NULL); + while (1); /* do_reset() does not occur immediately */ + } +} + +void board_gpio_init(void) +{ +#ifdef CONFIG_QE + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); + + /* Enable VSC7385 switch */ + setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA); + + /* Enable SLIC */ + setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA); +#else + + ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); + + /* + * GPIO10 DDR Reset, open drain + * GPIO7 LOAD_DEFAULT_N Input + * GPIO11 WDI (watchdog input) + * GPIO12 Ethernet Switch Reset + * GPIO13 SLIC Reset + */ + + setbits_be32(&pgpio->gpdir, 0x02130000); +#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL) + /* init DDR3 reset signal */ + setbits_be32(&pgpio->gpdir, 0x00200000); + setbits_be32(&pgpio->gpodr, 0x00200000); + clrbits_be32(&pgpio->gpdat, 0x00200000); + udelay(1000); + setbits_be32(&pgpio->gpdat, 0x00200000); + udelay(1000); + clrbits_be32(&pgpio->gpdir, 0x00200000); +#endif + +#ifdef CONFIG_VSC7385_ENET + /* reset VSC7385 Switch */ + setbits_be32(&pgpio->gpdir, 0x00080000); + setbits_be32(&pgpio->gpdat, 0x00080000); +#endif + +#ifdef CFG_SLIC + /* reset SLIC */ + setbits_be32(&pgpio->gpdir, 0x00040000); + setbits_be32(&pgpio->gpdat, 0x00040000); +#endif +#endif +} + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_CD); +#ifndef SDHC_WP_IS_GPIO + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_WP); +#endif + clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV); + + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); +#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC) + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA); +#endif + + board_gpio_init(); + board_cpld_init(); + + return 0; +} + +#if defined(CONFIG_TARGET_P1020RDB_PC) +#define BOARD_NAME "P1020RDB-PC" +#elif defined(CONFIG_TARGET_P1020RDB_PD) +#define BOARD_NAME "P1020RDB-PD" +#elif defined(CONFIG_TARGET_P2020RDB) +#define BOARD_NAME "P2020RDB-PC" +#endif + +int checkboard_p1_p2(void) +{ + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + u8 in, out, invert, io_config, val; + int bus_num = CONFIG_SYS_SPD_BUS_NUM; + + /* FIXME: This should just use the model from the device tree or similar */ +#ifdef BOARD_NAME + printf("Board: %s ", BOARD_NAME); +#endif + + printf("CPLD: V%d.%d PCBA: V%d.0\n", + in_8(&cpld_data->cpld_rev_major) & 0x0F, + in_8(&cpld_data->cpld_rev_minor) & 0x0F, + in_8(&cpld_data->pcba_rev) & 0x0F); + + /* Initialize i2c early for rom_loc and flash bank information */ + #if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_PCA9557_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return 0; /* Don't want to hang() on this error */ + } + + if (dm_i2c_read(dev, 0, &in, 1) < 0 || + dm_i2c_read(dev, 1, &out, 1) < 0 || + dm_i2c_read(dev, 2, &invert, 1) < 0 || + dm_i2c_read(dev, 3, &io_config, 1) < 0) { + printf("Error reading i2c boot information!\n"); + return 0; /* Don't want to hang() on this error */ + } + #else /* Non DM I2C support - will be removed */ + i2c_set_bus_num(bus_num); + + if (i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 || + i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 || + i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 || + i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) { + printf("Error reading i2c boot information!\n"); + return 0; /* Don't want to hang() on this error */ + } + #endif + + val = ((in ^ invert) & io_config) | (out & (~io_config)); + + puts("rom_loc: "); + if (0) { +#ifdef __SW_BOOT_SD + } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) { + puts("sd"); +#endif +#ifdef __SW_BOOT_SD2 + } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD2) { + puts("sd"); +#endif +#ifdef __SW_BOOT_SPI + } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) { + puts("spi"); +#endif +#ifdef __SW_BOOT_NAND + } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) { + puts("nand"); +#endif +#ifdef __SW_BOOT_PCIE + } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) { + puts("pcie"); +#endif + } else { + if (val & 0x2) + puts("nor lower bank"); + else + puts("nor upper bank"); + } + puts("\n"); + + if (val & 0x1) { + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); + puts("SD/MMC : 8-bit Mode\n"); + puts("eSPI : Disabled\n"); + } else { + puts("SD/MMC : 4-bit Mode\n"); + puts("eSPI : Enabled\n"); + } + + return 0; +} + +#if !defined(CONFIG_TARGET_TURRIS_1X) +int checkboard(void) +{ + return checkboard_p1_p2(); +} +#endif + +int board_early_init_r(void) +{ + const unsigned int flashbase = CFG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); +#ifdef CONFIG_VSC7385_ENET + unsigned int vscfw_addr; + char *tmp; +#endif + + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */ + 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */ + +#ifdef CONFIG_VSC7385_ENET + /* If a VSC7385 microcode image is present, then upload it. */ + tmp = env_get("vscfw_addr"); + if (tmp) { + vscfw_addr = hextoul(tmp, NULL); + printf("uploading VSC7385 microcode from %x\n", vscfw_addr); + if (vsc7385_upload_firmware((void *)vscfw_addr, + CFG_VSC7385_IMAGE_SIZE)) + puts("Failure uploading VSC7385 microcode.\n"); + } else { + puts("No address specified for VSC7385 microcode.\n"); + } +#endif + return 0; +} + +__weak void p1_p2_rdb_pc_fix_fdt_model(void *blob) {} + +#if defined(CONFIG_OF_BOARD_SETUP) || defined(CONFIG_OF_BOARD_FIXUP) +static void fix_max6370_watchdog(void *blob) +{ + int off = fdt_node_offset_by_compatible(blob, -1, "maxim,max6370"); + ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); + u32 gpioval = in_be32(&pgpio->gpdat); + + /* + * Delete watchdog max6370 node in load_default mode (detected by + * GPIO7 - LOAD_DEFAULT_N) because CPLD in load_default mode ignores + * watchdog reset signal. CPLD in load_default mode does not reset + * board when watchdog triggers reset signal. + */ + if (!(gpioval & BIT(31-7)) && off >= 0) + fdt_del_node(blob, off); +} +#endif + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + phys_addr_t base; + phys_size_t size; +#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC) + const char *soc_usb_compat = "fsl-usb2-dr"; + int usb_err, usb1_off, usb2_off; +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) + int err; +#endif +#endif + + ft_cpu_setup(blob, bd); + + base = env_get_bootm_low(); + size = env_get_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_QE + do_fixup_by_compat(blob, "fsl,qe", "status", "okay", + sizeof("okay"), 0); +#endif + + p1_p2_rdb_pc_fix_fdt_model(blob); + fix_max6370_watchdog(blob); + +#if defined(CONFIG_HAS_FSL_DR_USB) + fsl_fdt_fixup_dr_usb(blob, bd); +#endif + +#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC) +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) + /* Delete eLBC node as it is muxed with USB2 controller */ + if (hwconfig("usb2")) { + const char *soc_elbc_compat = "fsl,p1020-elbc"; + int off = fdt_node_offset_by_compatible(blob, -1, + soc_elbc_compat); + if (off < 0) { + printf("WARNING: could not find compatible node %s\n", + soc_elbc_compat); + return off; + } + err = fdt_del_node(blob, off); + if (err < 0) { + printf("WARNING: could not remove %s\n", + soc_elbc_compat); + return err; + } + return 0; + } +#endif + +/* Delete USB2 node as it is muxed with eLBC */ + usb1_off = fdt_node_offset_by_compatible(blob, -1, + soc_usb_compat); + if (usb1_off < 0) { + printf("WARNING: could not find compatible node %s\n", + soc_usb_compat); + return usb1_off; + } + usb2_off = fdt_node_offset_by_compatible(blob, usb1_off, + soc_usb_compat); + if (usb2_off < 0) { + printf("WARNING: could not find compatible node %s\n", + soc_usb_compat); + return usb2_off; + } + usb_err = fdt_del_node(blob, usb2_off); + if (usb_err < 0) { + printf("WARNING: could not remove %s\n", soc_usb_compat); + return usb_err; + } +#endif + + return 0; +} +#endif + +#ifdef CONFIG_OF_BOARD_FIXUP +int board_fix_fdt(void *blob) +{ + p1_p2_rdb_pc_fix_fdt_model(blob); + fix_max6370_watchdog(blob); + return 0; +} +#endif diff --git a/board/nxp/p1_p2_rdb_pc/spl.c b/board/nxp/p1_p2_rdb_pc/spl.c new file mode 100644 index 00000000000..b07f481fbf9 --- /dev/null +++ b/board/nxp/p1_p2_rdb_pc/spl.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/spl.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L2_SIZE; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, bus_clk; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + + /* + * Call board_early_init_f() as early as possible as it workarounds + * reboot loop due to broken CPLD state machine for reset line. + */ + board_early_init_f(); + + console_init_f(); + + /* Set pmuxcr to allow both i2c1 and i2c2 */ + setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); + setbits_be32(&gur->pmuxcr, + in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); + + /* Read back the register to synchronize the write. */ + in_be32(&gur->pmuxcr); + +#ifdef CONFIG_SPL_SPI_BOOT + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); +#endif + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + bus_clk = get_board_sys_clk() * plat_ratio; + gd->bus_clk = bus_clk; + + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); +#ifdef CONFIG_SPL_MMC_BOOT + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI Flash boot...\n"); +#endif + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_VAL(RELOC_STACK), 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *)CONFIG_VAL(GD_ADDR); + struct bd_info *bd; + + memset(gd, 0, sizeof(gd_t)); + bd = (struct bd_info *)(CONFIG_VAL(GD_ADDR) + sizeof(gd_t)); + memset(bd, 0, sizeof(struct bd_info)); + gd->bd = bd; + + arch_cpu_init(); + get_clocks(); + mem_malloc_init(CONFIG_VAL(RELOC_MALLOC_ADDR), + CONFIG_VAL(RELOC_MALLOC_SIZE)); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; + +#ifdef CONFIG_SPL_ENV_SUPPORT +#ifndef CONFIG_SPL_NAND_BOOT + env_init(); +#endif +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif +#ifdef CONFIG_SPL_ENV_SUPPORT + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)SPL_ENV_ADDR); + gd->env_addr = (ulong)(SPL_ENV_ADDR); + gd->env_valid = ENV_VALID; +#else + env_relocate(); +#endif +#endif + +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) + i2c_init_all(); +#else + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + + dram_init(); +#ifdef CONFIG_SPL_NAND_BOOT + puts("Tertiary program loader running in sram..."); +#else + puts("Second program loader running in sram...\n"); +#endif + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + fsl_spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/nxp/p1_p2_rdb_pc/spl_minimal.c b/board/nxp/p1_p2_rdb_pc/spl_minimal.c new file mode 100644 index 00000000000..511bcf5506b --- /dev/null +++ b/board/nxp/p1_p2_rdb_pc/spl_minimal.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + +#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM); +#endif + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + gd->bus_clk = get_board_sys_clk() * plat_ratio; + + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, + gd->bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot... "); + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + puts("\nSecond program loader running in sram..."); + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, '\r'); + + ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} diff --git a/board/nxp/p1_p2_rdb_pc/tlb.c b/board/nxp/p1_p2_rdb_pc/tlb.c new file mode 100644 index 00000000000..f27821418eb --- /dev/null +++ b/board/nxp/p1_p2_rdb_pc/tlb.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + */ + +#include +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +#ifndef CONFIG_XPL_BUILD + /* W**G* - Flash/promjet, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_64M, 1), + +#ifdef CONFIG_PCI + /* *I*G* - PCI memory 1.5G */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O effective: 192K */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), +#endif + +#ifdef CONFIG_VSC7385_ENET + /* *I*G - VSC7385 Switch */ + SET_TLB_ENTRY(1, CFG_SYS_VSC7385_BASE, CFG_SYS_VSC7385_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_1M, 1), +#endif +#endif /* not SPL */ + + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_1M, 1), + +#ifdef CFG_SYS_NAND_BASE + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_1M, 1), +#endif + +#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR) + /* **M** - 1G DDR for eSDHC/eSPI/NAND boot */ + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 8, BOOKE_PAGESZ_1G, 1), + +#if defined(CONFIG_TARGET_P1020RDB_PD) + /* **M** - 2G DDR on P1020MBG, map the second 1G */ + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000, + CFG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 9, BOOKE_PAGESZ_1G, 1), +#endif +#endif /* RAMBOOT/SPL */ + +#ifdef CFG_SYS_INIT_L2_ADDR + /* ***G - L2SRAM */ + SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR, CFG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1), +#if CONFIG_SYS_L2_SIZE >= (256 << 10) + SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR + 0x40000, + CFG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 12, BOOKE_PAGESZ_256K, 1) +#endif +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/nxp/p2041rdb/Kconfig b/board/nxp/p2041rdb/Kconfig new file mode 100644 index 00000000000..47c93b6eb55 --- /dev/null +++ b/board/nxp/p2041rdb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_P2041RDB + +config SYS_BOARD + default "p2041rdb" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "P2041RDB" + +endif diff --git a/board/nxp/p2041rdb/MAINTAINERS b/board/nxp/p2041rdb/MAINTAINERS new file mode 100644 index 00000000000..f0d5c1192ac --- /dev/null +++ b/board/nxp/p2041rdb/MAINTAINERS @@ -0,0 +1,11 @@ +P2041RDB BOARD +M: Priyanka Jain +S: Maintained +F: board/nxp/p2041rdb/ +F: include/configs/P2041RDB.h +F: configs/P2041RDB_defconfig +F: configs/P2041RDB_NAND_defconfig +F: configs/P2041RDB_SDCARD_defconfig +F: configs/P2041RDB_SECURE_BOOT_defconfig +F: configs/P2041RDB_SPIFLASH_defconfig +F: configs/P2041RDB_SRIO_PCIE_BOOT_defconfig diff --git a/board/nxp/p2041rdb/Makefile b/board/nxp/p2041rdb/Makefile new file mode 100644 index 00000000000..ebd0982b5db --- /dev/null +++ b/board/nxp/p2041rdb/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2011 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y += p2041rdb.o +obj-y += cpld.o +obj-y += ddr.o +obj-y += eth.o diff --git a/board/nxp/p2041rdb/README b/board/nxp/p2041rdb/README new file mode 100644 index 00000000000..ae770277372 --- /dev/null +++ b/board/nxp/p2041rdb/README @@ -0,0 +1,138 @@ +Overview +========= +The P2041 Processor combines four Power Architecture processor cores +with high-performance datapath acceleration architecture(DPAA), CoreNet +fabric infrastructure, as well as network and peripheral bus interfaces +required for networking, telecom/datacom, wireless infrastructure, and +military/aerospace applications. + +P2041RDB board is a quad core platform supporting the P2041 processor +of QorIQ DPAA series. + +Boot from NOR flash +=================== +1. Build image + make P2041RDB_config + make all + +2. Program image + => tftp 1000000 u-boot.bin + => protect off all + => erase eff40000 efffffff + => cp.b 1000000 eff40000 c0000 + +3. Program RCW + => tftp 1000000 rcw.bin + => protect off all + => erase e8000000 e801ffff + => cp.b 1000000 e8000000 50 + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => protect off all + => erase eff00000 eff3ffff + => cp.b 1000000 eff00000 2000 + +5. Change DIP-switch + SW1[1-5] = 10110 + Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SDCard +=================== +1. Build image + make P2041RDB_SDCARD_config + make all + +2. Generate PBL imge + Use PE tool to produce a image used to be programed to + SDCard which contains RCW and U-Boot image. + +3. Program the PBL image to SDCard + => tftp 1000000 pbl_sd.bin + => mmcinfo + => mmc write 1000000 8 672 + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => mmc write 1000000 690 10 + +5. Change DIP-switch + SW1[1-5] = 01100 + Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SPI flash +=================== +1. Build image + make P2041RDB_SPIFLASH_config + make all + +2. Generate PBL imge + Use PE tool to produce a image used to be programed to + SPI flash which contains RCW and U-Boot image. + +3. Program the PBL image to SPI flash + => tftp 1000000 pbl_spi.bin + => spi probe 0 + => sf erase 0 100000 + => sf write 1000000 0 $filesize + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => sf erase 110000 10000 + => sf write 1000000 110000 $filesize + +5. Change DIP-switch + SW1[1-5] = 10100 + Note: 1 stands for 'on', 0 stands for 'off' + +Device tree support and how to enable it for different configs +-------------------------------------------------------------- +Device tree support is available for p2041rdb for below mentioned boot, +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CFG_RESET_VECTOR_ADDRESS - 0xffc + +CPLD command +============ +The CPLD is used to control the power sequence and some serdes lane +mux function. + +cpld reset - hard reset to default bank +cpld reset altbank - reset to alternate bank +cpld lane_mux - set multiplexed lane pin + lane 6: 0 -> slot1 (Default) + 1 -> SGMII + lane a: 0 -> slot2 (Default) + 1 -> AURORA + lane c: 0 -> slot2 (Default) + 1 -> SATA0 + lane d: 0 -> slot2 (Default) + 1 -> SATA1 + +Using the Device Tree Source File +================================= +To create the DTB (Device Tree Binary) image file, use a command +similar to this: + dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb + +Or use the following command: + {linux-2.6}/make p2041rdb.dtb ARCH=powerpc + +then the dtb file will be generated under the following directory: + {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb + +Booting Linux +============= +Place a linux uImage in the TFTP disk area. + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp 3000000 p2041rdb.dtb + bootm 1000000 2000000 3000000 diff --git a/board/nxp/p2041rdb/cpld.c b/board/nxp/p2041rdb/cpld.c new file mode 100644 index 00000000000..2bba377d4d4 --- /dev/null +++ b/board/nxp/p2041rdb/cpld.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * Copyright 2011 Freescale Semiconductor + * Author: Mingkai Hu + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CPLD_BASE - The virtual address of the base of the CPLD register map + */ + +#include +#include +#include + +#include "cpld.h" + +static u8 __cpld_read(unsigned int reg) +{ + void *p = (void *)CPLD_BASE; + + return in_8(p + reg); +} +u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read"))); + +static void __cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CPLD_BASE; + + out_8(p + reg, value); +} +void cpld_write(unsigned int reg, u8 value) + __attribute__((weak, alias("__cpld_write"))); + +/* + * Reset the board. This honors the por_cfg registers. + */ +void __cpld_reset(void) +{ + CPLD_WRITE(system_rst, 1); +} +void cpld_reset(void) __attribute__((weak, alias("__cpld_reset"))); + +/** + * Set the boot bank to the alternate bank + */ +void __cpld_set_altbank(void) +{ + u8 reg5 = CPLD_READ(sw_ctl_on); + + CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE); + CPLD_WRITE(fbank_sel, 1); + CPLD_WRITE(system_rst, 1); +} +void cpld_set_altbank(void) + __attribute__((weak, alias("__cpld_set_altbank"))); + +/** + * Set the boot bank to the default bank + */ +void __cpld_set_defbank(void) +{ + CPLD_WRITE(system_rst_default, 1); +} +void cpld_set_defbank(void) + __attribute__((weak, alias("__cpld_set_defbank"))); + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); + printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); + printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver)); + printf("system_rst = 0x%02x\n", CPLD_READ(system_rst)); + printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on)); + printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg)); + printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe)); + printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel)); + printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk)); + printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk)); + printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel)); + printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux)); + printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2))); + putc('\n'); +} +#endif + +int cpld_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); + } else if (strcmp(argv[1], "lane_mux") == 0) { + u32 lane = hextoul(argv[2], NULL); + u8 val = (u8)hextoul(argv[3], NULL); + u8 reg = CPLD_READ(serdes_mux); + + switch (lane) { + case 0x6: + reg &= ~SERDES_MUX_LANE_6_MASK; + reg |= val << SERDES_MUX_LANE_6_SHIFT; + break; + case 0xa: + reg &= ~SERDES_MUX_LANE_A_MASK; + reg |= val << SERDES_MUX_LANE_A_SHIFT; + break; + case 0xc: + reg &= ~SERDES_MUX_LANE_C_MASK; + reg |= val << SERDES_MUX_LANE_C_SHIFT; + break; + case 0xd: + reg &= ~SERDES_MUX_LANE_D_MASK; + reg |= val << SERDES_MUX_LANE_D_SHIFT; + break; + default: + printf("Invalid value\n"); + break; + } + + CPLD_WRITE(serdes_mux, reg); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd, + "Reset the board or pin mulexing selection using the CPLD sequencer", + "reset - hard reset to default bank\n" + "cpld_cmd reset altbank - reset to alternate bank\n" + "cpld_cmd lane_mux - set multiplexed lane pin\n" + " lane 6: 0 -> slot1\n" + " 1 -> SGMII (Default)\n" + " lane a: 0 -> slot2\n" + " 1 -> AURORA (Default)\n" + " lane c: 0 -> slot2\n" + " 1 -> SATA0 (Default)\n" + " lane d: 0 -> slot2\n" + " 1 -> SATA1 (Default)\n" +#ifdef DEBUG + "cpld_cmd dump - display the CPLD registers\n" +#endif + ); diff --git a/board/nxp/p2041rdb/cpld.h b/board/nxp/p2041rdb/cpld.h new file mode 100644 index 00000000000..8c90c1ccf32 --- /dev/null +++ b/board/nxp/p2041rdb/cpld.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/** + * Copyright 2011 Freescale Semiconductor + * Author: Mingkai Hu + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +typedef struct cpld_data { + u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ + u8 pcba_ver; /* 0x2 - PCBA Revision Register */ + u8 system_rst; /* 0x3 - system reset register */ + u8 res0; /* 0x4 - not used */ + u8 sw_ctl_on; /* 0x5 - Switch Control Enable Register */ + u8 por_cfg; /* 0x6 - POR Control Register */ + u8 switch_strobe; /* 0x7 - Multiplexed pin Select Register */ + u8 jtag_sel; /* 0x8 - JTAG or AURORA Selection */ + u8 sdbank1_clk; /* 0x9 - SerDes Bank1 Reference clock */ + u8 sdbank2_clk; /* 0xa - SerDes Bank2 Reference clock */ + u8 fbank_sel; /* 0xb - Flash bank selection */ + u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */ + u8 sw[1]; /* 0xd - SW2 Status */ + u8 system_rst_default; /* 0xe - system reset to default register */ + u8 sysclk_sw1; /* 0xf - sysclk configuration register */ +} __attribute__ ((packed)) cpld_data_t; + +#define SERDES_MUX_LANE_6_MASK 0x2 +#define SERDES_MUX_LANE_6_SHIFT 1 +#define SERDES_MUX_LANE_A_MASK 0x1 +#define SERDES_MUX_LANE_A_SHIFT 0 +#define SERDES_MUX_LANE_C_MASK 0x4 +#define SERDES_MUX_LANE_C_SHIFT 2 +#define SERDES_MUX_LANE_D_MASK 0x8 +#define SERDES_MUX_LANE_D_SHIFT 3 +#define CPLD_SWITCH_BANK_ENABLE 0x40 +#define CPLD_SYSCLK_83 0x1 /* system clock 83.3MHz */ +#define CPLD_SYSCLK_100 0x2 /* system clock 100MHz */ + +/* Pointer to the CPLD register set */ +#define cpld ((cpld_data_t *)CPLD_BASE) + +/* The CPLD SW register that corresponds to board switch X, where x >= 1 */ +#define CPLD_SW(x) (cpld->sw[(x) - 2]) + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg)) +#define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value) diff --git a/board/nxp/p2041rdb/ddr.c b/board/nxp/p2041rdb/ddr.c new file mode 100644 index 00000000000..b8b765a85ef --- /dev/null +++ b/board/nxp/p2041rdb/ddr.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2011 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 clk_adjust; + u32 wrlvl_start; + u32 cpo; + u32 write_data_delay; + u32 force_2t; +}; + +/* + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + * + * ranges for parameters: + * wr_data_delay = 0-6 + * clk adjust = 0-8 + * cpo 2-0x1E (30) + */ +static const struct board_specific_parameters dimm0[] = { + /* + * memory controller 0 + * num| hi| clk| wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | delay| + */ + {2, 750, 3, 5, 0xff, 2, 0}, + {2, 1250, 4, 6, 0xff, 2, 0}, + {2, 1350, 5, 7, 0xff, 2, 0}, + {2, 1666, 5, 8, 0xff, 2, 0}, + {} +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = dimm0; + + /* + * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->twot_en = pbsp->force_2t; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found " + "for data rate %lu MT/s!\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->twot_en = pbsp_highest->force_2t; + } else { + panic("DIMM is not supported by this board"); + } + +found: + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* Write leveling override */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* Rtt and Rtt_WR override */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 60 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN; +} + +int dram_init(void) +{ + phys_size_t dram_size = 0; + + puts("Initializing...."); + + if (fsl_use_spd()) { + puts("using SPD\n"); + dram_size = fsl_ddr_sdram(); + } else { + puts("no SPD and fixed parameters\n"); + return -ENXIO; + } + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + debug(" DDR: "); + gd->ram_size = dram_size; + + return 0; +} diff --git a/board/nxp/p2041rdb/eth.c b/board/nxp/p2041rdb/eth.c new file mode 100644 index 00000000000..65850866777 --- /dev/null +++ b/board/nxp/p2041rdb/eth.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Author: Mingkai Hu + */ + +/* + * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs + * are provided by the three on-board PHY or by the standard Freescale + * four-port SGMII riser card. We need to change the phy-handle in the + * kernel dts file to point to the correct PHY according to serdes mux + * and serdes protocol selection. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cpld.h" +#include "../common/fman.h" + +#ifdef CONFIG_FMAN_ENET +/* + * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means + * that the mapping must be determined dynamically, or that the lane maps to + * something other than a board slot + */ +static u8 lane_to_slot[] = { + 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0 +}; + +static int riser_phy_addr[] = { + CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, + CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, + CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, + CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, +}; + +/* + * Initialize the lane_to_slot[] array. + * + * On the P2040RDB board the mapping is controlled by CPLD register. + */ +static void initialize_lane_to_slot(void) +{ + u8 mux = CPLD_READ(serdes_mux); + + lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1; + lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2; + lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2; + lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2; +} + +/* + * Given the following ... + * + * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' + * compatible string and 'addr' physical address) + * + * 2) An Fman port + * + * ... update the phy-handle property of the Ethernet node to point to the + * right PHY. This assumes that we already know the PHY for each port. + * + * The offset of the Fman Ethernet node is also passed in for convenience, but + * it is not used, and we recalculate the offset anyway. + * + * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. + * Inside the Fman, "ports" are things that connect to MACs. We only call them + * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs + * and ports are the same thing. + * + */ +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + phy_interface_t intf = fm_info_get_enet_if(port); + char phy[16]; + int lane; + u8 slot; + + switch (intf) { + /* The RGMII PHY is identified by the MAC connected to it */ + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: + sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1); + fdt_set_phy_handle(fdt, compat, addr, phy); + break; + /* The SGMII PHY is identified by the MAC connected to it */ + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); + if (lane < 0) + return; + slot = lane_to_slot[lane]; + if (slot) { + sprintf(phy, "phy_sgmii_%x", + CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + + (port - FM1_DTSEC1)); + fdt_set_phy_handle(fdt, compat, addr, phy); + } else { + sprintf(phy, "phy_sgmii_%x", + CFG_SYS_FM1_DTSEC1_PHY_ADDR + + (port - FM1_DTSEC1)); + fdt_set_phy_handle(fdt, compat, addr, phy); + } + break; + case PHY_INTERFACE_MODE_XGMII: + /* XAUI */ + lane = serdes_get_first_lane(XAUI_FM1); + if (lane >= 0) { + /* The XAUI PHY is identified by the slot */ + sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); + fdt_set_phy_handle(fdt, compat, addr, phy); + } + break; + default: + break; + } +} +#endif /* #ifdef CONFIG_FMAN_ENET */ + +int board_eth_init(struct bd_info *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct fsl_pq_mdio_info dtsec_mdio_info; + struct tgec_mdio_info tgec_mdio_info; + unsigned int i, slot; + int lane; + + printf("Initializing Fman\n"); + + initialize_lane_to_slot(); + + dtsec_mdio_info.regs = + (struct tsec_mii_mng *)CFG_SYS_FM1_DTSEC1_MDIO_ADDR; + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fsl_pq_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct tgec_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the real 10G MDIO bus */ + fm_tgec_mdio_init(bis, &tgec_mdio_info); + + /* + * Program the three on-board SGMII PHY addresses. If the SGMII Riser + * card used, we'll override the PHY address later. For any DTSEC that + * is RGMII, we'll also override its PHY address later. We assume that + * DTSEC4 and DTSEC5 are used for RGMII. + */ + fm_info_set_phy_address(FM1_DTSEC1, CFG_SYS_FM1_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, CFG_SYS_FM1_DTSEC2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, CFG_SYS_FM1_DTSEC3_PHY_ADDR); + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + if (slot) + fm_info_set_phy_address(i, riser_phy_addr[i]); + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: + /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ + fm_info_set_phy_address(i, i == FM1_DTSEC5 ? + CFG_SYS_FM1_DTSEC5_PHY_ADDR : + CFG_SYS_FM1_DTSEC4_PHY_ADDR); + break; + default: + printf("Fman1: DTSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + break; + } + + fm_info_set_mdio(i, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + } + + lane = serdes_get_first_lane(XAUI_FM1); + if (lane >= 0) { + slot = lane_to_slot[lane]; + if (slot) + fm_info_set_phy_address(FM1_10GEC1, + CFG_SYS_FM1_10GEC1_PHY_ADDR); + } + + fm_info_set_mdio(FM1_10GEC1, + miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} diff --git a/board/nxp/p2041rdb/p2041rdb.c b/board/nxp/p2041rdb/p2041rdb.c new file mode 100644 index 00000000000..d5b71f78430 --- /dev/null +++ b/board/nxp/p2041rdb/p2041rdb.c @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2011,2012 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern void pci_of_setup(void *blob, struct bd_info *bd); + +#include "cpld.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + u8 sw; + struct cpu_type *cpu = gd->arch.cpu; + unsigned int i; + + printf("Board: %sRDB, ", cpu->name); + printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver), + CPLD_READ(cpld_ver_sub)); + + sw = CPLD_READ(fbank_sel); + printf("vBank: %d\n", sw & 0x1); + + /* + * Display the actual SERDES reference clocks as configured by the + * dip switches on the board. Note that the SWx registers could + * technically be set to force the reference clocks to match the + * values that the SERDES expects (or vice versa). For now, however, + * we just display both values and hope the user notices when they + * don't match. + */ + puts("SERDES Reference Clocks: "); + sw = in_8(&CPLD_SW(2)) >> 2; + for (i = 0; i < 2; i++) { + static const char * const freq[][3] = {{"0", "100", "125"}, + {"100", "156.25", "125"} + }; + unsigned int clock = (sw >> (2 * i)) & 3; + + printf("Bank%u=%sMhz ", i+1, freq[i][clock]); + } + puts("\n"); + + return 0; +} + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + + /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */ + setbits_be32(&gur->ddrclkdr, 0x000f000f); + + return 0; +} + +#define CPLD_LANE_A_SEL 0x1 +#define CPLD_LANE_G_SEL 0x2 +#define CPLD_LANE_C_SEL 0x4 +#define CPLD_LANE_D_SEL 0x8 + +void board_config_lanes_mux(void) +{ + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + int srds_prtcl = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + u8 mux = 0; + switch (srds_prtcl) { + case 0x2: + case 0x5: + case 0x9: + case 0xa: + case 0xf: + break; + case 0x8: + mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; + break; + case 0x14: + mux |= CPLD_LANE_A_SEL; + break; + case 0x17: + mux |= CPLD_LANE_G_SEL; + break; + case 0x16: + case 0x19: + case 0x1a: + mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; + break; + case 0x1c: + mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL; + break; + default: + printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl); + break; + } + CPLD_WRITE(serdes_mux, mux); +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CFG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + board_config_lanes_mux(); + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = CPLD_READ(sysclk_sw1); + + switch (sysclk_conf & 0x7) { + case CPLD_SYSCLK_83: + return 83333333; + case CPLD_SYSCLK_100: + return 100000000; + default: + return 66666666; + } +} + +#define NUM_SRDS_BANKS 2 + +int misc_init_r(void) +{ + serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; + u32 actual[NUM_SRDS_BANKS]; + unsigned int i; + u8 sw; + static const int freq[][3] = { + {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125}, + {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25, + SRDS_PLLCR0_RFCK_SEL_125} + }; + + sw = in_8(&CPLD_SW(2)) >> 2; + for (i = 0; i < NUM_SRDS_BANKS; i++) { + unsigned int clock = (sw >> (2 * i)) & 3; + if (clock == 0x3) { + printf("Warning: SDREFCLK%u switch setting of '11' is " + "unsupported\n", i + 1); + break; + } + if (i == 0 && clock == 0) + puts("Warning: SDREFCLK1 switch setting of" + "'00' is unsupported\n"); + else + actual[i] = freq[i][clock]; + + /* + * PC board uses a different CPLD with PB board, this CPLD + * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB + * board has cpld_ver_sub = 0, and pcba_ver = 4. + */ + if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) && + (CPLD_READ(pcba_ver) == 5)) { + /* PC board bank2 frequency */ + actual[i] = freq[i-1][clock]; + } + } + + for (i = 0; i < NUM_SRDS_BANKS; i++) { + u32 expected = in_be32(®s->bank[i].pllcr0); + expected &= SRDS_PLLCR0_RFCK_SEL_MASK; + if (expected != actual[i]) { + printf("Warning: SERDES bank %u expects reference clock" + " %sMHz, but actual is %sMHz\n", i + 1, + serdes_clock_to_string(expected), + serdes_clock_to_string(actual[i])); + } + } + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = env_get_bootm_low(); + size = env_get_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#if defined(CONFIG_HAS_FSL_DR_USB) + fsl_fdt_fixup_dr_usb(blob, bd); +#endif + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); +#ifdef CONFIG_SYS_DPAA_FMAN +#ifndef CONFIG_DM_ETH + fdt_fixup_fman_ethernet(blob); +#endif +#endif + + return 0; +} diff --git a/board/nxp/p2041rdb/pbi.cfg b/board/nxp/p2041rdb/pbi.cfg new file mode 100644 index 00000000000..75dfc321626 --- /dev/null +++ b/board/nxp/p2041rdb/pbi.cfg @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2012 Freescale Semiconductor, Inc. +# Refer doc/README.pblimage for more details about how-to configure +# and create PBL boot image +# + +#PBI commands +#Initialize CPC1 as 1MB SRAM +09010000 00200400 +09138000 00000000 +091380c0 00000100 +09010100 00000000 +09010104 fff0000b +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff00000 +09000d08 81000013 +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Initialize eSPI controller, default configuration is slow for eSPI to +#load data, this configuration comes from u-boot eSPI driver. +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/nxp/p2041rdb/rcw_p2041rdb.cfg b/board/nxp/p2041rdb/rcw_p2041rdb.cfg new file mode 100644 index 00000000000..8df19dd3fe4 --- /dev/null +++ b/board/nxp/p2041rdb/rcw_p2041rdb.cfg @@ -0,0 +1,11 @@ +# +# Default RCW for P2041RDB. +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +12600000 00000000 241C0000 00000000 +649FA0C1 C3C02000 58000000 40000000 +00000000 00000000 00000000 D0030F07 +00000000 00000000 00000000 00000000 diff --git a/board/nxp/t102xrdb/Kconfig b/board/nxp/t102xrdb/Kconfig new file mode 100644 index 00000000000..925a984677e --- /dev/null +++ b/board/nxp/t102xrdb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_T1023RDB || TARGET_T1024RDB + +config SYS_BOARD + default "t102xrdb" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "T102xRDB" + +endif diff --git a/board/nxp/t102xrdb/MAINTAINERS b/board/nxp/t102xrdb/MAINTAINERS new file mode 100644 index 00000000000..030dc3f950e --- /dev/null +++ b/board/nxp/t102xrdb/MAINTAINERS @@ -0,0 +1,9 @@ +T102XRDB BOARD +M: Priyanka Jain +S: Maintained +F: board/nxp/t102xrdb/ +F: include/configs/T102xRDB.h +F: configs/T1024RDB_defconfig +F: configs/T1024RDB_NAND_defconfig +F: configs/T1024RDB_SDCARD_defconfig +F: configs/T1024RDB_SPIFLASH_defconfig diff --git a/board/nxp/t102xrdb/Makefile b/board/nxp/t102xrdb/Makefile new file mode 100644 index 00000000000..b0f27c47191 --- /dev/null +++ b/board/nxp/t102xrdb/Makefile @@ -0,0 +1,16 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +else +obj-y += t102xrdb.o +obj-$(CONFIG_TARGET_T1024RDB) += cpld.o +obj-y += eth_t102xrdb.o +endif +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/nxp/t102xrdb/README b/board/nxp/t102xrdb/README new file mode 100644 index 00000000000..de170f52b4d --- /dev/null +++ b/board/nxp/t102xrdb/README @@ -0,0 +1,340 @@ +T1024 SoC Overview +------------------ +The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor +combines two or one 64-bit Power Architecture e5500 core respectively with high +performance datapath acceleration logic, and network peripheral bus interfaces +required for networking and telecommunications. This processor can be used in +applications such as enterprise WLAN access points, routers, switches, firewall +and other packet processing intensive small enterprise and branch office appliances, +and general-purpose embedded computing. Its high level of integration offers +significant performance benefits and greatly helps to simplify board design. + + +The T1024 SoC includes the following function and features: +- two e5500 cores, each with a private 256 KB L2 cache + - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant) + - Three levels of instructions: User, supervisor, and hypervisor + - Independent boot and reset + - Secure boot capability +- 256 KB shared L3 CoreNet platform cache (CPC) +- Interconnect CoreNet platform + - CoreNet coherency manager supporting coherent and noncoherent transactions + with prioritization and bandwidth allocation amongst CoreNet endpoints + - 150 Gbps coherent read bandwidth +- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support +- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: + - Packet parsing, classification, and distribution + - Queue management for scheduling, packet sequencing, and congestion management + - Cryptography Acceleration (SEC 5.x) + - IEEE 1588 support + - Hardware buffer management for buffer allocation and deallocation + - MACSEC on DPAA-based Ethernet ports +- Ethernet interfaces + - Four 1 Gbps Ethernet controllers +- Parallel Ethernet interfaces + - Two RGMII interfaces +- High speed peripheral interfaces + - Three PCI Express 2.0 controllers/ports running at up to 5 GHz + - One SATA controller supporting 1.5 and 3.0 Gb/s operation + - One QSGMII interface + - Four SGMII interface supporting 1000 Mbps + - Three SGMII interfaces supporting up to 2500 Mbps + - 10GBase-R or 10Base-KR interface +- Additional peripheral interfaces + - Two USB 2.0 controllers with integrated PHY + - SD/eSDHC/eMMC + - eSPI controller + - Four I2C controllers + - Four UARTs + - Four GPIO controllers + - Integrated flash controller (IFC) + - LCD interface (DIU) with 12 bit dual data rate +- Multicore programmable interrupt controller (PIC) +- Two 8-channel DMA engines +- Single source clocking implementation +- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) +- QUICC Engine block + - 32-bit RISC controller for flexible support of the communications peripherals + - Serial DMA channel for receive and transmit on all serial channels + - Two universal communication controllers, supporting TDM, HDLC, and UART + +T1023 Personality +------------------ +T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and +unavailable deep sleep. Rest of the blocks are almost same as T1024. +Differences between T1024 and T1023 +Feature T1024 T1023 +QUICC Engine: yes no +DIU: yes no +Deep Sleep: yes no +I2C controller: 4 3 +DDR: 64-bit 32-bit +IFC: 32-bit 28-bit +Package: 23x23 19x19 + + +T1024RDB board Overview +----------------------- + - Ethernet + - Two on-board 10M/100M/1G bps RGMII ethernet ports + - One on-board 10G bps Base-T port. + - DDR Memory + - Supports 64-bit 4GB DDR3L DIMM + - PCIe + - One on-board PCIe slot. + - Two on-board PCIe Mini-PCIe connectors. + - IFC/Local Bus + - NOR: 128MB 16-bit NOR Flash + - NAND: 1GB 8-bit NAND flash + - CPLD: for system controlling with programable header on-board + - USB + - Supports two USB 2.0 ports with integrated PHYs + - Two type A ports with 5V@1.5A per port. + - SDHC + - one SD connector supporting 1.8V/3.3V via J53. + - SPI + - On-board 64MB SPI flash + - Other + - Two Serial ports + - Four I2C ports + + +T1023RDB board Overview +----------------------- +- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz +- CoreNet fabric supporting coherent and noncoherent transactions with + prioritization and bandwidth allocation +- SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC +- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC +- Ethernet interfaces: + - one 1G RGMII port on-board(RTL8211FS PHY) + - one 1G SGMII port on-board(RTL8211FS PHY) + - one 2.5G SGMII port on-board(AQR105 PHY) +- PCIe: Two Mini-PCIe connectors on-board. +- SerDes: 4 lanes up to 10.3125GHz +- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash +- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash +- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash. +- USB: one Type-A USB 2.0 port with internal PHY +- eSDHC: support SD/MMC and eMMC card +- 256Kbit M24256 I2C EEPROM +- RTC: Real-time clock DS1339U on I2C bus +- UART: one serial port on-board with RJ45 connector +- Debugging: JTAG/COP for T1023 debugging + + +Memory map on T1024RDB +---------------------- +Start Address End Address Description Size +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB +0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB +0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB +0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB +0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB +0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB +0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB +0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB +0xF_0000_0000 0xF_003F_FFFF DCSR 4MB +0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB +0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB +0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB +0x0_0000_0000 0x0_ffff_ffff DDR 4GB + + +128MB NOR Flash Memory Layout +----------------------------- +Start Address End Address Definition Max size +0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB +0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB +0xED300000 0xEFDFFFFF rootfs (alt bank) 44MB +0xED000000 0xED2FFFFF Guest image #3 (alternate bank) 3MB +0xECD00000 0xECFFFFFF Guest image #2 (alternate bank) 3MB +0xECA00000 0xECCFFFFF Guest image #1 (alternate bank) 3MB +0xEC900000 0xEC9FFFFF HV config device tree(alt bank) 1MB +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB +0xEC700000 0xEC7FFFFF HV.uImage (alternate bank) 1MB +0xEC020000 0xEC6FFFFF Linux.uImage (alt bank) ~7MB +0xEC000000 0xEC01FFFF RCW (alt bank) 128KB +0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB +0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB +0xE9300000 0xEBDFFFFF rootfs (current bank) 44MB +0xE9000000 0xE92FFFFF Guest image #3 (current bank) 3MB +0xE8D00000 0xE8FFFFFF Guest image #2 (current bank) 3MB +0xE8A00000 0xE8CFFFFF Guest image #1 (current bank) 3MB +0xE8900000 0xE89FFFFF HV config device tree(cur bank) 1MB +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB +0xE8700000 0xE87FFFFF HV.uImage (current bank) 1MB +0xE8020000 0xE86FFFFF Linux.uImage (current bank) ~7MB +0xE8000000 0xE801FFFF RCW (current bank) 128KB + + +T1024/T1023 Clock frequency +--------------------------- +BIN Core DDR Platform FMan +Bin1: 1400MHz 1600MT/s 400MHz 700MHz +Bin2: 1200MHz 1600MT/s 400MHz 600MHz +Bin3: 1000MHz 1600MT/s 400MHz 500MHz + + +Software configurations and board settings +------------------------------------------ +1. NOR boot: + a. build NOR boot image + $ make T1024RDB_defconfig + $ make + b. program u-boot.bin image to NOR flash + => tftp 1000000 u-boot.bin + => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize + on T1024RDB: + set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot + on T1023RDB: + set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot + + Switching between default bank0 and alternate bank4 on NOR flash + To change boot source to vbank4: + on T1024RDB: + via software: run command 'cpld reset altbank' in U-Boot. + via DIP-switch: set SW3[5:7] = '100' + on T1023RDB: + via software: run command 'switch bank4' in U-Boot. + via DIP-switch: set SW3[5:7] = '100' + + To change boot source to vbank0: + on T1024RDB: + via software: run command 'cpld reset' in U-Boot. + via DIP-Switch: set SW3[5:7] = '000' + on T1023RDB: + via software: run command 'switch bank0' in U-Boot. + via DIP-switch: set SW3[5:7] = '000' + +2. NAND Boot: + a. build PBL image for NAND boot + $ make T1024RDB_NAND_defconfig + $ make + b. program u-boot-with-spl-pbl.bin to NAND flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => nand erase 0 $filesize + => nand write 1000000 0 $filesize + set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot + +3. SPI Boot: + a. build PBL image for SPI boot + $ make T1024RDB_SPIFLASH_defconfig + $ make + b. program u-boot-with-spl-pbl.bin to SPI flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => sf probe 0 + => sf erase 0 100000 + => sf write 1000000 0 $filesize + => tftp 1000000 fsl_fman_ucode_t1024_xx.bin + => sf erase 100000 100000 + => sf write 1000000 110000 20000 + set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot + +4. SD Boot: + a. build PBL image for SD boot + $ make T1024RDB_SDCARD_defconfig + $ make + b. program u-boot-with-spl-pbl.bin to SD/MMC card + => tftp 1000000 u-boot-with-spl-pbl.bin + => mmc write 1000000 8 0x7f0 + => tftp 1000000 fsl_fman_ucode_t1024_xx.bin + => mmc write 1000000 0x820 80 + set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot + + SW3[3] = '1' for SD card(or 'switch sd' by software) + SW3[3] = '0' for eMMC (or 'switch emmc' by software) + + +device tree support and how to enable it for different configs +-------------------------------------------------------------- +device tree support is available for t1024rdb for below mentioned boot, +1. nor boot +2. nand boot +3. sd boot +4. spiflash boot + +to enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. config_default_device_tree="t1024rdb" (change default device tree name if required) +2. config_of_control +3. config_mpc85xx_have_reset_vector if reset vector is located at + config_reset_vector_address - 0xffc + +if device tree support is enabled in defconfig, +1. use 'u-boot.bin' for nor boot. +2. use 'u-boot-with-spl-pbl.bin' for other boot. + +2-stage NAND/SPI/SD boot loader +------------------------------- +PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. +SPL further initializes DDR using SPD and environment variables +and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR. +Finally SPL transers control to U-Boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + +Run time view of SPL framework +------------------------------------------------- +|Area | Address | +------------------------------------------------- +|SecureBoot header | 0xFFFC0000 (32KB) | +------------------------------------------------- +|GD, BD | 0xFFFC8000 (4KB) | +------------------------------------------------- +|ENV | 0xFFFC9000 (8KB) | +------------------------------------------------- +|HEAP | 0xFFFCB000 (30KB) | +------------------------------------------------- +|STACK | 0xFFFD8000 (22KB) | +------------------------------------------------- +|U-Boot SPL | 0xFFFD8000 (160KB) | +------------------------------------------------- + +NAND Flash memory Map on T1024RDB +------------------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF U-Boot 1MB(2 block) +0x100000 0x17FFFF U-Boot env 512KB(1 block) +0x180000 0x1FFFFF FMAN Ucode 512KB(1 block) +0x200000 0x27FFFF QE Firmware 512KB(1 block) + + +NAND Flash memory Map on T1023RDB +---------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF U-Boot 1MB +0x100000 0x15FFFF U-Boot env 8KB +0x160000 0x17FFFF FMAN Ucode 128KB + + +SD Card memory Map on T102xRDB +---------------------------------------------------- +Block #blocks Definition Size +0x008 2048 U-Boot img 1MB +0x800 0016 U-Boot env 8KB +0x820 0256 FMAN Ucode 128KB +0x920 0256 QE Firmware 128KB(only T1024RDB) + + +64MB SPI Flash memory Map on T102xRDB +---------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF U-Boot img 1MB +0x100000 0x101FFF U-Boot env 8KB +0x110000 0x12FFFF FMAN Ucode 128KB +0x130000 0x14FFFF QE Firmware 128KB(only T1024RDB) +0x300000 0x3FFFFF device tree 128KB +0x400000 0x9FFFFF Linux kernel 6MB +0xa00000 0x3FFFFFF rootfs 54MB + + +For more details, please refer to T1024RDB/T1023RDB User Guide +and Freescale QorIQ SDK Infocenter document. diff --git a/board/nxp/t102xrdb/cpld.c b/board/nxp/t102xrdb/cpld.c new file mode 100644 index 00000000000..00ea9d8f503 --- /dev/null +++ b/board/nxp/t102xrdb/cpld.c @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * Copyright 2014 Freescale Semiconductor + * + * Freescale T1024RDB board-specific CPLD controlling supports. + * + * The following macros need to be defined: + */ + +#include +#include +#include +#include +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CFG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CFG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(void) +{ + u8 reg = CPLD_READ(flash_csr); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; + + CPLD_WRITE(flash_csr, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + u8 reg = CPLD_READ(flash_csr); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; + + CPLD_WRITE(flash_csr, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +static void cpld_dump_regs(void) +{ + printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); + printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); + printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); + printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); + printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); + printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); + printf("int_status = 0x%02x\n", CPLD_READ(int_status)); + printf("flash_csr = 0x%02x\n", CPLD_READ(flash_csr)); + printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status)); + printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status)); + printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status)); + printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status)); + printf("boot_override = 0x%02x\n", CPLD_READ(boot_override)); + printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1)); + printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2)); + putc('\n'); +} + +int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); + } else { + rc = cmd_usage(cmdtp); + } + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset - hard reset to default bank\n" + "cpld reset altbank - reset to alternate bank\n" + "cpld dump - display the CPLD registers\n" + ); diff --git a/board/nxp/t102xrdb/cpld.h b/board/nxp/t102xrdb/cpld.h new file mode 100644 index 00000000000..b504c3fcc47 --- /dev/null +++ b/board/nxp/t102xrdb/cpld.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/** + * Copyright 2014 Freescale Semiconductor + * + */ + +struct cpld_data { + u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */ + u8 hw_ver; /* 0x02 - Hardware Revision Register */ + u8 sw_ver; /* 0x03 - Software Revision register */ + u8 res0[12]; /* 0x04 - 0x0F - not used */ + u8 reset_ctl1; /* 0x10 - Reset control Register1 */ + u8 reset_ctl2; /* 0x11 - Reset control Register2 */ + u8 int_status; /* 0x12 - Interrupt status Register */ + u8 flash_csr; /* 0x13 - Flash control and status register */ + u8 fan_ctl_status; /* 0x14 - Fan control and status register */ + u8 led_ctl_status; /* 0x15 - LED control and status register */ + u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ + u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ + u8 boot_override; /* 0x18 - Boot override register */ + u8 boot_config1; /* 0x19 - Boot config override register*/ + u8 boot_config2; /* 0x1A - Boot config override register*/ +}; + +/* Pointer to the CPLD register set */ + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value)\ + cpld_write(offsetof(struct cpld_data, reg), value) + +/* CPLD on IFC */ +#define CPLD_LBMAP_MASK 0x3F +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_OVERRIDE 0x40 +#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ +#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */ +#define CPLD_LBMAP_RESET 0xFF +#define CPLD_LBMAP_SHIFT 0x03 +#define CPLD_BOOT_SEL 0x80 + +#define CPLD_PCIE_SGMII_MUX 0x80 +#define CPLD_OVERRIDE_BOOT_EN 0x01 +#define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override enable */ diff --git a/board/nxp/t102xrdb/ddr.c b/board/nxp/t102xrdb/ddr.c new file mode 100644 index 00000000000..1a8a131cdcc --- /dev/null +++ b/board/nxp/t102xrdb/ddr.c @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * datarate_mhz_high values need to be in ascending order + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ + {2, 833, 0, 8, 6, 0x06060607, 0x08080807,}, + {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {1, 833, 0, 8, 6, 0x06060607, 0x08080807,}, + {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, + {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + struct cpu_type *cpu = gd->arch.cpu; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust according to the board ddr freqency and n_banks + * specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found\n"); + printf("for data rate %lu MT/s\n", ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ", + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2); + debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * rtt and rtt_wr override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF); + + /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit, + * force DDR bus width to 32bit for T1023 + */ + if (cpu->soc_ver == SVR_T1023) + popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; + +#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32 + /* for DDR bus 32bit test on T1024 */ + popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; +#endif + +#ifdef CONFIG_TARGET_T1023RDB + popts->wrlvl_ctl_2 = 0x07070606; + popts->half_strength_driver_enable = 1; + popts->cpo_sample = 0x43; +#elif defined(CONFIG_TARGET_T1024RDB) + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x52; +#endif +} + +#ifdef CONFIG_SYS_DDR_RAW_TIMING +/* 2GB discrete DDR4 MT40A512M8HX on T1023RDB */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 0x80000000, + .capacity = 0x80000000, + .primary_sdram_width = 32, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .bank_addr_bits = 2, + .bank_group_bits = 2, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + .tckmin_x_ps = 938, + .tckmax_ps = 1500, + .caslat_x = 0x000DFA00, + .taa_ps = 13500, + .trcd_ps = 13500, + .trp_ps = 13500, + .tras_ps = 33000, + .trc_ps = 46500, + .trfc1_ps = 260000, + .trfc2_ps = 160000, + .trfc4_ps = 110000, + .tfaw_ps = 25000, + .trrds_ps = 3700, + .trrdl_ps = 5300, + .tccdl_ps = 5355, + .refresh_rate_ps = 7800000, + .dq_mapping[0] = 0x0, + .dq_mapping[1] = 0x0, + .dq_mapping[2] = 0x0, + .dq_mapping[3] = 0x0, + .dq_mapping[4] = 0x0, + .dq_mapping[5] = 0x0, + .dq_mapping[6] = 0x0, + .dq_mapping[7] = 0x0, + .dq_mapping[8] = 0x0, + .dq_mapping[9] = 0x0, + .dq_mapping[10] = 0x0, + .dq_mapping[11] = 0x0, + .dq_mapping[12] = 0x0, + .dq_mapping[13] = 0x0, + .dq_mapping[14] = 0x0, + .dq_mapping[15] = 0x0, + .dq_mapping[16] = 0x0, + .dq_mapping[17] = 0x0, + .dq_mapping_ors = 1, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR4 on board"; + + if (((controller_number == 0) && (dimm_number == 0)) || + ((controller_number == 1) && (dimm_number == 0))) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} +#endif + +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void) +{ + void __iomem *cpld_base = (void *)CFG_SYS_CPLD_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(cpld_base + 0x17, 0x40); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif + +int dram_init(void) +{ + phys_size_t dram_size; + +#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) +#ifndef CONFIG_SYS_DDR_RAW_TIMING + puts("Initializing....using SPD\n"); +#endif + dram_size = fsl_ddr_sdram(); +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD) + fsl_dp_resume(); +#endif + + gd->ram_size = dram_size; + + return 0; +} diff --git a/board/nxp/t102xrdb/eth_t102xrdb.c b/board/nxp/t102xrdb/eth_t102xrdb.c new file mode 100644 index 00000000000..7185a0abd52 --- /dev/null +++ b/board/nxp/t102xrdb/eth_t102xrdb.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * Shengzhou Liu + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/fman.h" + +int board_eth_init(struct bd_info *bis) +{ +#if defined(CONFIG_FMAN_ENET) + int i, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + struct mii_dev *dev; + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Set the on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); + + switch (srds_s1) { +#ifdef CONFIG_TARGET_T1024RDB + case 0x95: + /* set the on-board RGMII2 PHY */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); + + /* set 10GBase-R with Aquantia AQR105 PHY */ + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + break; +#endif + case 0x6a: + case 0x6b: + case 0x77: + case 0x135: + /* set the on-board 2.5G SGMII AQR105 PHY */ + fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR); +#ifdef CONFIG_TARGET_T1023RDB + /* set the on-board 1G SGMII RTL8211F PHY */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR); +#endif + break; + default: + printf("SerDes protocol 0x%x is not supported on T102xRDB\n", + srds_s1); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + case PHY_INTERFACE_MODE_SGMII: +#if defined(CONFIG_TARGET_T1023RDB) + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); +#elif defined(CONFIG_TARGET_T1024RDB) + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); +#endif + fm_info_set_mdio(i, dev); + break; + case PHY_INTERFACE_MODE_2500BASEX: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} + +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ +#if defined(CONFIG_TARGET_T1024RDB) + if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) || + (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) && + (port == FM1_DTSEC3)) { + fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4"); + fdt_setprop_string(fdt, offset, "phy-connection-type", + "2500base-x"); + fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3"); + } +#endif +} + +void fdt_fixup_board_enet(void *fdt) +{ +} diff --git a/board/nxp/t102xrdb/law.c b/board/nxp/t102xrdb/law.c new file mode 100644 index 00000000000..81caa961897 --- /dev/null +++ b/board/nxp/t102xrdb/law.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include +#include +#include + +struct law_entry law_table[] = { +#ifdef CONFIG_MTD_NOR_FLASH + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#endif +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CFG_SYS_CPLD_BASE_PHYS + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/nxp/t102xrdb/spl.c b/board/nxp/t102xrdb/spl.c new file mode 100644 index 00000000000..de6cdda194e --- /dev/null +++ b/board/nxp/t102xrdb/spl.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/sleep.h" +#include "../common/spl.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +#if defined(CONFIG_SPL_MMC_BOOT) +#define GPIO1_SD_SEL 0x00020000 +int board_mmc_getcd(struct mmc *mmc) +{ + ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); + u32 val = in_be32(&pgpio->gpdat); + + /* GPIO1_14, 0: eMMC, 1: SD */ + val &= GPIO1_SD_SEL; + + return val ? -1 : 1; +} + +int board_mmc_getwp(struct mmc *mmc) +{ + ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); + u32 val = in_be32(&pgpio->gpdat); + + val &= GPIO1_SD_SEL; + + return val ? -1 : 0; +} +#endif + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + console_init_f(); + +#ifdef CONFIG_DEEP_SLEEP + /* disable the console if boot from deep sleep */ + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#if defined(CONFIG_SPL_MMC_BOOT) + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + struct bd_info *bd; + + bd = (struct bd_info *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(struct bd_info)); + gd->bd = bd; + + arch_cpu_init(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; + +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)SPL_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)SPL_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)SPL_ENV_ADDR); +#endif + + gd->env_addr = (ulong)(SPL_ENV_ADDR); + gd->env_valid = ENV_VALID; + + i2c_init_all(); + + dram_init(); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + fsl_spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/nxp/t102xrdb/t1023_nand_rcw.cfg b/board/nxp/t102xrdb/t1023_nand_rcw.cfg new file mode 100644 index 00000000000..f8f72826b16 --- /dev/null +++ b/board/nxp/t102xrdb/t1023_nand_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header for T1023RDB +aa55aa55 010e0100 +#SerDes Protocol: 0x77 +#Default Core=1200MHz, DDR=1600MT/s with single source clock +0810000c 00000000 00000000 00000000 +3b800003 00000012 e8104000 21000000 +00000000 00000000 00000000 00022800 +00000130 04020200 00000000 00000006 diff --git a/board/nxp/t102xrdb/t1023_sd_rcw.cfg b/board/nxp/t102xrdb/t1023_sd_rcw.cfg new file mode 100644 index 00000000000..dbf8fba5535 --- /dev/null +++ b/board/nxp/t102xrdb/t1023_sd_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header for T1023RDB +aa55aa55 010e0100 +#SerDes Protocol: 0x77 +#Default Core=1200MHz, DDR=1600MT/s with single source clock +0810000c 00000000 00000000 00000000 +3b800003 00000012 68104000 21000000 +00000000 00000000 00000000 00022800 +00000130 04020200 00000000 00000006 diff --git a/board/nxp/t102xrdb/t1023_spi_rcw.cfg b/board/nxp/t102xrdb/t1023_spi_rcw.cfg new file mode 100644 index 00000000000..5edcdb50ea9 --- /dev/null +++ b/board/nxp/t102xrdb/t1023_spi_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header for T1023RDB +aa55aa55 010e0100 +#SerDes Protocol: 0x77 +#Default Core=1200MHz, DDR=1600MT/s with single source clock +0810000c 00000000 00000000 00000000 +3b800003 00000012 58104000 21000000 +00000000 00000000 00000000 00022800 +00000130 04020200 00000000 00000006 diff --git a/board/nxp/t102xrdb/t1024_nand_rcw.cfg b/board/nxp/t102xrdb/t1024_nand_rcw.cfg new file mode 100644 index 00000000000..cd6f906396e --- /dev/null +++ b/board/nxp/t102xrdb/t1024_nand_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header for T1024RDB +aa55aa55 010e0100 +#SerDes Protocol: 0x95 +#Core/DDR: 1400Mhz/1600MT/s with single source clock +0810000c 00000000 00000000 00000000 +4a800003 80000012 ec027000 21000000 +00000000 00000000 00000000 00030810 +00000000 0b005a08 00000000 00000006 diff --git a/board/nxp/t102xrdb/t1024_pbi.cfg b/board/nxp/t102xrdb/t1024_pbi.cfg new file mode 100644 index 00000000000..98efca25a29 --- /dev/null +++ b/board/nxp/t102xrdb/t1024_pbi.cfg @@ -0,0 +1,26 @@ +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 fffc0007 +09010f00 081e000d +09010000 80000000 +#Configure LAW for CPC1 +09000cd0 00000000 +09000cd4 fffc0000 +09000cd8 81000011 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +091380c0 000FFFFF diff --git a/board/nxp/t102xrdb/t1024_sd_rcw.cfg b/board/nxp/t102xrdb/t1024_sd_rcw.cfg new file mode 100644 index 00000000000..05b3f377636 --- /dev/null +++ b/board/nxp/t102xrdb/t1024_sd_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header for T1024RDB +aa55aa55 010e0100 +#SerDes Protocol: 0x95 +#Core/DDR: 1400Mhz/1600MT/s with single source clock +0810000c 00000000 00000000 00000000 +4a800003 80000012 6c027000 21000000 +00000000 00000000 00000000 00030810 +00000000 0b005a08 00000000 00000006 diff --git a/board/nxp/t102xrdb/t1024_spi_rcw.cfg b/board/nxp/t102xrdb/t1024_spi_rcw.cfg new file mode 100644 index 00000000000..8b695b4ab7b --- /dev/null +++ b/board/nxp/t102xrdb/t1024_spi_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header for T1024RDB +aa55aa55 010e0100 +#SerDes Protocol: 0x95 +#Core/DDR: 1400Mhz/1600MT/s with single source clock +0810000c 00000000 00000000 00000000 +4a800003 80000012 5c027000 21000000 +00000000 00000000 00000000 00030810 +00000000 0b005a08 00000000 00000006 diff --git a/board/nxp/t102xrdb/t102xrdb.c b/board/nxp/t102xrdb/t102xrdb.c new file mode 100644 index 00000000000..0a29e27b42c --- /dev/null +++ b/board/nxp/t102xrdb/t102xrdb.c @@ -0,0 +1,397 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020-2023 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "t102xrdb.h" +#ifdef CONFIG_TARGET_T1024RDB +#include "cpld.h" +#elif defined(CONFIG_TARGET_T1023RDB) +#include +#include +#endif +#include "../common/sleep.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_TARGET_T1023RDB +enum { + GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */ + GPIO1_EMMC_SEL, + GPIO3_GET_VERSION, /* GPIO3_4/5, 00:RevB, 01: RevC */ + GPIO3_BRD_VER_MASK = 0x0c000000, + GPIO3_OFFSET = 0x2000, + I2C_GET_BANK, + I2C_SET_BANK0, + I2C_SET_BANK4, +}; +#endif + +#if CONFIG_IS_ENABLED(DM_SERIAL) +int get_serial_clock(void) +{ + return get_bus_freq(0) / 2; +} +#endif + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + printf("Board: %sRDB, ", cpu->name); +#if defined(CONFIG_TARGET_T1024RDB) + printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", + CPLD_READ(hw_ver), CPLD_READ(sw_ver)); +#elif defined(CONFIG_TARGET_T1023RDB) + printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B'); +#endif + printf("boot from "); + +#ifdef CONFIG_SDCARD + puts("SD/MMC\n"); +#elif CONFIG_SPIFLASH + puts("SPI\n"); +#elif defined(CONFIG_TARGET_T1024RDB) + u8 reg; + + reg = CPLD_READ(flash_csr); + + if (reg & CPLD_BOOT_SEL) { + puts("NAND\n"); + } else { + reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); + printf("NOR vBank%d\n", reg); + } +#elif defined(CONFIG_TARGET_T1023RDB) +#ifdef CONFIG_MTD_RAW_NAND + puts("NAND\n"); +#else + printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK)); +#endif +#endif + + puts("SERDES Reference Clocks:\n"); + if (srds_s1 == 0x95) + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); + else + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]); + + return 0; +} + +#ifdef CONFIG_TARGET_T1024RDB +static void board_mux_lane(void) +{ + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1; + u8 reg = CPLD_READ(misc_ctl_status); + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + if (srds_prtcl_s1 == 0x95) { + /* Route Lane B to PCIE */ + CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX); + } else { + /* Route Lane B to SGMII */ + CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX); + } + CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN); +} +#endif + +int board_early_init_f(void) +{ +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + return 0; +} + +int board_early_init_r(void) +{ +#ifdef CFG_SYS_FLASH_BASE + const unsigned int flashbase = CFG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); +#endif + +#ifdef CONFIG_TARGET_T1024RDB + board_mux_lane(); +#endif + + pci_init(); + + return 0; +} + +#ifdef CONFIG_TARGET_T1024RDB +void board_reset(void) +{ + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} +#endif + +int misc_init_r(void) +{ + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = env_get_bootm_low(); + size = env_get_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fsl_fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN +#ifndef CONFIG_DM_ETH + fdt_fixup_fman_ethernet(blob); +#endif + fdt_fixup_board_enet(blob); +#endif + +#ifdef CONFIG_TARGET_T1023RDB + if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0) + fdt_enable_nor(blob); +#endif + + return 0; +} + +#ifdef CONFIG_TARGET_T1023RDB +/* Enable NOR flash for RevC */ +static void fdt_enable_nor(void *blob) +{ + int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash"); + + if (nodeoff >= 0) + fdt_status_okay(blob, nodeoff); + else + printf("WARNING unable to set status for NOR\n"); +} + +int board_mmc_getcd(struct mmc *mmc) +{ + ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); + u32 val = in_be32(&pgpio->gpdat); + + /* GPIO1_14, 0: eMMC, 1: SD/MMC */ + val &= GPIO1_SD_SEL; + + return val ? -1 : 1; +} + +int board_mmc_getwp(struct mmc *mmc) +{ + ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); + u32 val = in_be32(&pgpio->gpdat); + + val &= GPIO1_SD_SEL; + + return val ? -1 : 0; +} + +static u32 t1023rdb_ctrl(u32 ctrl_type) +{ + ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + u32 val; + u8 tmp; + int bus_num = I2C_PCA6408_BUS_NUM; + +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA6408_ADDR, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + bus_num); + return ret; + } + switch (ctrl_type) { + case GPIO1_SD_SEL: + val = in_be32(&pgpio->gpdat); + val |= GPIO1_SD_SEL; + out_be32(&pgpio->gpdat, val); + setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); + break; + case GPIO1_EMMC_SEL: + val = in_be32(&pgpio->gpdat); + val &= ~GPIO1_SD_SEL; + out_be32(&pgpio->gpdat, val); + setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); + break; + case GPIO3_GET_VERSION: + pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR + + GPIO3_OFFSET); + val = in_be32(&pgpio->gpdat); + val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3; + if (val == 0x3) /* GPIO3_4/5 not used on RevB */ + val = 0; + return val; + case I2C_GET_BANK: + dm_i2c_read(dev, 0, &tmp, 1); + tmp &= 0x7; + tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2); + return tmp; + case I2C_SET_BANK0: + tmp = 0x0; + dm_i2c_write(dev, 1, &tmp, 1); + tmp = 0xf8; + dm_i2c_write(dev, 3, &tmp, 1); + /* asserting HRESET_REQ */ + out_be32(&gur->rstcr, 0x2); + break; + case I2C_SET_BANK4: + tmp = 0x1; + dm_i2c_write(dev, 1, &tmp, 1); + tmp = 0xf8; + dm_i2c_write(dev, 3, &tmp, 1); + out_be32(&gur->rstcr, 0x2); + break; + default: + break; + } +#else + u32 orig_bus; + + orig_bus = i2c_get_bus_num(); + + switch (ctrl_type) { + case GPIO1_SD_SEL: + val = in_be32(&pgpio->gpdat); + val |= GPIO1_SD_SEL; + out_be32(&pgpio->gpdat, val); + setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); + break; + case GPIO1_EMMC_SEL: + val = in_be32(&pgpio->gpdat); + val &= ~GPIO1_SD_SEL; + out_be32(&pgpio->gpdat, val); + setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); + break; + case GPIO3_GET_VERSION: + pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR + + GPIO3_OFFSET); + val = in_be32(&pgpio->gpdat); + val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3; + if (val == 0x3) /* GPIO3_4/5 not used on RevB */ + val = 0; + return val; + case I2C_GET_BANK: + i2c_set_bus_num(bus_num); + i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1); + tmp &= 0x7; + tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2); + i2c_set_bus_num(orig_bus); + return tmp; + case I2C_SET_BANK0: + i2c_set_bus_num(bus_num); + tmp = 0x0; + i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1); + tmp = 0xf8; + i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1); + /* asserting HRESET_REQ */ + out_be32(&gur->rstcr, 0x2); + break; + case I2C_SET_BANK4: + i2c_set_bus_num(bus_num); + tmp = 0x1; + i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1); + tmp = 0xf8; + i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1); + out_be32(&gur->rstcr, 0x2); + break; + default: + break; + } +#endif + return 0; +} + +static int switch_cmd(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (argc < 2) + return CMD_RET_USAGE; + if (!strcmp(argv[1], "bank0")) + t1023rdb_ctrl(I2C_SET_BANK0); + else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank")) + t1023rdb_ctrl(I2C_SET_BANK4); + else if (!strcmp(argv[1], "sd")) + t1023rdb_ctrl(GPIO1_SD_SEL); + else if (!strcmp(argv[1], "emmc")) + t1023rdb_ctrl(GPIO1_EMMC_SEL); + else + return CMD_RET_USAGE; + return 0; +} + +U_BOOT_CMD( + switch, 2, 0, switch_cmd, + "for bank0/bank4/sd/emmc switch control in runtime", + "command (e.g. switch bank4)" +); +#endif diff --git a/board/nxp/t102xrdb/t102xrdb.h b/board/nxp/t102xrdb/t102xrdb.h new file mode 100644 index 00000000000..33df0f24df8 --- /dev/null +++ b/board/nxp/t102xrdb/t102xrdb.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __T1024_RDB_H__ +#define __T1024_RDB_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, struct bd_info *bd); +#ifdef CONFIG_TARGET_T1023RDB +static u32 t1023rdb_ctrl(u32 ctrl_type); +static void fdt_enable_nor(void *blob); +#endif +#endif diff --git a/board/nxp/t102xrdb/tlb.c b/board/nxp/t102xrdb/tlb.c new file mode 100644 index 00000000000..8e99c2c7022 --- /dev/null +++ b/board/nxp/t102xrdb/tlb.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the + * SRAM is at 0xfffc0000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256K, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + +#ifndef CONFIG_XPL_BUILD + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_16M, 1), +#endif +#endif +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_4M, 1), +#endif +#ifdef CFG_SYS_NAND_BASE + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef CFG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1), +#endif + +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD) + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 12, BOOKE_PAGESZ_1G, 1), + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000, + CFG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 13, BOOKE_PAGESZ_1G, 1) +#endif + /* entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so if needed more, will use entry 16 later. + */ +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/nxp/t104xrdb/Kconfig b/board/nxp/t104xrdb/Kconfig new file mode 100644 index 00000000000..fb26b7c9256 --- /dev/null +++ b/board/nxp/t104xrdb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_T1042D4RDB + +config SYS_BOARD + default "t104xrdb" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "T104xRDB" + +endif diff --git a/board/nxp/t104xrdb/MAINTAINERS b/board/nxp/t104xrdb/MAINTAINERS new file mode 100644 index 00000000000..5542530698d --- /dev/null +++ b/board/nxp/t104xrdb/MAINTAINERS @@ -0,0 +1,26 @@ +T104XRDB BOARD +M: Priyanka Jain +S: Maintained +F: board/nxp/t104xrdb/ +F: include/configs/T104xRDB.h +F: configs/T1040RDB_defconfig +F: configs/T1040RDB_NAND_defconfig +F: configs/T1040RDB_SPIFLASH_defconfig +F: configs/T1040D4RDB_defconfig +F: configs/T1040D4RDB_NAND_defconfig +F: configs/T1040D4RDB_SPIFLASH_defconfig +F: configs/T1042RDB_defconfig +F: configs/T1042D4RDB_defconfig +F: configs/T1042D4RDB_NAND_defconfig +F: configs/T1042D4RDB_SPIFLASH_defconfig +F: configs/T1042RDB_PI_defconfig +F: configs/T1042RDB_PI_NAND_defconfig +F: configs/T1042RDB_PI_SPIFLASH_defconfig + +T1040RDB_SDCARD BOARD +M: Priyanka Jain +S: Maintained +F: configs/T1040RDB_SDCARD_defconfig +F: configs/T1040D4RDB_SDCARD_defconfig +F: configs/T1042D4RDB_SDCARD_defconfig +F: configs/T1042RDB_PI_SDCARD_defconfig diff --git a/board/nxp/t104xrdb/Makefile b/board/nxp/t104xrdb/Makefile new file mode 100644 index 00000000000..9bca1a1fbcc --- /dev/null +++ b/board/nxp/t104xrdb/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2013 Freescale Semiconductor, Inc. + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +else +obj-y += t104xrdb.o +obj-y += cpld.o +obj-y += eth.o +endif +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/nxp/t104xrdb/README b/board/nxp/t104xrdb/README new file mode 100644 index 00000000000..b852f72998d --- /dev/null +++ b/board/nxp/t104xrdb/README @@ -0,0 +1,386 @@ +Overview +-------- +The T1040RDB is a Freescale reference board that hosts the T1040 SoC +(and variants). Variants inclued T1042 presonality of T1040, in which +case T1040RDB can also be called T1042RDB. + +The T1042RDB is a Freescale reference board that hosts the T1042 SoC +(and variants). The board is similar to T1040RDB, T1040 is a reduced +personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch). + +The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC. +(a personality of T1040 SoC). The board is similar to T1040RDB but is +designed specially with low power features targeted for Printing Image Market. + +The T1040D4RDB is a Freescale reference board that hosts the T1040 SoC. +The board is re-designed T1040RDB board with following changes : + - Support of DDR4 memory and some enhancements + +The T1042D4RDB is a Freescale reference board that hosts the T1042 SoC. +The board is re-designed T1040RDB board with following changes : + - Support of DDR4 memory + - Support for 0x86 serdes protocol which can support following interfaces + - 2 RGMII's on DTSEC4, DTSEC5 + - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3 + +Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB +------------------------------------------------------------------------- +Board Si Protocol Targeted Market +------------------------------------------------------------------------- +T1040RDB T1040 0x66 Networking +T1040RDB T1042 0x86 Networking +T1042RDB_PI T1042 0x06 Printing & Imaging +T1040D4RDB T1040 0x66 Networking +T1042D4RDB T1042 0x86 Networking + + +T1040 SoC Overview +------------------ +The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA +processor cores with high-performance data path acceleration architecture +and network peripheral interfaces required for networking & telecommunications. + +The T1040/T1042 SoC includes the following function and features: + + - Four e5500 cores, each with a private 256 KB L2 cache + - 256 KB shared L3 CoreNet platform cache (CPC) + - Interconnect CoreNet platform + - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving + support + - Data Path Acceleration Architecture (DPAA) incorporating acceleration + for the following functions: + - Packet parsing, classification, and distribution + - Queue management for scheduling, packet sequencing, and congestion + management + - Cryptography Acceleration (SEC 5.0) + - RegEx Pattern Matching Acceleration (PME 2.2) + - IEEE Std 1588 support + - Hardware buffer management for buffer allocation and deallocation + - Ethernet interfaces + - Integrated 8-port Gigabit Ethernet switch (T1040 only) + - Four 1 Gbps Ethernet controllers + - Two RGMII interfaces or one RGMII and one MII interfaces + - High speed peripheral interfaces + - Four PCI Express 2.0 controllers running at up to 5 GHz + - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation + - Upto two QSGMII interface + - Upto six SGMII interface supporting 1000 Mbps + - One SGMII interface supporting upto 2500 Mbps + - Additional peripheral interfaces + - Two USB 2.0 controllers with integrated PHY + - SD/eSDHC/eMMC + - eSPI controller + - Four I2C controllers + - Four UARTs + - Four GPIO controllers + - Integrated flash controller (IFC) + - LCD and HDMI interface (DIU) with 12 bit dual data rate + - TDM interface + - Multicore programmable interrupt controller (PIC) + - Two 8-channel DMA engines + - Single source clocking implementation + - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) + +T1040 SoC Personalities +------------------------- +T1022 Personality: +T1022 is a reduced personality of T1040 with less core/clusters. + +T1042 Personality: +T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit +Ethernet switch. Rest of the blocks are same as T1040 + + +T1040RDB board Overview +------------------------- + - SERDES Connections, 8 lanes information: + 1: None + 2: SGMII + 3: QSGMII + 4: QSGMII + 5: PCIe1 x1 slot + 6: mini PCIe connector + 7: mini PCIe connector + 8: SATA connector + - DDR Controller + - Supports rates of up to 1600 MHz data-rate + - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types. + - IFC/Local Bus + - NAND flash: 1GB 8-bit NAND flash + - NOR: 128MB 16-bit NOR Flash + - Ethernet + - Two on-board RGMII 10/100/1G ethernet ports. + - CPLD + - Clocks + - System and DDR clock (SYSCLK, “DDRCLK”) + - SERDES clocks + - Power Supplies + - USB + - Supports two USB 2.0 ports with integrated PHYs + - Two type A ports with 5V@1.5A per port. + - SDHC + - SDHC/SDXC connector + - SPI + - On-board 64MB SPI flash + - Other IO + - Two Serial ports + - Four I2C ports + +T1042RDB_PI board Overview +------------------------- + - SERDES Connections, 8 lanes information: + 1, 2, 3, 4 : PCIe x4 slot + 5: mini PCIe connector + 6: mini PCIe connector + 7: NA + 8: SATA connector + - DDR Controller + - Supports rates of up to 1600 MHz data-rate + - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types. + - IFC/Local Bus + - NAND flash: 1GB 8-bit NAND flash + - NOR: 128MB 16-bit NOR Flash + - Ethernet + - Two on-board RGMII 10/100/1G ethernet ports. + - CPLD + - Clocks + - System and DDR clock (SYSCLK, “DDRCLK”) + - SERDES clocks + - Video + - DIU supports video at up to 1280x1024x32bpp + - Power Supplies + - USB + - Supports two USB 2.0 ports with integrated PHYs + - Two type A ports with 5V@1.5A per port. + - SDHC + - SDHC/SDXC connector + - SPI + - On-board 64MB SPI flash + - Other IO + - Two Serial ports + - Four I2C ports + +Memory map +----------- +The addresses in brackets are physical addresses. + +Start Address End Address Description Size +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB +0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB +0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB +0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB +0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB +0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB +0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB +0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB +0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB +0xF_0000_0000 0xF_003F_FFFF DCSR 4MB +0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB +0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB +0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB +0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB +0x0_0000_0000 0x0_ffff_ffff DDR 2GB + + +NOR Flash memory Map +--------------------- + Start End Definition Size +0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB +0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB +0xEC000000 0xEC01FFFF RCW (alt bank) 128KB +0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB +0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB +0xE8000000 0xE801FFFF RCW (current bank) 128KB + + +Various Software configurations/environment variables/commands +-------------------------------------------------------------- +The below commands apply to the board + +1. U-Boot environment variable hwconfig + The default hwconfig is: + hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1: + dr_mode=host,phy_type=utmi + Note: For USB gadget set "dr_mode=peripheral" + +2. FMAN Ucode versions + fsl_fman_ucode_t1040.bin + +3. Switching to alternate bank + Commands for switching to alternate bank. + + 1. To change from vbank0 to vbank4 + => cpld reset altbank (it will boot using vbank4) + + 2.To change from vbank4 to vbank0 + => cpld reset (it will boot using vbank0) + +NAND boot with 2 Stage boot loader +---------------------------------- +PBL initialise the internal SRAM and copy SPL(160KB) in SRAM. +SPL further initialise DDR using SPD and environment variables and copy +U-Boot(768 KB) from flash to DDR. +Finally SPL transer control to U-Boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + + Run time view of SPL framework during boot :- + ----------------------------------------------- + Area | Address | +----------------------------------------------- + Secure boot | 0xFFFC0000 (32KB) | + headers | | + ----------------------------------------------- + GD, BD | 0xFFFC8000 (4KB) | + ----------------------------------------------- + ENV | 0xFFFC9000 (8KB) | + ----------------------------------------------- + HEAP | 0xFFFCB000 (30KB) | + ----------------------------------------------- + STACK | 0xFFFD8000 (22KB) | + ----------------------------------------------- + U-Boot SPL | 0xFFFD8000 (160KB) | + ----------------------------------------------- + +NAND Flash memory Map on T104xRDB +------------------------------------------ + Start End Definition Size +0x000000 0x0FFFFF U-Boot 1MB +0x180000 0x19FFFF U-Boot env 128KB +0x280000 0x29FFFF FMAN Ucode 128KB +0x380000 0x39FFFF QE Firmware 128KB + +SD Card memory Map on T104xRDB +------------------------------------------ + Block #blocks Definition Size +0x008 2048 U-Boot 1MB +0x800 0024 U-Boot env 8KB +0x820 0256 FMAN Ucode 128KB +0x920 0256 QE Firmware 128KB + +SPI Flash memory Map on T104xRDB +------------------------------------------ + Start End Definition Size +0x000000 0x0FFFFF U-Boot 1MB +0x100000 0x101FFF U-Boot env 8KB +0x110000 0x12FFFF FMAN Ucode 128KB +0x130000 0x14FFFF QE Firmware 128KB + +Please note QE Firmware is only valid for T1040RDB + + +Switch Settings for T104xRDB boards: (ON is 0, OFF is 1) +========================================================== +NOR boot SW setting: +SW1: 00010011 +SW2: 10111011 +SW3: 11100001 + +NAND boot SW setting: +SW1: 10001000 +SW2: 00111011 +SW3: 11110001 + +SPI boot SW setting: +SW1: 00100010 +SW2: 10111011 +SW3: 11100001 + +SD boot SW setting: +SW1: 00100000 +SW2: 00111011 +SW3: 11100001 + +Switch Settings for T104xD4RDB boards: (ON is 0, OFF is 1) +============================================================= +NOR boot SW setting: +SW1: 00010011 +SW2: 10111001 +SW3: 11100001 + +NAND boot SW setting: +SW1: 10001000 +SW2: 00111001 +SW3: 11110001 + +SPI boot SW setting: +SW1: 00100010 +SW2: 10111001 +SW3: 11100001 + +SD boot SW setting: +SW1: 00100000 +SW2: 00111001 +SW3: 11100001 + +PBL-based image generation +========================== +Changes only the required register bit in in PBI commands. + +Provides reference code which might needs some +modification as per requirement. +example: +By default PBI_SRC=14 (which is for IFC-NAND/NOR) in rcw.cfg file +which needs to be changed for SPI and SD. + +For SD-boot +============== +1. Set RCW[192:195], PBI_SRC bits as 6 in RCW file (t1040d4_rcw.cfg type files) + +example: + RCW file: board/nxp/t104xrdb/t1040d4_rcw.cfg + +Change +66000002 40000002 ec027000 01000000 +to +66000002 40000002 6c027000 01000000 + +2. SD does not support flush so remove flush from pbl, make changes in + tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000 + with 0x091380c0 + +For SPI-boot +============== +1. Set RCW[192:195], PBI_SRC bits as 5 in RCW file (t1040d4_rcw.cfg type files) + +example: + RCW file: board/nxp/t104xrdb/t1040d4_rcw.cfg + +Change +66000002 40000002 ec027000 01000000 +to +66000002 40000002 5c027000 01000000 + +2. SPI does not support flush so remove flush from pbl, make changes in + tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000 + with 0x091380c0 + +Device tree support and how to enable it for different configs +-------------------------------------------------------------- +Device tree support is available for t1042d4rdb for below mentioned boot, +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CFG_RESET_VECTOR_ADDRESS - 0xffc + +If device tree support is enabled in defconfig, +1. use 'u-boot.bin' for NOR boot. +2. use 'u-boot-with-spl-pbl.bin' for other boot. diff --git a/board/nxp/t104xrdb/cpld.c b/board/nxp/t104xrdb/cpld.c new file mode 100644 index 00000000000..038e40e2fae --- /dev/null +++ b/board/nxp/t104xrdb/cpld.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * Copyright 2014 Freescale Semiconductor + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CFG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map + */ + +#include +#include +#include +#include + +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CFG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CFG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(void) +{ + u8 reg = CPLD_READ(flash_ctl_status); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; + + CPLD_WRITE(flash_ctl_status, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + u8 reg = CPLD_READ(flash_ctl_status); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; + + CPLD_WRITE(flash_ctl_status, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); + printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); + printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); + printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); + printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); + printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); + printf("int_status = 0x%02x\n", CPLD_READ(int_status)); + printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status)); + printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status)); +#if defined(CONFIG_TARGET_T1040D4D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) + printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); +#else + printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status)); +#endif + printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status)); + printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status)); + printf("boot_override = 0x%02x\n", CPLD_READ(boot_override)); + printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1)); + printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2)); + putc('\n'); +} +#endif + +int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset - hard reset to default bank\n" + "cpld reset altbank - reset to alternate bank\n" +#ifdef DEBUG + "cpld dump - display the CPLD registers\n" +#endif + ); diff --git a/board/nxp/t104xrdb/cpld.h b/board/nxp/t104xrdb/cpld.h new file mode 100644 index 00000000000..0384202fbcb --- /dev/null +++ b/board/nxp/t104xrdb/cpld.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/** + * Copyright 2013 Freescale Semiconductor + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +struct cpld_data { + u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */ + u8 hw_ver; /* 0x02 - Hardware Revision Register */ + u8 sw_ver; /* 0x03 - Software Revision register */ + u8 res0[12]; /* 0x04 - 0x0F - not used */ + u8 reset_ctl1; /* 0x10 - Reset control Register1 */ + u8 reset_ctl2; /* 0x11 - Reset control Register2 */ + u8 int_status; /* 0x12 - Interrupt status Register */ + u8 flash_ctl_status; /* 0x13 - Flash control and status register */ + u8 fan_ctl_status; /* 0x14 - Fan control and status register */ +#if defined(CONFIG_TARGET_T1042D4RDB) + u8 int_mask; /* 0x15 - Interrupt mask Register */ +#else + u8 led_ctl_status; /* 0x15 - LED control and status register */ +#endif + u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ + u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ + u8 boot_override; /* 0x18 - Boot override register */ + u8 boot_config1; /* 0x19 - Boot config override register*/ + u8 boot_config2; /* 0x1A - Boot config override register*/ +}; + +/* Pointer to the CPLD register set */ + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value)\ + cpld_write(offsetof(struct cpld_data, reg), value) +#define MISC_CTL_SG_SEL 0x80 +#define MISC_CTL_AURORA_SEL 0x02 +#define MISC_MUX_QE_TDM 0xc0 diff --git a/board/nxp/t104xrdb/ddr.c b/board/nxp/t104xrdb/ddr.c new file mode 100644 index 00000000000..6c066480b46 --- /dev/null +++ b/board/nxp/t104xrdb/ddr.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found\n"); + printf("for data rate %lu MT/s\n", ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " + "wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ +#ifdef CONFIG_SYS_FSL_DDR4 + popts->half_strength_driver_enable = 1; + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x59; +#else + popts->cpo_sample = 0x54; + popts->half_strength_driver_enable = 0; +#endif + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * rtt and rtt_wr override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif +} + +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void) +{ + void __iomem *cpld_base = (void *)CFG_SYS_CPLD_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(cpld_base + 0x17, 0x40); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif + +int dram_init(void) +{ + phys_size_t dram_size; + +#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + puts("Initializing....using SPD\n"); + dram_size = fsl_ddr_sdram(); +#else + dram_size = fsl_ddr_sdram_size(); +#endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_XPL_BUILD) + fsl_dp_resume(); +#endif + + gd->ram_size = dram_size; + + return 0; +} diff --git a/board/nxp/t104xrdb/ddr.h b/board/nxp/t104xrdb/ddr.h new file mode 100644 index 00000000000..f9d667f6174 --- /dev/null +++ b/board/nxp/t104xrdb/ddr.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 + */ +#ifdef CONFIG_SYS_FSL_DDR4 + {2, 1600, 4, 8, 6, 0x07090A0c, 0x0e0f100a}, + {1, 1600, 4, 8, 5, 0x0607080B, 0x0C0C0D09}, +#elif defined(CONFIG_SYS_FSL_DDR3) + {2, 833, 4, 8, 6, 0x06060607, 0x08080807}, + {2, 833, 0, 8, 6, 0x06060607, 0x08080807}, + {2, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09}, + {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09}, + {2, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A}, + {1, 833, 4, 8, 6, 0x06060607, 0x08080807}, + {1, 833, 0, 8, 6, 0x06060607, 0x08080807}, + {1, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09}, + {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09}, + {1, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A}, + {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A}, +#else +#error DDR type not defined +#endif + {} +}; + +#endif + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; diff --git a/board/nxp/t104xrdb/eth.c b/board/nxp/t104xrdb/eth.c new file mode 100644 index 00000000000..c35ec368a45 --- /dev/null +++ b/board/nxp/t104xrdb/eth.c @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/fman.h" + +int board_eth_init(struct bd_info *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info memac_mdio_info; + unsigned int i; + int phy_addr = 0; + + printf("Initializing Fman\n"); + + memac_mdio_info.regs = + (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; + memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fm_memac_mdio_init(bis, &memac_mdio_info); + + /* + * Program on board RGMII, SGMII PHY addresses. + */ + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + + switch (fm_info_get_enet_if(i)) { +#ifdef CONFIG_TARGET_T1042D4RDB + case PHY_INTERFACE_MODE_SGMII: + /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2 + * & DTSEC3 + */ + if (FM1_DTSEC1 == i) + phy_addr = CFG_SYS_SGMII1_PHY_ADDR; + if (FM1_DTSEC2 == i) + phy_addr = CFG_SYS_SGMII2_PHY_ADDR; + if (FM1_DTSEC3 == i) + phy_addr = CFG_SYS_SGMII3_PHY_ADDR; + fm_info_set_phy_address(i, phy_addr); + break; +#endif + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: + if (FM1_DTSEC4 == i) + phy_addr = CFG_SYS_RGMII1_PHY_ADDR; + if (FM1_DTSEC5 == i) + phy_addr = CFG_SYS_RGMII2_PHY_ADDR; + fm_info_set_phy_address(i, phy_addr); + break; + case PHY_INTERFACE_MODE_QSGMII: + fm_info_set_phy_address(i, 0); + break; + case PHY_INTERFACE_MODE_NA: + fm_info_set_phy_address(i, 0); + break; + default: + printf("Fman1: DTSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + fm_info_set_phy_address(i, 0); + break; + } + if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII || + fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NA) + fm_info_set_mdio(i, NULL); + else + fm_info_set_mdio(i, + miiphy_get_dev_by_name( + DEFAULT_FM_MDIO_NAME)); + } + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} diff --git a/board/nxp/t104xrdb/law.c b/board/nxp/t104xrdb/law.c new file mode 100644 index 00000000000..d34641c2397 --- /dev/null +++ b/board/nxp/t104xrdb/law.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#include +#include +#include + +struct law_entry law_table[] = { +#ifdef CONFIG_MTD_NOR_FLASH + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#endif +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CFG_SYS_CPLD_BASE_PHYS + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), +#endif +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/nxp/t104xrdb/spl.c b/board/nxp/t104xrdb/spl.c new file mode 100644 index 00000000000..e02a1f95d4c --- /dev/null +++ b/board/nxp/t104xrdb/spl.c @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright 2013 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/sleep.h" +#include "../common/spl.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, uart_clk; +#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) + u32 porsr1, pinctl; + u32 svr = get_svr(); +#endif + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + +#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) + if (IS_SVR_REV(svr, 1, 0)) { + /* + * There is T1040 SoC issue where NOR, FPGA are inaccessible + * during NAND boot because IFC signals > IFC_AD7 are not + * enabled. This workaround changes RCW source to make all + * signals enabled. + */ + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) + | 0x24800000); + out_be32((unsigned int *)(CFG_SYS_DCSRBAR + 0x20000), + pinctl); + } +#endif + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + +#ifdef CONFIG_DEEP_SLEEP + /* disable the console if boot from deep sleep */ + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + uart_clk = sys_clk * plat_ratio / 2; + + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, + uart_clk / 16 / CONFIG_BAUDRATE); + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + struct bd_info *bd; + + bd = (struct bd_info *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(struct bd_info)); + gd->bd = bd; + + arch_cpu_init(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + + /* relocate environment function pointers etc. */ +#if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_MMC) || \ + defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)SPL_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)SPL_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)SPL_ENV_ADDR); +#endif + gd->env_addr = (ulong)(SPL_ENV_ADDR); + gd->env_valid = ENV_VALID; +#endif + + i2c_init_all(); + + puts("\n\n"); + + dram_init(); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + fsl_spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/nxp/t104xrdb/t1040_nand_rcw.cfg b/board/nxp/t104xrdb/t1040_nand_rcw.cfg new file mode 100644 index 00000000000..3300c184a1a --- /dev/null +++ b/board/nxp/t104xrdb/t1040_nand_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +66000002 80000002 e8106000 01000000 +00000000 00000000 00000000 00032810 +00000000 0342500f 00000000 00000000 diff --git a/board/nxp/t104xrdb/t1040_sd_rcw.cfg b/board/nxp/t104xrdb/t1040_sd_rcw.cfg new file mode 100644 index 00000000000..fd3e8c5bbf5 --- /dev/null +++ b/board/nxp/t104xrdb/t1040_sd_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +66000002 80000002 68106000 01000000 +00000000 00000000 00000000 00032810 +00000000 0342500f 00000000 00000000 diff --git a/board/nxp/t104xrdb/t1040_spi_rcw.cfg b/board/nxp/t104xrdb/t1040_spi_rcw.cfg new file mode 100644 index 00000000000..fccde5e01fe --- /dev/null +++ b/board/nxp/t104xrdb/t1040_spi_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +66000002 80000002 58106000 01000000 +00000000 00000000 00000000 00032810 +00000000 0342500f 00000000 00000000 diff --git a/board/nxp/t104xrdb/t1040d4_nand_rcw.cfg b/board/nxp/t104xrdb/t1040d4_nand_rcw.cfg new file mode 100644 index 00000000000..c1034b3dfa3 --- /dev/null +++ b/board/nxp/t104xrdb/t1040d4_nand_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +66000002 40000002 ec027000 01000000 +00000000 00000000 00000000 00030810 +00000000 0342580f 00000000 00000000 diff --git a/board/nxp/t104xrdb/t1040d4_sd_rcw.cfg b/board/nxp/t104xrdb/t1040d4_sd_rcw.cfg new file mode 100644 index 00000000000..e6f7585bb02 --- /dev/null +++ b/board/nxp/t104xrdb/t1040d4_sd_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +66000002 40000002 6c027000 01000000 +00000000 00000000 00000000 00030810 +00000000 0342580f 00000000 00000000 diff --git a/board/nxp/t104xrdb/t1040d4_spi_rcw.cfg b/board/nxp/t104xrdb/t1040d4_spi_rcw.cfg new file mode 100644 index 00000000000..cde862dff5c --- /dev/null +++ b/board/nxp/t104xrdb/t1040d4_spi_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +66000002 40000002 5c027000 01000000 +00000000 00000000 00000000 00030810 +00000000 0342580f 00000000 00000000 diff --git a/board/nxp/t104xrdb/t1042_nand_rcw.cfg b/board/nxp/t104xrdb/t1042_nand_rcw.cfg new file mode 100644 index 00000000000..db4d52f397d --- /dev/null +++ b/board/nxp/t104xrdb/t1042_nand_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x86 +0c18000e 0e000000 00000000 00000000 +86000002 80000002 ec027000 01000000 +00000000 00000000 00000000 00032810 +00000000 0342500f 00000000 00000000 diff --git a/board/nxp/t104xrdb/t1042_pi_nand_rcw.cfg b/board/nxp/t104xrdb/t1042_pi_nand_rcw.cfg new file mode 100644 index 00000000000..57de89ad0e7 --- /dev/null +++ b/board/nxp/t104xrdb/t1042_pi_nand_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x06 +0c18000e 0e000000 00000000 00000000 +06000002 00400002 e8106000 01000000 +00000000 00000000 00000000 00030810 +00000000 01fe0a06 00000000 00000000 diff --git a/board/nxp/t104xrdb/t1042_pi_sd_rcw.cfg b/board/nxp/t104xrdb/t1042_pi_sd_rcw.cfg new file mode 100644 index 00000000000..bbce9a36930 --- /dev/null +++ b/board/nxp/t104xrdb/t1042_pi_sd_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x06 +0c18000e 0e000000 00000000 00000000 +06000002 00400002 68106000 01000000 +00000000 00000000 00000000 00030810 +00000000 01fe0a06 00000000 00000000 diff --git a/board/nxp/t104xrdb/t1042_pi_spi_rcw.cfg b/board/nxp/t104xrdb/t1042_pi_spi_rcw.cfg new file mode 100644 index 00000000000..b1d8b4c65af --- /dev/null +++ b/board/nxp/t104xrdb/t1042_pi_spi_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x06 +0c18000e 0e000000 00000000 00000000 +06000002 00400002 58106000 01000000 +00000000 00000000 00000000 00030810 +00000000 01fe0a06 00000000 00000000 diff --git a/board/nxp/t104xrdb/t1042_sd_rcw.cfg b/board/nxp/t104xrdb/t1042_sd_rcw.cfg new file mode 100644 index 00000000000..d77bf189b22 --- /dev/null +++ b/board/nxp/t104xrdb/t1042_sd_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x86 +0c18000e 0e000000 00000000 00000000 +86000002 80000002 6c027000 01000000 +00000000 00000000 00000000 00032810 +00000000 0342500f 00000000 00000000 diff --git a/board/nxp/t104xrdb/t1042_spi_rcw.cfg b/board/nxp/t104xrdb/t1042_spi_rcw.cfg new file mode 100644 index 00000000000..e8a3ad12804 --- /dev/null +++ b/board/nxp/t104xrdb/t1042_spi_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x86 +0c18000e 0e000000 00000000 00000000 +86000002 80000002 5c027000 01000000 +00000000 00000000 00000000 00032810 +00000000 0342500f 00000000 00000000 diff --git a/board/nxp/t104xrdb/t1042d4_nand_rcw.cfg b/board/nxp/t104xrdb/t1042d4_nand_rcw.cfg new file mode 100644 index 00000000000..9e0ee2795f8 --- /dev/null +++ b/board/nxp/t104xrdb/t1042d4_nand_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x86 +0c18000e 0e000000 00000000 00000000 +86000002 40000002 ec027000 01000000 +00000000 00000000 00000000 00030810 +00000000 0342500f 00000000 00000000 diff --git a/board/nxp/t104xrdb/t1042d4_sd_rcw.cfg b/board/nxp/t104xrdb/t1042d4_sd_rcw.cfg new file mode 100644 index 00000000000..9d9046d6549 --- /dev/null +++ b/board/nxp/t104xrdb/t1042d4_sd_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x86 +0c18000e 0e000000 00000000 00000000 +86000002 40000002 6c027000 01000000 +00000000 00000000 00000000 00030810 +00000000 0342500f 00000000 00000000 diff --git a/board/nxp/t104xrdb/t1042d4_spi_rcw.cfg b/board/nxp/t104xrdb/t1042d4_spi_rcw.cfg new file mode 100644 index 00000000000..f1ec98932f8 --- /dev/null +++ b/board/nxp/t104xrdb/t1042d4_spi_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x86 +0c18000e 0e000000 00000000 00000000 +86000002 40000002 5c027000 01000000 +00000000 00000000 00000000 00030810 +00000000 0342500f 00000000 00000000 diff --git a/board/nxp/t104xrdb/t104x_pbi.cfg b/board/nxp/t104xrdb/t104x_pbi.cfg new file mode 100644 index 00000000000..51945b47489 --- /dev/null +++ b/board/nxp/t104xrdb/t104x_pbi.cfg @@ -0,0 +1,36 @@ +#PBI commands +#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed +09250100 00000400 +09250108 00002000 +#Software Workaround for errata A-008007 to reset PVR register +09000010 0000000b +09000014 c0000000 +09000018 81d00017 +89020400 a1000000 +091380c0 000f0000 +89020400 00000000 +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 fffc0007 +09010f00 081e000d +09010000 80000000 +#Configure LAW for CPC1 +09000cd0 00000000 +09000cd4 fffc0000 +09000cd8 81000011 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +091380c0 000FFFFF diff --git a/board/nxp/t104xrdb/t104x_pbi_sb.cfg b/board/nxp/t104xrdb/t104x_pbi_sb.cfg new file mode 100644 index 00000000000..98dc8e4c240 --- /dev/null +++ b/board/nxp/t104xrdb/t104x_pbi_sb.cfg @@ -0,0 +1,38 @@ +#PBI commands +#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed +09250100 00000400 +09250108 00002000 +#Software Workaround for errata A-008007 to reset PVR register +09000010 0000000b +09000014 c0000000 +09000018 81d00017 +89020400 a1000000 +091380c0 000f0000 +89020400 00000000 +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 bffc0007 +09010f00 081e000d +09010000 80000000 +#Configure LAW for CPC1 +09000cd0 00000000 +09000cd4 bffc0000 +09000cd8 81000011 +#Configure alternate space +09000010 00000000 +09000014 bf000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +091380c0 000FFFFF +090e0200 bffd0000 +091380c0 000FFFFF diff --git a/board/nxp/t104xrdb/t104xrdb.c b/board/nxp/t104xrdb/t104xrdb.c new file mode 100644 index 00000000000..ef4dfef4965 --- /dev/null +++ b/board/nxp/t104xrdb/t104xrdb.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2023 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/sleep.h" +#include "t104xrdb.h" +#include "cpld.h" + +DECLARE_GLOBAL_DATA_PTR; + +#if CONFIG_IS_ENABLED(DM_SERIAL) +int get_serial_clock(void) +{ + return get_bus_freq(0) / 2; +} +#endif + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + u8 sw; + +#if defined(CONFIG_TARGET_T1042D4RDB) + printf("Board: %sD4RDB\n", cpu->name); +#else + printf("Board: %sRDB\n", cpu->name); +#endif + printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", + CPLD_READ(hw_ver), CPLD_READ(sw_ver)); + + sw = CPLD_READ(flash_ctl_status); + sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); + + printf("vBank: %d\n", sw); + + return 0; +} + +int board_early_init_f(void) +{ +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + return 0; +} + +int board_early_init_r(void) +{ +#ifdef CFG_SYS_FLASH_BASE + const unsigned int flashbase = CFG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); +#endif + + pci_init(); + + return 0; +} + +int misc_init_r(void) +{ + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) >> 24; + + printf("SERDES Reference : 0x%X\n", srds_s1); + + /* select SGMII*/ + if (srds_s1 == 0x86) + CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | + MISC_CTL_SG_SEL); + + /* select SGMII and Aurora*/ + if (srds_s1 == 0x8E) + CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | + MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL); + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = env_get_bootm_low(); + size = env_get_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + +#ifdef CONFIG_HAS_FSL_DR_USB + fsl_fdt_fixup_dr_usb(blob, bd); +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN +#ifndef CONFIG_DM_ETH + fdt_fixup_fman_ethernet(blob); +#endif +#endif + + if (hwconfig("qe-tdm")) + fdt_del_diu(blob); + return 0; +} diff --git a/board/nxp/t104xrdb/t104xrdb.h b/board/nxp/t104xrdb/t104xrdb.h new file mode 100644 index 00000000000..678724c7e2b --- /dev/null +++ b/board/nxp/t104xrdb/t104xrdb.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#ifndef __T104x_RDB_H__ +#define __T104x_RDB_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, struct bd_info *bd); + +#endif diff --git a/board/nxp/t104xrdb/tlb.c b/board/nxp/t104xrdb/tlb.c new file mode 100644 index 00000000000..7b2183da8b0 --- /dev/null +++ b/board/nxp/t104xrdb/tlb.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#include +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) && \ + !defined(CONFIG_NXP_ESBC) + /* + * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the + * SRAM is at 0xfffc0000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256K, 1), + +#elif defined(CONFIG_NXP_ESBC) && defined(CONFIG_XPL_BUILD) + /* + * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot + * the physical address of the SRAM is at 0xbffc0000, + * and virtual address is 0xfffc0000 + */ + + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_VADDR, + CFG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256K, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + +#ifndef CONFIG_XPL_BUILD + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_16M, 1), +#endif +#endif +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_4M, 1), +#endif +#ifdef CFG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef CFG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1), +#endif + +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD) + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 12, BOOKE_PAGESZ_1G, 1), + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000, + CFG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 13, BOOKE_PAGESZ_1G, 1) +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/nxp/t208xqds/Kconfig b/board/nxp/t208xqds/Kconfig new file mode 100644 index 00000000000..a7d1e0a1e30 --- /dev/null +++ b/board/nxp/t208xqds/Kconfig @@ -0,0 +1,15 @@ +if TARGET_T2080QDS + +config SYS_BOARD + default "t208xqds" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "T208xQDS" + +config SRIO_PCIE_BOOT_SLAVE + bool "Boot as a SRIO PCIe slave device" + +endif diff --git a/board/nxp/t208xqds/MAINTAINERS b/board/nxp/t208xqds/MAINTAINERS new file mode 100644 index 00000000000..56911e8fd15 --- /dev/null +++ b/board/nxp/t208xqds/MAINTAINERS @@ -0,0 +1,20 @@ +T208XQDS BOARD +M: Shengzhou Liu +S: Maintained +F: board/nxp/t208xqds/ +F: include/configs/T208xQDS.h +F: configs/T2080QDS_defconfig +F: configs/T2080QDS_NAND_defconfig +F: configs/T2080QDS_SDCARD_defconfig +F: configs/T2080QDS_SPIFLASH_defconfig +F: configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +F: configs/T2081QDS_defconfig +F: configs/T2081QDS_NAND_defconfig +F: configs/T2081QDS_SDCARD_defconfig +F: configs/T2081QDS_SPIFLASH_defconfig +F: configs/T2081QDS_SRIO_PCIE_BOOT_defconfig + +T2080QDS_SECURE_BOOT BOARD +M: Ruchika Gupta +S: Maintained +F: configs/T2080QDS_SECURE_BOOT_defconfig diff --git a/board/nxp/t208xqds/Makefile b/board/nxp/t208xqds/Makefile new file mode 100644 index 00000000000..eb99d921b4a --- /dev/null +++ b/board/nxp/t208xqds/Makefile @@ -0,0 +1,15 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +else +obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o +endif + +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/nxp/t208xqds/README b/board/nxp/t208xqds/README new file mode 100644 index 00000000000..0d80c6901fb --- /dev/null +++ b/board/nxp/t208xqds/README @@ -0,0 +1,292 @@ +The T2080QDS is a high-performance computing evaluation, development and +test platform supporting the T2080 QorIQ Power Architecture processor. + +T2080 SoC Overview +------------------ +The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power +Architecture processor cores with high-performance datapath acceleration +logic and network and peripheral bus interfaces required for networking, +telecom/datacom, wireless infrastructure, and mil/aerospace applications. + +T2080 includes the following functions and features: + - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz + - 2MB L2 cache and 512KB CoreNet platform cache (CPC) + - Hierarchical interconnect fabric + - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving + - Data Path Acceleration Architecture (DPAA) incorporating acceleration + - 16 SerDes lanes up to 10.3125 GHz + - 8 Ethernet interfaces, supporting combinations of the following: + - Up to four 10 Gbps Ethernet MACs + - Up to eight 1 Gbps Ethernet MACs + - Up to four 2.5 Gbps Ethernet MACs + - High-speed peripheral interfaces + - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) + - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz + - Additional peripheral interfaces + - Two serial ATA (SATA 2.0) controllers + - Two high-speed USB 2.0 controllers with integrated PHY + - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) + - Enhanced serial peripheral interface (eSPI) + - Four I2C controllers + - Four 2-pin UARTs or two 4-pin UARTs + - Integrated Flash Controller supporting NAND and NOR flash + - Three eight-channel DMA engines + - Support for hardware virtualization and partitioning enforcement + - QorIQ Platform's Trust Architecture 2.0 + +Differences between T2080 and T2081 +----------------------------------- + Feature T2080 T2081 + 1G Ethernet numbers: 8 6 + 10G Ethernet numbers: 4 2 + SerDes lanes: 16 8 + Serial RapidIO,RMan: 2 no + SATA Controller: 2 no + Aurora: yes no + SoC Package: 896-pins 780-pins + + +T2080QDS feature overview +------------------------- +Processor: + - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz +Memory: + - Single memory controller capable of supporting DDR3 and DDR3-LV devices + - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support +Ethernet interfaces: + - Two 1Gbps RGMII on-board ports + - Four 10GBase-R on-board cages + - 1Gbps/2.5Gbps SGMII Riser card + - 10Gbps XAUI Riser card +Accelerator: + - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC +SerDes: + - 16 lanes up to 10.3125GHz + - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, 10GBase-R and XAUI +IFC: + - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA +eSPI: + - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040) +USB: + - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB) +PCIE: + - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) +SATA: + - Two SATA 2.0 ports on-board +SRIO: + - Two Serial RapidIO 2.0 ports up to 5 GHz +eSDHC: + - Supports SD/SDHC/SDXC/eMMC Card +I2C: + - Four I2C controllers. +UART: + - Dual 4-pins UART serial ports +System Logic: + - QIXIS-II FPGA system controll +Debug Features: + - Support Legacy, COP/JTAG, Aurora, Event and EVT +10GBase-R: + - 10GBase-R is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to + a on-board SFP+ cages, which to house optical module (fiber cable) or + direct attach cable(copper), the copper cable is used to emulate + 10GBASE-KR scenario. + So, for 10GBase-R usage, there are two scenarios, one will use fiber cable, + another will use copper cable. An hwconfig env "fsl_10gkr_copper" is + introduced to indicate a 10GBase-R port will use copper cable, and U-Boot + will fixup the dtb accordingly. + It's used as: fsl_10gkr_copper:<10g_mac_name> + The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they + do not have to be coexist in hwconfig. If a MAC is listed in the env + "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable + will be used by default. + for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in + hwconfig, then both four 10GBase-R ports will use copper cable. + set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two + 10GBase-R ports will use copper cable, the other two 10GBase-R ports will use + fiber cable. +1000BASE-KX(1G-KX): + - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane + runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane + in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration + Register 1 (PCCR1), and U-Boot fixup the dtb for kernel to do proper + initialization. + Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC + 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a + MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1' + stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc. + For ex. set "fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10" in + hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode. + +System Memory map +---------------- + +Start Address End Address Description Size +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB +0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB +0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB +0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB +0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB +0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB +0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB +0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB +0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB +0xF_0000_0000 0xF_003F_FFFF DCSR 4MB +0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB +0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB +0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB +0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB +0x0_0000_0000 0x0_ffff_ffff DDR 4GB + + +128M NOR Flash memory Map +------------------------- +Start Address End Address Definition Max size +0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB +0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB +0xEC000000 0xEC01FFFF RCW (alt bank) 128KB +0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB +0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB +0xE8000000 0xE801FFFF RCW (current bank) 128KB + + +Software configurations and board settings +------------------------------------------ +1. NOR boot: + a. build NOR boot image + $ make T2080QDS_config + $ make + b. program u-boot.bin image to NOR flash + => tftp 1000000 u-boot.bin + => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize + set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot + + Switching between default bank0 and alternate bank4 on NOR flash + To change boot source to vbank4: + by software: run command 'qixis_reset altbank' in U-Boot. + by DIP-switch: set SW6[1:4] = '0100' + + To change boot source to vbank0: + by software: run command 'qixis_reset' in U-Boot. + by DIP-Switch: set SW6[1:4] = '0000' + +2. NAND Boot: + a. build PBL image for NAND boot + $ make T2080QDS_NAND_config + $ make + b. program u-boot-with-spl-pbl.bin to NAND flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => nand erase 0 $filesize + => nand write 1000000 0 $filesize + set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot + +3. SPI Boot: + a. build PBL image for SPI boot + $ make T2080QDS_SPIFLASH_config + $ make + b. program u-boot-with-spl-pbl.bin to SPI flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => sf probe 0 + => sf erase 0 f0000 + => sf write 1000000 0 $filesize + set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot + +4. SD Boot: + a. build PBL image for SD boot + $ make T2080QDS_SDCARD_config + $ make + b. program u-boot-with-spl-pbl.bin to SD/MMC card + => tftp 1000000 u-boot-with-spl-pbl.bin + => mmc write 1000000 8 0x800 + => tftp 1000000 fsl_fman_ucode_T2080_xx.bin + => mmc write 1000000 0x820 80 + set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot + + +2-stage NAND/SPI/SD boot loader +------------------------------- +PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. +SPL further initializes DDR using SPD and environment variables +and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR. +Finally SPL transers control to U-Boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + +Run time view of SPL framework +------------------------------------------------- +|Area | Address | +------------------------------------------------- +|SecureBoot header | 0xFFFC0000 (32KB) | +------------------------------------------------- +|GD, BD | 0xFFFC8000 (4KB) | +------------------------------------------------- +|ENV | 0xFFFC9000 (8KB) | +------------------------------------------------- +|HEAP | 0xFFFCB000 (50KB) | +------------------------------------------------- +|STACK | 0xFFFD8000 (22KB) | +------------------------------------------------- +|U-Boot SPL | 0xFFFD8000 (160KB) | +------------------------------------------------- + +NAND Flash memory Map on T2080QDS +-------------------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF U-Boot img 1MB (2 blocks) +0x100000 0x17FFFF U-Boot env 512KB (1 block) +0x180000 0x1FFFFF FMAN ucode 512KB (1 block) + + +Micro SD Card memory Map on T2080QDS +---------------------------------------------------- +Block #blocks Definition Size +0x008 2048 U-Boot img 1MB +0x800 0016 U-Boot env 8KB +0x820 0128 FMAN ucode 64KB + + +SPI Flash memory Map on T2080QDS +---------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF U-Boot img 1MB +0x100000 0x101FFF U-Boot env 8KB +0x110000 0x11FFFF FMAN ucode 64KB + + +How to update the ucode of Freescale FMAN +----------------------------------------- +=> tftp 1000000 fsl_fman_ucode_t2080_xx.bin +=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize + + +For more details, please refer to T2080QDS User Guide and access +website www.freescale.com and Freescale QorIQ SDK Infocenter document. + +Device tree support and how to enable it for different configs +-------------------------------------------------------------- +Device tree support is available for t2080qds for below mentioned boot, +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. CONFIG_DEFAULT_DEVICE_TREE="t2080qds" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CFG_RESET_VECTOR_ADDRESS - 0xffc + +If device tree support is enabled in defconfig, +1. use 'u-boot.bin' for NOR boot. +2. use 'u-boot-with-spl-pbl.bin' for other boot. diff --git a/board/nxp/t208xqds/ddr.c b/board/nxp/t208xqds/ddr.c new file mode 100644 index 00000000000..77c8ce0c870 --- /dev/null +++ b/board/nxp/t208xqds/ddr.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + /* + * we use identical timing for all slots. If needed, change the code + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; + */ + if (popts->registered_dimm_en) + pbsp = rdimms[0]; + else + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found"); + printf("for data rate %lu MT/s\n", ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " + "wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); + + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x64; +} + +int dram_init(void) +{ + phys_size_t dram_size; + +#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + puts("Initializing....using SPD\n"); + dram_size = fsl_ddr_sdram(); +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + gd->ram_size = dram_size; + + return 0; +} diff --git a/board/nxp/t208xqds/ddr.h b/board/nxp/t208xqds/ddr.h new file mode 100644 index 00000000000..9dd39813bf0 --- /dev/null +++ b/board/nxp/t208xqds/ddr.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ + {2, 1200, 0, 10, 7, 0x0708090a, 0x0b0c0d09}, + {2, 1400, 0, 10, 7, 0x08090a0c, 0x0d0e0f0a}, + {2, 1700, 0, 10, 8, 0x090a0b0c, 0x0e10110c}, + {2, 1900, 0, 10, 8, 0x090b0c0f, 0x1012130d}, + {2, 2140, 0, 10, 8, 0x090b0c0f, 0x1012130d}, + {1, 1200, 0, 10, 7, 0x0808090a, 0x0b0c0c0a}, + {1, 1500, 0, 10, 6, 0x07070809, 0x0a0b0b09}, + {1, 1600, 0, 10, 8, 0x090b0b0d, 0x0d0e0f0b}, + {1, 1700, 0, 8, 8, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 0, 10, 8, 0x090a0c0d, 0x0e0f110c}, + {1, 2140, 0, 8, 8, 0x090a0b0d, 0x0e0f110b}, + {} +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ + /* TODO: need tuning these parameters if RDIMM is used */ + {4, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906}, + {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, + {2, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, + {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, + {1, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, + {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +static const struct board_specific_parameters *rdimms[] = { + rdimm0, +}; +#endif diff --git a/board/nxp/t208xqds/eth_t208xqds.c b/board/nxp/t208xqds/eth_t208xqds.c new file mode 100644 index 00000000000..b55078c8fe1 --- /dev/null +++ b/board/nxp/t208xqds/eth_t208xqds.c @@ -0,0 +1,723 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + * + * Shengzhou Liu + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/qixis.h" +#include "../common/fman.h" +#include "t208xqds_qixis.h" +#include + +#define EMI_NONE 0xFFFFFFFF +#define EMI1_RGMII1 0 +#define EMI1_RGMII2 1 +#define EMI1_SLOT1 2 +#if defined(CONFIG_TARGET_T2080QDS) +#define EMI1_SLOT2 6 +#define EMI1_SLOT3 3 +#define EMI1_SLOT4 4 +#define EMI1_SLOT5 5 +#define EMI2 7 +#endif + +#define PCCR1_SGMIIA_KX_MASK 0x00008000 +#define PCCR1_SGMIIB_KX_MASK 0x00004000 +#define PCCR1_SGMIIC_KX_MASK 0x00002000 +#define PCCR1_SGMIID_KX_MASK 0x00001000 +#define PCCR1_SGMIIE_KX_MASK 0x00000800 +#define PCCR1_SGMIIF_KX_MASK 0x00000400 +#define PCCR1_SGMIIG_KX_MASK 0x00000200 +#define PCCR1_SGMIIH_KX_MASK 0x00000100 + +static int mdio_mux[NUM_FM_PORTS]; + +static const char * const mdio_names[] = { +#if defined(CONFIG_TARGET_T2080QDS) + "T2080QDS_MDIO_RGMII1", + "T2080QDS_MDIO_RGMII2", + "T2080QDS_MDIO_SLOT1", + "T2080QDS_MDIO_SLOT3", + "T2080QDS_MDIO_SLOT4", + "T2080QDS_MDIO_SLOT5", + "T2080QDS_MDIO_SLOT2", + "T2080QDS_MDIO_10GC", +#endif +}; + +/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ +#if defined(CONFIG_TARGET_T2080QDS) +static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; +#endif + +static const char *t208xqds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name = t208xqds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +struct t208xqds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static void t208xqds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + if (muxval < 8) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct t208xqds_mdio *priv = bus->priv; + + t208xqds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct t208xqds_mdio *priv = bus->priv; + + t208xqds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int t208xqds_mdio_reset(struct mii_dev *bus) +{ + struct t208xqds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int t208xqds_mdio_init(char *realbusname, u8 muxval) +{ + struct t208xqds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate t208xqds MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate t208xqds private data\n"); + free(bus); + return -1; + } + + bus->read = t208xqds_mdio_read; + bus->write = t208xqds_mdio_write; + bus->reset = t208xqds_mdio_reset; + strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + return mdio_register(bus); +} + +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + int phy; + char alias[20]; + char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"}; + char buf[32] = "serdes-1,"; + struct fixed_link f_link; + int media_type = 0; + const char *phyconn; + int off; + + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_TARGET_T2080QDS + serdes_corenet_t *srds_regs = + (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; + u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1); +#endif + u32 srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + phy = fm_info_get_phy_address(port); + switch (port) { +#if defined(CONFIG_TARGET_T2080QDS) + case FM1_DTSEC1: + if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx1"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1"); + strcat(buf, "lane-c,"); + strcat(buf, (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIH_KX_MASK); + break; + } + case FM1_DTSEC2: + if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx2"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2"); + strcat(buf, "lane-d,"); + strcat(buf, (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIG_KX_MASK); + break; + } + case FM1_DTSEC9: + if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx9"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9"); + strcat(buf, "lane-a,"); + strcat(buf, (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIE_KX_MASK); + break; + } + case FM1_DTSEC10: + if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx10"); + fdt_status_okay_by_alias(fdt, + "1gkx_pcs_mdio10"); + strcat(buf, "lane-b,"); + strcat(buf, (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIF_KX_MASK); + break; + } + if (mdio_mux[port] == EMI1_SLOT2) { + sprintf(alias, "phy_sgmii_s2_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + } else if (mdio_mux[port] == EMI1_SLOT3) { + sprintf(alias, "phy_sgmii_s3_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + } + break; + case FM1_DTSEC5: + if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx5"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5"); + strcat(buf, "lane-g,"); + strcat(buf, (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIC_KX_MASK); + break; + } + case FM1_DTSEC6: + if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx6"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6"); + strcat(buf, "lane-h,"); + strcat(buf, (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIID_KX_MASK); + break; + } + if (mdio_mux[port] == EMI1_SLOT1) { + sprintf(alias, "phy_sgmii_s1_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot1"); + } else if (mdio_mux[port] == EMI1_SLOT2) { + sprintf(alias, "phy_sgmii_s2_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + } + break; +#endif + default: + break; + } + if (media_type) { + /* set property for 1000BASE-KX in dtb */ + off = fdt_node_offset_by_compat_reg(fdt, + "fsl,fman-memac-mdio", addr + 0x1000); + fdt_setprop_string(fdt, off, "lane-instance", buf); + } + + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { + switch (srds_s1) { + case 0x66: /* 10GBase-R interface */ + case 0x6b: + case 0x6c: + case 0x6d: + case 0x71: + /* + * Check hwconfig to see what is the media type, there + * are two types, fiber or copper, fix the dtb + * accordingly. + */ + switch (port) { + case FM1_10GEC1: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { + /* it's MAC9 */ + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_xfi9"); + fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9"); + strcat(buf, "lane-a,"); + strcat(buf, (char *)lane_mode[1]); + } + break; + case FM1_10GEC2: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) { + /* it's MAC10 */ + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_xfi10"); + fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10"); + strcat(buf, "lane-b,"); + strcat(buf, (char *)lane_mode[1]); + } + break; + case FM1_10GEC3: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) { + /* it's MAC1 */ + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_xfi1"); + fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1"); + strcat(buf, "lane-c,"); + strcat(buf, (char *)lane_mode[1]); + } + break; + case FM1_10GEC4: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) { + /* it's MAC2 */ + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_xfi2"); + fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2"); + strcat(buf, "lane-d,"); + strcat(buf, (char *)lane_mode[1]); + } + break; + default: + return; + } + + if (!media_type) { + phyconn = fdt_getprop(fdt, offset, + "phy-connection-type", + NULL); + if (is_backplane_mode(phyconn)) { + /* Backplane KR mode: skip fixups */ + printf("Interface %d in backplane KR mode\n", + port); + } else { + /* fixed-link for 10GBase-R fiber cable */ + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 10000; + f_link.pause = 0; + f_link.asym_pause = 0; + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", + &f_link, sizeof(f_link)); + } + } else { + /* set property for copper cable */ + off = fdt_node_offset_by_compat_reg(fdt, + "fsl,fman-memac-mdio", addr + 0x1000); + fdt_setprop_string(fdt, off, + "lane-instance", buf); + } + break; + default: + break; + } + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + return; +} + +/* + * This function reads RCW to check if Serdes1{A:H} is configured + * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly + */ +static void initialize_lane_to_slot(void) +{ + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + switch (srds_s1) { +#if defined(CONFIG_TARGET_T2080QDS) + case 0x51: + case 0x5f: + case 0x65: + case 0x6b: + case 0x71: + lane_to_slot[5] = 2; + lane_to_slot[6] = 2; + lane_to_slot[7] = 2; + break; + case 0xa6: + case 0x8e: + case 0x8f: + case 0x82: + case 0x83: + case 0xd3: + case 0xd9: + case 0xcb: + lane_to_slot[6] = 2; + lane_to_slot[7] = 2; + break; + case 0xda: + lane_to_slot[4] = 3; + lane_to_slot[5] = 3; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; +#endif + default: + break; + } +} + +int board_eth_init(struct bd_info *bis) +{ +#if defined(CONFIG_FMAN_ENET) + int i, idx, lane, slot, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + initialize_lane_to_slot(); + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Register the muxing front-ends to the MDIO buses */ + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); +#if defined(CONFIG_TARGET_T2080QDS) + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); +#endif + t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); + t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII) + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); + else + fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR); + + switch (srds_s1) { + case 0x1b: + case 0x1c: + case 0x95: + case 0xa2: + case 0x94: + /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); + break; + case 0x50: + case 0x51: + case 0x5e: + case 0x5f: + case 0x64: + case 0x65: + /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */ + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); + break; + case 0x66: + case 0x67: + /* + * 10GBase-R does not need a PHY to work, but to avoid U-Boot + * use default PHY address which is zero to a MAC when it found + * a MAC has no PHY address, we give a PHY address to 10GBase-R + * MAC, and should not use a real XAUI PHY address, since + * MDIO can access it successfully, and then MDIO thinks + * the XAUI card is used for the 10GBase-R MAC, which will cause + * error. + */ + fm_info_set_phy_address(FM1_10GEC1, 4); + fm_info_set_phy_address(FM1_10GEC2, 5); + fm_info_set_phy_address(FM1_10GEC3, 6); + fm_info_set_phy_address(FM1_10GEC4, 7); + break; + case 0x6a: + case 0x6b: + fm_info_set_phy_address(FM1_10GEC1, 4); + fm_info_set_phy_address(FM1_10GEC2, 5); + fm_info_set_phy_address(FM1_10GEC3, 6); + fm_info_set_phy_address(FM1_10GEC4, 7); + /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + break; + case 0x6c: + case 0x6d: + fm_info_set_phy_address(FM1_10GEC1, 4); + fm_info_set_phy_address(FM1_10GEC2, 5); + /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + break; + case 0x70: + case 0x71: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + /* SGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + break; + case 0xa6: + case 0x8e: + case 0x8f: + case 0x82: + case 0x83: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + /* SGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + break; + case 0xa4: + case 0x96: + case 0x8a: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + break; +#if defined(CONFIG_TARGET_T2080QDS) + case 0xd9: + case 0xd3: + case 0xcb: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + /* SGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + break; +#endif + case 0xf2: + /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); + break; + default: + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + debug("FM1@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + } + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: + if (i == FM1_DTSEC3) + mdio_mux[i] = EMI1_RGMII1; + else if (i == FM1_DTSEC4 || FM1_DTSEC10) + mdio_mux[i] = EMI1_RGMII2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { + idx = i - FM1_10GEC1; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + if (srds_s1 == 0x51) { + lane = serdes_get_first_lane(FSL_SRDS_1, + XAUI_FM1_MAC9 + idx); + } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) { + lane = serdes_get_first_lane(FSL_SRDS_1, + HIGIG_FM1_MAC9 + idx); + } else { + if (i == FM1_10GEC1 || i == FM1_10GEC2) + lane = serdes_get_first_lane(FSL_SRDS_1, + XFI_FM1_MAC9 + idx); + else + lane = serdes_get_first_lane(FSL_SRDS_1, + XFI_FM1_MAC1 + idx); + } + + if (lane < 0) + break; + mdio_mux[i] = EMI2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + + if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) || + (srds_s1 == 0x6a) || (srds_s1 == 0x70) || + (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || + (srds_s1 == 0x71)) { + /* As 10GBase-R is in cage intead of a slot, so + * ensure doesn't disable the corresponding port + */ + break; + } + + slot = lane_to_slot[lane]; + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/nxp/t208xqds/law.c b/board/nxp/t208xqds/law.c new file mode 100644 index 00000000000..287f4650e05 --- /dev/null +++ b/board/nxp/t208xqds/law.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef QIXIS_BASE_PHYS + SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif +#ifdef CFG_SYS_DCSRBAR_PHYS + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/nxp/t208xqds/spl.c b/board/nxp/t208xqds/spl.c new file mode 100644 index 00000000000..44ad4e68d9f --- /dev/null +++ b/board/nxp/t208xqds/spl.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright 2013 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/qixis.h" +#include "t208xqds_qixis.h" +#include "../common/spl.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#if defined(CONFIG_SPL_MMC_BOOT) + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + struct bd_info *bd; + + bd = (struct bd_info *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(struct bd_info)); + gd->bd = bd; + + arch_cpu_init(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; + +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)SPL_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)SPL_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)SPL_ENV_ADDR); +#endif + + gd->env_addr = (ulong)(SPL_ENV_ADDR); + gd->env_valid = ENV_VALID; + + i2c_init_all(); + + dram_init(); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + fsl_spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/nxp/t208xqds/t2080_nand_rcw.cfg b/board/nxp/t208xqds/t2080_nand_rcw.cfg new file mode 100644 index 00000000000..52a1652a222 --- /dev/null +++ b/board/nxp/t208xqds/t2080_nand_rcw.cfg @@ -0,0 +1,16 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 + +#For T2080 v1.0 +#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s +#12100017 15000000 00000000 00000000 +#66150002 00008400 e8104000 c1000000 +#00000000 00000000 00000000 000307fc +#00000000 00000000 00000000 00000004 + +#For T2080 v1.1 +#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s +0c070012 0e000000 00000000 00000000 +66150002 00000000 e8104000 c1000000 +00000000 00000000 00000000 000307fc +00000000 00000000 00000000 00000004 diff --git a/board/nxp/t208xqds/t2080_sd_rcw.cfg b/board/nxp/t208xqds/t2080_sd_rcw.cfg new file mode 100644 index 00000000000..73f53faa259 --- /dev/null +++ b/board/nxp/t208xqds/t2080_sd_rcw.cfg @@ -0,0 +1,16 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 + +#For T2080 v1.0 +#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s +#12100017 15000000 00000000 00000000 +#66150002 00008400 e8104000 c1000000 +#00000000 00000000 00000000 000307fc +#00000000 00000000 00000000 00000004 + +#For T2080 v1.1 +#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s +0c070012 0e000000 00000000 00000000 +66150002 00000000 68104000 c1000000 +00000000 00000000 00000000 000307fc +00000000 00000000 00000000 00000004 diff --git a/board/nxp/t208xqds/t2080_spi_rcw.cfg b/board/nxp/t208xqds/t2080_spi_rcw.cfg new file mode 100644 index 00000000000..8474c8ef7ce --- /dev/null +++ b/board/nxp/t208xqds/t2080_spi_rcw.cfg @@ -0,0 +1,16 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 + +#For T2080 v1.0 +#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s +#12100017 15000000 00000000 00000000 +#66150002 00008400 e8104000 c1000000 +#00000000 00000000 00000000 000307fc +#00000000 00000000 00000000 00000004 + +#For T2080 v1.1 +#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s +0c070012 0e000000 00000000 00000000 +66150002 00000000 58104000 c1000000 +00000000 00000000 00000000 000307fc +00000000 00000000 00000000 00000004 diff --git a/board/nxp/t208xqds/t2081_nand_rcw.cfg b/board/nxp/t208xqds/t2081_nand_rcw.cfg new file mode 100644 index 00000000000..a2d5ecf4adc --- /dev/null +++ b/board/nxp/t208xqds/t2081_nand_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +#Default SerDes Protocol: 0x6C +#Core/DDR: 1533Mhz/2133MT/s +12100017 15000000 00000000 00000000 +6c000002 00008000 e8104000 c1000000 +00000000 00000000 00000000 000307fc +00000000 00000000 00000000 00000004 diff --git a/board/nxp/t208xqds/t2081_sd_rcw.cfg b/board/nxp/t208xqds/t2081_sd_rcw.cfg new file mode 100644 index 00000000000..daced6796ba --- /dev/null +++ b/board/nxp/t208xqds/t2081_sd_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +#Default SerDes Protocol: 0x6C +#Core/DDR: 1533Mhz/2133MT/s +12100017 15000000 00000000 00000000 +6c000002 00008000 68104000 c1000000 +00000000 00000000 00000000 000307fc +00000000 00000000 00000000 00000004 diff --git a/board/nxp/t208xqds/t2081_spi_rcw.cfg b/board/nxp/t208xqds/t2081_spi_rcw.cfg new file mode 100644 index 00000000000..79ba1f1ab77 --- /dev/null +++ b/board/nxp/t208xqds/t2081_spi_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +#Default SerDes Protocol: 0x6C +#Core/DDR: 1533Mhz/2133MT/s +12100017 15000000 00000000 00000000 +6c000002 00008000 58104000 c1000000 +00000000 00000000 00000000 000307fc +00000000 00000000 00000000 00000004 diff --git a/board/nxp/t208xqds/t208x_pbi.cfg b/board/nxp/t208xqds/t208x_pbi.cfg new file mode 100644 index 00000000000..43be8a864e3 --- /dev/null +++ b/board/nxp/t208xqds/t208x_pbi.cfg @@ -0,0 +1,40 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.pblimage for more details about how-to configure +# and create PBL boot image +# + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#512KB SRAM +09010100 00000000 +09010104 fff80009 +09010f00 08000000 +#enable CPC1 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff80000 +09000d08 81000012 +#Initialize eSPI controller, default configuration is slow for eSPI to +#load data, this configuration comes from u-boot eSPI driver. +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Errata for slowing down the MDC clock to make it <= 2.5 MHZ +094fc030 00008148 +094fd030 00008148 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Flush PBL data +091380c0 00100000 diff --git a/board/nxp/t208xqds/t208xqds.c b/board/nxp/t208xqds/t208xqds.c new file mode 100644 index 00000000000..5e71da0e163 --- /dev/null +++ b/board/nxp/t208xqds/t208xqds.c @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2009-2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/i2c_mux.h" + +#include "../common/qixis.h" +#include "../common/vsc3316_3308.h" +#include "../common/vid.h" +#include "t208xqds.h" +#include "t208xqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + char buf[64]; + u8 sw; + struct cpu_type *cpu = gd->arch.cpu; + static const char *freq[4] = { + "100.00MHZ(from 8T49N222A)", "125.00MHz", + "156.25MHZ", "100.00MHz" + }; + + printf("Board: %sQDS, ", cpu->name); + sw = QIXIS_READ(arch); + printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4); + printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); + +#ifdef CONFIG_SDCARD + puts("SD/MMC\n"); +#elif CONFIG_SPIFLASH + puts("SPI\n"); +#else + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank%d\n", sw); + else if (sw == 0x8) + puts("Promjet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); +#endif + + printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver), + qixis_read_tag(buf), (int)qixis_read_minor()); + /* the timestamp string contains "\n" at the end */ + printf(" on %s", qixis_read_time(buf)); + + puts("SERDES Reference Clocks:\n"); + sw = QIXIS_READ(brdcfg[2]); + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6], + freq[(sw >> 4) & 0x3]); + printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2], + freq[sw & 0x3]); + + return 0; +} + +int i2c_multiplexer_select_vid_channel(u8 channel) +{ + return select_i2c_ch_pca9547(channel, 0); +} + +int brd_mux_lane_to_slot(void) +{ + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1; + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; +#if defined(CONFIG_TARGET_T2080QDS) + u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; +#endif + + switch (srds_prtcl_s1) { + case 0: + /* SerDes1 is not enabled */ + break; +#if defined(CONFIG_TARGET_T2080QDS) + case 0x1b: + case 0x1c: + case 0xa2: + /* SD1(A:D) => SLOT3 SGMII + * SD1(G:H) => SLOT1 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x1a); + break; + case 0x94: + case 0x95: + /* SD1(A:B) => SLOT3 SGMII@1.25bps + * SD1(C:D) => SFP Module, SGMII@3.125bps + * SD1(E:H) => SLOT1 SGMII@1.25bps + */ + case 0x96: + /* SD1(A:B) => SLOT3 SGMII@1.25bps + * SD1(C) => SFP Module, SGMII@3.125bps + * SD1(D) => SFP Module, SGMII@1.25bps + * SD1(E:H) => SLOT1 PCIe4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0x3a); + break; + case 0x50: + case 0x51: + /* SD1(A:D) => SLOT3 XAUI + * SD1(E) => SLOT1 PCIe4 + * SD1(F:H) => SLOT2 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x15); + break; + case 0x66: + case 0x67: + /* SD1(A:D) => 10GBase-R cage + * SD1(E:H) => SLOT1 PCIe4 + */ + QIXIS_WRITE(brdcfg[12], 0xfe); + break; + case 0x6a: + case 0x6b: + /* SD1(A:D) => 10GBase-R cage + * SD1(E) => SLOT1 PCIe4 + * SD1(F:H) => SLOT2 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0xf1); + break; + case 0x6c: + case 0x6d: + /* SD1(A:B) => 10GBase-R cage + * SD1(C:D) => SLOT3 SGMII + * SD1(E:H) => SLOT1 PCIe4 + */ + QIXIS_WRITE(brdcfg[12], 0xda); + break; + case 0x6e: + /* SD1(A:B) => SFP Module, 10GBase-R + * SD1(C:D) => SLOT3 SGMII + * SD1(E:F) => SLOT1 PCIe4 x2 + * SD1(G:H) => SLOT2 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0xd9); + break; + case 0xda: + /* SD1(A:H) => SLOT3 PCIe3 x8 + */ + QIXIS_WRITE(brdcfg[12], 0x0); + break; + case 0xc8: + /* SD1(A) => SLOT3 PCIe3 x1 + * SD1(B) => SFP Module, SGMII@1.25bps + * SD1(C:D) => SFP Module, SGMII@3.125bps + * SD1(E:F) => SLOT1 PCIe4 x2 + * SD1(G:H) => SLOT2 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x79); + break; + case 0xab: + /* SD1(A:D) => SLOT3 PCIe3 x4 + * SD1(E:H) => SLOT1 PCIe4 x4 + */ + QIXIS_WRITE(brdcfg[12], 0x1a); + break; +#endif + default: + printf("WARNING: unsupported for SerDes1 Protocol %d\n", + srds_prtcl_s1); + return -1; + } + +#ifdef CONFIG_TARGET_T2080QDS + switch (srds_prtcl_s2) { + case 0: + /* SerDes2 is not enabled */ + break; + case 0x01: + case 0x02: + /* SD2(A:H) => SLOT4 PCIe1 */ + QIXIS_WRITE(brdcfg[13], 0x10); + break; + case 0x15: + case 0x16: + /* + * SD2(A:D) => SLOT4 PCIe1 + * SD2(E:F) => SLOT5 PCIe2 + * SD2(G:H) => SATA1,SATA2 + */ + QIXIS_WRITE(brdcfg[13], 0xb0); + break; + case 0x18: + /* + * SD2(A:D) => SLOT4 PCIe1 + * SD2(E:F) => SLOT5 Aurora + * SD2(G:H) => SATA1,SATA2 + */ + QIXIS_WRITE(brdcfg[13], 0x78); + break; + case 0x1f: + /* + * SD2(A:D) => SLOT4 PCIe1 + * SD2(E:H) => SLOT5 PCIe2 + */ + QIXIS_WRITE(brdcfg[13], 0xa0); + break; + case 0x29: + case 0x2d: + case 0x2e: + /* + * SD2(A:D) => SLOT4 SRIO2 + * SD2(E:H) => SLOT5 SRIO1 + */ + QIXIS_WRITE(brdcfg[13], 0xa0); + break; + case 0x36: + /* + * SD2(A:D) => SLOT4 SRIO2 + * SD2(E:F) => Aurora + * SD2(G:H) => SATA1,SATA2 + */ + QIXIS_WRITE(brdcfg[13], 0x78); + break; + default: + printf("WARNING: unsupported for SerDes2 Protocol %d\n", + srds_prtcl_s2); + return -1; + } +#endif + return 0; +} + +static void esdhc_adapter_card_ident(void) +{ + u8 card_id, value; + + card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; + + switch (card_id) { + case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: + value = QIXIS_READ(brdcfg[5]); + value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); + QIXIS_WRITE(brdcfg[5], value); + break; + case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: + value = QIXIS_READ(pwr_ctl[1]); + value |= QIXIS_EVDD_BY_SDHC_VS; + QIXIS_WRITE(pwr_ctl[1], value); + break; + case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: + value = QIXIS_READ(brdcfg[5]); + value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); + QIXIS_WRITE(brdcfg[5], value); + break; + default: + break; + } +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CFG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + /* Disable remote I2C connection to qixis fpga */ + QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); + + /* + * Adjust core voltage according to voltage ID + * This function changes I2C mux to channel 2. + */ + if (adjust_vdd(0)) + printf("Warning: Adjusting core voltage failed.\n"); + + brd_mux_lane_to_slot(); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); + esdhc_adapter_card_ident(); + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); +#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT + /* use accurate clock measurement */ + int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]); + int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); + u32 val; + + val = freq * base; + if (val) { + debug("SYS Clock measurement is: %d\n", val); + return val; + } else { + printf("Warning: SYS clock measurement is invalid, "); + printf("using value from brdcfg1.\n"); + } +#endif + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); +#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT + /* use accurate clock measurement */ + int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]); + int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); + u32 val; + + val = freq * base; + if (val) { + debug("DDR Clock measurement is: %d\n", val); + return val; + } else { + printf("Warning: DDR clock measurement is invalid, "); + printf("using value from brdcfg1.\n"); + } +#endif + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +int misc_init_r(void) +{ + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = env_get_bootm_low(); + size = env_get_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fsl_fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN +#ifndef CONFIG_DM_ETH + fdt_fixup_fman_ethernet(blob); +#endif + fdt_fixup_board_enet(blob); +#endif + + return 0; +} diff --git a/board/nxp/t208xqds/t208xqds.h b/board/nxp/t208xqds/t208xqds.h new file mode 100644 index 00000000000..50ebb6f6f98 --- /dev/null +++ b/board/nxp/t208xqds/t208xqds.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2011-2013 Freescale Semiconductor, Inc. + */ + +#ifndef __CORENET_DS_H__ +#define __CORENET_DS_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, struct bd_info *bd); + +#endif diff --git a/board/nxp/t208xqds/t208xqds_qixis.h b/board/nxp/t208xqds/t208xqds_qixis.h new file mode 100644 index 00000000000..66651422031 --- /dev/null +++ b/board/nxp/t208xqds/t208xqds_qixis.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#ifndef __T208xQDS_QIXIS_H__ +#define __T208xQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for T208xQDS */ + +#define QIXIS_SRDS1CLK_122 0x5a +#define QIXIS_SRDS1CLK_125 0x5e + +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xE0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */ + +#define BRDCFG9_SFP_TX_EN 0x10 + +#define BRDCFG12_SD3EN_MASK 0x20 +#define BRDCFG12_SD3MX_MASK 0x08 +#define BRDCFG12_SD3MX_SLOT5 0x08 +#define BRDCFG12_SD3MX_SLOT6 0x00 +#define BRDCFG12_SD4EN_MASK 0x04 +#define BRDCFG12_SD4MX_MASK 0x03 +#define BRDCFG12_SD4MX_SLOT7 0x02 +#define BRDCFG12_SD4MX_SLOT8 0x01 +#define BRDCFG12_SD4MX_AURO_SATA 0x00 +#endif diff --git a/board/nxp/t208xqds/tlb.c b/board/nxp/t208xqds/tlb.c new file mode 100644 index 00000000000..08c140afc68 --- /dev/null +++ b/board/nxp/t208xqds/tlb.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2008-2013 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#include +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) + /* + * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the + * space is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + +#ifndef CONFIG_XPL_BUILD + /* *I*G* - PCIe 1, 0x80000000 */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_512M, 1), + + /* *I*G* - PCIe 2, 0xa0000000 */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE2_MEM_VIRT, CFG_SYS_PCIE2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCIe 3, 0xb0000000 */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE3_MEM_VIRT, CFG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCIe 4, 0xc0000000 */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_16M, 1), +#endif +#endif +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_32M, 1), +#endif +#ifdef CFG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef QIXIS_BASE_PHYS + SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 17, BOOKE_PAGESZ_4K, 1), +#endif +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE + /* + * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for + * fetching ucode and ENV from master + */ + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 18, BOOKE_PAGESZ_1M, 1), +#endif + +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD) + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 19, BOOKE_PAGESZ_2G, 1) +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/nxp/t208xrdb/Kconfig b/board/nxp/t208xrdb/Kconfig new file mode 100644 index 00000000000..cf3c73f9100 --- /dev/null +++ b/board/nxp/t208xrdb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_T2080RDB + +config SYS_BOARD + default "t208xrdb" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "T208xRDB" + +config T2080RDB_REV_D + bool "Support for T2080RDB revisions D and up" + +endif diff --git a/board/nxp/t208xrdb/MAINTAINERS b/board/nxp/t208xrdb/MAINTAINERS new file mode 100644 index 00000000000..db58c79c254 --- /dev/null +++ b/board/nxp/t208xrdb/MAINTAINERS @@ -0,0 +1,14 @@ +T208XRDB BOARD +M: Shengzhou Liu +S: Maintained +F: board/nxp/t208xrdb/ +F: include/configs/T208xRDB.h +F: configs/T2080RDB_defconfig +F: configs/T2080RDB_NAND_defconfig +F: configs/T2080RDB_SDCARD_defconfig +F: configs/T2080RDB_SPIFLASH_defconfig +F: configs/T2080RDB_SRIO_PCIE_BOOT_defconfig +F: configs/T2080RDB_revD_defconfig +F: configs/T2080RDB_revD_NAND_defconfig +F: configs/T2080RDB_revD_SDCARD_defconfig +F: configs/T2080RDB_revD_SPIFLASH_defconfig diff --git a/board/nxp/t208xrdb/Makefile b/board/nxp/t208xrdb/Makefile new file mode 100644 index 00000000000..e5ef250c8b2 --- /dev/null +++ b/board/nxp/t208xrdb/Makefile @@ -0,0 +1,15 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +else +obj-$(CONFIG_TARGET_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o +endif + +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/nxp/t208xrdb/README b/board/nxp/t208xrdb/README new file mode 100644 index 00000000000..533054bfe19 --- /dev/null +++ b/board/nxp/t208xrdb/README @@ -0,0 +1,288 @@ +T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC. +It can work in two mode: standalone mode and PCIe endpoint mode. + +T2080 SoC Overview +------------------ +The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power +Architecture processor cores with high-performance datapath acceleration +logic and network and peripheral bus interfaces required for networking, +telecom/datacom, wireless infrastructure, and mil/aerospace applications. + +T2080 includes the following functions and features: + - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz + - 2MB L2 cache and 512KB CoreNet platform cache (CPC) + - Hierarchical interconnect fabric + - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving + - Data Path Acceleration Architecture (DPAA) incorporating acceleration + - 16 SerDes lanes up to 10.3125 GHz + - 8 Ethernet interfaces, supporting combinations of the following: + - Up to four 10 Gbps Ethernet MACs + - Up to eight 1 Gbps Ethernet MACs + - Up to four 2.5 Gbps Ethernet MACs + - High-speed peripheral interfaces + - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) + - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz + - Additional peripheral interfaces + - Two serial ATA (SATA 2.0) controllers + - Two high-speed USB 2.0 controllers with integrated PHY + - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) + - Enhanced serial peripheral interface (eSPI) + - Four I2C controllers + - Four 2-pin UARTs or two 4-pin UARTs + - Integrated Flash Controller supporting NAND and NOR flash + - Three eight-channel DMA engines + - Support for hardware virtualization and partitioning enforcement + - QorIQ Platform's Trust Architecture 2.0 + +User Guide +---------- +The T2080RDB User Guide is available on the web at +https://www.nxp.com/docs/en/user-guide/T2080RDBPCUG.pdf + +Differences between T2080 and T2081 +----------------------------------- + Feature T2080 T2081 + 1G Ethernet numbers: 8 6 + 10G Ethernet numbers: 4 2 + SerDes lanes: 16 8 + Serial RapidIO,RMan: 2 no + SATA Controller: 2 no + Aurora: yes no + SoC Package: 896-pins 780-pins + + +T2080PCIe-RDB board Overview +---------------------------- + - SERDES Configuration + - SerDes-1 Lane A-B: to two 10GBase-R fiber (MAC9 & MAC10) + - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) + - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) + - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) + - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2) + - SerDes-2 Lane G-H: to SATA1 & SATA2 + - Ethernet + - Two on-board 10M/100M/1G RGMII ethernet ports + - Two on-board 10GBase-R fiber ports + - Two on-board 10Gbps Base-T copper ports + - DDR Memory + - Supports 72bit 4GB DDR3-LP SODIMM + - PCIe + - One PCIe x4 gold-finger + - One PCIe x4 connector + - One PCIe x2 end-point device (C293 Crypto co-processor) + - IFC/Local Bus + - NOR: 128MB 16-bit NOR Flash + - NAND: 1GB 8-bit NAND flash + - CPLD: for system controlling with programable header on-board + - SATA + - Two SATA 2.0 onnectors on-board + - USB + - Supports two USB 2.0 ports with integrated PHYs + - Two type A ports with 5V@1.5A per port. + - SDHC + - one TF-card connector on-board + - SPI + - On-board 64MB SPI flash + - Other + - Two Serial ports + - Four I2C ports + + +System Memory map +----------------- +Start Address End Address Description Size +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB +0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB +0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB +0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB +0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB +0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB +0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB +0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB +0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB +0xF_0000_0000 0xF_003F_FFFF DCSR 4MB +0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB +0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB +0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB +0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB +0x0_0000_0000 0x0_ffff_ffff DDR 4GB + + +128M NOR Flash memory Map +------------------------- +Start Address End Address Definition Max size +0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB +0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB +0xEFE00000 0xEFE3FFFF PHY CS4315 firmware 256KB +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB +0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB +0xEC000000 0xEC01FFFF RCW (alt bank) 128KB +0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB +0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB +0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB +0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB +0xE8000000 0xE801FFFF RCW (current bank) 128KB + + +T2080PCIe-RDB Ethernet Port Map +------------------------------- +Label In Uboot In Linux FMan Address Comments PHY +ETH0 FM1@GTEC1 fm1-mac9 0xfe4f0000 10G SFP+ (CS4315) +ETH1 FM1@GTEC2 fm1-mac10 0xfe4f2000 10G SFP+ (CS4315) +ETH2 FM1@GTEC3 fm1-mac1 0xfe4e0000 10G Base-T (AQ1202) +ETH3 FM1@GTEC4 fm1-mac2 0xfe4e2000 10G Base-T (AQ1202) +ETH4 FM1@DTSEC3 fm1-mac3 0xfe4e4000 1G RGMII (RTL8211E) +ETH5 FM1@DTSEC4 fm1-mac4 0xfe4e6000 1G RGMII (RTL8211E) + + +T2080PCIe-RDB Default DIP-Switch setting +---------------------------------------- +SW1[1:8] = '00010011' +SW2[1:8] = '10111111' +SW3[1:8] = '11100001' + +Software configurations and board settings +------------------------------------------ +1. NOR boot: + a. build NOR boot image + $ make T2080RDB_config + $ make + b. program u-boot.bin image to NOR flash + => tftp 1000000 u-boot.bin + => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize + set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot + + Switching between default bank and alternate bank on NOR flash + To change boot source to vbank4: + via software: run command 'cpld reset altbank' in U-Boot. + via DIP-switch: set SW3[5:7] = '100' + + To change boot source to vbank0: + via software: run command 'cpld reset' in U-Boot. + via DIP-Switch: set SW3[5:7] = '000' + +2. NAND Boot: + a. build PBL image for NAND boot + $ make T2080RDB_NAND_config + $ make + b. program u-boot-with-spl-pbl.bin to NAND flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => nand erase 0 d0000 + => nand write 1000000 0 $filesize + set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot + +3. SPI Boot: + a. build PBL image for SPI boot + $ make T2080RDB_SPIFLASH_config + $ make + b. program u-boot-with-spl-pbl.bin to SPI flash + => tftp 1000000 u-boot-with-spl-pbl.bin + => sf probe 0 + => sf erase 0 d0000 + => sf write 1000000 0 $filesize + set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot + +4. SD Boot: + a. build PBL image for SD boot + $ make T2080RDB_SDCARD_config + $ make + b. program u-boot-with-spl-pbl.bin to micro-SD/TF card + => tftp 1000000 u-boot-with-spl-pbl.bin + => mmc write 1000000 8 0x800 + set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot + + +2-stage NAND/SPI/SD boot loader +------------------------------- +PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. +SPL further initializes DDR using SPD and environment variables +and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR. +Finally SPL transers control to U-Boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + +Run time view of SPL framework +------------------------------------------------- +|Area | Address | +------------------------------------------------- +|SecureBoot header | 0xFFFC0000 (32KB) | +------------------------------------------------- +|GD, BD | 0xFFFC8000 (4KB) | +------------------------------------------------- +|ENV | 0xFFFC9000 (8KB) | +------------------------------------------------- +|HEAP | 0xFFFCB000 (50KB) | +------------------------------------------------- +|STACK | 0xFFFD8000 (22KB) | +------------------------------------------------- +|U-Boot SPL | 0xFFFD8000 (160KB) | +------------------------------------------------- + +NAND Flash memory Map on T2080RDB +-------------------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF U-Boot img 1MB (2 blocks) +0x100000 0x17FFFF U-Boot env 512KB (1 block) +0x180000 0x1FFFFF FMAN ucode 512KB (1 block) +0x200000 0x27FFFF CS4315 ucode 512KB (1 block) + + +Micro SD Card memory Map on T2080RDB +---------------------------------------------------- +Block #blocks Definition Size +0x008 2048 U-Boot img 1MB +0x800 0016 U-Boot env 8KB +0x820 0128 FMAN ucode 64KB +0x8a0 0512 CS4315 ucode 256KB + + +SPI Flash memory Map on T2080RDB +---------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF U-Boot img 1MB +0x100000 0x101FFF U-Boot env 8KB +0x110000 0x11FFFF FMAN ucode 64KB +0x120000 0x15FFFF CS4315 ucode 256KB + + +How to update the ucode of Cortina CS4315/CS4340 10G PHY +-------------------------------------------------------- +=> tftp 1000000 CS4315-CS4340-PHY-ucode.txt +=> pro off all;era 0xefe00000 0xefefffff;cp.b 1000000 0xefe00000 $filesize + + +How to update the ucode of Freescale FMAN +----------------------------------------- +=> tftp 1000000 fsl_fman_ucode_t2080_r1.0.bin +=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize + + +For more details, please refer to T2080PCIe-RDB User Guide and access +website www.freescale.com and Freescale QorIQ SDK Infocenter document. + +Device tree support and how to enable it for different configs +-------------------------------------------------------------- +Device tree support is available for t2080rdb for below mentioned boot, +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CFG_RESET_VECTOR_ADDRESS - 0xffc + +If device tree support is enabled in defconfig, +1. use 'u-boot.bin' for NOR boot. +2. use 'u-boot-with-spl-pbl.bin' for other boot. diff --git a/board/nxp/t208xrdb/cpld.c b/board/nxp/t208xrdb/cpld.c new file mode 100644 index 00000000000..838d88d977e --- /dev/null +++ b/board/nxp/t208xrdb/cpld.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor + * + * Freescale T2080RDB board-specific CPLD controlling supports. + */ + +#include +#include +#include +#include +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CFG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CFG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/* Set the boot bank to the alternate bank */ +void cpld_set_altbank(void) +{ + u8 reg = CPLD_READ(flash_csr); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; + CPLD_WRITE(flash_csr, reg); + CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET); +} + +/* Set the boot bank to the default bank */ +void cpld_set_defbank(void) +{ + u8 reg = CPLD_READ(flash_csr); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; + CPLD_WRITE(flash_csr, reg); + CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET); +} + +int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); + } else { + rc = cmd_usage(cmdtp); + } + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset: reset to default bank\n" + "cpld reset altbank: reset to alternate bank\n" +); diff --git a/board/nxp/t208xrdb/cpld.h b/board/nxp/t208xrdb/cpld.h new file mode 100644 index 00000000000..3139c2b85fd --- /dev/null +++ b/board/nxp/t208xrdb/cpld.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor + * Copyright 2021 NXP + */ + +/* + * CPLD register set of T2080RDB board-specific. + */ +struct cpld_data { + u8 chip_id1; /* 0x00 - Chip ID1 register */ + u8 chip_id2; /* 0x01 - Chip ID2 register */ + u8 hw_ver; /* 0x02 - Hardware Revision Register */ + u8 sw_ver; /* 0x03 - Software Revision register */ + u8 res0[12]; /* 0x04 - 0x0F - not used */ + u8 reset_ctl; /* 0x10 - Reset control Register */ + u8 flash_csr; /* 0x11 - Flash control and status register */ + u8 thermal_csr; /* 0x12 - Thermal control and status register */ + u8 led_csr; /* 0x13 - LED control and status register */ + u8 sfp_csr; /* 0x14 - SFP+ control and status register */ + u8 misc_csr; /* 0x15 - Misc control and status register */ + u8 boot_or; /* 0x16 - Boot config override register */ + u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */ + u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */ +}; + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value) \ + cpld_write(offsetof(struct cpld_data, reg), value) + +/* CPLD on IFC */ +#define CPLD_LBMAP_MASK 0x3F +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_OVERRIDE 0x40 +#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ +#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */ +#define CPLD_LBMAP_RESET 0xFF +#define CPLD_LBMAP_SHIFT 0x03 +#define CPLD_BOOT_SEL 0x80 + +/* RSTCON Register */ +#define CPLD_RSTCON_EDC_RST 0x04 + +/* MISCCSR Register */ +#define CPLD_MISC_POR_EN 0x30 diff --git a/board/nxp/t208xrdb/ddr.c b/board/nxp/t208xrdb/ddr.c new file mode 100644 index 00000000000..cc9586eaa14 --- /dev/null +++ b/board/nxp/t208xrdb/ddr.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found"); + printf("for data rate %lu MT/s\n", ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " + "wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); + + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x54; +} + +int dram_init(void) +{ + phys_size_t dram_size; + +#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + puts("Initializing....using SPD\n"); + dram_size = fsl_ddr_sdram(); +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + gd->ram_size = dram_size; + + return 0; +} diff --git a/board/nxp/t208xrdb/ddr.h b/board/nxp/t208xrdb/ddr.h new file mode 100644 index 00000000000..c00f1781667 --- /dev/null +++ b/board/nxp/t208xrdb/ddr.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | + */ + {2, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a}, + {2, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09}, + {2, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a}, + {2, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a}, + {2, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09}, + {1, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a}, + {1, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09}, + {1, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a}, + {1, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; +#endif diff --git a/board/nxp/t208xrdb/eth_t208xrdb.c b/board/nxp/t208xrdb/eth_t208xrdb.c new file mode 100644 index 00000000000..5223eccb280 --- /dev/null +++ b/board/nxp/t208xrdb/eth_t208xrdb.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2021 NXP + * + * Shengzhou Liu + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern u8 get_hw_revision(void); + +/* Disable the MAC5 and MAC6 "fsl,fman-memac" nodes and the two + * "fsl,dpa-ethernet" nodes that reference them. + */ +void fdt_fixup_board_fman_ethernet(void *fdt) +{ + int mac_off, eth_off, i; + char mac_path[2][42] = { + "/soc@ffe000000/fman@400000/ethernet@e8000", + "/soc@ffe000000/fman@400000/ethernet@ea000", + }; + u32 eth_ph; + + for (i = 0; i < 2; i++) { + /* Disable the MAC node */ + mac_off = fdt_path_offset(fdt, mac_path[i]); + if (mac_off < 0) + continue; + fdt_status_disabled(fdt, mac_off); + + /* Disable the fsl,dpa-ethernet node that points to the MAC. + * The fsl,fman-mac property refers to the MAC's phandle. + */ + eth_ph = fdt_get_phandle(fdt, mac_off); + if (eth_ph <= 0) + continue; + + eth_off = fdt_node_offset_by_prop_value(fdt, -1, "fsl,fman-mac", + ð_ph, + sizeof(eth_ph)); + if (eth_off >= 0) + fdt_status_disabled(fdt, eth_off); + } +} + +/* Update the address of the second Aquantia PHY on boards revision D and up. + * Also rename the PHY node to align with the address change. + */ +void fdt_fixup_board_phy(void *fdt) +{ + const char phy_path[] = + "/soc@ffe000000/fman@400000/mdio@fd000/ethernet-phy@1"; + int ret, offset, new_addr = AQR113C_PHY_ADDR2; + char new_name[] = "ethernet-phy@00"; + + if (get_hw_revision() == 'C') + return; + + offset = fdt_path_offset(fdt, phy_path); + if (offset < 0) { + printf("ethernet-phy@1 node not found in the dts\n"); + return; + } + + ret = fdt_setprop(fdt, offset, "reg", &new_addr, sizeof(new_addr)); + if (ret < 0) { + printf("Unable to set 'reg' for node ethernet-phy@1: %s\n", + fdt_strerror(ret)); + return; + } + + sprintf(new_name, "ethernet-phy@%x", new_addr); + ret = fdt_set_name(fdt, offset, new_name); + if (ret < 0) + printf("Unable to rename node ethernet-phy@1: %s\n", + fdt_strerror(ret)); +} + +void fdt_fixup_board_enet(void *fdt) +{ + return; +} diff --git a/board/nxp/t208xrdb/law.c b/board/nxp/t208xrdb/law.c new file mode 100644 index 00000000000..e1f570a8935 --- /dev/null +++ b/board/nxp/t208xrdb/law.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CFG_SYS_CPLD_BASE_PHYS + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif +#ifdef CFG_SYS_DCSRBAR_PHYS + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/nxp/t208xrdb/spl.c b/board/nxp/t208xrdb/spl.c new file mode 100644 index 00000000000..df3b9c6fe40 --- /dev/null +++ b/board/nxp/t208xrdb/spl.c @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright 2013 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/spl.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#if defined(CONFIG_SPL_MMC_BOOT) + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + struct bd_info *bd; + + bd = (struct bd_info *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(struct bd_info)); + gd->bd = bd; + + arch_cpu_init(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; + +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)SPL_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)SPL_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)SPL_ENV_ADDR); +#endif + + gd->env_addr = (ulong)(SPL_ENV_ADDR); + gd->env_valid = ENV_VALID; + + i2c_init_all(); + + dram_init(); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + fsl_spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/nxp/t208xrdb/t2080_nand_rcw.cfg b/board/nxp/t208xrdb/t2080_nand_rcw.cfg new file mode 100644 index 00000000000..8096ff9f372 --- /dev/null +++ b/board/nxp/t208xrdb/t2080_nand_rcw.cfg @@ -0,0 +1,19 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 + +#For T2080 v1.0 +#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s +#120c0017 15000000 00000000 00000000 +#66150002 00008400 ec104000 c1000000 +#00000000 00000000 00000000 000307fc +#00000000 00000000 00000000 00000004 + +#For T2080 v1.1 +#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s +#1206001b 15000000 00000000 00000000 + +#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s +1207001b 15000000 00000000 00000000 +66150002 00000000 e8104000 c1000000 +00800000 00000000 00000000 000307fc +00000000 00000000 00000000 00000004 diff --git a/board/nxp/t208xrdb/t2080_pbi.cfg b/board/nxp/t208xrdb/t2080_pbi.cfg new file mode 100644 index 00000000000..43be8a864e3 --- /dev/null +++ b/board/nxp/t208xrdb/t2080_pbi.cfg @@ -0,0 +1,40 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.pblimage for more details about how-to configure +# and create PBL boot image +# + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#512KB SRAM +09010100 00000000 +09010104 fff80009 +09010f00 08000000 +#enable CPC1 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff80000 +09000d08 81000012 +#Initialize eSPI controller, default configuration is slow for eSPI to +#load data, this configuration comes from u-boot eSPI driver. +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Errata for slowing down the MDC clock to make it <= 2.5 MHZ +094fc030 00008148 +094fd030 00008148 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Flush PBL data +091380c0 00100000 diff --git a/board/nxp/t208xrdb/t2080_sd_rcw.cfg b/board/nxp/t208xrdb/t2080_sd_rcw.cfg new file mode 100644 index 00000000000..6309b1d2200 --- /dev/null +++ b/board/nxp/t208xrdb/t2080_sd_rcw.cfg @@ -0,0 +1,19 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 + +#For T2080 v1.0 +#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s +#120c0017 15000000 00000000 00000000 +#66150002 00008400 ec104000 c1000000 +#00000000 00000000 00000000 000307fc +#00000000 00000000 00000000 00000004 + +#For T2080 v1.1 +#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s +#1206001b 15000000 00000000 00000000 + +#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s +1207001b 15000000 00000000 00000000 +66150002 00000000 68104000 c1000000 +00800000 00000000 00000000 000307fc +00000000 00000000 00000000 00000004 diff --git a/board/nxp/t208xrdb/t2080_spi_rcw.cfg b/board/nxp/t208xrdb/t2080_spi_rcw.cfg new file mode 100644 index 00000000000..f1674958870 --- /dev/null +++ b/board/nxp/t208xrdb/t2080_spi_rcw.cfg @@ -0,0 +1,19 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 + +#For T2080 v1.0 +#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s +#120c0017 15000000 00000000 00000000 +#66150002 00008400 ec104000 c1000000 +#00000000 00000000 00000000 000307fc +#00000000 00000000 00000000 00000004 + +#For T2080 v1.1 +#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s +#1206001b 15000000 00000000 00000000 + +#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s +1207001b 15000000 00000000 00000000 +66150002 00000000 58104000 c1000000 +00800000 00000000 00000000 000307fc +00000000 00000000 00000000 00000004 diff --git a/board/nxp/t208xrdb/t208xrdb.c b/board/nxp/t208xrdb/t208xrdb.c new file mode 100644 index 00000000000..d93edf007ad --- /dev/null +++ b/board/nxp/t208xrdb/t208xrdb.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2009-2013 Freescale Semiconductor, Inc. + * Copyright 2021-2023 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "t208xrdb.h" +#include "cpld.h" +#include "../common/vid.h" + +DECLARE_GLOBAL_DATA_PTR; + +u8 get_hw_revision(void) +{ + u8 ver = CPLD_READ(hw_ver); + + switch (ver) { + default: + case 0x1: + return 'C'; + case 0x0: + return 'D'; + case 0x2: + return 'E'; + } +} + +#if CONFIG_IS_ENABLED(DM_SERIAL) +int get_serial_clock(void) +{ + return get_bus_freq(0) / 2; +} +#endif + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; + + printf("Board: %sRDB, ", cpu->name); + printf("Board rev: %c CPLD ver: 0x%02x, boot from ", + get_hw_revision(), CPLD_READ(sw_ver)); + +#ifdef CONFIG_SDCARD + puts("SD/MMC\n"); +#elif CONFIG_SPIFLASH + puts("SPI\n"); +#else + u8 reg; + + reg = CPLD_READ(flash_csr); + + if (reg & CPLD_BOOT_SEL) { + puts("NAND\n"); + } else { + reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); + printf("NOR vBank%d\n", reg); + } +#endif + + puts("SERDES Reference Clocks:\n"); + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); + printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CFG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + /* + * Adjust core voltage according to voltage ID + * This function changes I2C mux to channel 2. + */ + if (adjust_vdd(0)) + printf("Warning: Adjusting core voltage failed.\n"); + + pci_init(); + + return 0; +} + +int misc_init_r(void) +{ + u8 reg; + + /* Reset CS4315 PHY */ + reg = CPLD_READ(reset_ctl); + reg |= CPLD_RSTCON_EDC_RST; + CPLD_WRITE(reset_ctl, reg); + + /* Enable POR for boards revisions D and up */ + if (get_hw_revision() >= 'D') { + reg = CPLD_READ(misc_csr); + reg |= CPLD_MISC_POR_EN; + CPLD_WRITE(misc_csr, reg); + } + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = env_get_bootm_low(); + size = env_get_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fsl_fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_board_fman_ethernet(blob); + fdt_fixup_board_enet(blob); + fdt_fixup_board_phy(blob); +#endif + + return 0; +} + +ulong *cs4340_get_fw_addr(void) +{ + ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR; + +#ifdef CONFIG_SYS_CORTINA_FW_IN_NOR + u8 reg; + + reg = CPLD_READ(flash_csr); + if (!(reg & CPLD_BOOT_SEL)) { + reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); + if (reg == 0) + cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR; + else if (reg == 4) + cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK; + } +#endif + + return (ulong *)cortina_fw_addr; +} diff --git a/board/nxp/t208xrdb/t208xrdb.h b/board/nxp/t208xrdb/t208xrdb.h new file mode 100644 index 00000000000..26998898e82 --- /dev/null +++ b/board/nxp/t208xrdb/t208xrdb.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2021 NXP + */ + +#ifndef __CORENET_DS_H__ +#define __CORENET_DS_H__ + +#define CORTINA_FW_ADDR_IFCNOR 0xefe00000 +#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebe00000 + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, struct bd_info *bd); +void fdt_fixup_board_fman_ethernet(void *blob); +void fdt_fixup_board_phy(void *blob); + +#endif diff --git a/board/nxp/t208xrdb/tlb.c b/board/nxp/t208xrdb/tlb.c new file mode 100644 index 00000000000..a3f283548f3 --- /dev/null +++ b/board/nxp/t208xrdb/tlb.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2008-2014 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#include +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) + /* + * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the + * space is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + +#ifndef CONFIG_XPL_BUILD + /* *I*G* - PCIe 1, 0x80000000 */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_512M, 1), + + /* *I*G* - PCIe 2, 0xa0000000 */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE2_MEM_VIRT, CFG_SYS_PCIE2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCIe 3, 0xb0000000 */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE3_MEM_VIRT, CFG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCIe 4, 0xc0000000 */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_16M, 1), +#endif +#endif +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_32M, 1), +#endif +#ifdef CFG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef CFG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 17, BOOKE_PAGESZ_4K, 1), +#endif +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE + /* + * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for + * fetching ucode and ENV from master + */ + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 18, BOOKE_PAGESZ_1M, 1), +#endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD) + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 19, BOOKE_PAGESZ_2G, 1) +#endif + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/nxp/t4rdb/Kconfig b/board/nxp/t4rdb/Kconfig new file mode 100644 index 00000000000..1a6874ab562 --- /dev/null +++ b/board/nxp/t4rdb/Kconfig @@ -0,0 +1,12 @@ +if TARGET_T4240RDB + +config SYS_BOARD + default "t4rdb" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "T4240RDB" + +endif diff --git a/board/nxp/t4rdb/MAINTAINERS b/board/nxp/t4rdb/MAINTAINERS new file mode 100644 index 00000000000..6d328595d39 --- /dev/null +++ b/board/nxp/t4rdb/MAINTAINERS @@ -0,0 +1,7 @@ +T4RDB BOARD +M: Priyanka Jain +S: Maintained +F: board/nxp/t4rdb/ +F: include/configs/T4240RDB.h +F: configs/T4240RDB_defconfig +F: configs/T4240RDB_SDCARD_defconfig diff --git a/board/nxp/t4rdb/Makefile b/board/nxp/t4rdb/Makefile new file mode 100644 index 00000000000..8d94faaba1c --- /dev/null +++ b/board/nxp/t4rdb/Makefile @@ -0,0 +1,17 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +else +obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o +obj-y += cpld.o +obj-y += eth.o +endif + +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/nxp/t4rdb/cpld.c b/board/nxp/t4rdb/cpld.c new file mode 100644 index 00000000000..258581eee96 --- /dev/null +++ b/board/nxp/t4rdb/cpld.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * Copyright 2014 Freescale Semiconductor + * + * Author: Chunhe Lan + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CFG_SYS_CPLD_BASE - The virtual address of the base of the + * CPLD register map + * + */ + +#include +#include +#include +#include + +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CFG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CFG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(void) +{ + u8 val, curbank, altbank, override; + + val = CPLD_READ(vbank); + curbank = val & CPLD_BANK_SEL_MASK; + + switch (curbank) { + case CPLD_SELECT_BANK0: + case CPLD_SELECT_BANK4: + altbank = CPLD_SELECT_BANK4; + CPLD_WRITE(vbank, altbank); + override = CPLD_READ(software_on); + CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); + CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET); + break; + default: + printf("CPLD Altbank Fail: Invalid value!\n"); + return; + } +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + u8 val; + + val = CPLD_DEFAULT_BANK; + + CPLD_WRITE(global_reset, val); +} + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("chip_id1 = 0x%02x\n", CPLD_READ(chip_id1)); + printf("chip_id2 = 0x%02x\n", CPLD_READ(chip_id2)); + printf("sw_maj_ver = 0x%02x\n", CPLD_READ(sw_maj_ver)); + printf("sw_min_ver = 0x%02x\n", CPLD_READ(sw_min_ver)); + printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); + printf("software_on = 0x%02x\n", CPLD_READ(software_on)); + printf("cfg_rcw_src = 0x%02x\n", CPLD_READ(cfg_rcw_src)); + printf("res0 = 0x%02x\n", CPLD_READ(res0)); + printf("vbank = 0x%02x\n", CPLD_READ(vbank)); + printf("sw1_sysclk = 0x%02x\n", CPLD_READ(sw1_sysclk)); + printf("sw2_status = 0x%02x\n", CPLD_READ(sw2_status)); + printf("sw3_status = 0x%02x\n", CPLD_READ(sw3_status)); + printf("sw4_status = 0x%02x\n", CPLD_READ(sw4_status)); + printf("sys_reset = 0x%02x\n", CPLD_READ(sys_reset)); + printf("global_reset = 0x%02x\n", CPLD_READ(global_reset)); + printf("res1 = 0x%02x\n", CPLD_READ(res1)); + putc('\n'); +} +#endif + +#ifndef CONFIG_XPL_BUILD +int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset - reset to default bank\n" + "cpld reset altbank - reset to alternate bank\n" +#ifdef DEBUG + "cpld dump - display the CPLD registers\n" +#endif + ); +#endif diff --git a/board/nxp/t4rdb/cpld.h b/board/nxp/t4rdb/cpld.h new file mode 100644 index 00000000000..fcac9244c8a --- /dev/null +++ b/board/nxp/t4rdb/cpld.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/** + * Copyright 2014 Freescale Semiconductor + * + * Author: Chunhe Lan + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +struct cpld_data { + u8 chip_id1; /* 0x00 - CPLD Chip ID1 Register */ + u8 chip_id2; /* 0x01 - CPLD Chip ID2 Register */ + u8 sw_maj_ver; /* 0x02 - CPLD Code Major Version Register */ + u8 sw_min_ver; /* 0x03 - CPLD Code Minor Version Register */ + u8 hw_ver; /* 0x04 - PCBA Version Register */ + u8 software_on; /* 0x05 - Override Physical Switch Enable Register */ + u8 cfg_rcw_src; /* 0x06 - RCW Source Location Control Register */ + u8 res0; /* 0x07 - not used */ + u8 vbank; /* 0x08 - Flash Bank Selection Control Register */ + u8 sw1_sysclk; /* 0x09 - SW1 Status Read Back Register */ + u8 sw2_status; /* 0x0a - SW2 Status Read Back Register */ + u8 sw3_status; /* 0x0b - SW3 Status Read Back Register */ + u8 sw4_status; /* 0x0c - SW4 Status Read Back Register */ + u8 sys_reset; /* 0x0d - Reset System With Reserving Registers Value*/ + u8 global_reset;/* 0x0e - Reset System With Default Registers Value */ + u8 res1; /* 0x0f - not used */ +}; + +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_SEL_EN 0x04 +#define CPLD_SYSTEM_RESET 0x01 +#define CPLD_SELECT_BANK0 0x00 +#define CPLD_SELECT_BANK4 0x04 +#define CPLD_DEFAULT_BANK 0x01 + +/* Pointer to the CPLD register set */ + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value) \ + cpld_write(offsetof(struct cpld_data, reg), value) diff --git a/board/nxp/t4rdb/ddr.c b/board/nxp/t4rdb/ddr.c new file mode 100644 index 00000000000..1ce70962264 --- /dev/null +++ b/board/nxp/t4rdb/ddr.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 2) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + /* + * we use identical timing for all slots. If needed, change the code + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; + */ + if (popts->registered_dimm_en) + pbsp = rdimms[0]; + else + pbsp = udimms[0]; + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for data\n" + "rate %lu MT/s\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n" + "wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); + + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x64; +} + +int dram_init(void) +{ + phys_size_t dram_size; + + puts("Initializing....using SPD\n"); + +#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + dram_size = fsl_ddr_sdram(); +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + gd->ram_size = dram_size; + + return 0; +} diff --git a/board/nxp/t4rdb/ddr.h b/board/nxp/t4rdb/ddr.h new file mode 100644 index 00000000000..241b13475da --- /dev/null +++ b/board/nxp/t4rdb/ddr.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a}, + {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09}, + {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b}, + {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a}, + {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c}, + {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c}, + {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a}, + {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a}, + {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b}, + {} +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {4, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906}, + {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, + {2, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, + {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, + {1, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, + {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07}, + {} +}; + +/* + * The three slots have slightly different timing. The center values are good + * for all slots. We use identical speed tables for them. In future use, if + * DIMMs require separated tables, make more entries as needed. + */ +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +/* + * The three slots have slightly different timing. See comments above. + */ +static const struct board_specific_parameters *rdimms[] = { + rdimm0, +}; + +#endif diff --git a/board/nxp/t4rdb/eth.c b/board/nxp/t4rdb/eth.c new file mode 100644 index 00000000000..e7646365d7d --- /dev/null +++ b/board/nxp/t4rdb/eth.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * Chunhe Lan + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/fman.h" +#include "t4rdb.h" + +void fdt_fixup_board_enet(void *fdt) +{ + return; +} + +int board_eth_init(struct bd_info *bis) +{ +#if defined(CONFIG_FMAN_ENET) + int i, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + struct mii_dev *dev; + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1, srds_prtcl_s2; + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CFG_SYS_FM2_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CFG_SYS_FM2_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) { + /* SGMII */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3); + fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4); + } else { + puts("Invalid SerDes1 protocol for T4240RDB\n"); + } + + fm_disable_port(FM1_DTSEC5); + fm_disable_port(FM1_DTSEC6); + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + +#if (CFG_SYS_NUM_FMAN == 2) + if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) { + /* SGMII && 10GBase-R */ + fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); + fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); + fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7); + fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8); + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR); + } else { + puts("Invalid SerDes2 protocol for T4240RDB\n"); + } + + fm_disable_port(FM2_DTSEC5); + fm_disable_port(FM2_DTSEC6); + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CFG_SYS_NUM_FM2_DTSEC; i++) { + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + for (i = FM2_10GEC1; i < FM2_10GEC1 + CFG_SYS_NUM_FM2_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } +#endif /* CFG_SYS_NUM_FMAN */ + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/nxp/t4rdb/law.c b/board/nxp/t4rdb/law.c new file mode 100644 index 00000000000..c43ac0f30d7 --- /dev/null +++ b/board/nxp/t4rdb/law.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CFG_SYS_CPLD_BASE_PHYS + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif +#ifdef CFG_SYS_DCSRBAR_PHYS + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/nxp/t4rdb/spl.c b/board/nxp/t4rdb/spl.c new file mode 100644 index 00000000000..9d2472dec25 --- /dev/null +++ b/board/nxp/t4rdb/spl.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * Author: Chunhe Lan + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "t4rdb.h" + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + + puts("\nSD boot...\n"); + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + struct bd_info *bd; + + bd = (struct bd_info *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(struct bd_info)); + gd->bd = bd; + + arch_cpu_init(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; + + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)SPL_ENV_ADDR); + + gd->env_addr = (ulong)(SPL_ENV_ADDR); + gd->env_valid = ENV_VALID; + + i2c_init_all(); + + dram_init(); + + mmc_boot(); +} diff --git a/board/nxp/t4rdb/t4240rdb.c b/board/nxp/t4rdb/t4240rdb.c new file mode 100644 index 00000000000..5cacfd27380 --- /dev/null +++ b/board/nxp/t4rdb/t4240rdb.c @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2023 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "t4rdb.h" +#include "cpld.h" +#include "../common/vid.h" + +DECLARE_GLOBAL_DATA_PTR; + +#if CONFIG_IS_ENABLED(DM_SERIAL) +int get_serial_clock(void) +{ + return get_bus_freq(0) / 2; +} +#endif + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + u8 sw; + + printf("Board: %sRDB, ", cpu->name); + printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ", + CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver)); + + sw = CPLD_READ(vbank); + sw = sw & CPLD_BANK_SEL_MASK; + + if (sw <= 7) + printf("vBank: %d\n", sw); + else + printf("Unsupported Bank=%x\n", sw); + + puts("SERDES Reference Clocks:\n"); + printf(" SERDES1=100MHz SERDES2=156.25MHz\n" + " SERDES3=100MHz SERDES4=100MHz\n"); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CFG_SYS_FLASH_BASE; + int flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } + + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + /* + * Adjust core voltage according to voltage ID + * This function changes I2C mux to channel 2. + */ + if (adjust_vdd(0)) + printf("Warning: Adjusting core voltage failed.\n"); + + pci_init(); + + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = env_get_bootm_low(); + size = env_get_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fsl_fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN +#ifndef CONFIG_DM_ETH + fdt_fixup_fman_ethernet(blob); +#endif + fdt_fixup_board_enet(blob); +#endif + + return 0; +} + +/* + * This function is called by bdinfo to print detail board information. + * As an exmaple for future board, we organize the messages into + * several sections. If applicable, the message is in the format of + * = + * It should aligned with normal output of bdinfo command. + * + * Voltage: Core, DDR and another configurable voltages + * Clock : Critical clocks which are not printed already + * RCW : RCW source if not printed already + * Misc : Other important information not in above catagories + */ +void board_detail(void) +{ + int rcwsrc; + + /* RCW section SW3[4] */ + rcwsrc = 0x0; + puts("RCW source = "); + switch (rcwsrc & 0x1) { + case 0x1: + puts("SDHC/eMMC\n"); + break; + default: + puts("I2C normal addressing\n"); + break; + } +} + +ulong *cs4340_get_fw_addr(void) +{ + ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR; + +#ifdef CONFIG_SYS_CORTINA_FW_IN_NOR + u8 sw; + + sw = CPLD_READ(vbank); + sw = sw & CPLD_BANK_SEL_MASK; + + if (sw == 0) + cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR; + else if (sw == 4) + cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK; +#endif + + return (ulong *)cortina_fw_addr; +} diff --git a/board/nxp/t4rdb/t4_pbi.cfg b/board/nxp/t4rdb/t4_pbi.cfg new file mode 100644 index 00000000000..0b326fa1635 --- /dev/null +++ b/board/nxp/t4rdb/t4_pbi.cfg @@ -0,0 +1,27 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#512KB SRAM +09010100 00000000 +09010104 fff80009 +09010f00 08000000 +#enable CPC1 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff80000 +09000d08 81000012 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Flush PBL data +091380c0 00100000 diff --git a/board/nxp/t4rdb/t4_sd_rcw.cfg b/board/nxp/t4rdb/t4_sd_rcw.cfg new file mode 100644 index 00000000000..cc2bff68269 --- /dev/null +++ b/board/nxp/t4rdb/t4_sd_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +#serdes protocol 27_55_1_9 +16070019 18101916 00000000 00000000 +6c6e0848 00448c00 6c020000 f5000000 +00000000 ee0000ee 00000000 000307fc +00000000 00000000 00000000 00000028 diff --git a/board/nxp/t4rdb/t4rdb.h b/board/nxp/t4rdb/t4rdb.h new file mode 100644 index 00000000000..bb3ce216d7d --- /dev/null +++ b/board/nxp/t4rdb/t4rdb.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#ifndef __T4RDB_H__ +#define __T4RDB_H__ + +#undef CFG_SYS_NUM_FM1_DTSEC +#undef CFG_SYS_NUM_FM2_DTSEC +#define CFG_SYS_NUM_FM1_DTSEC 4 +#define CFG_SYS_NUM_FM2_DTSEC 4 + +#define CORTINA_FW_ADDR_IFCNOR 0xefe00000 +#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebf00000 + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, struct bd_info *bd); + +#endif diff --git a/board/nxp/t4rdb/tlb.c b/board/nxp/t4rdb/tlb.c new file mode 100644 index 00000000000..7c58c14f3b6 --- /dev/null +++ b/board/nxp/t4rdb/tlb.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 512K SRAM */ + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_512K, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + +#ifndef CONFIG_XPL_BUILD + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CFG_SYS_PCIE1_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CFG_SYS_PCIE1_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_16M, 1), +#endif +#endif + +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_32M, 1), +#endif +#ifdef CFG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef CFG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, + MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 17, BOOKE_PAGESZ_4K, 1), +#endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_XPL_BUILD) + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 18, BOOKE_PAGESZ_2G, 1) +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/nxp/vf610twr/Kconfig b/board/nxp/vf610twr/Kconfig new file mode 100644 index 00000000000..4d9433cd929 --- /dev/null +++ b/board/nxp/vf610twr/Kconfig @@ -0,0 +1,15 @@ +if TARGET_VF610TWR + +config SYS_BOARD + default "vf610twr" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "vf610twr" + +config IMX_CONFIG + default "board/nxp/vf610twr/imximage.cfg" + +endif diff --git a/board/nxp/vf610twr/MAINTAINERS b/board/nxp/vf610twr/MAINTAINERS new file mode 100644 index 00000000000..b8d4cb9a784 --- /dev/null +++ b/board/nxp/vf610twr/MAINTAINERS @@ -0,0 +1,7 @@ +VF610TWR BOARD +M: Alison Wang +S: Maintained +F: board/nxp/vf610twr/ +F: include/configs/vf610twr.h +F: configs/vf610twr_defconfig +F: configs/vf610twr_nand_defconfig diff --git a/board/nxp/vf610twr/Makefile b/board/nxp/vf610twr/Makefile new file mode 100644 index 00000000000..43934e8b2ae --- /dev/null +++ b/board/nxp/vf610twr/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2013 Freescale Semiconductor, Inc. + +obj-y := vf610twr.o diff --git a/board/nxp/vf610twr/imximage.cfg b/board/nxp/vf610twr/imximage.cfg new file mode 100644 index 00000000000..e2fa1a582d2 --- /dev/null +++ b/board/nxp/vf610twr/imximage.cfg @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +#include + +/* image version */ +IMAGE_VERSION 2 + +/* Boot Offset 0x400, valid for both SD and NAND boot */ +BOOT_OFFSET FLASH_OFFSET_STANDARD diff --git a/board/nxp/vf610twr/vf610twr.c b/board/nxp/vf610twr/vf610twr.c new file mode 100644 index 00000000000..bfb49ad8604 --- /dev/null +++ b/board/nxp/vf610twr/vf610twr.c @@ -0,0 +1,386 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE) + +#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) + +static struct ddrmc_cr_setting vf610twr_cr_settings[] = { + /* levelling */ + { DDRMC_CR97_WRLVL_EN, 97 }, + { DDRMC_CR98_WRLVL_DL_0(0), 98 }, + { DDRMC_CR99_WRLVL_DL_1(0), 99 }, + { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 }, + { DDRMC_CR105_RDLVL_DL_0(0), 105 }, + { DDRMC_CR106_RDLVL_GTDL_0(4), 106 }, + { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 }, + /* AXI */ + { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 }, + { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, + { DDRMC_CR120_AXI0_PRI1_RPRI(2) | + DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 }, + { DDRMC_CR121_AXI0_PRI3_RPRI(2) | + DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 }, + { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | + DDRMC_CR122_AXI0_PRIRLX(100), 122 }, + { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | + DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 }, + { DDRMC_CR124_AXI1_PRIRLX(100), 124 }, + { DDRMC_CR126_PHY_RDLAT(8), 126 }, + { DDRMC_CR132_WRLAT_ADJ(5) | + DDRMC_CR132_RDLAT_ADJ(6), 132 }, + { DDRMC_CR137_PHYCTL_DL(2), 137 }, + { DDRMC_CR138_PHY_WRLV_MXDL(256) | + DDRMC_CR138_PHYDRAM_CK_EN(1), 138 }, + { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | + DDRMC_CR139_PHY_WRLV_DLL(3) | + DDRMC_CR139_PHY_WRLV_EN(3), 139 }, + { DDRMC_CR140_PHY_WRLV_WW(64), 140 }, + { DDRMC_CR143_RDLV_GAT_MXDL(1536) | + DDRMC_CR143_RDLV_MXDL(128), 143 }, + { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) | + DDRMC_CR144_PHY_RDLV_DLL(3) | + DDRMC_CR144_PHY_RDLV_EN(3), 144 }, + { DDRMC_CR145_PHY_RDLV_RR(64), 145 }, + { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 }, + { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 }, + { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 }, + { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) | + DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 }, + + { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | + DDRMC_CR154_PAD_ZQ_MODE(1) | + DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | + DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 }, + { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 }, + { DDRMC_CR158_TWR(6), 158 }, + { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) | + DDRMC_CR161_TODTH_WR(2), 161 }, + /* end marker */ + { 0, -1 } +}; + +int dram_init(void) +{ + static const struct ddr3_jedec_timings timings = { + .tinit = 5, + .trst_pwron = 80000, + .cke_inactive = 200000, + .wrlat = 5, + .caslat_lin = 12, + .trc = 21, + .trrd = 4, + .tccd = 4, + .tbst_int_interval = 0, + .tfaw = 20, + .trp = 6, + .twtr = 4, + .tras_min = 15, + .tmrd = 4, + .trtp = 4, + .tras_max = 28080, + .tmod = 12, + .tckesr = 4, + .tcke = 3, + .trcd_int = 6, + .tras_lockout = 0, + .tdal = 12, + .bstlen = 3, + .tdll = 512, + .trp_ab = 6, + .tref = 3120, + .trfc = 44, + .tref_int = 0, + .tpdex = 3, + .txpdll = 10, + .txsnr = 48, + .txsr = 468, + .cksrx = 5, + .cksre = 5, + .freq_chg_en = 0, + .zqcl = 256, + .zqinit = 512, + .zqcs = 64, + .ref_per_zq = 64, + .zqcs_rotate = 0, + .aprebit = 10, + .cmd_age_cnt = 64, + .age_cnt = 64, + .q_fullness = 7, + .odt_rd_mapcs0 = 0, + .odt_wr_mapcs0 = 1, + .wlmrd = 40, + .wldqsen = 25, + }; + + ddrmc_setup_iomux(NULL, 0); + + ddrmc_ctrl_init_ddr3(&timings, vf610twr_cr_settings, NULL, 1, 3); + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static void setup_iomux_uart(void) +{ + static const iomux_v3_cfg_t uart1_pads[] = { + NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static void setup_iomux_enet(void) +{ + static const iomux_v3_cfg_t enet0_pads[] = { + NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); +} + +static void setup_iomux_i2c(void) +{ + static const iomux_v3_cfg_t i2c0_pads[] = { + VF610_PAD_PTB14__I2C0_SCL, + VF610_PAD_PTB15__I2C0_SDA, + }; + + imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads)); +} + +#ifdef CONFIG_NAND_VF610_NFC +static void setup_iomux_nfc(void) +{ + static const iomux_v3_cfg_t nfc_pads[] = { + VF610_PAD_PTD31__NF_IO15, + VF610_PAD_PTD30__NF_IO14, + VF610_PAD_PTD29__NF_IO13, + VF610_PAD_PTD28__NF_IO12, + VF610_PAD_PTD27__NF_IO11, + VF610_PAD_PTD26__NF_IO10, + VF610_PAD_PTD25__NF_IO9, + VF610_PAD_PTD24__NF_IO8, + VF610_PAD_PTD23__NF_IO7, + VF610_PAD_PTD22__NF_IO6, + VF610_PAD_PTD21__NF_IO5, + VF610_PAD_PTD20__NF_IO4, + VF610_PAD_PTD19__NF_IO3, + VF610_PAD_PTD18__NF_IO2, + VF610_PAD_PTD17__NF_IO1, + VF610_PAD_PTD16__NF_IO0, + VF610_PAD_PTB24__NF_WE_B, + VF610_PAD_PTB25__NF_CE0_B, + VF610_PAD_PTB27__NF_RE_B, + VF610_PAD_PTC26__NF_RB_B, + VF610_PAD_PTC27__NF_ALE, + VF610_PAD_PTC28__NF_CLE + }; + + imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); +} +#endif + +static void setup_iomux_qspi(void) +{ + static const iomux_v3_cfg_t qspi0_pads[] = { + VF610_PAD_PTD0__QSPI0_A_QSCK, + VF610_PAD_PTD1__QSPI0_A_CS0, + VF610_PAD_PTD2__QSPI0_A_DATA3, + VF610_PAD_PTD3__QSPI0_A_DATA2, + VF610_PAD_PTD4__QSPI0_A_DATA1, + VF610_PAD_PTD5__QSPI0_A_DATA0, + VF610_PAD_PTD7__QSPI0_B_QSCK, + VF610_PAD_PTD8__QSPI0_B_CS0, + VF610_PAD_PTD9__QSPI0_B_DATA3, + VF610_PAD_PTD10__QSPI0_B_DATA2, + VF610_PAD_PTD11__QSPI0_B_DATA1, + VF610_PAD_PTD12__QSPI0_B_DATA0, + }; + + imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads)); +} + +#ifdef CONFIG_FSL_ESDHC_IMX +struct fsl_esdhc_cfg esdhc_cfg[1] = { + {ESDHC1_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + /* eSDHC1 is always present */ + return 1; +} + +int board_mmc_init(struct bd_info *bis) +{ + static const iomux_v3_cfg_t esdhc1_pads[] = { + NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), + }; + + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + imx_iomux_v3_setup_multiple_pads( + esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); + + return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); +} +#endif + +static void clock_init(void) +{ + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; + struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; + + clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, + CCM_CCGR0_UART1_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, + CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, + CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | + CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | + CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK | + CCM_CCGR2_QSPI0_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, + CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, + CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | + CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, + CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, + CCM_CCGR7_SDHC1_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, + CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, + CCM_CCGR10_NFC_CTRL_MASK); + + clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, + ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); + clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, + ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); + + clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, + CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); + clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, + CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN | + CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN | + CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN | + CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN | + CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) | + CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4)); + clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, + CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | + CCM_CACRR_ARM_CLK_DIV(0)); + clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, + CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) | + CCM_CSCMR1_NFC_CLK_SEL(0)); + clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, + CCM_CSCDR1_RMII_CLK_EN); + clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, + CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | + CCM_CSCDR2_NFC_EN); + clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, + CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) | + CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) | + CCM_CSCDR3_NFC_PRE_DIV(5)); + clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, + CCM_CSCMR2_RMII_CLK_SEL(0)); +} + +static void mscm_init(void) +{ + struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; + int i; + + for (i = 0; i < MSCM_IRSPRC_NUM; i++) + writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_early_init_f(void) +{ + clock_init(); + mscm_init(); + + setup_iomux_uart(); + setup_iomux_enet(); + setup_iomux_i2c(); + setup_iomux_qspi(); +#ifdef CONFIG_NAND_VF610_NFC + setup_iomux_nfc(); +#endif + + return 0; +} + +int board_init(void) +{ + struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR; + + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* + * Enable external 32K Oscillator + * + * The internal clock experiences significant drift + * so we must use the external oscillator in order + * to maintain correct time in the hwclock + */ + setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN); + + return 0; +} + +int checkboard(void) +{ + puts("Board: vf610twr\n"); + + return 0; +} diff --git a/board/sifive/unmatched/hifive-platform-i2c-eeprom.c b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c index d25c24b08b3..7ad34fe8d20 100644 --- a/board/sifive/unmatched/hifive-platform-i2c-eeprom.c +++ b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c @@ -2,7 +2,7 @@ /* * Copyright (C) 2020 SiFive, Inc. * - * Based on board/freescale/common/sys_eeprom.c: + * Based on board/nxp/common/sys_eeprom.c: * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor * York Sun (yorksun@freescale.com) * Haiying Wang (haiying.wang@freescale.com) diff --git a/board/technexion/pico-imx6ul/pico-imx6ul.c b/board/technexion/pico-imx6ul/pico-imx6ul.c index 10dcf8077e2..57d514853b1 100644 --- a/board/technexion/pico-imx6ul/pico-imx6ul.c +++ b/board/technexion/pico-imx6ul/pico-imx6ul.c @@ -23,7 +23,7 @@ #include #include #include -#include "../../freescale/common/pfuze.h" +#include "../../nxp/common/pfuze.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/technexion/pico-imx7d/Makefile b/board/technexion/pico-imx7d/Makefile index 61b55fcc55a..cb6e1626a7d 100644 --- a/board/technexion/pico-imx7d/Makefile +++ b/board/technexion/pico-imx7d/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ # (C) Copyright 2017 NXP Semiconductors -obj-y := pico-imx7d.o spl.o ../../freescale/common/mmc.o +obj-y := pico-imx7d.o spl.o ../../nxp/common/mmc.o diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index cf6b7fcbd95..63b8b29d097 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -19,7 +19,7 @@ #include #include #include -#include "../../freescale/common/pfuze.h" +#include "../../nxp/common/pfuze.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index 4cd3ff0051b..8b1cff2955b 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -20,7 +20,7 @@ #include #include #include -#include "../freescale/common/pfuze.h" +#include "../nxp/common/pfuze.h" #include #include diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 71b02050c56..a23570e84b7 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -27,8 +27,8 @@ CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/p2041rdb/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/p2041rdb/rcw_p2041rdb.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/p2041rdb/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/p2041rdb/rcw_p2041rdb.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 6b8e8d9de4c..1ed3a8f72fd 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -27,8 +27,8 @@ CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/p2041rdb/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/p2041rdb/rcw_p2041rdb.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/p2041rdb/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/p2041rdb/rcw_p2041rdb.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 3f12aca2dc4..3d47b002b5b 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -29,8 +29,8 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y CONFIG_SPIFLASH=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/p2041rdb/pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/p2041rdb/rcw_p2041rdb.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/p2041rdb/pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/p2041rdb/rcw_p2041rdb.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index d78d89ee07f..ab4c012e274 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -30,8 +30,8 @@ CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/t102xrdb/t1024_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/t102xrdb/t1024_nand_rcw.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/t102xrdb/t1024_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/t102xrdb/t1024_nand_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 5e2a8739242..b48bc8d5cc0 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -30,8 +30,8 @@ CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/t102xrdb/t1024_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/t102xrdb/t1024_sd_rcw.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/t102xrdb/t1024_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/t102xrdb/t1024_sd_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 86fb67c66c8..03d2f65af48 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -33,8 +33,8 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y CONFIG_SPIFLASH=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/t102xrdb/t1024_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/t102xrdb/t1024_spi_rcw.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/t102xrdb/t1024_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/t102xrdb/t1024_spi_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index e03fcb63d19..a3b1958340a 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -29,8 +29,8 @@ CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg" +CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/nxp/t104xrdb/t104x_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/nxp/t104xrdb/t1042d4_nand_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index f3f5c27dd0b..3e3ae2c7a44 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -29,8 +29,8 @@ CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg" +CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/nxp/t104xrdb/t104x_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/nxp/t104xrdb/t1042d4_sd_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 36d855a1ac9..c1890912515 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -32,8 +32,8 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y CONFIG_SPIFLASH=y -CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg" +CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/nxp/t104xrdb/t104x_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/nxp/t104xrdb/t1042d4_spi_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 67e606548a6..40c1e82a87c 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -41,8 +41,8 @@ CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_nand_rcw.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/t208xqds/t208x_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/t208xqds/t2080_nand_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index b9fd336a35a..7ddf5e0619b 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -41,8 +41,8 @@ CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_sd_rcw.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/t208xqds/t208x_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/t208xqds/t2080_sd_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 3e66d47a257..1f9ff569d90 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -44,8 +44,8 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y CONFIG_SPIFLASH=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_spi_rcw.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/t208xqds/t208x_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/t208xqds/t2080_spi_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index c3589b19a7e..a0e4f8619c1 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -35,8 +35,8 @@ CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_nand_rcw.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/t208xrdb/t2080_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/t208xrdb/t2080_nand_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index becc99eff8f..c4f647fd205 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -35,8 +35,8 @@ CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_sd_rcw.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/t208xrdb/t2080_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/t208xrdb/t2080_sd_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 51766dac9c0..04f8ab03af0 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -38,8 +38,8 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y CONFIG_SPIFLASH=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_spi_rcw.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/t208xrdb/t2080_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/t208xrdb/t2080_spi_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index e7f2b02a410..a1a63d9f91f 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -36,8 +36,8 @@ CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_nand_rcw.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/t208xrdb/t2080_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/t208xrdb/t2080_nand_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig index 92defbe55b5..32909cbad2a 100644 --- a/configs/T2080RDB_revD_SDCARD_defconfig +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -36,8 +36,8 @@ CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_sd_rcw.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/t208xrdb/t2080_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/t208xrdb/t2080_sd_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig index f37117d3c9d..3a99374746e 100644 --- a/configs/T2080RDB_revD_SPIFLASH_defconfig +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -39,8 +39,8 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y CONFIG_SPIFLASH=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_spi_rcw.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/t208xrdb/t2080_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/t208xrdb/t2080_spi_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index cf0b7418fac..d9acf5bfac7 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -33,8 +33,8 @@ CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg" +CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/nxp/t4rdb/t4_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/nxp/t4rdb/t4_sd_rcw.cfg" CONFIG_BOOTDELAY=10 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig index 0cefcadff6a..d25f1f90f22 100644 --- a/configs/imx8mm_beacon_fspi_defconfig +++ b/configs/imx8mm_beacon_fspi_defconfig @@ -9,7 +9,7 @@ CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SF_DEFAULT_MODE=0 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 -CONFIG_IMX_CONFIG="board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg" +CONFIG_IMX_CONFIG="board/nxp/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg" CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-beacon-kit" CONFIG_TARGET_IMX8MM_BEACON=y diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig index f364e17bab2..71419eb7d37 100644 --- a/configs/imx8mm_evk_fspi_defconfig +++ b/configs/imx8mm_evk_fspi_defconfig @@ -9,7 +9,7 @@ CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SF_DEFAULT_MODE=0 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 -CONFIG_IMX_CONFIG="board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg" +CONFIG_IMX_CONFIG="board/nxp/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg" CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-evk" CONFIG_TARGET_IMX8MM_EVK=y diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index 113e0e0284a..e97beda2827 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -42,7 +42,7 @@ CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set CONFIG_SPL_LOAD_IMX_CONTAINER=y -CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg" +CONFIG_IMX_CONTAINER_CFG="board/nxp/imx8qm_mek/uboot-container.cfg" CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_HAVE_INIT_STACK=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index 951d73fefd5..dea5188c2d7 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -43,7 +43,7 @@ CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set CONFIG_SPL_LOAD_IMX_CONTAINER=y -CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" +CONFIG_IMX_CONTAINER_CFG="board/nxp/imx8qxp_mek/uboot-container.cfg" CONFIG_SPL_SYS_MALLOC_SIMPLE=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_HAVE_INIT_STACK=y diff --git a/configs/imxrt1050-evk_fspi_defconfig b/configs/imxrt1050-evk_fspi_defconfig index f213135eb20..defb26b0d95 100644 --- a/configs/imxrt1050-evk_fspi_defconfig +++ b/configs/imxrt1050-evk_fspi_defconfig @@ -13,7 +13,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20020000 CONFIG_ENV_OFFSET=0x80000 -CONFIG_IMX_CONFIG="board/freescale/imxrt1050-evk/imximage-nor.cfg" +CONFIG_IMX_CONFIG="board/nxp/imxrt1050-evk/imximage-nor.cfg" CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imxrt1050-evk" CONFIG_TARGET_IMXRT1050_EVK=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index 78b81c1895e..e4978223302 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -30,8 +30,8 @@ CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aiot/ls102xa_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/ls1021aiot/ls102xa_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/ls1021aiot/ls102xa_rcw_sd.cfg" CONFIG_SD_BOOT=y CONFIG_SD_BOOT_QSPI=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 1d90a27c0ac..d606a4ff002 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -40,8 +40,8 @@ CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/ls1021aqds/ls102xa_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/ls1021aqds/ls102xa_rcw_nand.cfg" CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index c1d5ee340e9..098c62db51d 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -41,8 +41,8 @@ CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/ls1021aqds/ls102xa_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/ls1021aqds/ls102xa_rcw_sd_ifc.cfg" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_SYS_CBSIZE=256 diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 9b96676bb69..ce0b190de3c 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -39,8 +39,8 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021aqds/ls102xa_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/ls1021aqds/ls102xa_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/ls1021aqds/ls102xa_rcw_sd_qspi.cfg" CONFIG_SD_BOOT=y CONFIG_SD_BOOT_QSPI=y CONFIG_BOOTDELAY=3 diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index 3a927c858b3..70203dc94f9 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -31,8 +31,8 @@ CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_FIT=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atsn/ls102xa_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/ls1021atsn/ls102xa_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/ls1021atsn/ls102xa_rcw_sd.cfg" CONFIG_DISTRO_DEFAULTS=y CONFIG_SD_BOOT=y CONFIG_SD_BOOT_QSPI=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 6c12c35ab96..af4bb562b87 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -36,8 +36,8 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/ls1021atwr/ls102xa_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/ls1021atwr/ls102xa_rcw_sd_ifc.cfg" CONFIG_DISTRO_DEFAULTS=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=0 diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 8c7126b53f5..a6041337800 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -36,8 +36,8 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/ls1021atwr/ls102xa_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/ls1021atwr/ls102xa_rcw_sd_ifc.cfg" CONFIG_DISTRO_DEFAULTS=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 6f249d7fb1f..d3194ffdbcd 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -36,8 +36,8 @@ CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y -CONFIG_SYS_FSL_PBL_PBI="board/freescale/ls1021atwr/ls102xa_pbi.cfg" -CONFIG_SYS_FSL_PBL_RCW="board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg" +CONFIG_SYS_FSL_PBL_PBI="board/nxp/ls1021atwr/ls102xa_pbi.cfg" +CONFIG_SYS_FSL_PBL_RCW="board/nxp/ls1021atwr/ls102xa_rcw_sd_qspi.cfg" CONFIG_DISTRO_DEFAULTS=y CONFIG_SD_BOOT=y CONFIG_SD_BOOT_QSPI=y diff --git a/doc/README.pblimage b/doc/README.pblimage index 58202c14a28..e99b010d262 100644 --- a/doc/README.pblimage +++ b/doc/README.pblimage @@ -61,7 +61,7 @@ Following steps describe it in detail. Board specific configuration file specifications: ------------------------------------------------ 1. Configuration files rcw.cfg and pbi.cfg must present in the -board/freescale// directory, rcw.cfg is for RCW, pbi.cfg is for +board/nxp// directory, rcw.cfg is for RCW, pbi.cfg is for PBI instructions. File name must not be changed since they are used in Makefile. 2. These files can have empty lines and lines starting with "#" as first diff --git a/doc/imx/mkimage/imximage.txt b/doc/imx/mkimage/imximage.txt index fa4e486661c..cb2670562e7 100644 --- a/doc/imx/mkimage/imximage.txt +++ b/doc/imx/mkimage/imximage.txt @@ -25,7 +25,7 @@ Command syntax: -e -d For example, for the mx51evk board: -./tools/mkimage -n ./board/freescale/mx51evk/imximage.cfg \ +./tools/mkimage -n ./board/nxp/mx51evk/imximage.cfg \ -T imximage -e 0x97800000 \ -d u-boot.bin u-boot.imx diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 683a7931c98..79296c4b580 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -29,7 +29,7 @@ #include #include #include -#include "../../board/freescale/common/qixis.h" +#include "../../board/nxp/common/qixis.h" DECLARE_GLOBAL_DATA_PTR; -- cgit v1.2.3 From 8e918cbe7a1cb87d0b18df91ed1edec9fff2f941 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 17 Dec 2025 16:13:23 +0800 Subject: firmware: scmi: sandbox: Use scmi_clk_state_in_v2 The sandbox scmi clock protocol use version 3.0, so need to use scmi_clk_state_in_v2. Signed-off-by: Peng Fan Reviewed-by: Marek Vasut --- drivers/firmware/scmi/sandbox-scmi_agent.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c b/drivers/firmware/scmi/sandbox-scmi_agent.c index 5b242a039c2..010bf99fbc6 100644 --- a/drivers/firmware/scmi/sandbox-scmi_agent.c +++ b/drivers/firmware/scmi/sandbox-scmi_agent.c @@ -828,7 +828,7 @@ static int sandbox_scmi_clock_rate_get(struct udevice *dev, static int sandbox_scmi_clock_gate(struct udevice *dev, struct scmi_msg *msg) { - struct scmi_clk_state_in_v1 *in = NULL; + struct scmi_clk_state_in_v2 *in = NULL; struct scmi_clk_state_out *out = NULL; struct sandbox_scmi_clk *clk_state = NULL; @@ -836,7 +836,7 @@ static int sandbox_scmi_clock_gate(struct udevice *dev, struct scmi_msg *msg) !msg->out_msg || msg->out_msg_sz < sizeof(*out)) return -EINVAL; - in = (struct scmi_clk_state_in_v1 *)msg->in_msg; + in = (struct scmi_clk_state_in_v2 *)msg->in_msg; out = (struct scmi_clk_state_out *)msg->out_msg; clk_state = get_scmi_clk_state(in->clock_id); -- cgit v1.2.3