From d623e52c9fae29161e5cdcefaf19a8c38f4b0aa9 Mon Sep 17 00:00:00 2001 From: Siew Chin Lim Date: Wed, 24 Mar 2021 13:11:35 +0800 Subject: arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c Rename to common file name to used by all SOC64 devices. Signed-off-by: Siew Chin Lim --- arch/arm/mach-socfpga/Makefile | 4 +- arch/arm/mach-socfpga/wrap_pll_config_s10.c | 62 --------------------------- arch/arm/mach-socfpga/wrap_pll_config_soc64.c | 62 +++++++++++++++++++++++++++ 3 files changed, 64 insertions(+), 64 deletions(-) delete mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_soc64.c diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index e4c2da93d59..eca6fd173ff 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -38,7 +38,7 @@ obj-y += reset_manager_s10.o obj-y += system_manager_s10.o obj-y += timer_s10.o obj-y += wrap_pinmux_config_s10.o -obj-y += wrap_pll_config_s10.o +obj-y += wrap_pll_config_soc64.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX @@ -53,7 +53,7 @@ obj-y += system_manager_s10.o obj-y += timer_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o obj-y += wrap_pinmux_config_s10.o -obj-y += wrap_pll_config_s10.o +obj-y += wrap_pll_config_soc64.o endif ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c deleted file mode 100644 index 6a0d6b5ead7..00000000000 --- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2016-2018 Intel Corporation - * - */ - -#include -#include -#include -#include -#include - -const struct cm_config * const cm_get_default_config(void) -{ -#ifdef CONFIG_SPL_BUILD - struct cm_config *cm_handoff_cfg = (struct cm_config *) - (SOC64_HANDOFF_CLOCK + SOC64_HANDOFF_OFFSET_DATA); - u32 *conversion = (u32 *)cm_handoff_cfg; - u32 i; - u32 handoff_clk = readl(SOC64_HANDOFF_CLOCK); - - if (swab32(handoff_clk) == SOC64_HANDOFF_MAGIC_CLOCK) { - writel(swab32(handoff_clk), SOC64_HANDOFF_CLOCK); - for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++) - conversion[i] = swab32(conversion[i]); - return cm_handoff_cfg; - } else if (handoff_clk == SOC64_HANDOFF_MAGIC_CLOCK) { - return cm_handoff_cfg; - } -#endif - return NULL; -} - -const unsigned int cm_get_osc_clk_hz(void) -{ -#ifdef CONFIG_SPL_BUILD - - u32 clock = readl(SOC64_HANDOFF_CLOCK_OSC); - - writel(clock, - socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD1); -#endif - return readl(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_BOOT_SCRATCH_COLD1); -} - -const unsigned int cm_get_intosc_clk_hz(void) -{ - return CLKMGR_INTOSC_HZ; -} - -const unsigned int cm_get_fpga_clk_hz(void) -{ -#ifdef CONFIG_SPL_BUILD - u32 clock = readl(SOC64_HANDOFF_CLOCK_FPGA); - - writel(clock, - socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD2); -#endif - return readl(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_BOOT_SCRATCH_COLD2); -} diff --git a/arch/arm/mach-socfpga/wrap_pll_config_soc64.c b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c new file mode 100644 index 00000000000..6a0d6b5ead7 --- /dev/null +++ b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Intel Corporation + * + */ + +#include +#include +#include +#include +#include + +const struct cm_config * const cm_get_default_config(void) +{ +#ifdef CONFIG_SPL_BUILD + struct cm_config *cm_handoff_cfg = (struct cm_config *) + (SOC64_HANDOFF_CLOCK + SOC64_HANDOFF_OFFSET_DATA); + u32 *conversion = (u32 *)cm_handoff_cfg; + u32 i; + u32 handoff_clk = readl(SOC64_HANDOFF_CLOCK); + + if (swab32(handoff_clk) == SOC64_HANDOFF_MAGIC_CLOCK) { + writel(swab32(handoff_clk), SOC64_HANDOFF_CLOCK); + for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++) + conversion[i] = swab32(conversion[i]); + return cm_handoff_cfg; + } else if (handoff_clk == SOC64_HANDOFF_MAGIC_CLOCK) { + return cm_handoff_cfg; + } +#endif + return NULL; +} + +const unsigned int cm_get_osc_clk_hz(void) +{ +#ifdef CONFIG_SPL_BUILD + + u32 clock = readl(SOC64_HANDOFF_CLOCK_OSC); + + writel(clock, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD1); +#endif + return readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD1); +} + +const unsigned int cm_get_intosc_clk_hz(void) +{ + return CLKMGR_INTOSC_HZ; +} + +const unsigned int cm_get_fpga_clk_hz(void) +{ +#ifdef CONFIG_SPL_BUILD + u32 clock = readl(SOC64_HANDOFF_CLOCK_FPGA); + + writel(clock, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD2); +#endif + return readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD2); +} -- cgit v1.3.1