From 2b8eabbaf2e2aa19455d880fd13af8c20f72b81f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Barna=C5=9B?= Date: Tue, 19 Mar 2024 18:18:13 +0000 Subject: arm: socfpga: arria10: add option to reprogram the FPGA every reboot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Kconfig that enables FPGA reprogramming with warm boot on Arria 10. This option allows to change the bitstream on the filesystem and apply changes with warm reboot without the need for a power cycle. Signed-off-by: Michał Barnaś --- arch/arm/mach-socfpga/Kconfig | 8 ++++++++ arch/arm/mach-socfpga/spl_a10.c | 8 ++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 1008232cac8..6b6a162f568 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -90,6 +90,14 @@ config TARGET_SOCFPGA_ARRIA10 imply FPGA_SOCFPGA imply SPL_USE_TINY_PRINTF +config SOCFPGA_ARRIA10_ALWAYS_REPROGRAM + bool "Always reprogram Arria 10 FPGA" + depends on TARGET_SOCFPGA_ARRIA10 + help + Arria 10 FPGA is only programmed during the cold boot. + This option forces the FPGA to be reprogrammed every reboot, + allowing to change the bitstream and apply it with warm reboot. + config TARGET_SOCFPGA_CYCLONE5 bool select TARGET_SOCFPGA_GEN5 diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 9edbbf4a29c..3981d2d4f14 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -122,7 +122,10 @@ void spl_board_init(void) arch_early_init_r(); /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */ - if (is_fpgamgr_user_mode()) { + if ((IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) && + is_regular_boot_valid()) || + (!IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) && + is_fpgamgr_user_mode())) { ret = config_pins(gd->fdt_blob, "shared"); if (ret) return; @@ -130,7 +133,8 @@ void spl_board_init(void) ret = config_pins(gd->fdt_blob, "fpga"); if (ret) return; - } else if (!is_fpgamgr_early_user_mode()) { + } else if (IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) || + !is_fpgamgr_early_user_mode()) { /* Program IOSSM(early IO release) or full FPGA */ fpgamgr_program(buf, FPGA_BUFSIZ, 0); -- cgit v1.2.3 From adb64208c8df9b11c351f027cee6f786e8b06058 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Barna=C5=9B?= Date: Tue, 19 Mar 2024 18:18:14 +0000 Subject: chameleonv3: set in defconfig for FPGA to reprogram every reboot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set CONFIG_TARGET_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM as enabled in chameleon v3 board's defconfig. Signed-off-by: Michał Barnaś --- configs/socfpga_chameleonv3_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_chameleonv3_defconfig b/configs/socfpga_chameleonv3_defconfig index 6ea61ca6ea9..7506aa8d329 100644 --- a/configs/socfpga_chameleonv3_defconfig +++ b/configs/socfpga_chameleonv3_defconfig @@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2" CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_SPL_DRIVERS_MISC=y CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y +CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM=y CONFIG_SPL_FS_FAT=y CONFIG_FIT=y CONFIG_SPL_FIT=y -- cgit v1.2.3 From 27ed98d491521a637f2b4468ac021511294f897f Mon Sep 17 00:00:00 2001 From: Wan Yee Lau Date: Thu, 28 Mar 2024 14:24:00 +0800 Subject: drivers: misc: Fixes: Rename CONFIG_SPL_SOCFPGA_SEC_REG to CONFIG_SPL_SOCFPGA_DT_REG Commit 3f190c55a4211215914126b74357344342329943 ("drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA") This commit rename CONFIG_SPL_SOCFPGA_SEC_REG to CONFIG_SPL_SOCFPGA_DT_REG in Makefile. Signed-off-by: Wan Yee Lau --- drivers/misc/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 9e829905f12..e53d52c47b3 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -91,4 +91,4 @@ obj-$(CONFIG_K3_AVS0) += k3_avs.o obj-$(CONFIG_ESM_K3) += k3_esm.o obj-$(CONFIG_ESM_PMIC) += esm_pmic.o obj-$(CONFIG_SL28CPLD) += sl28cpld.o -obj-$(CONFIG_SPL_SOCFPGA_SEC_REG) += socfpga_dtreg.o +obj-$(CONFIG_SPL_SOCFPGA_DT_REG) += socfpga_dtreg.o -- cgit v1.2.3