From 9487764e7e4f58a41fcfc4df7ae0db5fa4e4ffd8 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 4 Oct 2022 10:09:52 +0200 Subject: cmd/sbi: format RustSBI version number The SBI command can print out the version number of the SBI implementation. Choose the correct output format for RustSBI. Signed-off-by: Heinrich Schuchardt Reviewed-by: Rick Chen --- cmd/riscv/sbi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index 522f502435b..9bbe7d4b906 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -74,6 +74,7 @@ static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, vers >> 16, vers & 0xffff); break; case 3: /* KVM */ + case 4: /* RustSBI */ printf("%ld.%ld.%ld", vers >> 16, (vers >> 8) & 0xff, -- cgit v1.3.1 From 72c1f5f282737156ef630db911979eeb16796522 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 4 Oct 2022 10:09:53 +0200 Subject: cmd/sbi: error message for failure to get spec version If calling 'Get SBI specification version' fails, write an error message and return CMD_RET_FAILURE. Signed-off-by: Heinrich Schuchardt Reviewed-by: Rick Chen --- cmd/riscv/sbi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index 9bbe7d4b906..24955d2be19 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -56,8 +56,11 @@ static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, long mvendorid, marchid, mimpid; ret = sbi_get_spec_version(); - if (ret >= 0) - printf("SBI %ld.%ld", ret >> 24, ret & 0xffffff); + if (ret < 0) { + printf("No SBI 0.2+\n"); + return CMD_RET_FAILURE; + } + printf("SBI %ld.%ld", ret >> 24, ret & 0xffffff); impl_id = sbi_get_impl_id(); if (impl_id >= 0) { for (i = 0; i < ARRAY_SIZE(implementations); ++i) { -- cgit v1.3.1 From f22db44c1bb6ae86b0ffb416bdd690bcf97d7250 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 4 Oct 2022 10:09:54 +0200 Subject: cmd/sbi: user friendly short texts In the sbi command use the same short texts for the legacy extensions as the SBI specification 1.0.0. Signed-off-by: Heinrich Schuchardt Reviewed-by: Rick Chen --- cmd/riscv/sbi.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index 24955d2be19..6f2cad4e7ed 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -30,15 +30,15 @@ static struct sbi_imp implementations[] = { }; static struct sbi_ext extensions[] = { - { SBI_EXT_0_1_SET_TIMER, "sbi_set_timer" }, - { SBI_EXT_0_1_CONSOLE_PUTCHAR, "sbi_console_putchar" }, - { SBI_EXT_0_1_CONSOLE_GETCHAR, "sbi_console_getchar" }, - { SBI_EXT_0_1_CLEAR_IPI, "sbi_clear_ipi" }, - { SBI_EXT_0_1_SEND_IPI, "sbi_send_ipi" }, - { SBI_EXT_0_1_REMOTE_FENCE_I, "sbi_remote_fence_i" }, - { SBI_EXT_0_1_REMOTE_SFENCE_VMA, "sbi_remote_sfence_vma" }, - { SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, "sbi_remote_sfence_vma_asid" }, - { SBI_EXT_0_1_SHUTDOWN, "sbi_shutdown" }, + { SBI_EXT_0_1_SET_TIMER, "Set Timer" }, + { SBI_EXT_0_1_CONSOLE_PUTCHAR, "Console Putchar" }, + { SBI_EXT_0_1_CONSOLE_GETCHAR, "Console Getchar" }, + { SBI_EXT_0_1_CLEAR_IPI, "Clear IPI" }, + { SBI_EXT_0_1_SEND_IPI, "Send IPI" }, + { SBI_EXT_0_1_REMOTE_FENCE_I, "Remote FENCE.I" }, + { SBI_EXT_0_1_REMOTE_SFENCE_VMA, "Remote SFENCE.VMA" }, + { SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, "Remote SFENCE.VMA with ASID" }, + { SBI_EXT_0_1_SHUTDOWN, "System Shutdown" }, { SBI_EXT_BASE, "SBI Base Functionality" }, { SBI_EXT_TIME, "Timer Extension" }, { SBI_EXT_IPI, "IPI Extension" }, -- cgit v1.3.1 From e67f34f778baabd76f2e0e645a409fed14d2d156 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 12 Oct 2022 14:59:51 +0200 Subject: riscv: support building double-float modules The riscv32 toolchain for GCC-12 provided by kernel.org contains libgcc.a compiled for double-float. To link to it we have to adjust how we build U-Boot. As U-Boot actually does not use floating point at all this should not make a significant difference for the produced binaries. Signed-off-by: Heinrich Schuchardt Reviewed-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 15 +++++++++++++++ arch/riscv/Makefile | 15 ++++++++++++--- 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 32a90b83b5a..8f9578171d3 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -152,6 +152,21 @@ config RISCV_ISA_C when building U-Boot, which results in compressed instructions in the U-Boot binary. +config RISCV_ISA_F + bool "Standard extension for Single-Precision Floating Point" + default y + help + Adds "F" to the ISA string passed to the compiler. + +config RISCV_ISA_D + bool "Standard extension for Double-Precision Floating Point" + depends on RISCV_ISA_F + default y + help + Adds "D" to the ISA string passed to the compiler and changes the + riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to + lp64d. + config RISCV_ISA_A def_bool y diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 53d1194ffb6..4963b5109b2 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -5,15 +5,22 @@ ifeq ($(CONFIG_ARCH_RV64I),y) ARCH_BASE = rv64im - ABI = lp64 + ABI_BASE = lp64 endif ifeq ($(CONFIG_ARCH_RV32I),y) ARCH_BASE = rv32im - ABI = ilp32 + ABI_BASE = ilp32 endif ifeq ($(CONFIG_RISCV_ISA_A),y) ARCH_A = a endif +ifeq ($(CONFIG_RISCV_ISA_F),y) + ARCH_F = f +endif +ifeq ($(CONFIG_RISCV_ISA_D),y) + ARCH_D = d + ABI_D = d +endif ifeq ($(CONFIG_RISCV_ISA_C),y) ARCH_C = c endif @@ -24,7 +31,9 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) CMODEL = medany endif -RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C) + +RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C) +ABI = $(ABI_BASE)$(ABI_D) # Newer binutils versions default to ISA spec version 20191213 which moves some # instructions from the I extension to the Zicsr and Zifencei extensions. -- cgit v1.3.1 From e77ef0bb74c0df010e83a1f60a1c3004f00703da Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 16 Oct 2022 18:12:32 +0200 Subject: k210: fix k210_pll_calc_config() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The k210 driver is selected by sandbox_defconfig. Building the sandbox on 32bit systems fails with: test/dm/k210_pll.c: In function ‘dm_test_k210_pll_calc_config’: include/linux/bitops.h:11:38: warning: left shift count >= width of type [-Wshift-count-overflow] 11 | #define BIT(nr) (1UL << (nr)) | ^~ test/dm/k210_pll.c:36:54: note: in expansion of macro ‘BIT’ 36 | error = abs((error - BIT(32))) >> 16; | ^~~ Use the BIT_ULL() macro to create a u64 value. Replace abs() by abs64() to get correct results on 32bit system Apply the same for the unit test. Signed-off-by: Heinrich Schuchardt Reviewed-by: Sean Anderson --- drivers/clk/clk_k210.c | 2 +- test/dm/k210_pll.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk_k210.c b/drivers/clk/clk_k210.c index 1961efaa5e7..f7d36963f85 100644 --- a/drivers/clk/clk_k210.c +++ b/drivers/clk/clk_k210.c @@ -846,7 +846,7 @@ again: error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od); /* The lower 16 bits are spurious */ - error = abs((error - BIT(32))) >> 16; + error = abs64((error - BIT_ULL(32))) >> 16; if (error < best_error) { best->r = r; diff --git a/test/dm/k210_pll.c b/test/dm/k210_pll.c index a0cc84c3961..354720f61e2 100644 --- a/test/dm/k210_pll.c +++ b/test/dm/k210_pll.c @@ -33,7 +33,7 @@ static int dm_test_k210_pll_calc_config(u32 rate, u32 rate_in, error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od); /* The lower 16 bits are spurious */ - error = abs((error - BIT(32))) >> 16; + error = abs64((error - BIT_ULL(32))) >> 16; if (error < best_error) { best->r = r; best->f = f; -- cgit v1.3.1 From cb052d771200b15717eeb68f185cf7caa2dcfea0 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 17 Oct 2022 00:42:06 +0800 Subject: riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+ Since OpenSBI commit bf3ef53bb7f5 ("firmware: Enable FW_PIC by default"), OpenSBI runs directly at the load address without any code movement. This causes the SPL version of QEMU 'virt' U-Boot does not boot Linux kernel anymore. In that case, OpenSBI is loaded and runs at 0x81000000, and it creates a 512KiB PMP window from that address. When booting the Linux kernel, moving kernel to its linking address 0x80200000 overlaps the PMP window, and a PMP access failure is raised. Update SPL_OPENSBI_LOAD_ADDR to load OpenSBI to a safe address. Reported-by: Yangjie Zhang Signed-off-by: Bin Meng Tested-by: Yangjie Zhang Reviewed-by: Rick Chen --- board/emulation/qemu-riscv/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index d8c57e6bb05..f9883f18b0b 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -23,7 +23,7 @@ config SPL_TEXT_BASE config SPL_OPENSBI_LOAD_ADDR hex - default 0x81000000 + default 0x80100000 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y -- cgit v1.3.1 From bdb238355c37ac175520577fd2355f01db29714b Mon Sep 17 00:00:00 2001 From: Yu Chien Peter Lin Date: Fri, 14 Oct 2022 15:00:18 +0800 Subject: riscv: andes_plic.c: use modified IPI scheme The IPI scheme in OpenSBI has been updated to support 8-core AE350 platform, the plicsw configuration needs to be modified accordingly. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Rick Chen --- arch/riscv/lib/andes_plic.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index 68514758a86..1eabcacd09d 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plic.c @@ -27,8 +27,8 @@ /* claim register */ #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) -#define ENABLE_HART_IPI (0x80808080) -#define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) +#define ENABLE_HART_IPI (0x01010101) +#define SEND_IPI_TO_HART(hart) (0x1 << (hart)) DECLARE_GLOBAL_DATA_PTR; @@ -36,8 +36,9 @@ static int enable_ipi(int hart) { unsigned int en; - en = ENABLE_HART_IPI >> hart; + en = ENABLE_HART_IPI << hart; writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); + writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic + 0x4, hart)); return 0; } -- cgit v1.3.1 From b3b44c674a473bdd3d53cf5196fae897107af619 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Thu, 20 Oct 2022 13:56:17 +0800 Subject: riscv: ae350: Check firmware_fdt_addr header Check firmware_fdt_addr header to see if it is a valid fdt blob. Signed-off-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang --- board/AndesTech/ax25-ae350/ax25-ae350.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index 36f0dd4b0fd..63a966e0924 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -60,7 +60,7 @@ void *board_fdt_blob_setup(int *err) *err = 0; if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) { - if (gd->arch.firmware_fdt_addr) + if (fdt_magic((uintptr_t)gd->arch.firmware_fdt_addr) == FDT_MAGIC) return (void *)(ulong)gd->arch.firmware_fdt_addr; } -- cgit v1.3.1