From 9390876cc8235fdb339a32c8b8d1af42ced74393 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 19 Sep 2025 14:58:32 +0800 Subject: imx: imx8ulp: Call DM post init function for init_r phase The ELE MU driver needs to be probed at init_r phase as well because some ELE APIs will be called. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/mach-imx/imx8ulp/soc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index e85cb0dd252..7640f9b84da 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -804,6 +804,7 @@ int imx8ulp_dm_post_init(void) return 0; } EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx8ulp_dm_post_init); +EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_R, imx8ulp_dm_post_init); #if defined(CONFIG_XPL_BUILD) __weak void __noreturn jump_to_image(struct spl_image_info *spl_image) -- cgit v1.3.1 From aee235798724fd041af21460e7f6ba02bdeedaeb Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 19 Sep 2025 14:58:33 +0800 Subject: imx8ulp_evk: Fix ELE FW version print bug According to latest ELE Get FW version API, the FW version word is defined as below. The patch version only has 4 bits and minor version has 12 bits. However, the codes use 8 bits for patch version and minor version. Add the patch to fix the issue. ELE firmware version [31] - When set indicates a dirty build. [30] - Reserved [29:28] - Hotfix version. [27] - When set, indicate that ELE FW is authenticated and operational. [26:25] - Reserved [24] - When set, indicate that an alternative FW is running. [23:16] - Indicate the major version. This byte is checked against the version set in the fuses to determine if the FW execution can be authorized [15:4] - Indicate the minor version. [3:0] - Indicate the patch version. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- board/freescale/imx8ulp_evk/spl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c index d123b21b722..fe637077928 100644 --- a/board/freescale/imx8ulp_evk/spl.c +++ b/board/freescale/imx8ulp_evk/spl.c @@ -69,8 +69,8 @@ void display_ele_fw_version(void) } else { printf("ELE firmware version %u.%u.%u-%x", (fw_version & (0x00ff0000)) >> 16, - (fw_version & (0x0000ff00)) >> 8, - (fw_version & (0x000000ff)), sha1); + (fw_version & (0x0000fff0)) >> 4, + (fw_version & (0x0000000f)), sha1); ((fw_version & (0x80000000)) >> 31) == 1 ? puts("-dirty\n") : puts("\n"); } } -- cgit v1.3.1 From 2d7a6f19bbbc0f5eaff79b50497a1b4af1717432 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 19 Sep 2025 14:58:34 +0800 Subject: arm: imx9: Fix LPCG number in ccm_reg structure The LPCG number on iMX93 and iMX91 is 127 not 122. The wrong value is used in ccm_reg structure and Coverity reports several issues as out-of-bounds write. Signed-off-by: Ye Li Reviewed-by: Peng Fan --- arch/arm/include/asm/arch-imx9/clock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h index ffaf6b5f7d8..ddc84d2c9ed 100644 --- a/arch/arm/include/asm/arch-imx9/clock.h +++ b/arch/arm/include/asm/arch-imx9/clock.h @@ -111,7 +111,7 @@ struct ccm_reg { u32 reserved_3[192]; struct ccm_lpcg_oscpll clk_oscplls[19]; /* 0x5000 */ u32 reserved_4[2768]; - struct ccm_lpcg_oscpll clk_lpcgs[122]; /* 0x8000 */ + struct ccm_lpcg_oscpll clk_lpcgs[127]; /* 0x8000 */ }; struct ana_pll_reg_elem { -- cgit v1.3.1 From 1f95591cee01ea5e065b61d99a9853b164acbcf8 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Fri, 19 Sep 2025 09:51:42 +0200 Subject: board: phytec: phycore-imx93: Fix i.MX93 voltage modes Fix support for i.MX93 voltage modes on phyCORE-i.MX93 SoM boards. First of all, Kconfig option CONFIG_IMX9_LOW_DRIVE_MODE is gone since commit c9efcad23741 ("imx93_evk: Remove CONFIG_IMX9_LOW_DRIVE_MODE and ld defconfig") and was replaced by runtime detection mechanism. Thus lets use is_voltage_mode() instead of Kconfig to detect CPU type and select proper voltage mode. Secondly, 1400MHz ND mode (Nominal Drive) requiring 0.85V BUCK voltage was not supported with current power_init_board() PMIC settings. Add check also for this CPU type and set BUCK voltage accordingly. Last but not least, add printf() printouts about PMIC voltage mode to the console. This makes it more apparent and verbose about voltage mode in use. Also our internal tests depend on this printout to catch issues with i.MX93 CPU types and set PMIC voltage modes. Signed-off-by: Primoz Fiser --- board/phytec/phycore_imx93/spl.c | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c index beaa536c600..9768b5257de 100644 --- a/board/phytec/phycore_imx93/spl.c +++ b/board/phytec/phycore_imx93/spl.c @@ -93,7 +93,7 @@ int power_init_board(void) { struct udevice *dev; int ret; - unsigned int val = 0; + unsigned int val = 0, buck_val; ret = pmic_get("pmic@25", &dev); if (ret == -ENODEV) { @@ -115,24 +115,23 @@ int power_init_board(void) return ret; val = ret; - if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) { - /* 0.8v for Low drive mode */ - if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x0c); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x0c); - } else { - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x10); - } + if (is_voltage_mode(VOLT_LOW_DRIVE)) { + buck_val = 0x0c; /* 0.8v for Low drive mode */ + printf("PMIC: Low Drive Voltage Mode\n"); + } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) { + buck_val = 0x10; /* 0.85v for Nominal drive mode */ + printf("PMIC: Nominal Voltage Mode\n"); } else { - /* 0.9v for Over drive mode */ - if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x14); - } else { - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18); - } + buck_val = 0x14; /* 0.9v for Over drive mode */ + printf("PMIC: Over Drive Voltage Mode\n"); + } + + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val); + } else { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4); } /* set standby voltage to 0.65v */ @@ -174,7 +173,7 @@ void board_init_f(ulong dummy) power_init_board(); - if (!IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)) + if (!is_voltage_mode(VOLT_LOW_DRIVE)) set_arm_core_max_clk(); /* Init power of mix */ -- cgit v1.3.1