From 4e3d9844f177bc4e32e60724f87ee5b48a6bd131 Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:29 +0200
Subject: clk: mediatek: mt8188: deduplicate clock gate drivers

MT8188 currently declares a separate U_BOOT_DRIVER, probe() function and
compatible table for each clock gate controller, despite all of them
sharing the same implementation.

Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. All the clock gate controllers can then share a
single U_BOOT_DRIVER, eliminating the duplicated code.

This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.

No functional change intended.

Suggested-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-1-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt8188.c | 138 +++++++++++---------------------------
 1 file changed, 40 insertions(+), 98 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c
index f73fa1fce95..3c14d65487c 100644
--- a/drivers/clk/mediatek/clk-mt8188.c
+++ b/drivers/clk/mediatek/clk-mt8188.c
@@ -1622,6 +1622,8 @@ static const struct mtk_gate infracfg_ao_clks[] = {
 static const struct mtk_clk_tree mt8188_infracfg_ao_clk_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = infracfg_ao_clks,
+	.num_gates = ARRAY_SIZE(infracfg_ao_clks),
 };
 
 static const struct mtk_gate_regs peri_ao_cg_regs = {
@@ -1665,6 +1667,8 @@ static const struct mtk_gate pericfg_ao_clks[] = {
 static const struct mtk_clk_tree mt8188_pericfg_ao_clk_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = pericfg_ao_clks,
+	.num_gates = ARRAY_SIZE(pericfg_ao_clks),
 };
 
 static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
@@ -1700,16 +1704,22 @@ static const struct mtk_gate imp_iic_wrap_en_clks[] = {
 const struct mtk_clk_tree mt8188_imp_iic_wrap_c_clk_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = imp_iic_wrap_c_clks,
+	.num_gates = ARRAY_SIZE(imp_iic_wrap_c_clks),
 };
 
 const struct mtk_clk_tree mt8188_imp_iic_wrap_w_clk_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = imp_iic_wrap_w_clks,
+	.num_gates = ARRAY_SIZE(imp_iic_wrap_w_clks),
 };
 
 const struct mtk_clk_tree mt8188_imp_iic_wrap_en_clk_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = imp_iic_wrap_en_clks,
+	.num_gates = ARRAY_SIZE(imp_iic_wrap_en_clks),
 };
 
 static int mt8188_apmixedsys_probe(struct udevice *dev)
@@ -1722,39 +1732,11 @@ static int mt8188_topckgen_probe(struct udevice *dev)
 	return mtk_common_clk_init(dev, &mt8188_topckgen_clk_tree);
 }
 
-static int mt8188_infracfg_ao_probe(struct udevice *dev)
+static int mt8188_clk_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt8188_infracfg_ao_clk_tree,
-					infracfg_ao_clks,
-					ARRAY_SIZE(infracfg_ao_clks), 0);
-}
-
-static int mt8188_pericfg_ao_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt8188_pericfg_ao_clk_tree,
-					pericfg_ao_clks,
-					ARRAY_SIZE(pericfg_ao_clks), 0);
-}
-
-static int mt8188_imp_iic_wrap_c_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt8188_imp_iic_wrap_c_clk_tree,
-					imp_iic_wrap_c_clks,
-					ARRAY_SIZE(imp_iic_wrap_c_clks), 0);
-}
-
-static int mt8188_imp_iic_wrap_w_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt8188_imp_iic_wrap_w_clk_tree,
-					imp_iic_wrap_w_clks,
-					ARRAY_SIZE(imp_iic_wrap_w_clks), 0);
-}
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 
-static int mt8188_imp_iic_wrap_en_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt8188_imp_iic_wrap_en_clk_tree,
-					imp_iic_wrap_en_clks,
-					ARRAY_SIZE(imp_iic_wrap_en_clks), 0);
+	return mtk_common_clk_init(dev, tree);
 }
 
 static const struct udevice_id mt8188_apmixed_compat[] = {
@@ -1767,30 +1749,30 @@ static const struct udevice_id mt8188_topckgen_compat[] = {
 	{ }
 };
 
-static const struct udevice_id mt8188_infracfg_ao_compat[] = {
-	{ .compatible = "mediatek,mt8188-infracfg-ao", },
-	{ }
-};
-
-static const struct udevice_id mt8188_pericfg_ao_compat[] = {
-	{ .compatible = "mediatek,mt8188-pericfg-ao", },
-	{ }
-};
-
-static const struct udevice_id mt8188_imp_iic_wrap_c_compat[] = {
-	{ .compatible = "mediatek,mt8188-imp-iic-wrap-c", },
-	{ }
-};
-
-static const struct udevice_id mt8188_imp_iic_wrap_w_compat[] = {
-	{ .compatible = "mediatek,mt8188-imp-iic-wrap-w", },
+static const struct udevice_id of_match_mt8188_clk[] = {
+	{
+		.compatible = "mediatek,mt8188-infracfg-ao",
+		.data = (ulong)&mt8188_infracfg_ao_clk_tree,
+	},
+	{
+		.compatible = "mediatek,mt8188-pericfg-ao",
+		.data = (ulong)&mt8188_pericfg_ao_clk_tree,
+	},
+	{
+		.compatible = "mediatek,mt8188-imp-iic-wrap-c",
+		.data = (ulong)&mt8188_imp_iic_wrap_c_clk_tree,
+	},
+	{
+		.compatible = "mediatek,mt8188-imp-iic-wrap-w",
+		.data = (ulong)&mt8188_imp_iic_wrap_w_clk_tree,
+	},
+	{
+		.compatible = "mediatek,mt8188-imp-iic-wrap-en",
+		.data = (ulong)&mt8188_imp_iic_wrap_en_clk_tree,
+	},
 	{ }
 };
 
-static const struct udevice_id mt8188_imp_iic_wrap_en_compat[] = {
-	{ .compatible = "mediatek,mt8188-imp-iic-wrap-en", },
-	{ }
-};
 
 U_BOOT_DRIVER(mt8188_clk_apmixedsys) = {
 	.name = "mt8188-apmixedsys",
@@ -1814,52 +1796,12 @@ U_BOOT_DRIVER(mt8188_clk_topckgen) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mt8188_clk_infracfg_ao) = {
-	.name = "mt8188-infracfg-ao",
-	.id = UCLASS_CLK,
-	.of_match = mt8188_infracfg_ao_compat,
-	.probe = mt8188_infracfg_ao_probe,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
-	.flags = DM_FLAG_PRE_RELOC,
-};
-
-U_BOOT_DRIVER(mt8188_clk_pericfg_ao) = {
-	.name = "mt8188-pericfg-ao",
-	.id = UCLASS_CLK,
-	.of_match = mt8188_pericfg_ao_compat,
-	.probe = mt8188_pericfg_ao_probe,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
-	.flags = DM_FLAG_PRE_RELOC,
-};
-
-U_BOOT_DRIVER(mt8188_clk_imp_iic_wrap_c) = {
-	.name = "mt8188-imp_iic_wrap_c",
+U_BOOT_DRIVER(mt8188_clk) = {
+	.name = "mt8188-clk",
 	.id = UCLASS_CLK,
-	.of_match = mt8188_imp_iic_wrap_c_compat,
-	.probe = mt8188_imp_iic_wrap_c_probe,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
-	.flags = DM_FLAG_PRE_RELOC,
-};
-
-U_BOOT_DRIVER(mt8188_clk_imp_iic_wrap_w) = {
-	.name = "mt8188-imp_iic_wrap_w",
-	.id = UCLASS_CLK,
-	.of_match = mt8188_imp_iic_wrap_w_compat,
-	.probe = mt8188_imp_iic_wrap_w_probe,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
-	.flags = DM_FLAG_PRE_RELOC,
-};
-
-U_BOOT_DRIVER(mt8188_clk_imp_iic_wrap_en) = {
-	.name = "mt8188-imp_iic_wrap_en",
-	.id = UCLASS_CLK,
-	.of_match = mt8188_imp_iic_wrap_en_compat,
-	.probe = mt8188_imp_iic_wrap_en_probe,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.of_match = of_match_mt8188_clk,
+	.probe = mt8188_clk_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
-- 
cgit v1.3.1


From 2460955d031de3052bf88acee50fef64ecc1ef5c Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:30 +0200
Subject: clk: mediatek: mt8188: use driver data to store the clock tree

Pass each controller's struct mtk_clk_tree through the driver data and use
a single shared probe function for all the MT8188 clock drivers, instead of
a dedicated probe per controller.

The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
share the generic probe and get their tree from the compatible data, just
like the clock gate controllers.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-2-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt8188.c | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c
index 3c14d65487c..7f0402a87b6 100644
--- a/drivers/clk/mediatek/clk-mt8188.c
+++ b/drivers/clk/mediatek/clk-mt8188.c
@@ -1722,16 +1722,6 @@ const struct mtk_clk_tree mt8188_imp_iic_wrap_en_clk_tree = {
 	.num_gates = ARRAY_SIZE(imp_iic_wrap_en_clks),
 };
 
-static int mt8188_apmixedsys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt8188_apmixedsys_clk_tree);
-}
-
-static int mt8188_topckgen_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt8188_topckgen_clk_tree);
-}
-
 static int mt8188_clk_probe(struct udevice *dev)
 {
 	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
@@ -1740,12 +1730,18 @@ static int mt8188_clk_probe(struct udevice *dev)
 }
 
 static const struct udevice_id mt8188_apmixed_compat[] = {
-	{ .compatible = "mediatek,mt8188-apmixedsys", },
+	{
+		.compatible = "mediatek,mt8188-apmixedsys",
+		.data = (ulong)&mt8188_apmixedsys_clk_tree,
+	},
 	{ }
 };
 
 static const struct udevice_id mt8188_topckgen_compat[] = {
-	{ .compatible = "mediatek,mt8188-topckgen", },
+	{
+		.compatible = "mediatek,mt8188-topckgen",
+		.data = (ulong)&mt8188_topckgen_clk_tree,
+	},
 	{ }
 };
 
@@ -1779,7 +1775,7 @@ U_BOOT_DRIVER(mt8188_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8188_apmixed_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8188_apmixedsys_probe,
+	.probe = mt8188_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -1790,7 +1786,7 @@ U_BOOT_DRIVER(mt8188_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8188_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8188_topckgen_probe,
+	.probe = mt8188_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
-- 
cgit v1.3.1


From f8a883826abdb00801aebcecb40bce996ca212de Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:31 +0200
Subject: clk: mediatek: mt7622: deduplicate clock gate drivers

MT7622 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for each clock gate controller, despite all of them sharing the same
implementation.

Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. Clock gate controllers that share the same DM flags
and bind() callback can then share a single U_BOOT_DRIVER: the pciesys and
ethsys controllers, which both bind a reset controller at the same offset,
are merged into one driver, and the sgmiisys and ssusbsys controllers into
another.

This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-3-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com> (changed to CONFIG_IS_ENABLED)
---
 drivers/clk/mediatek/clk-mt7622.c | 150 ++++++++++++++++----------------------
 1 file changed, 64 insertions(+), 86 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 76bc31f06d2..0a8185f9027 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -652,9 +652,32 @@ static const struct mtk_clk_tree mt7622_peri_clk_tree = {
 	.num_gates = ARRAY_SIZE(peri_cgs),
 };
 
-static const struct mtk_clk_tree mt7622_clk_tree = {
+static const struct mtk_clk_tree mt7622_pcie_clk_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = pcie_cgs,
+	.num_gates = ARRAY_SIZE(pcie_cgs),
+};
+
+static const struct mtk_clk_tree mt7622_eth_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = eth_cgs,
+	.num_gates = ARRAY_SIZE(eth_cgs),
+};
+
+static const struct mtk_clk_tree mt7622_sgmii_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = sgmii_cgs,
+	.num_gates = ARRAY_SIZE(sgmii_cgs),
+};
+
+static const struct mtk_clk_tree mt7622_ssusb_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = ssusb_cgs,
+	.num_gates = ARRAY_SIZE(ssusb_cgs),
 };
 
 static int mt7622_mcucfg_probe(struct udevice *dev)
@@ -707,56 +730,26 @@ static int mt7622_pericfg_probe(struct udevice *dev)
 	return mtk_common_clk_init(dev, &mt7622_peri_clk_tree);
 }
 
-static int mt7622_pciesys_probe(struct udevice *dev)
+static int mt7622_clk_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs,
-					ARRAY_SIZE(pcie_cgs), 0);
-}
-
-static int mt7622_pciesys_bind(struct udevice *dev)
-{
-	int ret = 0;
-
-	if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) {
-	ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
-	if (ret)
-		debug("Warning: failed to bind reset controller\n");
-	}
-
-	return ret;
-}
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 
-static int mt7622_ethsys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs,
-					ARRAY_SIZE(eth_cgs), 0);
+	return mtk_common_clk_init(dev, tree);
 }
 
-static int mt7622_ethsys_bind(struct udevice *dev)
+static int mt7622_reset_bind(struct udevice *dev)
 {
 	int ret = 0;
 
-#if CONFIG_IS_ENABLED(RESET_MEDIATEK)
-	ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
-	if (ret)
-		debug("Warning: failed to bind reset controller\n");
-#endif
+	if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
+		ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
+		if (ret)
+			debug("Warning: failed to bind reset controller\n");
+	}
 
 	return ret;
 }
 
-static int mt7622_sgmiisys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs,
-					ARRAY_SIZE(sgmii_cgs), 0);
-}
-
-static int mt7622_ssusbsys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs,
-					ARRAY_SIZE(ssusb_cgs), 0);
-}
-
 static const struct udevice_id mt7622_apmixed_compat[] = {
 	{ .compatible = "mediatek,mt7622-apmixedsys" },
 	{ }
@@ -777,18 +770,27 @@ static const struct udevice_id mt7622_pericfg_compat[] = {
 	{ }
 };
 
-static const struct udevice_id mt7622_pciesys_compat[] = {
-	{ .compatible = "mediatek,mt7622-pciesys", },
-	{ }
-};
-
-static const struct udevice_id mt7622_ethsys_compat[] = {
-	{ .compatible = "mediatek,mt7622-ethsys", },
+static const struct udevice_id of_match_mt7622_clk_eth[] = {
+	{
+		.compatible = "mediatek,mt7622-pciesys",
+		.data = (ulong)&mt7622_pcie_clk_tree,
+	},
+	{
+		.compatible = "mediatek,mt7622-ethsys",
+		.data = (ulong)&mt7622_eth_clk_tree,
+	},
 	{ }
 };
 
-static const struct udevice_id mt7622_sgmiisys_compat[] = {
-	{ .compatible = "mediatek,mt7622-sgmiisys", },
+static const struct udevice_id of_match_mt7622_clk[] = {
+	{
+		.compatible = "mediatek,mt7622-sgmiisys",
+		.data = (ulong)&mt7622_sgmii_clk_tree,
+	},
+	{
+		.compatible = "mediatek,mt7622-ssusbsys",
+		.data = (ulong)&mt7622_ssusb_clk_tree,
+	},
 	{ }
 };
 
@@ -797,11 +799,6 @@ static const struct udevice_id mt7622_mcucfg_compat[] = {
 	{ }
 };
 
-static const struct udevice_id mt7622_ssusbsys_compat[] = {
-	{ .compatible = "mediatek,mt7622-ssusbsys" },
-	{ }
-};
-
 U_BOOT_DRIVER(mt7622_mcucfg) = {
 	.name = "mt7622-mcucfg",
 	.id = UCLASS_SYSCON,
@@ -852,40 +849,21 @@ U_BOOT_DRIVER(mt7622_clk_pericfg) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mt7622_clk_pciesys) = {
-	.name = "mt7622-clock-pciesys",
-	.id = UCLASS_CLK,
-	.of_match = mt7622_pciesys_compat,
-	.probe = mt7622_pciesys_probe,
-	.bind = mt7622_pciesys_bind,
-	.priv_auto	= sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
-};
-
-U_BOOT_DRIVER(mt7622_clk_ethsys) = {
-	.name = "mt7622-clock-ethsys",
+U_BOOT_DRIVER(mt7622_clk_eth) = {
+	.name = "mt7622-clk-eth",
 	.id = UCLASS_CLK,
-	.of_match = mt7622_ethsys_compat,
-	.probe = mt7622_ethsys_probe,
-	.bind = mt7622_ethsys_bind,
-	.priv_auto	= sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
-};
-
-U_BOOT_DRIVER(mt7622_clk_sgmiisys) = {
-	.name = "mt7622-clock-sgmiisys",
-	.id = UCLASS_CLK,
-	.of_match = mt7622_sgmiisys_compat,
-	.probe = mt7622_sgmiisys_probe,
-	.priv_auto	= sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.of_match = of_match_mt7622_clk_eth,
+	.probe = mt7622_clk_probe,
+	.bind = mt7622_reset_bind,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 };
 
-U_BOOT_DRIVER(mt7622_clk_ssusbsys) = {
-	.name = "mt7622-clock-ssusbsys",
+U_BOOT_DRIVER(mt7622_clk) = {
+	.name = "mt7622-clk",
 	.id = UCLASS_CLK,
-	.of_match = mt7622_ssusbsys_compat,
-	.probe = mt7622_ssusbsys_probe,
-	.priv_auto	= sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.of_match = of_match_mt7622_clk,
+	.probe = mt7622_clk_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 };
-- 
cgit v1.3.1


From 07cc855d80175b837a5860fef7f321eb997a7f3e Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:32 +0200
Subject: clk: mediatek: mt7622: use driver data to store the clock tree

Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT7622 clock drivers, instead of a
dedicated probe per controller.

The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data. The apmixedsys probe still performs
its SoC specific register tweaks. The infracfg and pericfg controllers share
the same ops, flags and (absent) bind() callback and are merged into a
single driver.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-4-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt7622.c | 60 ++++++++++++++-------------------------
 1 file changed, 22 insertions(+), 38 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 0a8185f9027..b085689f4d4 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -699,9 +699,10 @@ static int mt7622_mcucfg_probe(struct udevice *dev)
 static int mt7622_apmixedsys_probe(struct udevice *dev)
 {
 	struct mtk_clk_priv *priv = dev_get_priv(dev);
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 	int ret;
 
-	ret = mtk_common_clk_init(dev, &mt7622_apmixed_clk_tree);
+	ret = mtk_common_clk_init(dev, tree);
 	if (ret)
 		return ret;
 
@@ -715,21 +716,6 @@ static int mt7622_apmixedsys_probe(struct udevice *dev)
 	return 0;
 }
 
-static int mt7622_topckgen_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt7622_topckgen_clk_tree);
-}
-
-static int mt7622_infracfg_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt7622_infra_clk_tree);
-}
-
-static int mt7622_pericfg_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt7622_peri_clk_tree);
-}
-
 static int mt7622_clk_probe(struct udevice *dev)
 {
 	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
@@ -751,22 +737,30 @@ static int mt7622_reset_bind(struct udevice *dev)
 }
 
 static const struct udevice_id mt7622_apmixed_compat[] = {
-	{ .compatible = "mediatek,mt7622-apmixedsys" },
+	{
+		.compatible = "mediatek,mt7622-apmixedsys",
+		.data = (ulong)&mt7622_apmixed_clk_tree,
+	},
 	{ }
 };
 
 static const struct udevice_id mt7622_topckgen_compat[] = {
-	{ .compatible = "mediatek,mt7622-topckgen" },
-	{ }
-};
-
-static const struct udevice_id mt7622_infracfg_compat[] = {
-	{ .compatible = "mediatek,mt7622-infracfg", },
+	{
+		.compatible = "mediatek,mt7622-topckgen",
+		.data = (ulong)&mt7622_topckgen_clk_tree,
+	},
 	{ }
 };
 
-static const struct udevice_id mt7622_pericfg_compat[] = {
-	{ .compatible = "mediatek,mt7622-pericfg", },
+static const struct udevice_id of_match_mt7622_infracfg[] = {
+	{
+		.compatible = "mediatek,mt7622-infracfg",
+		.data = (ulong)&mt7622_infra_clk_tree,
+	},
+	{
+		.compatible = "mediatek,mt7622-pericfg",
+		.data = (ulong)&mt7622_peri_clk_tree,
+	},
 	{ }
 };
 
@@ -823,7 +817,7 @@ U_BOOT_DRIVER(mt7622_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt7622_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7622_topckgen_probe,
+	.probe = mt7622_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -832,23 +826,13 @@ U_BOOT_DRIVER(mt7622_clk_topckgen) = {
 U_BOOT_DRIVER(mt7622_clk_infracfg) = {
 	.name = "mt7622-clock-infracfg",
 	.id = UCLASS_CLK,
-	.of_match = mt7622_infracfg_compat,
-	.probe = mt7622_infracfg_probe,
+	.of_match = of_match_mt7622_infracfg,
+	.probe = mt7622_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mt7622_clk_pericfg) = {
-	.name = "mt7622-clock-pericfg",
-	.id = UCLASS_CLK,
-	.of_match = mt7622_pericfg_compat,
-	.probe = mt7622_pericfg_probe,
-	.priv_auto = sizeof(struct mtk_clk_priv),
-	.ops = &mtk_clk_infrasys_ops,
-	.flags = DM_FLAG_PRE_RELOC,
-};
-
 U_BOOT_DRIVER(mt7622_clk_eth) = {
 	.name = "mt7622-clk-eth",
 	.id = UCLASS_CLK,
-- 
cgit v1.3.1


From 2428c2b14182f08d1ae1cafc2b76cddf8a5b9355 Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:33 +0200
Subject: clk: mediatek: mt7623: deduplicate clock gate drivers

MT7623 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for each clock gate controller, despite all of them sharing the same
implementation.

Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. The ethsys and hifsys controllers, which share the
same reset-binding bind() callback, are merged into a single U_BOOT_DRIVER;
infracfg keeps its own driver since it is pre-relocation and does not bind a
reset controller.

This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-5-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt7623.c | 89 ++++++++++++++++++++-------------------
 1 file changed, 46 insertions(+), 43 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index 56912ebdb53..1b8507eb8ef 100644
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -1064,15 +1064,35 @@ static int mt7623_topckgen_probe(struct udevice *dev)
 	return mtk_common_clk_init(dev, &mt7623_topckgen_clk_tree);
 }
 
-static const struct mtk_clk_tree mt7623_clk_gate_tree = {
+static const struct mtk_clk_tree mt7623_infracfg_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates_offs = 1,
+	.gates = infra_cgs,
+	.num_gates = ARRAY_SIZE(infra_cgs),
 };
 
-static int mt7623_infracfg_probe(struct udevice *dev)
+static const struct mtk_clk_tree mt7623_hifsys_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates_offs = 1,
+	.gates = hif_cgs,
+	.num_gates = ARRAY_SIZE(hif_cgs),
+};
+
+static const struct mtk_clk_tree mt7623_ethsys_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates_offs = 1,
+	.gates = eth_cgs,
+	.num_gates = ARRAY_SIZE(eth_cgs),
+};
+
+static int mt7623_clk_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, infra_cgs,
-					ARRAY_SIZE(infra_cgs), 1);
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
+
+	return mtk_common_clk_init(dev, tree);
 }
 
 static const struct mtk_clk_tree mt7623_clk_peri_tree = {
@@ -1093,18 +1113,6 @@ static int mt7623_pericfg_probe(struct udevice *dev)
 	return mtk_common_clk_init(dev, &mt7623_clk_peri_tree);
 }
 
-static int mt7623_hifsys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, hif_cgs,
-					ARRAY_SIZE(hif_cgs), 1);
-}
-
-static int mt7623_ethsys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, eth_cgs,
-					ARRAY_SIZE(eth_cgs), 1);
-}
-
 static int mt7623_ethsys_hifsys_bind(struct udevice *dev)
 {
 	int ret = 0;
@@ -1129,7 +1137,10 @@ static const struct udevice_id mt7623_topckgen_compat[] = {
 };
 
 static const struct udevice_id mt7623_infracfg_compat[] = {
-	{ .compatible = "mediatek,mt7623-infracfg", },
+	{
+		.compatible = "mediatek,mt7623-infracfg",
+		.data = (ulong)&mt7623_infracfg_tree,
+	},
 	{ }
 };
 
@@ -1138,13 +1149,15 @@ static const struct udevice_id mt7623_pericfg_compat[] = {
 	{ }
 };
 
-static const struct udevice_id mt7623_ethsys_compat[] = {
-	{ .compatible = "mediatek,mt7623-ethsys" },
-	{ }
-};
-
-static const struct udevice_id mt7623_hifsys_compat[] = {
-	{ .compatible = "mediatek,mt7623-hifsys" },
+static const struct udevice_id of_match_mt7623_clk_eth[] = {
+	{
+		.compatible = "mediatek,mt7623-ethsys",
+		.data = (ulong)&mt7623_ethsys_tree,
+	},
+	{
+		.compatible = "mediatek,mt7623-hifsys",
+		.data = (ulong)&mt7623_hifsys_tree,
+	},
 	{ }
 };
 
@@ -1187,9 +1200,9 @@ U_BOOT_DRIVER(mt7623_clk_infracfg) = {
 	.name = "mt7623-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7623_infracfg_compat,
-	.probe = mt7623_infracfg_probe,
-	.priv_auto	= sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.probe = mt7623_clk_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
@@ -1203,22 +1216,12 @@ U_BOOT_DRIVER(mt7623_clk_pericfg) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mt7623_clk_hifsys) = {
-	.name = "mt7623-clock-hifsys",
+U_BOOT_DRIVER(mt7623_clk_eth) = {
+	.name = "mt7623-clk-eth",
 	.id = UCLASS_CLK,
-	.of_match = mt7623_hifsys_compat,
-	.probe = mt7623_hifsys_probe,
+	.of_match = of_match_mt7623_clk_eth,
+	.probe = mt7623_clk_probe,
 	.bind = mt7623_ethsys_hifsys_bind,
-	.priv_auto	= sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
-};
-
-U_BOOT_DRIVER(mt7623_clk_ethsys) = {
-	.name = "mt7623-clock-ethsys",
-	.id = UCLASS_CLK,
-	.of_match = mt7623_ethsys_compat,
-	.probe = mt7623_ethsys_probe,
-	.bind = mt7623_ethsys_hifsys_bind,
-	.priv_auto	= sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 };
-- 
cgit v1.3.1


From 45c29eade55b30be4a3bfe1907308d62322bd574 Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:34 +0200
Subject: clk: mediatek: mt7623: use driver data to store the clock tree

Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT7623 clock drivers, instead of a
dedicated probe per controller.

The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data. The apmixedsys probe still performs
its SoC specific register tweaks.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-6-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt7623.c | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index 1b8507eb8ef..6a6e61af5db 100644
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -1045,9 +1045,10 @@ static int mt7623_mcucfg_probe(struct udevice *dev)
 static int mt7623_apmixedsys_probe(struct udevice *dev)
 {
 	struct mtk_clk_priv *priv = dev_get_priv(dev);
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 	int ret;
 
-	ret = mtk_common_clk_init(dev, &mt7623_apmixedsys_clk_tree);
+	ret = mtk_common_clk_init(dev, tree);
 	if (ret)
 		return ret;
 
@@ -1059,11 +1060,6 @@ static int mt7623_apmixedsys_probe(struct udevice *dev)
 	return 0;
 }
 
-static int mt7623_topckgen_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt7623_topckgen_clk_tree);
-}
-
 static const struct mtk_clk_tree mt7623_infracfg_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
@@ -1108,11 +1104,6 @@ static const struct mtk_clk_tree mt7623_clk_peri_tree = {
 	.num_gates = ARRAY_SIZE(peri_cgs),
 };
 
-static int mt7623_pericfg_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt7623_clk_peri_tree);
-}
-
 static int mt7623_ethsys_hifsys_bind(struct udevice *dev)
 {
 	int ret = 0;
@@ -1127,12 +1118,18 @@ static int mt7623_ethsys_hifsys_bind(struct udevice *dev)
 }
 
 static const struct udevice_id mt7623_apmixed_compat[] = {
-	{ .compatible = "mediatek,mt7623-apmixedsys" },
+	{
+		.compatible = "mediatek,mt7623-apmixedsys",
+		.data = (ulong)&mt7623_apmixedsys_clk_tree,
+	},
 	{ }
 };
 
 static const struct udevice_id mt7623_topckgen_compat[] = {
-	{ .compatible = "mediatek,mt7623-topckgen" },
+	{
+		.compatible = "mediatek,mt7623-topckgen",
+		.data = (ulong)&mt7623_topckgen_clk_tree,
+	},
 	{ }
 };
 
@@ -1145,7 +1142,10 @@ static const struct udevice_id mt7623_infracfg_compat[] = {
 };
 
 static const struct udevice_id mt7623_pericfg_compat[] = {
-	{ .compatible = "mediatek,mt7623-pericfg", },
+	{
+		.compatible = "mediatek,mt7623-pericfg",
+		.data = (ulong)&mt7623_clk_peri_tree,
+	},
 	{ }
 };
 
@@ -1190,7 +1190,7 @@ U_BOOT_DRIVER(mt7623_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt7623_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7623_topckgen_probe,
+	.probe = mt7623_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -1210,7 +1210,7 @@ U_BOOT_DRIVER(mt7623_clk_pericfg) = {
 	.name = "mt7623-pericfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7623_pericfg_compat,
-	.probe = mt7623_pericfg_probe,
+	.probe = mt7623_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
-- 
cgit v1.3.1


From e1fdd94f78fecd2bd4706bf1efbcf0ea896b24c0 Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:35 +0200
Subject: clk: mediatek: mt7629: deduplicate clock gate drivers

MT7629 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for each clock gate controller, despite all of them sharing the same
implementation.

Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. Controllers that share the same DM flags and bind()
callback are then merged: infracfg and pericfg into one pre-relocation
driver, sgmiisys and ssusbsys into another. ethsys keeps its own driver as
it binds a reset controller.

While at it, this fixes a latent off-by-one in the infracfg gate lookup: its
clock IDs start at CLK_INFRA_DBGCLK_PD (1), but the old code passed a gate
offset of 0, so requesting e.g. CLK_INFRA_TRNG_PD resolved to the wrong
gate. The offset is now taken from the first gate ID, like the other
controllers.

This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-7-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt7629.c | 145 +++++++++++++++++++-------------------
 1 file changed, 71 insertions(+), 74 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
index aee340aeb37..dd546a4ad42 100644
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -598,9 +598,41 @@ static const struct mtk_clk_tree mt7629_topckgen_clk_tree = {
 	.type = MTK_CLK_TREE_TOPCKGEN,
 };
 
-static const struct mtk_clk_tree mt7629_clk_tree = {
+static const struct mtk_clk_tree mt7629_infracfg_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates_offs = CLK_INFRA_DBGCLK_PD,
+	.gates = infra_cgs,
+	.num_gates = ARRAY_SIZE(infra_cgs),
+};
+
+static const struct mtk_clk_tree mt7629_pericfg_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates_offs = CLK_PERI_PWM1_PD,
+	.gates = peri_cgs,
+	.num_gates = ARRAY_SIZE(peri_cgs),
+};
+
+static const struct mtk_clk_tree mt7629_ethsys_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = eth_cgs,
+	.num_gates = ARRAY_SIZE(eth_cgs),
+};
+
+static const struct mtk_clk_tree mt7629_sgmii_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = sgmii_cgs,
+	.num_gates = ARRAY_SIZE(sgmii_cgs),
+};
+
+static const struct mtk_clk_tree mt7629_ssusb_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = ssusb_cgs,
+	.num_gates = ARRAY_SIZE(ssusb_cgs),
 };
 
 static int mt7629_mcucfg_probe(struct udevice *dev)
@@ -641,22 +673,11 @@ static int mt7629_topckgen_probe(struct udevice *dev)
 	return mtk_common_clk_init(dev, &mt7629_topckgen_clk_tree);
 }
 
-static int mt7629_infracfg_probe(struct udevice *dev)
+static int mt7629_clk_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, infra_cgs,
-					ARRAY_SIZE(infra_cgs), 0);
-}
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 
-static int mt7629_pericfg_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, peri_cgs,
-					ARRAY_SIZE(peri_cgs), CLK_PERI_PWM1_PD);
-}
-
-static int mt7629_ethsys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, eth_cgs,
-					ARRAY_SIZE(eth_cgs), 0);
+	return mtk_common_clk_init(dev, tree);
 }
 
 static int mt7629_ethsys_bind(struct udevice *dev)
@@ -672,18 +693,6 @@ static int mt7629_ethsys_bind(struct udevice *dev)
 	return ret;
 }
 
-static int mt7629_sgmiisys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs,
-					ARRAY_SIZE(sgmii_cgs), 0);
-}
-
-static int mt7629_ssusbsys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, ssusb_cgs,
-					ARRAY_SIZE(ssusb_cgs), 0);
-}
-
 static const struct udevice_id mt7629_apmixed_compat[] = {
 	{ .compatible = "mediatek,mt7629-apmixedsys" },
 	{ }
@@ -694,28 +703,35 @@ static const struct udevice_id mt7629_topckgen_compat[] = {
 	{ }
 };
 
-static const struct udevice_id mt7629_infracfg_compat[] = {
-	{ .compatible = "mediatek,mt7629-infracfg", },
-	{ }
-};
-
-static const struct udevice_id mt7629_pericfg_compat[] = {
-	{ .compatible = "mediatek,mt7629-pericfg", },
+static const struct udevice_id of_match_mt7629_infracfg[] = {
+	{
+		.compatible = "mediatek,mt7629-infracfg",
+		.data = (ulong)&mt7629_infracfg_tree,
+	},
+	{
+		.compatible = "mediatek,mt7629-pericfg",
+		.data = (ulong)&mt7629_pericfg_tree,
+	},
 	{ }
 };
 
 static const struct udevice_id mt7629_ethsys_compat[] = {
-	{ .compatible = "mediatek,mt7629-ethsys", },
-	{ }
-};
-
-static const struct udevice_id mt7629_sgmiisys_compat[] = {
-	{ .compatible = "mediatek,mt7629-sgmiisys", },
+	{
+		.compatible = "mediatek,mt7629-ethsys",
+		.data = (ulong)&mt7629_ethsys_tree,
+	},
 	{ }
 };
 
-static const struct udevice_id mt7629_ssusbsys_compat[] = {
-	{ .compatible = "mediatek,mt7629-ssusbsys" },
+static const struct udevice_id of_match_mt7629_clk[] = {
+	{
+		.compatible = "mediatek,mt7629-sgmiisys",
+		.data = (ulong)&mt7629_sgmii_clk_tree,
+	},
+	{
+		.compatible = "mediatek,mt7629-ssusbsys",
+		.data = (ulong)&mt7629_ssusb_clk_tree,
+	},
 	{ }
 };
 
@@ -757,20 +773,10 @@ U_BOOT_DRIVER(mt7629_clk_topckgen) = {
 U_BOOT_DRIVER(mt7629_clk_infracfg) = {
 	.name = "mt7629-clock-infracfg",
 	.id = UCLASS_CLK,
-	.of_match = mt7629_infracfg_compat,
-	.probe = mt7629_infracfg_probe,
-	.priv_auto	= sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
-	.flags = DM_FLAG_PRE_RELOC,
-};
-
-U_BOOT_DRIVER(mt7629_clk_pericfg) = {
-	.name = "mt7629-clock-pericfg",
-	.id = UCLASS_CLK,
-	.of_match = mt7629_pericfg_compat,
-	.probe = mt7629_pericfg_probe,
-	.priv_auto	= sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.of_match = of_match_mt7629_infracfg,
+	.probe = mt7629_clk_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
@@ -778,26 +784,17 @@ U_BOOT_DRIVER(mt7629_clk_ethsys) = {
 	.name = "mt7629-clock-ethsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7629_ethsys_compat,
-	.probe = mt7629_ethsys_probe,
+	.probe = mt7629_clk_probe,
 	.bind = mt7629_ethsys_bind,
-	.priv_auto	= sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
-};
-
-U_BOOT_DRIVER(mt7629_clk_sgmiisys) = {
-	.name = "mt7629-clock-sgmiisys",
-	.id = UCLASS_CLK,
-	.of_match = mt7629_sgmiisys_compat,
-	.probe = mt7629_sgmiisys_probe,
-	.priv_auto	= sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 };
 
-U_BOOT_DRIVER(mt7629_clk_ssusbsys) = {
-	.name = "mt7629-clock-ssusbsys",
+U_BOOT_DRIVER(mt7629_clk) = {
+	.name = "mt7629-clk",
 	.id = UCLASS_CLK,
-	.of_match = mt7629_ssusbsys_compat,
-	.probe = mt7629_ssusbsys_probe,
-	.priv_auto	= sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.of_match = of_match_mt7629_clk,
+	.probe = mt7629_clk_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 };
-- 
cgit v1.3.1


From 21aacf2979a63e02ad07616ff2319dc3f6f7886d Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:36 +0200
Subject: clk: mediatek: mt7629: use driver data to store the clock tree

Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT7629 clock drivers, instead of a
dedicated probe per controller.

The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data. The apmixedsys probe still performs
its SoC specific register tweaks.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-8-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt7629.c | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
index dd546a4ad42..f7a5f9f75ce 100644
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -654,9 +654,10 @@ static int mt7629_mcucfg_probe(struct udevice *dev)
 static int mt7629_apmixedsys_probe(struct udevice *dev)
 {
 	struct mtk_clk_priv *priv = dev_get_priv(dev);
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 	int ret;
 
-	ret = mtk_common_clk_init(dev, &mt7629_apmixed_clk_tree);
+	ret = mtk_common_clk_init(dev, tree);
 	if (ret)
 		return ret;
 
@@ -668,11 +669,6 @@ static int mt7629_apmixedsys_probe(struct udevice *dev)
 	return 0;
 }
 
-static int mt7629_topckgen_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt7629_topckgen_clk_tree);
-}
-
 static int mt7629_clk_probe(struct udevice *dev)
 {
 	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
@@ -694,12 +690,18 @@ static int mt7629_ethsys_bind(struct udevice *dev)
 }
 
 static const struct udevice_id mt7629_apmixed_compat[] = {
-	{ .compatible = "mediatek,mt7629-apmixedsys" },
+	{
+		.compatible = "mediatek,mt7629-apmixedsys",
+		.data = (ulong)&mt7629_apmixed_clk_tree,
+	},
 	{ }
 };
 
 static const struct udevice_id mt7629_topckgen_compat[] = {
-	{ .compatible = "mediatek,mt7629-topckgen" },
+	{
+		.compatible = "mediatek,mt7629-topckgen",
+		.data = (ulong)&mt7629_topckgen_clk_tree,
+	},
 	{ }
 };
 
@@ -764,7 +766,7 @@ U_BOOT_DRIVER(mt7629_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt7629_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7629_topckgen_probe,
+	.probe = mt7629_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
-- 
cgit v1.3.1


From d474acfa02f6e7fd9af2912198cf6986b7278f3c Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:37 +0200
Subject: clk: mediatek: mt7981: deduplicate clock gate drivers

MT7981 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for each clock gate controller, despite all of them sharing the same
implementation.

Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. The two sgmiisys controllers, which share the same DM
flags and (absent) bind() callback, are merged into a single U_BOOT_DRIVER;
ethsys keeps its own driver as it binds a reset controller.

This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-9-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt7981.c | 91 ++++++++++++++++++++-------------------
 1 file changed, 46 insertions(+), 45 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c
index 4e3a1c9d835..82ff1e39b0d 100644
--- a/drivers/clk/mediatek/clk-mt7981.c
+++ b/drivers/clk/mediatek/clk-mt7981.c
@@ -656,10 +656,12 @@ static const struct mtk_clk_tree mt7981_infracfg_clk_tree = {
 	.type = MTK_CLK_TREE_INFRASYS,
 };
 
-static const struct mtk_clk_tree mt7981_clk_tree = {
-	.ext_clk_rates = ext_clock_rates,
-	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
-};
+static int mt7981_clk_probe(struct udevice *dev)
+{
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
+
+	return mtk_common_clk_init(dev, tree);
+}
 
 static const struct udevice_id mt7981_fixed_pll_compat[] = {
 	{ .compatible = "mediatek,mt7981-fixed-plls" },
@@ -751,24 +753,11 @@ static const struct mtk_gate sgmii0_cgs[] = {
 	GATE_SGMII(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", CLK_TOP_USB_CDR_CK, 5),
 };
 
-static int mt7981_sgmii0sys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7981_clk_tree,
-					sgmii0_cgs, ARRAY_SIZE(sgmii0_cgs), 0);
-}
-
-static const struct udevice_id mt7981_sgmii0sys_compat[] = {
-	{ .compatible = "mediatek,mt7981-sgmiisys_0", },
-	{}
-};
-
-U_BOOT_DRIVER(mt7981_clk_sgmii0sys) = {
-	.name = "mt7981-clock-sgmii0sys",
-	.id = UCLASS_CLK,
-	.of_match = mt7981_sgmii0sys_compat,
-	.probe = mt7981_sgmii0sys_probe,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+static const struct mtk_clk_tree mt7981_sgmii0_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = sgmii0_cgs,
+	.num_gates = ARRAY_SIZE(sgmii0_cgs),
 };
 
 static const struct mtk_gate sgmii1_cgs[] = {
@@ -778,24 +767,32 @@ static const struct mtk_gate sgmii1_cgs[] = {
 	GATE_SGMII(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", CLK_TOP_USB_CDR_CK, 5),
 };
 
-static int mt7981_sgmii1sys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7981_clk_tree,
-					sgmii1_cgs, ARRAY_SIZE(sgmii1_cgs), 0);
-}
-
-static const struct udevice_id mt7981_sgmii1sys_compat[] = {
-	{ .compatible = "mediatek,mt7981-sgmiisys_1", },
+static const struct mtk_clk_tree mt7981_sgmii1_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = sgmii1_cgs,
+	.num_gates = ARRAY_SIZE(sgmii1_cgs),
+};
+
+static const struct udevice_id of_match_mt7981_sgmiisys[] = {
+	{
+		.compatible = "mediatek,mt7981-sgmiisys_0",
+		.data = (ulong)&mt7981_sgmii0_clk_tree,
+	},
+	{
+		.compatible = "mediatek,mt7981-sgmiisys_1",
+		.data = (ulong)&mt7981_sgmii1_clk_tree,
+	},
 	{}
 };
 
-U_BOOT_DRIVER(mt7981_clk_sgmii1sys) = {
-	.name = "mt7981-clock-sgmii1sys",
+U_BOOT_DRIVER(mt7981_clk_sgmiisys) = {
+	.name = "mt7981-clock-sgmiisys",
 	.id = UCLASS_CLK,
-	.of_match = mt7981_sgmii1sys_compat,
-	.probe = mt7981_sgmii1sys_probe,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.of_match = of_match_mt7981_sgmiisys,
+	.probe = mt7981_clk_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 };
 
 /* ethsys */
@@ -819,11 +816,12 @@ static const struct mtk_gate eth_cgs[] = {
 	GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", CLK_TOP_NETSYS_WED_MCU, 15),
 };
 
-static int mt7981_ethsys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7981_clk_tree,
-					eth_cgs, ARRAY_SIZE(eth_cgs), 0);
-}
+static const struct mtk_clk_tree mt7981_eth_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = eth_cgs,
+	.num_gates = ARRAY_SIZE(eth_cgs),
+};
 
 static int mt7981_ethsys_bind(struct udevice *dev)
 {
@@ -839,7 +837,10 @@ static int mt7981_ethsys_bind(struct udevice *dev)
 }
 
 static const struct udevice_id mt7981_ethsys_compat[] = {
-	{ .compatible = "mediatek,mt7981-ethsys", },
+	{
+		.compatible = "mediatek,mt7981-ethsys",
+		.data = (ulong)&mt7981_eth_clk_tree,
+	},
 	{}
 };
 
@@ -847,8 +848,8 @@ U_BOOT_DRIVER(mt7981_clk_ethsys) = {
 	.name = "mt7981-clock-ethsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7981_ethsys_compat,
-	.probe = mt7981_ethsys_probe,
+	.probe = mt7981_clk_probe,
 	.bind = mt7981_ethsys_bind,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 };
-- 
cgit v1.3.1


From 8d0b12cc06a24b830428907a8eea19c344f5ea4c Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:38 +0200
Subject: clk: mediatek: mt7981: use driver data to store the clock tree

Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for the MT7981 clock drivers, instead of a
dedicated probe per controller.

The fixed-pll, topckgen and infracfg controllers keep their own U_BOOT_DRIVER
since they rely on dedicated ops and on the parent bind() callback, but they
now get their tree from the compatible data. The topckgen probe still
performs its SoC specific register tweaks.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-10-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt7981.c | 37 ++++++++++++++++++++-----------------
 1 file changed, 20 insertions(+), 17 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c
index 82ff1e39b0d..cd1eed46383 100644
--- a/drivers/clk/mediatek/clk-mt7981.c
+++ b/drivers/clk/mediatek/clk-mt7981.c
@@ -664,29 +664,34 @@ static int mt7981_clk_probe(struct udevice *dev)
 }
 
 static const struct udevice_id mt7981_fixed_pll_compat[] = {
-	{ .compatible = "mediatek,mt7981-fixed-plls" },
-	{ .compatible = "mediatek,mt7981-apmixedsys" },
+	{
+		.compatible = "mediatek,mt7981-fixed-plls",
+		.data = (ulong)&mt7981_fixed_pll_clk_tree,
+	},
+	{
+		.compatible = "mediatek,mt7981-apmixedsys",
+		.data = (ulong)&mt7981_fixed_pll_clk_tree,
+	},
 	{}
 };
 
 static const struct udevice_id mt7981_topckgen_compat[] = {
-	{ .compatible = "mediatek,mt7981-topckgen" },
+	{
+		.compatible = "mediatek,mt7981-topckgen",
+		.data = (ulong)&mt7981_topckgen_clk_tree,
+	},
 	{}
 };
 
-static int mt7981_fixed_pll_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt7981_fixed_pll_clk_tree);
-}
-
 static int mt7981_topckgen_probe(struct udevice *dev)
 {
 	struct mtk_clk_priv *priv = dev_get_priv(dev);
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 
 	priv->base = dev_read_addr_ptr(dev);
 	writel(MT7981_CLK_PDN_EN_WRITE, priv->base + MT7981_CLK_PDN);
 
-	return mtk_common_clk_init(dev, &mt7981_topckgen_clk_tree);
+	return mtk_common_clk_init(dev, tree);
 }
 
 U_BOOT_DRIVER(mt7981_clk_apmixedsys) = {
@@ -694,7 +699,7 @@ U_BOOT_DRIVER(mt7981_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt7981_fixed_pll_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7981_fixed_pll_probe,
+	.probe = mt7981_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_fixed_pll_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -712,21 +717,19 @@ U_BOOT_DRIVER(mt7981_clk_topckgen) = {
 };
 
 static const struct udevice_id mt7981_infracfg_compat[] = {
-	{ .compatible = "mediatek,mt7981-infracfg" },
+	{
+		.compatible = "mediatek,mt7981-infracfg",
+		.data = (ulong)&mt7981_infracfg_clk_tree,
+	},
 	{}
 };
 
-static int mt7981_infracfg_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt7981_infracfg_clk_tree);
-}
-
 U_BOOT_DRIVER(mt7981_clk_infracfg) = {
 	.name = "mt7981-clock-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7981_infracfg_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7981_infracfg_probe,
+	.probe = mt7981_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
-- 
cgit v1.3.1


From 81c047b88296b26b9fdb852061b26dc7dcca72c4 Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:39 +0200
Subject: clk: mediatek: mt7986: deduplicate clock gate drivers

Describe the ethsys gates directly in a struct mtk_clk_tree, reference the
tree from the driver data and use the generic mtk_clk_topckgen_ops instead
of the dedicated clock gate ops.

This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-11-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt7986.c | 32 +++++++++++++++++++-------------
 1 file changed, 19 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index 56e18d403c8..68f92c9625c 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -564,10 +564,12 @@ static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
 	.type = MTK_CLK_TREE_INFRASYS,
 };
 
-static const struct mtk_clk_tree mt7986_clk_tree = {
-	.ext_clk_rates = ext_clock_rates,
-	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
-};
+static int mt7986_clk_probe(struct udevice *dev)
+{
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
+
+	return mtk_common_clk_init(dev, tree);
+}
 
 static const struct udevice_id mt7986_fixed_pll_compat[] = {
 	{ .compatible = "mediatek,mt7986-fixed-plls" },
@@ -658,11 +660,12 @@ static const struct mtk_gate eth_cgs[] = {
 	GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", CLK_TOP_NETSYS_MCU_SEL, 15),
 };
 
-static int mt7986_ethsys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7986_clk_tree, eth_cgs,
-					ARRAY_SIZE(eth_cgs), 0);
-}
+static const struct mtk_clk_tree mt7986_eth_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = eth_cgs,
+	.num_gates = ARRAY_SIZE(eth_cgs),
+};
 
 static int mt7986_ethsys_bind(struct udevice *dev)
 {
@@ -678,7 +681,10 @@ static int mt7986_ethsys_bind(struct udevice *dev)
 }
 
 static const struct udevice_id mt7986_ethsys_compat[] = {
-	{ .compatible = "mediatek,mt7986-ethsys" },
+	{
+		.compatible = "mediatek,mt7986-ethsys",
+		.data = (ulong)&mt7986_eth_clk_tree,
+	},
 	{ }
 };
 
@@ -686,8 +692,8 @@ U_BOOT_DRIVER(mt7986_clk_ethsys) = {
 	.name = "mt7986-clock-ethsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7986_ethsys_compat,
-	.probe = mt7986_ethsys_probe,
+	.probe = mt7986_clk_probe,
 	.bind = mt7986_ethsys_bind,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 };
-- 
cgit v1.3.1


From 237560743b896a6ee5303a47104ba3d139d8f9b8 Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:40 +0200
Subject: clk: mediatek: mt7986: use driver data to store the clock tree

Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for the MT7986 clock drivers, instead of a
dedicated probe per controller.

The fixed-pll, topckgen and infracfg controllers keep their own U_BOOT_DRIVER
since they rely on dedicated ops and on the parent bind() callback, but they
now get their tree from the compatible data. The topckgen probe still
performs its SoC specific register tweaks.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-12-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt7986.c | 37 ++++++++++++++++++++-----------------
 1 file changed, 20 insertions(+), 17 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index 68f92c9625c..5a54f789d0e 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -572,29 +572,34 @@ static int mt7986_clk_probe(struct udevice *dev)
 }
 
 static const struct udevice_id mt7986_fixed_pll_compat[] = {
-	{ .compatible = "mediatek,mt7986-fixed-plls" },
-	{ .compatible = "mediatek,mt7986-apmixedsys" },
+	{
+		.compatible = "mediatek,mt7986-fixed-plls",
+		.data = (ulong)&mt7986_fixed_pll_clk_tree,
+	},
+	{
+		.compatible = "mediatek,mt7986-apmixedsys",
+		.data = (ulong)&mt7986_fixed_pll_clk_tree,
+	},
 	{}
 };
 
 static const struct udevice_id mt7986_topckgen_compat[] = {
-	{ .compatible = "mediatek,mt7986-topckgen" },
+	{
+		.compatible = "mediatek,mt7986-topckgen",
+		.data = (ulong)&mt7986_topckgen_clk_tree,
+	},
 	{}
 };
 
-static int mt7986_fixed_pll_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt7986_fixed_pll_clk_tree);
-}
-
 static int mt7986_topckgen_probe(struct udevice *dev)
 {
 	struct mtk_clk_priv *priv = dev_get_priv(dev);
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 
 	priv->base = dev_read_addr_ptr(dev);
 	writel(MT7986_CLK_PDN_EN_WRITE, priv->base + MT7986_CLK_PDN);
 
-	return mtk_common_clk_init(dev, &mt7986_topckgen_clk_tree);
+	return mtk_common_clk_init(dev, tree);
 }
 
 U_BOOT_DRIVER(mt7986_clk_apmixedsys) = {
@@ -602,7 +607,7 @@ U_BOOT_DRIVER(mt7986_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt7986_fixed_pll_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7986_fixed_pll_probe,
+	.probe = mt7986_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_fixed_pll_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -620,21 +625,19 @@ U_BOOT_DRIVER(mt7986_clk_topckgen) = {
 };
 
 static const struct udevice_id mt7986_infracfg_compat[] = {
-	{ .compatible = "mediatek,mt7986-infracfg" },
+	{
+		.compatible = "mediatek,mt7986-infracfg",
+		.data = (ulong)&mt7986_infracfg_clk_tree,
+	},
 	{}
 };
 
-static int mt7986_infracfg_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt7986_infracfg_clk_tree);
-}
-
 U_BOOT_DRIVER(mt7986_clk_infracfg) = {
 	.name = "mt7986-clock-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7986_infracfg_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7986_infracfg_probe,
+	.probe = mt7986_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
-- 
cgit v1.3.1


From 6644d823acea9752f7a64963a14f94de9429e803 Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:41 +0200
Subject: clk: mediatek: mt7987: deduplicate clock gate drivers

Describe the ethsys gates directly in a struct mtk_clk_tree, reference the
tree from the driver data and use the generic mtk_clk_topckgen_ops instead
of the dedicated clock gate ops.

This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-13-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt7987.c | 30 +++++++++++++++++-------------
 1 file changed, 17 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c
index 4ac0c6faa94..55e57a90775 100644
--- a/drivers/clk/mediatek/clk-mt7987.c
+++ b/drivers/clk/mediatek/clk-mt7987.c
@@ -53,6 +53,13 @@ static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
 	FIXED_CLK0(CLK_APMIXED_MSDCPLL, 384000000),
 };
 
+static int mt7987_clk_probe(struct udevice *dev)
+{
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
+
+	return mtk_common_clk_init(dev, tree);
+}
+
 static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
@@ -462,11 +469,6 @@ static const struct mtk_clk_tree mt7987_topckgen_clk_tree = {
 	.type = MTK_CLK_TREE_TOPCKGEN,
 };
 
-static const struct mtk_clk_tree mt7987_clk_tree = {
-	.ext_clk_rates = ext_clock_rates,
-	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
-};
-
 static const struct udevice_id mt7987_topckgen_compat[] = {
 	{ .compatible = "mediatek,mt7987-topckgen" },
 	{}
@@ -838,11 +840,12 @@ static const struct mtk_gate eth_cgs[] = {
 	GATE_ETH_TOP(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", CLK_TOP_NETSYS_500M_SEL, 10),
 };
 
-static int mt7987_ethsys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7987_clk_tree, eth_cgs,
-					ARRAY_SIZE(eth_cgs), 0);
-}
+static const struct mtk_clk_tree mt7987_eth_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = eth_cgs,
+	.num_gates = ARRAY_SIZE(eth_cgs),
+};
 
 static int mt7987_ethsys_bind(struct udevice *dev)
 {
@@ -860,6 +863,7 @@ static int mt7987_ethsys_bind(struct udevice *dev)
 static const struct udevice_id mt7987_ethsys_compat[] = {
 	{
 		.compatible = "mediatek,mt7987-ethsys",
+		.data = (ulong)&mt7987_eth_clk_tree,
 	},
 	{}
 };
@@ -868,8 +872,8 @@ U_BOOT_DRIVER(mt7987_clk_ethsys) = {
 	.name = "mt7987-clock-ethsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7987_ethsys_compat,
-	.probe = mt7987_ethsys_probe,
+	.probe = mt7987_clk_probe,
 	.bind = mt7987_ethsys_bind,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 };
-- 
cgit v1.3.1


From 7cac2672755b230f9bf1dfcac4f20033a7fd5a9d Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:42 +0200
Subject: clk: mediatek: mt7987: use driver data to store the clock tree

Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for the MT7987 clock drivers, instead of a
dedicated probe per controller.

The fixed-pll, topckgen and infracfg controllers keep their own U_BOOT_DRIVER
since they rely on dedicated ops and on the parent bind() callback, but they
now get their tree from the compatible data. The topckgen probe still
performs its SoC specific register tweaks.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-14-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt7987.c | 42 ++++++++++++++++++++++-----------------
 1 file changed, 24 insertions(+), 18 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c
index 55e57a90775..25faad9edc6 100644
--- a/drivers/clk/mediatek/clk-mt7987.c
+++ b/drivers/clk/mediatek/clk-mt7987.c
@@ -71,22 +71,23 @@ static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = {
 };
 
 static const struct udevice_id mt7987_fixed_pll_compat[] = {
-	{ .compatible = "mediatek,mt7987-fixed-plls" },
-	{ .compatible = "mediatek,mt7987-apmixedsys" },
+	{
+		.compatible = "mediatek,mt7987-fixed-plls",
+		.data = (ulong)&mt7987_fixed_pll_clk_tree,
+	},
+	{
+		.compatible = "mediatek,mt7987-apmixedsys",
+		.data = (ulong)&mt7987_fixed_pll_clk_tree,
+	},
 	{}
 };
 
-static int mt7987_fixed_pll_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt7987_fixed_pll_clk_tree);
-}
-
 U_BOOT_DRIVER(mt7987_clk_apmixedsys) = {
 	.name = "mt7987-clock-fixed-pll",
 	.id = UCLASS_CLK,
 	.of_match = mt7987_fixed_pll_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7987_fixed_pll_probe,
+	.probe = mt7987_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_fixed_pll_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -470,20 +471,24 @@ static const struct mtk_clk_tree mt7987_topckgen_clk_tree = {
 };
 
 static const struct udevice_id mt7987_topckgen_compat[] = {
-	{ .compatible = "mediatek,mt7987-topckgen" },
+	{
+		.compatible = "mediatek,mt7987-topckgen",
+		.data = (ulong)&mt7987_topckgen_clk_tree,
+	},
 	{}
 };
 
 static int mt7987_topckgen_probe(struct udevice *dev)
 {
 	struct mtk_clk_priv *priv = dev_get_priv(dev);
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 
 	priv->base = dev_read_addr_ptr(dev);
 	if (!priv->base)
 		return -ENOENT;
 
 	writel(MT7987_CLK_PDN_EN_WRITE, priv->base + MT7987_CLK_PDN);
-	return mtk_common_clk_init(dev, &mt7987_topckgen_clk_tree);
+	return mtk_common_clk_init(dev, tree);
 }
 
 U_BOOT_DRIVER(mt7987_clk_topckgen) = {
@@ -798,22 +803,23 @@ static const struct mtk_clk_tree mt7987_infracfg_clk_tree = {
 };
 
 static const struct udevice_id mt7987_infracfg_compat[] = {
-	{ .compatible = "mediatek,mt7987-infracfg_ao" },
-	{ .compatible = "mediatek,mt7987-infracfg" },
+	{
+		.compatible = "mediatek,mt7987-infracfg_ao",
+		.data = (ulong)&mt7987_infracfg_clk_tree,
+	},
+	{
+		.compatible = "mediatek,mt7987-infracfg",
+		.data = (ulong)&mt7987_infracfg_clk_tree,
+	},
 	{}
 };
 
-static int mt7987_infracfg_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt7987_infracfg_clk_tree);
-}
-
 U_BOOT_DRIVER(mt7987_clk_infracfg) = {
 	.name = "mt7987-clock-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7987_infracfg_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7987_infracfg_probe,
+	.probe = mt7987_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
-- 
cgit v1.3.1


From 35d09b4becc80d19dffd1eaa8b9c25af147261d5 Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:43 +0200
Subject: clk: mediatek: mt7988: deduplicate clock gate drivers

MT7988 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for each clock gate controller, despite all of them sharing the same
implementation.

Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. The two sgmiisys controllers, which share the same DM
flags and (absent) bind() callback, are merged into a single U_BOOT_DRIVER;
ethdma and ethwarp keep their own drivers since they bind reset controllers
at different offsets.

This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-15-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt7988.c | 104 ++++++++++++++++++--------------------
 1 file changed, 49 insertions(+), 55 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index ebad78a9151..6637ab4c287 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -838,10 +838,12 @@ static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
 	.type = MTK_CLK_TREE_INFRASYS,
 };
 
-static const struct mtk_clk_tree mt7988_clk_tree = {
-	.ext_clk_rates = ext_clock_rates,
-	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
-};
+static int mt7988_clk_probe(struct udevice *dev)
+{
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
+
+	return mtk_common_clk_init(dev, tree);
+}
 
 static const struct udevice_id mt7988_fixed_pll_compat[] = {
 	{ .compatible = "mediatek,mt7988-fixed-plls" },
@@ -933,11 +935,12 @@ static const struct mtk_gate ethdma_mtk_gate[] = {
 	GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", CLK_TOP_NETSYS_2X_SEL, 6),
 };
 
-static int mt7988_ethdma_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7988_clk_tree, ethdma_mtk_gate,
-					ARRAY_SIZE(ethdma_mtk_gate), 0);
-}
+static const struct mtk_clk_tree mt7988_ethdma_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = ethdma_mtk_gate,
+	.num_gates = ARRAY_SIZE(ethdma_mtk_gate),
+};
 
 static int mt7988_ethdma_bind(struct udevice *dev)
 {
@@ -955,6 +958,7 @@ static int mt7988_ethdma_bind(struct udevice *dev)
 static const struct udevice_id mt7988_ethdma_compat[] = {
 	{
 		.compatible = "mediatek,mt7988-ethdma",
+		.data = (ulong)&mt7988_ethdma_clk_tree,
 	},
 	{}
 };
@@ -963,10 +967,10 @@ U_BOOT_DRIVER(mt7988_clk_ethdma) = {
 	.name = "mt7988-clock-ethdma",
 	.id = UCLASS_CLK,
 	.of_match = mt7988_ethdma_compat,
-	.probe = mt7988_ethdma_probe,
+	.probe = mt7988_clk_probe,
 	.bind = mt7988_ethdma_bind,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 };
 
 /* SGMIISYS_0 */
@@ -991,27 +995,11 @@ static const struct mtk_gate sgmiisys_0_mtk_gate[] = {
 	GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", CLK_TOP_XTAL, 3),
 };
 
-static int mt7988_sgmiisys_0_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7988_clk_tree,
-					sgmiisys_0_mtk_gate,
-					ARRAY_SIZE(sgmiisys_0_mtk_gate), 0);
-}
-
-static const struct udevice_id mt7988_sgmiisys_0_compat[] = {
-	{
-		.compatible = "mediatek,mt7988-sgmiisys_0",
-	},
-	{}
-};
-
-U_BOOT_DRIVER(mt7988_clk_sgmiisys_0) = {
-	.name = "mt7988-clock-sgmiisys_0",
-	.id = UCLASS_CLK,
-	.of_match = mt7988_sgmiisys_0_compat,
-	.probe = mt7988_sgmiisys_0_probe,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+static const struct mtk_clk_tree mt7988_sgmiisys_0_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = sgmiisys_0_mtk_gate,
+	.num_gates = ARRAY_SIZE(sgmiisys_0_mtk_gate),
 };
 
 /* SGMIISYS_1 */
@@ -1036,27 +1024,32 @@ static const struct mtk_gate sgmiisys_1_mtk_gate[] = {
 	GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", CLK_TOP_XTAL, 3),
 };
 
-static int mt7988_sgmiisys_1_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7988_clk_tree,
-					sgmiisys_1_mtk_gate,
-					ARRAY_SIZE(sgmiisys_1_mtk_gate), 0);
-}
+static const struct mtk_clk_tree mt7988_sgmiisys_1_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = sgmiisys_1_mtk_gate,
+	.num_gates = ARRAY_SIZE(sgmiisys_1_mtk_gate),
+};
 
-static const struct udevice_id mt7988_sgmiisys_1_compat[] = {
+static const struct udevice_id of_match_mt7988_sgmiisys[] = {
+	{
+		.compatible = "mediatek,mt7988-sgmiisys_0",
+		.data = (ulong)&mt7988_sgmiisys_0_clk_tree,
+	},
 	{
 		.compatible = "mediatek,mt7988-sgmiisys_1",
+		.data = (ulong)&mt7988_sgmiisys_1_clk_tree,
 	},
 	{}
 };
 
-U_BOOT_DRIVER(mt7988_clk_sgmiisys_1) = {
-	.name = "mt7988-clock-sgmiisys_1",
+U_BOOT_DRIVER(mt7988_clk_sgmiisys) = {
+	.name = "mt7988-clock-sgmiisys",
 	.id = UCLASS_CLK,
-	.of_match = mt7988_sgmiisys_1_compat,
-	.probe = mt7988_sgmiisys_1_probe,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.of_match = of_match_mt7988_sgmiisys,
+	.probe = mt7988_clk_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 };
 
 /* ETHWARP */
@@ -1083,12 +1076,12 @@ static const struct mtk_gate ethwarp_mtk_gate[] = {
 		     CLK_TOP_NETSYS_MCU_SEL, 15),
 };
 
-static int mt7988_ethwarp_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7988_clk_tree,
-					ethwarp_mtk_gate,
-					ARRAY_SIZE(ethwarp_mtk_gate), 0);
-}
+static const struct mtk_clk_tree mt7988_ethwarp_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = ethwarp_mtk_gate,
+	.num_gates = ARRAY_SIZE(ethwarp_mtk_gate),
+};
 
 static int mt7988_ethwarp_bind(struct udevice *dev)
 {
@@ -1106,6 +1099,7 @@ static int mt7988_ethwarp_bind(struct udevice *dev)
 static const struct udevice_id mt7988_ethwarp_compat[] = {
 	{
 		.compatible = "mediatek,mt7988-ethwarp",
+		.data = (ulong)&mt7988_ethwarp_clk_tree,
 	},
 	{}
 };
@@ -1114,8 +1108,8 @@ U_BOOT_DRIVER(mt7988_clk_ethwarp) = {
 	.name = "mt7988-clock-ethwarp",
 	.id = UCLASS_CLK,
 	.of_match = mt7988_ethwarp_compat,
-	.probe = mt7988_ethwarp_probe,
+	.probe = mt7988_clk_probe,
 	.bind = mt7988_ethwarp_bind,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 };
-- 
cgit v1.3.1


From 5c65308b55752b4309ff45ce55f5e667e034d23a Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:44 +0200
Subject: clk: mediatek: mt7988: use driver data to store the clock tree

Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for the MT7988 clock drivers, instead of a
dedicated probe per controller.

The fixed-pll, topckgen and infracfg controllers keep their own U_BOOT_DRIVER
since they rely on dedicated ops and on the parent bind() callback, but they
now get their tree from the compatible data. The topckgen probe still
performs its SoC specific register tweaks.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-16-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt7988.c | 37 ++++++++++++++++++++-----------------
 1 file changed, 20 insertions(+), 17 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 6637ab4c287..2208185274a 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -846,31 +846,36 @@ static int mt7988_clk_probe(struct udevice *dev)
 }
 
 static const struct udevice_id mt7988_fixed_pll_compat[] = {
-	{ .compatible = "mediatek,mt7988-fixed-plls" },
-	{ .compatible = "mediatek,mt7988-apmixedsys" },
+	{
+		.compatible = "mediatek,mt7988-fixed-plls",
+		.data = (ulong)&mt7988_fixed_pll_clk_tree,
+	},
+	{
+		.compatible = "mediatek,mt7988-apmixedsys",
+		.data = (ulong)&mt7988_fixed_pll_clk_tree,
+	},
 	{}
 };
 
 static const struct udevice_id mt7988_topckgen_compat[] = {
-	{ .compatible = "mediatek,mt7988-topckgen" },
+	{
+		.compatible = "mediatek,mt7988-topckgen",
+		.data = (ulong)&mt7988_topckgen_clk_tree,
+	},
 	{}
 };
 
-static int mt7988_fixed_pll_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt7988_fixed_pll_clk_tree);
-}
-
 static int mt7988_topckgen_probe(struct udevice *dev)
 {
 	struct mtk_clk_priv *priv = dev_get_priv(dev);
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 
 	priv->base = dev_read_addr_ptr(dev);
 	if (!priv->base)
 		return -ENOENT;
 
 	writel(MT7988_CLK_PDN_EN_WRITE, priv->base + MT7988_CLK_PDN);
-	return mtk_common_clk_init(dev, &mt7988_topckgen_clk_tree);
+	return mtk_common_clk_init(dev, tree);
 }
 
 U_BOOT_DRIVER(mt7988_clk_apmixedsys) = {
@@ -878,7 +883,7 @@ U_BOOT_DRIVER(mt7988_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt7988_fixed_pll_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7988_fixed_pll_probe,
+	.probe = mt7988_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_fixed_pll_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -896,21 +901,19 @@ U_BOOT_DRIVER(mt7988_clk_topckgen) = {
 };
 
 static const struct udevice_id mt7988_infracfg_compat[] = {
-	{ .compatible = "mediatek,mt7988-infracfg" },
+	{
+		.compatible = "mediatek,mt7988-infracfg",
+		.data = (ulong)&mt7988_infracfg_clk_tree,
+	},
 	{}
 };
 
-static int mt7988_infracfg_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt7988_infracfg_clk_tree);
-}
-
 U_BOOT_DRIVER(mt7988_clk_infracfg) = {
 	.name = "mt7988-clock-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7988_infracfg_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7988_infracfg_probe,
+	.probe = mt7988_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
-- 
cgit v1.3.1


From 3e50b3c680a17faac601eec036e82c6e13431285 Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:45 +0200
Subject: clk: mediatek: mt8183: deduplicate clock gate drivers

Describe the infracfg gates directly in a struct mtk_clk_tree, reference the
tree from the driver data and use the generic mtk_clk_topckgen_ops instead
of the dedicated clock gate ops.

This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-17-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt8183.c | 30 ++++++++++++++++++------------
 1 file changed, 18 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index a619dce5ca3..c2c8957c740 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -627,10 +627,12 @@ static const struct mtk_clk_tree mt8183_topckgen_clk_tree = {
 	.type = MTK_CLK_TREE_TOPCKGEN,
 };
 
-static const struct mtk_clk_tree mt8183_clk_tree = {
-	.ext_clk_rates = ext_clock_rates,
-	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
-};
+static int mt8183_clk_probe(struct udevice *dev)
+{
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
+
+	return mtk_common_clk_init(dev, tree);
+}
 
 static const struct mtk_gate_regs infra0_cg_regs = {
 	.set_ofs = 0x80,
@@ -802,11 +804,12 @@ static int mt8183_topckgen_probe(struct udevice *dev)
 	return mtk_common_clk_init(dev, &mt8183_topckgen_clk_tree);
 }
 
-static int mt8183_infracfg_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt8183_clk_tree, infra_clks,
-					ARRAY_SIZE(infra_clks), 0);
-}
+static const struct mtk_clk_tree mt8183_infracfg_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = infra_clks,
+	.num_gates = ARRAY_SIZE(infra_clks),
+};
 
 static const struct udevice_id mt8183_apmixed_compat[] = {
 	{ .compatible = "mediatek,mt8183-apmixedsys", },
@@ -819,7 +822,10 @@ static const struct udevice_id mt8183_topckgen_compat[] = {
 };
 
 static const struct udevice_id mt8183_infracfg_compat[] = {
-	{ .compatible = "mediatek,mt8183-infracfg", },
+	{
+		.compatible = "mediatek,mt8183-infracfg",
+		.data = (ulong)&mt8183_infracfg_tree,
+	},
 	{ }
 };
 
@@ -849,8 +855,8 @@ U_BOOT_DRIVER(mt8183_clk_infracfg) = {
 	.name = "mt8183-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt8183_infracfg_compat,
-	.probe = mt8183_infracfg_probe,
+	.probe = mt8183_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
-	.ops = &mtk_clk_gate_ops,
+	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
-- 
cgit v1.3.1


From 4b040cc0df1be6bc51617649d625a336bd41797d Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:46 +0200
Subject: clk: mediatek: mt8183: use driver data to store the clock tree

Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8183 clock drivers, instead of a
dedicated probe per controller.

The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-18-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt8183.c | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index c2c8957c740..97e2aaddab4 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -794,16 +794,6 @@ static const struct mtk_gate infra_clks[] = {
 	GATE_INFRA3(CLK_INFRA_FBIST2FPC, CLK_TOP_MUX_MSDC50_0, 24),
 };
 
-static int mt8183_apmixedsys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt8183_apmixed_clk_tree);
-}
-
-static int mt8183_topckgen_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt8183_topckgen_clk_tree);
-}
-
 static const struct mtk_clk_tree mt8183_infracfg_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
@@ -812,12 +802,18 @@ static const struct mtk_clk_tree mt8183_infracfg_tree = {
 };
 
 static const struct udevice_id mt8183_apmixed_compat[] = {
-	{ .compatible = "mediatek,mt8183-apmixedsys", },
+	{
+		.compatible = "mediatek,mt8183-apmixedsys",
+		.data = (ulong)&mt8183_apmixed_clk_tree,
+	},
 	{ }
 };
 
 static const struct udevice_id mt8183_topckgen_compat[] = {
-	{ .compatible = "mediatek,mt8183-topckgen", },
+	{
+		.compatible = "mediatek,mt8183-topckgen",
+		.data = (ulong)&mt8183_topckgen_clk_tree,
+	},
 	{ }
 };
 
@@ -834,7 +830,7 @@ U_BOOT_DRIVER(mt8183_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8183_apmixed_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8183_apmixedsys_probe,
+	.probe = mt8183_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -845,7 +841,7 @@ U_BOOT_DRIVER(mt8183_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8183_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8183_topckgen_probe,
+	.probe = mt8183_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
-- 
cgit v1.3.1


From a49f820faec56dadab60d5b2c141e6460831e388 Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:47 +0200
Subject: clk: mediatek: mt8516: deduplicate clock gate drivers

Describe the topckgen clock gates directly in a struct mtk_clk_tree,
reference the tree from the driver data and use the generic
mtk_clk_topckgen_ops instead of the dedicated clock gate ops.

This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-19-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt8516.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c
index 9c510005b42..1ead3d3ffc5 100644
--- a/drivers/clk/mediatek/clk-mt8516.c
+++ b/drivers/clk/mediatek/clk-mt8516.c
@@ -770,6 +770,8 @@ static const struct mtk_clk_tree mt8516_topckgen_clk_tree = {
 static const struct mtk_clk_tree mt8516_clk_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = top_clks,
+	.num_gates = ARRAY_SIZE(top_clks),
 };
 
 static int mt8516_apmixedsys_probe(struct udevice *dev)
@@ -782,10 +784,11 @@ static int mt8516_topckgen_probe(struct udevice *dev)
 	return mtk_common_clk_init(dev, &mt8516_topckgen_clk_tree);
 }
 
-static int mt8516_topckgen_cg_probe(struct udevice *dev)
+static int mt8516_clk_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt8516_clk_tree, top_clks,
-					ARRAY_SIZE(top_clks), 0);
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
+
+	return mtk_common_clk_init(dev, tree);
 }
 
 static const struct udevice_id mt8516_apmixed_compat[] = {
@@ -799,7 +802,10 @@ static const struct udevice_id mt8516_topckgen_compat[] = {
 };
 
 static const struct udevice_id mt8516_topckgen_cg_compat[] = {
-	{ .compatible = "mediatek,mt8516-topckgen-cg", },
+	{
+		.compatible = "mediatek,mt8516-topckgen-cg",
+		.data = (ulong)&mt8516_clk_tree,
+	},
 	{ }
 };
 
@@ -829,8 +835,8 @@ U_BOOT_DRIVER(mt8516_clk_topckgen_cg) = {
 	.name = "mt8516-topckgen-cg",
 	.id = UCLASS_CLK,
 	.of_match = mt8516_topckgen_cg_compat,
-	.probe = mt8516_topckgen_cg_probe,
-	.priv_auto	= sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.probe = mt8516_clk_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
-- 
cgit v1.3.1


From e7ccfc5e0075842aea0896aef882a379f09f529d Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:48 +0200
Subject: clk: mediatek: mt8516: use driver data to store the clock tree

Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8516 clock drivers, instead of a
dedicated probe per controller.

The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-20-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt8516.c | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c
index 1ead3d3ffc5..5f0f5ba4ef4 100644
--- a/drivers/clk/mediatek/clk-mt8516.c
+++ b/drivers/clk/mediatek/clk-mt8516.c
@@ -774,16 +774,6 @@ static const struct mtk_clk_tree mt8516_clk_tree = {
 	.num_gates = ARRAY_SIZE(top_clks),
 };
 
-static int mt8516_apmixedsys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt8516_apmixed_clk_tree);
-}
-
-static int mt8516_topckgen_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt8516_topckgen_clk_tree);
-}
-
 static int mt8516_clk_probe(struct udevice *dev)
 {
 	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
@@ -792,12 +782,18 @@ static int mt8516_clk_probe(struct udevice *dev)
 }
 
 static const struct udevice_id mt8516_apmixed_compat[] = {
-	{ .compatible = "mediatek,mt8516-apmixedsys", },
+	{
+		.compatible = "mediatek,mt8516-apmixedsys",
+		.data = (ulong)&mt8516_apmixed_clk_tree,
+	},
 	{ }
 };
 
 static const struct udevice_id mt8516_topckgen_compat[] = {
-	{ .compatible = "mediatek,mt8516-topckgen", },
+	{
+		.compatible = "mediatek,mt8516-topckgen",
+		.data = (ulong)&mt8516_topckgen_clk_tree,
+	},
 	{ }
 };
 
@@ -814,7 +810,7 @@ U_BOOT_DRIVER(mt8516_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8516_apmixed_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8516_apmixedsys_probe,
+	.probe = mt8516_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -825,7 +821,7 @@ U_BOOT_DRIVER(mt8516_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8516_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8516_topckgen_probe,
+	.probe = mt8516_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
-- 
cgit v1.3.1


From edb0ff28dc3c6e04f11f27104cb1a5cc434d27fb Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:49 +0200
Subject: clk: mediatek: mt8518: deduplicate clock gate drivers

Describe the topckgen clock gates directly in a struct mtk_clk_tree,
reference the tree from the driver data and use the generic
mtk_clk_topckgen_ops instead of the dedicated clock gate ops.

This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-21-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt8518.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c
index 1033ecae187..273ab03df46 100644
--- a/drivers/clk/mediatek/clk-mt8518.c
+++ b/drivers/clk/mediatek/clk-mt8518.c
@@ -1526,6 +1526,8 @@ static const struct mtk_clk_tree mt8518_topckgen_clk_tree = {
 static const struct mtk_clk_tree mt8518_clk_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = top_clks,
+	.num_gates = ARRAY_SIZE(top_clks),
 };
 
 static int mt8518_apmixedsys_probe(struct udevice *dev)
@@ -1538,10 +1540,11 @@ static int mt8518_topckgen_probe(struct udevice *dev)
 	return mtk_common_clk_init(dev, &mt8518_topckgen_clk_tree);
 }
 
-static int mt8518_topckgen_cg_probe(struct udevice *dev)
+static int mt8518_clk_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt8518_clk_tree, top_clks,
-					ARRAY_SIZE(top_clks), 0);
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
+
+	return mtk_common_clk_init(dev, tree);
 }
 
 static const struct udevice_id mt8518_apmixed_compat[] = {
@@ -1555,7 +1558,10 @@ static const struct udevice_id mt8518_topckgen_compat[] = {
 };
 
 static const struct udevice_id mt8518_topckgen_cg_compat[] = {
-	{ .compatible = "mediatek,mt8518-topckgen-cg", },
+	{
+		.compatible = "mediatek,mt8518-topckgen-cg",
+		.data = (ulong)&mt8518_clk_tree,
+	},
 	{ }
 };
 
@@ -1585,8 +1591,8 @@ U_BOOT_DRIVER(mt8518_clk_topckgen_cg) = {
 	.name = "mt8518-topckgen-cg",
 	.id = UCLASS_CLK,
 	.of_match = mt8518_topckgen_cg_compat,
-	.probe = mt8518_topckgen_cg_probe,
-	.priv_auto	= sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.probe = mt8518_clk_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
-- 
cgit v1.3.1


From c58d6877c11a1e179ef4babf6a52510980042ea0 Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:50 +0200
Subject: clk: mediatek: mt8518: use driver data to store the clock tree

Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8518 clock drivers, instead of a
dedicated probe per controller.

The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-22-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt8518.c | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c
index 273ab03df46..95e66b97fbd 100644
--- a/drivers/clk/mediatek/clk-mt8518.c
+++ b/drivers/clk/mediatek/clk-mt8518.c
@@ -1530,16 +1530,6 @@ static const struct mtk_clk_tree mt8518_clk_tree = {
 	.num_gates = ARRAY_SIZE(top_clks),
 };
 
-static int mt8518_apmixedsys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt8518_apmixed_clk_tree);
-}
-
-static int mt8518_topckgen_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt8518_topckgen_clk_tree);
-}
-
 static int mt8518_clk_probe(struct udevice *dev)
 {
 	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
@@ -1548,12 +1538,18 @@ static int mt8518_clk_probe(struct udevice *dev)
 }
 
 static const struct udevice_id mt8518_apmixed_compat[] = {
-	{ .compatible = "mediatek,mt8518-apmixedsys", },
+	{
+		.compatible = "mediatek,mt8518-apmixedsys",
+		.data = (ulong)&mt8518_apmixed_clk_tree,
+	},
 	{ }
 };
 
 static const struct udevice_id mt8518_topckgen_compat[] = {
-	{ .compatible = "mediatek,mt8518-topckgen", },
+	{
+		.compatible = "mediatek,mt8518-topckgen",
+		.data = (ulong)&mt8518_topckgen_clk_tree,
+	},
 	{ }
 };
 
@@ -1570,7 +1566,7 @@ U_BOOT_DRIVER(mt8518_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8518_apmixed_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8518_apmixedsys_probe,
+	.probe = mt8518_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -1581,7 +1577,7 @@ U_BOOT_DRIVER(mt8518_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8518_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8518_topckgen_probe,
+	.probe = mt8518_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
-- 
cgit v1.3.1


From 7fac0d08441f7d6e917f615c1588579b7db40c31 Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:51 +0200
Subject: clk: mediatek: mt8195: deduplicate clock gate drivers

Describe the infracfg_ao gates directly in a struct mtk_clk_tree, reference
the tree from the driver data and use the generic mtk_clk_topckgen_ops
instead of the dedicated clock gate ops.

This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-23-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt8195.c | 21 +++++++++++++--------
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c
index c12463cc616..adbcef96e47 100644
--- a/drivers/clk/mediatek/clk-mt8195.c
+++ b/drivers/clk/mediatek/clk-mt8195.c
@@ -1599,6 +1599,8 @@ static const struct mtk_gate infra_ao_clks[] = {
 static const struct mtk_clk_tree mt8195_infracfg_ao_clk_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = infra_ao_clks,
+	.num_gates = ARRAY_SIZE(infra_ao_clks),
 };
 
 static int mt8195_apmixedsys_probe(struct udevice *dev)
@@ -1611,11 +1613,11 @@ static int mt8195_topckgen_probe(struct udevice *dev)
 	return mtk_common_clk_init(dev, &mt8195_topckgen_clk_tree);
 }
 
-static int mt8195_infra_ao_probe(struct udevice *dev)
+static int mt8195_clk_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt8195_infracfg_ao_clk_tree,
-					infra_ao_clks,
-					ARRAY_SIZE(infra_ao_clks), 0);
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
+
+	return mtk_common_clk_init(dev, tree);
 }
 
 static const struct udevice_id mt8195_apmixed[] = {
@@ -1629,7 +1631,10 @@ static const struct udevice_id mt8195_topckgen_compat[] = {
 };
 
 static const struct udevice_id of_match_clk_mt8195_infra_ao[] = {
-	{ .compatible = "mediatek,mt8195-infracfg_ao", },
+	{
+		.compatible = "mediatek,mt8195-infracfg_ao",
+		.data = (ulong)&mt8195_infracfg_ao_clk_tree,
+	},
 	{ }
 };
 
@@ -1659,8 +1664,8 @@ U_BOOT_DRIVER(mt8195_clk_infra_ao) = {
 	.name = "mt8195-infra_ao",
 	.id = UCLASS_CLK,
 	.of_match = of_match_clk_mt8195_infra_ao,
-	.probe = mt8195_infra_ao_probe,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.probe = mt8195_clk_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
-- 
cgit v1.3.1


From 05d109e09b0ba00bf1e2023a108288b20b724f73 Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:52 +0200
Subject: clk: mediatek: mt8195: use driver data to store the clock tree

Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8195 clock drivers, instead of a
dedicated probe per controller.

The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-24-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt8195.c | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c
index adbcef96e47..809f39fcffc 100644
--- a/drivers/clk/mediatek/clk-mt8195.c
+++ b/drivers/clk/mediatek/clk-mt8195.c
@@ -1603,16 +1603,6 @@ static const struct mtk_clk_tree mt8195_infracfg_ao_clk_tree = {
 	.num_gates = ARRAY_SIZE(infra_ao_clks),
 };
 
-static int mt8195_apmixedsys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt8195_apmixedsys_clk_tree);
-}
-
-static int mt8195_topckgen_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt8195_topckgen_clk_tree);
-}
-
 static int mt8195_clk_probe(struct udevice *dev)
 {
 	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
@@ -1621,12 +1611,18 @@ static int mt8195_clk_probe(struct udevice *dev)
 }
 
 static const struct udevice_id mt8195_apmixed[] = {
-	{ .compatible = "mediatek,mt8195-apmixedsys", },
+	{
+		.compatible = "mediatek,mt8195-apmixedsys",
+		.data = (ulong)&mt8195_apmixedsys_clk_tree,
+	},
 	{ }
 };
 
 static const struct udevice_id mt8195_topckgen_compat[] = {
-	{ .compatible = "mediatek,mt8195-topckgen", },
+	{
+		.compatible = "mediatek,mt8195-topckgen",
+		.data = (ulong)&mt8195_topckgen_clk_tree,
+	},
 	{ }
 };
 
@@ -1643,7 +1639,7 @@ U_BOOT_DRIVER(mt8195_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8195_apmixed,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8195_apmixedsys_probe,
+	.probe = mt8195_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -1654,7 +1650,7 @@ U_BOOT_DRIVER(mt8195_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8195_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8195_topckgen_probe,
+	.probe = mt8195_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
-- 
cgit v1.3.1


From 8ee35039efae8ee9e1f9645d16c0211473920a0f Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:53 +0200
Subject: clk: mediatek: mt8365: deduplicate clock gate drivers

Describe the infracfg gates directly in a struct mtk_clk_tree, reference the
tree from the driver data and use the generic mtk_clk_topckgen_ops instead
of the dedicated clock gate ops.

This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-25-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt8365.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c
index bb00d6154e1..1a0d1149496 100644
--- a/drivers/clk/mediatek/clk-mt8365.c
+++ b/drivers/clk/mediatek/clk-mt8365.c
@@ -757,6 +757,8 @@ static const struct mtk_gate ifr_clks[] = {
 static const struct mtk_clk_tree mt8365_infracfg_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = ifr_clks,
+	.num_gates = ARRAY_SIZE(ifr_clks),
 };
 
 static int mt8365_apmixedsys_probe(struct udevice *dev)
@@ -769,10 +771,11 @@ static int mt8365_topckgen_probe(struct udevice *dev)
 	return mtk_common_clk_init(dev, &mt8365_topckgen_tree);
 }
 
-static int mt8365_infracfg_probe(struct udevice *dev)
+static int mt8365_clk_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt8365_infracfg_tree, ifr_clks,
-					ARRAY_SIZE(ifr_clks), 0);
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
+
+	return mtk_common_clk_init(dev, tree);
 }
 
 static const struct udevice_id mt8365_apmixed_compat[] = {
@@ -786,7 +789,10 @@ static const struct udevice_id mt8365_topckgen_compat[] = {
 };
 
 static const struct udevice_id mt8365_infracfg_compat[] = {
-	{ .compatible = "mediatek,mt8365-infracfg", },
+	{
+		.compatible = "mediatek,mt8365-infracfg",
+		.data = (ulong)&mt8365_infracfg_tree,
+	},
 	{ }
 };
 
@@ -816,8 +822,8 @@ U_BOOT_DRIVER(mt8365_clk_infracfg) = {
 	.name = "mt8365-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt8365_infracfg_compat,
-	.probe = mt8365_infracfg_probe,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.probe = mt8365_clk_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
-- 
cgit v1.3.1


From 7a26bf29e26e2d18829435fbd7c7adf8d560468d Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:54 +0200
Subject: clk: mediatek: mt8365: use driver data to store the clock tree

Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8365 clock drivers, instead of a
dedicated probe per controller.

The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-26-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt8365.c | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c
index 1a0d1149496..ef0d7cc9828 100644
--- a/drivers/clk/mediatek/clk-mt8365.c
+++ b/drivers/clk/mediatek/clk-mt8365.c
@@ -761,16 +761,6 @@ static const struct mtk_clk_tree mt8365_infracfg_tree = {
 	.num_gates = ARRAY_SIZE(ifr_clks),
 };
 
-static int mt8365_apmixedsys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt8365_apmixed_tree);
-}
-
-static int mt8365_topckgen_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt8365_topckgen_tree);
-}
-
 static int mt8365_clk_probe(struct udevice *dev)
 {
 	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
@@ -779,12 +769,18 @@ static int mt8365_clk_probe(struct udevice *dev)
 }
 
 static const struct udevice_id mt8365_apmixed_compat[] = {
-	{ .compatible = "mediatek,mt8365-apmixedsys", },
+	{
+		.compatible = "mediatek,mt8365-apmixedsys",
+		.data = (ulong)&mt8365_apmixed_tree,
+	},
 	{ }
 };
 
 static const struct udevice_id mt8365_topckgen_compat[] = {
-	{ .compatible = "mediatek,mt8365-topckgen", },
+	{
+		.compatible = "mediatek,mt8365-topckgen",
+		.data = (ulong)&mt8365_topckgen_tree,
+	},
 	{ }
 };
 
@@ -801,7 +797,7 @@ U_BOOT_DRIVER(mt8365_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8365_apmixed_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8365_apmixedsys_probe,
+	.probe = mt8365_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -812,7 +808,7 @@ U_BOOT_DRIVER(mt8365_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8365_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8365_topckgen_probe,
+	.probe = mt8365_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
-- 
cgit v1.3.1


From 5899b763bad31a1ad973f186416a428359028991 Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:55 +0200
Subject: clk: mediatek: mt8512: deduplicate clock gate drivers

MT8512 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for the topckgen and infracfg clock gate controllers, despite both
sharing the same implementation.

Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. Both controllers share the same DM flags and (absent)
bind() callback and are merged into a single U_BOOT_DRIVER.

This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-27-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt8512.c | 60 ++++++++++++++++++---------------------
 1 file changed, 28 insertions(+), 32 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c
index 88c55e5ac6c..47a57c4d749 100644
--- a/drivers/clk/mediatek/clk-mt8512.c
+++ b/drivers/clk/mediatek/clk-mt8512.c
@@ -815,9 +815,18 @@ static const struct mtk_clk_tree mt8512_topckgen_clk_tree = {
 	.type = MTK_CLK_TREE_TOPCKGEN,
 };
 
-static const struct mtk_clk_tree mt8512_clk_tree = {
+static const struct mtk_clk_tree mt8512_topckgen_cg_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = top_clks,
+	.num_gates = ARRAY_SIZE(top_clks),
+};
+
+static const struct mtk_clk_tree mt8512_infracfg_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = infra_clks,
+	.num_gates = ARRAY_SIZE(infra_clks),
 };
 
 static int mt8512_apmixedsys_probe(struct udevice *dev)
@@ -830,16 +839,11 @@ static int mt8512_topckgen_probe(struct udevice *dev)
 	return mtk_common_clk_init(dev, &mt8512_topckgen_clk_tree);
 }
 
-static int mt8512_topckgen_cg_probe(struct udevice *dev)
+static int mt8512_clk_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, top_clks,
-					ARRAY_SIZE(top_clks), 0);
-}
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 
-static int mt8512_infracfg_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, infra_clks,
-					ARRAY_SIZE(infra_clks), 0);
+	return mtk_common_clk_init(dev, tree);
 }
 
 static const struct udevice_id mt8512_apmixed_compat[] = {
@@ -852,13 +856,15 @@ static const struct udevice_id mt8512_topckgen_compat[] = {
 	{ }
 };
 
-static const struct udevice_id mt8512_topckgen_cg_compat[] = {
-	{ .compatible = "mediatek,mt8512-topckgen-cg", },
-	{ }
-};
-
-static const struct udevice_id mt8512_infracfg_compat[] = {
-	{ .compatible = "mediatek,mt8512-infracfg", },
+static const struct udevice_id of_match_mt8512_clk_gate[] = {
+	{
+		.compatible = "mediatek,mt8512-topckgen-cg",
+		.data = (ulong)&mt8512_topckgen_cg_tree,
+	},
+	{
+		.compatible = "mediatek,mt8512-infracfg",
+		.data = (ulong)&mt8512_infracfg_tree,
+	},
 	{ }
 };
 
@@ -884,22 +890,12 @@ U_BOOT_DRIVER(mt8512_clk_topckgen) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mt8512_clk_topckgen_cg) = {
-	.name = "mt8512-topckgen-cg",
+U_BOOT_DRIVER(mt8512_clk_gate) = {
+	.name = "mt8512-clk-gate",
 	.id = UCLASS_CLK,
-	.of_match = mt8512_topckgen_cg_compat,
-	.probe = mt8512_topckgen_cg_probe,
-	.priv_auto	= sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
-	.flags = DM_FLAG_PRE_RELOC,
-};
-
-U_BOOT_DRIVER(mt8512_clk_infracfg) = {
-	.name = "mt8512-infracfg",
-	.id = UCLASS_CLK,
-	.of_match = mt8512_infracfg_compat,
-	.probe = mt8512_infracfg_probe,
-	.priv_auto	= sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.of_match = of_match_mt8512_clk_gate,
+	.probe = mt8512_clk_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
-- 
cgit v1.3.1


From 02b947b367881233379ad1d3a608b7bb61a4af51 Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:56 +0200
Subject: clk: mediatek: mt8512: use driver data to store the clock tree

Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8512 clock drivers, instead of a
dedicated probe per controller.

The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-28-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt8512.c | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c
index 47a57c4d749..894bcd0eff6 100644
--- a/drivers/clk/mediatek/clk-mt8512.c
+++ b/drivers/clk/mediatek/clk-mt8512.c
@@ -829,16 +829,6 @@ static const struct mtk_clk_tree mt8512_infracfg_tree = {
 	.num_gates = ARRAY_SIZE(infra_clks),
 };
 
-static int mt8512_apmixedsys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt8512_apmixed_clk_tree);
-}
-
-static int mt8512_topckgen_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt8512_topckgen_clk_tree);
-}
-
 static int mt8512_clk_probe(struct udevice *dev)
 {
 	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
@@ -847,12 +837,18 @@ static int mt8512_clk_probe(struct udevice *dev)
 }
 
 static const struct udevice_id mt8512_apmixed_compat[] = {
-	{ .compatible = "mediatek,mt8512-apmixedsys", },
+	{
+		.compatible = "mediatek,mt8512-apmixedsys",
+		.data = (ulong)&mt8512_apmixed_clk_tree,
+	},
 	{ }
 };
 
 static const struct udevice_id mt8512_topckgen_compat[] = {
-	{ .compatible = "mediatek,mt8512-topckgen", },
+	{
+		.compatible = "mediatek,mt8512-topckgen",
+		.data = (ulong)&mt8512_topckgen_clk_tree,
+	},
 	{ }
 };
 
@@ -873,7 +869,7 @@ U_BOOT_DRIVER(mt8512_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8512_apmixed_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8512_apmixedsys_probe,
+	.probe = mt8512_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -884,7 +880,7 @@ U_BOOT_DRIVER(mt8512_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8512_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8512_topckgen_probe,
+	.probe = mt8512_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
-- 
cgit v1.3.1


From 6d0ba2669994e0a3efa35f444bd93506a9736477 Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:57 +0200
Subject: clk: mediatek: mt8189: deduplicate clock gate drivers

MT8189 already shares a single U_BOOT_DRIVER across all its clock gate
controllers, passing the per-controller gate table through the driver data
via a dedicated struct mt8189_gate_clk_data.

Now that struct mtk_clk_tree can describe the gates directly, drop that
bespoke helper: give each controller its own struct mtk_clk_tree
(.gates/.num_gates/.gates_offs) and use the generic mtk_clk_topckgen_ops.
The gate offset, previously computed at runtime from the first gate ID, is
now encoded statically in each tree.

This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-29-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com> (dropped _gates_offs arg from GATE_CLK_TREE)
---
 drivers/clk/mediatek/clk-mt8189.c | 64 +++++++++++++++++----------------------
 1 file changed, 27 insertions(+), 37 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c
index 3093fac23ce..883b92f57aa 100644
--- a/drivers/clk/mediatek/clk-mt8189.c
+++ b/drivers/clk/mediatek/clk-mt8189.c
@@ -1970,11 +1970,6 @@ static const struct mtk_clk_tree mt8189_vlpckgen_clk_tree = {
 	.type = MTK_CLK_TREE_VLP_CK,
 };
 
-static const struct mtk_clk_tree mt8189_clk_tree = {
-	.ext_clk_rates = ext_clock_rates,
-	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
-};
-
 static const struct udevice_id mt8189_apmixed[] = {
 	{ .compatible = "mediatek,mt8189-apmixedsys", },
 	{ }
@@ -1990,32 +1985,31 @@ static const struct udevice_id mt8189_vlpckgen[] = {
 	{ }
 };
 
-struct mt8189_gate_clk_data {
-	const struct mtk_gate *gates;
-	int num_gates;
-};
-
-#define GATE_CLK_DATA(name) \
-static const struct mt8189_gate_clk_data name##_data = { \
-	.gates = name, .num_gates = ARRAY_SIZE(name) \
+#define GATE_CLK_TREE(_name) \
+static const struct mtk_clk_tree _name##_tree = { \
+	.ext_clk_rates = ext_clock_rates, \
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates), \
+	.gates = _name, \
+	.num_gates = ARRAY_SIZE(_name), \
+	.gates_offs = _name[0].id, \
 }
 
-GATE_CLK_DATA(perao_clks);
-GATE_CLK_DATA(imp_clks);
-GATE_CLK_DATA(mm_clks);
-GATE_CLK_DATA(mminfra_config_clks);
-GATE_CLK_DATA(ufs_config_ao_clks);
-GATE_CLK_DATA(ufs_config_pdn_clks);
-GATE_CLK_DATA(vlpcfg_ao_clks);
+GATE_CLK_TREE(perao_clks);
+GATE_CLK_TREE(imp_clks);
+GATE_CLK_TREE(mm_clks);
+GATE_CLK_TREE(mminfra_config_clks);
+GATE_CLK_TREE(ufs_config_ao_clks);
+GATE_CLK_TREE(ufs_config_pdn_clks);
+GATE_CLK_TREE(vlpcfg_ao_clks);
 
 static const struct udevice_id of_match_mt8189_clk_gate[] = {
-	{ .compatible = "mediatek,mt8189-peri-ao", .data = (ulong)&perao_clks_data },
-	{ .compatible = "mediatek,mt8189-iic-wrap", .data = (ulong)&imp_clks_data },
-	{ .compatible = "mediatek,mt8189-dispsys", .data = (ulong)&mm_clks_data },
-	{ .compatible = "mediatek,mt8189-mm-infra", .data = (ulong)&mminfra_config_clks_data },
-	{ .compatible = "mediatek,mt8189-ufscfg-ao", .data = (ulong)&ufs_config_ao_clks_data },
-	{ .compatible = "mediatek,mt8189-ufscfg-pdn", .data = (ulong)&ufs_config_pdn_clks_data },
-	{ .compatible = "mediatek,mt8189-vlpcfg-ao", .data = (ulong)&vlpcfg_ao_clks_data },
+	{ .compatible = "mediatek,mt8189-peri-ao", .data = (ulong)&perao_clks_tree },
+	{ .compatible = "mediatek,mt8189-iic-wrap", .data = (ulong)&imp_clks_tree },
+	{ .compatible = "mediatek,mt8189-dispsys", .data = (ulong)&mm_clks_tree },
+	{ .compatible = "mediatek,mt8189-mm-infra", .data = (ulong)&mminfra_config_clks_tree },
+	{ .compatible = "mediatek,mt8189-ufscfg-ao", .data = (ulong)&ufs_config_ao_clks_tree },
+	{ .compatible = "mediatek,mt8189-ufscfg-pdn", .data = (ulong)&ufs_config_pdn_clks_tree },
+	{ .compatible = "mediatek,mt8189-vlpcfg-ao", .data = (ulong)&vlpcfg_ao_clks_tree },
 	{ }
 };
 
@@ -2034,15 +2028,11 @@ static int mt8189_infrasys_probe(struct udevice *dev)
 	return mtk_common_clk_init(dev, &mt8189_vlpckgen_clk_tree);
 }
 
-static int mt8189_clk_gate_probe(struct udevice *dev)
+static int mt8189_clk_probe(struct udevice *dev)
 {
-	struct mt8189_gate_clk_data *data;
-
-	data = (void *)dev_get_driver_data(dev);
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 
-	return mtk_common_clk_gate_init(dev, &mt8189_clk_tree,
-					data->gates, data->num_gates,
-					data->gates[0].id);
+	return mtk_common_clk_init(dev, tree);
 }
 
 U_BOOT_DRIVER(mt8189_clk_apmixedsys) = {
@@ -2082,8 +2072,8 @@ U_BOOT_DRIVER(mt8189_clk_gate) = {
 	.name = "mt8189-gate-clk",
 	.id = UCLASS_CLK,
 	.of_match = of_match_mt8189_clk_gate,
-	.probe = mt8189_clk_gate_probe,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.probe = mt8189_clk_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
-- 
cgit v1.3.1


From 0f9a65d7b0a72febff33e31da3a6975dd03faa44 Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:58 +0200
Subject: clk: mediatek: mt8189: use driver data to store the clock tree

Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8189 clock drivers, instead of a
dedicated probe per controller.

The apmixedsys, topckgen and vlpckgen controllers keep their own
U_BOOT_DRIVER since they rely on dedicated ops and on the parent bind()
callback, but they now get their tree from the compatible data, like the
clock gate controllers.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-30-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt8189.c | 36 +++++++++++++++---------------------
 1 file changed, 15 insertions(+), 21 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c
index 883b92f57aa..6aa0235f7fe 100644
--- a/drivers/clk/mediatek/clk-mt8189.c
+++ b/drivers/clk/mediatek/clk-mt8189.c
@@ -1971,17 +1971,26 @@ static const struct mtk_clk_tree mt8189_vlpckgen_clk_tree = {
 };
 
 static const struct udevice_id mt8189_apmixed[] = {
-	{ .compatible = "mediatek,mt8189-apmixedsys", },
+	{
+		.compatible = "mediatek,mt8189-apmixedsys",
+		.data = (ulong)&mt8189_apmixedsys_clk_tree,
+	},
 	{ }
 };
 
 static const struct udevice_id mt8189_topckgen_compat[] = {
-	{ .compatible = "mediatek,mt8189-topckgen", },
+	{
+		.compatible = "mediatek,mt8189-topckgen",
+		.data = (ulong)&mt8189_topckgen_clk_tree,
+	},
 	{ }
 };
 
 static const struct udevice_id mt8189_vlpckgen[] = {
-	{ .compatible = "mediatek,mt8189-vlpckgen", },
+	{
+		.compatible = "mediatek,mt8189-vlpckgen",
+		.data = (ulong)&mt8189_vlpckgen_clk_tree,
+	},
 	{ }
 };
 
@@ -2013,21 +2022,6 @@ static const struct udevice_id of_match_mt8189_clk_gate[] = {
 	{ }
 };
 
-static int mt8189_apmixedsys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt8189_apmixedsys_clk_tree);
-}
-
-static int mt8189_topckgen_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt8189_topckgen_clk_tree);
-}
-
-static int mt8189_infrasys_probe(struct udevice *dev)
-{
-	return mtk_common_clk_init(dev, &mt8189_vlpckgen_clk_tree);
-}
-
 static int mt8189_clk_probe(struct udevice *dev)
 {
 	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
@@ -2040,7 +2034,7 @@ U_BOOT_DRIVER(mt8189_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8189_apmixed,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8189_apmixedsys_probe,
+	.probe = mt8189_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -2051,7 +2045,7 @@ U_BOOT_DRIVER(mt8189_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8189_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8189_topckgen_probe,
+	.probe = mt8189_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -2062,7 +2056,7 @@ U_BOOT_DRIVER(mt8189_clk_vlpckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8189_vlpckgen,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8189_infrasys_probe,
+	.probe = mt8189_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
-- 
cgit v1.3.1


From c399402b0ebede2b68c47ea03d6301f96e4aa8c4 Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:28:59 +0200
Subject: clk: mediatek: remove the dedicated clock gate code path

Now that every MediaTek SoC describes its clock gates through struct
mtk_clk_tree and handles them with the generic topckgen ops, nothing uses
the dedicated clock gate code path anymore.

Remove struct mtk_cg_priv, the mtk_clk_gate_ops (of_xlate/enable/disable/
get_rate/dump) and mtk_common_clk_gate_init() from clk-mtk. Clock gate
controllers are now just regular mtk_clk_tree providers.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-31-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mtk.c | 113 -----------------------------------------
 drivers/clk/mediatek/clk-mtk.h |  13 -----
 2 files changed, 126 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 61d718f162d..a5e983c44ac 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -1039,90 +1039,6 @@ static void mtk_infrasys_dump(struct udevice *dev)
 }
 #endif
 
-/* CG functions */
-
-static const int mtk_clk_gate_of_xlate(struct clk *clk,
-				       struct ofnode_phandle_args *args)
-{
-	struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
-	const struct mtk_clk_tree *tree = priv->tree;
-	int ret;
-
-	ret = mtk_common_clk_of_xlate(clk, args, tree);
-	if (ret)
-		return ret;
-
-	if (clk->id >= priv->gates_offs &&
-	    clk->id < priv->gates_offs + priv->num_gates)
-		return 0;
-
-	return -ENOENT;
-}
-
-static int mtk_clk_gate_enable(struct clk *clk)
-{
-	struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
-	const struct mtk_gate *gate;
-
-	if (clk->id < priv->gates_offs)
-		return -EINVAL;
-
-	gate = &priv->gates[clk->id - priv->gates_offs];
-	return mtk_gate_enable(priv->base, gate);
-}
-
-static int mtk_clk_gate_disable(struct clk *clk)
-{
-	struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
-	const struct mtk_gate *gate;
-
-	if (clk->id < priv->gates_offs)
-		return -EINVAL;
-
-	gate = &priv->gates[clk->id - priv->gates_offs];
-	return mtk_gate_disable(priv->base, gate);
-}
-
-static ulong mtk_clk_gate_get_rate(struct clk *clk)
-{
-	struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
-	const struct mtk_gate *gate;
-	struct udevice *pdev;
-
-	if (clk->id < priv->gates_offs)
-		return -EINVAL;
-
-	gate = &priv->gates[clk->id - priv->gates_offs];
-
-	if (gate->flags & CLK_PARENT_EXT)
-		return mtk_ext_clock_get_rate(priv->tree, gate->parent);
-
-	pdev = mtk_clk_parent_get_provider(gate->flags);
-	if (IS_ERR(pdev))
-		return -ENOENT;
-
-	return mtk_clk_find_parent_rate(clk, gate->parent, pdev);
-}
-
-#if CONFIG_IS_ENABLED(CMD_CLK)
-static void mtk_clk_gate_dump(struct udevice *dev)
-{
-	struct mtk_cg_priv *priv = dev_get_priv(dev);
-	const struct mtk_clk_tree *tree = priv->tree;
-	u32 i;
-
-	for (i = 0; i < priv->num_gates; i++) {
-		const struct mtk_gate *gate = &priv->gates[i];
-
-		printf("[GATE%u] DT: %u", i, gate->id);
-		mtk_clk_print_mapped_id(gate->id, i + priv->gates_offs, tree->id_offs_map);
-		mtk_clk_print_rate(dev, i + priv->gates_offs);
-		mtk_clk_print_single_parent(gate->parent, gate->flags);
-		printf("\n");
-	}
-}
-#endif
-
 const struct clk_ops mtk_clk_apmixedsys_ops = {
 	.of_xlate = mtk_apmixedsys_of_xlate,
 	.enable = mtk_apmixedsys_enable,
@@ -1166,16 +1082,6 @@ const struct clk_ops mtk_clk_infrasys_ops = {
 #endif
 };
 
-const struct clk_ops mtk_clk_gate_ops = {
-	.of_xlate = mtk_clk_gate_of_xlate,
-	.enable = mtk_clk_gate_enable,
-	.disable = mtk_clk_gate_disable,
-	.get_rate = mtk_clk_gate_get_rate,
-#if CONFIG_IS_ENABLED(CMD_CLK)
-	.dump = mtk_clk_gate_dump,
-#endif
-};
-
 int mtk_common_clk_parent_bind(struct udevice *dev)
 {
 	/*
@@ -1199,22 +1105,3 @@ int mtk_common_clk_init(struct udevice *dev, const struct mtk_clk_tree *tree)
 
 	return mtk_clk_tree_register_provider(dev, tree);
 }
-
-int mtk_common_clk_gate_init(struct udevice *dev,
-			     const struct mtk_clk_tree *tree,
-			     const struct mtk_gate *gates, int num_gates,
-			     int gates_offs)
-{
-	struct mtk_cg_priv *priv = dev_get_priv(dev);
-
-	priv->base = dev_read_addr_ptr(dev);
-	if (!priv->base)
-		return -ENOENT;
-
-	priv->tree = tree;
-	priv->gates = gates;
-	priv->num_gates = num_gates;
-	priv->gates_offs = gates_offs;
-
-	return 0;
-}
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 437797dd0df..a6251547ecc 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -284,26 +284,13 @@ struct mtk_clk_priv {
 	const struct mtk_clk_tree *tree;
 };
 
-struct mtk_cg_priv {
-	void __iomem *base;
-	const struct mtk_clk_tree *tree;
-	const struct mtk_gate *gates;
-	int num_gates;
-	int gates_offs;
-};
-
 extern const struct clk_ops mtk_clk_apmixedsys_ops;
 extern const struct clk_ops mtk_clk_fixed_pll_ops;
 extern const struct clk_ops mtk_clk_topckgen_ops;
 extern const struct clk_ops mtk_clk_infrasys_ops;
-extern const struct clk_ops mtk_clk_gate_ops;
 
 int mtk_common_clk_parent_bind(struct udevice *dev);
 int mtk_common_clk_init(struct udevice *dev,
 			const struct mtk_clk_tree *tree);
-int mtk_common_clk_gate_init(struct udevice *dev,
-			     const struct mtk_clk_tree *tree,
-			     const struct mtk_gate *gates, int num_gates,
-			     int gates_offs);
 
 #endif /* __DRV_CLK_MTK_H */
-- 
cgit v1.3.1


From 02ac5662ca6591beda139d8d01d5971a22ae13dc Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 16:29:00 +0200
Subject: clk: mediatek: get the clock tree from the driver data in
 mtk_common_clk_init

Every clock driver now stores its struct mtk_clk_tree in the compatible
data. Rename mtk_common_clk_init() to mtk_clk_probe() and make if fetch
the tree from dev_get_driver_data() instead of taking it as an argument,
so it matches the driver .probe prototype and can be used directly as
the probe callback.

Drop all the per-SoC probe wrappers that only forwarded the driver data
to mtk_clk_probe(), and point the corresponding drivers at
mtk_clk_probe() directly. The few controllers that still need a
dedicated probe for SoC specific register tweaks (some apmixedsys and
topckgen instances) keep it, but now call the single-argument
mtk_clk_probe().

This touches every MediaTek clock driver at once to keep the tree building
across the whole series.

No functional change intended.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-32-23e907516010@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com> (renamed mtk_common_clk_init() to mtk_clk_probe())
---
 drivers/clk/mediatek/clk-mt7622.c | 18 +++++-------------
 drivers/clk/mediatek/clk-mt7623.c | 18 +++++-------------
 drivers/clk/mediatek/clk-mt7629.c | 18 +++++-------------
 drivers/clk/mediatek/clk-mt7981.c | 18 +++++-------------
 drivers/clk/mediatek/clk-mt7986.c | 16 ++++------------
 drivers/clk/mediatek/clk-mt7987.c | 16 ++++------------
 drivers/clk/mediatek/clk-mt7988.c | 20 ++++++--------------
 drivers/clk/mediatek/clk-mt8183.c | 13 +++----------
 drivers/clk/mediatek/clk-mt8188.c | 13 +++----------
 drivers/clk/mediatek/clk-mt8189.c | 15 ++++-----------
 drivers/clk/mediatek/clk-mt8195.c | 13 +++----------
 drivers/clk/mediatek/clk-mt8365.c | 13 +++----------
 drivers/clk/mediatek/clk-mt8512.c | 13 +++----------
 drivers/clk/mediatek/clk-mt8516.c | 13 +++----------
 drivers/clk/mediatek/clk-mt8518.c | 13 +++----------
 drivers/clk/mediatek/clk-mtk.c    |  3 ++-
 drivers/clk/mediatek/clk-mtk.h    |  3 +--
 17 files changed, 62 insertions(+), 174 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index b085689f4d4..a1785b79041 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -699,10 +699,9 @@ static int mt7622_mcucfg_probe(struct udevice *dev)
 static int mt7622_apmixedsys_probe(struct udevice *dev)
 {
 	struct mtk_clk_priv *priv = dev_get_priv(dev);
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 	int ret;
 
-	ret = mtk_common_clk_init(dev, tree);
+	ret = mtk_clk_probe(dev);
 	if (ret)
 		return ret;
 
@@ -716,13 +715,6 @@ static int mt7622_apmixedsys_probe(struct udevice *dev)
 	return 0;
 }
 
-static int mt7622_clk_probe(struct udevice *dev)
-{
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
-
-	return mtk_common_clk_init(dev, tree);
-}
-
 static int mt7622_reset_bind(struct udevice *dev)
 {
 	int ret = 0;
@@ -817,7 +809,7 @@ U_BOOT_DRIVER(mt7622_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt7622_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7622_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -827,7 +819,7 @@ U_BOOT_DRIVER(mt7622_clk_infracfg) = {
 	.name = "mt7622-clock-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = of_match_mt7622_infracfg,
-	.probe = mt7622_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -837,7 +829,7 @@ U_BOOT_DRIVER(mt7622_clk_eth) = {
 	.name = "mt7622-clk-eth",
 	.id = UCLASS_CLK,
 	.of_match = of_match_mt7622_clk_eth,
-	.probe = mt7622_clk_probe,
+	.probe = mtk_clk_probe,
 	.bind = mt7622_reset_bind,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
@@ -847,7 +839,7 @@ U_BOOT_DRIVER(mt7622_clk) = {
 	.name = "mt7622-clk",
 	.id = UCLASS_CLK,
 	.of_match = of_match_mt7622_clk,
-	.probe = mt7622_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 };
diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index 6a6e61af5db..8409120e083 100644
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -1045,10 +1045,9 @@ static int mt7623_mcucfg_probe(struct udevice *dev)
 static int mt7623_apmixedsys_probe(struct udevice *dev)
 {
 	struct mtk_clk_priv *priv = dev_get_priv(dev);
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 	int ret;
 
-	ret = mtk_common_clk_init(dev, tree);
+	ret = mtk_clk_probe(dev);
 	if (ret)
 		return ret;
 
@@ -1084,13 +1083,6 @@ static const struct mtk_clk_tree mt7623_ethsys_tree = {
 	.num_gates = ARRAY_SIZE(eth_cgs),
 };
 
-static int mt7623_clk_probe(struct udevice *dev)
-{
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
-
-	return mtk_common_clk_init(dev, tree);
-}
-
 static const struct mtk_clk_tree mt7623_clk_peri_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
@@ -1190,7 +1182,7 @@ U_BOOT_DRIVER(mt7623_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt7623_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7623_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -1200,7 +1192,7 @@ U_BOOT_DRIVER(mt7623_clk_infracfg) = {
 	.name = "mt7623-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7623_infracfg_compat,
-	.probe = mt7623_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -1210,7 +1202,7 @@ U_BOOT_DRIVER(mt7623_clk_pericfg) = {
 	.name = "mt7623-pericfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7623_pericfg_compat,
-	.probe = mt7623_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -1220,7 +1212,7 @@ U_BOOT_DRIVER(mt7623_clk_eth) = {
 	.name = "mt7623-clk-eth",
 	.id = UCLASS_CLK,
 	.of_match = of_match_mt7623_clk_eth,
-	.probe = mt7623_clk_probe,
+	.probe = mtk_clk_probe,
 	.bind = mt7623_ethsys_hifsys_bind,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
index f7a5f9f75ce..fe97d9226f9 100644
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -654,10 +654,9 @@ static int mt7629_mcucfg_probe(struct udevice *dev)
 static int mt7629_apmixedsys_probe(struct udevice *dev)
 {
 	struct mtk_clk_priv *priv = dev_get_priv(dev);
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 	int ret;
 
-	ret = mtk_common_clk_init(dev, tree);
+	ret = mtk_clk_probe(dev);
 	if (ret)
 		return ret;
 
@@ -669,13 +668,6 @@ static int mt7629_apmixedsys_probe(struct udevice *dev)
 	return 0;
 }
 
-static int mt7629_clk_probe(struct udevice *dev)
-{
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
-
-	return mtk_common_clk_init(dev, tree);
-}
-
 static int mt7629_ethsys_bind(struct udevice *dev)
 {
 	int ret = 0;
@@ -766,7 +758,7 @@ U_BOOT_DRIVER(mt7629_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt7629_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7629_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -776,7 +768,7 @@ U_BOOT_DRIVER(mt7629_clk_infracfg) = {
 	.name = "mt7629-clock-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = of_match_mt7629_infracfg,
-	.probe = mt7629_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -786,7 +778,7 @@ U_BOOT_DRIVER(mt7629_clk_ethsys) = {
 	.name = "mt7629-clock-ethsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7629_ethsys_compat,
-	.probe = mt7629_clk_probe,
+	.probe = mtk_clk_probe,
 	.bind = mt7629_ethsys_bind,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
@@ -796,7 +788,7 @@ U_BOOT_DRIVER(mt7629_clk) = {
 	.name = "mt7629-clk",
 	.id = UCLASS_CLK,
 	.of_match = of_match_mt7629_clk,
-	.probe = mt7629_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 };
diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c
index cd1eed46383..d16fa74a2fa 100644
--- a/drivers/clk/mediatek/clk-mt7981.c
+++ b/drivers/clk/mediatek/clk-mt7981.c
@@ -656,13 +656,6 @@ static const struct mtk_clk_tree mt7981_infracfg_clk_tree = {
 	.type = MTK_CLK_TREE_INFRASYS,
 };
 
-static int mt7981_clk_probe(struct udevice *dev)
-{
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
-
-	return mtk_common_clk_init(dev, tree);
-}
-
 static const struct udevice_id mt7981_fixed_pll_compat[] = {
 	{
 		.compatible = "mediatek,mt7981-fixed-plls",
@@ -686,12 +679,11 @@ static const struct udevice_id mt7981_topckgen_compat[] = {
 static int mt7981_topckgen_probe(struct udevice *dev)
 {
 	struct mtk_clk_priv *priv = dev_get_priv(dev);
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 
 	priv->base = dev_read_addr_ptr(dev);
 	writel(MT7981_CLK_PDN_EN_WRITE, priv->base + MT7981_CLK_PDN);
 
-	return mtk_common_clk_init(dev, tree);
+	return mtk_clk_probe(dev);
 }
 
 U_BOOT_DRIVER(mt7981_clk_apmixedsys) = {
@@ -699,7 +691,7 @@ U_BOOT_DRIVER(mt7981_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt7981_fixed_pll_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7981_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_fixed_pll_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -729,7 +721,7 @@ U_BOOT_DRIVER(mt7981_clk_infracfg) = {
 	.id = UCLASS_CLK,
 	.of_match = mt7981_infracfg_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7981_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -793,7 +785,7 @@ U_BOOT_DRIVER(mt7981_clk_sgmiisys) = {
 	.name = "mt7981-clock-sgmiisys",
 	.id = UCLASS_CLK,
 	.of_match = of_match_mt7981_sgmiisys,
-	.probe = mt7981_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 };
@@ -851,7 +843,7 @@ U_BOOT_DRIVER(mt7981_clk_ethsys) = {
 	.name = "mt7981-clock-ethsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7981_ethsys_compat,
-	.probe = mt7981_clk_probe,
+	.probe = mtk_clk_probe,
 	.bind = mt7981_ethsys_bind,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index 5a54f789d0e..6492bb893b2 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -564,13 +564,6 @@ static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
 	.type = MTK_CLK_TREE_INFRASYS,
 };
 
-static int mt7986_clk_probe(struct udevice *dev)
-{
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
-
-	return mtk_common_clk_init(dev, tree);
-}
-
 static const struct udevice_id mt7986_fixed_pll_compat[] = {
 	{
 		.compatible = "mediatek,mt7986-fixed-plls",
@@ -594,12 +587,11 @@ static const struct udevice_id mt7986_topckgen_compat[] = {
 static int mt7986_topckgen_probe(struct udevice *dev)
 {
 	struct mtk_clk_priv *priv = dev_get_priv(dev);
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 
 	priv->base = dev_read_addr_ptr(dev);
 	writel(MT7986_CLK_PDN_EN_WRITE, priv->base + MT7986_CLK_PDN);
 
-	return mtk_common_clk_init(dev, tree);
+	return mtk_clk_probe(dev);
 }
 
 U_BOOT_DRIVER(mt7986_clk_apmixedsys) = {
@@ -607,7 +599,7 @@ U_BOOT_DRIVER(mt7986_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt7986_fixed_pll_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7986_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_fixed_pll_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -637,7 +629,7 @@ U_BOOT_DRIVER(mt7986_clk_infracfg) = {
 	.id = UCLASS_CLK,
 	.of_match = mt7986_infracfg_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7986_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -695,7 +687,7 @@ U_BOOT_DRIVER(mt7986_clk_ethsys) = {
 	.name = "mt7986-clock-ethsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7986_ethsys_compat,
-	.probe = mt7986_clk_probe,
+	.probe = mtk_clk_probe,
 	.bind = mt7986_ethsys_bind,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c
index 25faad9edc6..cc9052c5943 100644
--- a/drivers/clk/mediatek/clk-mt7987.c
+++ b/drivers/clk/mediatek/clk-mt7987.c
@@ -53,13 +53,6 @@ static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
 	FIXED_CLK0(CLK_APMIXED_MSDCPLL, 384000000),
 };
 
-static int mt7987_clk_probe(struct udevice *dev)
-{
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
-
-	return mtk_common_clk_init(dev, tree);
-}
-
 static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
@@ -87,7 +80,7 @@ U_BOOT_DRIVER(mt7987_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt7987_fixed_pll_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7987_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_fixed_pll_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -481,14 +474,13 @@ static const struct udevice_id mt7987_topckgen_compat[] = {
 static int mt7987_topckgen_probe(struct udevice *dev)
 {
 	struct mtk_clk_priv *priv = dev_get_priv(dev);
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 
 	priv->base = dev_read_addr_ptr(dev);
 	if (!priv->base)
 		return -ENOENT;
 
 	writel(MT7987_CLK_PDN_EN_WRITE, priv->base + MT7987_CLK_PDN);
-	return mtk_common_clk_init(dev, tree);
+	return mtk_clk_probe(dev);
 }
 
 U_BOOT_DRIVER(mt7987_clk_topckgen) = {
@@ -819,7 +811,7 @@ U_BOOT_DRIVER(mt7987_clk_infracfg) = {
 	.id = UCLASS_CLK,
 	.of_match = mt7987_infracfg_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7987_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -878,7 +870,7 @@ U_BOOT_DRIVER(mt7987_clk_ethsys) = {
 	.name = "mt7987-clock-ethsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7987_ethsys_compat,
-	.probe = mt7987_clk_probe,
+	.probe = mtk_clk_probe,
 	.bind = mt7987_ethsys_bind,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 2208185274a..68880bae601 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -838,13 +838,6 @@ static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
 	.type = MTK_CLK_TREE_INFRASYS,
 };
 
-static int mt7988_clk_probe(struct udevice *dev)
-{
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
-
-	return mtk_common_clk_init(dev, tree);
-}
-
 static const struct udevice_id mt7988_fixed_pll_compat[] = {
 	{
 		.compatible = "mediatek,mt7988-fixed-plls",
@@ -868,14 +861,13 @@ static const struct udevice_id mt7988_topckgen_compat[] = {
 static int mt7988_topckgen_probe(struct udevice *dev)
 {
 	struct mtk_clk_priv *priv = dev_get_priv(dev);
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 
 	priv->base = dev_read_addr_ptr(dev);
 	if (!priv->base)
 		return -ENOENT;
 
 	writel(MT7988_CLK_PDN_EN_WRITE, priv->base + MT7988_CLK_PDN);
-	return mtk_common_clk_init(dev, tree);
+	return mtk_clk_probe(dev);
 }
 
 U_BOOT_DRIVER(mt7988_clk_apmixedsys) = {
@@ -883,7 +875,7 @@ U_BOOT_DRIVER(mt7988_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt7988_fixed_pll_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7988_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_fixed_pll_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -913,7 +905,7 @@ U_BOOT_DRIVER(mt7988_clk_infracfg) = {
 	.id = UCLASS_CLK,
 	.of_match = mt7988_infracfg_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt7988_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -970,7 +962,7 @@ U_BOOT_DRIVER(mt7988_clk_ethdma) = {
 	.name = "mt7988-clock-ethdma",
 	.id = UCLASS_CLK,
 	.of_match = mt7988_ethdma_compat,
-	.probe = mt7988_clk_probe,
+	.probe = mtk_clk_probe,
 	.bind = mt7988_ethdma_bind,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
@@ -1050,7 +1042,7 @@ U_BOOT_DRIVER(mt7988_clk_sgmiisys) = {
 	.name = "mt7988-clock-sgmiisys",
 	.id = UCLASS_CLK,
 	.of_match = of_match_mt7988_sgmiisys,
-	.probe = mt7988_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 };
@@ -1111,7 +1103,7 @@ U_BOOT_DRIVER(mt7988_clk_ethwarp) = {
 	.name = "mt7988-clock-ethwarp",
 	.id = UCLASS_CLK,
 	.of_match = mt7988_ethwarp_compat,
-	.probe = mt7988_clk_probe,
+	.probe = mtk_clk_probe,
 	.bind = mt7988_ethwarp_bind,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 97e2aaddab4..f9681f4217f 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -627,13 +627,6 @@ static const struct mtk_clk_tree mt8183_topckgen_clk_tree = {
 	.type = MTK_CLK_TREE_TOPCKGEN,
 };
 
-static int mt8183_clk_probe(struct udevice *dev)
-{
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
-
-	return mtk_common_clk_init(dev, tree);
-}
-
 static const struct mtk_gate_regs infra0_cg_regs = {
 	.set_ofs = 0x80,
 	.clr_ofs = 0x84,
@@ -830,7 +823,7 @@ U_BOOT_DRIVER(mt8183_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8183_apmixed_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8183_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -841,7 +834,7 @@ U_BOOT_DRIVER(mt8183_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8183_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8183_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -851,7 +844,7 @@ U_BOOT_DRIVER(mt8183_clk_infracfg) = {
 	.name = "mt8183-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt8183_infracfg_compat,
-	.probe = mt8183_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c
index 7f0402a87b6..3f2ca3433d7 100644
--- a/drivers/clk/mediatek/clk-mt8188.c
+++ b/drivers/clk/mediatek/clk-mt8188.c
@@ -1722,13 +1722,6 @@ const struct mtk_clk_tree mt8188_imp_iic_wrap_en_clk_tree = {
 	.num_gates = ARRAY_SIZE(imp_iic_wrap_en_clks),
 };
 
-static int mt8188_clk_probe(struct udevice *dev)
-{
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
-
-	return mtk_common_clk_init(dev, tree);
-}
-
 static const struct udevice_id mt8188_apmixed_compat[] = {
 	{
 		.compatible = "mediatek,mt8188-apmixedsys",
@@ -1775,7 +1768,7 @@ U_BOOT_DRIVER(mt8188_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8188_apmixed_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8188_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -1786,7 +1779,7 @@ U_BOOT_DRIVER(mt8188_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8188_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8188_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -1796,7 +1789,7 @@ U_BOOT_DRIVER(mt8188_clk) = {
 	.name = "mt8188-clk",
 	.id = UCLASS_CLK,
 	.of_match = of_match_mt8188_clk,
-	.probe = mt8188_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c
index 6aa0235f7fe..57fa9f4e2c3 100644
--- a/drivers/clk/mediatek/clk-mt8189.c
+++ b/drivers/clk/mediatek/clk-mt8189.c
@@ -2022,19 +2022,12 @@ static const struct udevice_id of_match_mt8189_clk_gate[] = {
 	{ }
 };
 
-static int mt8189_clk_probe(struct udevice *dev)
-{
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
-
-	return mtk_common_clk_init(dev, tree);
-}
-
 U_BOOT_DRIVER(mt8189_clk_apmixedsys) = {
 	.name = "mt8189-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt8189_apmixed,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8189_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -2045,7 +2038,7 @@ U_BOOT_DRIVER(mt8189_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8189_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8189_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -2056,7 +2049,7 @@ U_BOOT_DRIVER(mt8189_clk_vlpckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8189_vlpckgen,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8189_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -2066,7 +2059,7 @@ U_BOOT_DRIVER(mt8189_clk_gate) = {
 	.name = "mt8189-gate-clk",
 	.id = UCLASS_CLK,
 	.of_match = of_match_mt8189_clk_gate,
-	.probe = mt8189_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c
index 809f39fcffc..02f92cb4096 100644
--- a/drivers/clk/mediatek/clk-mt8195.c
+++ b/drivers/clk/mediatek/clk-mt8195.c
@@ -1603,13 +1603,6 @@ static const struct mtk_clk_tree mt8195_infracfg_ao_clk_tree = {
 	.num_gates = ARRAY_SIZE(infra_ao_clks),
 };
 
-static int mt8195_clk_probe(struct udevice *dev)
-{
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
-
-	return mtk_common_clk_init(dev, tree);
-}
-
 static const struct udevice_id mt8195_apmixed[] = {
 	{
 		.compatible = "mediatek,mt8195-apmixedsys",
@@ -1639,7 +1632,7 @@ U_BOOT_DRIVER(mt8195_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8195_apmixed,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8195_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -1650,7 +1643,7 @@ U_BOOT_DRIVER(mt8195_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8195_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8195_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -1660,7 +1653,7 @@ U_BOOT_DRIVER(mt8195_clk_infra_ao) = {
 	.name = "mt8195-infra_ao",
 	.id = UCLASS_CLK,
 	.of_match = of_match_clk_mt8195_infra_ao,
-	.probe = mt8195_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c
index ef0d7cc9828..d861aa0dee3 100644
--- a/drivers/clk/mediatek/clk-mt8365.c
+++ b/drivers/clk/mediatek/clk-mt8365.c
@@ -761,13 +761,6 @@ static const struct mtk_clk_tree mt8365_infracfg_tree = {
 	.num_gates = ARRAY_SIZE(ifr_clks),
 };
 
-static int mt8365_clk_probe(struct udevice *dev)
-{
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
-
-	return mtk_common_clk_init(dev, tree);
-}
-
 static const struct udevice_id mt8365_apmixed_compat[] = {
 	{
 		.compatible = "mediatek,mt8365-apmixedsys",
@@ -797,7 +790,7 @@ U_BOOT_DRIVER(mt8365_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8365_apmixed_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8365_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -808,7 +801,7 @@ U_BOOT_DRIVER(mt8365_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8365_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8365_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -818,7 +811,7 @@ U_BOOT_DRIVER(mt8365_clk_infracfg) = {
 	.name = "mt8365-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt8365_infracfg_compat,
-	.probe = mt8365_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c
index 894bcd0eff6..05948368f7d 100644
--- a/drivers/clk/mediatek/clk-mt8512.c
+++ b/drivers/clk/mediatek/clk-mt8512.c
@@ -829,13 +829,6 @@ static const struct mtk_clk_tree mt8512_infracfg_tree = {
 	.num_gates = ARRAY_SIZE(infra_clks),
 };
 
-static int mt8512_clk_probe(struct udevice *dev)
-{
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
-
-	return mtk_common_clk_init(dev, tree);
-}
-
 static const struct udevice_id mt8512_apmixed_compat[] = {
 	{
 		.compatible = "mediatek,mt8512-apmixedsys",
@@ -869,7 +862,7 @@ U_BOOT_DRIVER(mt8512_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8512_apmixed_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8512_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -880,7 +873,7 @@ U_BOOT_DRIVER(mt8512_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8512_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8512_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -890,7 +883,7 @@ U_BOOT_DRIVER(mt8512_clk_gate) = {
 	.name = "mt8512-clk-gate",
 	.id = UCLASS_CLK,
 	.of_match = of_match_mt8512_clk_gate,
-	.probe = mt8512_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c
index 5f0f5ba4ef4..9c6d91718ae 100644
--- a/drivers/clk/mediatek/clk-mt8516.c
+++ b/drivers/clk/mediatek/clk-mt8516.c
@@ -774,13 +774,6 @@ static const struct mtk_clk_tree mt8516_clk_tree = {
 	.num_gates = ARRAY_SIZE(top_clks),
 };
 
-static int mt8516_clk_probe(struct udevice *dev)
-{
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
-
-	return mtk_common_clk_init(dev, tree);
-}
-
 static const struct udevice_id mt8516_apmixed_compat[] = {
 	{
 		.compatible = "mediatek,mt8516-apmixedsys",
@@ -810,7 +803,7 @@ U_BOOT_DRIVER(mt8516_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8516_apmixed_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8516_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -821,7 +814,7 @@ U_BOOT_DRIVER(mt8516_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8516_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8516_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -831,7 +824,7 @@ U_BOOT_DRIVER(mt8516_clk_topckgen_cg) = {
 	.name = "mt8516-topckgen-cg",
 	.id = UCLASS_CLK,
 	.of_match = mt8516_topckgen_cg_compat,
-	.probe = mt8516_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c
index 95e66b97fbd..89b85fae295 100644
--- a/drivers/clk/mediatek/clk-mt8518.c
+++ b/drivers/clk/mediatek/clk-mt8518.c
@@ -1530,13 +1530,6 @@ static const struct mtk_clk_tree mt8518_clk_tree = {
 	.num_gates = ARRAY_SIZE(top_clks),
 };
 
-static int mt8518_clk_probe(struct udevice *dev)
-{
-	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
-
-	return mtk_common_clk_init(dev, tree);
-}
-
 static const struct udevice_id mt8518_apmixed_compat[] = {
 	{
 		.compatible = "mediatek,mt8518-apmixedsys",
@@ -1566,7 +1559,7 @@ U_BOOT_DRIVER(mt8518_clk_apmixedsys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8518_apmixed_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8518_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -1577,7 +1570,7 @@ U_BOOT_DRIVER(mt8518_clk_topckgen) = {
 	.id = UCLASS_CLK,
 	.of_match = mt8518_topckgen_compat,
 	.bind = mtk_common_clk_parent_bind,
-	.probe = mt8518_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
@@ -1587,7 +1580,7 @@ U_BOOT_DRIVER(mt8518_clk_topckgen_cg) = {
 	.name = "mt8518-topckgen-cg",
 	.id = UCLASS_CLK,
 	.of_match = mt8518_topckgen_cg_compat,
-	.probe = mt8518_clk_probe,
+	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index a5e983c44ac..ec8175552b0 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -1093,9 +1093,10 @@ int mtk_common_clk_parent_bind(struct udevice *dev)
 	return 0;
 }
 
-int mtk_common_clk_init(struct udevice *dev, const struct mtk_clk_tree *tree)
+int mtk_clk_probe(struct udevice *dev)
 {
 	struct mtk_clk_priv *priv = dev_get_priv(dev);
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
 
 	priv->base = dev_read_addr_ptr(dev);
 	if (!priv->base)
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index a6251547ecc..db43cab4659 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -290,7 +290,6 @@ extern const struct clk_ops mtk_clk_topckgen_ops;
 extern const struct clk_ops mtk_clk_infrasys_ops;
 
 int mtk_common_clk_parent_bind(struct udevice *dev);
-int mtk_common_clk_init(struct udevice *dev,
-			const struct mtk_clk_tree *tree);
+int mtk_clk_probe(struct udevice *dev);
 
 #endif /* __DRV_CLK_MTK_H */
-- 
cgit v1.3.1


From 9864f23f45a4b1f837dc873e670b7b00eefc4efc Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Wed, 15 Jul 2026 17:24:26 +0200
Subject: clk: mediatek: mt8188: add display related clock driver

Add display related clock drivers, needed for HDMI support.

Signed-off-by: Chris-QJ Chen <chris-qj.chen@mediatek.com>
Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260715-mt8188-add-clk-add-display-related-clocks-v2-1-0aaf7accaeb0@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt8188.c | 403 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 402 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c
index 3f2ca3433d7..1961dcdd10f 100644
--- a/drivers/clk/mediatek/clk-mt8188.c
+++ b/drivers/clk/mediatek/clk-mt8188.c
@@ -1722,6 +1722,392 @@ const struct mtk_clk_tree mt8188_imp_iic_wrap_en_clk_tree = {
 	.num_gates = ARRAY_SIZE(imp_iic_wrap_en_clks),
 };
 
+static const struct mtk_gate_regs vdo0_0_cg_regs = {
+	.set_ofs = 0x104,
+	.clr_ofs = 0x108,
+	.sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs vdo0_1_cg_regs = {
+	.set_ofs = 0x114,
+	.clr_ofs = 0x118,
+	.sta_ofs = 0x110,
+};
+
+static const struct mtk_gate_regs vdo0_2_cg_regs = {
+	.set_ofs = 0x124,
+	.clr_ofs = 0x128,
+	.sta_ofs = 0x120,
+};
+
+static const struct mtk_gate_regs vpp0_0_cg_regs = {
+	.set_ofs = 0x24,
+	.clr_ofs = 0x28,
+	.sta_ofs = 0x20,
+};
+
+static const struct mtk_gate_regs vpp0_1_cg_regs = {
+	.set_ofs = 0x30,
+	.clr_ofs = 0x34,
+	.sta_ofs = 0x2c,
+};
+
+static const struct mtk_gate_regs vpp0_2_cg_regs = {
+	.set_ofs = 0x3c,
+	.clr_ofs = 0x40,
+	.sta_ofs = 0x38,
+};
+
+#define GATE_VPP0_0(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &vpp0_0_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+#define GATE_VPP0_1(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &vpp0_1_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+#define GATE_VPP0_2(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &vpp0_2_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+static const struct mtk_gate vpp0_clks[] = {
+	/* VPP0_0 */
+	GATE_VPP0_0(CLK_VPP0_MDP_FG, CLK_TOP_VPP, 1),
+	GATE_VPP0_0(CLK_VPP0_STITCH, CLK_TOP_VPP, 2),
+	GATE_VPP0_0(CLK_VPP0_PADDING, CLK_TOP_VPP, 7),
+	GATE_VPP0_0(CLK_VPP0_MDP_TCC, CLK_TOP_VPP, 8),
+	GATE_VPP0_0(CLK_VPP0_WARP0_ASYNC_TX, CLK_TOP_VPP, 10),
+	GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, CLK_TOP_VPP, 11),
+	GATE_VPP0_0(CLK_VPP0_MUTEX, CLK_TOP_VPP, 13),
+	GATE_VPP0_0(CLK_VPP02VPP1_RELAY, CLK_TOP_VPP, 14),
+	GATE_VPP0_0(CLK_VPP0_VPP12VPP0_ASYNC, CLK_TOP_VPP, 15),
+	GATE_VPP0_0(CLK_VPP0_MMSYSRAM_TOP, CLK_TOP_VPP, 16),
+	GATE_VPP0_0(CLK_VPP0_MDP_AAL, CLK_TOP_VPP, 17),
+	GATE_VPP0_0(CLK_VPP0_MDP_RSZ, CLK_TOP_VPP, 18),
+	/* VPP0_1 */
+	GATE_VPP0_1(CLK_VPP0_SMI_COMMON_MMSRAM, CLK_TOP_VPP, 0),
+	GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB0_MMSRAM, CLK_TOP_VPP, 1),
+	GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB1_MMSRAM, CLK_TOP_VPP, 2),
+	GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_MMSRAM, CLK_TOP_VPP, 3),
+	GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM, CLK_TOP_VPP, 4),
+	GATE_VPP0_1(CLK_VPP0_GALS_INFRA_MMSRAM, CLK_TOP_VPP, 5),
+	GATE_VPP0_1(CLK_VPP0_GALS_CAMSYS_MMSRAM, CLK_TOP_VPP, 6),
+	GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB5_MMSRAM, CLK_TOP_VPP, 7),
+	GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB6_MMSRAM, CLK_TOP_VPP, 8),
+	GATE_VPP0_1(CLK_VPP0_SMI_REORDER_MMSRAM, CLK_TOP_VPP, 9),
+	GATE_VPP0_1(CLK_VPP0_SMI_IOMMU, CLK_TOP_VPP, 10),
+	GATE_VPP0_1(CLK_VPP0_GALS_IMGSYS_CAMSYS, CLK_TOP_VPP, 11),
+	GATE_VPP0_1(CLK_VPP0_MDP_RDMA, CLK_TOP_VPP, 12),
+	GATE_VPP0_1(CLK_VPP0_MDP_WROT, CLK_TOP_VPP, 13),
+	GATE_VPP0_1(CLK_VPP0_GALS_EMI0_EMI1, CLK_TOP_VPP, 16),
+	GATE_VPP0_1(CLK_VPP0_SMI_SUB_COMMON_REORDER, CLK_TOP_VPP, 17),
+	GATE_VPP0_1(CLK_VPP0_SMI_RSI, CLK_TOP_VPP, 18),
+	GATE_VPP0_1(CLK_VPP0_SMI_COMMON_LARB4, CLK_TOP_VPP, 19),
+	GATE_VPP0_1(CLK_VPP0_GALS_VDEC_VDEC_CORE1, CLK_TOP_VPP, 20),
+	GATE_VPP0_1(CLK_VPP0_GALS_VPP1_WPESYS, CLK_TOP_VPP, 21),
+	GATE_VPP0_1(CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1, CLK_TOP_VPP, 22),
+	GATE_VPP0_1(CLK_VPP0_FAKE_ENG, CLK_TOP_VPP, 23),
+	GATE_VPP0_1(CLK_VPP0_MDP_HDR, CLK_TOP_VPP, 24),
+	GATE_VPP0_1(CLK_VPP0_MDP_TDSHP, CLK_TOP_VPP, 25),
+	GATE_VPP0_1(CLK_VPP0_MDP_COLOR, CLK_TOP_VPP, 26),
+	GATE_VPP0_1(CLK_VPP0_MDP_OVL, CLK_TOP_VPP, 27),
+	GATE_VPP0_1(CLK_VPP0_DSIP_RDMA, CLK_TOP_VPP, 28),
+	GATE_VPP0_1(CLK_VPP0_DISP_WDMA, CLK_TOP_VPP, 29),
+	GATE_VPP0_1(CLK_VPP0_MDP_HMS, CLK_TOP_VPP, 30),
+	/* VPP0_2 */
+	GATE_VPP0_2(CLK_VPP0_WARP0_RELAY, CLK_TOP_WPE_VPP, 0),
+	GATE_VPP0_2(CLK_VPP0_WARP0_ASYNC, CLK_TOP_WPE_VPP, 1),
+	GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, CLK_TOP_WPE_VPP, 2),
+	GATE_VPP0_2(CLK_VPP0_WARP1_ASYNC, CLK_TOP_WPE_VPP, 3),
+};
+
+static const struct mtk_gate_regs vpp1_0_cg_regs = {
+	.set_ofs = 0x104,
+	.clr_ofs = 0x108,
+	.sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs vpp1_1_cg_regs = {
+	.set_ofs = 0x114,
+	.clr_ofs = 0x118,
+	.sta_ofs = 0x110,
+};
+
+#define GATE_VPP1_0(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &vpp1_0_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+#define GATE_VPP1_1(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &vpp1_1_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+static const struct mtk_gate vpp1_clks[] = {
+	/* VPP1_0 */
+	GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_OVL, CLK_TOP_VPP, 0),
+	GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TCC, CLK_TOP_VPP, 1),
+	GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_WROT, CLK_TOP_VPP, 2),
+	GATE_VPP1_0(CLK_VPP1_SVPP1_VPP_PAD, CLK_TOP_VPP, 3),
+	GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_WROT, CLK_TOP_VPP, 4),
+	GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_PAD, CLK_TOP_VPP, 5),
+	GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_WROT, CLK_TOP_VPP, 6),
+	GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_PAD, CLK_TOP_VPP, 7),
+	GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RDMA, CLK_TOP_VPP, 8),
+	GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_FG, CLK_TOP_VPP, 9),
+	GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RDMA, CLK_TOP_VPP, 10),
+	GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_FG, CLK_TOP_VPP, 11),
+	GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RDMA, CLK_TOP_VPP, 12),
+	GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_FG, CLK_TOP_VPP, 13),
+	GATE_VPP1_0(CLK_VPP1_VPP_SPLIT, CLK_TOP_VPP, 14),
+	GATE_VPP1_0(CLK_VPP1_SVPP2_VDO0_DL_RELAY, CLK_TOP_VPP, 15),
+	GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RSZ, CLK_TOP_VPP, 16),
+	GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TDSHP, CLK_TOP_VPP, 17),
+	GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_COLOR, CLK_TOP_VPP, 18),
+	GATE_VPP1_0(CLK_VPP1_SVPP3_VDO1_DL_RELAY, CLK_TOP_VPP, 19),
+	GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RSZ, CLK_TOP_VPP, 20),
+	GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_MERGE, CLK_TOP_VPP, 21),
+	GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_TDSHP, CLK_TOP_VPP, 22),
+	GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_COLOR, CLK_TOP_VPP, 23),
+	GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RSZ, CLK_TOP_VPP, 24),
+	GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_MERGE, CLK_TOP_VPP, 25),
+	GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_TDSHP, CLK_TOP_VPP, 26),
+	GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_COLOR, CLK_TOP_VPP, 27),
+	GATE_VPP1_0(CLK_VPP1_GALS5, CLK_TOP_VPP, 28),
+	GATE_VPP1_0(CLK_VPP1_GALS6, CLK_TOP_VPP, 29),
+	GATE_VPP1_0(CLK_VPP1_LARB5, CLK_TOP_VPP, 30),
+	GATE_VPP1_0(CLK_VPP1_LARB6, CLK_TOP_VPP, 31),
+	/* VPP1_1 */
+	GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_HDR, CLK_TOP_VPP, 0),
+	GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_AAL, CLK_TOP_VPP, 1),
+	GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_HDR, CLK_TOP_VPP, 2),
+	GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_AAL, CLK_TOP_VPP, 3),
+	GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_HDR, CLK_TOP_VPP, 4),
+	GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_AAL, CLK_TOP_VPP, 5),
+	GATE_VPP1_1(CLK_VPP1_DISP_MUTEX, CLK_TOP_VPP, 7),
+	GATE_VPP1_1(CLK_VPP1_SVPP2_VDO1_DL_RELAY, CLK_TOP_VPP, 8),
+	GATE_VPP1_1(CLK_VPP1_SVPP3_VDO0_DL_RELAY, CLK_TOP_VPP, 9),
+	GATE_VPP1_1(CLK_VPP1_VPP0_DL_ASYNC, CLK_TOP_VPP, 10),
+	GATE_VPP1_1(CLK_VPP1_VPP0_DL1_RELAY, CLK_TOP_VPP, 11),
+	GATE_VPP1_1(CLK_VPP1_LARB5_FAKE_ENG, CLK_TOP_VPP, 12),
+	GATE_VPP1_1(CLK_VPP1_LARB6_FAKE_ENG, CLK_TOP_VPP, 13),
+	GATE_VPP1_1(CLK_VPP1_HDMI_META, CLK_TOP_VPP, 16),
+	GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_HDMI, CLK_TOP_VPP, 17),
+	GATE_VPP1_1(CLK_VPP1_DGI_IN, CLK_TOP_VPP, 18),
+	GATE_VPP1_1(CLK_VPP1_DGI_OUT, CLK_TOP_VPP, 19),
+	GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_DGI, CLK_TOP_VPP, 20),
+	GATE_VPP1_1(CLK_VPP1_DL_CON_OCC, CLK_TOP_VPP, 21),
+	GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, CLK_TOP_VPP, 26),
+};
+
+#define GATE_VDO0_0(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &vdo0_0_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+#define GATE_VDO0_1(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &vdo0_1_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+#define GATE_VDO0_2(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &vdo0_2_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+static const struct mtk_gate vdo0_clks[] = {
+	/* VDO0_0 */
+	GATE_VDO0_0(CLK_VDO0_DISP_OVL0, CLK_TOP_VPP, 0),
+	GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, CLK_TOP_VPP, 2),
+	GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, CLK_TOP_VPP, 4),
+	GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, CLK_TOP_VPP, 6),
+	GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, CLK_TOP_VPP, 8),
+	GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, CLK_TOP_VPP, 10),
+	GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, CLK_TOP_VPP, 17),
+	GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, CLK_TOP_VPP, 19),
+	GATE_VDO0_0(CLK_VDO0_DSI0, CLK_TOP_VPP, 21),
+	GATE_VDO0_0(CLK_VDO0_DSI1, CLK_TOP_VPP, 22),
+	GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, CLK_TOP_VPP, 23),
+	GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, CLK_TOP_VPP, 24),
+	GATE_VDO0_0(CLK_VDO0_DP_INTF0, CLK_TOP_VPP, 25),
+	GATE_VDO0_0(CLK_VDO0_DISP_AAL0, CLK_TOP_VPP, 26),
+	GATE_VDO0_0(CLK_VDO0_INLINEROT0, CLK_TOP_VPP, 27),
+	GATE_VDO0_0(CLK_VDO0_APB_BUS, CLK_TOP_VPP, 28),
+	GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, CLK_TOP_VPP, 29),
+	GATE_VDO0_0(CLK_VDO0_MDP_WROT0, CLK_TOP_VPP, 30),
+	GATE_VDO0_0(CLK_VDO0_DISP_RSZ0, CLK_TOP_VPP, 31),
+	/* VDO0_1 */
+	GATE_VDO0_1(CLK_VDO0_DISP_POSTMASK0, CLK_TOP_VPP, 0),
+	GATE_VDO0_1(CLK_VDO0_FAKE_ENG1, CLK_TOP_VPP, 1),
+	GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, CLK_TOP_VPP, 5),
+	GATE_VDO0_1(CLK_VDO0_DL_RELAY3, CLK_TOP_VPP, 6),
+	GATE_VDO0_1(CLK_VDO0_DL_RELAY4, CLK_TOP_VPP, 7),
+	GATE_VDO0_1(CLK_VDO0_SMI_GALS, CLK_TOP_VPP, 10),
+	GATE_VDO0_1(CLK_VDO0_SMI_COMMON, CLK_TOP_VPP, 11),
+	GATE_VDO0_1(CLK_VDO0_SMI_EMI, CLK_TOP_VPP, 12),
+	GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, CLK_TOP_VPP, 13),
+	GATE_VDO0_1(CLK_VDO0_SMI_LARB, CLK_TOP_VPP, 14),
+	GATE_VDO0_1(CLK_VDO0_SMI_RSI, CLK_TOP_VPP, 15),
+	/* VDO0_2 */
+	GATE_VDO0_2(CLK_VDO0_DSI0_DSI, CLK_TOP_DSI_OCC, 0),
+	GATE_VDO0_2(CLK_VDO0_DSI1_DSI, CLK_TOP_DSI_OCC, 8),
+	GATE_VDO0_2(CLK_VDO0_DP_INTF0_DP_INTF, CLK_TOP_EDP, 16),
+};
+
+static const struct mtk_gate_regs vdo1_0_cg_regs = {
+	.set_ofs = 0x104,
+	.clr_ofs = 0x108,
+	.sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs vdo1_1_cg_regs = {
+	.set_ofs = 0x114,
+	.clr_ofs = 0x118,
+	.sta_ofs = 0x110,
+};
+
+static const struct mtk_gate_regs vdo1_2_cg_regs = {
+	.set_ofs = 0x124,
+	.clr_ofs = 0x128,
+	.sta_ofs = 0x120,
+};
+
+static const struct mtk_gate_regs vdo1_3_cg_regs = {
+	.set_ofs = 0x134,
+	.clr_ofs = 0x138,
+	.sta_ofs = 0x130,
+};
+
+static const struct mtk_gate_regs vdo1_4_cg_regs = {
+	.set_ofs = 0x144,
+	.clr_ofs = 0x148,
+	.sta_ofs = 0x140,
+};
+
+static const struct mtk_gate_regs vdo1_5_cg_regs = {
+	.set_ofs = 0x400,
+	.clr_ofs = 0x400,
+	.sta_ofs = 0x400,
+};
+
+#define GATE_VDO1_0(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &vdo1_0_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+#define GATE_VDO1_1(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &vdo1_1_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+#define GATE_VDO1_2(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &vdo1_2_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+#define GATE_VDO1_3(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &vdo1_3_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+#define GATE_VDO1_4(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &vdo1_4_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+#define GATE_VDO1_5(_id, _parent, _shift) \
+	GATE_FLAGS(_id, _parent, &vdo1_5_cg_regs, _shift, \
+		   CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR)
+
+static const struct mtk_gate vdo1_clks[] = {
+	/* VDO1_0 */
+	GATE_VDO1_0(CLK_VDO1_SMI_LARB2, CLK_TOP_VPP, 0),
+	GATE_VDO1_0(CLK_VDO1_SMI_LARB3, CLK_TOP_VPP, 1),
+	GATE_VDO1_0(CLK_VDO1_GALS, CLK_TOP_VPP, 2),
+	GATE_VDO1_0(CLK_VDO1_FAKE_ENG0, CLK_TOP_VPP, 3),
+	GATE_VDO1_0(CLK_VDO1_FAKE_ENG1, CLK_TOP_VPP, 4),
+	GATE_VDO1_0(CLK_VDO1_MDP_RDMA0, CLK_TOP_VPP, 5),
+	GATE_VDO1_0(CLK_VDO1_MDP_RDMA1, CLK_TOP_VPP, 6),
+	GATE_VDO1_0(CLK_VDO1_MDP_RDMA2, CLK_TOP_VPP, 7),
+	GATE_VDO1_0(CLK_VDO1_MDP_RDMA3, CLK_TOP_VPP, 8),
+	GATE_VDO1_0(CLK_VDO1_VPP_MERGE0, CLK_TOP_VPP, 9),
+	GATE_VDO1_0(CLK_VDO1_VPP_MERGE1, CLK_TOP_VPP, 10),
+	GATE_VDO1_0(CLK_VDO1_VPP_MERGE2, CLK_TOP_VPP, 11),
+	/* VDO1_1 */
+	GATE_VDO1_1(CLK_VDO1_VPP_MERGE3, CLK_TOP_VPP, 0),
+	GATE_VDO1_1(CLK_VDO1_VPP_MERGE4, CLK_TOP_VPP, 1),
+	GATE_VDO1_1(CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC, CLK_TOP_VPP, 2),
+	GATE_VDO1_1(CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC, CLK_TOP_VPP, 3),
+	GATE_VDO1_1(CLK_VDO1_DISP_MUTEX, CLK_TOP_VPP, 4),
+	GATE_VDO1_1(CLK_VDO1_MDP_RDMA4, CLK_TOP_VPP, 5),
+	GATE_VDO1_1(CLK_VDO1_MDP_RDMA5, CLK_TOP_VPP, 6),
+	GATE_VDO1_1(CLK_VDO1_MDP_RDMA6, CLK_TOP_VPP, 7),
+	GATE_VDO1_1(CLK_VDO1_MDP_RDMA7, CLK_TOP_VPP, 8),
+	GATE_VDO1_1(CLK_VDO1_DP_INTF0_MMCK, CLK_TOP_VPP, 9),
+	GATE_VDO1_1(CLK_VDO1_DPI0_MM, CLK_TOP_VPP, 10),
+	GATE_VDO1_1(CLK_VDO1_DPI1_MM, CLK_TOP_VPP, 11),
+	GATE_VDO1_1(CLK_VDO1_MERGE0_DL_ASYNC, CLK_TOP_VPP, 13),
+	GATE_VDO1_1(CLK_VDO1_MERGE1_DL_ASYNC, CLK_TOP_VPP, 14),
+	GATE_VDO1_1(CLK_VDO1_MERGE2_DL_ASYNC, CLK_TOP_VPP, 15),
+	GATE_VDO1_1(CLK_VDO1_MERGE3_DL_ASYNC, CLK_TOP_VPP, 16),
+	GATE_VDO1_1(CLK_VDO1_MERGE4_DL_ASYNC, CLK_TOP_VPP, 17),
+	GATE_VDO1_1(CLK_VDO1_DSC_VDO1_DL_ASYNC, CLK_TOP_VPP, 18),
+	GATE_VDO1_1(CLK_VDO1_MERGE_VDO1_DL_ASYNC, CLK_TOP_VPP, 19),
+	GATE_VDO1_1(CLK_VDO1_PADDING0, CLK_TOP_VPP, 20),
+	GATE_VDO1_1(CLK_VDO1_PADDING1, CLK_TOP_VPP, 21),
+	GATE_VDO1_1(CLK_VDO1_PADDING2, CLK_TOP_VPP, 22),
+	GATE_VDO1_1(CLK_VDO1_PADDING3, CLK_TOP_VPP, 23),
+	GATE_VDO1_1(CLK_VDO1_PADDING4, CLK_TOP_VPP, 24),
+	GATE_VDO1_1(CLK_VDO1_PADDING5, CLK_TOP_VPP, 25),
+	GATE_VDO1_1(CLK_VDO1_PADDING6, CLK_TOP_VPP, 26),
+	GATE_VDO1_1(CLK_VDO1_PADDING7, CLK_TOP_VPP, 27),
+	GATE_VDO1_1(CLK_VDO1_DISP_RSZ0, CLK_TOP_VPP, 28),
+	GATE_VDO1_1(CLK_VDO1_DISP_RSZ1, CLK_TOP_VPP, 29),
+	GATE_VDO1_1(CLK_VDO1_DISP_RSZ2, CLK_TOP_VPP, 30),
+	GATE_VDO1_1(CLK_VDO1_DISP_RSZ3, CLK_TOP_VPP, 31),
+	/* VDO1_2 */
+	GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE0, CLK_TOP_VPP, 0),
+	GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE0, CLK_TOP_VPP, 1),
+	GATE_VDO1_2(CLK_VDO1_HDR_VDO_BE, CLK_TOP_VPP, 2),
+	GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE1, CLK_TOP_VPP, 16),
+	GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE1, CLK_TOP_VPP, 17),
+	GATE_VDO1_2(CLK_VDO1_DISP_MIXER, CLK_TOP_VPP, 18),
+	GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE0_DL_ASYNC, CLK_TOP_VPP, 19),
+	GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE1_DL_ASYNC, CLK_TOP_VPP, 20),
+	GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE0_DL_ASYNC, CLK_TOP_VPP, 21),
+	GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE1_DL_ASYNC, CLK_TOP_VPP, 22),
+	GATE_VDO1_2(CLK_VDO1_HDR_VDO_BE_DL_ASYNC, CLK_TOP_VPP, 23),
+	/* VDO1_3 */
+	GATE_VDO1_3(CLK_VDO1_DPI0, CLK_TOP_VPP, 0),
+	GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPI0, CLK_TOP_VPP, 1),
+	GATE_VDO1_3(CLK_VDO1_DPI1, CLK_TOP_VPP, 8),
+	GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPI1, CLK_TOP_VPP, 9),
+	GATE_VDO1_3(CLK_VDO1_DPINTF, CLK_TOP_VPP, 16),
+	GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPINTF, CLK_TOP_VPP, 17),
+	/* VDO1_4 */
+	GATE_VDO1_4(CLK_VDO1_26M_SLOW, CLK_PAD_CLK26M, 8),
+	/* VDO1_5 */
+	GATE_VDO1_5(CLK_VDO1_DPI1_HDMI, CLK_TOP_VPP, 0),
+};
+
+const struct mtk_clk_tree mt8188_vpp0_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = vpp0_clks,
+	.num_gates = ARRAY_SIZE(vpp0_clks),
+};
+
+const struct mtk_clk_tree mt8188_vpp1_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = vpp1_clks,
+	.num_gates = ARRAY_SIZE(vpp1_clks),
+};
+
+const struct mtk_clk_tree mt8188_vdo0_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = vdo0_clks,
+	.num_gates = ARRAY_SIZE(vdo0_clks),
+};
+
+const struct mtk_clk_tree mt8188_vdo1_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = vdo1_clks,
+	.num_gates = ARRAY_SIZE(vdo1_clks),
+};
+
 static const struct udevice_id mt8188_apmixed_compat[] = {
 	{
 		.compatible = "mediatek,mt8188-apmixedsys",
@@ -1759,10 +2145,25 @@ static const struct udevice_id of_match_mt8188_clk[] = {
 		.compatible = "mediatek,mt8188-imp-iic-wrap-en",
 		.data = (ulong)&mt8188_imp_iic_wrap_en_clk_tree,
 	},
+	{
+		.compatible = "mediatek,mt8188-vppsys0",
+		.data = (ulong)&mt8188_vpp0_clk_tree,
+	},
+	{
+		.compatible = "mediatek,mt8188-vppsys1",
+		.data = (ulong)&mt8188_vpp1_clk_tree,
+	},
+	{
+		.compatible = "mediatek,mt8188-vdosys0",
+		.data = (ulong)&mt8188_vdo0_clk_tree,
+	},
+	{
+		.compatible = "mediatek,mt8188-vdosys1",
+		.data = (ulong)&mt8188_vdo1_clk_tree,
+	},
 	{ }
 };
 
-
 U_BOOT_DRIVER(mt8188_clk_apmixedsys) = {
 	.name = "mt8188-apmixedsys",
 	.id = UCLASS_CLK,
-- 
cgit v1.3.1


From 976b12414c18cb7d601f073dcb2282bac1924197 Mon Sep 17 00:00:00 2001
From: Carlo Caione <ccaione@baylibre.com>
Date: Fri, 24 Jul 2026 10:36:05 +0200
Subject: clk: mediatek: probe parent providers on demand

MediaTek clock trees can reference parents provided by a different clock
controller. The provider registry is populated when each controller
probes, so an early consumer can request a parent before its provider has
been registered.

When lookup misses, find the MediaTek clock device whose operations and
clock-tree type match the requested provider, then probe that device.
This removes the probe-order dependency without probing unrelated clock
controllers or treating a driver's bind callback as a type marker.

Co-developed-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Link: https://patch.msgid.link/20260724-ccaione-upstream-fix-clk-probe-v2-1-ebcef2e94e9d@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mtk.c | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index ec8175552b0..d4cb23aa0fc 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -9,6 +9,7 @@
 #include <clk-uclass.h>
 #include <div64.h>
 #include <dm.h>
+#include <dm/device-internal.h>
 #include <asm/io.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
@@ -60,6 +61,40 @@ static struct udevice *mtk_clk_tree_get_provider(enum mtk_clk_tree_type type)
 	if (!mtk_clk_tree_type_is_provider(type))
 		return NULL;
 
+	if (!mtk_clk_providers[type]) {
+		struct udevice *dev;
+		struct uclass *uc;
+		int ret;
+
+		/* Lazily probe and register the requested provider. */
+		ret = uclass_get(UCLASS_CLK, &uc);
+		if (ret)
+			return ERR_PTR(ret);
+
+		uclass_foreach_dev(dev, uc) {
+			const struct mtk_clk_tree *tree;
+			const void *ops;
+
+			ops = dev_get_driver_ops(dev);
+			if (ops != &mtk_clk_apmixedsys_ops &&
+			    ops != &mtk_clk_fixed_pll_ops &&
+			    ops != &mtk_clk_topckgen_ops &&
+			    ops != &mtk_clk_infrasys_ops)
+				continue;
+
+			tree = (const void *)dev_get_driver_data(dev);
+			if (tree->type != type)
+				continue;
+
+			/* Probe will add it to mtk_clk_providers[type]. */
+			ret = device_probe(dev);
+			if (ret)
+				return ERR_PTR(ret);
+
+			break;
+		}
+	}
+
 	return mtk_clk_providers[type] ?: ERR_PTR(-ENOENT);
 }
 
-- 
cgit v1.3.1


From bf75f80082a194a95eb2aef039a746c5765ba8d1 Mon Sep 17 00:00:00 2001
From: David Lechner <dlechner@baylibre.com>
Date: Fri, 24 Jul 2026 10:36:06 +0200
Subject: clk: mediatek: drop probe-after-bind provider setup

Parent lookup now probes the exact missing provider on demand, making the
eager probing of every parent provider after bind redundant. The common
bind callback also occupies a driver callback that a provider may need
for unrelated setup.

Remove the common bind callback and its use from all MediaTek parent
providers. Providers are now registered only when first needed or when
normal driver-model probing reaches them.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Link: https://patch.msgid.link/20260724-ccaione-upstream-fix-clk-probe-v2-2-ebcef2e94e9d@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt7622.c |  2 --
 drivers/clk/mediatek/clk-mt7623.c |  2 --
 drivers/clk/mediatek/clk-mt7629.c |  2 --
 drivers/clk/mediatek/clk-mt7981.c |  3 ---
 drivers/clk/mediatek/clk-mt7986.c |  3 ---
 drivers/clk/mediatek/clk-mt7987.c |  3 ---
 drivers/clk/mediatek/clk-mt7988.c |  3 ---
 drivers/clk/mediatek/clk-mt8183.c |  2 --
 drivers/clk/mediatek/clk-mt8188.c |  2 --
 drivers/clk/mediatek/clk-mt8189.c |  3 ---
 drivers/clk/mediatek/clk-mt8195.c |  2 --
 drivers/clk/mediatek/clk-mt8365.c |  2 --
 drivers/clk/mediatek/clk-mt8512.c |  2 --
 drivers/clk/mediatek/clk-mt8516.c |  2 --
 drivers/clk/mediatek/clk-mt8518.c |  2 --
 drivers/clk/mediatek/clk-mtk.c    | 11 -----------
 drivers/clk/mediatek/clk-mtk.h    |  8 +-------
 17 files changed, 1 insertion(+), 53 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index a1785b79041..d66200f1938 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -797,7 +797,6 @@ U_BOOT_DRIVER(mt7622_clk_apmixedsys) = {
 	.name = "mt7622-clock-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7622_apmixed_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7622_apmixedsys_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
@@ -808,7 +807,6 @@ U_BOOT_DRIVER(mt7622_clk_topckgen) = {
 	.name = "mt7622-clock-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt7622_topckgen_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index 8409120e083..cc075495b09 100644
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -1170,7 +1170,6 @@ U_BOOT_DRIVER(mt7623_clk_apmixedsys) = {
 	.name = "mt7623-clock-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7623_apmixed_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7623_apmixedsys_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
@@ -1181,7 +1180,6 @@ U_BOOT_DRIVER(mt7623_clk_topckgen) = {
 	.name = "mt7623-clock-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt7623_topckgen_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
index fe97d9226f9..b271b96ebf3 100644
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -746,7 +746,6 @@ U_BOOT_DRIVER(mt7629_clk_apmixedsys) = {
 	.name = "mt7629-clock-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7629_apmixed_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7629_apmixedsys_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
@@ -757,7 +756,6 @@ U_BOOT_DRIVER(mt7629_clk_topckgen) = {
 	.name = "mt7629-clock-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt7629_topckgen_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c
index d16fa74a2fa..7e3e60477d9 100644
--- a/drivers/clk/mediatek/clk-mt7981.c
+++ b/drivers/clk/mediatek/clk-mt7981.c
@@ -690,7 +690,6 @@ U_BOOT_DRIVER(mt7981_clk_apmixedsys) = {
 	.name = "mt7981-clock-fixed-pll",
 	.id = UCLASS_CLK,
 	.of_match = mt7981_fixed_pll_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_fixed_pll_ops,
@@ -701,7 +700,6 @@ U_BOOT_DRIVER(mt7981_clk_topckgen) = {
 	.name = "mt7981-clock-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt7981_topckgen_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7981_topckgen_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
@@ -720,7 +718,6 @@ U_BOOT_DRIVER(mt7981_clk_infracfg) = {
 	.name = "mt7981-clock-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7981_infracfg_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index 6492bb893b2..e4abddbd515 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -598,7 +598,6 @@ U_BOOT_DRIVER(mt7986_clk_apmixedsys) = {
 	.name = "mt7986-clock-fixed-pll",
 	.id = UCLASS_CLK,
 	.of_match = mt7986_fixed_pll_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_fixed_pll_ops,
@@ -609,7 +608,6 @@ U_BOOT_DRIVER(mt7986_clk_topckgen) = {
 	.name = "mt7986-clock-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt7986_topckgen_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7986_topckgen_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
@@ -628,7 +626,6 @@ U_BOOT_DRIVER(mt7986_clk_infracfg) = {
 	.name = "mt7986-clock-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7986_infracfg_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c
index cc9052c5943..6f2fe12a186 100644
--- a/drivers/clk/mediatek/clk-mt7987.c
+++ b/drivers/clk/mediatek/clk-mt7987.c
@@ -79,7 +79,6 @@ U_BOOT_DRIVER(mt7987_clk_apmixedsys) = {
 	.name = "mt7987-clock-fixed-pll",
 	.id = UCLASS_CLK,
 	.of_match = mt7987_fixed_pll_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_fixed_pll_ops,
@@ -487,7 +486,6 @@ U_BOOT_DRIVER(mt7987_clk_topckgen) = {
 	.name = "mt7987-clock-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt7987_topckgen_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7987_topckgen_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
@@ -810,7 +808,6 @@ U_BOOT_DRIVER(mt7987_clk_infracfg) = {
 	.name = "mt7987-clock-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7987_infracfg_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 68880bae601..4728ca3e25a 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -874,7 +874,6 @@ U_BOOT_DRIVER(mt7988_clk_apmixedsys) = {
 	.name = "mt7988-clock-fixed-pll",
 	.id = UCLASS_CLK,
 	.of_match = mt7988_fixed_pll_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_fixed_pll_ops,
@@ -885,7 +884,6 @@ U_BOOT_DRIVER(mt7988_clk_topckgen) = {
 	.name = "mt7988-clock-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt7988_topckgen_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7988_topckgen_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
@@ -904,7 +902,6 @@ U_BOOT_DRIVER(mt7988_clk_infracfg) = {
 	.name = "mt7988-clock-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7988_infracfg_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index f9681f4217f..5a4863049c5 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -822,7 +822,6 @@ U_BOOT_DRIVER(mt8183_clk_apmixedsys) = {
 	.name = "mt8183-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt8183_apmixed_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
@@ -833,7 +832,6 @@ U_BOOT_DRIVER(mt8183_clk_topckgen) = {
 	.name = "mt8183-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt8183_topckgen_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c
index 1961dcdd10f..56a98e9ac4f 100644
--- a/drivers/clk/mediatek/clk-mt8188.c
+++ b/drivers/clk/mediatek/clk-mt8188.c
@@ -2168,7 +2168,6 @@ U_BOOT_DRIVER(mt8188_clk_apmixedsys) = {
 	.name = "mt8188-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt8188_apmixed_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
@@ -2179,7 +2178,6 @@ U_BOOT_DRIVER(mt8188_clk_topckgen) = {
 	.name = "mt8188-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt8188_topckgen_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c
index 57fa9f4e2c3..15e040569e7 100644
--- a/drivers/clk/mediatek/clk-mt8189.c
+++ b/drivers/clk/mediatek/clk-mt8189.c
@@ -2026,7 +2026,6 @@ U_BOOT_DRIVER(mt8189_clk_apmixedsys) = {
 	.name = "mt8189-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt8189_apmixed,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
@@ -2037,7 +2036,6 @@ U_BOOT_DRIVER(mt8189_clk_topckgen) = {
 	.name = "mt8189-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt8189_topckgen_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
@@ -2048,7 +2046,6 @@ U_BOOT_DRIVER(mt8189_clk_vlpckgen) = {
 	.name = "mt8189-vlpckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt8189_vlpckgen,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c
index 02f92cb4096..de40821100e 100644
--- a/drivers/clk/mediatek/clk-mt8195.c
+++ b/drivers/clk/mediatek/clk-mt8195.c
@@ -1631,7 +1631,6 @@ U_BOOT_DRIVER(mt8195_clk_apmixedsys) = {
 	.name = "mt8195-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt8195_apmixed,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
@@ -1642,7 +1641,6 @@ U_BOOT_DRIVER(mt8195_clk_topckgen) = {
 	.name = "mt8195-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt8195_topckgen_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c
index d861aa0dee3..3fa030d7218 100644
--- a/drivers/clk/mediatek/clk-mt8365.c
+++ b/drivers/clk/mediatek/clk-mt8365.c
@@ -789,7 +789,6 @@ U_BOOT_DRIVER(mt8365_clk_apmixedsys) = {
 	.name = "mt8365-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt8365_apmixed_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
@@ -800,7 +799,6 @@ U_BOOT_DRIVER(mt8365_clk_topckgen) = {
 	.name = "mt8365-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt8365_topckgen_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c
index 05948368f7d..a0beae8fa5f 100644
--- a/drivers/clk/mediatek/clk-mt8512.c
+++ b/drivers/clk/mediatek/clk-mt8512.c
@@ -861,7 +861,6 @@ U_BOOT_DRIVER(mt8512_clk_apmixedsys) = {
 	.name = "mt8512-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt8512_apmixed_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
@@ -872,7 +871,6 @@ U_BOOT_DRIVER(mt8512_clk_topckgen) = {
 	.name = "mt8512-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt8512_topckgen_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c
index 9c6d91718ae..ea00b8dbca1 100644
--- a/drivers/clk/mediatek/clk-mt8516.c
+++ b/drivers/clk/mediatek/clk-mt8516.c
@@ -802,7 +802,6 @@ U_BOOT_DRIVER(mt8516_clk_apmixedsys) = {
 	.name = "mt8516-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt8516_apmixed_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
@@ -813,7 +812,6 @@ U_BOOT_DRIVER(mt8516_clk_topckgen) = {
 	.name = "mt8516-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt8516_topckgen_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c
index 89b85fae295..4fef36f458a 100644
--- a/drivers/clk/mediatek/clk-mt8518.c
+++ b/drivers/clk/mediatek/clk-mt8518.c
@@ -1558,7 +1558,6 @@ U_BOOT_DRIVER(mt8518_clk_apmixedsys) = {
 	.name = "mt8518-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt8518_apmixed_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
@@ -1569,7 +1568,6 @@ U_BOOT_DRIVER(mt8518_clk_topckgen) = {
 	.name = "mt8518-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt8518_topckgen_compat,
-	.bind = mtk_common_clk_parent_bind,
 	.probe = mtk_clk_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index d4cb23aa0fc..13c248c93a6 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -1117,17 +1117,6 @@ const struct clk_ops mtk_clk_infrasys_ops = {
 #endif
 };
 
-int mtk_common_clk_parent_bind(struct udevice *dev)
-{
-	/*
-	 * Clock trees that provide parent clocks need to be probed right away
-	 * so that any clock depending on them will work correctly.
-	 */
-	dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
-
-	return 0;
-}
-
 int mtk_clk_probe(struct udevice *dev)
 {
 	struct mtk_clk_priv *priv = dev_get_priv(dev);
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index db43cab4659..9244542a2a5 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -270,12 +270,7 @@ struct mtk_clk_tree {
 	const int num_muxes;
 	const int num_gates;
 	u32 flags;
-	/*
-	 * Set this if this tree provides a specific type for parent lookup.
-	 * Devices that set this should also include mtk_common_clk_parent_bind()
-	 * in the driver bind function to ensure that it will be registered as
-	 * a provider.
-	 */
+	/* Set this if this tree provides a specific type for parent lookup. */
 	enum mtk_clk_tree_type type;
 };
 
@@ -289,7 +284,6 @@ extern const struct clk_ops mtk_clk_fixed_pll_ops;
 extern const struct clk_ops mtk_clk_topckgen_ops;
 extern const struct clk_ops mtk_clk_infrasys_ops;
 
-int mtk_common_clk_parent_bind(struct udevice *dev);
 int mtk_clk_probe(struct udevice *dev);
 
 #endif /* __DRV_CLK_MTK_H */
-- 
cgit v1.3.1


From b889cdc2675563d1c80da8e0234137452f389adf Mon Sep 17 00:00:00 2001
From: David Lechner <dlechner@baylibre.com>
Date: Thu, 11 Jun 2026 16:59:13 -0500
Subject: cmd: ufetch: fix compiling with no CONFIG_SYS_CONFIG_NAME

Add some preprocessor guards to avoid a compile error when
CONFIG_SYS_CONFIG_NAME is not defined.

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260611-fix-ufetch-compile-v1-1-43f2e3239265@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 cmd/ufetch.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/cmd/ufetch.c b/cmd/ufetch.c
index 763ab42c48a..d4b54f77b7b 100644
--- a/cmd/ufetch.c
+++ b/cmd/ufetch.c
@@ -60,7 +60,9 @@ enum output_lines {
 	FIRST,
 	SECOND,
 	KERNEL,
+#ifdef CONFIG_SYS_CONFIG_NAME
 	SYSINFO,
+#endif
 	HOST,
 	UPTIME,
 	IP,
@@ -125,9 +127,11 @@ static int do_ufetch(struct cmd_tbl *cmdtp, int flag, int argc,
 		case KERNEL:
 			printf("Kernel:" RESET " %s\n", U_BOOT_VERSION);
 			break;
+#ifdef CONFIG_SYS_CONFIG_NAME
 		case SYSINFO:
 			printf("Config:" RESET " %s_defconfig\n", CONFIG_SYS_CONFIG_NAME);
 			break;
+#endif
 		case HOST:
 			model = ofnode_read_string(ofnode_root(), "model");
 			if (model)
-- 
cgit v1.3.1


From cdc0564d4f4a38c924c709007dee51a5a9bd6a0d Mon Sep 17 00:00:00 2001
From: Carlo Caione <ccaione@baylibre.com>
Date: Fri, 24 Jul 2026 10:45:09 +0200
Subject: arm: mediatek: use phase-aware PSCI reset on MT8188

MT8188 reset_cpu() checks the U-Boot proper PSCI symbol even when the
function is built for SPL. A standalone SPL download agent runs before
BL31, so fastboot acknowledges a reboot request and then stalls while
attempting an unavailable PSCI system reset.

Use the phase-aware configuration check so SPL falls back to the
watchdog reset provider. U-Boot proper continues to use PSCI as before.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260724-ccaione-upstream-mt8188-spl-reset-v1-1-08da6554ecd8@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 arch/arm/mach-mediatek/mt8188/init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-mediatek/mt8188/init.c b/arch/arm/mach-mediatek/mt8188/init.c
index 1108bc19373..b2cdec8c218 100644
--- a/arch/arm/mach-mediatek/mt8188/init.c
+++ b/arch/arm/mach-mediatek/mt8188/init.c
@@ -33,7 +33,7 @@ void reset_cpu(void)
 {
 	struct udevice *wdt;
 
-	if (IS_ENABLED(CONFIG_PSCI_RESET)) {
+	if (CONFIG_IS_ENABLED(PSCI_RESET)) {
 		psci_system_reset();
 	} else {
 		uclass_first_device(UCLASS_WDT, &wdt);
-- 
cgit v1.3.1


From 6a77840b2f01e98bbad157fd1984a2dce2a3eecd Mon Sep 17 00:00:00 2001
From: Julien Stephan <jstephan@baylibre.com>
Date: Tue, 28 Jul 2026 14:28:23 +0200
Subject: clk: mediatek: mt8188: fix top0 gate polarity

Gates in top0_cg_regs are active-high. The GATE_TOP0/GATE_TOP0E macros
set CLK_GATE_NO_SETCLR flags, which treat them as active-low. Enabling
the clock is currently disabling them.

Switch both macros to CLK_GATE_NO_SETCLR_INV to use the correct
active-high semantics.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Fixes: 11f3cc46322a ("clk: mediatek: add MT8188 clock driver")
Link: https://patch.msgid.link/20260728-mt8188-clk-fix-top0-gate-polarity-v1-1-56bc92ba6055@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>
---
 drivers/clk/mediatek/clk-mt8188.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c
index 56a98e9ac4f..0829ebf4f9a 100644
--- a/drivers/clk/mediatek/clk-mt8188.c
+++ b/drivers/clk/mediatek/clk-mt8188.c
@@ -1363,7 +1363,7 @@ static const struct mtk_gate_regs top1_cg_regs = {
 		.parent = _parent,				   \
 		.regs = &top0_cg_regs,				   \
 		.shift = _shift,				   \
-		.flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
 	}
 
 #define GATE_TOP0E(_id, _parent, _shift) {			   \
@@ -1371,7 +1371,7 @@ static const struct mtk_gate_regs top1_cg_regs = {
 		.parent = _parent,				   \
 		.regs = &top0_cg_regs,				   \
 		.shift = _shift,				   \
-		.flags = CLK_GATE_NO_SETCLR | CLK_PARENT_EXT,	   \
+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_EXT,  \
 	}
 
 #define GATE_TOP1(_id, _parent, _shift) {			       \
-- 
cgit v1.3.1