From f717b9cf3918aa709af4b44b9ef46759abb9d2e5 Mon Sep 17 00:00:00 2001 From: Harini T Date: Mon, 29 Jun 2026 11:46:33 +0200 Subject: arch: arm: dts: Add RTC clock nodes for ZynqMP platform Add fixed RTC clock nodes at 32.768 kHz for ZynqMP. The RTC driver uses this clock to calculate the calibration value, replacing the deprecated calibration device tree property. Signed-off-by: Harini T Reviewed-by: Tomas Melin Signed-off-by: Michal Simek Link: https://patch.msgid.link/8838c8c4fcd0dfe151bcee2a6c4da51df81e23cb.1782726386.git.michal.simek@amd.com --- arch/arm/dts/zynqmp-clk-ccf.dtsi | 15 ++++++++++++++- arch/arm/dts/zynqmp.dtsi | 1 - 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 482f432ba7f..877962df2b3 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -3,7 +3,7 @@ * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ @@ -49,6 +49,14 @@ clock-frequency = <27000000>; clock-output-names = "aux_ref_clk"; }; + + rtc_clk: rtc-clk { + bootph-all; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "rtc_clk"; + }; }; &zynqmp_firmware { @@ -302,3 +310,8 @@ <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ }; + +&rtc { + clocks = <&rtc_clk>; + clock-names = "rtc"; +}; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 13cfca66657..c225eb219f4 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -1006,7 +1006,6 @@ interrupts = , ; interrupt-names = "alarm", "sec"; - calibration = <0x7FFF>; }; sata: ahci@fd0c0000 { -- cgit v1.3.1