From fac2121a47fe5fe6af45af0f5acfa5b8bd369b52 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Tue, 7 Nov 2023 12:41:00 +0000 Subject: clk/qcom: move ipq4019 driver from mach-ipq40xx This driver is just a stub, but it's necessary to support the upcoming reset driver changes. Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- arch/arm/Kconfig | 1 + arch/arm/mach-ipq40xx/Makefile | 1 - arch/arm/mach-ipq40xx/clock-ipq4019.c | 88 ----------------------------------- drivers/clk/qcom/Kconfig | 8 ++++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clock-ipq4019.c | 51 ++++++++++++++++++++ drivers/clk/qcom/clock-qcom.c | 1 + 7 files changed, 62 insertions(+), 89 deletions(-) delete mode 100644 arch/arm/mach-ipq40xx/clock-ipq4019.c create mode 100644 drivers/clk/qcom/clock-ipq4019.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2d4458b7b56..294ab9d0a3f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -776,6 +776,7 @@ config ARCH_IPQ40XX select CLK select SMEM select OF_CONTROL + select CLK_QCOM_IPQ4019 imply CMD_DM config ARCH_KEYSTONE diff --git a/arch/arm/mach-ipq40xx/Makefile b/arch/arm/mach-ipq40xx/Makefile index 08a65b8854d..b36a935c6f9 100644 --- a/arch/arm/mach-ipq40xx/Makefile +++ b/arch/arm/mach-ipq40xx/Makefile @@ -4,6 +4,5 @@ # # Author: Robert Marko -obj-y += clock-ipq4019.o obj-y += pinctrl-snapdragon.o obj-y += pinctrl-ipq4019.o diff --git a/arch/arm/mach-ipq40xx/clock-ipq4019.c b/arch/arm/mach-ipq40xx/clock-ipq4019.c deleted file mode 100644 index c1d5c4ecdd8..00000000000 --- a/arch/arm/mach-ipq40xx/clock-ipq4019.c +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Clock drivers for Qualcomm IPQ40xx - * - * Copyright (c) 2020 Sartura Ltd. - * - * Author: Robert Marko - * - */ - -#include -#include -#include -#include - -#include - -struct msm_clk_priv { - phys_addr_t base; -}; - -ulong msm_set_rate(struct clk *clk, ulong rate) -{ - switch (clk->id) { - case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/ - /* This clock is already initialized by SBL1 */ - return 0; - default: - return -EINVAL; - } -} - -static int msm_clk_probe(struct udevice *dev) -{ - struct msm_clk_priv *priv = dev_get_priv(dev); - - priv->base = dev_read_addr(dev); - if (priv->base == FDT_ADDR_T_NONE) - return -EINVAL; - - return 0; -} - -static ulong msm_clk_set_rate(struct clk *clk, ulong rate) -{ - return msm_set_rate(clk, rate); -} - -static int msm_enable(struct clk *clk) -{ - switch (clk->id) { - case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/ - /* This clock is already initialized by SBL1 */ - return 0; - case GCC_PRNG_AHB_CLK: /*PRNG*/ - /* This clock is already initialized by SBL1 */ - return 0; - case GCC_USB3_MASTER_CLK: - case GCC_USB3_SLEEP_CLK: - case GCC_USB3_MOCK_UTMI_CLK: - case GCC_USB2_MASTER_CLK: - case GCC_USB2_SLEEP_CLK: - case GCC_USB2_MOCK_UTMI_CLK: - /* These clocks is already initialized by SBL1 */ - return 0; - default: - return -EINVAL; - } -} - -static struct clk_ops msm_clk_ops = { - .set_rate = msm_clk_set_rate, - .enable = msm_enable, -}; - -static const struct udevice_id msm_clk_ids[] = { - { .compatible = "qcom,gcc-ipq4019" }, - { } -}; - -U_BOOT_DRIVER(clk_msm) = { - .name = "clk_msm", - .id = UCLASS_CLK, - .of_match = msm_clk_ids, - .ops = &msm_clk_ops, - .priv_auto = sizeof(struct msm_clk_priv), - .probe = msm_clk_probe, -}; diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index a884f077d9b..0df0d1881a4 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -23,6 +23,14 @@ config CLK_QCOM_APQ8096 on the Snapdragon APQ8096 SoC. This driver supports the clocks and resets exposed by the GCC hardware block. +config CLK_QCOM_IPQ4019 + bool "Qualcomm IPQ4019 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon IPQ4019 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + config CLK_QCOM_QCS404 bool "Qualcomm QCS404 GCC" select CLK_QCOM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 44d55583596..cb179fdac58 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -6,4 +6,5 @@ obj-y += clock-qcom.o obj-$(CONFIG_CLK_QCOM_SDM845) += clock-sdm845.o obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o +obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c new file mode 100644 index 00000000000..04c99964df1 --- /dev/null +++ b/drivers/clk/qcom/clock-ipq4019.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Clock drivers for Qualcomm IPQ40xx + * + * Copyright (c) 2020 Sartura Ltd. + * + * Author: Robert Marko + * + */ + +#include +#include +#include +#include +#include + +#include "clock-qcom.h" + +ulong msm_set_rate(struct clk *clk, ulong rate) +{ + switch (clk->id) { + case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/ + /* This clock is already initialized by SBL1 */ + return 0; + default: + return -EINVAL; + } +} + +int msm_enable(struct clk *clk) +{ + switch (clk->id) { + case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/ + /* This clock is already initialized by SBL1 */ + return 0; + case GCC_PRNG_AHB_CLK: /*PRNG*/ + /* This clock is already initialized by SBL1 */ + return 0; + case GCC_USB3_MASTER_CLK: + case GCC_USB3_SLEEP_CLK: + case GCC_USB3_MOCK_UTMI_CLK: + case GCC_USB2_MASTER_CLK: + case GCC_USB2_SLEEP_CLK: + case GCC_USB2_MOCK_UTMI_CLK: + /* These clocks is already initialized by SBL1 */ + return 0; + default: + return -EINVAL; + } +} + diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 5667abeb89a..5914616fba5 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -166,6 +166,7 @@ static const struct udevice_id msm_clk_ids[] = { { .compatible = "qcom,gcc-apq8016" }, { .compatible = "qcom,gcc-msm8996" }, { .compatible = "qcom,gcc-apq8096" }, + { .compatible = "qcom,gcc-ipq4019" }, { .compatible = "qcom,gcc-sdm845" }, { .compatible = "qcom,gcc-qcs404" }, { } -- cgit v1.3.1