From f0baa0a6685db0b59d8e9860c6cfcb942f74697f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 19 Nov 2025 00:17:14 +0100 Subject: stm32mp: Fix handling of OPTEE in the middle of DRAM STM32MP13xx may have OPTEE-OS at 0xdd000000 even on systems with 1 GiB of DRAM at 0xc0000000, which is not the end of DRAM anymore. This puts the OPTEE-OS in the middle of DRAM. Currently, the code sets RAM top to 0xdd000000 and prevents the DRAM range past OPTEE at 0xe0000000..0xffffffff from being set as cacheable and from being usable. The code also sets the area over OPTEE as invalid region in MMU tables, which is not correct. Adjust the code such, that it only ever sets RAM top just before OPTEE in case the OPTEE is really at the end of DRAM, mainly to be backward compatible. Furthermore, adjust the MMU table configuration such, that the regions over the OPTEE are simply skipped and not reconfigured, and the regions between end of OPTEE and RAM top are set as cacheable, if any actually exist. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard Tested-by: Patrice Chotard --- arch/arm/mach-stm32mp/dram_init.c | 4 +++- arch/arm/mach-stm32mp/stm32mp1/cpu.c | 11 ++++++----- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 34b958d7afd..e36e42e7c61 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -65,6 +65,7 @@ int dram_init(void) phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { + phys_addr_t top = gd->ram_top; phys_size_t size; phys_addr_t reg; u32 optee_start, optee_size; @@ -86,7 +87,8 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) /* Reserved memory for OP-TEE at END of DDR for STM32MP1 SoC */ if (IS_ENABLED(CONFIG_STM32MP13X) || IS_ENABLED(CONFIG_STM32MP15X)) { if (!optee_get_reserved_memory(&optee_start, &optee_size)) - reg = ALIGN(optee_start - size, MMU_SECTION_SIZE); + if (optee_start + optee_size == top) + reg = ALIGN(optee_start - size, MMU_SECTION_SIZE); } /* before relocation, mark the U-Boot memory as cacheable by default */ diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index e0c6f8ba937..252aef1852e 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -82,11 +82,12 @@ void dram_bank_mmu_setup(int bank) i++) { addr = i << MMU_SECTION_SHIFT; option = DCACHE_DEFAULT_OPTION; - if (use_lmb && - (lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP) || - (gd->ram_top && addr >= gd->ram_top)) - ) - option = 0; /* INVALID ENTRY in TLB */ + if (use_lmb) { + if (lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP)) + continue; + if (gd->ram_top && addr >= gd->ram_top) + option = 0; /* INVALID ENTRY in TLB */ + } set_section_dcache(i, option); } } -- cgit v1.3.1 From fd26267b4c2b882363e639c7a1eed97068aaff01 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 19 Nov 2025 00:19:17 +0100 Subject: ARM: dts: stm32: Fix 512 MiB DRAM settings for DH STM32MP13xx DHCOR SoM Update DRAM chip type and density comment for 512 MiB DRAM settings for DH STM32MP13xx DHCOR DHSBC to match the chip on the SoM. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi index 7b344541c3e..b464c04aa2b 100644 --- a/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi @@ -3,13 +3,13 @@ * Copyright (C) 2025, DH electronics - All Rights Reserved * * STM32MP13xx DHSOM configuration - * 1x DDR3L 1Gb, 16-bit, 533MHz, Single Die Package in flyby topology. - * Reference used W631GU6MB15I from Winbond + * 1x DDR3L 4Gb, 16-bit, 533MHz, Single Die Package in flyby topology. + * Reference used W634GU6RB11I from Winbond * * DDR type / Platform DDR3/3L * freq 533MHz * width 16 - * datasheet 0 = W631GU6MB15I / DDR3-1333 + * datasheet 0 = W634GU6RB11I / DDR3-1866 * DDR density 2 * timing mode optimized * address mapping : RBC -- cgit v1.3.1 From 86ff2cfa80e9abb71789b299cfcbfc0b9337174d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 19 Nov 2025 00:19:36 +0100 Subject: ARM: dts: stm32: Add 1 GiB DRAM settings for DH STM32MP13xx DHCOR SoM Add DRAM settings for 1 GiB variant of DH STM32MP13xx DHCOR SoM and support for SoM DRAM coding HW straps decoding and automatic DRAM configuration selection. Enable CONFIG_BOARD_EARLY_INIT_F on all STM32MP1 DHSOM, as it is required for the HW straps decoding. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- .../dts/stm32mp13-ddr3-dhsom-1x4Gb-1066-binG.dtsi | 100 +++++++++++++++++++++ arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi | 1 + board/dhelectronics/dh_stm32mp1/board.c | 30 +++++-- configs/stm32mp15_dhsom.config | 1 - configs/stm32mp_dhsom.config | 1 + 5 files changed, 123 insertions(+), 10 deletions(-) create mode 100644 arch/arm/dts/stm32mp13-ddr3-dhsom-1x4Gb-1066-binG.dtsi diff --git a/arch/arm/dts/stm32mp13-ddr3-dhsom-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x4Gb-1066-binG.dtsi new file mode 100644 index 00000000000..1d268d58b54 --- /dev/null +++ b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x4Gb-1066-binG.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2025, DH electronics - All Rights Reserved + * + * STM32MP13xx DHSOM configuration + * 1x DDR3L 8Gb, 16-bit, 533MHz, Single Die Package in flyby topology. + * Reference used W638GU6QB11I from Winbond + * + * DDR type / Platform DDR3/3L + * freq 533MHz + * width 16 + * datasheet 0 = W638GU6QB11I / DDR3-1866 + * DDR density 4 + * timing mode optimized + * address mapping : RBC + * Tc > + 85C : J + */ +#define DDR_MEM_COMPATIBLE ddr3l-dhsom-1066-888-bin-g-1x4gb-533mhz +#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz" +#define DDR_MEM_SPEED 533000 +#define DDR_MEM_SIZE 0x40000000 + +#define DDR_MSTR 0x00040401 +#define DDR_MRCTRL0 0x00000010 +#define DDR_MRCTRL1 0x00000000 +#define DDR_DERATEEN 0x00000000 +#define DDR_DERATEINT 0x00800000 +#define DDR_PWRCTL 0x00000000 +#define DDR_PWRTMG 0x00400010 +#define DDR_HWLPCTL 0x00000000 +#define DDR_RFSHCTL0 0x00210000 +#define DDR_RFSHCTL3 0x00000000 +#define DDR_RFSHTMG 0x0081008B +#define DDR_CRCPARCTL0 0x00000000 +#define DDR_DRAMTMG0 0x121B2414 +#define DDR_DRAMTMG1 0x000A041B +#define DDR_DRAMTMG2 0x0607080F +#define DDR_DRAMTMG3 0x0050400C +#define DDR_DRAMTMG4 0x07040607 +#define DDR_DRAMTMG5 0x06060403 +#define DDR_DRAMTMG6 0x02020002 +#define DDR_DRAMTMG7 0x00000202 +#define DDR_DRAMTMG8 0x00001005 +#define DDR_DRAMTMG14 0x000000A0 +#define DDR_ZQCTL0 0xC2000040 +#define DDR_DFITMG0 0x02050105 +#define DDR_DFITMG1 0x00000202 +#define DDR_DFILPCFG0 0x07000000 +#define DDR_DFIUPD0 0xC0400003 +#define DDR_DFIUPD1 0x00000000 +#define DDR_DFIUPD2 0x00000000 +#define DDR_DFIPHYMSTR 0x00000000 +#define DDR_ADDRMAP1 0x00080808 +#define DDR_ADDRMAP2 0x00000000 +#define DDR_ADDRMAP3 0x00000000 +#define DDR_ADDRMAP4 0x00001F1F +#define DDR_ADDRMAP5 0x07070707 +#define DDR_ADDRMAP6 0x07070707 +#define DDR_ADDRMAP9 0x00000000 +#define DDR_ADDRMAP10 0x00000000 +#define DDR_ADDRMAP11 0x00000000 +#define DDR_ODTCFG 0x06000600 +#define DDR_ODTMAP 0x00000001 +#define DDR_SCHED 0x00000F01 +#define DDR_SCHED1 0x00000000 +#define DDR_PERFHPR1 0x00000001 +#define DDR_PERFLPR1 0x04000200 +#define DDR_PERFWR1 0x08000400 +#define DDR_DBG0 0x00000000 +#define DDR_DBG1 0x00000000 +#define DDR_DBGCMD 0x00000000 +#define DDR_POISONCFG 0x00000000 +#define DDR_PCCFG 0x00000010 +#define DDR_PCFGR_0 0x00000000 +#define DDR_PCFGW_0 0x00000000 +#define DDR_PCFGQOS0_0 0x00100009 +#define DDR_PCFGQOS1_0 0x00000020 +#define DDR_PCFGWQOS0_0 0x01100B03 +#define DDR_PCFGWQOS1_0 0x01000200 +#define DDR_PGCR 0x01442E02 +#define DDR_PTR0 0x0022AA5B +#define DDR_PTR1 0x04841104 +#define DDR_PTR2 0x042DA068 +#define DDR_ACIOCR 0x10400812 +#define DDR_DXCCR 0x00000C40 +#define DDR_DSGCR 0xF200011F +#define DDR_DCR 0x0000000B +#define DDR_DTPR0 0x36D477D0 +#define DDR_DTPR1 0x098B00D8 +#define DDR_DTPR2 0x10023600 +#define DDR_MR0 0x00000830 +#define DDR_MR1 0x00000000 +#define DDR_MR2 0x00000208 +#define DDR_MR3 0x00000000 +#define DDR_ODTCR 0x00010000 +#define DDR_ZQ0CR1 0x00000038 +#define DDR_DX0GCR 0x0000CE81 +#define DDR_DX1GCR 0x0000CE81 + +#include "stm32mp13-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi index bedb7c600d5..39ac5692e08 100644 --- a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi @@ -6,6 +6,7 @@ #include #include "stm32mp13-u-boot.dtsi" #include "stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi" +#include "stm32mp13-ddr3-dhsom-1x4Gb-1066-binG.dtsi" / { aliases { diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index c18f1911fe4..55526189d5a 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -304,17 +304,29 @@ static void board_get_coding_straps(void) int board_stm32mp1_ddr_config_name_match(struct udevice *dev, const char *name) { - if (ddr3code == 1 && - !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz")) - return 0; + if (IS_ENABLED(CONFIG_TARGET_DH_STM32MP13X)) { + if (ddr3code == 1 && + !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-1x2gb-533mhz")) + return 0; + + if (ddr3code == 2 && + !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-1x4gb-533mhz")) + return 0; + } - if (ddr3code == 2 && - !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz")) - return 0; + if (IS_ENABLED(CONFIG_TARGET_DH_STM32MP15X)) { + if (ddr3code == 1 && + !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz")) + return 0; - if (ddr3code == 3 && - !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz")) - return 0; + if (ddr3code == 2 && + !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz")) + return 0; + + if (ddr3code == 3 && + !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz")) + return 0; + } return -EINVAL; } diff --git a/configs/stm32mp15_dhsom.config b/configs/stm32mp15_dhsom.config index 210ec201bf5..d5ecbac29e0 100644 --- a/configs/stm32mp15_dhsom.config +++ b/configs/stm32mp15_dhsom.config @@ -2,7 +2,6 @@ # CONFIG_ARMV7_VIRT is not set # CONFIG_BINMAN_FDT is not set -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_SIZE_LIMIT=1441792 CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_BOOTDELAY=1 diff --git a/configs/stm32mp_dhsom.config b/configs/stm32mp_dhsom.config index 56a40839d28..31fae2de19d 100644 --- a/configs/stm32mp_dhsom.config +++ b/configs/stm32mp_dhsom.config @@ -6,6 +6,7 @@ # CONFIG_SPL_PARTITION_UUIDS is not set # CONFIG_SPL_PINCTRL_FULL is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_BOOTCOUNT_LIMIT=y CONFIG_CMD_BOOTCOUNT=y -- cgit v1.3.1 From 78e94666dd794ccfab561a9ef6e5b9d6a785ee97 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 19 Nov 2025 00:17:23 +0100 Subject: ARM: stm32: Add missing build of debug UART init code on DH STM32MP1 DHSOM Commit c37a6684818d ("stm32mp: fix compilation issue with DEBUG_UART") split the debug UART initialization code into two files, but failed to update other non-ST boards. This did not lead to noticeable breakage until debug UART is enabled, which is not the default. Update the Makefile accordingly to allow debug UART to work. Fixes: c37a6684818d ("stm32mp: fix compilation issue with DEBUG_UART") Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- board/dhelectronics/dh_stm32mp1/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/dhelectronics/dh_stm32mp1/Makefile b/board/dhelectronics/dh_stm32mp1/Makefile index 2f4a301d1a0..429e01453bb 100644 --- a/board/dhelectronics/dh_stm32mp1/Makefile +++ b/board/dhelectronics/dh_stm32mp1/Makefile @@ -3,6 +3,8 @@ # Copyright (C) 2018, STMicroelectronics - All Rights Reserved # +obj-$(CONFIG_DEBUG_UART_BOARD_INIT) += ../../st/stm32mp1/debug_uart.o + obj-$(CONFIG_PMIC_STPMIC1) += ../../st/common/stpmic1.o obj-y += board.o -- cgit v1.3.1