From b28fee5cc2ae0c1103a4c5a98473369b597c3e74 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 17 Apr 2025 15:49:11 +0200 Subject: board: dragonboard410c: Fix button cmd name Commit 359e1d4a57e0 ("board: dragonboard410c: Use button_cmd instead of custom code") was made in parallel with commit 8f5685d5d32f ("button: qcom-pmic: prettify and standardise button labels"), which changed the default button label from "vol_down" to "Volume Down". This is causing errors in the console during boot now: No button labelled 'vol_down' Fix this by using the new label. Fixes: 359e1d4a57e0 ("board: dragonboard410c: Use button_cmd instead of custom code") Fixes: 8f5685d5d32f ("button: qcom-pmic: prettify and standardise button labels") Signed-off-by: Stephan Gerhold Reviewed-by: Reviewed-by: Sumit Garg Link: https://lore.kernel.org/r/20250417-db410c-fixes2-v1-1-76ad994da152@linaro.org Signed-off-by: Casey Connolly --- board/qualcomm/dragonboard410c/dragonboard410c.env | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.env b/board/qualcomm/dragonboard410c/dragonboard410c.env index 38399d65c64..ab253435ae7 100644 --- a/board/qualcomm/dragonboard410c/dragonboard410c.env +++ b/board/qualcomm/dragonboard410c/dragonboard410c.env @@ -2,5 +2,5 @@ initrd_high=0xffffffffffffffff fastboot=fastboot -l $fastboot_addr_r usb 0 boot_targets=usb mmc1 mmc0 pxe -button_cmd_0_name=vol_down +button_cmd_0_name=Volume Down button_cmd_0=run fastboot -- cgit v1.2.3 From 036b54c7200ec361776061ab1fe2ddd302fa78c5 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 17 Apr 2025 15:49:12 +0200 Subject: board: dragonboard410c: Drop custom reduced malloc size At the moment, the dragonboard410c_defconfig specifies a custom SYS_MALLOC_LEN, lower than the default for Qualcomm boards defined in arch/arm/mach-snapdragon/Kconfig. It looks like it's too low, since flashing larger sparse partition images using Fastboot fails with: FAILED (remote: 'Malloc failed for: CHUNK_TYPE_RAW') We are not really that memory-constrained for U-Boot on DB410c, so fix this by just dropping the custom malloc size and using the default. Signed-off-by: Stephan Gerhold Reviewed-by: Reviewed-by: Sumit Garg Link: https://lore.kernel.org/r/20250417-db410c-fixes2-v1-2-76ad994da152@linaro.org Signed-off-by: Casey Connolly --- configs/dragonboard410c_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index 449d48a3c00..6feba70b943 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -4,7 +4,6 @@ CONFIG_COUNTER_FREQUENCY=19200000 CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y CONFIG_ARCH_SNAPDRAGON=y CONFIG_TEXT_BASE=0x8f600000 -CONFIG_SYS_MALLOC_LEN=0x802000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0 CONFIG_ENV_SIZE=0x2000 -- cgit v1.2.3 From 792ccccb46e58fbeb3666efbe241bcfaa450568f Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 17 Apr 2025 15:49:13 +0200 Subject: board: dragonboard410c: Enable support for KASLR in Linux When booting Linux, there is currently the following warning in the console when using the default dragonboard410c_defconfig: [ 0.000000] KASLR disabled due to lack of seed Fix this by enabling DM_RNG and RNG_MSM in the defconfig to generate the KASLR seed: [ 0.000000] KASLR enabled Signed-off-by: Stephan Gerhold Reviewed-by: Reviewed-by: Sumit Garg Link: https://lore.kernel.org/r/20250417-db410c-fixes2-v1-3-76ad994da152@linaro.org Signed-off-by: Casey Connolly --- configs/dragonboard410c_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index 6feba70b943..d267b6ed34d 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -55,6 +55,8 @@ CONFIG_PINCONF=y CONFIG_PINCTRL_QCOM_APQ8016=y CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y +CONFIG_DM_RNG=y +CONFIG_RNG_MSM=y CONFIG_MSM_SERIAL=y CONFIG_SPMI_MSM=y CONFIG_USB=y -- cgit v1.2.3 From eb2c63ddccb94b134846f890fcada84554ba2896 Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Sat, 12 Apr 2025 18:41:31 +0100 Subject: power: qcom_vbus_regulator: add and fix support for pmic variants Fix and add support for different pmic variants pm8x50b to handle the vbus regulator. Signed-off-by: Rui Miguel Silva Link: https://lore.kernel.org/r/20250412174157.104419-1-rui.silva@linaro.org Signed-off-by: Casey Connolly --- drivers/power/regulator/qcom_usb_vbus_regulator.c | 37 ++++++++++++++++++----- 1 file changed, 30 insertions(+), 7 deletions(-) diff --git a/drivers/power/regulator/qcom_usb_vbus_regulator.c b/drivers/power/regulator/qcom_usb_vbus_regulator.c index 2d58ef5e111..07f118d4797 100644 --- a/drivers/power/regulator/qcom_usb_vbus_regulator.c +++ b/drivers/power/regulator/qcom_usb_vbus_regulator.c @@ -15,14 +15,33 @@ #include #include -#define CMD_OTG 0x50 +enum pm8x50b_vbus { + PM8150B, + PM8550B, +}; + #define OTG_EN BIT(0) -// The 0 bit in this register's bit field is undocumented -#define OTG_CFG 0x56 + #define OTG_EN_SRC_CFG BIT(1) +struct qcom_otg_regs { + u32 otg_cmd; + u32 otg_cfg; +}; struct qcom_usb_vbus_priv { phys_addr_t base; + struct qcom_otg_regs *regs; +}; + +static const struct qcom_otg_regs qcom_otg[] = { + [PM8150B] = { + .otg_cmd = 0x40, + .otg_cfg = 0x53, + }, + [PM8550B] = { + .otg_cmd = 0x50, + .otg_cfg = 0x56, + }, }; static int qcom_usb_vbus_regulator_of_to_plat(struct udevice *dev) @@ -38,8 +57,9 @@ static int qcom_usb_vbus_regulator_of_to_plat(struct udevice *dev) static int qcom_usb_vbus_regulator_get_enable(struct udevice *dev) { + const struct qcom_otg_regs *regs = &qcom_otg[dev_get_driver_data(dev)]; struct qcom_usb_vbus_priv *priv = dev_get_priv(dev); - int otg_en_reg = priv->base + CMD_OTG; + int otg_en_reg = priv->base + regs->otg_cmd; int ret; ret = pmic_reg_read(dev->parent, otg_en_reg); @@ -53,8 +73,9 @@ static int qcom_usb_vbus_regulator_get_enable(struct udevice *dev) static int qcom_usb_vbus_regulator_set_enable(struct udevice *dev, bool enable) { + const struct qcom_otg_regs *regs = &qcom_otg[dev_get_driver_data(dev)]; struct qcom_usb_vbus_priv *priv = dev_get_priv(dev); - int otg_en_reg = priv->base + CMD_OTG; + int otg_en_reg = priv->base + regs->otg_cmd; int ret; if (enable) { @@ -76,8 +97,9 @@ static int qcom_usb_vbus_regulator_set_enable(struct udevice *dev, bool enable) static int qcom_usb_vbus_regulator_probe(struct udevice *dev) { + const struct qcom_otg_regs *regs = &qcom_otg[dev_get_driver_data(dev)]; struct qcom_usb_vbus_priv *priv = dev_get_priv(dev); - int otg_cfg_reg = priv->base + OTG_CFG; + int otg_cfg_reg = priv->base + regs->otg_cfg; int ret; /* Disable HW logic for VBUS enable */ @@ -96,7 +118,8 @@ static const struct dm_regulator_ops qcom_usb_vbus_regulator_ops = { }; static const struct udevice_id qcom_usb_vbus_regulator_ids[] = { - { .compatible = "qcom,pm8150b-vbus-reg"}, + { .compatible = "qcom,pm8150b-vbus-reg", .data = PM8150B }, + { .compatible = "qcom,pm8550b-vbus-reg", .data = PM8550B }, { }, }; -- cgit v1.2.3 From 3d9e6d42ca1433c6dd478bf6c0f73e2b9484c94c Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 24 Apr 2025 11:16:41 +0200 Subject: clk: qcom: apq8016: Fix SDCC clock addresses The SDCC_...(n) macros in clock-apq8016.c result in the wrong addresses: - SDCC1: SDCC_APPS_CBCR(0) = ((0 * 0x1000) + 0x41018) = 0x41018 Should be 0x42018, this is an invalid register close to the USB clocks. - SDCC2: SDCC_APPS_CBCR(1) = ((1 * 0x1000) + 0x41018) = 0x42018 Should be 0x43018, this is the SDCC1 clock. When we try to enable SDCC2, we actually end up enabling SDCC1. When we try to enable SDCC1, we just issue some broken register writes. This hasn't caused any trouble so far, because the boot firmware is keeping both SDCC clocks running. However, if these clocks are disabled when entering U-Boot, MMC initialization is failing. Fix this by using the proper offset for the macros. The SDCC_CMD_RCGR() was already correct, but change it the same way for consistency. Fixes: 085921368b7d ("arm: Add support for Qualcomm Snapdragon family") Reviewed-by: Neil Armstrong Signed-off-by: Stephan Gerhold Reviewed-by: Sumit Garg Reviewed-by: Casey Connolly Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-1-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly --- drivers/clk/qcom/clock-apq8016.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 6a53f900a9e..274c71c53ff 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -23,10 +23,10 @@ #define APCS_GPLL_ENA_VOTE (0x45000) #define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) -#define SDCC_BCR(n) ((n * 0x1000) + 0x41000) -#define SDCC_CMD_RCGR(n) (((n + 1) * 0x1000) + 0x41004) -#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018) -#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C) +#define SDCC_BCR(n) (((n) * 0x1000) + 0x42000) +#define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x42004) +#define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x42018) +#define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4201C) /* BLSP1 AHB clock (root clock for BLSP) */ #define BLSP1_AHB_CBCR 0x1008 -- cgit v1.2.3 From 409da8c4935338743b054e7c82f463c4a1c538e0 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 24 Apr 2025 11:16:42 +0200 Subject: clk: qcom: Move qcom_gate_clk_en() to C file This avoids having to inline it separately into every single clock driver, when U-Boot is built with support for multiple SoCs. Reviewed-by: Neil Armstrong Signed-off-by: Stephan Gerhold Reviewed-by: Sumit Garg Reviewed-by: Casey Connolly Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-2-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly --- drivers/clk/qcom/clock-qcom.c | 15 +++++++++++++++ drivers/clk/qcom/clock-qcom.h | 15 +-------------- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 7687bbe6a23..5018851725b 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -74,6 +74,21 @@ void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk) } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL)); } +int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id) +{ + u32 val; + if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) { + log_err("gcc@%#08llx: unknown clock ID %lu!\n", + priv->base, id); + return -ENOENT; + } + + val = readl(priv->base + priv->data->clks[id].reg); + writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg); + + return 0; +} + #define APPS_CMD_RCGR_UPDATE BIT(0) /* Update clock command via CMD_RCGR */ diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index f43edea2525..ee0347d9d86 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -107,19 +107,6 @@ void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, int source); void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled); -static inline int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id) -{ - u32 val; - if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) { - log_err("gcc@%#08llx: unknown clock ID %lu!\n", - priv->base, id); - return -ENOENT; - } - - val = readl(priv->base + priv->data->clks[id].reg); - writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg); - - return 0; -} +int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id); #endif -- cgit v1.2.3 From 94e57ba2011b4bb96c0714e02a5056bc0c7f87d0 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 24 Apr 2025 11:16:43 +0200 Subject: clk: qcom: Use setbits_le32() for qcom_gate_clk_en() The other clock enable functions in clock-qcom.c use setbits_le32() to read/modify/write the enable registers. Use the same for qcom_gate_clk_en() to simplify the code a bit. Reviewed-by: Neil Armstrong Signed-off-by: Stephan Gerhold Reviewed-by: Sumit Garg Reviewed-by: Casey Connolly Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-3-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly --- drivers/clk/qcom/clock-qcom.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 5018851725b..7a259db7934 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -76,16 +76,13 @@ void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk) int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id) { - u32 val; if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) { log_err("gcc@%#08llx: unknown clock ID %lu!\n", priv->base, id); return -ENOENT; } - val = readl(priv->base + priv->data->clks[id].reg); - writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg); - + setbits_le32(priv->base + priv->data->clks[id].reg, priv->data->clks[id].en_val); return 0; } -- cgit v1.2.3 From 6c049ed99392353bcda24f708e1cfa5c21f2a0f9 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 24 Apr 2025 11:16:44 +0200 Subject: clk: qcom: Allow polling for clock status in qcom_gate_clk_en() GATE_CLK() in its current state is unsafe: A simple write to the clock enable register does not guarantee that the clock is immediately running. Without polling the clock status, we may issue writes to registers before the necessary clocks start running. This doesn't seem to cause issues in U-Boot at the moment, but for example removing the CLK_OFF polling in TF-A for the SMMU clocks on DB410c reliably triggers an exception during boot. Make it possible to poll the branch clock status register, by adding a new GATE_CLK_POLLED() macro that takes the extra register address. Existing usages work just as before, without polling the clock status. Ideally all usages should be updated to specify the correct poll address in the future. The Qualcomm naming for these clocks is "branch" and not "gate", but let's keep the existing naming for now to avoid confusion until all others drivers have been converted. Reviewed-by: Neil Armstrong Signed-off-by: Stephan Gerhold Reviewed-by: Sumit Garg Reviewed-by: Casey Connolly Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-4-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly --- drivers/clk/qcom/clock-qcom.c | 15 +++++++++++++++ drivers/clk/qcom/clock-qcom.h | 11 +++++++++-- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 7a259db7934..6b46d9db744 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -83,6 +83,21 @@ int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id) } setbits_le32(priv->base + priv->data->clks[id].reg, priv->data->clks[id].en_val); + if (priv->data->clks[id].cbcr_reg) { + unsigned int count; + u32 val; + + for (count = 0; count < 200; count++) { + val = readl(priv->base + priv->data->clks[id].cbcr_reg); + val &= BRANCH_CHECK_MASK; + if (val == BRANCH_ON_VAL || val == BRANCH_NOC_FSM_ON_VAL) + break; + udelay(1); + } + if (WARN(count == 200, "WARNING: Clock @ %#lx [%#010x] stuck at off\n", + priv->data->clks[id].cbcr_reg, val)) + return -EBUSY; + } return 0; } diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index ee0347d9d86..1b60882dae4 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -52,13 +52,20 @@ struct freq_tbl { struct gate_clk { uintptr_t reg; u32 en_val; + uintptr_t cbcr_reg; const char *name; }; +/* + * GATE_CLK() is deprecated: Use GATE_CLK_POLLED() instead to ensure the clock + * is running before we start making use of devices or registers. + */ #ifdef DEBUG -#define GATE_CLK(clk, reg, val) [clk] = { reg, val, #clk } +#define GATE_CLK(clk, reg, val) [clk] = { reg, val, 0, #clk } +#define GATE_CLK_POLLED(clk, en_reg, val, cbcr_reg) [clk] = { en_reg, val, cbcr_reg, #clk } #else -#define GATE_CLK(clk, reg, val) [clk] = { reg, val, NULL } +#define GATE_CLK(clk, reg, val) [clk] = { reg, val, 0, NULL } +#define GATE_CLK_POLLED(clk, en_reg, val, cbcr_reg) [clk] = { en_reg, val, cbcr_reg, NULL } #endif struct qcom_reset_map { -- cgit v1.2.3 From 9d9bac00bc071deaeac1428c9d7dfe0afa1939a7 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 24 Apr 2025 11:16:45 +0200 Subject: clk: qcom: apq8016: Convert GATE_CLK() to GATE_CLK_POLLED() Convert the usages of GATE_CLK() in clock-apq8016 to GATE_CLK_POLLED() to make sure that we poll the status when enabling clocks: - PRNG_AHB_CLK is a vote clock, so we poll a different register address. - The USB clocks are simple branches, so enable/poll is the same register. Reviewed-by: Neil Armstrong Signed-off-by: Stephan Gerhold Reviewed-by: Sumit Garg Reviewed-by: Casey Connolly Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-5-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly --- drivers/clk/qcom/clock-apq8016.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 274c71c53ff..e3a9807f580 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -54,9 +54,9 @@ static struct vote_clk gcc_blsp1_ahb_clk = { }; static const struct gate_clk apq8016_clks[] = { - GATE_CLK(GCC_PRNG_AHB_CLK, 0x45004, BIT(8)), - GATE_CLK(GCC_USB_HS_AHB_CLK, 0x41008, BIT(0)), - GATE_CLK(GCC_USB_HS_SYSTEM_CLK, 0x41004, BIT(0)), + GATE_CLK_POLLED(GCC_PRNG_AHB_CLK, 0x45004, BIT(8), 0x13004), + GATE_CLK_POLLED(GCC_USB_HS_AHB_CLK, 0x41008, BIT(0), 0x41008), + GATE_CLK_POLLED(GCC_USB_HS_SYSTEM_CLK, 0x41004, BIT(0), 0x41004), }; /* SDHCI */ -- cgit v1.2.3 From 1079d4bf2ed88e7e34a56152a63eb16fca7f7811 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 24 Apr 2025 11:16:46 +0200 Subject: clk: qcom: apq8016: Fix SDCC clock warnings As of commit dc8754e8e408 ("clk/qcom: apq8016: improve clk_enable logging") there are now warnings in the U-Boot console on DragonBoard 410c: apq8016_clk_enable: unknown clk id 122 apq8016_clk_enable: unknown clk id 123 apq8016_clk_enable: unknown clk id 124 apq8016_clk_enable: unknown clk id 125 This is because we don't implement enable() properly for the SDCC clocks. Currently they are being enabled as part of set_rate(). Fix this by moving the enable calls out of the apq8016_clk_init_sdc() function and convert them to the equivalent GATE_CLK_POLLED() definitions. Reviewed-by: Neil Armstrong Signed-off-by: Stephan Gerhold Reviewed-by: Sumit Garg Reviewed-by: Casey Connolly Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-6-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly --- drivers/clk/qcom/clock-apq8016.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index e3a9807f580..b7bd9c9a342 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -23,10 +23,7 @@ #define APCS_GPLL_ENA_VOTE (0x45000) #define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) -#define SDCC_BCR(n) (((n) * 0x1000) + 0x42000) #define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x42004) -#define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x42018) -#define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4201C) /* BLSP1 AHB clock (root clock for BLSP) */ #define BLSP1_AHB_CBCR 0x1008 @@ -55,6 +52,10 @@ static struct vote_clk gcc_blsp1_ahb_clk = { static const struct gate_clk apq8016_clks[] = { GATE_CLK_POLLED(GCC_PRNG_AHB_CLK, 0x45004, BIT(8), 0x13004), + GATE_CLK_POLLED(GCC_SDCC1_AHB_CLK, 0x4201c, BIT(0), 0x4201c), + GATE_CLK_POLLED(GCC_SDCC1_APPS_CLK, 0x42018, BIT(0), 0x42018), + GATE_CLK_POLLED(GCC_SDCC2_AHB_CLK, 0x4301c, BIT(0), 0x4301c), + GATE_CLK_POLLED(GCC_SDCC2_APPS_CLK, 0x43018, BIT(0), 0x43018), GATE_CLK_POLLED(GCC_USB_HS_AHB_CLK, 0x41008, BIT(0), 0x41008), GATE_CLK_POLLED(GCC_USB_HS_SYSTEM_CLK, 0x41004, BIT(0), 0x41004), }; @@ -67,12 +68,10 @@ static int apq8016_clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) if (rate == 200000000) div = 4; - clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot)); /* 800Mhz/div, gpll0 */ clk_rcg_set_rate_mnd(priv->base, SDCC_CMD_RCGR(slot), div, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_enable_gpll0(priv->base, &gpll0_vote_clk); - clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot)); return rate; } -- cgit v1.2.3 From c92bf21e731a20d7de6acacd6487e98c69fd2a83 Mon Sep 17 00:00:00 2001 From: Alexey Minnekhanov Date: Thu, 24 Apr 2025 04:48:11 +0300 Subject: button: qcom-pmic: allow to specify code in devicetree Most device vendors put "Volume Down" button onto PMIC RESIN. But Sony is special: see dts/upstream/src/arm64/qcom/sdm630-sony-xperia-nile.dtsi or [1]. They put "Volume Down" on PMIC GPIO 7 where others usually put "Volume Up", and KEY_VOLUMEUP is inside &pon_resin. Currently if you boot U-Boot on such Sony device, you end up with 2 "Volume Down" buttons, and no "Volume Up", which makes navigating menu problematic. Support reading devicetree "linux,code" property and override statically defined button code & label based on that. [1] https://elixir.bootlin.com/linux/v6.15-rc3/source/arch/ arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi#L263 Signed-off-by: Alexey Minnekhanov Signed-off-by: Alexey Minnekhanov Reviewed-by: Casey Connolly Link: https://lore.kernel.org/r/20250424014811.3809818-1-alexeymin@minlexx.ru Signed-off-by: Casey Connolly --- drivers/button/button-qcom-pmic.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/button/button-qcom-pmic.c b/drivers/button/button-qcom-pmic.c index e3bb9bd758a..85addfe32a2 100644 --- a/drivers/button/button-qcom-pmic.c +++ b/drivers/button/button-qcom-pmic.c @@ -143,6 +143,21 @@ static int qcom_pwrkey_probe(struct udevice *dev) priv->base = base; + ret = dev_read_u32(dev, "linux,code", &priv->code); + if (ret == 0) { + /* convert key, if read OK */ + switch (priv->code) { + case KEY_VOLUMEDOWN: + priv->code = KEY_DOWN; + uc_plat->label = "Volume Down"; + break; + case KEY_VOLUMEUP: + priv->code = KEY_UP; + uc_plat->label = "Volume Up"; + break; + } + } + /* Do a sanity check */ ret = pmic_reg_read(priv->pmic, priv->base + REG_TYPE); if (ret != 0x1 && ret != 0xb) { -- cgit v1.2.3 From 14315b73a8e7aef9125c7c1aa28ebe3f0725a202 Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Mon, 5 May 2025 18:13:33 +0530 Subject: mach-snapdragon: Update fdtfile logic to work for RB1 and RB2 RB1 and RB2 have three root compatibles where the last one can't be used to decode fdtfile name (qcm* vs qrb*). So rather just rely on the first compatible to retrieve the SoC name. Signed-off-by: Sumit Garg Link: https://lore.kernel.org/r/20250505124333.12344-1-sumit.garg@kernel.org Signed-off-by: Casey Connolly --- arch/arm/mach-snapdragon/board.c | 63 +++++++++++++++++++++++----------------- 1 file changed, 36 insertions(+), 27 deletions(-) diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 3ab75f0fce0..5547d6d054f 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -409,52 +409,39 @@ static void configure_env(void) return; } - /* The last compatible is always the SoC compatible */ - ret = ofnode_read_string_index(root, "compatible", compat_count - 1, &last_compat); - if (ret < 0) { - log_warning("Can't read second compatible\n"); - return; - } - - /* Copy the second compat (e.g. "qcom,sdm845") into buf */ - strlcpy(buf, last_compat, sizeof(buf) - 1); - tmp = buf; - - /* strsep() is destructive, it replaces the comma with a \0 */ - if (!strsep(&tmp, ",")) { - log_warning("second compatible '%s' has no ','\n", buf); - return; - } - - /* tmp now points to just the "sdm845" part of the string */ - env_set("soc", tmp); - - /* Now figure out the "board" part from the first compatible */ - memset(buf, 0, sizeof(buf)); strlcpy(buf, first_compat, sizeof(buf) - 1); tmp = buf; /* The Qualcomm reference boards (RBx, HDK, etc) */ if (!strncmp("qcom", buf, strlen("qcom"))) { + char *soc; + /* * They all have the first compatible as "qcom,-" * (e.g. "qcom,qrb5165-rb5"). We extract just the part after * the dash. */ - if (!strsep(&tmp, "-")) { + if (!strsep(&tmp, ",")) { + log_warning("compatible '%s' has no ','\n", buf); + return; + } + soc = strsep(&tmp, "-"); + if (!soc) { log_warning("compatible '%s' has no '-'\n", buf); return; } - /* tmp is now "rb5" */ + + env_set("soc", soc); env_set("board", tmp); } else { if (!strsep(&tmp, ",")) { log_warning("compatible '%s' has no ','\n", buf); return; } - /* for thundercomm we just want the bit after the comma (e.g. "db845c"), - * for all other boards we replace the comma with a '-' and take both - * (e.g. "oneplus-enchilada") + /* + * For thundercomm we just want the bit after the comma + * (e.g. "db845c"), for all other boards we replace the comma + * with a '-' and take both (e.g. "oneplus-enchilada") */ if (!strncmp("thundercomm", buf, strlen("thundercomm"))) { env_set("board", tmp); @@ -462,6 +449,28 @@ static void configure_env(void) *(tmp - 1) = '-'; env_set("board", buf); } + + /* The last compatible is always the SoC compatible */ + ret = ofnode_read_string_index(root, "compatible", + compat_count - 1, &last_compat); + if (ret < 0) { + log_warning("Can't read second compatible\n"); + return; + } + + /* Copy the last compat (e.g. "qcom,sdm845") into buf */ + memset(buf, 0, sizeof(buf)); + strlcpy(buf, last_compat, sizeof(buf) - 1); + tmp = buf; + + /* strsep() is destructive, it replaces the comma with a \0 */ + if (!strsep(&tmp, ",")) { + log_warning("second compatible '%s' has no ','\n", buf); + return; + } + + /* tmp now points to just the "sdm845" part of the string */ + env_set("soc", tmp); } /* Now build the full path name */ -- cgit v1.2.3