From ffda1089dd8065a943b27eb6f9ceeea51171d951 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 14 Nov 2023 09:59:48 -0600 Subject: arm: mach-k3: Move R5 specific code into new r5/ directory This makes it clear these are only to be used by the R5 builds of SPL. And this will be used to later more cleanly split the two builds. Signed-off-by: Andrew Davis --- arch/arm/mach-k3/Makefile | 6 +- arch/arm/mach-k3/am62ax/Makefile | 7 - arch/arm/mach-k3/am62ax/am62a_qos_data.c | 46 -- arch/arm/mach-k3/am62ax/clk-data.c | 317 ----------- arch/arm/mach-k3/am62ax/dev-data.c | 73 --- arch/arm/mach-k3/am62x/Makefile | 6 - arch/arm/mach-k3/am62x/clk-data.c | 367 ------------- arch/arm/mach-k3/am62x/dev-data.c | 79 --- arch/arm/mach-k3/j7200/Makefile | 5 - arch/arm/mach-k3/j7200/clk-data.c | 555 ------------------- arch/arm/mach-k3/j7200/dev-data.c | 83 --- arch/arm/mach-k3/j721e/Makefile | 5 - arch/arm/mach-k3/j721e/clk-data.c | 789 ---------------------------- arch/arm/mach-k3/j721e/dev-data.c | 81 --- arch/arm/mach-k3/j721s2/Makefile | 5 - arch/arm/mach-k3/j721s2/clk-data.c | 406 -------------- arch/arm/mach-k3/j721s2/dev-data.c | 87 --- arch/arm/mach-k3/lowlevel_init.S | 20 - arch/arm/mach-k3/r5/Makefile | 13 + arch/arm/mach-k3/r5/am62ax/Makefile | 7 + arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c | 46 ++ arch/arm/mach-k3/r5/am62ax/clk-data.c | 317 +++++++++++ arch/arm/mach-k3/r5/am62ax/dev-data.c | 73 +++ arch/arm/mach-k3/r5/am62x/Makefile | 6 + arch/arm/mach-k3/r5/am62x/clk-data.c | 367 +++++++++++++ arch/arm/mach-k3/r5/am62x/dev-data.c | 79 +++ arch/arm/mach-k3/r5/j7200/Makefile | 5 + arch/arm/mach-k3/r5/j7200/clk-data.c | 555 +++++++++++++++++++ arch/arm/mach-k3/r5/j7200/dev-data.c | 83 +++ arch/arm/mach-k3/r5/j721e/Makefile | 5 + arch/arm/mach-k3/r5/j721e/clk-data.c | 789 ++++++++++++++++++++++++++++ arch/arm/mach-k3/r5/j721e/dev-data.c | 81 +++ arch/arm/mach-k3/r5/j721s2/Makefile | 5 + arch/arm/mach-k3/r5/j721s2/clk-data.c | 406 ++++++++++++++ arch/arm/mach-k3/r5/j721s2/dev-data.c | 87 +++ arch/arm/mach-k3/r5/lowlevel_init.S | 20 + arch/arm/mach-k3/r5/r5_mpu.c | 49 ++ arch/arm/mach-k3/r5_mpu.c | 48 -- 38 files changed, 2994 insertions(+), 2984 deletions(-) delete mode 100644 arch/arm/mach-k3/am62ax/Makefile delete mode 100644 arch/arm/mach-k3/am62ax/am62a_qos_data.c delete mode 100644 arch/arm/mach-k3/am62ax/clk-data.c delete mode 100644 arch/arm/mach-k3/am62ax/dev-data.c delete mode 100644 arch/arm/mach-k3/am62x/Makefile delete mode 100644 arch/arm/mach-k3/am62x/clk-data.c delete mode 100644 arch/arm/mach-k3/am62x/dev-data.c delete mode 100644 arch/arm/mach-k3/j7200/Makefile delete mode 100644 arch/arm/mach-k3/j7200/clk-data.c delete mode 100644 arch/arm/mach-k3/j7200/dev-data.c delete mode 100644 arch/arm/mach-k3/j721e/Makefile delete mode 100644 arch/arm/mach-k3/j721e/clk-data.c delete mode 100644 arch/arm/mach-k3/j721e/dev-data.c delete mode 100644 arch/arm/mach-k3/j721s2/Makefile delete mode 100644 arch/arm/mach-k3/j721s2/clk-data.c delete mode 100644 arch/arm/mach-k3/j721s2/dev-data.c delete mode 100644 arch/arm/mach-k3/lowlevel_init.S create mode 100644 arch/arm/mach-k3/r5/Makefile create mode 100644 arch/arm/mach-k3/r5/am62ax/Makefile create mode 100644 arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c create mode 100644 arch/arm/mach-k3/r5/am62ax/clk-data.c create mode 100644 arch/arm/mach-k3/r5/am62ax/dev-data.c create mode 100644 arch/arm/mach-k3/r5/am62x/Makefile create mode 100644 arch/arm/mach-k3/r5/am62x/clk-data.c create mode 100644 arch/arm/mach-k3/r5/am62x/dev-data.c create mode 100644 arch/arm/mach-k3/r5/j7200/Makefile create mode 100644 arch/arm/mach-k3/r5/j7200/clk-data.c create mode 100644 arch/arm/mach-k3/r5/j7200/dev-data.c create mode 100644 arch/arm/mach-k3/r5/j721e/Makefile create mode 100644 arch/arm/mach-k3/r5/j721e/clk-data.c create mode 100644 arch/arm/mach-k3/r5/j721e/dev-data.c create mode 100644 arch/arm/mach-k3/r5/j721s2/Makefile create mode 100644 arch/arm/mach-k3/r5/j721s2/clk-data.c create mode 100644 arch/arm/mach-k3/r5/j721s2/dev-data.c create mode 100644 arch/arm/mach-k3/r5/lowlevel_init.S create mode 100644 arch/arm/mach-k3/r5/r5_mpu.c delete mode 100644 arch/arm/mach-k3/r5_mpu.c diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index c7ca0fdce56..215c755c5dc 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -3,12 +3,8 @@ # Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ # Lokesh Vutla -obj-$(CONFIG_SOC_K3_J721E) += j721e/ j7200/ -obj-$(CONFIG_SOC_K3_J721S2) += j721s2/ -obj-$(CONFIG_SOC_K3_AM625) += am62x/ -obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/ +obj-$(CONFIG_CPU_V7R) += r5/ obj-$(CONFIG_ARM64) += arm64-mmu.o -obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o obj-$(CONFIG_ARM64) += cache.o obj-$(CONFIG_OF_LIBFDT) += common_fdt.o ifeq ($(CONFIG_OF_LIBFDT)$(CONFIG_OF_SYSTEM_SETUP),yy) diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/am62ax/Makefile deleted file mode 100644 index 02a941805e9..00000000000 --- a/arch/arm/mach-k3/am62ax/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ - -obj-y += clk-data.o -obj-y += dev-data.o -obj-y += am62a_qos_data.o diff --git a/arch/arm/mach-k3/am62ax/am62a_qos_data.c b/arch/arm/mach-k3/am62ax/am62a_qos_data.c deleted file mode 100644 index 38db4f2f5c8..00000000000 --- a/arch/arm/mach-k3/am62ax/am62a_qos_data.c +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * am62a Quality of Service (QoS) Configuration Data - * Auto generated from K3 Resource Partitioning tool - * - * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ - */ -#include -#include "common.h" - -struct k3_qos_data am62a_qos_data[] = { - /* modules_qosConfig0 - 1 endpoints, 4 channels */ - { - .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 0, - .val = ORDERID_8, - }, - { - .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 1, - .val = ORDERID_8, - }, - { - .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 2, - .val = ORDERID_8, - }, - { - .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 3, - .val = ORDERID_8, - }, - - /* Following registers set 1:1 mapping for orderID MAP1/MAP2 - * remap registers. orderID x is remapped to orderID x again - * This is to ensure orderID from MAP register is unchanged - */ - - /* K3_DSS_UL_MAIN_0_VBUSM_DMA - 1 groups */ - { - .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0, - .val = 0x76543210, - }, - { - .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 4, - .val = 0xfedcba98, - }, -}; - -uint32_t am62a_qos_count = sizeof(am62a_qos_data) / sizeof(am62a_qos_data[0]); diff --git a/arch/arm/mach-k3/am62ax/clk-data.c b/arch/arm/mach-k3/am62ax/clk-data.c deleted file mode 100644 index d950b35e0be..00000000000 --- a/arch/arm/mach-k3/am62ax/clk-data.c +++ /dev/null @@ -1,317 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * AM62AX specific clock platform data - * - * This file is auto generated. Please do not hand edit and report any issues - * to Bryan Brattlof . - * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include "k3-clk.h" - -static const char * const gluelogic_hfosc0_clkout_parents[] = { - NULL, - NULL, - "osc_24_mhz", - "osc_25_mhz", - "osc_26_mhz", - NULL, -}; - -static const char * const clk_32k_rc_sel_out0_parents[] = { - "gluelogic_rcosc_clk_1p0v_97p65k", - "gluelogic_hfosc0_clkout", - "gluelogic_rcosc_clk_1p0v_97p65k", - "gluelogic_lfosc0_clkout", -}; - -static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = { - "board_0_mmc0_clklb_out", - "board_0_mmc0_clk_out", -}; - -static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = { - "board_0_mmc1_clklb_out", - "board_0_mmc1_clk_out", -}; - -static const char * const main_ospi_loopback_clk_sel_out0_parents[] = { - "board_0_ospi0_dqs_out", - "board_0_ospi0_lbclko_out", -}; - -static const char * const main_usb0_refclk_sel_out0_parents[] = { - "gluelogic_hfosc0_clkout", - "postdiv4_16ff_main_0_hsdivout8_clk", -}; - -static const char * const main_usb1_refclk_sel_out0_parents[] = { - "gluelogic_hfosc0_clkout", - "postdiv4_16ff_main_0_hsdivout8_clk", -}; - -static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { - "gluelogic_hfosc0_clkout", - "hsdiv4_16fft_main_0_hsdivout0_clk", -}; - -static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { - "gluelogic_hfosc0_clkout", - "hsdiv4_16fft_mcu_0_hsdivout0_clk", -}; - -static const char * const clkout0_ctrl_out0_parents[] = { - "hsdiv4_16fft_main_2_hsdivout1_clk", - "hsdiv4_16fft_main_2_hsdivout1_clk", -}; - -static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { - "postdiv4_16ff_main_0_hsdivout5_clk", - "hsdiv4_16fft_main_2_hsdivout2_clk", -}; - -static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { - "postdiv4_16ff_main_0_hsdivout5_clk", - "hsdiv4_16fft_main_2_hsdivout2_clk", -}; - -static const char * const main_gtcclk_sel_out0_parents[] = { - "postdiv4_16ff_main_2_hsdivout5_clk", - "postdiv4_16ff_main_0_hsdivout6_clk", - "board_0_cp_gemac_cpts0_rft_clk_out", - NULL, - "board_0_mcu_ext_refclk0_out", - "board_0_ext_refclk1_out", - "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", - "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", -}; - -static const char * const main_ospi_ref_clk_sel_out0_parents[] = { - "hsdiv4_16fft_main_0_hsdivout1_clk", - "postdiv1_16fft_main_1_hsdivout5_clk", -}; - -static const char * const wkup_clkout_sel_out0_parents[] = { - NULL, - "gluelogic_lfosc0_clkout", - "hsdiv4_16fft_main_0_hsdivout2_clk", - "hsdiv4_16fft_main_1_hsdivout2_clk", - "postdiv4_16ff_main_2_hsdivout9_clk", - "clk_32k_rc_sel_out0", - "gluelogic_rcosc_clkout", - "gluelogic_hfosc0_clkout", -}; - -static const char * const wkup_clkout_sel_io_out0_parents[] = { - "wkup_clkout_sel_out0", - "gluelogic_hfosc0_clkout", -}; - -static const char * const wkup_clksel_out0_parents[] = { - "hsdiv2_16fft_main_15_hsdivout0_clk", - "hsdiv4_16fft_mcu_0_hsdivout0_clk", -}; - -static const char * const main_usart0_fclk_sel_out0_parents[] = { - "usart_programmable_clock_divider_out0", - "hsdiv4_16fft_main_1_hsdivout1_clk", -}; - -static const struct clk_data clk_list[] = { - CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), - CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), - CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), - CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), - CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0), - CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0), - CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0), - CLK_FIXED_RATE("board_0_ddr0_ck0_out", 0, 0), - CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), - CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0), - CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), - CLK_FIXED_RATE("board_0_mmc0_clklb_out", 0, 0), - CLK_FIXED_RATE("board_0_mmc0_clk_out", 0, 0), - CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0), - CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), - CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), - CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), - CLK_FIXED_RATE("board_0_tck_out", 0, 0), - CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), - CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0), - CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), - CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0), - CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0), - CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_PLL("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0), - CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0), - CLK_PLL("pllfracf_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0), - CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0), - CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0), - CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0), - CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), - CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0), - CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), - CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0), - CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0), - CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0), - CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0), - CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0), - CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0), - CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0), - CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0), - CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0), - CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0), - CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), - CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), - CLK_DIV("hsdiv2_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), - CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), - CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), - CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), - CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), - CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), - CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), - CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), - CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), - CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), - CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), - CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0), - CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000), - CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0), - CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0), - CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0), - CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0), - CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0), - CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0), - CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), - CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0), -}; - -static const struct dev_clk soc_dev_clk_data[] = { - DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), - DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), - DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), - DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"), - DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"), - DEV_CLK(16, 5, "board_0_ext_refclk1_out"), - DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"), - DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"), - DEV_CLK(16, 9, "board_0_ext_refclk1_out"), - DEV_CLK(16, 10, "gluelogic_rcosc_clkout"), - DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(57, 0, "main_emmcsd0_io_clklb_sel_out0"), - DEV_CLK(57, 1, "board_0_mmc0_clklb_out"), - DEV_CLK(57, 2, "board_0_mmc0_clk_out"), - DEV_CLK(57, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(57, 6, "main_emmcsd0_refclk_sel_out0"), - DEV_CLK(57, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), - DEV_CLK(57, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), - DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"), - DEV_CLK(58, 1, "board_0_mmc1_clklb_out"), - DEV_CLK(58, 2, "board_0_mmc1_clk_out"), - DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"), - DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), - DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), - DEV_CLK(61, 0, "main_gtcclk_sel_out0"), - DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"), - DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"), - DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"), - DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"), - DEV_CLK(61, 6, "board_0_ext_refclk1_out"), - DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), - DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(61, 9, "wkup_clksel_out0"), - DEV_CLK(61, 10, "hsdiv2_16fft_main_15_hsdivout0_clk"), - DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), - DEV_CLK(75, 0, "board_0_ospi0_dqs_out"), - DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"), - DEV_CLK(75, 3, "board_0_ospi0_dqs_out"), - DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"), - DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"), - DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"), - DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"), - DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(95, 0, "gluelogic_rcosc_clkout"), - DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"), - DEV_CLK(95, 2, "wkup_clksel_out0"), - DEV_CLK(95, 3, "hsdiv2_16fft_main_15_hsdivout0_clk"), - DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), - DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(102, 1, "board_0_i2c0_scl_out"), - DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"), - DEV_CLK(107, 0, "wkup_clksel_out0"), - DEV_CLK(107, 1, "hsdiv2_16fft_main_15_hsdivout0_clk"), - DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), - DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"), - DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), - DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), - DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), - DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"), - DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"), - DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"), - DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(157, 20, "clkout0_ctrl_out0"), - DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), - DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"), - DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(157, 25, "board_0_ddr0_ck0_out"), - DEV_CLK(157, 40, "mshsi2c_main_0_porscl"), - DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), - DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"), - DEV_CLK(157, 85, "emmcsd8ss_main_0_emmcsdss_io_clk_o"), - DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), - DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), - DEV_CLK(157, 130, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), - DEV_CLK(157, 146, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"), - DEV_CLK(157, 159, "wkup_clkout_sel_io_out0"), - DEV_CLK(157, 160, "wkup_clkout_sel_out0"), - DEV_CLK(157, 161, "gluelogic_hfosc0_clkout"), - DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"), - DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"), - DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), - DEV_CLK(161, 10, "board_0_tck_out"), - DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"), - DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"), - DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), - DEV_CLK(162, 10, "board_0_tck_out"), - DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"), - DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"), - DEV_CLK(170, 2, "board_0_tck_out"), - DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), -}; - -const struct ti_k3_clk_platdata am62ax_clk_platdata = { - .clk_list = clk_list, - .clk_list_cnt = 80, - .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 104, -}; diff --git a/arch/arm/mach-k3/am62ax/dev-data.c b/arch/arm/mach-k3/am62ax/dev-data.c deleted file mode 100644 index abf5d8e91aa..00000000000 --- a/arch/arm/mach-k3/am62ax/dev-data.c +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * AM62AX specific device platform data - * - * This file is auto generated. Please do not hand edit and report any issues - * to Bryan Brattlof . - * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "k3-dev.h" - -static struct ti_psc soc_psc_list[] = { - [0] = PSC(0, 0x04000000), - [1] = PSC(1, 0x00400000), -}; - -static struct ti_pd soc_pd_list[] = { - [0] = PSC_PD(0, &soc_psc_list[1], NULL), - [1] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]), - [2] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[1]), - [3] = PSC_PD(13, &soc_psc_list[1], &soc_pd_list[0]), -}; - -static struct ti_lpsc soc_lpsc_list[] = { - [0] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[0], NULL), - [1] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[5]), - [2] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[6]), - [3] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), - [4] = PSC_LPSC(21, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), - [5] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), - [6] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), - [7] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), - [8] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), - [9] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]), - [10] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[9]), - [11] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[8]), - [12] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[11]), - [13] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[12]), -}; - -static struct ti_dev soc_dev_list[] = { - PSC_DEV(16, &soc_lpsc_list[0]), - PSC_DEV(77, &soc_lpsc_list[0]), - PSC_DEV(61, &soc_lpsc_list[0]), - PSC_DEV(95, &soc_lpsc_list[0]), - PSC_DEV(107, &soc_lpsc_list[0]), - PSC_DEV(178, &soc_lpsc_list[1]), - PSC_DEV(179, &soc_lpsc_list[2]), - PSC_DEV(57, &soc_lpsc_list[3]), - PSC_DEV(58, &soc_lpsc_list[4]), - PSC_DEV(161, &soc_lpsc_list[5]), - PSC_DEV(162, &soc_lpsc_list[6]), - PSC_DEV(75, &soc_lpsc_list[7]), - PSC_DEV(102, &soc_lpsc_list[8]), - PSC_DEV(146, &soc_lpsc_list[8]), - PSC_DEV(166, &soc_lpsc_list[9]), - PSC_DEV(135, &soc_lpsc_list[10]), - PSC_DEV(170, &soc_lpsc_list[11]), - PSC_DEV(177, &soc_lpsc_list[12]), - PSC_DEV(55, &soc_lpsc_list[13]), -}; - -const struct ti_k3_pd_platdata am62ax_pd_platdata = { - .psc = soc_psc_list, - .pd = soc_pd_list, - .lpsc = soc_lpsc_list, - .devs = soc_dev_list, - .num_psc = ARRAY_SIZE(soc_psc_list), - .num_pd = ARRAY_SIZE(soc_pd_list), - .num_lpsc = ARRAY_SIZE(soc_lpsc_list), - .num_devs = ARRAY_SIZE(soc_dev_list), -}; diff --git a/arch/arm/mach-k3/am62x/Makefile b/arch/arm/mach-k3/am62x/Makefile deleted file mode 100644 index d6c876df66d..00000000000 --- a/arch/arm/mach-k3/am62x/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - -obj-y += clk-data.o -obj-y += dev-data.o diff --git a/arch/arm/mach-k3/am62x/clk-data.c b/arch/arm/mach-k3/am62x/clk-data.c deleted file mode 100644 index d7bfed0e031..00000000000 --- a/arch/arm/mach-k3/am62x/clk-data.c +++ /dev/null @@ -1,367 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * AM62X specific clock platform data - * - * This file is auto generated. Please do not hand edit and report any issues - * to Dave Gerlach . - * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include "k3-clk.h" - -static const char * const gluelogic_hfosc0_clkout_parents[] = { - NULL, - NULL, - "osc_24_mhz", - "osc_25_mhz", - "osc_26_mhz", - NULL, -}; - -static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = { - "board_0_mmc0_clklb_out", - "board_0_mmc0_clk_out", -}; - -static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = { - "board_0_mmc1_clklb_out", - "board_0_mmc1_clk_out", -}; - -static const char * const main_ospi_loopback_clk_sel_out0_parents[] = { - "board_0_ospi0_dqs_out", - "board_0_ospi0_lbclko_out", -}; - -static const char * const main_usb0_refclk_sel_out0_parents[] = { - "gluelogic_hfosc0_clkout", - "postdiv4_16ff_main_0_hsdivout8_clk", -}; - -static const char * const main_usb1_refclk_sel_out0_parents[] = { - "gluelogic_hfosc0_clkout", - "postdiv4_16ff_main_0_hsdivout8_clk", -}; - -static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { - "gluelogic_hfosc0_clkout", - "hsdiv4_16fft_main_0_hsdivout0_clk", -}; - -static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { - "gluelogic_hfosc0_clkout", - "hsdiv4_16fft_mcu_0_hsdivout0_clk", -}; - -static const char * const clkout0_ctrl_out0_parents[] = { - "hsdiv4_16fft_main_2_hsdivout1_clk", - "hsdiv4_16fft_main_2_hsdivout1_clk10", -}; - -static const char * const clk_32k_rc_sel_out0_parents[] = { - "gluelogic_rcosc_clk_1p0v_97p65k", - "hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk", - "clk_32k_rc_sel_div_clkout", - "gluelogic_lfosc0_clkout", -}; - -static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = { - "postdiv4_16ff_main_2_hsdivout5_clk", - "postdiv4_16ff_main_0_hsdivout6_clk", - "board_0_cp_gemac_cpts0_rft_clk_out", - NULL, - "board_0_mcu_ext_refclk0_out", - "board_0_ext_refclk1_out", - "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", - "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", -}; - -static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { - "postdiv4_16ff_main_0_hsdivout5_clk", - "hsdiv4_16fft_main_2_hsdivout2_clk", -}; - -static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { - "postdiv4_16ff_main_0_hsdivout5_clk", - "hsdiv4_16fft_main_2_hsdivout2_clk", -}; - -static const char * const main_gtcclk_sel_out0_parents[] = { - "postdiv4_16ff_main_2_hsdivout5_clk", - "postdiv4_16ff_main_0_hsdivout6_clk", - "board_0_cp_gemac_cpts0_rft_clk_out", - NULL, - "board_0_mcu_ext_refclk0_out", - "board_0_ext_refclk1_out", - "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", - "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", -}; - -static const char * const main_ospi_ref_clk_sel_out0_parents[] = { - "hsdiv4_16fft_main_0_hsdivout1_clk", - "postdiv1_16fft_main_1_hsdivout5_clk", -}; - -static const char * const wkup_clkout_sel_out0_parents[] = { - "gluelogic_hfosc0_clkout", - "gluelogic_lfosc0_clkout", - "hsdiv4_16fft_main_0_hsdivout2_clk", - "hsdiv4_16fft_main_1_hsdivout2_clk", - "postdiv4_16ff_main_2_hsdivout9_clk", - "clk_32k_rc_sel_out0", - "gluelogic_rcosc_clkout", - "gluelogic_hfosc0_clkout", -}; - -static const char * const wkup_clksel_out0_parents[] = { - "hsdiv1_16fft_main_15_hsdivout0_clk", - "hsdiv4_16fft_mcu_0_hsdivout0_clk", -}; - -static const char * const main_usart0_fclk_sel_out0_parents[] = { - "usart_programmable_clock_divider_out0", - "hsdiv4_16fft_main_1_hsdivout1_clk", -}; - -static const struct clk_data clk_list[] = { - CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), - CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), - CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), - CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), - CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0), - CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0), - CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0), - CLK_FIXED_RATE("board_0_ddr0_ck0_out", 0, 0), - CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), - CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0), - CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), - CLK_FIXED_RATE("board_0_mmc0_clklb_out", 0, 0), - CLK_FIXED_RATE("board_0_mmc0_clk_out", 0, 0), - CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0), - CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), - CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), - CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), - CLK_FIXED_RATE("board_0_rgmii1_rxc_out", 0, 0), - CLK_FIXED_RATE("board_0_rgmii1_txc_out", 0, 0), - CLK_FIXED_RATE("board_0_rgmii2_rxc_out", 0, 0), - CLK_FIXED_RATE("board_0_rgmii2_txc_out", 0, 0), - CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0), - CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0), - CLK_FIXED_RATE("board_0_tck_out", 0, 0), - CLK_FIXED_RATE("cpsw_3guss_main_0_mdio_mdclk_o", 0, 0), - CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii1_txc_o", 0, 0), - CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii2_txc_o", 0, 0), - CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), - CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0), - CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), - CLK_DIV("hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk", "gluelogic_hfosc0_clkout", 0x4508030, 0, 7, 0, 0), - CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0), - CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0), - CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_PLL("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0), - CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0), - CLK_PLL("pllfracf_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0), - CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0), - CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0), - CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0), - CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), - CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0), - CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), - CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0), - CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0), - CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0), - CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0), - CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0), - CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0), - CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0), - CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0), - CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0), - CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), - CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), - CLK_DIV("hsdiv1_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), - CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), - CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk10", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), - CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), - CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), - CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), - CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), - CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), - CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0), - CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0), - CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), - CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), - CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), - CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0), - CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000), - CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0), - CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0), - CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0), - CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0), - CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0), - CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), - CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0), -}; - -static const struct dev_clk soc_dev_clk_data[] = { - DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"), - DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"), - DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"), - DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"), - DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"), - DEV_CLK(13, 9, "board_0_ext_refclk1_out"), - DEV_CLK(13, 10, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), - DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"), - DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"), - DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"), - DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"), - DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"), - DEV_CLK(13, 19, "board_0_rgmii1_rxc_out"), - DEV_CLK(13, 20, "board_0_rgmii1_txc_out"), - DEV_CLK(13, 22, "board_0_rgmii2_rxc_out"), - DEV_CLK(13, 23, "board_0_rgmii2_txc_out"), - DEV_CLK(13, 25, "hsdiv4_16fft_main_2_hsdivout1_clk"), - DEV_CLK(13, 26, "hsdiv4_16fft_main_2_hsdivout1_clk"), - DEV_CLK(13, 27, "hsdiv4_16fft_main_2_hsdivout1_clk"), - DEV_CLK(13, 28, "board_0_rmii1_ref_clk_out"), - DEV_CLK(13, 29, "board_0_rmii2_ref_clk_out"), - DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), - DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), - DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), - DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"), - DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"), - DEV_CLK(16, 5, "board_0_ext_refclk1_out"), - DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"), - DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"), - DEV_CLK(16, 9, "board_0_ext_refclk1_out"), - DEV_CLK(16, 10, "gluelogic_rcosc_clkout"), - DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(57, 0, "main_emmcsd0_io_clklb_sel_out0"), - DEV_CLK(57, 1, "board_0_mmc0_clklb_out"), - DEV_CLK(57, 2, "board_0_mmc0_clk_out"), - DEV_CLK(57, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(57, 6, "main_emmcsd0_refclk_sel_out0"), - DEV_CLK(57, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), - DEV_CLK(57, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), - DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"), - DEV_CLK(58, 1, "board_0_mmc1_clklb_out"), - DEV_CLK(58, 2, "board_0_mmc1_clk_out"), - DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"), - DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), - DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), - DEV_CLK(61, 0, "main_gtcclk_sel_out0"), - DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"), - DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"), - DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"), - DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"), - DEV_CLK(61, 6, "board_0_ext_refclk1_out"), - DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), - DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(61, 9, "wkup_clksel_out0"), - DEV_CLK(61, 10, "hsdiv1_16fft_main_15_hsdivout0_clk"), - DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), - DEV_CLK(75, 0, "board_0_ospi0_dqs_out"), - DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"), - DEV_CLK(75, 3, "board_0_ospi0_dqs_out"), - DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"), - DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"), - DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"), - DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"), - DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(95, 0, "gluelogic_rcosc_clkout"), - DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"), - DEV_CLK(95, 2, "wkup_clksel_out0"), - DEV_CLK(95, 3, "hsdiv1_16fft_main_15_hsdivout0_clk"), - DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), - DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(102, 1, "board_0_i2c0_scl_out"), - DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"), - DEV_CLK(107, 0, "wkup_clksel_out0"), - DEV_CLK(107, 1, "hsdiv1_16fft_main_15_hsdivout0_clk"), - DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), - DEV_CLK(107, 3, "mshsi2c_wkup_0_porscl"), - DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"), - DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), - DEV_CLK(136, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), - DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), - DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), - DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"), - DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"), - DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"), - DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(157, 20, "clkout0_ctrl_out0"), - DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), - DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk10"), - DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(157, 25, "board_0_ddr0_ck0_out"), - DEV_CLK(157, 40, "mshsi2c_main_0_porscl"), - DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), - DEV_CLK(157, 82, "cpsw_3guss_main_0_mdio_mdclk_o"), - DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"), - DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), - DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), - DEV_CLK(157, 129, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), - DEV_CLK(157, 132, "cpsw_3guss_main_0_rgmii1_txc_o"), - DEV_CLK(157, 135, "cpsw_3guss_main_0_rgmii2_txc_o"), - DEV_CLK(157, 145, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"), - DEV_CLK(157, 158, "wkup_clkout_sel_out0"), - DEV_CLK(157, 159, "gluelogic_hfosc0_clkout"), - DEV_CLK(157, 160, "gluelogic_lfosc0_clkout"), - DEV_CLK(157, 161, "hsdiv4_16fft_main_0_hsdivout2_clk"), - DEV_CLK(157, 162, "hsdiv4_16fft_main_1_hsdivout2_clk"), - DEV_CLK(157, 163, "postdiv4_16ff_main_2_hsdivout9_clk"), - DEV_CLK(157, 164, "clk_32k_rc_sel_out0"), - DEV_CLK(157, 165, "gluelogic_rcosc_clkout"), - DEV_CLK(157, 166, "gluelogic_hfosc0_clkout"), - DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"), - DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"), - DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), - DEV_CLK(161, 10, "board_0_tck_out"), - DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"), - DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"), - DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), - DEV_CLK(162, 10, "board_0_tck_out"), - DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"), - DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(170, 0, "hsdiv0_16fft_main_12_hsdivout0_clk"), - DEV_CLK(170, 1, "board_0_tck_out"), - DEV_CLK(170, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), -}; - -const struct ti_k3_clk_platdata am62x_clk_platdata = { - .clk_list = clk_list, - .clk_list_cnt = 90, - .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 137, -}; diff --git a/arch/arm/mach-k3/am62x/dev-data.c b/arch/arm/mach-k3/am62x/dev-data.c deleted file mode 100644 index 59c95df2a88..00000000000 --- a/arch/arm/mach-k3/am62x/dev-data.c +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * AM62X specific device platform data - * - * This file is auto generated. Please do not hand edit and report any issues - * to Dave Gerlach . - * - * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "k3-dev.h" - -static struct ti_psc soc_psc_list[] = { - [0] = PSC(0, 0x04000000), - [1] = PSC(1, 0x00400000), -}; - -static struct ti_pd soc_pd_list[] = { - [0] = PSC_PD(0, &soc_psc_list[1], NULL), - [1] = PSC_PD(2, &soc_psc_list[1], &soc_pd_list[0]), - [2] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]), - [3] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[2]), - [4] = PSC_PD(5, &soc_psc_list[1], &soc_pd_list[2]), -}; - -static struct ti_lpsc soc_lpsc_list[] = { - [0] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[0], NULL), - [1] = PSC_LPSC(9, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), - [2] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[1]), - [3] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[2]), - [4] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), - [5] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[9]), - [6] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), - [7] = PSC_LPSC(21, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), - [8] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), - [9] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), - [10] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), - [11] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), - [12] = PSC_LPSC(41, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[11]), - [13] = PSC_LPSC(42, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[11]), - [14] = PSC_LPSC(45, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[13]), - [15] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[13]), -}; - -static struct ti_dev soc_dev_list[] = { - PSC_DEV(16, &soc_lpsc_list[0]), - PSC_DEV(77, &soc_lpsc_list[0]), - PSC_DEV(61, &soc_lpsc_list[0]), - PSC_DEV(95, &soc_lpsc_list[0]), - PSC_DEV(107, &soc_lpsc_list[0]), - PSC_DEV(170, &soc_lpsc_list[1]), - PSC_DEV(177, &soc_lpsc_list[2]), - PSC_DEV(55, &soc_lpsc_list[3]), - PSC_DEV(178, &soc_lpsc_list[4]), - PSC_DEV(179, &soc_lpsc_list[5]), - PSC_DEV(57, &soc_lpsc_list[6]), - PSC_DEV(58, &soc_lpsc_list[7]), - PSC_DEV(161, &soc_lpsc_list[8]), - PSC_DEV(162, &soc_lpsc_list[9]), - PSC_DEV(75, &soc_lpsc_list[10]), - PSC_DEV(36, &soc_lpsc_list[11]), - PSC_DEV(102, &soc_lpsc_list[11]), - PSC_DEV(146, &soc_lpsc_list[11]), - PSC_DEV(13, &soc_lpsc_list[12]), - PSC_DEV(166, &soc_lpsc_list[13]), - PSC_DEV(135, &soc_lpsc_list[14]), - PSC_DEV(136, &soc_lpsc_list[15]), -}; - -const struct ti_k3_pd_platdata am62x_pd_platdata = { - .psc = soc_psc_list, - .pd = soc_pd_list, - .lpsc = soc_lpsc_list, - .devs = soc_dev_list, - .num_psc = ARRAY_SIZE(soc_psc_list), - .num_pd = ARRAY_SIZE(soc_pd_list), - .num_lpsc = ARRAY_SIZE(soc_lpsc_list), - .num_devs = ARRAY_SIZE(soc_dev_list), -}; diff --git a/arch/arm/mach-k3/j7200/Makefile b/arch/arm/mach-k3/j7200/Makefile deleted file mode 100644 index 0f91cf4daea..00000000000 --- a/arch/arm/mach-k3/j7200/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ -obj-y += clk-data.o -obj-y += dev-data.o diff --git a/arch/arm/mach-k3/j7200/clk-data.c b/arch/arm/mach-k3/j7200/clk-data.c deleted file mode 100644 index 9b45786a2d4..00000000000 --- a/arch/arm/mach-k3/j7200/clk-data.c +++ /dev/null @@ -1,555 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * J7200 specific clock platform data - * - * This file is auto generated. Please do not hand edit and report any issues - * to Dave Gerlach . - * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include "k3-clk.h" - -static const char * const gluelogic_hfosc0_clkout_parents[] = { - "osc_19_2_mhz", - "osc_20_mhz", - "osc_24_mhz", - "osc_25_mhz", - "osc_26_mhz", - "osc_27_mhz", -}; - -static const char * const mcu_ospi0_iclk_sel_out0_parents[] = { - "board_0_mcu_ospi0_dqs_out", - "fss_mcu_0_ospi_0_ospi_oclk_clk", -}; - -static const char * const wkup_fref_clksel_out0_parents[] = { - "gluelogic_hfosc0_clkout", - "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", -}; - -static const char * const main_pll_hfosc_sel_out1_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = { - "wkup_fref_clksel_out0", - "hsdiv1_16fft_mcu_0_hsdivout0_clk", -}; - -static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = { - "hsdiv4_16fft_mcu_1_hsdivout4_clk", - "hsdiv4_16fft_mcu_2_hsdivout4_clk", -}; - -static const char * const mcuusart_clk_sel_out0_parents[] = { - "hsdiv4_16fft_mcu_1_hsdivout3_clk", - "postdiv2_16fft_main_1_hsdivout5_clk", -}; - -static const char * const wkup_gpio0_clksel_out0_parents[] = { - "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", - "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", - "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", - "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", -}; - -static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = { - "hsdiv4_16fft_mcu_1_hsdivout3_clk", - "gluelogic_hfosc0_clkout", -}; - -static const char * const main_pll_hfosc_sel_out0_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out12_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out14_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out2_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out3_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out4_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out7_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out8_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const usb0_refclk_sel_out0_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const wkup_obsclk_mux_out0_parents[] = { - "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", - NULL, - "hsdiv1_16fft_mcu_0_hsdivout0_clk", - "hsdiv1_16fft_mcu_0_hsdivout0_clk", - "hsdiv4_16fft_mcu_1_hsdivout1_clk", - "hsdiv4_16fft_mcu_1_hsdivout2_clk", - "hsdiv4_16fft_mcu_1_hsdivout3_clk", - "hsdiv4_16fft_mcu_1_hsdivout4_clk", - "hsdiv4_16fft_mcu_2_hsdivout0_clk", - "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", - "hsdiv4_16fft_mcu_2_hsdivout1_clk", - "hsdiv4_16fft_mcu_2_hsdivout2_clk", - "hsdiv4_16fft_mcu_2_hsdivout3_clk", - "hsdiv4_16fft_mcu_2_hsdivout4_clk", - "gluelogic_hfosc0_clkout", - "board_0_wkup_lf_clkin_out", -}; - -static const char * const main_pll4_xref_sel_out0_parents[] = { - "main_pll_hfosc_sel_out4", - "board_0_ext_refclk1_out", -}; - -static const char * const mcu_clkout_mux_out0_parents[] = { - "hsdiv4_16fft_mcu_2_hsdivout0_clk", - "hsdiv4_16fft_mcu_2_hsdivout0_clk", -}; - -static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { - "main_pll_hfosc_sel_out0", - "hsdiv4_16fft_main_0_hsdivout0_clk", -}; - -static const char * const mcu_obsclk_outmux_out0_parents[] = { - "mcu_obsclk_div_out0", - "gluelogic_hfosc0_clkout", -}; - -static const char * const clkout_mux_out0_parents[] = { - "hsdiv4_16fft_main_3_hsdivout0_clk", - "hsdiv4_16fft_main_3_hsdivout0_clk", -}; - -static const char * const emmcsd_refclk_sel_out0_parents[] = { - "hsdiv4_16fft_main_0_hsdivout2_clk", - "hsdiv4_16fft_main_1_hsdivout2_clk", - "hsdiv4_16fft_main_3_hsdivout2_clk", - "hsdiv4_16fft_main_3_hsdivout2_clk", -}; - -static const char * const emmcsd_refclk_sel_out1_parents[] = { - "hsdiv4_16fft_main_0_hsdivout2_clk", - "hsdiv4_16fft_main_1_hsdivout2_clk", - "hsdiv4_16fft_main_3_hsdivout2_clk", - "hsdiv4_16fft_main_3_hsdivout2_clk", -}; - -static const char * const gtc_clk_mux_out0_parents[] = { - "hsdiv4_16fft_main_3_hsdivout1_clk", - "postdiv2_16fft_main_0_hsdivout6_clk", - "board_0_mcu_cpts0_rft_clk_out", - "board_0_cpts0_rft_clk_out", - "board_0_mcu_ext_refclk0_out", - "board_0_ext_refclk1_out", - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - "hsdiv4_16fft_mcu_2_hsdivout1_clk", - "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", -}; - -static const char * const obsclk1_mux_out0_parents[] = { - NULL, - "hsdiv0_16fft_main_8_hsdivout0_clk", - NULL, - NULL, -}; - -static const char * const gpmc_fclk_sel_out0_parents[] = { - "hsdiv4_16fft_main_0_hsdivout3_clk", - "hsdiv4_16fft_main_2_hsdivout1_clk", - "hsdiv4_16fft_main_2_hsdivout1_clk", - "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", -}; - -static const char * const audio_refclko_mux_out0_parents[] = { - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - "hsdiv2_16fft_main_4_hsdivout2_clk", - NULL, - NULL, - NULL, -}; - -static const char * const audio_refclko_mux_out1_parents[] = { - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - "hsdiv2_16fft_main_4_hsdivout2_clk", - NULL, - NULL, - NULL, -}; - -static const char * const obsclk0_mux_out0_parents[] = { - "hsdiv4_16fft_main_0_hsdivout0_clk", - "hsdiv4_16fft_main_1_hsdivout0_clk", - "hsdiv4_16fft_main_2_hsdivout0_clk", - "hsdiv4_16fft_main_3_hsdivout0_clk", - "hsdiv2_16fft_main_4_hsdivout0_clk", - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - "hsdiv0_16fft_main_12_hsdivout0_clk", - "obsclk1_mux_out0", - "hsdiv1_16fft_main_14_hsdivout0_clk", - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", - "board_0_wkup_lf_clkin_out", - "hsdiv4_16fft_main_0_hsdivout0_clk", - "board_0_hfosc1_clk_out", - "gluelogic_hfosc0_clkout", -}; - -static const struct clk_data clk_list[] = { - CLK_FIXED_RATE("osc_27_mhz", 27000000, 0), - CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), - CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), - CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), - CLK_FIXED_RATE("osc_20_mhz", 20000000, 0), - CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0), - CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), - CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0), - CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0), - CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0), - CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0), - CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0), - CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), - CLK_FIXED_RATE("j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0), - CLK_FIXED_RATE("j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32550, 0), - CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0), - CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0), - CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0), - CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000), - CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0), - CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000), - CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000), - CLK_DIV("postdiv2_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), - CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0), - CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666), - CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0), - CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0), - CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), - CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0), - CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0), - CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out14", main_pll_hfosc_sel_out14_parents, 2, 0x430080b8, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out4", main_pll_hfosc_sel_out4_parents, 2, 0x43008090, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0), - CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0), - CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0), - CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), - CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0), - CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), - CLK_FIXED_RATE("board_0_mcu_i2c0_scl_out", 0, 0), - CLK_FIXED_RATE("board_0_wkup_lf_clkin_out", 0, 0), - CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), - CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), - CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01084, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01088, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0, 0), - CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0), - CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0), - CLK_PLL("pllfracf_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0), - CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0), - CLK_PLL("pllfracf_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0), - CLK_PLL("pllfracf_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0), - CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0), - CLK_DIV("postdiv2_16fft_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), - CLK_DIV("postdiv2_16fft_main_1_hsdivout7_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0), - CLK_MUX("wkup_obsclk_mux_out0", wkup_obsclk_mux_out0_parents, 16, 0x43008000, 0, 4, 0), - CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0), - CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), - CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), - CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out1", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c4, 0, 2, 0, 0, 48000000), - CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), - CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0), - CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), - CLK_DIV("hsdiv1_16fft_main_14_hsdivout0_clk", "pllfracf_ssmod_16fft_main_14_foutvcop_clk", 0x68e080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_2_hsdivout0_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_3_hsdivout0_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0), - CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), - CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), - CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0, 0), - CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0), - CLK_PLL("pllfracf_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0), - CLK_MUX("clkout_mux_out0", clkout_mux_out0_parents, 2, 0x108010, 0, 1, 0), - CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0), - CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0), - CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0), - CLK_MUX("obsclk1_mux_out0", obsclk1_mux_out0_parents, 4, 0x108004, 0, 2, 0), - CLK_MUX("gpmc_fclk_sel_out0", gpmc_fclk_sel_out0_parents, 4, 0x1080d0, 0, 2, 0), - CLK_DIV("hsdiv2_16fft_main_4_hsdivout0_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684080, 0, 7, 0, 0), - CLK_DIV("hsdiv2_16fft_main_4_hsdivout2_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684088, 0, 7, 0, 0), - CLK_MUX("audio_refclko_mux_out0", audio_refclko_mux_out0_parents, 32, 0x1082e0, 0, 5, 0), - CLK_MUX("audio_refclko_mux_out1", audio_refclko_mux_out1_parents, 32, 0x1082e4, 0, 5, 0), - CLK_MUX("obsclk0_mux_out0", obsclk0_mux_out0_parents, 32, 0x108000, 0, 5, 0), - CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0, 0), - CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), - CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0), -}; - -static const struct dev_clk soc_dev_clk_data[] = { - DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), - DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), - DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(8, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(8, 5, "hsdiv0_16fft_main_12_hsdivout0_clk"), - DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(30, 1, "board_0_hfosc1_clk_out"), - DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), - DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"), - DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"), - DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"), - DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"), - DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"), - DEV_CLK(30, 10, "board_0_hfosc1_clk_out"), - DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(30, 12, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), - DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(61, 1, "gtc_clk_mux_out0"), - DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"), - DEV_CLK(61, 3, "postdiv2_16fft_main_0_hsdivout6_clk"), - DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"), - DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"), - DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"), - DEV_CLK(61, 7, "board_0_ext_refclk1_out"), - DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), - DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(91, 3, "emmcsd_refclk_sel_out0"), - DEV_CLK(91, 4, "hsdiv4_16fft_main_0_hsdivout2_clk"), - DEV_CLK(91, 5, "hsdiv4_16fft_main_1_hsdivout2_clk"), - DEV_CLK(91, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"), - DEV_CLK(91, 7, "hsdiv4_16fft_main_3_hsdivout2_clk"), - DEV_CLK(92, 0, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), - DEV_CLK(92, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(92, 2, "emmcsd_refclk_sel_out1"), - DEV_CLK(92, 3, "hsdiv4_16fft_main_0_hsdivout2_clk"), - DEV_CLK(92, 4, "hsdiv4_16fft_main_1_hsdivout2_clk"), - DEV_CLK(92, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"), - DEV_CLK(92, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"), - DEV_CLK(102, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), - DEV_CLK(102, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), - DEV_CLK(102, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(102, 5, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), - DEV_CLK(102, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), - DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"), - DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), - DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), - DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(103, 4, "board_0_mcu_ospi0_dqs_out"), - DEV_CLK(103, 5, "mcu_ospi0_iclk_sel_out0"), - DEV_CLK(103, 6, "board_0_mcu_ospi0_dqs_out"), - DEV_CLK(103, 7, "fss_mcu_0_ospi_0_ospi_oclk_clk"), - DEV_CLK(103, 8, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(104, 0, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), - DEV_CLK(104, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(113, 0, "wkup_gpio0_clksel_out0"), - DEV_CLK(113, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(113, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(113, 3, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk"), - DEV_CLK(113, 4, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), - DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(146, 2, "usart_programmable_clock_divider_out0"), - DEV_CLK(146, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(149, 2, "mcuusart_clk_sel_out0"), - DEV_CLK(149, 3, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), - DEV_CLK(149, 4, "postdiv2_16fft_main_1_hsdivout5_clk"), - DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(154, 0, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), - DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"), - DEV_CLK(157, 5, "osbclk0_div_out0"), - DEV_CLK(157, 7, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), - DEV_CLK(157, 14, "mcu_obsclk_outmux_out0"), - DEV_CLK(157, 15, "mcu_obsclk_div_out0"), - DEV_CLK(157, 16, "gluelogic_hfosc0_clkout"), - DEV_CLK(157, 35, "clkout_mux_out0"), - DEV_CLK(157, 36, "hsdiv4_16fft_main_3_hsdivout0_clk"), - DEV_CLK(157, 37, "hsdiv4_16fft_main_3_hsdivout0_clk"), - DEV_CLK(157, 38, "osbclk0_div_out0"), - DEV_CLK(157, 57, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), - DEV_CLK(157, 65, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), - DEV_CLK(157, 69, "mcu_clkout_mux_out0"), - DEV_CLK(157, 70, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), - DEV_CLK(157, 71, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), - DEV_CLK(157, 77, "audio_refclko_mux_out1"), - DEV_CLK(157, 106, "hsdiv2_16fft_main_4_hsdivout2_clk"), - DEV_CLK(157, 110, "fss_mcu_0_ospi_0_ospi_oclk_clk"), - DEV_CLK(157, 114, "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk"), - DEV_CLK(157, 123, "mshsi2c_wkup_0_porscl"), - DEV_CLK(157, 131, "audio_refclko_mux_out0"), - DEV_CLK(157, 160, "hsdiv2_16fft_main_4_hsdivout2_clk"), - DEV_CLK(157, 169, "board_0_mcu_i2c0_scl_out"), - DEV_CLK(157, 177, "k3_pll_ctrl_wrap_main_0_sysclkout_clk"), - DEV_CLK(157, 184, "gpmc_fclk_sel_out0"), - DEV_CLK(157, 187, "fss_mcu_0_ospi_0_ospi_oclk_clk"), - DEV_CLK(157, 192, "osbclk0_div_out0"), - DEV_CLK(157, 193, "hsdiv4_16fft_main_0_hsdivout0_clk"), - DEV_CLK(157, 194, "hsdiv4_16fft_main_1_hsdivout0_clk"), - DEV_CLK(157, 195, "hsdiv4_16fft_main_2_hsdivout0_clk"), - DEV_CLK(157, 196, "hsdiv4_16fft_main_3_hsdivout0_clk"), - DEV_CLK(157, 197, "hsdiv2_16fft_main_4_hsdivout0_clk"), - DEV_CLK(157, 205, "hsdiv0_16fft_main_12_hsdivout0_clk"), - DEV_CLK(157, 206, "obsclk1_mux_out0"), - DEV_CLK(157, 207, "hsdiv1_16fft_main_14_hsdivout0_clk"), - DEV_CLK(157, 220, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), - DEV_CLK(157, 221, "board_0_wkup_lf_clkin_out"), - DEV_CLK(157, 222, "hsdiv4_16fft_main_0_hsdivout0_clk"), - DEV_CLK(157, 223, "board_0_hfosc1_clk_out"), - DEV_CLK(157, 224, "gluelogic_hfosc0_clkout"), - DEV_CLK(197, 0, "board_0_wkup_i2c0_scl_out"), - DEV_CLK(197, 1, "wkup_i2c0_mcupll_bypass_clksel_out0"), - DEV_CLK(197, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), - DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), - DEV_CLK(278, 2, "usart_programmable_clock_divider_out1"), - DEV_CLK(278, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(288, 3, "postdiv2_16fft_main_1_hsdivout7_clk"), - DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(288, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(288, 12, "usb0_refclk_sel_out0"), - DEV_CLK(288, 13, "gluelogic_hfosc0_clkout"), - DEV_CLK(288, 14, "board_0_hfosc1_clk_out"), - DEV_CLK(288, 15, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(288, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), -}; - -const struct ti_k3_clk_platdata j7200_clk_platdata = { - .clk_list = clk_list, - .clk_list_cnt = 109, - .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 129, -}; diff --git a/arch/arm/mach-k3/j7200/dev-data.c b/arch/arm/mach-k3/j7200/dev-data.c deleted file mode 100644 index 8ce6796fd04..00000000000 --- a/arch/arm/mach-k3/j7200/dev-data.c +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * J7200 specific device platform data - * - * This file is auto generated. Please do not hand edit and report any issues - * to Dave Gerlach . - * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "k3-dev.h" - -static struct ti_psc soc_psc_list[] = { - [0] = PSC(0, 0x00400000), - [1] = PSC(1, 0x42000000), -}; - -static struct ti_pd soc_pd_list[] = { - [0] = PSC_PD(0, &soc_psc_list[0], NULL), - [1] = PSC_PD(2, &soc_psc_list[0], &soc_pd_list[5]), - [2] = PSC_PD(14, &soc_psc_list[0], NULL), - [3] = PSC_PD(15, &soc_psc_list[0], &soc_pd_list[2]), - [4] = PSC_PD(16, &soc_psc_list[0], &soc_pd_list[2]), - [5] = PSC_PD(0, &soc_psc_list[1], NULL), -}; - -static struct ti_lpsc soc_lpsc_list[] = { - [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), - [1] = PSC_LPSC(9, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[14]), - [2] = PSC_LPSC(14, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[3]), - [3] = PSC_LPSC(15, &soc_psc_list[0], &soc_pd_list[0], NULL), - [4] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], NULL), - [5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], NULL), - [6] = PSC_LPSC(25, &soc_psc_list[0], &soc_pd_list[0], NULL), - [7] = PSC_LPSC(54, &soc_psc_list[0], &soc_pd_list[1], NULL), - [8] = PSC_LPSC(78, &soc_psc_list[0], &soc_pd_list[2], NULL), - [9] = PSC_LPSC(79, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]), - [10] = PSC_LPSC(80, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]), - [11] = PSC_LPSC(81, &soc_psc_list[0], &soc_pd_list[4], &soc_lpsc_list[8]), - [12] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[5], NULL), - [13] = PSC_LPSC(3, &soc_psc_list[1], &soc_pd_list[5], NULL), - [14] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[5], NULL), - [15] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[5], NULL), - [16] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[5], NULL), -}; - -static struct ti_dev soc_dev_list[] = { - PSC_DEV(30, &soc_lpsc_list[0]), - PSC_DEV(35, &soc_lpsc_list[0]), - PSC_DEV(61, &soc_lpsc_list[1]), - PSC_DEV(90, &soc_lpsc_list[2]), - PSC_DEV(8, &soc_lpsc_list[3]), - PSC_DEV(288, &soc_lpsc_list[4]), - PSC_DEV(92, &soc_lpsc_list[5]), - PSC_DEV(91, &soc_lpsc_list[6]), - PSC_DEV(146, &soc_lpsc_list[7]), - PSC_DEV(278, &soc_lpsc_list[7]), - PSC_DEV(4, &soc_lpsc_list[8]), - PSC_DEV(4, &soc_lpsc_list[9]), - PSC_DEV(202, &soc_lpsc_list[10]), - PSC_DEV(203, &soc_lpsc_list[11]), - PSC_DEV(102, &soc_lpsc_list[12]), - PSC_DEV(103, &soc_lpsc_list[12]), - PSC_DEV(104, &soc_lpsc_list[12]), - PSC_DEV(154, &soc_lpsc_list[12]), - PSC_DEV(149, &soc_lpsc_list[12]), - PSC_DEV(113, &soc_lpsc_list[13]), - PSC_DEV(197, &soc_lpsc_list[13]), - PSC_DEV(103, &soc_lpsc_list[14]), - PSC_DEV(104, &soc_lpsc_list[15]), - PSC_DEV(102, &soc_lpsc_list[16]), -}; - -const struct ti_k3_pd_platdata j7200_pd_platdata = { - .psc = soc_psc_list, - .pd = soc_pd_list, - .lpsc = soc_lpsc_list, - .devs = soc_dev_list, - .num_psc = ARRAY_SIZE(soc_psc_list), - .num_pd = ARRAY_SIZE(soc_pd_list), - .num_lpsc = ARRAY_SIZE(soc_lpsc_list), - .num_devs = ARRAY_SIZE(soc_dev_list), -}; diff --git a/arch/arm/mach-k3/j721e/Makefile b/arch/arm/mach-k3/j721e/Makefile deleted file mode 100644 index 0f91cf4daea..00000000000 --- a/arch/arm/mach-k3/j721e/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ -obj-y += clk-data.o -obj-y += dev-data.o diff --git a/arch/arm/mach-k3/j721e/clk-data.c b/arch/arm/mach-k3/j721e/clk-data.c deleted file mode 100644 index e4511092c86..00000000000 --- a/arch/arm/mach-k3/j721e/clk-data.c +++ /dev/null @@ -1,789 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * J721E specific clock platform data - * - * This file is auto generated. Please do not hand edit and report any issues - * to Dave Gerlach . - * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include "k3-clk.h" - -static const char * const gluelogic_hfosc0_clkout_parents[] = { - "osc_19_2_mhz", - "osc_20_mhz", - "osc_24_mhz", - "osc_25_mhz", - "osc_26_mhz", - "osc_27_mhz", -}; - -static const char * const mcu_ospi0_iclk_sel_out0_parents[] = { - "board_0_mcu_ospi0_dqs_out", - "fss_mcu_0_ospi_0_ospi_oclk_clk", -}; - -static const char * const mcu_ospi1_iclk_sel_out0_parents[] = { - "board_0_mcu_ospi1_dqs_out", - "fss_mcu_0_ospi_1_ospi_oclk_clk", -}; - -static const char * const wkup_fref_clksel_out0_parents[] = { - "gluelogic_hfosc0_clkout", - "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", -}; - -static const char * const main_pll_hfosc_sel_out1_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = { - "wkup_fref_clksel_out0", - "hsdiv1_16fft_mcu_0_hsdivout0_clk", -}; - -static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = { - "hsdiv4_16fft_mcu_1_hsdivout4_clk", - "hsdiv4_16fft_mcu_2_hsdivout4_clk", -}; - -static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = { - "hsdiv4_16fft_mcu_1_hsdivout4_clk", - "hsdiv4_16fft_mcu_2_hsdivout4_clk", -}; - -static const char * const mcuusart_clk_sel_out0_parents[] = { - "hsdiv4_16fft_mcu_1_hsdivout3_clk", - "postdiv3_16fft_main_1_hsdivout5_clk", -}; - -static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = { - "hsdiv4_16fft_mcu_1_hsdivout3_clk", - "gluelogic_hfosc0_clkout", -}; - -static const char * const main_pll25_hfosc_sel_out0_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out0_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out12_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out13_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out14_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out15_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out16_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out17_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out18_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out19_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out2_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out23_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out3_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out4_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out5_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out6_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out7_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out8_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const usb0_refclk_sel_out0_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const usb1_refclk_sel_out0_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const wkup_obsclk_mux_out0_parents[] = { - "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", - NULL, - "hsdiv1_16fft_mcu_0_hsdivout0_clk", - "hsdiv1_16fft_mcu_0_hsdivout0_clk", - "hsdiv4_16fft_mcu_1_hsdivout1_clk", - "hsdiv4_16fft_mcu_1_hsdivout2_clk", - "hsdiv4_16fft_mcu_1_hsdivout3_clk", - "hsdiv4_16fft_mcu_1_hsdivout4_clk", - "hsdiv4_16fft_mcu_2_hsdivout0_clk", - "j7_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", - "hsdiv4_16fft_mcu_2_hsdivout1_clk", - "hsdiv4_16fft_mcu_2_hsdivout2_clk", - "hsdiv4_16fft_mcu_2_hsdivout3_clk", - "hsdiv4_16fft_mcu_2_hsdivout4_clk", - "gluelogic_hfosc0_clkout", - "gluelogic_lpxosc_clkout", -}; - -static const char * const main_pll15_xref_sel_out0_parents[] = { - "main_pll_hfosc_sel_out15", - "board_0_ext_refclk1_out", -}; - -static const char * const main_pll24_hfosc_sel_out0_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_mlb0_mlbcp_out", -}; - -static const char * const main_pll4_xref_sel_out0_parents[] = { - "main_pll_hfosc_sel_out4", - "board_0_ext_refclk1_out", -}; - -static const char * const mcu_clkout_mux_out0_parents[] = { - "hsdiv4_16fft_mcu_2_hsdivout0_clk", - "hsdiv4_16fft_mcu_2_hsdivout0_clk", -}; - -static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { - "main_pll_hfosc_sel_out0", - "hsdiv4_16fft_main_0_hsdivout0_clk", -}; - -static const char * const mcu_obsclk_outmux_out0_parents[] = { - "mcu_obsclk_div_out0", - "gluelogic_hfosc0_clkout", -}; - -static const char * const obsclk1_mux_out0_parents[] = { - "hsdiv0_16fft_main_7_hsdivout0_clk", - "hsdiv0_16fft_main_8_hsdivout0_clk", - "hsdiv3_16fft_main_13_hsdivout0_clk", - NULL, -}; - -static const char * const clkout_mux_out0_parents[] = { - "hsdiv4_16fft_main_3_hsdivout0_clk", - "hsdiv4_16fft_main_3_hsdivout0_clk", -}; - -static const char * const emmcsd_refclk_sel_out0_parents[] = { - "hsdiv4_16fft_main_0_hsdivout2_clk", - "hsdiv4_16fft_main_1_hsdivout2_clk", - "hsdiv4_16fft_main_2_hsdivout2_clk", - "hsdiv4_16fft_main_3_hsdivout2_clk", -}; - -static const char * const emmcsd_refclk_sel_out1_parents[] = { - "hsdiv4_16fft_main_0_hsdivout2_clk", - "hsdiv4_16fft_main_1_hsdivout2_clk", - "hsdiv4_16fft_main_2_hsdivout2_clk", - "hsdiv4_16fft_main_3_hsdivout2_clk", -}; - -static const char * const gtc_clk_mux_out0_parents[] = { - "hsdiv4_16fft_main_3_hsdivout1_clk", - "postdiv3_16fft_main_0_hsdivout6_clk", - "board_0_mcu_cpts0_rft_clk_out", - "board_0_cpts0_rft_clk_out", - "board_0_mcu_ext_refclk0_out", - "board_0_ext_refclk1_out", - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - "hsdiv4_16fft_mcu_2_hsdivout1_clk", - "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", -}; - -static const char * const gpmc_fclk_sel_out0_parents[] = { - "hsdiv4_16fft_main_0_hsdivout3_clk", - "hsdiv4_16fft_main_2_hsdivout1_clk", - "hsdiv4_16fft_main_2_hsdivout1_clk", - "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", -}; - -static const char * const mcasp_ahclko_mux_out0_parents[] = { - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - "hsdiv3_16fft_main_4_hsdivout2_clk", - "hsdiv3_16fft_main_15_hsdivout2_clk", - NULL, - NULL, - "board_0_audio_ext_refclk0_out", -}; - -static const char * const mcasp_ahclko_mux_out1_parents[] = { - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - "hsdiv3_16fft_main_4_hsdivout2_clk", - "hsdiv3_16fft_main_15_hsdivout2_clk", - NULL, - NULL, - "board_0_audio_ext_refclk1_out", -}; - -static const char * const mcasp_ahclko_mux_out2_parents[] = { - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - "hsdiv3_16fft_main_4_hsdivout2_clk", - "hsdiv3_16fft_main_15_hsdivout2_clk", - NULL, - NULL, - "board_0_audio_ext_refclk2_out", -}; - -static const char * const mcasp_ahclko_mux_out3_parents[] = { - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - "hsdiv3_16fft_main_4_hsdivout2_clk", - "hsdiv3_16fft_main_15_hsdivout2_clk", - NULL, - NULL, - "board_0_audio_ext_refclk3_out", -}; - -static const char * const obsclk0_mux_out0_parents[] = { - "hsdiv4_16fft_main_0_hsdivout0_clk", - "hsdiv4_16fft_main_1_hsdivout0_clk", - "hsdiv4_16fft_main_2_hsdivout0_clk", - "hsdiv4_16fft_main_3_hsdivout0_clk", - "hsdiv3_16fft_main_4_hsdivout0_clk", - "hsdiv3_16fft_main_5_hsdivout0_clk", - "hsdiv0_16fft_main_6_hsdivout0_clk", - NULL, - NULL, - NULL, - NULL, - NULL, - "hsdiv0_16fft_main_12_hsdivout0_clk", - "obsclk1_mux_out0", - "hsdiv1_16fft_main_14_hsdivout0_clk", - "hsdiv3_16fft_main_15_hsdivout0_clk", - "hsdiv1_16fft_main_16_hsdivout0_clk", - "hsdiv1_16fft_main_17_hsdivout0_clk", - "hsdiv1_16fft_main_18_hsdivout0_clk", - "hsdiv1_16fft_main_19_hsdivout0_clk", - NULL, - NULL, - NULL, - "hsdiv1_16fft_main_23_hsdivout0_clk", - "hsdiv0_16fft_main_24_hsdivout0_clk", - "hsdiv1_16fft_main_25_hsdivout0_clk", - NULL, - "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", - "gluelogic_lpxosc_clkout", - "hsdiv4_16fft_main_0_hsdivout0_clk", - "board_0_hfosc1_clk_out", - "gluelogic_hfosc0_clkout", -}; - -static const struct clk_data clk_list[] = { - CLK_FIXED_RATE("osc_27_mhz", 27000000, 0), - CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), - CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), - CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), - CLK_FIXED_RATE("osc_20_mhz", 20000000, 0), - CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0), - CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), - CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0), - CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0), - CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0), - CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0), - CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0), - CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0), - CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), - CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0), - CLK_FIXED_RATE("j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0), - CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0), - CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 2, 0x40f08034, 4, 1, 0), - CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0), - CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0), - CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000), - CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_PLL("pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0), - CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000), - CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000), - CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), - CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0), - CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666), - CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0), - CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0), - CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), - CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0), - CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0), - CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0), - CLK_FIXED_RATE("gluelogic_lpxosc_clkout", 32768, 0), - CLK_MUX("main_pll25_hfosc_sel_out0", main_pll25_hfosc_sel_out0_parents, 2, 0x430080e4, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out13", main_pll_hfosc_sel_out13_parents, 2, 0x430080b4, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out14", main_pll_hfosc_sel_out14_parents, 2, 0x430080b8, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out15", main_pll_hfosc_sel_out15_parents, 2, 0x430080bc, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out16", main_pll_hfosc_sel_out16_parents, 2, 0x430080c0, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out17", main_pll_hfosc_sel_out17_parents, 2, 0x430080c4, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out18", main_pll_hfosc_sel_out18_parents, 2, 0x430080c8, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out19", main_pll_hfosc_sel_out19_parents, 2, 0x430080cc, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out23", main_pll_hfosc_sel_out23_parents, 2, 0x430080dc, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out4", main_pll_hfosc_sel_out4_parents, 2, 0x43008090, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out5", main_pll_hfosc_sel_out5_parents, 2, 0x43008094, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out6", main_pll_hfosc_sel_out6_parents, 2, 0x43008098, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0), - CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0), - CLK_MUX("usb1_refclk_sel_out0", usb1_refclk_sel_out0_parents, 2, 0x1080e4, 0, 1, 0), - CLK_FIXED_RATE("board_0_audio_ext_refclk0_out", 0, 0), - CLK_FIXED_RATE("board_0_audio_ext_refclk1_out", 0, 0), - CLK_FIXED_RATE("board_0_audio_ext_refclk2_out", 0, 0), - CLK_FIXED_RATE("board_0_audio_ext_refclk3_out", 0, 0), - CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0), - CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), - CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0), - CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), - CLK_FIXED_RATE("board_0_mlb0_mlbcp_out", 0, 0), - CLK_FIXED_RATE("ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck", 0, 0), - CLK_FIXED_RATE("ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck_n", 0, 0), - CLK_FIXED_RATE("emmc8ss_16ffc_main_0_emmcss_io_clk", 0, 0), - CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), - CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), - CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01084, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01088, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0, 0), - CLK_FIXED_RATE("j7_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32000, 0), - CLK_PLL("pllfrac2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0), - CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_PLL("pllfrac2_ssmod_16fft_main_13_foutvcop_clk", "main_pll_hfosc_sel_out13", 0x68d000, 0), - CLK_PLL("pllfrac2_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0), - CLK_PLL("pllfrac2_ssmod_16fft_main_16_foutvcop_clk", "main_pll_hfosc_sel_out16", 0x690000, 0), - CLK_PLL("pllfrac2_ssmod_16fft_main_17_foutvcop_clk", "main_pll_hfosc_sel_out17", 0x691000, 0), - CLK_PLL("pllfrac2_ssmod_16fft_main_18_foutvcop_clk", "main_pll_hfosc_sel_out18", 0x692000, 0), - CLK_PLL("pllfrac2_ssmod_16fft_main_19_foutvcop_clk", "main_pll_hfosc_sel_out19", 0x693000, 0), - CLK_PLL("pllfrac2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0), - CLK_PLL("pllfrac2_ssmod_16fft_main_23_foutvcop_clk", "main_pll_hfosc_sel_out23", 0x697000, 0), - CLK_PLL("pllfrac2_ssmod_16fft_main_25_foutvcop_clk", "main_pll25_hfosc_sel_out0", 0x699000, 0), - CLK_PLL("pllfrac2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0), - CLK_PLL("pllfrac2_ssmod_16fft_main_5_foutvcop_clk", "main_pll_hfosc_sel_out5", 0x685000, 0), - CLK_PLL("pllfrac2_ssmod_16fft_main_6_foutvcop_clk", "main_pll_hfosc_sel_out6", 0x686000, 0), - CLK_PLL("pllfrac2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0), - CLK_PLL("pllfrac2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0), - CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0), - CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), - CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0), - CLK_MUX("wkup_obsclk_mux_out0", wkup_obsclk_mux_out0_parents, 16, 0x43008000, 0, 4, 0), - CLK_MUX("main_pll15_xref_sel_out0", main_pll15_xref_sel_out0_parents, 2, 0x430080bc, 4, 1, 0), - CLK_MUX("main_pll24_hfosc_sel_out0", main_pll24_hfosc_sel_out0_parents, 2, 0x430080e0, 0, 1, 0), - CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0), - CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), - CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), - CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out2", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c8, 0, 2, 0, 0, 48000000), - CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), - CLK_DIV("hsdiv0_16fft_main_6_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_6_foutvcop_clk", 0x686080, 0, 7, 0, 0), - CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0), - CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), - CLK_DIV("hsdiv1_16fft_main_14_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_14_foutvcop_clk", 0x68e080, 0, 7, 0, 0), - CLK_DIV("hsdiv1_16fft_main_16_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_16_foutvcop_clk", 0x690080, 0, 7, 0, 0), - CLK_DIV("hsdiv1_16fft_main_17_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_17_foutvcop_clk", 0x691080, 0, 7, 0, 0), - CLK_DIV("hsdiv1_16fft_main_18_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_18_foutvcop_clk", 0x692080, 0, 7, 0, 0), - CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0, 0), - CLK_DIV("hsdiv1_16fft_main_23_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_23_foutvcop_clk", 0x697080, 0, 7, 0, 0), - CLK_DIV("hsdiv1_16fft_main_25_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_25_foutvcop_clk", 0x699080, 0, 7, 0, 0), - CLK_DIV("hsdiv3_16fft_main_13_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_13_foutvcop_clk", 0x68d080, 0, 7, 0, 0), - CLK_DIV("hsdiv3_16fft_main_5_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_5_foutvcop_clk", 0x685080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_2_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_3_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0), - CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), - CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), - CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0, 0), - CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0), - CLK_MUX("obsclk1_mux_out0", obsclk1_mux_out0_parents, 4, 0x108004, 0, 2, 0), - CLK_PLL("pllfrac2_ssmod_16fft_main_15_foutvcop_clk", "main_pll15_xref_sel_out0", 0x68f000, 0), - CLK_PLL("pllfrac2_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0), - CLK_MUX("clkout_mux_out0", clkout_mux_out0_parents, 2, 0x108010, 0, 1, 0), - CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0), - CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0), - CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0), - CLK_MUX("gpmc_fclk_sel_out0", gpmc_fclk_sel_out0_parents, 4, 0x1080d0, 0, 2, 0), - CLK_DIV("hsdiv0_16fft_main_24_hsdivout0_clk", "plldeskew_16fft_main_24_foutp_clk", 0x698080, 0, 0, 0, 0), - CLK_DIV("hsdiv3_16fft_main_15_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0), - CLK_DIV("hsdiv3_16fft_main_15_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_15_foutvcop_clk", 0x68f088, 0, 7, 0, 0), - CLK_DIV("hsdiv3_16fft_main_4_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_4_foutvcop_clk", 0x684080, 0, 7, 0, 0), - CLK_DIV("hsdiv3_16fft_main_4_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_4_foutvcop_clk", 0x684088, 0, 7, 0, 0), - CLK_MUX("mcasp_ahclko_mux_out0", mcasp_ahclko_mux_out0_parents, 33, 0x1082e0, 0, 5, 0), - CLK_MUX("mcasp_ahclko_mux_out1", mcasp_ahclko_mux_out1_parents, 33, 0x1082e4, 0, 5, 0), - CLK_MUX("mcasp_ahclko_mux_out2", mcasp_ahclko_mux_out2_parents, 33, 0x1082e8, 0, 5, 0), - CLK_MUX("mcasp_ahclko_mux_out3", mcasp_ahclko_mux_out3_parents, 33, 0x1082ec, 0, 5, 0), - CLK_MUX("obsclk0_mux_out0", obsclk0_mux_out0_parents, 32, 0x108000, 0, 5, 0), - CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0, 0), - CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), - CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0), -}; - -static const struct dev_clk soc_dev_clk_data[] = { - DEV_CLK(4, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), - DEV_CLK(4, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), - DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(30, 1, "board_0_hfosc1_clk_out"), - DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), - DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"), - DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"), - DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"), - DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"), - DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"), - DEV_CLK(30, 10, "board_0_hfosc1_clk_out"), - DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(30, 12, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), - DEV_CLK(47, 0, "hsdiv0_16fft_main_7_hsdivout0_clk"), - DEV_CLK(47, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(47, 2, "hsdiv0_16fft_main_12_hsdivout0_clk"), - DEV_CLK(47, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(61, 1, "gtc_clk_mux_out0"), - DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"), - DEV_CLK(61, 3, "postdiv3_16fft_main_0_hsdivout6_clk"), - DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"), - DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"), - DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"), - DEV_CLK(61, 7, "board_0_ext_refclk1_out"), - DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), - DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(91, 1, "emmcsd_refclk_sel_out0"), - DEV_CLK(91, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"), - DEV_CLK(91, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"), - DEV_CLK(91, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), - DEV_CLK(91, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"), - DEV_CLK(92, 0, "emmcsd_refclk_sel_out1"), - DEV_CLK(92, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), - DEV_CLK(92, 2, "hsdiv4_16fft_main_1_hsdivout2_clk"), - DEV_CLK(92, 3, "hsdiv4_16fft_main_2_hsdivout2_clk"), - DEV_CLK(92, 4, "hsdiv4_16fft_main_3_hsdivout2_clk"), - DEV_CLK(92, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(92, 6, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), - DEV_CLK(102, 0, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), - DEV_CLK(102, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), - DEV_CLK(102, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(102, 3, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), - DEV_CLK(102, 4, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), - DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"), - DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), - DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), - DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(103, 4, "mcu_ospi0_iclk_sel_out0"), - DEV_CLK(103, 5, "board_0_mcu_ospi0_dqs_out"), - DEV_CLK(103, 6, "fss_mcu_0_ospi_0_ospi_oclk_clk"), - DEV_CLK(103, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(103, 8, "board_0_mcu_ospi0_dqs_out"), - DEV_CLK(104, 0, "mcu_ospi_ref_clk_sel_out1"), - DEV_CLK(104, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), - DEV_CLK(104, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), - DEV_CLK(104, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(104, 4, "mcu_ospi1_iclk_sel_out0"), - DEV_CLK(104, 5, "board_0_mcu_ospi1_dqs_out"), - DEV_CLK(104, 6, "fss_mcu_0_ospi_1_ospi_oclk_clk"), - DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(104, 8, "board_0_mcu_ospi1_dqs_out"), - DEV_CLK(113, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(146, 0, "usart_programmable_clock_divider_out0"), - DEV_CLK(146, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(149, 0, "mcuusart_clk_sel_out0"), - DEV_CLK(149, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), - DEV_CLK(149, 2, "postdiv3_16fft_main_1_hsdivout5_clk"), - DEV_CLK(149, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(154, 0, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), - DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"), - DEV_CLK(157, 18, "fss_mcu_0_ospi_0_ospi_oclk_clk"), - DEV_CLK(157, 19, "fss_mcu_0_ospi_0_ospi_oclk_clk"), - DEV_CLK(157, 21, "fss_mcu_0_ospi_1_ospi_oclk_clk"), - DEV_CLK(157, 22, "fss_mcu_0_ospi_1_ospi_oclk_clk"), - DEV_CLK(157, 42, "mshsi2c_wkup_0_porscl"), - DEV_CLK(157, 50, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), - DEV_CLK(157, 51, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), - DEV_CLK(157, 91, "ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck"), - DEV_CLK(157, 92, "ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck_n"), - DEV_CLK(157, 99, "emmc8ss_16ffc_main_0_emmcss_io_clk"), - DEV_CLK(157, 100, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), - DEV_CLK(157, 104, "gpmc_fclk_sel_out0"), - DEV_CLK(157, 109, "hsdiv1_16fft_main_19_hsdivout0_clk"), - DEV_CLK(157, 111, "hsdiv1_16fft_main_23_hsdivout0_clk"), - DEV_CLK(157, 113, "osbclk0_div_out0"), - DEV_CLK(157, 114, "hsdiv4_16fft_main_0_hsdivout0_clk"), - DEV_CLK(157, 115, "hsdiv4_16fft_main_1_hsdivout0_clk"), - DEV_CLK(157, 116, "hsdiv4_16fft_main_2_hsdivout0_clk"), - DEV_CLK(157, 117, "hsdiv4_16fft_main_3_hsdivout0_clk"), - DEV_CLK(157, 118, "hsdiv3_16fft_main_4_hsdivout0_clk"), - DEV_CLK(157, 119, "hsdiv3_16fft_main_5_hsdivout0_clk"), - DEV_CLK(157, 120, "hsdiv0_16fft_main_6_hsdivout0_clk"), - DEV_CLK(157, 126, "hsdiv0_16fft_main_12_hsdivout0_clk"), - DEV_CLK(157, 127, "obsclk1_mux_out0"), - DEV_CLK(157, 128, "hsdiv1_16fft_main_14_hsdivout0_clk"), - DEV_CLK(157, 129, "hsdiv3_16fft_main_15_hsdivout0_clk"), - DEV_CLK(157, 130, "hsdiv1_16fft_main_16_hsdivout0_clk"), - DEV_CLK(157, 131, "hsdiv1_16fft_main_17_hsdivout0_clk"), - DEV_CLK(157, 132, "hsdiv1_16fft_main_18_hsdivout0_clk"), - DEV_CLK(157, 133, "hsdiv1_16fft_main_19_hsdivout0_clk"), - DEV_CLK(157, 137, "hsdiv1_16fft_main_23_hsdivout0_clk"), - DEV_CLK(157, 138, "hsdiv0_16fft_main_24_hsdivout0_clk"), - DEV_CLK(157, 139, "hsdiv1_16fft_main_25_hsdivout0_clk"), - DEV_CLK(157, 141, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), - DEV_CLK(157, 142, "gluelogic_lpxosc_clkout"), - DEV_CLK(157, 143, "hsdiv4_16fft_main_0_hsdivout0_clk"), - DEV_CLK(157, 144, "board_0_hfosc1_clk_out"), - DEV_CLK(157, 145, "gluelogic_hfosc0_clkout"), - DEV_CLK(157, 146, "obsclk1_mux_out0"), - DEV_CLK(157, 147, "hsdiv0_16fft_main_7_hsdivout0_clk"), - DEV_CLK(157, 148, "hsdiv0_16fft_main_8_hsdivout0_clk"), - DEV_CLK(157, 149, "hsdiv3_16fft_main_13_hsdivout0_clk"), - DEV_CLK(157, 152, "mcu_obsclk_outmux_out0"), - DEV_CLK(157, 153, "mcu_obsclk_div_out0"), - DEV_CLK(157, 154, "gluelogic_hfosc0_clkout"), - DEV_CLK(157, 169, "k3_pll_ctrl_wrap_main_0_sysclkout_clk"), - DEV_CLK(157, 170, "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk"), - DEV_CLK(157, 172, "clkout_mux_out0"), - DEV_CLK(157, 173, "hsdiv4_16fft_main_3_hsdivout0_clk"), - DEV_CLK(157, 174, "hsdiv4_16fft_main_3_hsdivout0_clk"), - DEV_CLK(157, 175, "mcu_clkout_mux_out0"), - DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), - DEV_CLK(157, 177, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), - DEV_CLK(157, 301, "mcasp_ahclko_mux_out0"), - DEV_CLK(157, 330, "hsdiv3_16fft_main_4_hsdivout2_clk"), - DEV_CLK(157, 331, "hsdiv3_16fft_main_15_hsdivout2_clk"), - DEV_CLK(157, 334, "board_0_audio_ext_refclk0_out"), - DEV_CLK(157, 336, "mcasp_ahclko_mux_out1"), - DEV_CLK(157, 365, "hsdiv3_16fft_main_4_hsdivout2_clk"), - DEV_CLK(157, 366, "hsdiv3_16fft_main_15_hsdivout2_clk"), - DEV_CLK(157, 369, "board_0_audio_ext_refclk1_out"), - DEV_CLK(157, 371, "mcasp_ahclko_mux_out2"), - DEV_CLK(157, 400, "hsdiv3_16fft_main_4_hsdivout2_clk"), - DEV_CLK(157, 401, "hsdiv3_16fft_main_15_hsdivout2_clk"), - DEV_CLK(157, 404, "board_0_audio_ext_refclk2_out"), - DEV_CLK(157, 406, "mcasp_ahclko_mux_out3"), - DEV_CLK(157, 435, "hsdiv3_16fft_main_4_hsdivout2_clk"), - DEV_CLK(157, 436, "hsdiv3_16fft_main_15_hsdivout2_clk"), - DEV_CLK(157, 439, "board_0_audio_ext_refclk3_out"), - DEV_CLK(197, 0, "wkup_i2c0_mcupll_bypass_clksel_out0"), - DEV_CLK(197, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), - DEV_CLK(197, 2, "gluelogic_hfosc0_clkout"), - DEV_CLK(197, 3, "board_0_wkup_i2c0_scl_out"), - DEV_CLK(197, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), - DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), - DEV_CLK(279, 0, "usart_programmable_clock_divider_out2"), - DEV_CLK(279, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(288, 3, "postdiv3_16fft_main_1_hsdivout7_clk"), - DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(288, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(288, 15, "usb0_refclk_sel_out0"), - DEV_CLK(288, 16, "gluelogic_hfosc0_clkout"), - DEV_CLK(288, 17, "board_0_hfosc1_clk_out"), - DEV_CLK(288, 18, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(288, 19, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(289, 3, "postdiv3_16fft_main_1_hsdivout7_clk"), - DEV_CLK(289, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(289, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(289, 15, "usb1_refclk_sel_out0"), - DEV_CLK(289, 16, "gluelogic_hfosc0_clkout"), - DEV_CLK(289, 17, "board_0_hfosc1_clk_out"), - DEV_CLK(289, 18, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(289, 19, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), -}; - -const struct ti_k3_clk_platdata j721e_clk_platdata = { - .clk_list = clk_list, - .clk_list_cnt = 157, - .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 173, -}; diff --git a/arch/arm/mach-k3/j721e/dev-data.c b/arch/arm/mach-k3/j721e/dev-data.c deleted file mode 100644 index b0adb1857be..00000000000 --- a/arch/arm/mach-k3/j721e/dev-data.c +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * J721E specific device platform data - * - * This file is auto generated. Please do not hand edit and report any issues - * to Dave Gerlach . - * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "k3-dev.h" - -static struct ti_psc soc_psc_list[] = { - [0] = PSC(0, 0x00400000), - [1] = PSC(1, 0x42000000), -}; - -static struct ti_pd soc_pd_list[] = { - [0] = PSC_PD(0, &soc_psc_list[0], NULL), - [1] = PSC_PD(14, &soc_psc_list[0], NULL), - [2] = PSC_PD(15, &soc_psc_list[0], &soc_pd_list[1]), - [3] = PSC_PD(16, &soc_psc_list[0], &soc_pd_list[1]), - [4] = PSC_PD(0, &soc_psc_list[1], NULL), -}; - -static struct ti_lpsc soc_lpsc_list[] = { - [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), - [1] = PSC_LPSC(7, &soc_psc_list[0], &soc_pd_list[0], NULL), - [2] = PSC_LPSC(14, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[3]), - [3] = PSC_LPSC(15, &soc_psc_list[0], &soc_pd_list[0], NULL), - [4] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], NULL), - [5] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], NULL), - [6] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], NULL), - [7] = PSC_LPSC(25, &soc_psc_list[0], &soc_pd_list[0], NULL), - [8] = PSC_LPSC(78, &soc_psc_list[0], &soc_pd_list[1], NULL), - [9] = PSC_LPSC(80, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]), - [10] = PSC_LPSC(81, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]), - [11] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[4], NULL), - [12] = PSC_LPSC(3, &soc_psc_list[1], &soc_pd_list[4], NULL), - [13] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[4], NULL), - [14] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[4], NULL), - [15] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[4], NULL), -}; - -static struct ti_dev soc_dev_list[] = { - PSC_DEV(30, &soc_lpsc_list[0]), - PSC_DEV(61, &soc_lpsc_list[0]), - PSC_DEV(146, &soc_lpsc_list[1]), - PSC_DEV(279, &soc_lpsc_list[1]), - PSC_DEV(90, &soc_lpsc_list[2]), - PSC_DEV(47, &soc_lpsc_list[3]), - PSC_DEV(288, &soc_lpsc_list[4]), - PSC_DEV(289, &soc_lpsc_list[5]), - PSC_DEV(92, &soc_lpsc_list[6]), - PSC_DEV(91, &soc_lpsc_list[7]), - PSC_DEV(4, &soc_lpsc_list[8]), - PSC_DEV(202, &soc_lpsc_list[9]), - PSC_DEV(203, &soc_lpsc_list[10]), - PSC_DEV(35, &soc_lpsc_list[11]), - PSC_DEV(102, &soc_lpsc_list[11]), - PSC_DEV(103, &soc_lpsc_list[11]), - PSC_DEV(104, &soc_lpsc_list[11]), - PSC_DEV(154, &soc_lpsc_list[11]), - PSC_DEV(149, &soc_lpsc_list[11]), - PSC_DEV(113, &soc_lpsc_list[12]), - PSC_DEV(197, &soc_lpsc_list[12]), - PSC_DEV(103, &soc_lpsc_list[13]), - PSC_DEV(104, &soc_lpsc_list[14]), - PSC_DEV(102, &soc_lpsc_list[15]), -}; - -const struct ti_k3_pd_platdata j721e_pd_platdata = { - .psc = soc_psc_list, - .pd = soc_pd_list, - .lpsc = soc_lpsc_list, - .devs = soc_dev_list, - .num_psc = ARRAY_SIZE(soc_psc_list), - .num_pd = ARRAY_SIZE(soc_pd_list), - .num_lpsc = ARRAY_SIZE(soc_lpsc_list), - .num_devs = ARRAY_SIZE(soc_dev_list), -}; diff --git a/arch/arm/mach-k3/j721s2/Makefile b/arch/arm/mach-k3/j721s2/Makefile deleted file mode 100644 index e794bffb3af..00000000000 --- a/arch/arm/mach-k3/j721s2/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ -obj-y += clk-data.o -obj-y += dev-data.o diff --git a/arch/arm/mach-k3/j721s2/clk-data.c b/arch/arm/mach-k3/j721s2/clk-data.c deleted file mode 100644 index 0c5c321c1eb..00000000000 --- a/arch/arm/mach-k3/j721s2/clk-data.c +++ /dev/null @@ -1,406 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * J721S2 specific clock platform data - * - * This file is auto generated. Please do not hand edit and report any issues - * to Dave Gerlach . - * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include "k3-clk.h" - -static const char * const gluelogic_hfosc0_clkout_parents[] = { - "osc_19_2_mhz", - "osc_20_mhz", - "osc_24_mhz", - "osc_25_mhz", - "osc_26_mhz", - "osc_27_mhz", -}; - -static const char * const mcu_ospi0_iclk_sel_out0_parents[] = { - "board_0_mcu_ospi0_dqs_out", - "fss_mcu_0_ospi_0_ospi_oclk_clk", -}; - -static const char * const mcu_ospi1_iclk_sel_out0_parents[] = { - "board_0_mcu_ospi1_dqs_out", - "fss_mcu_0_ospi_1_ospi_oclk_clk", -}; - -static const char * const wkup_fref_clksel_out0_parents[] = { - "gluelogic_hfosc0_clkout", - NULL, -}; - -static const char * const main_pll_hfosc_sel_out1_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = { - "wkup_fref_clksel_out0", - "hsdiv1_16fft_mcu_0_hsdivout0_clk", -}; - -static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = { - "hsdiv4_16fft_mcu_1_hsdivout4_clk", - "hsdiv4_16fft_mcu_2_hsdivout4_clk", -}; - -static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = { - "hsdiv4_16fft_mcu_1_hsdivout4_clk", - "hsdiv4_16fft_mcu_2_hsdivout4_clk", -}; - -static const char * const mcu_usart_clksel_out0_parents[] = { - "hsdiv4_16fft_mcu_1_hsdivout3_clk", - "postdiv3_16fft_main_1_hsdivout5_clk", -}; - -static const char * const wkup_i2c_mcupll_bypass_out0_parents[] = { - "hsdiv4_16fft_mcu_1_hsdivout3_clk", - "gluelogic_hfosc0_clkout", -}; - -static const char * const main_pll_hfosc_sel_out0_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out12_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out19_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out2_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out26_0_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out3_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out7_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const main_pll_hfosc_sel_out8_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const usb0_refclk_sel_out0_parents[] = { - "gluelogic_hfosc0_clkout", - "board_0_hfosc1_clk_out", -}; - -static const char * const emmcsd1_lb_clksel_out0_parents[] = { - "board_0_mmc1_clklb_out", - "board_0_mmc1_clk_out", -}; - -static const char * const mcu_clkout_mux_out0_parents[] = { - "hsdiv4_16fft_mcu_2_hsdivout0_clk", - "hsdiv4_16fft_mcu_2_hsdivout0_clk", -}; - -static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { - "main_pll_hfosc_sel_out0", - "hsdiv4_16fft_main_0_hsdivout0_clk", -}; - -static const char * const dpi0_ext_clksel_out0_parents[] = { - "hsdiv1_16fft_main_19_hsdivout0_clk", - "board_0_vout0_extpclkin_out", -}; - -static const char * const emmcsd_refclk_sel_out0_parents[] = { - "hsdiv4_16fft_main_0_hsdivout2_clk", - "hsdiv4_16fft_main_1_hsdivout2_clk", - "hsdiv4_16fft_main_2_hsdivout2_clk", - "hsdiv4_16fft_main_3_hsdivout2_clk", -}; - -static const char * const emmcsd_refclk_sel_out1_parents[] = { - "hsdiv4_16fft_main_0_hsdivout2_clk", - "hsdiv4_16fft_main_1_hsdivout2_clk", - "hsdiv4_16fft_main_2_hsdivout2_clk", - "hsdiv4_16fft_main_3_hsdivout2_clk", -}; - -static const char * const gtc_clk_mux_out0_parents[] = { - "hsdiv4_16fft_main_3_hsdivout1_clk", - "postdiv3_16fft_main_0_hsdivout6_clk", - "board_0_mcu_cpts0_rft_clk_out", - "board_0_cpts0_rft_clk_out", - "board_0_mcu_ext_refclk0_out", - "board_0_ext_refclk1_out", - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - "hsdiv4_16fft_mcu_2_hsdivout1_clk", - "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", -}; - -static const struct clk_data clk_list[] = { - CLK_FIXED_RATE("osc_27_mhz", 27000000, 0), - CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), - CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), - CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), - CLK_FIXED_RATE("osc_20_mhz", 20000000, 0), - CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0), - CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), - CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0), - CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0), - CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0), - CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0), - CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0), - CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0), - CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), - CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0), - CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0), - CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 2, 0x40f08034, 4, 1, 0), - CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0), - CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0), - CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000), - CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0), - CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000), - CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000), - CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), - CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0), - CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666), - CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0), - CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0), - CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), - CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0), - CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0), - CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out19", main_pll_hfosc_sel_out19_parents, 2, 0x430080cc, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out26_0", main_pll_hfosc_sel_out26_0_parents, 2, 0x430080e8, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0), - CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0), - CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0), - CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0), - CLK_FIXED_RATE("board_0_ddr0_ckn_out", 0, 0), - CLK_FIXED_RATE("board_0_ddr0_ckp_out", 0, 0), - CLK_FIXED_RATE("board_0_ddr1_ckn_out", 0, 0), - CLK_FIXED_RATE("board_0_ddr1_ckp_out", 0, 0), - CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), - CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0), - CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), - CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0), - CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), - CLK_FIXED_RATE("board_0_vout0_extpclkin_out", 0, 0), - CLK_FIXED_RATE("emmc8ss_16ffc_main_0_emmcss_io_clk", 0, 0), - CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), - CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), - CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0), - CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck", 0, 0), - CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n", 0, 0), - CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck", 0, 0), - CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n", 0, 0), - CLK_PLL("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0), - CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), - CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0), - CLK_PLL("pllfracf2_ssmod_16fft_main_19_foutvcop_clk", "main_pll_hfosc_sel_out19", 0x693000, 0), - CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0), - CLK_PLL("pllfracf2_ssmod_16fft_main_26_foutvcop_clk", "main_pll_hfosc_sel_out26_0", 0x69a000, 0), - CLK_PLL("pllfracf2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0), - CLK_PLL("pllfracf2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0), - CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0), - CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), - CLK_DIV("postdiv3_16fft_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0), - CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0), - CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0), - CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), - CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), - CLK_DIV("usart_programmable_clock_divider_out5", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0), - CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0), - CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), - CLK_DIV("hsdiv0_16fft_main_26_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_26_foutvcop_clk", 0x69a080, 0, 7, 0, 0), - CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0), - CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), - CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0), - CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), - CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), - CLK_MUX("dpi0_ext_clksel_out0", dpi0_ext_clksel_out0_parents, 2, 0x108300, 0, 1, 0), - CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0), - CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0), - CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0), - CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), - CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0), -}; - -static const struct dev_clk soc_dev_clk_data[] = { - DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), - DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), - DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(43, 0, "postdiv3_16fft_main_0_hsdivout8_clk"), - DEV_CLK(43, 1, "hsdiv4_16fft_main_0_hsdivout3_clk"), - DEV_CLK(43, 2, "gluelogic_hfosc0_clkout"), - DEV_CLK(43, 3, "board_0_hfosc1_clk_out"), - DEV_CLK(43, 5, "hsdiv4_16fft_main_0_hsdivout2_clk"), - DEV_CLK(43, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(43, 7, "board_0_hfosc1_clk_out"), - DEV_CLK(43, 9, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(43, 10, "hsdiv4_16fft_main_0_hsdivout4_clk"), - DEV_CLK(43, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(43, 12, "gluelogic_hfosc0_clkout"), - DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(61, 1, "gtc_clk_mux_out0"), - DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"), - DEV_CLK(61, 3, "postdiv3_16fft_main_0_hsdivout6_clk"), - DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"), - DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"), - DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"), - DEV_CLK(61, 7, "board_0_ext_refclk1_out"), - DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), - DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(98, 1, "emmcsd_refclk_sel_out0"), - DEV_CLK(98, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"), - DEV_CLK(98, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"), - DEV_CLK(98, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), - DEV_CLK(98, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"), - DEV_CLK(98, 6, "emmcsd1_lb_clksel_out0"), - DEV_CLK(98, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(99, 1, "emmcsd_refclk_sel_out1"), - DEV_CLK(99, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"), - DEV_CLK(99, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"), - DEV_CLK(99, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), - DEV_CLK(99, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"), - DEV_CLK(99, 7, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), - DEV_CLK(99, 8, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(108, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), - DEV_CLK(108, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), - DEV_CLK(108, 3, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), - DEV_CLK(108, 6, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), - DEV_CLK(108, 11, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(109, 0, "mcu_ospi0_iclk_sel_out0"), - DEV_CLK(109, 1, "board_0_mcu_ospi0_dqs_out"), - DEV_CLK(109, 2, "fss_mcu_0_ospi_0_ospi_oclk_clk"), - DEV_CLK(109, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(109, 5, "mcu_ospi_ref_clk_sel_out0"), - DEV_CLK(109, 6, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), - DEV_CLK(109, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), - DEV_CLK(109, 8, "board_0_mcu_ospi0_dqs_out"), - DEV_CLK(109, 9, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(110, 0, "mcu_ospi1_iclk_sel_out0"), - DEV_CLK(110, 1, "board_0_mcu_ospi1_dqs_out"), - DEV_CLK(110, 2, "fss_mcu_0_ospi_1_ospi_oclk_clk"), - DEV_CLK(110, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(110, 5, "mcu_ospi_ref_clk_sel_out1"), - DEV_CLK(110, 6, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), - DEV_CLK(110, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), - DEV_CLK(110, 8, "board_0_mcu_ospi1_dqs_out"), - DEV_CLK(110, 9, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(115, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(126, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(126, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(138, 0, "hsdiv0_16fft_main_12_hsdivout0_clk"), - DEV_CLK(138, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), - DEV_CLK(138, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(138, 3, "board_0_ddr0_ckn_out"), - DEV_CLK(138, 5, "board_0_ddr0_ckp_out"), - DEV_CLK(138, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(139, 0, "hsdiv0_16fft_main_26_hsdivout0_clk"), - DEV_CLK(139, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), - DEV_CLK(139, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(139, 3, "board_0_ddr1_ckn_out"), - DEV_CLK(139, 5, "board_0_ddr1_ckp_out"), - DEV_CLK(139, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(143, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(143, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(146, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(146, 3, "usart_programmable_clock_divider_out0"), - DEV_CLK(149, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(149, 3, "mcu_usart_clksel_out0"), - DEV_CLK(149, 4, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), - DEV_CLK(149, 5, "postdiv3_16fft_main_1_hsdivout5_clk"), - DEV_CLK(157, 9, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), - DEV_CLK(157, 103, "fss_mcu_0_ospi_0_ospi_oclk_clk"), - DEV_CLK(157, 104, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck"), - DEV_CLK(157, 111, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(157, 174, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck"), - DEV_CLK(157, 177, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(157, 179, "fss_mcu_0_ospi_0_ospi_oclk_clk"), - DEV_CLK(157, 182, "mshsi2c_wkup_0_porscl"), - DEV_CLK(157, 187, "fss_mcu_0_ospi_1_ospi_oclk_clk"), - DEV_CLK(157, 194, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), - DEV_CLK(157, 197, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n"), - DEV_CLK(157, 208, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n"), - DEV_CLK(157, 214, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), - DEV_CLK(157, 221, "mcu_clkout_mux_out0"), - DEV_CLK(157, 222, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), - DEV_CLK(157, 223, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), - DEV_CLK(157, 225, "emmc8ss_16ffc_main_0_emmcss_io_clk"), - DEV_CLK(157, 231, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), - DEV_CLK(157, 352, "dpi0_ext_clksel_out0"), - DEV_CLK(180, 0, "gluelogic_hfosc0_clkout"), - DEV_CLK(180, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(202, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), - DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), - DEV_CLK(223, 1, "wkup_i2c_mcupll_bypass_out0"), - DEV_CLK(223, 2, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), - DEV_CLK(223, 3, "gluelogic_hfosc0_clkout"), - DEV_CLK(223, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), - DEV_CLK(223, 5, "board_0_wkup_i2c0_scl_out"), - DEV_CLK(354, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(354, 3, "usart_programmable_clock_divider_out5"), - DEV_CLK(357, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(357, 3, "usart_programmable_clock_divider_out8"), - DEV_CLK(360, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(360, 13, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(360, 15, "postdiv3_16fft_main_1_hsdivout7_clk"), - DEV_CLK(360, 16, "usb0_refclk_sel_out0"), - DEV_CLK(360, 17, "gluelogic_hfosc0_clkout"), - DEV_CLK(360, 18, "board_0_hfosc1_clk_out"), - DEV_CLK(360, 22, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(360, 23, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), -}; - -const struct ti_k3_clk_platdata j721s2_clk_platdata = { - .clk_list = clk_list, - .clk_list_cnt = 105, - .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 124, -}; diff --git a/arch/arm/mach-k3/j721s2/dev-data.c b/arch/arm/mach-k3/j721s2/dev-data.c deleted file mode 100644 index df70c5e5d7c..00000000000 --- a/arch/arm/mach-k3/j721s2/dev-data.c +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * J721S2 specific device platform data - * - * This file is auto generated. Please do not hand edit and report any issues - * to Dave Gerlach . - * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "k3-dev.h" - -static struct ti_psc soc_psc_list[] = { - [0] = PSC(0, 0x42000000), - [1] = PSC(1, 0x00400000), -}; - -static struct ti_pd soc_pd_list[] = { - [0] = PSC_PD(0, &soc_psc_list[0], NULL), - [1] = PSC_PD(0, &soc_psc_list[1], NULL), - [2] = PSC_PD(1, &soc_psc_list[1], &soc_pd_list[1]), - [3] = PSC_PD(14, &soc_psc_list[1], NULL), - [4] = PSC_PD(15, &soc_psc_list[1], &soc_pd_list[3]), - [5] = PSC_PD(16, &soc_psc_list[1], &soc_pd_list[3]), -}; - -static struct ti_lpsc soc_lpsc_list[] = { - [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), - [1] = PSC_LPSC(3, &soc_psc_list[0], &soc_pd_list[0], NULL), - [2] = PSC_LPSC(10, &soc_psc_list[0], &soc_pd_list[0], NULL), - [3] = PSC_LPSC(11, &soc_psc_list[0], &soc_pd_list[0], NULL), - [4] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], NULL), - [5] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[1], NULL), - [6] = PSC_LPSC(9, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[2]), - [7] = PSC_LPSC(14, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]), - [8] = PSC_LPSC(15, &soc_psc_list[1], &soc_pd_list[1], NULL), - [9] = PSC_LPSC(16, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[10]), - [10] = PSC_LPSC(17, &soc_psc_list[1], &soc_pd_list[1], NULL), - [11] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[4]), - [12] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[4]), - [13] = PSC_LPSC(25, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[4]), - [14] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[2], NULL), - [15] = PSC_LPSC(45, &soc_psc_list[1], &soc_pd_list[2], NULL), - [16] = PSC_LPSC(78, &soc_psc_list[1], &soc_pd_list[3], NULL), - [17] = PSC_LPSC(80, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[16]), - [18] = PSC_LPSC(81, &soc_psc_list[1], &soc_pd_list[5], &soc_lpsc_list[16]), -}; - -static struct ti_dev soc_dev_list[] = { - PSC_DEV(35, &soc_lpsc_list[0]), - PSC_DEV(108, &soc_lpsc_list[0]), - PSC_DEV(109, &soc_lpsc_list[0]), - PSC_DEV(110, &soc_lpsc_list[0]), - PSC_DEV(180, &soc_lpsc_list[0]), - PSC_DEV(149, &soc_lpsc_list[0]), - PSC_DEV(115, &soc_lpsc_list[1]), - PSC_DEV(223, &soc_lpsc_list[1]), - PSC_DEV(109, &soc_lpsc_list[2]), - PSC_DEV(110, &soc_lpsc_list[3]), - PSC_DEV(108, &soc_lpsc_list[4]), - PSC_DEV(43, &soc_lpsc_list[5]), - PSC_DEV(61, &soc_lpsc_list[6]), - PSC_DEV(96, &soc_lpsc_list[7]), - PSC_DEV(138, &soc_lpsc_list[8]), - PSC_DEV(97, &soc_lpsc_list[9]), - PSC_DEV(139, &soc_lpsc_list[10]), - PSC_DEV(360, &soc_lpsc_list[11]), - PSC_DEV(99, &soc_lpsc_list[12]), - PSC_DEV(98, &soc_lpsc_list[13]), - PSC_DEV(146, &soc_lpsc_list[14]), - PSC_DEV(354, &soc_lpsc_list[15]), - PSC_DEV(357, &soc_lpsc_list[15]), - PSC_DEV(4, &soc_lpsc_list[16]), - PSC_DEV(202, &soc_lpsc_list[17]), - PSC_DEV(203, &soc_lpsc_list[18]), -}; - -const struct ti_k3_pd_platdata j721s2_pd_platdata = { - .psc = soc_psc_list, - .pd = soc_pd_list, - .lpsc = soc_lpsc_list, - .devs = soc_dev_list, - .num_psc = ARRAY_SIZE(soc_psc_list), - .num_pd = ARRAY_SIZE(soc_pd_list), - .num_lpsc = ARRAY_SIZE(soc_lpsc_list), - .num_devs = ARRAY_SIZE(soc_dev_list), -}; diff --git a/arch/arm/mach-k3/lowlevel_init.S b/arch/arm/mach-k3/lowlevel_init.S deleted file mode 100644 index 463ab0de1bd..00000000000 --- a/arch/arm/mach-k3/lowlevel_init.S +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ - * Lokesh Vutla - */ - -#include - -ENTRY(lowlevel_init) - - mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR - and r0, #0xff - cmp r0, #0x0 - bne park_cpu - bx lr -park_cpu: - wfi - b park_cpu - -ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile new file mode 100644 index 00000000000..8a6af73a44e --- /dev/null +++ b/arch/arm/mach-k3/r5/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# Andrew Davis + +obj-$(CONFIG_SOC_K3_J721E) += j721e/ +obj-$(CONFIG_SOC_K3_J721E) += j7200/ +obj-$(CONFIG_SOC_K3_J721S2) += j721s2/ +obj-$(CONFIG_SOC_K3_AM625) += am62x/ +obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/ + +obj-y += lowlevel_init.o +obj-y += r5_mpu.o diff --git a/arch/arm/mach-k3/r5/am62ax/Makefile b/arch/arm/mach-k3/r5/am62ax/Makefile new file mode 100644 index 00000000000..02a941805e9 --- /dev/null +++ b/arch/arm/mach-k3/r5/am62ax/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + +obj-y += clk-data.o +obj-y += dev-data.o +obj-y += am62a_qos_data.o diff --git a/arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c b/arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c new file mode 100644 index 00000000000..38db4f2f5c8 --- /dev/null +++ b/arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * am62a Quality of Service (QoS) Configuration Data + * Auto generated from K3 Resource Partitioning tool + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ +#include +#include "common.h" + +struct k3_qos_data am62a_qos_data[] = { + /* modules_qosConfig0 - 1 endpoints, 4 channels */ + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 0, + .val = ORDERID_8, + }, + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 1, + .val = ORDERID_8, + }, + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 2, + .val = ORDERID_8, + }, + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 3, + .val = ORDERID_8, + }, + + /* Following registers set 1:1 mapping for orderID MAP1/MAP2 + * remap registers. orderID x is remapped to orderID x again + * This is to ensure orderID from MAP register is unchanged + */ + + /* K3_DSS_UL_MAIN_0_VBUSM_DMA - 1 groups */ + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0, + .val = 0x76543210, + }, + { + .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 4, + .val = 0xfedcba98, + }, +}; + +uint32_t am62a_qos_count = sizeof(am62a_qos_data) / sizeof(am62a_qos_data[0]); diff --git a/arch/arm/mach-k3/r5/am62ax/clk-data.c b/arch/arm/mach-k3/r5/am62ax/clk-data.c new file mode 100644 index 00000000000..d950b35e0be --- /dev/null +++ b/arch/arm/mach-k3/r5/am62ax/clk-data.c @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AM62AX specific clock platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Bryan Brattlof . + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + NULL, + NULL, + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + NULL, +}; + +static const char * const clk_32k_rc_sel_out0_parents[] = { + "gluelogic_rcosc_clk_1p0v_97p65k", + "gluelogic_hfosc0_clkout", + "gluelogic_rcosc_clk_1p0v_97p65k", + "gluelogic_lfosc0_clkout", +}; + +static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = { + "board_0_mmc0_clklb_out", + "board_0_mmc0_clk_out", +}; + +static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = { + "board_0_mmc1_clklb_out", + "board_0_mmc1_clk_out", +}; + +static const char * const main_ospi_loopback_clk_sel_out0_parents[] = { + "board_0_ospi0_dqs_out", + "board_0_ospi0_lbclko_out", +}; + +static const char * const main_usb0_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const main_usb1_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const clkout0_ctrl_out0_parents[] = { + "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk", +}; + +static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_gtcclk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const main_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout1_clk", + "postdiv1_16fft_main_1_hsdivout5_clk", +}; + +static const char * const wkup_clkout_sel_out0_parents[] = { + NULL, + "gluelogic_lfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "postdiv4_16ff_main_2_hsdivout9_clk", + "clk_32k_rc_sel_out0", + "gluelogic_rcosc_clkout", + "gluelogic_hfosc0_clkout", +}; + +static const char * const wkup_clkout_sel_io_out0_parents[] = { + "wkup_clkout_sel_out0", + "gluelogic_hfosc0_clkout", +}; + +static const char * const wkup_clksel_out0_parents[] = { + "hsdiv2_16fft_main_15_hsdivout0_clk", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const main_usart0_fclk_sel_out0_parents[] = { + "usart_programmable_clock_divider_out0", + "hsdiv4_16fft_main_1_hsdivout1_clk", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0), + CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ddr0_ck0_out", 0, 0), + CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), + CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc0_clklb_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc0_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), + CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0), + CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0), + CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0), + CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0), + CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0), + CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0), + CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0), + CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0), + CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), + CLK_DIV("hsdiv2_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), + CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), + CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), + CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), + CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), + CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000), + CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0), + CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0), + CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0), + CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0), + CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0), + CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 5, "board_0_ext_refclk1_out"), + DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"), + DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 9, "board_0_ext_refclk1_out"), + DEV_CLK(16, 10, "gluelogic_rcosc_clkout"), + DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(57, 0, "main_emmcsd0_io_clklb_sel_out0"), + DEV_CLK(57, 1, "board_0_mmc0_clklb_out"), + DEV_CLK(57, 2, "board_0_mmc0_clk_out"), + DEV_CLK(57, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(57, 6, "main_emmcsd0_refclk_sel_out0"), + DEV_CLK(57, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(57, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"), + DEV_CLK(58, 1, "board_0_mmc1_clklb_out"), + DEV_CLK(58, 2, "board_0_mmc1_clk_out"), + DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"), + DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(61, 0, "main_gtcclk_sel_out0"), + DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(61, 6, "board_0_ext_refclk1_out"), + DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 9, "wkup_clksel_out0"), + DEV_CLK(61, 10, "hsdiv2_16fft_main_15_hsdivout0_clk"), + DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(75, 0, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"), + DEV_CLK(75, 3, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"), + DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"), + DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"), + DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(95, 0, "gluelogic_rcosc_clkout"), + DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"), + DEV_CLK(95, 2, "wkup_clksel_out0"), + DEV_CLK(95, 3, "hsdiv2_16fft_main_15_hsdivout0_clk"), + DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(102, 1, "board_0_i2c0_scl_out"), + DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"), + DEV_CLK(107, 0, "wkup_clksel_out0"), + DEV_CLK(107, 1, "hsdiv2_16fft_main_15_hsdivout0_clk"), + DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"), + DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"), + DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"), + DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"), + DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 20, "clkout0_ctrl_out0"), + DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 25, "board_0_ddr0_ck0_out"), + DEV_CLK(157, 40, "mshsi2c_main_0_porscl"), + DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), + DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 85, "emmcsd8ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 130, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 146, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"), + DEV_CLK(157, 159, "wkup_clkout_sel_io_out0"), + DEV_CLK(157, 160, "wkup_clkout_sel_out0"), + DEV_CLK(157, 161, "gluelogic_hfosc0_clkout"), + DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"), + DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), + DEV_CLK(161, 10, "board_0_tck_out"), + DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"), + DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), + DEV_CLK(162, 10, "board_0_tck_out"), + DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(170, 2, "board_0_tck_out"), + DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), +}; + +const struct ti_k3_clk_platdata am62ax_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = 80, + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = 104, +}; diff --git a/arch/arm/mach-k3/r5/am62ax/dev-data.c b/arch/arm/mach-k3/r5/am62ax/dev-data.c new file mode 100644 index 00000000000..abf5d8e91aa --- /dev/null +++ b/arch/arm/mach-k3/r5/am62ax/dev-data.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AM62AX specific device platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Bryan Brattlof . + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x04000000), + [1] = PSC(1, 0x00400000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[1], NULL), + [1] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]), + [2] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[1]), + [3] = PSC_PD(13, &soc_psc_list[1], &soc_pd_list[0]), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[5]), + [2] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[6]), + [3] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [4] = PSC_LPSC(21, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [5] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [6] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [7] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [8] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [9] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]), + [10] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[9]), + [11] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[8]), + [12] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[11]), + [13] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[12]), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(16, &soc_lpsc_list[0]), + PSC_DEV(77, &soc_lpsc_list[0]), + PSC_DEV(61, &soc_lpsc_list[0]), + PSC_DEV(95, &soc_lpsc_list[0]), + PSC_DEV(107, &soc_lpsc_list[0]), + PSC_DEV(178, &soc_lpsc_list[1]), + PSC_DEV(179, &soc_lpsc_list[2]), + PSC_DEV(57, &soc_lpsc_list[3]), + PSC_DEV(58, &soc_lpsc_list[4]), + PSC_DEV(161, &soc_lpsc_list[5]), + PSC_DEV(162, &soc_lpsc_list[6]), + PSC_DEV(75, &soc_lpsc_list[7]), + PSC_DEV(102, &soc_lpsc_list[8]), + PSC_DEV(146, &soc_lpsc_list[8]), + PSC_DEV(166, &soc_lpsc_list[9]), + PSC_DEV(135, &soc_lpsc_list[10]), + PSC_DEV(170, &soc_lpsc_list[11]), + PSC_DEV(177, &soc_lpsc_list[12]), + PSC_DEV(55, &soc_lpsc_list[13]), +}; + +const struct ti_k3_pd_platdata am62ax_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = ARRAY_SIZE(soc_psc_list), + .num_pd = ARRAY_SIZE(soc_pd_list), + .num_lpsc = ARRAY_SIZE(soc_lpsc_list), + .num_devs = ARRAY_SIZE(soc_dev_list), +}; diff --git a/arch/arm/mach-k3/r5/am62x/Makefile b/arch/arm/mach-k3/r5/am62x/Makefile new file mode 100644 index 00000000000..d6c876df66d --- /dev/null +++ b/arch/arm/mach-k3/r5/am62x/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/r5/am62x/clk-data.c b/arch/arm/mach-k3/r5/am62x/clk-data.c new file mode 100644 index 00000000000..d7bfed0e031 --- /dev/null +++ b/arch/arm/mach-k3/r5/am62x/clk-data.c @@ -0,0 +1,367 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AM62X specific clock platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Dave Gerlach . + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + NULL, + NULL, + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + NULL, +}; + +static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = { + "board_0_mmc0_clklb_out", + "board_0_mmc0_clk_out", +}; + +static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = { + "board_0_mmc1_clklb_out", + "board_0_mmc1_clk_out", +}; + +static const char * const main_ospi_loopback_clk_sel_out0_parents[] = { + "board_0_ospi0_dqs_out", + "board_0_ospi0_lbclko_out", +}; + +static const char * const main_usb0_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const main_usb1_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const clkout0_ctrl_out0_parents[] = { + "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk10", +}; + +static const char * const clk_32k_rc_sel_out0_parents[] = { + "gluelogic_rcosc_clk_1p0v_97p65k", + "hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk", + "clk_32k_rc_sel_div_clkout", + "gluelogic_lfosc0_clkout", +}; + +static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_gtcclk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const main_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout1_clk", + "postdiv1_16fft_main_1_hsdivout5_clk", +}; + +static const char * const wkup_clkout_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "gluelogic_lfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "postdiv4_16ff_main_2_hsdivout9_clk", + "clk_32k_rc_sel_out0", + "gluelogic_rcosc_clkout", + "gluelogic_hfosc0_clkout", +}; + +static const char * const wkup_clksel_out0_parents[] = { + "hsdiv1_16fft_main_15_hsdivout0_clk", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const main_usart0_fclk_sel_out0_parents[] = { + "usart_programmable_clock_divider_out0", + "hsdiv4_16fft_main_1_hsdivout1_clk", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0), + CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ddr0_ck0_out", 0, 0), + CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), + CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc0_clklb_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc0_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), + CLK_FIXED_RATE("board_0_rgmii1_rxc_out", 0, 0), + CLK_FIXED_RATE("board_0_rgmii1_txc_out", 0, 0), + CLK_FIXED_RATE("board_0_rgmii2_rxc_out", 0, 0), + CLK_FIXED_RATE("board_0_rgmii2_txc_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_main_0_mdio_mdclk_o", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii1_txc_o", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii2_txc_o", 0, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_DIV("hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk", "gluelogic_hfosc0_clkout", 0x4508030, 0, 7, 0, 0), + CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0), + CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0), + CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0), + CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0), + CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0), + CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0), + CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0), + CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk10", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), + CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), + CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0), + CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0), + CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), + CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), + CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), + CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000), + CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0), + CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0), + CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0), + CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0), + CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"), + DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(13, 9, "board_0_ext_refclk1_out"), + DEV_CLK(13, 10, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 19, "board_0_rgmii1_rxc_out"), + DEV_CLK(13, 20, "board_0_rgmii1_txc_out"), + DEV_CLK(13, 22, "board_0_rgmii2_rxc_out"), + DEV_CLK(13, 23, "board_0_rgmii2_txc_out"), + DEV_CLK(13, 25, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 26, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 27, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 28, "board_0_rmii1_ref_clk_out"), + DEV_CLK(13, 29, "board_0_rmii2_ref_clk_out"), + DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 5, "board_0_ext_refclk1_out"), + DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"), + DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 9, "board_0_ext_refclk1_out"), + DEV_CLK(16, 10, "gluelogic_rcosc_clkout"), + DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(57, 0, "main_emmcsd0_io_clklb_sel_out0"), + DEV_CLK(57, 1, "board_0_mmc0_clklb_out"), + DEV_CLK(57, 2, "board_0_mmc0_clk_out"), + DEV_CLK(57, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(57, 6, "main_emmcsd0_refclk_sel_out0"), + DEV_CLK(57, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(57, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"), + DEV_CLK(58, 1, "board_0_mmc1_clklb_out"), + DEV_CLK(58, 2, "board_0_mmc1_clk_out"), + DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"), + DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(61, 0, "main_gtcclk_sel_out0"), + DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(61, 6, "board_0_ext_refclk1_out"), + DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 9, "wkup_clksel_out0"), + DEV_CLK(61, 10, "hsdiv1_16fft_main_15_hsdivout0_clk"), + DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(75, 0, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"), + DEV_CLK(75, 3, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"), + DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"), + DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"), + DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(95, 0, "gluelogic_rcosc_clkout"), + DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"), + DEV_CLK(95, 2, "wkup_clksel_out0"), + DEV_CLK(95, 3, "hsdiv1_16fft_main_15_hsdivout0_clk"), + DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(102, 1, "board_0_i2c0_scl_out"), + DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"), + DEV_CLK(107, 0, "wkup_clksel_out0"), + DEV_CLK(107, 1, "hsdiv1_16fft_main_15_hsdivout0_clk"), + DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(107, 3, "mshsi2c_wkup_0_porscl"), + DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"), + DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(136, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"), + DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"), + DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"), + DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 20, "clkout0_ctrl_out0"), + DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk10"), + DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 25, "board_0_ddr0_ck0_out"), + DEV_CLK(157, 40, "mshsi2c_main_0_porscl"), + DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), + DEV_CLK(157, 82, "cpsw_3guss_main_0_mdio_mdclk_o"), + DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 129, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 132, "cpsw_3guss_main_0_rgmii1_txc_o"), + DEV_CLK(157, 135, "cpsw_3guss_main_0_rgmii2_txc_o"), + DEV_CLK(157, 145, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"), + DEV_CLK(157, 158, "wkup_clkout_sel_out0"), + DEV_CLK(157, 159, "gluelogic_hfosc0_clkout"), + DEV_CLK(157, 160, "gluelogic_lfosc0_clkout"), + DEV_CLK(157, 161, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(157, 162, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(157, 163, "postdiv4_16ff_main_2_hsdivout9_clk"), + DEV_CLK(157, 164, "clk_32k_rc_sel_out0"), + DEV_CLK(157, 165, "gluelogic_rcosc_clkout"), + DEV_CLK(157, 166, "gluelogic_hfosc0_clkout"), + DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"), + DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), + DEV_CLK(161, 10, "board_0_tck_out"), + DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"), + DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), + DEV_CLK(162, 10, "board_0_tck_out"), + DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(170, 0, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(170, 1, "board_0_tck_out"), + DEV_CLK(170, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), +}; + +const struct ti_k3_clk_platdata am62x_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = 90, + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = 137, +}; diff --git a/arch/arm/mach-k3/r5/am62x/dev-data.c b/arch/arm/mach-k3/r5/am62x/dev-data.c new file mode 100644 index 00000000000..59c95df2a88 --- /dev/null +++ b/arch/arm/mach-k3/r5/am62x/dev-data.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AM62X specific device platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Dave Gerlach . + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x04000000), + [1] = PSC(1, 0x00400000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[1], NULL), + [1] = PSC_PD(2, &soc_psc_list[1], &soc_pd_list[0]), + [2] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]), + [3] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[2]), + [4] = PSC_PD(5, &soc_psc_list[1], &soc_pd_list[2]), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(9, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), + [2] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[1]), + [3] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[2]), + [4] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [5] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[9]), + [6] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), + [7] = PSC_LPSC(21, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), + [8] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), + [9] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), + [10] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), + [11] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[11]), + [12] = PSC_LPSC(41, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[11]), + [13] = PSC_LPSC(42, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[11]), + [14] = PSC_LPSC(45, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[13]), + [15] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[13]), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(16, &soc_lpsc_list[0]), + PSC_DEV(77, &soc_lpsc_list[0]), + PSC_DEV(61, &soc_lpsc_list[0]), + PSC_DEV(95, &soc_lpsc_list[0]), + PSC_DEV(107, &soc_lpsc_list[0]), + PSC_DEV(170, &soc_lpsc_list[1]), + PSC_DEV(177, &soc_lpsc_list[2]), + PSC_DEV(55, &soc_lpsc_list[3]), + PSC_DEV(178, &soc_lpsc_list[4]), + PSC_DEV(179, &soc_lpsc_list[5]), + PSC_DEV(57, &soc_lpsc_list[6]), + PSC_DEV(58, &soc_lpsc_list[7]), + PSC_DEV(161, &soc_lpsc_list[8]), + PSC_DEV(162, &soc_lpsc_list[9]), + PSC_DEV(75, &soc_lpsc_list[10]), + PSC_DEV(36, &soc_lpsc_list[11]), + PSC_DEV(102, &soc_lpsc_list[11]), + PSC_DEV(146, &soc_lpsc_list[11]), + PSC_DEV(13, &soc_lpsc_list[12]), + PSC_DEV(166, &soc_lpsc_list[13]), + PSC_DEV(135, &soc_lpsc_list[14]), + PSC_DEV(136, &soc_lpsc_list[15]), +}; + +const struct ti_k3_pd_platdata am62x_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = ARRAY_SIZE(soc_psc_list), + .num_pd = ARRAY_SIZE(soc_pd_list), + .num_lpsc = ARRAY_SIZE(soc_lpsc_list), + .num_devs = ARRAY_SIZE(soc_dev_list), +}; diff --git a/arch/arm/mach-k3/r5/j7200/Makefile b/arch/arm/mach-k3/r5/j7200/Makefile new file mode 100644 index 00000000000..0f91cf4daea --- /dev/null +++ b/arch/arm/mach-k3/r5/j7200/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/r5/j7200/clk-data.c b/arch/arm/mach-k3/r5/j7200/clk-data.c new file mode 100644 index 00000000000..9b45786a2d4 --- /dev/null +++ b/arch/arm/mach-k3/r5/j7200/clk-data.c @@ -0,0 +1,555 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J7200 specific clock platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Dave Gerlach . + * + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + "osc_19_2_mhz", + "osc_20_mhz", + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + "osc_27_mhz", +}; + +static const char * const mcu_ospi0_iclk_sel_out0_parents[] = { + "board_0_mcu_ospi0_dqs_out", + "fss_mcu_0_ospi_0_ospi_oclk_clk", +}; + +static const char * const wkup_fref_clksel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", +}; + +static const char * const main_pll_hfosc_sel_out1_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = { + "wkup_fref_clksel_out0", + "hsdiv1_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", +}; + +static const char * const mcuusart_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "postdiv2_16fft_main_1_hsdivout5_clk", +}; + +static const char * const wkup_gpio0_clksel_out0_parents[] = { + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", + "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", + "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", +}; + +static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out12_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out14_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out2_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out3_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out4_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out7_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out8_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const usb0_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const wkup_obsclk_mux_out0_parents[] = { + "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", + NULL, + "hsdiv1_16fft_mcu_0_hsdivout0_clk", + "hsdiv1_16fft_mcu_0_hsdivout0_clk", + "hsdiv4_16fft_mcu_1_hsdivout1_clk", + "hsdiv4_16fft_mcu_1_hsdivout2_clk", + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout0_clk", + "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "hsdiv4_16fft_mcu_2_hsdivout2_clk", + "hsdiv4_16fft_mcu_2_hsdivout3_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", + "gluelogic_hfosc0_clkout", + "board_0_wkup_lf_clkin_out", +}; + +static const char * const main_pll4_xref_sel_out0_parents[] = { + "main_pll_hfosc_sel_out4", + "board_0_ext_refclk1_out", +}; + +static const char * const mcu_clkout_mux_out0_parents[] = { + "hsdiv4_16fft_mcu_2_hsdivout0_clk", + "hsdiv4_16fft_mcu_2_hsdivout0_clk", +}; + +static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "main_pll_hfosc_sel_out0", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const mcu_obsclk_outmux_out0_parents[] = { + "mcu_obsclk_div_out0", + "gluelogic_hfosc0_clkout", +}; + +static const char * const clkout_mux_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout0_clk", + "hsdiv4_16fft_main_3_hsdivout0_clk", +}; + +static const char * const emmcsd_refclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const emmcsd_refclk_sel_out1_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const gtc_clk_mux_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv2_16fft_main_0_hsdivout6_clk", + "board_0_mcu_cpts0_rft_clk_out", + "board_0_cpts0_rft_clk_out", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const obsclk1_mux_out0_parents[] = { + NULL, + "hsdiv0_16fft_main_8_hsdivout0_clk", + NULL, + NULL, +}; + +static const char * const gpmc_fclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout3_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const audio_refclko_mux_out0_parents[] = { + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv2_16fft_main_4_hsdivout2_clk", + NULL, + NULL, + NULL, +}; + +static const char * const audio_refclko_mux_out1_parents[] = { + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv2_16fft_main_4_hsdivout2_clk", + NULL, + NULL, + NULL, +}; + +static const char * const obsclk0_mux_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout0_clk", + "hsdiv4_16fft_main_1_hsdivout0_clk", + "hsdiv4_16fft_main_2_hsdivout0_clk", + "hsdiv4_16fft_main_3_hsdivout0_clk", + "hsdiv2_16fft_main_4_hsdivout0_clk", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv0_16fft_main_12_hsdivout0_clk", + "obsclk1_mux_out0", + "hsdiv1_16fft_main_14_hsdivout0_clk", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", + "board_0_wkup_lf_clkin_out", + "hsdiv4_16fft_main_0_hsdivout0_clk", + "board_0_hfosc1_clk_out", + "gluelogic_hfosc0_clkout", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_27_mhz", 27000000, 0), + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_FIXED_RATE("osc_20_mhz", 20000000, 0), + CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0), + CLK_FIXED_RATE("j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32550, 0), + CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0), + CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0), + CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0), + CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0), + CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000), + CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000), + CLK_DIV("postdiv2_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0), + CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), + CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0), + CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0), + CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out14", main_pll_hfosc_sel_out14_parents, 2, 0x430080b8, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out4", main_pll_hfosc_sel_out4_parents, 2, 0x43008090, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0), + CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0), + CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("board_0_wkup_lf_clkin_out", 0, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0), + CLK_DIV("postdiv2_16fft_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), + CLK_DIV("postdiv2_16fft_main_1_hsdivout7_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0), + CLK_MUX("wkup_obsclk_mux_out0", wkup_obsclk_mux_out0_parents, 16, 0x43008000, 0, 4, 0), + CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0), + CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out1", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c4, 0, 2, 0, 0, 48000000), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_14_hsdivout0_clk", "pllfracf_ssmod_16fft_main_14_foutvcop_clk", 0x68e080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout0_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout0_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), + CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0, 0), + CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0), + CLK_MUX("clkout_mux_out0", clkout_mux_out0_parents, 2, 0x108010, 0, 1, 0), + CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0), + CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0), + CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0), + CLK_MUX("obsclk1_mux_out0", obsclk1_mux_out0_parents, 4, 0x108004, 0, 2, 0), + CLK_MUX("gpmc_fclk_sel_out0", gpmc_fclk_sel_out0_parents, 4, 0x1080d0, 0, 2, 0), + CLK_DIV("hsdiv2_16fft_main_4_hsdivout0_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684080, 0, 7, 0, 0), + CLK_DIV("hsdiv2_16fft_main_4_hsdivout2_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684088, 0, 7, 0, 0), + CLK_MUX("audio_refclko_mux_out0", audio_refclko_mux_out0_parents, 32, 0x1082e0, 0, 5, 0), + CLK_MUX("audio_refclko_mux_out1", audio_refclko_mux_out1_parents, 32, 0x1082e4, 0, 5, 0), + CLK_MUX("obsclk0_mux_out0", obsclk0_mux_out0_parents, 32, 0x108000, 0, 5, 0), + CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(8, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(8, 5, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 1, "board_0_hfosc1_clk_out"), + DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"), + DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"), + DEV_CLK(30, 10, "board_0_hfosc1_clk_out"), + DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 12, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 1, "gtc_clk_mux_out0"), + DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(61, 3, "postdiv2_16fft_main_0_hsdivout6_clk"), + DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"), + DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"), + DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(61, 7, "board_0_ext_refclk1_out"), + DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(91, 3, "emmcsd_refclk_sel_out0"), + DEV_CLK(91, 4, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(91, 5, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(91, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(91, 7, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(92, 0, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(92, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(92, 2, "emmcsd_refclk_sel_out1"), + DEV_CLK(92, 3, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(92, 4, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(92, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(92, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(102, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(102, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(102, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(102, 5, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(102, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"), + DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(103, 4, "board_0_mcu_ospi0_dqs_out"), + DEV_CLK(103, 5, "mcu_ospi0_iclk_sel_out0"), + DEV_CLK(103, 6, "board_0_mcu_ospi0_dqs_out"), + DEV_CLK(103, 7, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(103, 8, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(104, 0, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(104, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(113, 0, "wkup_gpio0_clksel_out0"), + DEV_CLK(113, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(113, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(113, 3, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk"), + DEV_CLK(113, 4, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(146, 2, "usart_programmable_clock_divider_out0"), + DEV_CLK(146, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(149, 2, "mcuusart_clk_sel_out0"), + DEV_CLK(149, 3, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), + DEV_CLK(149, 4, "postdiv2_16fft_main_1_hsdivout5_clk"), + DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(154, 0, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"), + DEV_CLK(157, 5, "osbclk0_div_out0"), + DEV_CLK(157, 7, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), + DEV_CLK(157, 14, "mcu_obsclk_outmux_out0"), + DEV_CLK(157, 15, "mcu_obsclk_div_out0"), + DEV_CLK(157, 16, "gluelogic_hfosc0_clkout"), + DEV_CLK(157, 35, "clkout_mux_out0"), + DEV_CLK(157, 36, "hsdiv4_16fft_main_3_hsdivout0_clk"), + DEV_CLK(157, 37, "hsdiv4_16fft_main_3_hsdivout0_clk"), + DEV_CLK(157, 38, "osbclk0_div_out0"), + DEV_CLK(157, 57, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), + DEV_CLK(157, 65, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 69, "mcu_clkout_mux_out0"), + DEV_CLK(157, 70, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(157, 71, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(157, 77, "audio_refclko_mux_out1"), + DEV_CLK(157, 106, "hsdiv2_16fft_main_4_hsdivout2_clk"), + DEV_CLK(157, 110, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 114, "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk"), + DEV_CLK(157, 123, "mshsi2c_wkup_0_porscl"), + DEV_CLK(157, 131, "audio_refclko_mux_out0"), + DEV_CLK(157, 160, "hsdiv2_16fft_main_4_hsdivout2_clk"), + DEV_CLK(157, 169, "board_0_mcu_i2c0_scl_out"), + DEV_CLK(157, 177, "k3_pll_ctrl_wrap_main_0_sysclkout_clk"), + DEV_CLK(157, 184, "gpmc_fclk_sel_out0"), + DEV_CLK(157, 187, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 192, "osbclk0_div_out0"), + DEV_CLK(157, 193, "hsdiv4_16fft_main_0_hsdivout0_clk"), + DEV_CLK(157, 194, "hsdiv4_16fft_main_1_hsdivout0_clk"), + DEV_CLK(157, 195, "hsdiv4_16fft_main_2_hsdivout0_clk"), + DEV_CLK(157, 196, "hsdiv4_16fft_main_3_hsdivout0_clk"), + DEV_CLK(157, 197, "hsdiv2_16fft_main_4_hsdivout0_clk"), + DEV_CLK(157, 205, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(157, 206, "obsclk1_mux_out0"), + DEV_CLK(157, 207, "hsdiv1_16fft_main_14_hsdivout0_clk"), + DEV_CLK(157, 220, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(157, 221, "board_0_wkup_lf_clkin_out"), + DEV_CLK(157, 222, "hsdiv4_16fft_main_0_hsdivout0_clk"), + DEV_CLK(157, 223, "board_0_hfosc1_clk_out"), + DEV_CLK(157, 224, "gluelogic_hfosc0_clkout"), + DEV_CLK(197, 0, "board_0_wkup_i2c0_scl_out"), + DEV_CLK(197, 1, "wkup_i2c0_mcupll_bypass_clksel_out0"), + DEV_CLK(197, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(278, 2, "usart_programmable_clock_divider_out1"), + DEV_CLK(278, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(288, 3, "postdiv2_16fft_main_1_hsdivout7_clk"), + DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(288, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(288, 12, "usb0_refclk_sel_out0"), + DEV_CLK(288, 13, "gluelogic_hfosc0_clkout"), + DEV_CLK(288, 14, "board_0_hfosc1_clk_out"), + DEV_CLK(288, 15, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(288, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), +}; + +const struct ti_k3_clk_platdata j7200_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = 109, + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = 129, +}; diff --git a/arch/arm/mach-k3/r5/j7200/dev-data.c b/arch/arm/mach-k3/r5/j7200/dev-data.c new file mode 100644 index 00000000000..8ce6796fd04 --- /dev/null +++ b/arch/arm/mach-k3/r5/j7200/dev-data.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J7200 specific device platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Dave Gerlach . + * + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x00400000), + [1] = PSC(1, 0x42000000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[0], NULL), + [1] = PSC_PD(2, &soc_psc_list[0], &soc_pd_list[5]), + [2] = PSC_PD(14, &soc_psc_list[0], NULL), + [3] = PSC_PD(15, &soc_psc_list[0], &soc_pd_list[2]), + [4] = PSC_PD(16, &soc_psc_list[0], &soc_pd_list[2]), + [5] = PSC_PD(0, &soc_psc_list[1], NULL), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(9, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[14]), + [2] = PSC_LPSC(14, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[3]), + [3] = PSC_LPSC(15, &soc_psc_list[0], &soc_pd_list[0], NULL), + [4] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], NULL), + [5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], NULL), + [6] = PSC_LPSC(25, &soc_psc_list[0], &soc_pd_list[0], NULL), + [7] = PSC_LPSC(54, &soc_psc_list[0], &soc_pd_list[1], NULL), + [8] = PSC_LPSC(78, &soc_psc_list[0], &soc_pd_list[2], NULL), + [9] = PSC_LPSC(79, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]), + [10] = PSC_LPSC(80, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]), + [11] = PSC_LPSC(81, &soc_psc_list[0], &soc_pd_list[4], &soc_lpsc_list[8]), + [12] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[5], NULL), + [13] = PSC_LPSC(3, &soc_psc_list[1], &soc_pd_list[5], NULL), + [14] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[5], NULL), + [15] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[5], NULL), + [16] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[5], NULL), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(30, &soc_lpsc_list[0]), + PSC_DEV(35, &soc_lpsc_list[0]), + PSC_DEV(61, &soc_lpsc_list[1]), + PSC_DEV(90, &soc_lpsc_list[2]), + PSC_DEV(8, &soc_lpsc_list[3]), + PSC_DEV(288, &soc_lpsc_list[4]), + PSC_DEV(92, &soc_lpsc_list[5]), + PSC_DEV(91, &soc_lpsc_list[6]), + PSC_DEV(146, &soc_lpsc_list[7]), + PSC_DEV(278, &soc_lpsc_list[7]), + PSC_DEV(4, &soc_lpsc_list[8]), + PSC_DEV(4, &soc_lpsc_list[9]), + PSC_DEV(202, &soc_lpsc_list[10]), + PSC_DEV(203, &soc_lpsc_list[11]), + PSC_DEV(102, &soc_lpsc_list[12]), + PSC_DEV(103, &soc_lpsc_list[12]), + PSC_DEV(104, &soc_lpsc_list[12]), + PSC_DEV(154, &soc_lpsc_list[12]), + PSC_DEV(149, &soc_lpsc_list[12]), + PSC_DEV(113, &soc_lpsc_list[13]), + PSC_DEV(197, &soc_lpsc_list[13]), + PSC_DEV(103, &soc_lpsc_list[14]), + PSC_DEV(104, &soc_lpsc_list[15]), + PSC_DEV(102, &soc_lpsc_list[16]), +}; + +const struct ti_k3_pd_platdata j7200_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = ARRAY_SIZE(soc_psc_list), + .num_pd = ARRAY_SIZE(soc_pd_list), + .num_lpsc = ARRAY_SIZE(soc_lpsc_list), + .num_devs = ARRAY_SIZE(soc_dev_list), +}; diff --git a/arch/arm/mach-k3/r5/j721e/Makefile b/arch/arm/mach-k3/r5/j721e/Makefile new file mode 100644 index 00000000000..0f91cf4daea --- /dev/null +++ b/arch/arm/mach-k3/r5/j721e/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/r5/j721e/clk-data.c b/arch/arm/mach-k3/r5/j721e/clk-data.c new file mode 100644 index 00000000000..e4511092c86 --- /dev/null +++ b/arch/arm/mach-k3/r5/j721e/clk-data.c @@ -0,0 +1,789 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J721E specific clock platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Dave Gerlach . + * + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + "osc_19_2_mhz", + "osc_20_mhz", + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + "osc_27_mhz", +}; + +static const char * const mcu_ospi0_iclk_sel_out0_parents[] = { + "board_0_mcu_ospi0_dqs_out", + "fss_mcu_0_ospi_0_ospi_oclk_clk", +}; + +static const char * const mcu_ospi1_iclk_sel_out0_parents[] = { + "board_0_mcu_ospi1_dqs_out", + "fss_mcu_0_ospi_1_ospi_oclk_clk", +}; + +static const char * const wkup_fref_clksel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", +}; + +static const char * const main_pll_hfosc_sel_out1_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = { + "wkup_fref_clksel_out0", + "hsdiv1_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", +}; + +static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", +}; + +static const char * const mcuusart_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "postdiv3_16fft_main_1_hsdivout5_clk", +}; + +static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll25_hfosc_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out12_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out13_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out14_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out15_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out16_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out17_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out18_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out19_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out2_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out23_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out3_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out4_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out5_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out6_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out7_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out8_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const usb0_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const usb1_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const wkup_obsclk_mux_out0_parents[] = { + "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", + NULL, + "hsdiv1_16fft_mcu_0_hsdivout0_clk", + "hsdiv1_16fft_mcu_0_hsdivout0_clk", + "hsdiv4_16fft_mcu_1_hsdivout1_clk", + "hsdiv4_16fft_mcu_1_hsdivout2_clk", + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout0_clk", + "j7_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "hsdiv4_16fft_mcu_2_hsdivout2_clk", + "hsdiv4_16fft_mcu_2_hsdivout3_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", + "gluelogic_hfosc0_clkout", + "gluelogic_lpxosc_clkout", +}; + +static const char * const main_pll15_xref_sel_out0_parents[] = { + "main_pll_hfosc_sel_out15", + "board_0_ext_refclk1_out", +}; + +static const char * const main_pll24_hfosc_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_mlb0_mlbcp_out", +}; + +static const char * const main_pll4_xref_sel_out0_parents[] = { + "main_pll_hfosc_sel_out4", + "board_0_ext_refclk1_out", +}; + +static const char * const mcu_clkout_mux_out0_parents[] = { + "hsdiv4_16fft_mcu_2_hsdivout0_clk", + "hsdiv4_16fft_mcu_2_hsdivout0_clk", +}; + +static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "main_pll_hfosc_sel_out0", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const mcu_obsclk_outmux_out0_parents[] = { + "mcu_obsclk_div_out0", + "gluelogic_hfosc0_clkout", +}; + +static const char * const obsclk1_mux_out0_parents[] = { + "hsdiv0_16fft_main_7_hsdivout0_clk", + "hsdiv0_16fft_main_8_hsdivout0_clk", + "hsdiv3_16fft_main_13_hsdivout0_clk", + NULL, +}; + +static const char * const clkout_mux_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout0_clk", + "hsdiv4_16fft_main_3_hsdivout0_clk", +}; + +static const char * const emmcsd_refclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const emmcsd_refclk_sel_out1_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const gtc_clk_mux_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv3_16fft_main_0_hsdivout6_clk", + "board_0_mcu_cpts0_rft_clk_out", + "board_0_cpts0_rft_clk_out", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const gpmc_fclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout3_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const mcasp_ahclko_mux_out0_parents[] = { + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv3_16fft_main_4_hsdivout2_clk", + "hsdiv3_16fft_main_15_hsdivout2_clk", + NULL, + NULL, + "board_0_audio_ext_refclk0_out", +}; + +static const char * const mcasp_ahclko_mux_out1_parents[] = { + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv3_16fft_main_4_hsdivout2_clk", + "hsdiv3_16fft_main_15_hsdivout2_clk", + NULL, + NULL, + "board_0_audio_ext_refclk1_out", +}; + +static const char * const mcasp_ahclko_mux_out2_parents[] = { + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv3_16fft_main_4_hsdivout2_clk", + "hsdiv3_16fft_main_15_hsdivout2_clk", + NULL, + NULL, + "board_0_audio_ext_refclk2_out", +}; + +static const char * const mcasp_ahclko_mux_out3_parents[] = { + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv3_16fft_main_4_hsdivout2_clk", + "hsdiv3_16fft_main_15_hsdivout2_clk", + NULL, + NULL, + "board_0_audio_ext_refclk3_out", +}; + +static const char * const obsclk0_mux_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout0_clk", + "hsdiv4_16fft_main_1_hsdivout0_clk", + "hsdiv4_16fft_main_2_hsdivout0_clk", + "hsdiv4_16fft_main_3_hsdivout0_clk", + "hsdiv3_16fft_main_4_hsdivout0_clk", + "hsdiv3_16fft_main_5_hsdivout0_clk", + "hsdiv0_16fft_main_6_hsdivout0_clk", + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv0_16fft_main_12_hsdivout0_clk", + "obsclk1_mux_out0", + "hsdiv1_16fft_main_14_hsdivout0_clk", + "hsdiv3_16fft_main_15_hsdivout0_clk", + "hsdiv1_16fft_main_16_hsdivout0_clk", + "hsdiv1_16fft_main_17_hsdivout0_clk", + "hsdiv1_16fft_main_18_hsdivout0_clk", + "hsdiv1_16fft_main_19_hsdivout0_clk", + NULL, + NULL, + NULL, + "hsdiv1_16fft_main_23_hsdivout0_clk", + "hsdiv0_16fft_main_24_hsdivout0_clk", + "hsdiv1_16fft_main_25_hsdivout0_clk", + NULL, + "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", + "gluelogic_lpxosc_clkout", + "hsdiv4_16fft_main_0_hsdivout0_clk", + "board_0_hfosc1_clk_out", + "gluelogic_hfosc0_clkout", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_27_mhz", 27000000, 0), + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_FIXED_RATE("osc_20_mhz", 20000000, 0), + CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0), + CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0), + CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 2, 0x40f08034, 4, 1, 0), + CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0), + CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0), + CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000), + CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0), + CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000), + CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000), + CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0), + CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), + CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0), + CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0), + CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0), + CLK_FIXED_RATE("gluelogic_lpxosc_clkout", 32768, 0), + CLK_MUX("main_pll25_hfosc_sel_out0", main_pll25_hfosc_sel_out0_parents, 2, 0x430080e4, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out13", main_pll_hfosc_sel_out13_parents, 2, 0x430080b4, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out14", main_pll_hfosc_sel_out14_parents, 2, 0x430080b8, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out15", main_pll_hfosc_sel_out15_parents, 2, 0x430080bc, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out16", main_pll_hfosc_sel_out16_parents, 2, 0x430080c0, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out17", main_pll_hfosc_sel_out17_parents, 2, 0x430080c4, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out18", main_pll_hfosc_sel_out18_parents, 2, 0x430080c8, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out19", main_pll_hfosc_sel_out19_parents, 2, 0x430080cc, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out23", main_pll_hfosc_sel_out23_parents, 2, 0x430080dc, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out4", main_pll_hfosc_sel_out4_parents, 2, 0x43008090, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out5", main_pll_hfosc_sel_out5_parents, 2, 0x43008094, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out6", main_pll_hfosc_sel_out6_parents, 2, 0x43008098, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0), + CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0), + CLK_MUX("usb1_refclk_sel_out0", usb1_refclk_sel_out0_parents, 2, 0x1080e4, 0, 1, 0), + CLK_FIXED_RATE("board_0_audio_ext_refclk0_out", 0, 0), + CLK_FIXED_RATE("board_0_audio_ext_refclk1_out", 0, 0), + CLK_FIXED_RATE("board_0_audio_ext_refclk2_out", 0, 0), + CLK_FIXED_RATE("board_0_audio_ext_refclk3_out", 0, 0), + CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), + CLK_FIXED_RATE("board_0_mlb0_mlbcp_out", 0, 0), + CLK_FIXED_RATE("ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck", 0, 0), + CLK_FIXED_RATE("ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck_n", 0, 0), + CLK_FIXED_RATE("emmc8ss_16ffc_main_0_emmcss_io_clk", 0, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0, 0), + CLK_FIXED_RATE("j7_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0), + CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfrac2_ssmod_16fft_main_13_foutvcop_clk", "main_pll_hfosc_sel_out13", 0x68d000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_16_foutvcop_clk", "main_pll_hfosc_sel_out16", 0x690000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_17_foutvcop_clk", "main_pll_hfosc_sel_out17", 0x691000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_18_foutvcop_clk", "main_pll_hfosc_sel_out18", 0x692000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_19_foutvcop_clk", "main_pll_hfosc_sel_out19", 0x693000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_23_foutvcop_clk", "main_pll_hfosc_sel_out23", 0x697000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_25_foutvcop_clk", "main_pll25_hfosc_sel_out0", 0x699000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_5_foutvcop_clk", "main_pll_hfosc_sel_out5", 0x685000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_6_foutvcop_clk", "main_pll_hfosc_sel_out6", 0x686000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0), + CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), + CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0), + CLK_MUX("wkup_obsclk_mux_out0", wkup_obsclk_mux_out0_parents, 16, 0x43008000, 0, 4, 0), + CLK_MUX("main_pll15_xref_sel_out0", main_pll15_xref_sel_out0_parents, 2, 0x430080bc, 4, 1, 0), + CLK_MUX("main_pll24_hfosc_sel_out0", main_pll24_hfosc_sel_out0_parents, 2, 0x430080e0, 0, 1, 0), + CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0), + CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out2", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c8, 0, 2, 0, 0, 48000000), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_6_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_6_foutvcop_clk", 0x686080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_14_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_14_foutvcop_clk", 0x68e080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_16_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_16_foutvcop_clk", 0x690080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_17_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_17_foutvcop_clk", 0x691080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_18_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_18_foutvcop_clk", 0x692080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_23_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_23_foutvcop_clk", 0x697080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_25_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_25_foutvcop_clk", 0x699080, 0, 7, 0, 0), + CLK_DIV("hsdiv3_16fft_main_13_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_13_foutvcop_clk", 0x68d080, 0, 7, 0, 0), + CLK_DIV("hsdiv3_16fft_main_5_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_5_foutvcop_clk", 0x685080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), + CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0, 0), + CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0), + CLK_MUX("obsclk1_mux_out0", obsclk1_mux_out0_parents, 4, 0x108004, 0, 2, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_15_foutvcop_clk", "main_pll15_xref_sel_out0", 0x68f000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0), + CLK_MUX("clkout_mux_out0", clkout_mux_out0_parents, 2, 0x108010, 0, 1, 0), + CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0), + CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0), + CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0), + CLK_MUX("gpmc_fclk_sel_out0", gpmc_fclk_sel_out0_parents, 4, 0x1080d0, 0, 2, 0), + CLK_DIV("hsdiv0_16fft_main_24_hsdivout0_clk", "plldeskew_16fft_main_24_foutp_clk", 0x698080, 0, 0, 0, 0), + CLK_DIV("hsdiv3_16fft_main_15_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0), + CLK_DIV("hsdiv3_16fft_main_15_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_15_foutvcop_clk", 0x68f088, 0, 7, 0, 0), + CLK_DIV("hsdiv3_16fft_main_4_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_4_foutvcop_clk", 0x684080, 0, 7, 0, 0), + CLK_DIV("hsdiv3_16fft_main_4_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_4_foutvcop_clk", 0x684088, 0, 7, 0, 0), + CLK_MUX("mcasp_ahclko_mux_out0", mcasp_ahclko_mux_out0_parents, 33, 0x1082e0, 0, 5, 0), + CLK_MUX("mcasp_ahclko_mux_out1", mcasp_ahclko_mux_out1_parents, 33, 0x1082e4, 0, 5, 0), + CLK_MUX("mcasp_ahclko_mux_out2", mcasp_ahclko_mux_out2_parents, 33, 0x1082e8, 0, 5, 0), + CLK_MUX("mcasp_ahclko_mux_out3", mcasp_ahclko_mux_out3_parents, 33, 0x1082ec, 0, 5, 0), + CLK_MUX("obsclk0_mux_out0", obsclk0_mux_out0_parents, 32, 0x108000, 0, 5, 0), + CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(4, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(4, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 1, "board_0_hfosc1_clk_out"), + DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"), + DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"), + DEV_CLK(30, 10, "board_0_hfosc1_clk_out"), + DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 12, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(47, 0, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(47, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(47, 2, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(47, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 1, "gtc_clk_mux_out0"), + DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(61, 3, "postdiv3_16fft_main_0_hsdivout6_clk"), + DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"), + DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"), + DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(61, 7, "board_0_ext_refclk1_out"), + DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(91, 1, "emmcsd_refclk_sel_out0"), + DEV_CLK(91, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(91, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(91, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(91, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(92, 0, "emmcsd_refclk_sel_out1"), + DEV_CLK(92, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(92, 2, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(92, 3, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(92, 4, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(92, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(92, 6, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(102, 0, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(102, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(102, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(102, 3, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(102, 4, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"), + DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(103, 4, "mcu_ospi0_iclk_sel_out0"), + DEV_CLK(103, 5, "board_0_mcu_ospi0_dqs_out"), + DEV_CLK(103, 6, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(103, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(103, 8, "board_0_mcu_ospi0_dqs_out"), + DEV_CLK(104, 0, "mcu_ospi_ref_clk_sel_out1"), + DEV_CLK(104, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(104, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(104, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(104, 4, "mcu_ospi1_iclk_sel_out0"), + DEV_CLK(104, 5, "board_0_mcu_ospi1_dqs_out"), + DEV_CLK(104, 6, "fss_mcu_0_ospi_1_ospi_oclk_clk"), + DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(104, 8, "board_0_mcu_ospi1_dqs_out"), + DEV_CLK(113, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(146, 0, "usart_programmable_clock_divider_out0"), + DEV_CLK(146, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(149, 0, "mcuusart_clk_sel_out0"), + DEV_CLK(149, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), + DEV_CLK(149, 2, "postdiv3_16fft_main_1_hsdivout5_clk"), + DEV_CLK(149, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(154, 0, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"), + DEV_CLK(157, 18, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 19, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 21, "fss_mcu_0_ospi_1_ospi_oclk_clk"), + DEV_CLK(157, 22, "fss_mcu_0_ospi_1_ospi_oclk_clk"), + DEV_CLK(157, 42, "mshsi2c_wkup_0_porscl"), + DEV_CLK(157, 50, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), + DEV_CLK(157, 51, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), + DEV_CLK(157, 91, "ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck"), + DEV_CLK(157, 92, "ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck_n"), + DEV_CLK(157, 99, "emmc8ss_16ffc_main_0_emmcss_io_clk"), + DEV_CLK(157, 100, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 104, "gpmc_fclk_sel_out0"), + DEV_CLK(157, 109, "hsdiv1_16fft_main_19_hsdivout0_clk"), + DEV_CLK(157, 111, "hsdiv1_16fft_main_23_hsdivout0_clk"), + DEV_CLK(157, 113, "osbclk0_div_out0"), + DEV_CLK(157, 114, "hsdiv4_16fft_main_0_hsdivout0_clk"), + DEV_CLK(157, 115, "hsdiv4_16fft_main_1_hsdivout0_clk"), + DEV_CLK(157, 116, "hsdiv4_16fft_main_2_hsdivout0_clk"), + DEV_CLK(157, 117, "hsdiv4_16fft_main_3_hsdivout0_clk"), + DEV_CLK(157, 118, "hsdiv3_16fft_main_4_hsdivout0_clk"), + DEV_CLK(157, 119, "hsdiv3_16fft_main_5_hsdivout0_clk"), + DEV_CLK(157, 120, "hsdiv0_16fft_main_6_hsdivout0_clk"), + DEV_CLK(157, 126, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(157, 127, "obsclk1_mux_out0"), + DEV_CLK(157, 128, "hsdiv1_16fft_main_14_hsdivout0_clk"), + DEV_CLK(157, 129, "hsdiv3_16fft_main_15_hsdivout0_clk"), + DEV_CLK(157, 130, "hsdiv1_16fft_main_16_hsdivout0_clk"), + DEV_CLK(157, 131, "hsdiv1_16fft_main_17_hsdivout0_clk"), + DEV_CLK(157, 132, "hsdiv1_16fft_main_18_hsdivout0_clk"), + DEV_CLK(157, 133, "hsdiv1_16fft_main_19_hsdivout0_clk"), + DEV_CLK(157, 137, "hsdiv1_16fft_main_23_hsdivout0_clk"), + DEV_CLK(157, 138, "hsdiv0_16fft_main_24_hsdivout0_clk"), + DEV_CLK(157, 139, "hsdiv1_16fft_main_25_hsdivout0_clk"), + DEV_CLK(157, 141, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(157, 142, "gluelogic_lpxosc_clkout"), + DEV_CLK(157, 143, "hsdiv4_16fft_main_0_hsdivout0_clk"), + DEV_CLK(157, 144, "board_0_hfosc1_clk_out"), + DEV_CLK(157, 145, "gluelogic_hfosc0_clkout"), + DEV_CLK(157, 146, "obsclk1_mux_out0"), + DEV_CLK(157, 147, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(157, 148, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(157, 149, "hsdiv3_16fft_main_13_hsdivout0_clk"), + DEV_CLK(157, 152, "mcu_obsclk_outmux_out0"), + DEV_CLK(157, 153, "mcu_obsclk_div_out0"), + DEV_CLK(157, 154, "gluelogic_hfosc0_clkout"), + DEV_CLK(157, 169, "k3_pll_ctrl_wrap_main_0_sysclkout_clk"), + DEV_CLK(157, 170, "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk"), + DEV_CLK(157, 172, "clkout_mux_out0"), + DEV_CLK(157, 173, "hsdiv4_16fft_main_3_hsdivout0_clk"), + DEV_CLK(157, 174, "hsdiv4_16fft_main_3_hsdivout0_clk"), + DEV_CLK(157, 175, "mcu_clkout_mux_out0"), + DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(157, 177, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(157, 301, "mcasp_ahclko_mux_out0"), + DEV_CLK(157, 330, "hsdiv3_16fft_main_4_hsdivout2_clk"), + DEV_CLK(157, 331, "hsdiv3_16fft_main_15_hsdivout2_clk"), + DEV_CLK(157, 334, "board_0_audio_ext_refclk0_out"), + DEV_CLK(157, 336, "mcasp_ahclko_mux_out1"), + DEV_CLK(157, 365, "hsdiv3_16fft_main_4_hsdivout2_clk"), + DEV_CLK(157, 366, "hsdiv3_16fft_main_15_hsdivout2_clk"), + DEV_CLK(157, 369, "board_0_audio_ext_refclk1_out"), + DEV_CLK(157, 371, "mcasp_ahclko_mux_out2"), + DEV_CLK(157, 400, "hsdiv3_16fft_main_4_hsdivout2_clk"), + DEV_CLK(157, 401, "hsdiv3_16fft_main_15_hsdivout2_clk"), + DEV_CLK(157, 404, "board_0_audio_ext_refclk2_out"), + DEV_CLK(157, 406, "mcasp_ahclko_mux_out3"), + DEV_CLK(157, 435, "hsdiv3_16fft_main_4_hsdivout2_clk"), + DEV_CLK(157, 436, "hsdiv3_16fft_main_15_hsdivout2_clk"), + DEV_CLK(157, 439, "board_0_audio_ext_refclk3_out"), + DEV_CLK(197, 0, "wkup_i2c0_mcupll_bypass_clksel_out0"), + DEV_CLK(197, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), + DEV_CLK(197, 2, "gluelogic_hfosc0_clkout"), + DEV_CLK(197, 3, "board_0_wkup_i2c0_scl_out"), + DEV_CLK(197, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(279, 0, "usart_programmable_clock_divider_out2"), + DEV_CLK(279, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(288, 3, "postdiv3_16fft_main_1_hsdivout7_clk"), + DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(288, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(288, 15, "usb0_refclk_sel_out0"), + DEV_CLK(288, 16, "gluelogic_hfosc0_clkout"), + DEV_CLK(288, 17, "board_0_hfosc1_clk_out"), + DEV_CLK(288, 18, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(288, 19, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(289, 3, "postdiv3_16fft_main_1_hsdivout7_clk"), + DEV_CLK(289, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(289, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(289, 15, "usb1_refclk_sel_out0"), + DEV_CLK(289, 16, "gluelogic_hfosc0_clkout"), + DEV_CLK(289, 17, "board_0_hfosc1_clk_out"), + DEV_CLK(289, 18, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(289, 19, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), +}; + +const struct ti_k3_clk_platdata j721e_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = 157, + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = 173, +}; diff --git a/arch/arm/mach-k3/r5/j721e/dev-data.c b/arch/arm/mach-k3/r5/j721e/dev-data.c new file mode 100644 index 00000000000..b0adb1857be --- /dev/null +++ b/arch/arm/mach-k3/r5/j721e/dev-data.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J721E specific device platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Dave Gerlach . + * + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x00400000), + [1] = PSC(1, 0x42000000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[0], NULL), + [1] = PSC_PD(14, &soc_psc_list[0], NULL), + [2] = PSC_PD(15, &soc_psc_list[0], &soc_pd_list[1]), + [3] = PSC_PD(16, &soc_psc_list[0], &soc_pd_list[1]), + [4] = PSC_PD(0, &soc_psc_list[1], NULL), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(7, &soc_psc_list[0], &soc_pd_list[0], NULL), + [2] = PSC_LPSC(14, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[3]), + [3] = PSC_LPSC(15, &soc_psc_list[0], &soc_pd_list[0], NULL), + [4] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], NULL), + [5] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], NULL), + [6] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], NULL), + [7] = PSC_LPSC(25, &soc_psc_list[0], &soc_pd_list[0], NULL), + [8] = PSC_LPSC(78, &soc_psc_list[0], &soc_pd_list[1], NULL), + [9] = PSC_LPSC(80, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]), + [10] = PSC_LPSC(81, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]), + [11] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[4], NULL), + [12] = PSC_LPSC(3, &soc_psc_list[1], &soc_pd_list[4], NULL), + [13] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[4], NULL), + [14] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[4], NULL), + [15] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[4], NULL), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(30, &soc_lpsc_list[0]), + PSC_DEV(61, &soc_lpsc_list[0]), + PSC_DEV(146, &soc_lpsc_list[1]), + PSC_DEV(279, &soc_lpsc_list[1]), + PSC_DEV(90, &soc_lpsc_list[2]), + PSC_DEV(47, &soc_lpsc_list[3]), + PSC_DEV(288, &soc_lpsc_list[4]), + PSC_DEV(289, &soc_lpsc_list[5]), + PSC_DEV(92, &soc_lpsc_list[6]), + PSC_DEV(91, &soc_lpsc_list[7]), + PSC_DEV(4, &soc_lpsc_list[8]), + PSC_DEV(202, &soc_lpsc_list[9]), + PSC_DEV(203, &soc_lpsc_list[10]), + PSC_DEV(35, &soc_lpsc_list[11]), + PSC_DEV(102, &soc_lpsc_list[11]), + PSC_DEV(103, &soc_lpsc_list[11]), + PSC_DEV(104, &soc_lpsc_list[11]), + PSC_DEV(154, &soc_lpsc_list[11]), + PSC_DEV(149, &soc_lpsc_list[11]), + PSC_DEV(113, &soc_lpsc_list[12]), + PSC_DEV(197, &soc_lpsc_list[12]), + PSC_DEV(103, &soc_lpsc_list[13]), + PSC_DEV(104, &soc_lpsc_list[14]), + PSC_DEV(102, &soc_lpsc_list[15]), +}; + +const struct ti_k3_pd_platdata j721e_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = ARRAY_SIZE(soc_psc_list), + .num_pd = ARRAY_SIZE(soc_pd_list), + .num_lpsc = ARRAY_SIZE(soc_lpsc_list), + .num_devs = ARRAY_SIZE(soc_dev_list), +}; diff --git a/arch/arm/mach-k3/r5/j721s2/Makefile b/arch/arm/mach-k3/r5/j721s2/Makefile new file mode 100644 index 00000000000..e794bffb3af --- /dev/null +++ b/arch/arm/mach-k3/r5/j721s2/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/r5/j721s2/clk-data.c b/arch/arm/mach-k3/r5/j721s2/clk-data.c new file mode 100644 index 00000000000..0c5c321c1eb --- /dev/null +++ b/arch/arm/mach-k3/r5/j721s2/clk-data.c @@ -0,0 +1,406 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J721S2 specific clock platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Dave Gerlach . + * + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + "osc_19_2_mhz", + "osc_20_mhz", + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + "osc_27_mhz", +}; + +static const char * const mcu_ospi0_iclk_sel_out0_parents[] = { + "board_0_mcu_ospi0_dqs_out", + "fss_mcu_0_ospi_0_ospi_oclk_clk", +}; + +static const char * const mcu_ospi1_iclk_sel_out0_parents[] = { + "board_0_mcu_ospi1_dqs_out", + "fss_mcu_0_ospi_1_ospi_oclk_clk", +}; + +static const char * const wkup_fref_clksel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + NULL, +}; + +static const char * const main_pll_hfosc_sel_out1_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = { + "wkup_fref_clksel_out0", + "hsdiv1_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", +}; + +static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", +}; + +static const char * const mcu_usart_clksel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "postdiv3_16fft_main_1_hsdivout5_clk", +}; + +static const char * const wkup_i2c_mcupll_bypass_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out12_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out19_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out2_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out26_0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out3_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out7_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const main_pll_hfosc_sel_out8_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const usb0_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "board_0_hfosc1_clk_out", +}; + +static const char * const emmcsd1_lb_clksel_out0_parents[] = { + "board_0_mmc1_clklb_out", + "board_0_mmc1_clk_out", +}; + +static const char * const mcu_clkout_mux_out0_parents[] = { + "hsdiv4_16fft_mcu_2_hsdivout0_clk", + "hsdiv4_16fft_mcu_2_hsdivout0_clk", +}; + +static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "main_pll_hfosc_sel_out0", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const dpi0_ext_clksel_out0_parents[] = { + "hsdiv1_16fft_main_19_hsdivout0_clk", + "board_0_vout0_extpclkin_out", +}; + +static const char * const emmcsd_refclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const emmcsd_refclk_sel_out1_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const gtc_clk_mux_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv3_16fft_main_0_hsdivout6_clk", + "board_0_mcu_cpts0_rft_clk_out", + "board_0_cpts0_rft_clk_out", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_27_mhz", 27000000, 0), + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_FIXED_RATE("osc_20_mhz", 20000000, 0), + CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0), + CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0), + CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 2, 0x40f08034, 4, 1, 0), + CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0), + CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0), + CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000), + CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0), + CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000), + CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000), + CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0), + CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), + CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0), + CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0), + CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out19", main_pll_hfosc_sel_out19_parents, 2, 0x430080cc, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out26_0", main_pll_hfosc_sel_out26_0_parents, 2, 0x430080e8, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0), + CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0), + CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ddr0_ckn_out", 0, 0), + CLK_FIXED_RATE("board_0_ddr0_ckp_out", 0, 0), + CLK_FIXED_RATE("board_0_ddr1_ckn_out", 0, 0), + CLK_FIXED_RATE("board_0_ddr1_ckp_out", 0, 0), + CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_vout0_extpclkin_out", 0, 0), + CLK_FIXED_RATE("emmc8ss_16ffc_main_0_emmcss_io_clk", 0, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0), + CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck", 0, 0), + CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n", 0, 0), + CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck", 0, 0), + CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n", 0, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0), + CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_19_foutvcop_clk", "main_pll_hfosc_sel_out19", 0x693000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_26_foutvcop_clk", "main_pll_hfosc_sel_out26_0", 0x69a000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0), + CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0), + CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), + CLK_DIV("postdiv3_16fft_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0), + CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0), + CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0), + CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), + CLK_DIV("usart_programmable_clock_divider_out5", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0), + CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_26_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_26_foutvcop_clk", 0x69a080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), + CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), + CLK_MUX("dpi0_ext_clksel_out0", dpi0_ext_clksel_out0_parents, 2, 0x108300, 0, 1, 0), + CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0), + CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0), + CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(43, 0, "postdiv3_16fft_main_0_hsdivout8_clk"), + DEV_CLK(43, 1, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(43, 2, "gluelogic_hfosc0_clkout"), + DEV_CLK(43, 3, "board_0_hfosc1_clk_out"), + DEV_CLK(43, 5, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(43, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(43, 7, "board_0_hfosc1_clk_out"), + DEV_CLK(43, 9, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(43, 10, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(43, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(43, 12, "gluelogic_hfosc0_clkout"), + DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 1, "gtc_clk_mux_out0"), + DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(61, 3, "postdiv3_16fft_main_0_hsdivout6_clk"), + DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"), + DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"), + DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(61, 7, "board_0_ext_refclk1_out"), + DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(98, 1, "emmcsd_refclk_sel_out0"), + DEV_CLK(98, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(98, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(98, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(98, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(98, 6, "emmcsd1_lb_clksel_out0"), + DEV_CLK(98, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(99, 1, "emmcsd_refclk_sel_out1"), + DEV_CLK(99, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(99, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(99, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(99, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(99, 7, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(99, 8, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(108, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(108, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(108, 3, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(108, 6, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(108, 11, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(109, 0, "mcu_ospi0_iclk_sel_out0"), + DEV_CLK(109, 1, "board_0_mcu_ospi0_dqs_out"), + DEV_CLK(109, 2, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(109, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(109, 5, "mcu_ospi_ref_clk_sel_out0"), + DEV_CLK(109, 6, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(109, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(109, 8, "board_0_mcu_ospi0_dqs_out"), + DEV_CLK(109, 9, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(110, 0, "mcu_ospi1_iclk_sel_out0"), + DEV_CLK(110, 1, "board_0_mcu_ospi1_dqs_out"), + DEV_CLK(110, 2, "fss_mcu_0_ospi_1_ospi_oclk_clk"), + DEV_CLK(110, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(110, 5, "mcu_ospi_ref_clk_sel_out1"), + DEV_CLK(110, 6, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(110, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(110, 8, "board_0_mcu_ospi1_dqs_out"), + DEV_CLK(110, 9, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(115, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(126, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(126, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(138, 0, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(138, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(138, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(138, 3, "board_0_ddr0_ckn_out"), + DEV_CLK(138, 5, "board_0_ddr0_ckp_out"), + DEV_CLK(138, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(139, 0, "hsdiv0_16fft_main_26_hsdivout0_clk"), + DEV_CLK(139, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(139, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(139, 3, "board_0_ddr1_ckn_out"), + DEV_CLK(139, 5, "board_0_ddr1_ckp_out"), + DEV_CLK(139, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(143, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(143, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(146, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(146, 3, "usart_programmable_clock_divider_out0"), + DEV_CLK(149, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(149, 3, "mcu_usart_clksel_out0"), + DEV_CLK(149, 4, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), + DEV_CLK(149, 5, "postdiv3_16fft_main_1_hsdivout5_clk"), + DEV_CLK(157, 9, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 103, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 104, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck"), + DEV_CLK(157, 111, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(157, 174, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck"), + DEV_CLK(157, 177, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 179, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 182, "mshsi2c_wkup_0_porscl"), + DEV_CLK(157, 187, "fss_mcu_0_ospi_1_ospi_oclk_clk"), + DEV_CLK(157, 194, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 197, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n"), + DEV_CLK(157, 208, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n"), + DEV_CLK(157, 214, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), + DEV_CLK(157, 221, "mcu_clkout_mux_out0"), + DEV_CLK(157, 222, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(157, 223, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(157, 225, "emmc8ss_16ffc_main_0_emmcss_io_clk"), + DEV_CLK(157, 231, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), + DEV_CLK(157, 352, "dpi0_ext_clksel_out0"), + DEV_CLK(180, 0, "gluelogic_hfosc0_clkout"), + DEV_CLK(180, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(202, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(223, 1, "wkup_i2c_mcupll_bypass_out0"), + DEV_CLK(223, 2, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), + DEV_CLK(223, 3, "gluelogic_hfosc0_clkout"), + DEV_CLK(223, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(223, 5, "board_0_wkup_i2c0_scl_out"), + DEV_CLK(354, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(354, 3, "usart_programmable_clock_divider_out5"), + DEV_CLK(357, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(357, 3, "usart_programmable_clock_divider_out8"), + DEV_CLK(360, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(360, 13, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(360, 15, "postdiv3_16fft_main_1_hsdivout7_clk"), + DEV_CLK(360, 16, "usb0_refclk_sel_out0"), + DEV_CLK(360, 17, "gluelogic_hfosc0_clkout"), + DEV_CLK(360, 18, "board_0_hfosc1_clk_out"), + DEV_CLK(360, 22, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(360, 23, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), +}; + +const struct ti_k3_clk_platdata j721s2_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = 105, + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = 124, +}; diff --git a/arch/arm/mach-k3/r5/j721s2/dev-data.c b/arch/arm/mach-k3/r5/j721s2/dev-data.c new file mode 100644 index 00000000000..df70c5e5d7c --- /dev/null +++ b/arch/arm/mach-k3/r5/j721s2/dev-data.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J721S2 specific device platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Dave Gerlach . + * + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x42000000), + [1] = PSC(1, 0x00400000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[0], NULL), + [1] = PSC_PD(0, &soc_psc_list[1], NULL), + [2] = PSC_PD(1, &soc_psc_list[1], &soc_pd_list[1]), + [3] = PSC_PD(14, &soc_psc_list[1], NULL), + [4] = PSC_PD(15, &soc_psc_list[1], &soc_pd_list[3]), + [5] = PSC_PD(16, &soc_psc_list[1], &soc_pd_list[3]), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(3, &soc_psc_list[0], &soc_pd_list[0], NULL), + [2] = PSC_LPSC(10, &soc_psc_list[0], &soc_pd_list[0], NULL), + [3] = PSC_LPSC(11, &soc_psc_list[0], &soc_pd_list[0], NULL), + [4] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], NULL), + [5] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[1], NULL), + [6] = PSC_LPSC(9, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[2]), + [7] = PSC_LPSC(14, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]), + [8] = PSC_LPSC(15, &soc_psc_list[1], &soc_pd_list[1], NULL), + [9] = PSC_LPSC(16, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[10]), + [10] = PSC_LPSC(17, &soc_psc_list[1], &soc_pd_list[1], NULL), + [11] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[4]), + [12] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[4]), + [13] = PSC_LPSC(25, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[4]), + [14] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[2], NULL), + [15] = PSC_LPSC(45, &soc_psc_list[1], &soc_pd_list[2], NULL), + [16] = PSC_LPSC(78, &soc_psc_list[1], &soc_pd_list[3], NULL), + [17] = PSC_LPSC(80, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[16]), + [18] = PSC_LPSC(81, &soc_psc_list[1], &soc_pd_list[5], &soc_lpsc_list[16]), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(35, &soc_lpsc_list[0]), + PSC_DEV(108, &soc_lpsc_list[0]), + PSC_DEV(109, &soc_lpsc_list[0]), + PSC_DEV(110, &soc_lpsc_list[0]), + PSC_DEV(180, &soc_lpsc_list[0]), + PSC_DEV(149, &soc_lpsc_list[0]), + PSC_DEV(115, &soc_lpsc_list[1]), + PSC_DEV(223, &soc_lpsc_list[1]), + PSC_DEV(109, &soc_lpsc_list[2]), + PSC_DEV(110, &soc_lpsc_list[3]), + PSC_DEV(108, &soc_lpsc_list[4]), + PSC_DEV(43, &soc_lpsc_list[5]), + PSC_DEV(61, &soc_lpsc_list[6]), + PSC_DEV(96, &soc_lpsc_list[7]), + PSC_DEV(138, &soc_lpsc_list[8]), + PSC_DEV(97, &soc_lpsc_list[9]), + PSC_DEV(139, &soc_lpsc_list[10]), + PSC_DEV(360, &soc_lpsc_list[11]), + PSC_DEV(99, &soc_lpsc_list[12]), + PSC_DEV(98, &soc_lpsc_list[13]), + PSC_DEV(146, &soc_lpsc_list[14]), + PSC_DEV(354, &soc_lpsc_list[15]), + PSC_DEV(357, &soc_lpsc_list[15]), + PSC_DEV(4, &soc_lpsc_list[16]), + PSC_DEV(202, &soc_lpsc_list[17]), + PSC_DEV(203, &soc_lpsc_list[18]), +}; + +const struct ti_k3_pd_platdata j721s2_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = ARRAY_SIZE(soc_psc_list), + .num_pd = ARRAY_SIZE(soc_pd_list), + .num_lpsc = ARRAY_SIZE(soc_lpsc_list), + .num_devs = ARRAY_SIZE(soc_dev_list), +}; diff --git a/arch/arm/mach-k3/r5/lowlevel_init.S b/arch/arm/mach-k3/r5/lowlevel_init.S new file mode 100644 index 00000000000..463ab0de1bd --- /dev/null +++ b/arch/arm/mach-k3/r5/lowlevel_init.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ + * Lokesh Vutla + */ + +#include + +ENTRY(lowlevel_init) + + mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR + and r0, #0xff + cmp r0, #0x0 + bne park_cpu + bx lr +park_cpu: + wfi + b park_cpu + +ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-k3/r5/r5_mpu.c b/arch/arm/mach-k3/r5/r5_mpu.c new file mode 100644 index 00000000000..3dbbcaee5f3 --- /dev/null +++ b/arch/arm/mach-k3/r5/r5_mpu.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * K3: R5 MPU region definitions + * + * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ + * Lokesh Vutla + */ + +#include +#include +#include +#include + +struct mpu_region_config k3_mpu_regions[16] = { + /* + * Make all 4GB as Device Memory and not executable. We are overriding + * it with next region for any requirement. + */ + {0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW, SHARED_WRITE_BUFFERED, + REGION_4GB}, + + /* SPL code area marking it as WB and Write allocate. */ + {CONFIG_SPL_TEXT_BASE, REGION_1, XN_DIS, PRIV_RW_USR_RW, + O_I_WB_RD_WR_ALLOC, REGION_8MB}, + + /* U-Boot's code area marking it as WB and Write allocate */ + {CFG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW, + O_I_WB_RD_WR_ALLOC, REGION_2GB}, + /* mcu_r5fss0_core0 BTCM area marking it as WB and Write allocate. */ + {0x41010000, 3, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC, + REGION_8MB}, + {0x0, 4, 0x0, 0x0, 0x0, 0x0}, + {0x0, 5, 0x0, 0x0, 0x0, 0x0}, + {0x0, 6, 0x0, 0x0, 0x0, 0x0}, + {0x0, 7, 0x0, 0x0, 0x0, 0x0}, + {0x0, 8, 0x0, 0x0, 0x0, 0x0}, + {0x0, 9, 0x0, 0x0, 0x0, 0x0}, + {0x0, 10, 0x0, 0x0, 0x0, 0x0}, + {0x0, 11, 0x0, 0x0, 0x0, 0x0}, + {0x0, 12, 0x0, 0x0, 0x0, 0x0}, + {0x0, 13, 0x0, 0x0, 0x0, 0x0}, + {0x0, 14, 0x0, 0x0, 0x0, 0x0}, + {0x0, 15, 0x0, 0x0, 0x0, 0x0}, +}; + +void setup_k3_mpu_regions(void) +{ + setup_mpu_regions(k3_mpu_regions, ARRAY_SIZE(k3_mpu_regions)); +} diff --git a/arch/arm/mach-k3/r5_mpu.c b/arch/arm/mach-k3/r5_mpu.c deleted file mode 100644 index 2de5d28aebf..00000000000 --- a/arch/arm/mach-k3/r5_mpu.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * K3: R5 MPU region definitions - * - * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ - * Lokesh Vutla - */ - -#include -#include -#include "common.h" - -struct mpu_region_config k3_mpu_regions[16] = { - /* - * Make all 4GB as Device Memory and not executable. We are overriding - * it with next region for any requirement. - */ - {0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW, SHARED_WRITE_BUFFERED, - REGION_4GB}, - - /* SPL code area marking it as WB and Write allocate. */ - {CONFIG_SPL_TEXT_BASE, REGION_1, XN_DIS, PRIV_RW_USR_RW, - O_I_WB_RD_WR_ALLOC, REGION_8MB}, - - /* U-Boot's code area marking it as WB and Write allocate */ - {CFG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW, - O_I_WB_RD_WR_ALLOC, REGION_2GB}, - /* mcu_r5fss0_core0 BTCM area marking it as WB and Write allocate. */ - {0x41010000, 3, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC, - REGION_8MB}, - {0x0, 4, 0x0, 0x0, 0x0, 0x0}, - {0x0, 5, 0x0, 0x0, 0x0, 0x0}, - {0x0, 6, 0x0, 0x0, 0x0, 0x0}, - {0x0, 7, 0x0, 0x0, 0x0, 0x0}, - {0x0, 8, 0x0, 0x0, 0x0, 0x0}, - {0x0, 9, 0x0, 0x0, 0x0, 0x0}, - {0x0, 10, 0x0, 0x0, 0x0, 0x0}, - {0x0, 11, 0x0, 0x0, 0x0, 0x0}, - {0x0, 12, 0x0, 0x0, 0x0, 0x0}, - {0x0, 13, 0x0, 0x0, 0x0, 0x0}, - {0x0, 14, 0x0, 0x0, 0x0, 0x0}, - {0x0, 15, 0x0, 0x0, 0x0, 0x0}, -}; - -void setup_k3_mpu_regions(void) -{ - setup_mpu_regions(k3_mpu_regions, ARRAY_SIZE(k3_mpu_regions)); -} -- cgit v1.2.3