From 0f61de8d9dba4ebfc4ea4b2da7f91adc937b3875 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 17 Dec 2014 15:50:37 +0800 Subject: x86: Convert microcode format to device-tree-only To avoid having two microcode formats, adjust the build system to support obtaining the microcode from the device tree, even in the case where it must be made available before the device tree can be accessed. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- Makefile | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Makefile') diff --git a/Makefile b/Makefile index 1560bff2d88..bda8222af43 100644 --- a/Makefile +++ b/Makefile @@ -947,7 +947,9 @@ ifneq ($(CONFIG_X86_RESET_VECTOR),) rom: u-boot.rom FORCE IFDTOOL=$(objtree)/tools/ifdtool -IFDTOOL_FLAGS = -w $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin +IFDTOOL_FLAGS = -f 0:$(objtree)/u-boot.dtb +IFDTOOL_FLAGS += -m 0x$(shell $(NM) u-boot |grep _dt_ucode_base_size |cut -d' ' -f1) +IFDTOOL_FLAGS += -U $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot.bin IFDTOOL_FLAGS += -w $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin ifneq ($(CONFIG_HAVE_INTEL_ME),) -- cgit v1.3.1 From 8c5224c9f5c8a24ff5153f018e10a3ac4da5783a Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 17 Dec 2014 15:50:42 +0800 Subject: x86: Use consistent name XXX_ADDR for binary blob flash address Signed-off-by: Bin Meng Acked-by: Simon Glass --- Makefile | 2 +- arch/x86/cpu/ivybridge/sdram.c | 2 +- arch/x86/cpu/queensbay/Kconfig | 4 ++-- arch/x86/cpu/queensbay/fsp_support.c | 2 +- arch/x86/cpu/queensbay/tnc_car.S | 2 +- include/configs/chromebook_link.h | 2 +- 6 files changed, 7 insertions(+), 7 deletions(-) (limited to 'Makefile') diff --git a/Makefile b/Makefile index bda8222af43..d962576c34f 100644 --- a/Makefile +++ b/Makefile @@ -958,7 +958,7 @@ IFDTOOL_ME_FLAGS += -i ME:$(srctree)/board/$(BOARDDIR)/me.bin endif ifneq ($(CONFIG_HAVE_MRC),) -IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin +IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin endif ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),) diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index df2b9901fc0..b95e781bbfb 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -177,7 +177,7 @@ int sdram_initialise(struct pei_data *pei_data) debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data)); - data = (char *)CONFIG_X86_MRC_START; + data = (char *)CONFIG_X86_MRC_ADDR; if (data) { int rv; int (*func)(struct pei_data *); diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig index 56fe85ccad0..f6b52010c37 100644 --- a/arch/x86/cpu/queensbay/Kconfig +++ b/arch/x86/cpu/queensbay/Kconfig @@ -29,7 +29,7 @@ config FSP_FILE The filename of the file to use as Firmware Support Package binary in the board directory. -config FSP_LOCATION +config FSP_ADDR hex "Firmware Support Package binary location" depends on HAVE_FSP default 0xfffc0000 @@ -65,7 +65,7 @@ config CMC_FILE The filename of the file to use as Chipset Micro Code state machine binary in the board directory. -config CMC_LOCATION +config CMC_ADDR hex "Chipset Micro Code state machine binary location" depends on HAVE_CMC default 0xfffb0000 diff --git a/arch/x86/cpu/queensbay/fsp_support.c b/arch/x86/cpu/queensbay/fsp_support.c index df3bbd07c9e..f830eeb33da 100644 --- a/arch/x86/cpu/queensbay/fsp_support.c +++ b/arch/x86/cpu/queensbay/fsp_support.c @@ -64,7 +64,7 @@ u32 __attribute__((optimize("O0"))) find_fsp_header(void) volatile register u8 *fsp asm("eax"); /* Initalize the FSP base */ - fsp = (u8 *)CONFIG_FSP_LOCATION; + fsp = (u8 *)CONFIG_FSP_ADDR; /* Check the FV signature, _FVH */ if (((struct fv_header_t *)fsp)->sign == 0x4856465F) { diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/cpu/queensbay/tnc_car.S index 2e9139eb8c2..5e09568b85b 100644 --- a/arch/x86/cpu/queensbay/tnc_car.S +++ b/arch/x86/cpu/queensbay/tnc_car.S @@ -29,7 +29,7 @@ find_fsp_header_ret: mov %eax, %ebp /* sanity test */ - cmp $CONFIG_FSP_LOCATION, %eax + cmp $CONFIG_FSP_ADDR, %eax jb die /* calculate TempRamInitEntry address */ diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 645b31c2e28..c9d84e4f062 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -25,7 +25,7 @@ #define CONFIG_X86_RESET_VECTOR #define CONFIG_NR_DRAM_BANKS 8 -#define CONFIG_X86_MRC_START 0xfffa0000 +#define CONFIG_X86_MRC_ADDR 0xfffa0000 #define CONFIG_CACHE_MRC_SIZE_KB 512 #define CONFIG_COREBOOT_SERIAL -- cgit v1.3.1 From 63faf2507d263bbd6285b3fe637fd80df05a58a0 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 17 Dec 2014 15:50:43 +0800 Subject: x86: Include FSP and CMC binary in the u-boot.rom build rules Signed-off-by: Bin Meng Acked-by: Simon Glass --- Makefile | 10 +++++++++- include/configs/chromebook_link.h | 2 +- 2 files changed, 10 insertions(+), 2 deletions(-) (limited to 'Makefile') diff --git a/Makefile b/Makefile index d962576c34f..397edc19e2e 100644 --- a/Makefile +++ b/Makefile @@ -961,8 +961,16 @@ ifneq ($(CONFIG_HAVE_MRC),) IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin endif +ifneq ($(CONFIG_HAVE_FSP),) +IFDTOOL_FLAGS += -w $(CONFIG_FSP_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_FSP_FILE) +endif + +ifneq ($(CONFIG_HAVE_CMC),) +IFDTOOL_FLAGS += -w $(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE) +endif + ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),) -IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILENAME) +IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILE) endif quiet_cmd_ifdtool = IFDTOOL $@ diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index c9d84e4f062..b311f4c5e6f 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -39,7 +39,7 @@ {PCI_VENDOR_ID_INTEL, \ PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} -#define CONFIG_X86_OPTION_ROM_FILENAME pci8086,0166.bin +#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin #define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 #define CONFIG_VIDEO_X86 -- cgit v1.3.1 From 125738e819a3b9d15210794b3dcef9f4d9bcf866 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 29 Dec 2014 21:22:38 -0500 Subject: Prepare v2015.01-rc4 Signed-off-by: Tom Rini --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Makefile') diff --git a/Makefile b/Makefile index 397edc19e2e..1eb68219aed 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ VERSION = 2015 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc3 +EXTRAVERSION = -rc4 NAME = # *DOCUMENTATION* -- cgit v1.3.1