From fed36ac5ae613773b6cd90e61e292c45440e10c8 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 20 Nov 2008 09:57:47 +0100 Subject: powerpc: 83xx: add support for the kmeter1 board This patch adds support for the kmeter1 board from Keymile, based on a Freescale MPC8360 CPU. - serial console on UART 1 - 256 MB DDR2 RAM - 64 MB NOR Flash - Ethernet RMII Mode over UCC4 - PHY SMSC LAN8700 Signed-off-by: Heiko Schocher Signed-off-by: Kim Phillips --- Makefile | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Makefile') diff --git a/Makefile b/Makefile index fd521b6b56a..1fe8f70215b 100644 --- a/Makefile +++ b/Makefile @@ -2175,6 +2175,9 @@ TASREG_config : unconfig ## MPC83xx Systems ######################################################################### +kmeter1_config: unconfig + @$(MKCONFIG) kmeter1 ppc mpc83xx kmeter1 keymile + MPC8313ERDB_33_config \ MPC8313ERDB_66_config \ MPC8313ERDB_NAND_33_config \ -- cgit v1.3.1 From 8fab49ea911fe925392fa5afcc9bc7373a3d0cee Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 25 Nov 2008 11:42:20 +0100 Subject: microblaze: Remove XUPV2P board --- Microblaze platforms use generic settings and to have many platforms is confusing that's why I decided to remove this platform from U-BOOT. ml401 tree is sufficient for covering all Microblaze platforms. This change will go through microblaze custodian tree. --- MAINTAINERS | 1 - MAKEALL | 1 - Makefile | 5 - board/xilinx/xupv2p/Makefile | 50 --------- board/xilinx/xupv2p/config.mk | 32 ------ board/xilinx/xupv2p/u-boot.lds | 68 ------------ board/xilinx/xupv2p/xparameters.h | 58 ---------- board/xilinx/xupv2p/xupv2p.c | 49 --------- include/configs/xupv2p.h | 226 -------------------------------------- 9 files changed, 490 deletions(-) delete mode 100644 board/xilinx/xupv2p/Makefile delete mode 100644 board/xilinx/xupv2p/config.mk delete mode 100644 board/xilinx/xupv2p/u-boot.lds delete mode 100644 board/xilinx/xupv2p/xparameters.h delete mode 100644 board/xilinx/xupv2p/xupv2p.c delete mode 100644 include/configs/xupv2p.h (limited to 'Makefile') diff --git a/MAINTAINERS b/MAINTAINERS index 127604b0f70..f04879555a3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -704,7 +704,6 @@ Yasushi Shoji Michal Simek ML401 MicroBlaze - XUPV2P MicroBlaze ######################################################################### # Coldfire Systems: # diff --git a/MAKEALL b/MAKEALL index a16549c10db..cc49a98080c 100755 --- a/MAKEALL +++ b/MAKEALL @@ -698,7 +698,6 @@ LIST_nios2=" \ LIST_microblaze=" \ ml401 \ suzaku \ - xupv2p \ " ######################################################################### diff --git a/Makefile b/Makefile index f8fe29cf5ee..ca91f05a954 100644 --- a/Makefile +++ b/Makefile @@ -3153,11 +3153,6 @@ suzaku_config: unconfig @echo "#define CONFIG_SUZAKU 1" > $(obj)include/config.h @$(MKCONFIG) -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno -xupv2p_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_XUPV2P 1" > $(obj)include/config.h - @$(MKCONFIG) -a $(@:_config=) microblaze microblaze xupv2p xilinx - #======================================================================== # Blackfin #======================================================================== diff --git a/board/xilinx/xupv2p/Makefile b/board/xilinx/xupv2p/Makefile deleted file mode 100644 index 10b47b2ae54..00000000000 --- a/board/xilinx/xupv2p/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/xilinx/xupv2p/config.mk b/board/xilinx/xupv2p/config.mk deleted file mode 100644 index c07b0b35b18..00000000000 --- a/board/xilinx/xupv2p/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2007 Michal Simek -# -# Michal SIMEK -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# CAUTION: This file is automatically generated by libgen. -# Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4 -# - -TEXT_BASE = 0x38000000 - -PLATFORM_CPPFLAGS += -mno-xl-soft-mul -PLATFORM_CPPFLAGS += -mno-xl-soft-div -PLATFORM_CPPFLAGS += -mxl-barrel-shift diff --git a/board/xilinx/xupv2p/u-boot.lds b/board/xilinx/xupv2p/u-boot.lds deleted file mode 100644 index b38f6487725..00000000000 --- a/board/xilinx/xupv2p/u-boot.lds +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(microblaze) -ENTRY(_start) - -SECTIONS -{ - .text ALIGN(0x4): - { - __text_start = .; - cpu/microblaze/start.o (.text) - *(.text) - __text_end = .; - } - - .rodata ALIGN(0x4): - { - __rodata_start = .; - *(.rodata) - __rodata_end = .; - } - - .data ALIGN(0x4): - { - __data_start = .; - *(.data) - __data_end = .; - } - - .u_boot_cmd ALIGN(0x4): - { - . = .; - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } - - .bss ALIGN(0x4): - { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end = .; - } - __end = . ; -} diff --git a/board/xilinx/xupv2p/xparameters.h b/board/xilinx/xupv2p/xparameters.h deleted file mode 100644 index 9e5ebdabc11..00000000000 --- a/board/xilinx/xupv2p/xparameters.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * CAUTION: This file is automatically generated by libgen. - * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4 - */ - -/* System Clock Frequency */ -#define XILINX_CLOCK_FREQ 100000000 - -/* Interrupt controller is opb_intc_0 */ -#define XILINX_INTC_BASEADDR 0x41200000 -#define XILINX_INTC_NUM_INTR_INPUTS 11 - -/* Timer pheriphery is opb_timer_1 */ -#define XILINX_TIMER_BASEADDR 0x41c00000 -#define XILINX_TIMER_IRQ 1 - -/* Uart pheriphery is RS232_Uart_1 */ -#define XILINX_UARTLITE_BASEADDR 0x40600000 -#define XILINX_UARTLITE_BAUDRATE 115200 - -/* GPIO is LEDs_4Bit*/ -#define XILINX_GPIO_BASEADDR 0x40000000 - -/* FLASH doesn't exist none */ - -/* Main Memory is DDR_256MB_32MX64_rank1_row13_col10_cl2_5 */ -#define XILINX_RAM_START 0x30000000 -#define XILINX_RAM_SIZE 0x10000000 - -/* Sysace Controller is SysACE_CompactFlash */ -#define XILINX_SYSACE_BASEADDR 0x41800000 -#define XILINX_SYSACE_HIGHADDR 0x4180ffff -#define XILINX_SYSACE_MEM_WIDTH 16 - -/* Ethernet controller is Ethernet_MAC */ -#define XILINX_EMACLITE_BASEADDR 0x40C00000 diff --git a/board/xilinx/xupv2p/xupv2p.c b/board/xilinx/xupv2p/xupv2p.c deleted file mode 100644 index b1a76c0c514..00000000000 --- a/board/xilinx/xupv2p/xupv2p.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* This is a board specific file. It's OK to include board specific - * header files */ - -#include -#include - -void do_reset (void) -{ -#ifdef CONFIG_SYS_GPIO_0 - *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = - ++(*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR))); -#endif -#ifdef CONFIG_SYS_RESET_ADDRESS - puts ("Reseting board\n"); - asm ("bra r0"); -#endif -} - -int gpio_init (void) -{ -#ifdef CONFIG_SYS_GPIO_0 - *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = 0x0; -#endif - return 0; -} diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h deleted file mode 100644 index ed844bf9933..00000000000 --- a/include/configs/xupv2p.h +++ /dev/null @@ -1,226 +0,0 @@ -/* - * (C) Copyright 2007-2008 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "../board/xilinx/xupv2p/xparameters.h" - -#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */ -#define CONFIG_XUPV2P 1 - -/* uart */ -#ifdef XILINX_UARTLITE_BASEADDR -#define CONFIG_XILINX_UARTLITE -#define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR -#define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE -#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } -#else -#ifdef XILINX_UART16550_BASEADDR -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 4 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 XILINX_UART16550_BASEADDR -#define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 115200 } -#endif -#endif - -/* - * setting reset address - * - * TEXT_BASE is set to place, where the U-BOOT run in RAM, but - * if you want to store U-BOOT in flash, set CONFIG_SYS_RESET_ADDRESS - * to FLASH memory and after loading bitstream jump to FLASH. - * U-BOOT auto-relocate to TEXT_BASE. After RESET command Microblaze - * jump to CONFIG_SYS_RESET_ADDRESS where is the original U-BOOT code. - */ -/* #define CONFIG_SYS_RESET_ADDRESS 0x36000000 */ - -/* ethernet */ -#ifdef XILINX_EMAC_BASEADDR -#define CONFIG_XILINX_EMAC 1 -#define CONFIG_SYS_ENET -#else -#ifdef XILINX_EMACLITE_BASEADDR -#define CONFIG_XILINX_EMACLITE 1 -#define CONFIG_SYS_ENET -#endif -#endif -#undef ET_DEBUG - -/* gpio */ -#ifdef XILINX_GPIO_BASEADDR -#define CONFIG_SYS_GPIO_0 1 -#define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR -#endif - -/* interrupt controller */ -#ifdef XILINX_INTC_BASEADDR -#define CONFIG_SYS_INTC_0 1 -#define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR -#define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS -#endif - -/* timer */ -#ifdef XILINX_TIMER_BASEADDR -#if (XILINX_TIMER_IRQ != -1) -#define CONFIG_SYS_TIMER_0 1 -#define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR -#define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ -#define FREQUENCE XILINX_CLOCK_FREQ -#define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) -#endif -#else -#ifdef XILINX_CLOCK_FREQ -#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ -#else -#error BAD CLOCK FREQ -#endif -#endif -/* - * memory layout - Example - * TEXT_BASE = 0x3600_0000; - * CONFIG_SYS_SRAM_BASE = 0x3000_0000; - * CONFIG_SYS_SRAM_SIZE = 0x1000_0000; - * - * CONFIG_SYS_GBL_DATA_OFFSET = 0x3000_0000 + 0x1000_0000 - 0x1000 = 0x3FFF_F000 - * CONFIG_SYS_MONITOR_BASE = 0x3FFF_F000 - 0x40000 = 0x3FFB_F000 - * CONFIG_SYS_MALLOC_BASE = 0x3FFB_F000 - 0x40000 = 0x3FF7_F000 - * - * 0x3000_0000 CONFIG_SYS_SDRAM_BASE - * FREE - * 0x3600_0000 TEXT_BASE - * U-BOOT code - * 0x3602_0000 - * FREE - * - * STACK - * 0x3FF7_F000 CONFIG_SYS_MALLOC_BASE - * MALLOC_AREA 256kB Alloc - * 0x3FFB_F000 CONFIG_SYS_MONITOR_BASE - * MONITOR_CODE 256kB Env - * 0x3FFF_F000 CONFIG_SYS_GBL_DATA_OFFSET - * GLOBAL_DATA 4kB bd, gd - * 0x4000_0000 CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - */ - -/* ddr sdram - main memory */ -#define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START -#define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) - -/* global pointer */ -#define CONFIG_SYS_GBL_DATA_SIZE 0x1000 /* size of global data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) /* start of global data */ - -/* monitor code */ -#define SIZE 0x40000 -#define CONFIG_SYS_MONITOR_LEN SIZE -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_MONITOR_END (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_MALLOC_LEN SIZE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) - -/* stack */ -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MALLOC_BASE - -#define CONFIG_SYS_NO_FLASH 1 -#define CONFIG_ENV_IS_NOWHERE 1 -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_JFFS2 -#undef CONFIG_CMD_IMLS - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_IRQ - -#ifndef CONFIG_SYS_ENET - #undef CONFIG_CMD_NET -#else - #define CONFIG_CMD_PING -#endif - -#ifdef XILINX_SYSACE_BASEADDR -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_PROMPT "U-Boot-mONStR> " -#define CONFIG_SYS_CBSIZE 512 /* size of console buffer */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ -#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_LOAD_ADDR 0x12000000 /* default load address */ - -#define CONFIG_BOOTDELAY 30 -#define CONFIG_BOOTARGS "root=romfs" -#define CONFIG_HOSTNAME "xupv2p" -#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" -#define CONFIG_IPADDR 192.168.0.3 -#define CONFIG_SERVERIP 192.168.0.5 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_ETHADDR 00:E0:0C:00:00:FD - -/* architecture dependent code */ -#define CONFIG_SYS_USR_EXCEP /* user exception */ -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_PREBOOT "echo U-BOOT by mONStR;" \ - "base 0;" \ - "echo" - -/* system ace */ -#ifdef XILINX_SYSACE_BASEADDR -#define CONFIG_SYSTEMACE -/* #define DEBUG_SYSTEMACE */ -#define SYSTEMACE_CONFIG_FPGA -#define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR -#define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH -#define CONFIG_DOS_PARTITION -#endif - -#define CONFIG_CMDLINE_EDITING - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 1951f847f0a851853871b613ad7cf21a5242226c Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Wed, 10 Dec 2008 14:41:25 +0100 Subject: ppc4xx: Update TEXT_BASE for CPCI405 boards This patch fixes building U-Boot for CPCI405 boards. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- Makefile | 5 +---- board/esd/cpci405/config.mk | 6 +----- include/configs/CPCI405.h | 6 +++--- 3 files changed, 5 insertions(+), 12 deletions(-) (limited to 'Makefile') diff --git a/Makefile b/Makefile index f8fe29cf5ee..2f07657f5df 100644 --- a/Makefile +++ b/Makefile @@ -1261,14 +1261,11 @@ CMS700_config: unconfig CPCI2DP_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd -CPCI405_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd - +CPCI405_config \ CPCI4052_config \ CPCI405DT_config \ CPCI405AB_config: unconfig @mkdir -p $(obj)board/esd/cpci405 - @echo "TEXT_BASE = 0xFFFC0000" > $(obj)board/esd/cpci405/config.tmp @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd CPCIISER4_config: unconfig diff --git a/board/esd/cpci405/config.mk b/board/esd/cpci405/config.mk index 6cfb8912ddd..1bdf5e4fcf3 100644 --- a/board/esd/cpci405/config.mk +++ b/board/esd/cpci405/config.mk @@ -21,8 +21,4 @@ # MA 02111-1307 USA # -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -ifndef TEXT_BASE -TEXT_BASE = 0xFFFD0000 -endif +TEXT_BASE = 0xFFFC0000 diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 1a2bc1c2e72..89ba139af78 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -196,9 +196,9 @@ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFD0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ +#define CONFIG_SYS_FLASH_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ /* -- cgit v1.3.1 From 9a1d3557dcd47365c12eeab584b822e57d994352 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Tue, 11 Nov 2008 22:20:15 +0100 Subject: sh: fix rsk7203 and MigoR out of tree build Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nobuhiro Iwamatsu --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Makefile') diff --git a/Makefile b/Makefile index f8fe29cf5ee..91acd14eefa 100644 --- a/Makefile +++ b/Makefile @@ -3210,7 +3210,7 @@ mimc200_config : unconfig rsk7203_config: unconfig @ >include/config.h @echo "#define CONFIG_RSK7203 1" >> include/config.h - @./mkconfig -a $(@:_config=) sh sh2 rsk7203 renesas + @$(MKCONFIG) -a $(@:_config=) sh sh2 rsk7203 renesas ######################################################################### ## sh3 (Renesas SuperH) @@ -3233,7 +3233,7 @@ ms7720se_config: unconfig MigoR_config : unconfig @mkdir -p $(obj)include @echo "#define CONFIG_MIGO_R 1" > $(obj)include/config.h - @./mkconfig -a $(@:_config=) sh sh4 MigoR renesas + @$(MKCONFIG) -a $(@:_config=) sh sh4 MigoR renesas ms7750se_config: unconfig @mkdir -p $(obj)include -- cgit v1.3.1 From 4a0f7538c5c0805fd9a791967bbabacc41deadd9 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 16 Dec 2008 14:41:02 +0100 Subject: Makefile: fix dependency problem with parallel builds Parallel builds (using "make -jN") would occasionally fail with error messages like include/autoconf.mk:212: *** missing separator. Stop. Line numbers and affected boards were changing. Obviously some Makefiles included autoconf.mk while it was still being written to. As a fix, we now write to a temporary file first and then rename it, so that it is really ready to use as soon as it appears. Signed-off-by: Wolfgang Denk --- Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Makefile') diff --git a/Makefile b/Makefile index d6cd91a511f..1fd03a032dd 100644 --- a/Makefile +++ b/Makefile @@ -463,7 +463,8 @@ $(obj)include/autoconf.mk: $(obj)include/config.h set -e ; \ : Extract the config macros ; \ $(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM include/common.h | \ - sed -n -f tools/scripts/define2mk.sed > $@ + sed -n -f tools/scripts/define2mk.sed > $@.tmp && \ + mv $@.tmp $@ sinclude $(obj)include/autoconf.mk.dep -- cgit v1.3.1 From aced78d852d0b009e8aaa1445af8cb40861ee549 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 16 Dec 2008 23:48:27 +0100 Subject: Prepare 2009.01-rc1 Signed-off-by: Wolfgang Denk --- CHANGELOG | 102 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Makefile | 6 ++-- 2 files changed, 105 insertions(+), 3 deletions(-) (limited to 'Makefile') diff --git a/CHANGELOG b/CHANGELOG index 0c9c0479c83..9af36c123bf 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,105 @@ +commit 9e2a79b4c585ad31138fb90b68fd0234d64a8da8 +Author: Wolfgang Denk +Date: Tue Dec 16 23:13:46 2008 +0100 + + include/configs/at91cap9adk.h: fix typo. + + Signed-off-by: Wolfgang Denk + +commit 45ca04f2377361593151d2d4da51f8ba4832d233 +Author: Wolfgang Denk +Date: Tue Dec 16 22:32:25 2008 +0100 + + board/trab/memory.c: Fix compile problems. + + Apply changes from commit 44b4dbed to board/trab/memory.c, too. + + Actually we'd need a major cleanup here - as it turns out, + board/trab/memory.c is more or less a verbatim copy of + post/drivers/memory.c ... but then, trab is EOL anyway,r + so this is not worth the effort. + + Signed-off-by: Wolfgang Denk + +commit 584eedab66d0828f2d571a24b10526c4e65f547b +Author: Ilya Yanok +Date: Thu Dec 11 05:51:57 2008 +0300 + + jffs2: include instead of defining own min_t + + Include header for min_t definition instead of + providing our own one. Removes warnings in case of OneNAND support + enabled. + + Although I thinks it's a bit silly to include + just for min_t... + + Signed-off-by: Ilya Yanok + Acked-by: Stefan Roese + +commit b1ffecec37b57a59c139042267faac458e5324e9 +Author: Becky Bruce +Date: Wed Dec 3 23:04:37 2008 -0600 + + powerpc: fix io.h build warning with CONFIG_PHYS_64BIT + + Casting a pointer to a phys_addr_t when it's an unsigned long long + on a 32-bit system without first casting to a non-pointer type + generates a compiler warning. Fix this. + + Signed-off-by: Becky Bruce + +commit 6cdadcb3f1b6eac4a1c4256acaa1438413f95351 +Author: Wolfgang Denk +Date: Tue Dec 16 16:22:50 2008 +0100 + + trab: make trab_fkt standalone code independent of libgcc + + Use our own local functions in lib_arm/ instead. + + Signed-off-by: Wolfgang Denk + +commit aa1bcca3d2e22af4dea9f02132f9b56a30378ded +Author: Wolfgang Denk +Date: Tue Dec 16 14:44:06 2008 +0100 + + post/Makefile: fix dependency problem with parallel builds + + Parallel builds (using "make -jN") would occasionally fail with error + messages like + ppc_4xxFP-objdump: string.o: File format not recognized + or + post/libpost.a(cpu.o): In function `cpu_post_test': + /home/wd/git/u-boot/work/post/lib_ppc/cpu.c:130: undefined reference to `cpu_post_test_string' + or similar. We now make sure to run the 'postdeps" step before + attempting to build the specific POST libraries. + + Signed-off-by: Wolfgang Denk + +commit 4a0f7538c5c0805fd9a791967bbabacc41deadd9 +Author: Wolfgang Denk +Date: Tue Dec 16 14:41:02 2008 +0100 + + Makefile: fix dependency problem with parallel builds + + Parallel builds (using "make -jN") would occasionally fail with error + messages like + include/autoconf.mk:212: *** missing separator. Stop. + Line numbers and affected boards were changing. Obviously some + Makefiles included autoconf.mk while it was still being written to. + As a fix, we now write to a temporary file first and then rename it, + so that it is really ready to use as soon as it appears. + + Signed-off-by: Wolfgang Denk + +commit 455ae7e87f67c44e6aea68865c83acadd3fcd36c +Author: Wolfgang Denk +Date: Tue Dec 16 01:02:17 2008 +0100 + + Coding style cleanup, update CHANGELOG. + + Signed-off-by: Wolfgang Denk + commit 84bc72d90c505fec3ef4b693995407a0bd4064e5 Author: Mike Frysinger Date: Thu Dec 11 18:39:08 2008 -0500 diff --git a/Makefile b/Makefile index 1fd03a032dd..4df48129b8c 100644 --- a/Makefile +++ b/Makefile @@ -21,10 +21,10 @@ # MA 02111-1307 USA # -VERSION = 2008 -PATCHLEVEL = 10 +VERSION = 2009 +PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = +EXTRAVERSION = -rc1 ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else -- cgit v1.3.1 From e92739d34e2d6b6aca93b2598248210710897ce8 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Wed, 17 Dec 2008 16:36:21 -0600 Subject: Add support for PCA953x I2C gpio devices Initial support for NXP's 4 and 8 bit I2C gpio expanders (eg pca9537, pca9557, etc). The CONFIG_PCA953X define enables support for the devices while the CONFIG_CMD_PCA953X define enables the pca953x command. The CONFIG_CMD_PCA953X_INFO define enables an 'info' sub-command which provides summary information for the given pca953x device. Signed-off-by: Peter Tyser --- Makefile | 2 + README | 9 ++ drivers/gpio/Makefile | 47 ++++++++++ drivers/gpio/pca953x.c | 227 +++++++++++++++++++++++++++++++++++++++++++++++++ include/pca953x.h | 39 +++++++++ 5 files changed, 324 insertions(+) create mode 100644 drivers/gpio/Makefile create mode 100644 drivers/gpio/pca953x.c create mode 100644 include/pca953x.h (limited to 'Makefile') diff --git a/Makefile b/Makefile index 4df48129b8c..0fc64902f1c 100644 --- a/Makefile +++ b/Makefile @@ -228,6 +228,7 @@ LIBS += drivers/bios_emulator/libatibiosemu.a LIBS += drivers/block/libblock.a LIBS += drivers/dma/libdma.a LIBS += drivers/fpga/libfpga.a +LIBS += drivers/gpio/libgpio.a LIBS += drivers/hwmon/libhwmon.a LIBS += drivers/i2c/libi2c.a LIBS += drivers/input/libinput.a @@ -407,6 +408,7 @@ TAG_SUBDIRS += disk TAG_SUBDIRS += common TAG_SUBDIRS += drivers/bios_emulator TAG_SUBDIRS += drivers/block +TAG_SUBDIRS += drivers/gpio TAG_SUBDIRS += drivers/hwmon TAG_SUBDIRS += drivers/i2c TAG_SUBDIRS += drivers/input diff --git a/README b/README index 2a553c274c3..eb86ebaf110 100644 --- a/README +++ b/README @@ -621,6 +621,8 @@ The following options need to be configured: CONFIG_CMD_MII * MII utility commands CONFIG_CMD_NAND * NAND support CONFIG_CMD_NET bootp, tftpboot, rarpboot + CONFIG_CMD_PCA953X * PCA953x I2C gpio commands + CONFIG_CMD_PCA953X_INFO * PCA953x I2C gpio info command CONFIG_CMD_PCI * pciinfo CONFIG_CMD_PCMCIA * PCMCIA support CONFIG_CMD_PING * send ICMP ECHO_REQUEST to network @@ -698,6 +700,13 @@ The following options need to be configured: Note that if the RTC uses I2C, then the I2C interface must also be configured. See I2C Support, below. +- GPIO Support: + CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO + CONFIG_PCA953X_INFO - enable pca953x info command + + Note that if the GPIO device uses I2C, then the I2C interface + must also be configured. See I2C Support, below. + - Timestamp Support: When CONFIG_TIMESTAMP is selected, the timestamp diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile new file mode 100644 index 00000000000..dd618ed71c7 --- /dev/null +++ b/drivers/gpio/Makefile @@ -0,0 +1,47 @@ +# +# Copyright 2000-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libgpio.a + +COBJS-$(CONFIG_PCA953X) += pca953x.o + +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################## diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c new file mode 100644 index 00000000000..390d99ad3d6 --- /dev/null +++ b/drivers/gpio/pca953x.c @@ -0,0 +1,227 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Driver for NXP's 4 and 8 bit I2C gpio expanders (eg pca9537, pca9557, etc) + * TODO: support additional devices with more than 8-bits GPIO + */ + +#include +#include +#include + +/* Default to an address that hopefully won't corrupt other i2c devices */ +#ifndef CONFIG_SYS_I2C_PCA953X_ADDR +#define CONFIG_SYS_I2C_PCA953X_ADDR (~0) +#endif + +enum { + PCA953X_CMD_INFO, + PCA953X_CMD_DEVICE, + PCA953X_CMD_OUTPUT, + PCA953X_CMD_INPUT, + PCA953X_CMD_INVERT, +}; + +/* + * Modify masked bits in register + */ +static int pca953x_reg_write(uint8_t chip, uint addr, uint mask, uint data) +{ + uint8_t val; + + if (i2c_read(chip, addr, 1, &val, 1)) + return -1; + + val &= ~mask; + val |= data; + + return i2c_write(chip, addr, 1, &val, 1); +} + +/* + * Set output value of IO pins in 'mask' to corresponding value in 'data' + * 0 = low, 1 = high + */ +int pca953x_set_val(uint8_t chip, uint mask, uint data) +{ + return pca953x_reg_write(chip, PCA953X_OUT, mask, data); +} + +/* + * Set read polarity of IO pins in 'mask' to corresponding value in 'data' + * 0 = read pin value, 1 = read inverted pin value + */ +int pca953x_set_pol(uint8_t chip, uint mask, uint data) +{ + return pca953x_reg_write(chip, PCA953X_POL, mask, data); +} + +/* + * Set direction of IO pins in 'mask' to corresponding value in 'data' + * 0 = output, 1 = input + */ +int pca953x_set_dir(uint8_t chip, uint mask, uint data) +{ + return pca953x_reg_write(chip, PCA953X_CONF, mask, data); +} + +/* + * Read current logic level of all IO pins + */ +int pca953x_get_val(uint8_t chip) +{ + uint8_t val; + + if (i2c_read(chip, 0, 1, &val, 1)) + return -1; + + return (int)val; +} + +#ifdef CONFIG_CMD_PCA953X +#ifdef CONFIG_CMD_PCA953X_INFO +/* + * Display pca953x information + */ +static int pca953x_info(uint8_t chip) +{ + int i; + uint8_t data; + + printf("pca953x@ 0x%x:\n\n", chip); + printf("gpio pins: 76543210\n"); + printf("-------------------\n"); + + if (i2c_read(chip, PCA953X_CONF, 1, &data, 1)) + return -1; + printf("conf: "); + for (i = 7; i >= 0; i--) + printf("%c", data & (1 << i) ? 'i' : 'o'); + printf("\n"); + + if (i2c_read(chip, PCA953X_POL, 1, &data, 1)) + return -1; + printf("invert: "); + for (i = 7; i >= 0; i--) + printf("%c", data & (1 << i) ? '1' : '0'); + printf("\n"); + + if (i2c_read(chip, PCA953X_IN, 1, &data, 1)) + return -1; + printf("input: "); + for (i = 7; i >= 0; i--) + printf("%c", data & (1 << i) ? '1' : '0'); + printf("\n"); + + if (i2c_read(chip, PCA953X_OUT, 1, &data, 1)) + return -1; + printf("output: "); + for (i = 7; i >= 0; i--) + printf("%c", data & (1 << i) ? '1' : '0'); + printf("\n"); + + return 0; +} +#endif /* CONFIG_CMD_PCA953X_INFO */ + +cmd_tbl_t cmd_pca953x[] = { + U_BOOT_CMD_MKENT(device, 3, 0, (void *)PCA953X_CMD_DEVICE, "", ""), + U_BOOT_CMD_MKENT(output, 4, 0, (void *)PCA953X_CMD_OUTPUT, "", ""), + U_BOOT_CMD_MKENT(input, 3, 0, (void *)PCA953X_CMD_INPUT, "", ""), + U_BOOT_CMD_MKENT(invert, 4, 0, (void *)PCA953X_CMD_INVERT, "", ""), +#ifdef CONFIG_CMD_PCA953X_INFO + U_BOOT_CMD_MKENT(info, 2, 0, (void *)PCA953X_CMD_INFO, "", ""), +#endif +}; + +int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + static uint8_t chip = CONFIG_SYS_I2C_PCA953X_ADDR; + int val; + ulong ul_arg2 = 0; + ulong ul_arg3 = 0; + cmd_tbl_t *c; + + c = find_cmd_tbl(argv[1], cmd_pca953x, ARRAY_SIZE(cmd_pca953x)); + + /* All commands but "device" require 'maxargs' arguments */ + if (!c || !((argc == (c->maxargs)) || + (((int)c->cmd == PCA953X_CMD_DEVICE) && + (argc == (c->maxargs - 1))))) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* arg2 used as chip number or pin number */ + if (argc > 2) + ul_arg2 = simple_strtoul(argv[2], NULL, 16); + + /* arg3 used as pin or invert value */ + if (argc > 3) + ul_arg3 = simple_strtoul(argv[3], NULL, 16) & 0x1; + + switch ((int)c->cmd) { +#ifdef CONFIG_CMD_PCA953X_INFO + case PCA953X_CMD_INFO: + return pca953x_info(chip); +#endif + case PCA953X_CMD_DEVICE: + if (argc == 3) + chip = (uint8_t)ul_arg2; + printf("Current device address: 0x%x\n", chip); + return 0; + case PCA953X_CMD_INPUT: + pca953x_set_dir(chip, (1 << ul_arg2), + PCA953X_DIR_IN << ul_arg2); + val = (pca953x_get_val(chip) & (1 << ul_arg2)) != 0; + + printf("chip 0x%02x, pin 0x%lx = %d\n", chip, ul_arg2, val); + return val; + case PCA953X_CMD_OUTPUT: + pca953x_set_dir(chip, (1 << ul_arg2), + (PCA953X_DIR_OUT << ul_arg2)); + return pca953x_set_val(chip, (1 << ul_arg2), + (ul_arg3 << ul_arg2)); + case PCA953X_CMD_INVERT: + return pca953x_set_pol(chip, (1 << ul_arg2), + (ul_arg3 << ul_arg2)); + default: + /* We should never get here */ + return 1; + } +} + +U_BOOT_CMD( + pca953x, 5, 1, do_pca953x, + "pca953x - pca953x gpio access\n", + "device [dev]\n" + " - show or set current device address\n" +#ifdef CONFIG_CMD_PCA953X_INFO + "pca953x info\n" + " - display info for current chip\n" +#endif + "pca953x output pin 0|1\n" + " - set pin as output and drive low or high\n" + "pca953x invert pin 0|1\n" + " - disable/enable polarity inversion for reads\n" + "pca953x intput pin\n" + " - set pin as input and read value\n" +); + +#endif /* CONFIG_CMD_PCA953X */ diff --git a/include/pca953x.h b/include/pca953x.h new file mode 100644 index 00000000000..6c2b58c563d --- /dev/null +++ b/include/pca953x.h @@ -0,0 +1,39 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __PCA953X_H_ +#define __PCA953X_H_ + +#define PCA953X_IN 0x00 +#define PCA953X_OUT 0x01 +#define PCA953X_POL 0x02 +#define PCA953X_CONF 0x03 + +#define PCA953X_OUT_LOW 0 +#define PCA953X_OUT_HIGH 1 +#define PCA953X_POL_NORMAL 0 +#define PCA953X_POL_INVERT 1 +#define PCA953X_DIR_OUT 0 +#define PCA953X_DIR_IN 1 + +int pca953x_set_val(u8 chip, uint mask, uint data); +int pca953x_set_pol(u8 chip, uint mask, uint data); +int pca953x_set_dir(u8 chip, uint mask, uint data); +int pca953x_get_val(u8 chip); + +#endif /* __PCA953X_H_ */ -- cgit v1.3.1 From ccf0fdd02b97323f8caae18d06cc9daeac2f192f Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Wed, 17 Dec 2008 16:36:23 -0600 Subject: XPedite5370 board support Initial support for Extreme Engineering Solutions XPedite5370 - a MPC8572-based 3U VPX single board computer with a PMC/XMC site. Signed-off-by: Peter Tyser --- MAINTAINERS | 3 + MAKEALL | 1 + Makefile | 3 + board/xes/common/Makefile | 56 ++++ board/xes/common/fsl_8572_clk.c | 51 ++++ board/xes/common/fsl_85xx_ddr.c | 93 ++++++ board/xes/common/fsl_85xx_pci.c | 265 ++++++++++++++++ board/xes/xpedite5370/Makefile | 45 +++ board/xes/xpedite5370/config.mk | 35 +++ board/xes/xpedite5370/ddr.c | 270 +++++++++++++++++ board/xes/xpedite5370/law.c | 54 ++++ board/xes/xpedite5370/tlb.c | 94 ++++++ board/xes/xpedite5370/u-boot.lds | 145 +++++++++ board/xes/xpedite5370/xpedite5370.c | 128 ++++++++ include/configs/XPEDITE5370.h | 589 ++++++++++++++++++++++++++++++++++++ 15 files changed, 1832 insertions(+) create mode 100644 board/xes/common/Makefile create mode 100644 board/xes/common/fsl_8572_clk.c create mode 100644 board/xes/common/fsl_85xx_ddr.c create mode 100644 board/xes/common/fsl_85xx_pci.c create mode 100644 board/xes/xpedite5370/Makefile create mode 100644 board/xes/xpedite5370/config.mk create mode 100644 board/xes/xpedite5370/ddr.c create mode 100644 board/xes/xpedite5370/law.c create mode 100644 board/xes/xpedite5370/tlb.c create mode 100644 board/xes/xpedite5370/u-boot.lds create mode 100644 board/xes/xpedite5370/xpedite5370.c create mode 100644 include/configs/XPEDITE5370.h (limited to 'Makefile') diff --git a/MAINTAINERS b/MAINTAINERS index f04879555a3..be10eb49a0c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -411,6 +411,9 @@ Rune Torgersen MPC8266ADS MPC8266 +Peter Tyser + + XPEDITE5370 MPC8572 David Updegraff diff --git a/MAKEALL b/MAKEALL index cc49a98080c..a136bad7a8a 100755 --- a/MAKEALL +++ b/MAKEALL @@ -385,6 +385,7 @@ LIST_85xx=" \ TQM8548 \ TQM8555 \ TQM8560 \ + XPEDITE5370 \ " ######################################################################### diff --git a/Makefile b/Makefile index 0fc64902f1c..752a370669f 100644 --- a/Makefile +++ b/Makefile @@ -2463,6 +2463,9 @@ TQM8560_config: unconfig echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h; @$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc +XPEDITE5370_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5370 xes + ######################################################################### ## MPC86xx Systems ######################################################################### diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile new file mode 100644 index 00000000000..c5cd6331ef7 --- /dev/null +++ b/board/xes/common/Makefile @@ -0,0 +1,56 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)board/$(VENDOR)/common) +endif + +LIB = $(obj)lib$(VENDOR).a + +COBJS-$(CONFIG_MPC8572) += fsl_8572_clk.o +COBJS-$(CONFIG_MPC85xx) += fsl_85xx_ddr.o +COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_85xx_pci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xes/common/fsl_8572_clk.c b/board/xes/common/fsl_8572_clk.c new file mode 100644 index 00000000000..f5df2dae847 --- /dev/null +++ b/board/xes/common/fsl_8572_clk.c @@ -0,0 +1,51 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config + */ +unsigned long get_board_sys_clk(ulong dummy) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 gpporcr = gur->gpporcr; + + if (gpporcr & 0x10000) + return 66666666; + else + return 50000000; +} + +/* + * Return DDR input clock - synchronous with SYSCLK or 66 MHz + */ +unsigned long get_board_ddr_clk(ulong dummy) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + + if (ddr_ratio == 0x7) + return get_board_sys_clk(dummy); + + return 66666666; +} diff --git a/board/xes/common/fsl_85xx_ddr.c b/board/xes/common/fsl_85xx_ddr.c new file mode 100644 index 00000000000..30b47670197 --- /dev/null +++ b/board/xes/common/fsl_85xx_ddr.c @@ -0,0 +1,93 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + + dram_size *= 0x100000; + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* Initialize and enable DDR ECC */ + ddr_enable_ecc(dram_size); +#endif + + return dram_size; +} + +#if defined(CONFIG_DDR_ECC) || (CONFIG_NUM_DDR_CONTROLLERS > 1) +void board_add_ram_info(int use_default) +{ +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) + volatile ccsr_ddr_t *ddr1 = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); +#endif + + puts(" ("); + +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) + /* Print interleaving information */ + if (ddr1->cs0_config & 0x20000000) { + switch ((ddr1->cs0_config >> 24) & 0xf) { + case 0: + puts("cache line"); + break; + case 1: + puts("page"); + break; + case 2: + puts("bank"); + break; + case 3: + puts("super-bank"); + break; + default: + puts("invalid"); + break; + } + } else { + puts("no"); + } + + puts(" interleaving"); +#endif + +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) && defined(CONFIG_DDR_ECC) + puts(", "); +#endif + +#if defined(CONFIG_DDR_ECC) + puts("ECC enabled"); +#endif + + puts(")"); +} +#endif /* CONFIG_DDR_ECC || CONFIG_NUM_DDR_CONTROLLERS > 1 */ diff --git a/board/xes/common/fsl_85xx_pci.c b/board/xes/common/fsl_85xx_pci.c new file mode 100644 index 00000000000..b8e363ec965 --- /dev/null +++ b/board/xes/common/fsl_85xx_pci.c @@ -0,0 +1,265 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +extern int fsl_pci_setup_inbound_windows(struct pci_region *r); +extern void fsl_pci_init(struct pci_controller *hose); + +int first_free_busno = 0; + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif +#ifdef CONFIG_PCIE3 +static struct pci_controller pcie3_hose; +#endif + +/* Correlate host/agent POR bits to usable info. Table 4-14 */ +struct host_agent_cfg_t { + uchar pcie_root[3]; + uchar rio_host; +} host_agent_cfg[8] = { + {{0, 0, 0}, 0}, + {{0, 1, 1}, 1}, + {{1, 0, 1}, 0}, + {{1, 1, 0}, 1}, + {{0, 0, 1}, 0}, + {{0, 1, 0}, 1}, + {{1, 0, 0}, 0}, + {{1, 1, 1}, 1} +}; + +/* Correlate port width POR bits to usable info. Table 4-15 */ +struct io_port_cfg_t { + uchar pcie_width[3]; + uchar rio_width; +} io_port_cfg[16] = { + {{0, 0, 0}, 0}, + {{0, 0, 0}, 0}, + {{4, 0, 0}, 0}, + {{4, 4, 0}, 0}, + {{0, 0, 0}, 0}, + {{0, 0, 0}, 0}, + {{0, 0, 0}, 4}, + {{4, 2, 2}, 0}, + {{0, 0, 0}, 0}, + {{0, 0, 0}, 0}, + {{0, 0, 0}, 0}, + {{4, 0, 0}, 4}, + {{4, 0, 0}, 4}, + {{0, 0, 0}, 4}, + {{0, 0, 0}, 4}, + {{8, 0, 0}, 0}, +}; + +void pci_init_board(void) +{ + struct pci_controller *hose; + volatile ccsr_fsl_pci_t *pci; + int width; + int host; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + struct pci_region *r; + + debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", + devdisr, io_sel, host_agent); + +#ifdef CONFIG_PCIE1 + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; + hose = &pcie1_hose; + host = host_agent_cfg[host_agent].pcie_root[0]; + width = io_port_cfg[io_sel].pcie_width[0]; + r = hose->regions; + + if (width && !(devdisr & MPC85xx_DEVDISR_PCIE)) { + printf("\n PCIE1 connected as %s (x%d)", + host ? "Root Complex" : "End Point", width); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + printf("\n"); + + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + + /* outbound memory */ + pci_set_region(r++, + CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno = hose->last_busno+1; + printf(" PCIE1 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif /* CONFIG_PCIE1 */ + +#ifdef CONFIG_PCIE2 + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; + hose = &pcie2_hose; + host = host_agent_cfg[host_agent].pcie_root[1]; + width = io_port_cfg[io_sel].pcie_width[1]; + r = hose->regions; + + if (width && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { + printf("\n PCIE2 connected as %s (x%d)", + host ? "Root Complex" : "End Point", width); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + printf("\n"); + + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + + /* outbound memory */ + pci_set_region(r++, + CONFIG_SYS_PCIE2_MEM_BASE, + CONFIG_SYS_PCIE2_MEM_PHYS, + CONFIG_SYS_PCIE2_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + CONFIG_SYS_PCIE2_IO_BASE, + CONFIG_SYS_PCIE2_IO_PHYS, + CONFIG_SYS_PCIE2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno = hose->last_busno+1; + printf(" PCIE2 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ +#endif /* CONFIG_PCIE2 */ + +#ifdef CONFIG_PCIE3 + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; + hose = &pcie3_hose; + host = host_agent_cfg[host_agent].pcie_root[2]; + width = io_port_cfg[io_sel].pcie_width[2]; + r = hose->regions; + + if (width && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { + printf("\n PCIE3 connected as %s (x%d)", + host ? "Root Complex" : "End Point", width); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + printf("\n"); + + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + + /* outbound memory */ + pci_set_region(r++, + CONFIG_SYS_PCIE3_MEM_BASE, + CONFIG_SYS_PCIE3_MEM_PHYS, + CONFIG_SYS_PCIE3_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + CONFIG_SYS_PCIE3_IO_BASE, + CONFIG_SYS_PCIE3_IO_PHYS, + CONFIG_SYS_PCIE3_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno = hose->last_busno+1; + printf(" PCIE3 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ +#endif /* CONFIG_PCIE3 */ +} + +#if defined(CONFIG_OF_BOARD_SETUP) +extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, + struct pci_controller *hose); + +void ft_board_pci_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_PCIE1 + ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); +#endif +#ifdef CONFIG_PCIE2 + ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); +#endif +#ifdef CONFIG_PCIE3 + ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); +#endif +} +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/xes/xpedite5370/Makefile b/board/xes/xpedite5370/Makefile new file mode 100644 index 00000000000..919397c40d5 --- /dev/null +++ b/board/xes/xpedite5370/Makefile @@ -0,0 +1,45 @@ +# +# Copyright 2008 Extreme Engineering Solutions, Inc. +# Copyright 2007 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xes/xpedite5370/config.mk b/board/xes/xpedite5370/config.mk new file mode 100644 index 00000000000..39469b22c86 --- /dev/null +++ b/board/xes/xpedite5370/config.mk @@ -0,0 +1,35 @@ +# +# Copyright 2008 Extreme Engineering Solutions, Inc. +# Copyright 2007-2008 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# xpedite5370 board +# +ifndef TEXT_BASE +TEXT_BASE = 0xfff80000 +endif + +PLATFORM_RELFLAGS += -mrelocatable + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8572=1 diff --git a/board/xes/xpedite5370/ddr.c b/board/xes/xpedite5370/ddr.c new file mode 100644 index 00000000000..4d3f255d705 --- /dev/null +++ b/board/xes/xpedite5370/ddr.c @@ -0,0 +1,270 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include +#include + +static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, + sizeof(ddr2_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0) + i2c_address = SPD_EEPROM_ADDRESS1; + if (ctrl_num == 1) + i2c_address = SPD_EEPROM_ADDRESS2; + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +/* + * There are four board-specific SDRAM timing parameters which must be + * calculated based on the particular PCB artwork. These are: + * 1.) CPO (Read Capture Delay) + * - TIMING_CFG_2 register + * Source: Calculation based on board trace lengths and + * chip-specific internal delays. + * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay) + * - TIMING_CFG_2 register + * Source: Calculation based on board trace lengths. + * Unless clock and DQ lanes are very different + * lengths (>2"), this should be set to the nominal value + * of 1/2 clock delay. + * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control) + * - DDR_SDRAM_CLK_CNTL register + * Source: Signal Integrity Simulations + * 4.) 2T Timing on Addr/Ctl + * - TIMING_CFG_2 register + * Source: Signal Integrity Simulations + * Usually only needed with heavy load/very high speed (>DDR2-800) + * + * ====== XPedite5370 DDR2-600 read delay calculations ====== + * + * See Freescale's App Note AN2583 as refrence. This document also + * contains the chip-specific delays for 8548E, 8572, etc. + * + * For MPC8572E + * Minimum chip delay (Ch 0): 1.372ns + * Maximum chip delay (Ch 0): 2.914ns + * Minimum chip delay (Ch 1): 1.220ns + * Maximum chip delay (Ch 1): 2.595ns + * + * CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps + * + * Minimum delay calc (Ch 0): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps + * = 3808ps + * = 3.808ns + * + * Maximum delay calc (Ch 0): + * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly + * 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps + * = 6240ps + * = 6.240ns + * + * Minimum delay calc (Ch 1): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps + * = 3288ps + * = 3.288ns + * + * Maximum delay calc (Ch 1): + * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps + * = 5536ps + * = 5.536ns + * + * Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target) + * This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8) + * Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target) + * This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7) + * + * + * ====== XPedite5370 DDR2-800 read delay calculations ====== + * + * See Freescale's App Note AN2583 as refrence. This document also + * contains the chip-specific delays for 8548E, 8572, etc. + * + * For MPC8572E + * Minimum chip delay (Ch 0): 1.372ns + * Maximum chip delay (Ch 0): 2.914ns + * Minimum chip delay (Ch 1): 1.220ns + * Maximum chip delay (Ch 1): 2.595ns + * + * CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps + * + * Minimum delay calc (Ch 0): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps + * = 3341ps + * = 3.341ns + * + * Maximum delay calc (Ch 0): + * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly + * 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps + * = 5673ps + * = 5.673ns + * + * Minimum delay calc (Ch 1): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps + * = 2822ps + * = 2.822ns + * + * Maximum delay calc (Ch 1): + * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps + * = 4968ps + * = 4.968ns + * + * Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target) + * This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9) + * Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target) + * This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8) + * + * Write latency (WR_DATA_DELAY) is calculated by doing the following: + * + * The DDR SDRAM specification requires DQS be received no sooner than + * 75% of an SDRAM clock period—and no later than 125% of a clock + * period—from the capturing clock edge of the command/address at the + * SDRAM. + * + * Based on the above tracelengths, the following are calculated: + * Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns + * Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns + * Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns + * Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns + * + * Difference in arrival time CLK vs. DQS: + * Ch. 0 0.072ns + * Ch. 1 0.138ns + * + * Both of these values are much less than 25% of the clock + * period at DDR2-600 or DDR2-800, so no additional delay is needed over + * the 1/2 cycle which normally aligns the first DQS transition + * exactly WL (CAS latency minus one cycle) after the CAS strobe. + * See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's + * terminology corresponds to exactly one clock period delay after + * the CAS strobe. (due to the fact that the "delay" is referenced + * from the *falling* edge of the CLK, just after the rising edge + * which the CAS strobe is latched on. + */ + +typedef struct board_memctl_options { + uint16_t datarate_mhz_low; + uint16_t datarate_mhz_high; + uint8_t clk_adjust; + uint8_t cpo_override; + uint8_t write_data_delay; +} board_memctl_options_t; + +static struct board_memctl_options bopts_ctrl[][2] = { + { + /* Controller 0 */ + { + /* DDR2 600/667 */ + .datarate_mhz_low = 500, + .datarate_mhz_high = 750, + .clk_adjust = 5, + .cpo_override = 8, + .write_data_delay = 2, + }, + { + /* DDR2 800 */ + .datarate_mhz_low = 750, + .datarate_mhz_high = 850, + .clk_adjust = 5, + .cpo_override = 9, + .write_data_delay = 2, + }, + }, + { + /* Controller 1 */ + { + /* DDR2 600/667 */ + .datarate_mhz_low = 500, + .datarate_mhz_high = 750, + .clk_adjust = 5, + .cpo_override = 7, + .write_data_delay = 2, + }, + { + /* DDR2 800 */ + .datarate_mhz_low = 750, + .datarate_mhz_high = 850, + .clk_adjust = 5, + .cpo_override = 8, + .write_data_delay = 2, + }, + }, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + struct board_memctl_options *bopts = bopts_ctrl[ctrl_num]; + sys_info_t sysinfo; + int i; + unsigned int datarate; + + get_sys_info(&sysinfo); + datarate = sysinfo.freqDDRBus / 1000 / 1000; + + for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) { + if ((bopts[i].datarate_mhz_low <= datarate) && + (bopts[i].datarate_mhz_high >= datarate)) { + debug("controller %d:\n", ctrl_num); + debug(" clk_adjust = %d\n", bopts[i].clk_adjust); + debug(" cpo = %d\n", bopts[i].cpo_override); + debug(" write_data_delay = %d\n", + bopts[i].write_data_delay); + popts->clk_adjust = bopts[i].clk_adjust; + popts->cpo_override = bopts[i].cpo_override; + popts->write_data_delay = bopts[i].write_data_delay; + } + } + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/xes/xpedite5370/law.c b/board/xes/xpedite5370/law.c new file mode 100644 index 00000000000..daee676c426 --- /dev/null +++ b/board/xes/xpedite5370/law.c @@ -0,0 +1,54 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_PCIE1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), +#endif +#ifdef CONFIG_SYS_PCIE2_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2), +#endif +#ifdef CONFIG_SYS_PCIE3_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite5370/tlb.c b/board/xes/xpedite5370/tlb.c new file mode 100644 index 00000000000..caafa3011bb --- /dev/null +++ b/board/xes/xpedite5370/tlb.c @@ -0,0 +1,94 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* W**G* - NOR flashes */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* *I*G* - NAND flash */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1M, 1), + +#ifdef CONFIG_PCIE1 + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), +#endif + +#ifdef CONFIG_PCIE2 + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), +#endif + +#ifdef CONFIG_PCIE3 + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), +#endif + +#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3) + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_64M, 1), +#endif + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/xes/xpedite5370/u-boot.lds b/board/xes/xpedite5370/u-boot.lds new file mode 100644 index 00000000000..cb399120d4a --- /dev/null +++ b/board/xes/xpedite5370/u-boot.lds @@ -0,0 +1,145 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) + 0x7f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } :text = 0xffff + + .resetvec ADDR(.text) + 0x7fffc : + { + *(.resetvec) + } :text = 0xffff + + . = ADDR(.text) + 0x80000; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xes/xpedite5370/xpedite5370.c b/board/xes/xpedite5370/xpedite5370.c new file mode 100644 index 00000000000..487509527fe --- /dev/null +++ b/board/xes/xpedite5370/xpedite5370.c @@ -0,0 +1,128 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +extern void ft_board_pci_setup(void *blob, bd_t *bd); + +int checkboard(void) +{ + char *s; + + printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME); + printf(" "); + s = getenv("board_rev"); + if (s) + printf("Rev %s, ", s); + s = getenv("serial#"); + if (s) + printf("Serial# %s, ", s); + s = getenv("board_cfg"); + if (s) + printf("Cfg %s", s); + printf("\n"); + + return 0; +} + +static void flash_cs_fixup(void) +{ + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + int flash_sel; + + /* + * Print boot dev and swap flash flash chip selects if booted from 2nd + * flash. Swapping chip selects presents user with a common memory + * map regardless of which flash was booted from. + */ + flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & + CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS)); + printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); + + if (flash_sel) { + lbc->br0 = CONFIG_SYS_BR1_PRELIM; + lbc->or0 = CONFIG_SYS_OR1_PRELIM; + + lbc->br1 = CONFIG_SYS_BR0_PRELIM; + lbc->or1 = CONFIG_SYS_OR0_PRELIM; + } +} + +int board_early_init_r(void) +{ + /* Initialize PCA9557 devices */ + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + + /* + * Remap NOR flash region to caching-inhibited + * so that flash can be erased/programmed properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* Invalidate existing TLB entry for NOR flash */ + disable_tlb(0); + set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1); + + flash_cs_fixup(); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_PCI + ft_board_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); +} +#endif + +#ifdef CONFIG_MP +extern void cpu_mp_lmb_reserve(struct lmb *lmb); + +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} +#endif diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h new file mode 100644 index 00000000000..3bc0fe8f676 --- /dev/null +++ b/include/configs/XPEDITE5370.h @@ -0,0 +1,589 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * xpedite5370 board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ +#define CONFIG_MPC8572 1 +#define CONFIG_XPEDITE5370 1 +#define CONFIG_SYS_BOARD_NAME "XPedite5370" +#define CONFIG_NUM_CPUS 2 /* 2 Cores */ +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ +#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */ + +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + +/* + * DDR config + */ +#define CONFIG_FSL_DDR2 +#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ +#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ +#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM + +#ifndef __ASSEMBLY__ +extern unsigned long get_board_sys_clk(unsigned long dummy); +extern unsigned long get_board_ddr_clk(unsigned long dummy); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) + +/* + * Diagnostics + */ +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x20000000 + +/* + * Memory map + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable + * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable + * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable + * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable + * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable + * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable + * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable + * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable + * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable + */ + +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) + +/* + * NAND flash configuration + */ +#define CONFIG_SYS_NAND_BASE 0xef800000 +#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ + +/* + * NOR flash configuration + */ +#define CONFIG_SYS_FLASH_BASE 0xf8000000 +#define CONFIG_SYS_FLASH_BASE2 0xf0000000 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ + {0xf7f40000, 0xc0000} } +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +/* + * Chip select configuration + */ +/* NOR Flash 0 on CS0 */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | \ + BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ + OR_GPCM_CSNT | \ + OR_GPCM_XACS | \ + OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_8 | \ + OR_GPCM_TRLX | \ + OR_GPCM_EHTR | \ + OR_GPCM_EAD) + +/* NOR Flash 1 on CS1 */ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ + BR_PS_16 | \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM + +/* NAND flash on CS2 */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ + (2< " + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +#define CONFIG_SYS_64BIT_VSPRINTF 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE + +/* PEX8518 slave I2C interface */ +#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 + +/* I2C DS1631 temperature sensor */ +#define CONFIG_SYS_I2C_DS1621_ADDR 0x48 +#define CONFIG_DTT_DS1621 +#define CONFIG_DTT_SENSORS { 0 } + +/* I2C EEPROM - AT24C128B */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ + +/* I2C RTC */ +#define CONFIG_RTC_M41T11 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 + +/* GPIO/EEPROM/SRAM */ +#define CONFIG_DS4510 +#define CONFIG_SYS_I2C_DS4510_ADDR 0x51 + +/* GPIO */ +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 +#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c +#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e +#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f +#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 + +/* + * PU = pulled high, PD = pulled low + * I = input, O = output, IO = input/output + */ +/* PCA9557 @ 0x18*/ +#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ +#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ +#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ +#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ +#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ +#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ +#define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */ +#define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */ + +/* PCA9557 @ 0x1c*/ +#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ +#define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */ +#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ +#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ +#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ +#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ +#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ +#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ + +/* PCA9557 @ 0x1e*/ +#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */ +#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */ + +/* PCA9557 @ 0x1f */ +#define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */ +#define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */ +#define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */ +#define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */ +#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */ + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +/* PCIE1 - VPX P1 */ +#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ + +/* PCIE2 - PEX8518 */ +#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ + +/* + * Networking options + */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_TSEC_TBI +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_ETHPRIME "eTSEC2" + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC1_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define CONFIG_HAS_ETH0 + +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_PHY_ADDR 2 +#define TSEC2_PHYIDX 0 +#define CONFIG_HAS_ETH1 + +/* + * Command configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DS4510 +#define CONFIG_CMD_DS4510_INFO +#define CONFIG_CMD_DTT +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SNTP + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ +#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ +#define CONFIG_PANIC_HANG /* do not reset board on panic */ +#define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 +#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ + +/* + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ +#define CONFIG_ENV_SIZE 0x8000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) + +/* + * Flash memory map: + * fff80000 - ffffffff Pri U-Boot (512 KB) + * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) + * fff00000 - fff3ffff Pri FDT (256KB) + * fef00000 - ffefffff Pri OS image (16MB) + * f8000000 - feefffff Pri OS Use/Filesystem (111MB) + * + * f7f80000 - f7ffffff Sec U-Boot (512 KB) + * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) + * f7f00000 - f7f3ffff Sec FDT (256KB) + * f6f00000 - f7efffff Sec OS image (16MB) + * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) + */ +#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000) +#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000) +#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000) +#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000) +#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000) +#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000) + +#define CONFIG_PROG_UBOOT1 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_UBOOT2 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_BOOT_OS_NET \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "if test -n $fdtaddr; then " \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "bootm $osaddr - $fdtaddr; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi; " \ + "else; " \ + "bootm $osaddr; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS1 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS2 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT1 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT2 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=yes\0" \ + "download_cmd=tftp\0" \ + "console_args=console=ttyS0,115200\0" \ + "root_args=root=/dev/nfs rw\0" \ + "misc_args=ip=on\0" \ + "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ + "bootfile=/home/user/file\0" \ + "osfile=/home/user/uImage-XPedite5370\0" \ + "fdtfile=/home/user/xpedite5370.dtb\0" \ + "ubootfile=/home/user/u-boot.bin\0" \ + "fdtaddr=c00000\0" \ + "osaddr=0x1000000\0" \ + "loadaddr=0x1000000\0" \ + "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ + "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ + "prog_os1="CONFIG_PROG_OS1"\0" \ + "prog_os2="CONFIG_PROG_OS2"\0" \ + "prog_fdt1="CONFIG_PROG_FDT1"\0" \ + "prog_fdt2="CONFIG_PROG_FDT2"\0" \ + "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ + "bootcmd_flash1=run set_bootargs; " \ + "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ + "bootcmd_flash2=run set_bootargs; " \ + "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ + "bootcmd=run bootcmd_flash1\0" +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 78bbc5ce151c5a484bb51bf1866b4a993ffc16ec Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 1 Dec 2008 13:47:13 -0600 Subject: XPedite5200 board support Initial support for Extreme Engineering Solutions XPedite5200 - a MPC8548-based PMC single board computer. Signed-off-by: Peter Tyser --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 ++ board/xes/common/Makefile | 3 +- board/xes/common/fsl_85xx_pci.c | 103 ++++++++++++++++++++++++++++++++++++++-- 5 files changed, 106 insertions(+), 5 deletions(-) (limited to 'Makefile') diff --git a/MAINTAINERS b/MAINTAINERS index be10eb49a0c..60def0c34d7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -413,6 +413,7 @@ Rune Torgersen Peter Tyser + XPEDITE5200 MPC8548 XPEDITE5370 MPC8572 David Updegraff diff --git a/MAKEALL b/MAKEALL index a136bad7a8a..5ce3f3112c9 100755 --- a/MAKEALL +++ b/MAKEALL @@ -385,6 +385,7 @@ LIST_85xx=" \ TQM8548 \ TQM8555 \ TQM8560 \ + XPEDITE5200 \ XPEDITE5370 \ " diff --git a/Makefile b/Makefile index 752a370669f..c532e5b146d 100644 --- a/Makefile +++ b/Makefile @@ -2463,6 +2463,9 @@ TQM8560_config: unconfig echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h; @$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc +XPEDITE5200_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5200 xes + XPEDITE5370_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5370 xes diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile index c5cd6331ef7..e7620f447f6 100644 --- a/board/xes/common/Makefile +++ b/board/xes/common/Makefile @@ -29,9 +29,10 @@ endif LIB = $(obj)lib$(VENDOR).a +COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_85xx_pci.o COBJS-$(CONFIG_MPC8572) += fsl_8572_clk.o COBJS-$(CONFIG_MPC85xx) += fsl_85xx_ddr.o -COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_85xx_pci.o +COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/xes/common/fsl_85xx_pci.c b/board/xes/common/fsl_85xx_pci.c index 4b048814e89..56f34479582 100644 --- a/board/xes/common/fsl_85xx_pci.c +++ b/board/xes/common/fsl_85xx_pci.c @@ -34,6 +34,9 @@ extern void fsl_pci_init(struct pci_controller *hose); int first_free_busno = 0; +#ifdef CONFIG_PCI1 +static struct pci_controller pci1_hose; +#endif #ifdef CONFIG_PCIE1 static struct pci_controller pcie1_hose; #endif @@ -44,6 +47,7 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif +#ifdef CONFIG_MPC8572 /* Correlate host/agent POR bits to usable info. Table 4-14 */ struct host_agent_cfg_t { uchar pcie_root[3]; @@ -81,6 +85,38 @@ struct io_port_cfg_t { {{0, 0, 0}, 4}, {{8, 0, 0}, 0}, }; +#elif defined CONFIG_MPC8548 +/* Correlate host/agent POR bits to usable info. Table 4-12 */ +struct host_agent_cfg_t { + uchar pci_host[2]; + uchar pcie_root[1]; + uchar rio_host; +} host_agent_cfg[8] = { + {{1, 1}, {0}, 0}, + {{1, 1}, {1}, 0}, + {{1, 1}, {0}, 1}, + {{0, 0}, {0}, 0}, /* reserved */ + {{0, 1}, {1}, 0}, + {{1, 1}, {1}, 0}, + {{0, 1}, {1}, 1}, + {{1, 1}, {1}, 1} +}; + +/* Correlate port width POR bits to usable info. Table 4-13 */ +struct io_port_cfg_t { + uchar pcie_width[1]; + uchar rio_width; +} io_port_cfg[8] = { + {{0}, 0}, + {{0}, 0}, + {{0}, 0}, + {{4}, 4}, + {{4}, 4}, + {{0}, 4}, + {{0}, 4}, + {{8}, 0}, +}; +#endif void pci_init_board(void) { @@ -94,9 +130,65 @@ void pci_init_board(void) uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; struct pci_region *r; - debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", - devdisr, io_sel, host_agent); +#ifdef CONFIG_PCI1 + uint pci_spd_norm = (gur->pordevsr & MPC85xx_PORDEVSR_PCI1_SPD); + uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + uint pcix = gur->pordevsr & MPC85xx_PORDEVSR_PCI1; + uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000; + + width = 0; /* Silence compiler warning... */ + io_sel &= 0xf; /* Silence compiler warning... */ + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; + hose = &pci1_hose; + host = host_agent_cfg[host_agent].pci_host[0]; + r = hose->regions; + + + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n", + pci_32 ? 32 : 64, + pcix ? "PCIX" : "PCI", + pci_spd_norm ? ">=" : "<=", + pcix ? freq * 2 : freq, + host ? "host" : "agent", + pci_arb ? "arbiter" : "external-arbiter"); + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + + /* outbound memory */ + pci_set_region(r++, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno = hose->last_busno+1; + printf(" PCI1 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + } else { + printf(" PCI1: disabled\n"); + } +#elif defined CONFIG_MPC8548 + /* PCI1 not present on MPC8572 */ + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ +#endif #ifdef CONFIG_PCIE1 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; hose = &pcie1_hose; @@ -143,7 +235,7 @@ void pci_init_board(void) if (!host) fsl_pci_config_unlock(hose); - first_free_busno = hose->last_busno+1; + first_free_busno = hose->last_busno + 1; printf(" PCIE1 on bus %02x - %02x\n", hose->first_busno, hose->last_busno); } @@ -200,7 +292,6 @@ void pci_init_board(void) first_free_busno = hose->last_busno+1; printf(" PCIE2 on bus %02x - %02x\n", hose->first_busno, hose->last_busno); - } #else gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ @@ -267,6 +358,10 @@ extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, void ft_board_pci_setup(void *blob, bd_t *bd) { + /* TODO - make node name (eg pci0) dynamic */ +#ifdef CONFIG_PCI1 + ft_fsl_pci_setup(blob, "pci0", &pci1_hose); +#endif #ifdef CONFIG_PCIE1 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); #endif -- cgit v1.3.1 From e12d9a8fb48d24176efffccc072b445e60a3afe4 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 3 Jan 2009 17:22:24 +0100 Subject: at91: Fix Atmel's at91sam9 boards out of tree build introduced in commit 89a7a87f084c Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- Makefile | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Makefile') diff --git a/Makefile b/Makefile index c532e5b146d..0f8b520661e 100644 --- a/Makefile +++ b/Makefile @@ -2602,6 +2602,7 @@ at91sam9260ek_nandflash_config \ at91sam9260ek_dataflash_cs0_config \ at91sam9260ek_dataflash_cs1_config \ at91sam9260ek_config : unconfig + @mkdir -p $(obj)include @if [ "$(findstring _nandflash,$@)" ] ; then \ echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ $(XECHO) "... with environment variable in NAND FLASH" ; \ @@ -2618,6 +2619,7 @@ at91sam9261ek_nandflash_config \ at91sam9261ek_dataflash_cs0_config \ at91sam9261ek_dataflash_cs3_config \ at91sam9261ek_config : unconfig + @mkdir -p $(obj)include @if [ "$(findstring _nandflash,$@)" ] ; then \ echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ $(XECHO) "... with environment variable in NAND FLASH" ; \ @@ -2634,6 +2636,7 @@ at91sam9263ek_nandflash_config \ at91sam9263ek_dataflash_config \ at91sam9263ek_dataflash_cs0_config \ at91sam9263ek_config : unconfig + @mkdir -p $(obj)include @if [ "$(findstring _nandflash,$@)" ] ; then \ echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ $(XECHO) "... with environment variable in NAND FLASH" ; \ @@ -2647,6 +2650,7 @@ at91sam9rlek_nandflash_config \ at91sam9rlek_dataflash_config \ at91sam9rlek_dataflash_cs0_config \ at91sam9rlek_config : unconfig + @mkdir -p $(obj)include @if [ "$(findstring _nandflash,$@)" ] ; then \ echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ $(XECHO) "... with environment variable in NAND FLASH" ; \ -- cgit v1.3.1 From 9ffd53db870a7da134f9a1ae76894a6b31237be5 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Tue, 6 Jan 2009 21:15:57 +0100 Subject: fix bmp_logo.h make dependencies to allow parallel build Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Makefile') diff --git a/Makefile b/Makefile index 0f8b520661e..74b185461bc 100644 --- a/Makefile +++ b/Makefile @@ -348,7 +348,7 @@ $(obj)u-boot: depend $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(OBJS): depend $(obj)include/autoconf.mk $(MAKE) -C cpu/$(CPU) $(if $(REMOTE_BUILD),$@,$(notdir $@)) -$(LIBS): depend $(obj)include/autoconf.mk +$(LIBS): depend $(obj)include/autoconf.mk $(SUBDIRS) $(MAKE) -C $(dir $(subst $(obj),,$@)) $(LIBBOARD): depend $(LIBS) $(obj)include/autoconf.mk -- cgit v1.3.1 From 4e170b16625291aa10d0d9abc3f34e8a5945d157 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Tue, 6 Jan 2009 21:13:14 +0100 Subject: at91: add at91sam9xeek board support At91sam9xe is basically an at91sam9260 with embedded flash. We can manage it as another entry for at91sam9260 in the Makefile. Check documentation at : http://www.atmel.com/dyn/products/product_card.asp?part_id=4263 Signed-off-by: Nicolas Ferre Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- Makefile | 17 +++++++++++++++++ doc/README.at91 | 2 +- 2 files changed, 18 insertions(+), 1 deletion(-) (limited to 'Makefile') diff --git a/Makefile b/Makefile index 74b185461bc..ecde92b4c19 100644 --- a/Makefile +++ b/Makefile @@ -2615,6 +2615,23 @@ at91sam9260ek_config : unconfig fi; @$(MKCONFIG) -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91 +at91sam9xeek_nandflash_config \ +at91sam9xeek_dataflash_cs0_config \ +at91sam9xeek_dataflash_cs1_config \ +at91sam9xeek_config : unconfig + @mkdir -p $(obj)include + @if [ "$(findstring _nandflash,$@)" ] ; then \ + echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ + $(XECHO) "... with environment variable in NAND FLASH" ; \ + elif [ "$(findstring dataflash_cs0,$@)" ] ; then \ + echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1" >>$(obj)include/config.h ; \ + $(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \ + else \ + echo "#define CONFIG_SYS_USE_DATAFLASH_CS1 1" >>$(obj)include/config.h ; \ + $(XECHO) "... with environment variable in SPI DATAFLASH CS1" ; \ + fi; + @$(MKCONFIG) -n at91sam9xeek -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91sam9 + at91sam9261ek_nandflash_config \ at91sam9261ek_dataflash_cs0_config \ at91sam9261ek_dataflash_cs3_config \ diff --git a/doc/README.at91 b/doc/README.at91 index 838769a9084..4e3928a475f 100644 --- a/doc/README.at91 +++ b/doc/README.at91 @@ -3,7 +3,7 @@ Atmel AT91 Evaluation kits http://atmel.com/dyn/products/tools.asp?family_id=605#1443 ------------------------------------------------------------------------------ -AT91SAM9260EK +AT91SAM9260EK & AT91SAM9XEEK ------------------------------------------------------------------------------ Memory map -- cgit v1.3.1 From a5b04d00bfeb940c62232972ce644d50b45797f9 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Tue, 30 Dec 2008 01:16:03 +0000 Subject: sh: Fix up rsk7203 target for out of tree build Fix up rsk7203 target to build successfully using out-of-tree build. Signed-off-by: Kieran Bingham Signed-off-by: Nobuhiro Iwamatsu --- Makefile | 4 ++-- board/renesas/rsk7203/Makefile | 4 ++++ cpu/sh2/Makefile | 21 +++++++++++++-------- 3 files changed, 19 insertions(+), 10 deletions(-) (limited to 'Makefile') diff --git a/Makefile b/Makefile index ecde92b4c19..8fb1e2ae2ff 100644 --- a/Makefile +++ b/Makefile @@ -3230,8 +3230,8 @@ mimc200_config : unconfig ## sh2 (Renesas SuperH) ######################################################################### rsk7203_config: unconfig - @ >include/config.h - @echo "#define CONFIG_RSK7203 1" >> include/config.h + @mkdir -p $(obj)include + @echo "#define CONFIG_RSK7203 1" > $(obj)/include/config.h @$(MKCONFIG) -a $(@:_config=) sh sh2 rsk7203 renesas ######################################################################### diff --git a/board/renesas/rsk7203/Makefile b/board/renesas/rsk7203/Makefile index 7365d193018..5412010ae6a 100644 --- a/board/renesas/rsk7203/Makefile +++ b/board/renesas/rsk7203/Makefile @@ -26,6 +26,10 @@ LIB = lib$(BOARD).a OBJS := rsk7203.o SOBJS := lowlevel_init.o +LIB := $(addprefix $(obj),$(LIB)) +OBJS := $(addprefix $(obj),$(OBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) diff --git a/cpu/sh2/Makefile b/cpu/sh2/Makefile index e33ba0f2a90..346d3285dbc 100644 --- a/cpu/sh2/Makefile +++ b/cpu/sh2/Makefile @@ -28,18 +28,23 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o -OBJS = cpu.o interrupts.o watchdog.o +SOBJS = start.o +COBJS = cpu.o interrupts.o watchdog.o -all: .depend $(START) $(LIB) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) -######################################################################### +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ +######################################################################### # defines $(obj).depend target include $(SRCTREE)/rules.mk -- cgit v1.3.1 From 635e5f8fc82365e6e9734b3132bc95135a6de679 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 18 Jan 2009 21:37:48 +0100 Subject: Prepare 2009.01-rc3 Update CHANGELOG Signed-off-by: Wolfgang Denk --- CHANGELOG | 176 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Makefile | 2 +- 2 files changed, 177 insertions(+), 1 deletion(-) (limited to 'Makefile') diff --git a/CHANGELOG b/CHANGELOG index 17c56916767..e582ced9369 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,128 @@ +commit 4cda437898f7873752f0201757cd33f12196ce87 +Author: Mike Frysinger +Date: Sat Jan 17 13:32:42 2009 -0500 + + build system: treat all Darwin's alike + + The x86 based version of Darwin behaves the same quirky way as the powerpc + Darwin, so only check HOSTOS when setting up Darwin workarounds. + + Signed-off-by: Mike Frysinger + +commit c088a108c75db565e07292fd668dfa5491e85bc2 +Author: Peter Korsgaard +Date: Wed Jan 14 13:52:24 2009 +0100 + + fdt_resize(): fix actualsize calculations with unaligned blobs + + The code in fdt_resize() to extend the fdt size to end on a page boundary + is wrong for fdt's not located at an address aligned on a page boundary. + What's even worse, the code would make actualsize shrink rather than grow + if (blob & 0xfff) was bigger than the amount of padding added by ALIGN(), + causing fdt_add_mem_rsv to fail. + + Fix it by aligning end address (blob + size) to a page boundary instead. + For aligned fdt's this is equivalent to what we had before. + + Signed-off-by: Peter Korsgaard + +commit fadad1573fb16c90025f08a2861d6047d093cba7 +Author: Mike Frysinger +Date: Fri Jan 9 04:38:17 2009 -0500 + + ncb: use socklen_t + + The recvfrom() function takes a socklen_t, not an int. + + Signed-off-by: Mike Frysinger + +commit fc83c9273cec6e6e542f4a0ea3b653b7d0513ffa +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sun Jan 11 16:35:16 2009 +0100 + + sh: serial: use readx/writex accessors + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Nobuhiro Iwamatsu + +commit 9e1fa628bdb64745811cdd26c4f953846c076180 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sun Jan 11 16:35:15 2009 +0100 + + sh: serial: coding style cleanup + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Nobuhiro Iwamatsu + +commit c9935c992575922b7ef13eec0656ed8665d324e3 +Author: Nobuhiro Iwamatsu +Date: Sun Jan 11 17:48:56 2009 +0900 + + sh: Fix compile error on lowlevel_init file + + lowlevel_init of SH was corrected to use the write/readXX macro. + However, there was a problem that was not able to be compiled partially. + This patch corrected this. + + Signed-off-by: Nobuhiro Iwamatsu + +commit a5b04d00bfeb940c62232972ce644d50b45797f9 +Author: Kieran Bingham +Date: Tue Dec 30 01:16:03 2008 +0000 + + sh: Fix up rsk7203 target for out of tree build + + Fix up rsk7203 target to build successfully using out-of-tree build. + + Signed-off-by: Kieran Bingham + Signed-off-by: Nobuhiro Iwamatsu + +commit f7e78f3b74aae9caca2997bad865a72338326c0a +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sat Dec 20 19:29:49 2008 +0100 + + sh: use write{8,16,32} in all lowlevel_init + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Nobuhiro Iwamatsu + +commit e4430779623af500de1cee7892c379f07ef59813 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sat Dec 20 19:29:48 2008 +0100 + + sh: lowlevel_init coding style cleanup + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Nobuhiro Iwamatsu + +commit 85cb052ee41675ca361e6a4c69455dc715c8f2d9 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sat Dec 20 15:27:45 2008 +0100 + + sh: update sh2/sh2a timer coding style + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Nobuhiro Iwamatsu + +commit 1e15ff999322e81af4c0c0c548908f38944ba39c +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sat Dec 20 15:25:22 2008 +0100 + + sh: update sh timer coding style + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Nobuhiro Iwamatsu + +commit 0e3ece33801e377be67ffa29f083421ad820f28b +Author: Wolfgang Denk +Date: Wed Jan 14 23:26:05 2009 +0100 + + Prepare 2009.01-rc2 + + Update CHANGELOG. + + Signed-off-by: Wolfgang Denk + commit e92c9a860e44c14513c8909ce4299e253a775eeb Author: Wolfgang Denk Date: Wed Jan 14 22:35:30 2009 +0100 @@ -12,6 +137,57 @@ Date: Wed Jan 14 22:35:30 2009 +0100 Signed-off-by: Wolfgang Denk +commit 3ba605d4beec649438539e7df97b5fedb26592fb +Author: Matthias Fuchs +Date: Fri Jan 2 12:18:49 2009 +0100 + + ppc4xx: Add loadpci command to esd's CPCI4052 and CPCI405AB boards + + This patch adds esd's loadpci BSP command to CPCI4052 and + CPCI405AB board. This requires CONFIG_CMD_BSP and CONFIG_PRAM. + + Signed-off-by: Matthias Fuchs + Signed-off-by: Stefan Roese + +commit 600fe46fb3dab7f07604f9009904f31584415114 +Author: Matthias Fuchs +Date: Fri Jan 2 12:18:12 2009 +0100 + + ppc4xx: Disable pci node in device tree on CPCI405 pci adapters + + Signed-off-by: Matthias Fuchs + Signed-off-by: Stefan Roese + +commit f6a1f490d224c600a09137e58d1026d150b8e679 +Author: Matthias Fuchs +Date: Fri Jan 2 12:17:36 2009 +0100 + + ppc4xx: Cleanup CPCI405 board code + + This patch cleans up CPCI405 board support: + - wrap long lines + - unification of spaces in function calls + - remove dead code + + Use correct io accessors on peripherals. + + Signed-off-by: Matthias Fuchs + Signed-off-by: Stefan Roese + +commit fceebb45a0b97e92f9889861f8c3b9cb885e706f +Author: Matthias Fuchs +Date: Fri Jan 2 12:16:35 2009 +0100 + + ppc4xx: Enable auto RS485 mode on PLU405 boards + + This patch turns on the auto RS485 mode in the 2nd external + uart on PLU405 boards. This is a special mode of the used + Exar XR16C2850 uart. Because these boards only have a 485 physical + layer connected it's a good idea to turn it on by default. + + Signed-off-by: Matthias Fuchs + Signed-off-by: Stefan Roese + commit b5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6 Author: Haiying Wang Date: Tue Jan 13 16:29:28 2009 -0500 diff --git a/Makefile b/Makefile index 8fb1e2ae2ff..9c63643e68e 100644 --- a/Makefile +++ b/Makefile @@ -24,7 +24,7 @@ VERSION = 2009 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc3 ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else -- cgit v1.3.1 From 72d15e705bc3983884105cb7755c7ba80e74a0a5 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 21 Jan 2009 23:08:12 +0100 Subject: Prepare v2009.01 Signed-off-by: Wolfgang Denk --- CHANGELOG | 10 ++++++++++ Makefile | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) (limited to 'Makefile') diff --git a/CHANGELOG b/CHANGELOG index e582ced9369..bd3a7b76d8a 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,13 @@ +commit 635e5f8fc82365e6e9734b3132bc95135a6de679 +Author: Wolfgang Denk +Date: Sun Jan 18 21:37:48 2009 +0100 + + Prepare 2009.01-rc3 + + Update CHANGELOG + + Signed-off-by: Wolfgang Denk + commit 4cda437898f7873752f0201757cd33f12196ce87 Author: Mike Frysinger Date: Sat Jan 17 13:32:42 2009 -0500 diff --git a/Makefile b/Makefile index 9c63643e68e..d533564d9af 100644 --- a/Makefile +++ b/Makefile @@ -24,7 +24,7 @@ VERSION = 2009 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc3 +EXTRAVERSION = ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else -- cgit v1.3.1 From 52a822ed9c37a2ea0ed112a26d8ff5a6cb1c6f10 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 19 Dec 2008 13:14:05 +0100 Subject: microblaze: Rename ml401 to microblaze-generic Signed-off-by: Michal Simek --- MAINTAINERS | 2 +- MAKEALL | 6 +- Makefile | 5 +- board/xilinx/microblaze-generic/Makefile | 50 ++++ board/xilinx/microblaze-generic/config.mk | 32 +++ .../xilinx/microblaze-generic/microblaze-generic.c | 69 +++++ board/xilinx/microblaze-generic/u-boot.lds | 68 +++++ board/xilinx/microblaze-generic/xparameters.h | 69 +++++ board/xilinx/ml401/Makefile | 50 ---- board/xilinx/ml401/config.mk | 32 --- board/xilinx/ml401/ml401.c | 69 ----- board/xilinx/ml401/u-boot.lds | 68 ----- board/xilinx/ml401/xparameters.h | 69 ----- include/configs/microblaze-generic.h | 280 ++++++++++++++++++++ include/configs/ml401.h | 281 --------------------- 15 files changed, 574 insertions(+), 576 deletions(-) create mode 100644 board/xilinx/microblaze-generic/Makefile create mode 100644 board/xilinx/microblaze-generic/config.mk create mode 100644 board/xilinx/microblaze-generic/microblaze-generic.c create mode 100644 board/xilinx/microblaze-generic/u-boot.lds create mode 100644 board/xilinx/microblaze-generic/xparameters.h delete mode 100644 board/xilinx/ml401/Makefile delete mode 100644 board/xilinx/ml401/config.mk delete mode 100644 board/xilinx/ml401/ml401.c delete mode 100644 board/xilinx/ml401/u-boot.lds delete mode 100644 board/xilinx/ml401/xparameters.h create mode 100644 include/configs/microblaze-generic.h delete mode 100644 include/configs/ml401.h (limited to 'Makefile') diff --git a/MAINTAINERS b/MAINTAINERS index 60def0c34d7..dfe54a7cb72 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -707,7 +707,7 @@ Yasushi Shoji Michal Simek - ML401 MicroBlaze + microblaze-generic MicroBlaze ######################################################################### # Coldfire Systems: # diff --git a/MAKEALL b/MAKEALL index 5ce3f3112c9..f6271a29f1f 100755 --- a/MAKEALL +++ b/MAKEALL @@ -697,9 +697,9 @@ LIST_nios2=" \ ## MicroBlaze Systems ######################################################################### -LIST_microblaze=" \ - ml401 \ - suzaku \ +LIST_microblaze=" \ + microblaze-generic \ + suzaku \ " ######################################################################### diff --git a/Makefile b/Makefile index d533564d9af..5cc950dea5f 100644 --- a/Makefile +++ b/Makefile @@ -3170,10 +3170,9 @@ PCI5441_config : unconfig ## Microblaze #======================================================================== -ml401_config: unconfig +microblaze-generic_config: unconfig @mkdir -p $(obj)include - @echo "#define CONFIG_ML401 1" > $(obj)include/config.h - @$(MKCONFIG) -a $(@:_config=) microblaze microblaze ml401 xilinx + @$(MKCONFIG) -a $(@:_config=) microblaze microblaze microblaze-generic xilinx suzaku_config: unconfig @mkdir -p $(obj)include diff --git a/board/xilinx/microblaze-generic/Makefile b/board/xilinx/microblaze-generic/Makefile new file mode 100644 index 00000000000..10b47b2ae54 --- /dev/null +++ b/board/xilinx/microblaze-generic/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk new file mode 100644 index 00000000000..c75daaf0b54 --- /dev/null +++ b/board/xilinx/microblaze-generic/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2007 Michal Simek +# +# Michal SIMEK +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# CAUTION: This file is automatically generated by libgen. +# Version: Xilinx EDK 6.3 EDK_Gmm.12.3 +# + +TEXT_BASE = 0x29000000 + +PLATFORM_CPPFLAGS += -mno-xl-soft-mul +PLATFORM_CPPFLAGS += -mno-xl-soft-div +PLATFORM_CPPFLAGS += -mxl-barrel-shift diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c new file mode 100644 index 00000000000..f388b775c2e --- /dev/null +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This is a board specific file. It's OK to include board specific + * header files */ + +#include +#include +#include +#include + +void do_reset (void) +{ +#ifdef CONFIG_SYS_GPIO_0 + *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = + ++(*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR))); +#endif +#ifdef CONFIG_SYS_RESET_ADDRESS + puts ("Reseting board\n"); + asm ("bra r0"); +#endif +} + +int gpio_init (void) +{ +#ifdef CONFIG_SYS_GPIO_0 + *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = 0xFFFFFFFF; +#endif + return 0; +} + +#ifdef CONFIG_SYS_FSL_2 +void fsl_isr2 (void *arg) { + volatile int num; + *((unsigned int *)(CONFIG_SYS_GPIO_0_ADDR + 0x4)) = + ++(*((unsigned int *)(CONFIG_SYS_GPIO_0_ADDR + 0x4))); + GET (num, 2); + NGET (num, 2); + puts("*"); +} + +void fsl_init2 (void) { + puts("fsl_init2\n"); + install_interrupt_handler (FSL_INTR_2,\ + fsl_isr2,\ + NULL); +} +#endif diff --git a/board/xilinx/microblaze-generic/u-boot.lds b/board/xilinx/microblaze-generic/u-boot.lds new file mode 100644 index 00000000000..b38f6487725 --- /dev/null +++ b/board/xilinx/microblaze-generic/u-boot.lds @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(microblaze) +ENTRY(_start) + +SECTIONS +{ + .text ALIGN(0x4): + { + __text_start = .; + cpu/microblaze/start.o (.text) + *(.text) + __text_end = .; + } + + .rodata ALIGN(0x4): + { + __rodata_start = .; + *(.rodata) + __rodata_end = .; + } + + .data ALIGN(0x4): + { + __data_start = .; + *(.data) + __data_end = .; + } + + .u_boot_cmd ALIGN(0x4): + { + . = .; + __u_boot_cmd_start = .; + *(.u_boot_cmd) + __u_boot_cmd_end = .; + } + + .bss ALIGN(0x4): + { + __bss_start = .; + *(.bss) + . = ALIGN(4); + __bss_end = .; + } + __end = . ; +} diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h new file mode 100644 index 00000000000..d805061c0d0 --- /dev/null +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * CAUTION: This file is automatically generated by libgen. + * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4 + */ + +/* System Clock Frequency */ +#define XILINX_CLOCK_FREQ 100000000 + +/* Microblaze is microblaze_0 */ +#define XILINX_USE_MSR_INSTR 1 +#define XILINX_FSL_NUMBER 3 + +/* Interrupt controller is opb_intc_0 */ +#define XILINX_INTC_BASEADDR 0x41200000 +#define XILINX_INTC_NUM_INTR_INPUTS 6 + +/* Timer pheriphery is opb_timer_1 */ +#define XILINX_TIMER_BASEADDR 0x41c00000 +#define XILINX_TIMER_IRQ 0 + +/* Uart pheriphery is RS232_Uart */ +#define XILINX_UARTLITE_BASEADDR 0x40600000 +#define XILINX_UARTLITE_BAUDRATE 115200 + +/* IIC pheriphery is IIC_EEPROM */ +#define XILINX_IIC_0_BASEADDR 0x40800000 +#define XILINX_IIC_0_FREQ 100000 +#define XILINX_IIC_0_BIT 0 + +/* GPIO is LEDs_4Bit*/ +#define XILINX_GPIO_BASEADDR 0x40000000 + +/* Flash Memory is FLASH_2Mx32 */ +#define XILINX_FLASH_START 0x2c000000 +#define XILINX_FLASH_SIZE 0x00800000 + +/* Main Memory is DDR_SDRAM_64Mx32 */ +#define XILINX_RAM_START 0x28000000 +#define XILINX_RAM_SIZE 0x04000000 + +/* Sysace Controller is SysACE_CompactFlash */ +#define XILINX_SYSACE_BASEADDR 0x41800000 +#define XILINX_SYSACE_HIGHADDR 0x4180ffff +#define XILINX_SYSACE_MEM_WIDTH 16 + +/* Ethernet controller is Ethernet_MAC */ +#define XILINX_EMACLITE_BASEADDR 0x40C00000 diff --git a/board/xilinx/ml401/Makefile b/board/xilinx/ml401/Makefile deleted file mode 100644 index 10b47b2ae54..00000000000 --- a/board/xilinx/ml401/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/xilinx/ml401/config.mk b/board/xilinx/ml401/config.mk deleted file mode 100644 index c75daaf0b54..00000000000 --- a/board/xilinx/ml401/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2007 Michal Simek -# -# Michal SIMEK -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# CAUTION: This file is automatically generated by libgen. -# Version: Xilinx EDK 6.3 EDK_Gmm.12.3 -# - -TEXT_BASE = 0x29000000 - -PLATFORM_CPPFLAGS += -mno-xl-soft-mul -PLATFORM_CPPFLAGS += -mno-xl-soft-div -PLATFORM_CPPFLAGS += -mxl-barrel-shift diff --git a/board/xilinx/ml401/ml401.c b/board/xilinx/ml401/ml401.c deleted file mode 100644 index f388b775c2e..00000000000 --- a/board/xilinx/ml401/ml401.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* This is a board specific file. It's OK to include board specific - * header files */ - -#include -#include -#include -#include - -void do_reset (void) -{ -#ifdef CONFIG_SYS_GPIO_0 - *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = - ++(*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR))); -#endif -#ifdef CONFIG_SYS_RESET_ADDRESS - puts ("Reseting board\n"); - asm ("bra r0"); -#endif -} - -int gpio_init (void) -{ -#ifdef CONFIG_SYS_GPIO_0 - *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = 0xFFFFFFFF; -#endif - return 0; -} - -#ifdef CONFIG_SYS_FSL_2 -void fsl_isr2 (void *arg) { - volatile int num; - *((unsigned int *)(CONFIG_SYS_GPIO_0_ADDR + 0x4)) = - ++(*((unsigned int *)(CONFIG_SYS_GPIO_0_ADDR + 0x4))); - GET (num, 2); - NGET (num, 2); - puts("*"); -} - -void fsl_init2 (void) { - puts("fsl_init2\n"); - install_interrupt_handler (FSL_INTR_2,\ - fsl_isr2,\ - NULL); -} -#endif diff --git a/board/xilinx/ml401/u-boot.lds b/board/xilinx/ml401/u-boot.lds deleted file mode 100644 index b38f6487725..00000000000 --- a/board/xilinx/ml401/u-boot.lds +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(microblaze) -ENTRY(_start) - -SECTIONS -{ - .text ALIGN(0x4): - { - __text_start = .; - cpu/microblaze/start.o (.text) - *(.text) - __text_end = .; - } - - .rodata ALIGN(0x4): - { - __rodata_start = .; - *(.rodata) - __rodata_end = .; - } - - .data ALIGN(0x4): - { - __data_start = .; - *(.data) - __data_end = .; - } - - .u_boot_cmd ALIGN(0x4): - { - . = .; - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } - - .bss ALIGN(0x4): - { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end = .; - } - __end = . ; -} diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h deleted file mode 100644 index d805061c0d0..00000000000 --- a/board/xilinx/ml401/xparameters.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * CAUTION: This file is automatically generated by libgen. - * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4 - */ - -/* System Clock Frequency */ -#define XILINX_CLOCK_FREQ 100000000 - -/* Microblaze is microblaze_0 */ -#define XILINX_USE_MSR_INSTR 1 -#define XILINX_FSL_NUMBER 3 - -/* Interrupt controller is opb_intc_0 */ -#define XILINX_INTC_BASEADDR 0x41200000 -#define XILINX_INTC_NUM_INTR_INPUTS 6 - -/* Timer pheriphery is opb_timer_1 */ -#define XILINX_TIMER_BASEADDR 0x41c00000 -#define XILINX_TIMER_IRQ 0 - -/* Uart pheriphery is RS232_Uart */ -#define XILINX_UARTLITE_BASEADDR 0x40600000 -#define XILINX_UARTLITE_BAUDRATE 115200 - -/* IIC pheriphery is IIC_EEPROM */ -#define XILINX_IIC_0_BASEADDR 0x40800000 -#define XILINX_IIC_0_FREQ 100000 -#define XILINX_IIC_0_BIT 0 - -/* GPIO is LEDs_4Bit*/ -#define XILINX_GPIO_BASEADDR 0x40000000 - -/* Flash Memory is FLASH_2Mx32 */ -#define XILINX_FLASH_START 0x2c000000 -#define XILINX_FLASH_SIZE 0x00800000 - -/* Main Memory is DDR_SDRAM_64Mx32 */ -#define XILINX_RAM_START 0x28000000 -#define XILINX_RAM_SIZE 0x04000000 - -/* Sysace Controller is SysACE_CompactFlash */ -#define XILINX_SYSACE_BASEADDR 0x41800000 -#define XILINX_SYSACE_HIGHADDR 0x4180ffff -#define XILINX_SYSACE_MEM_WIDTH 16 - -/* Ethernet controller is Ethernet_MAC */ -#define XILINX_EMACLITE_BASEADDR 0x40C00000 diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h new file mode 100644 index 00000000000..ed4bf6d3596 --- /dev/null +++ b/include/configs/microblaze-generic.h @@ -0,0 +1,280 @@ +/* + * (C) Copyright 2007-2008 Michal Simek + * + * Michal SIMEK + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "../board/xilinx/microblaze-generic/xparameters.h" + +#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */ +#define MICROBLAZE_V5 1 + +/* uart */ +#ifdef XILINX_UARTLITE_BASEADDR +#define CONFIG_XILINX_UARTLITE +#define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR +#define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE +#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } +#elif XILINX_UART16550_BASEADDR +#define CONFIG_SYS_NS16550 1 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 (XILINX_UART16550_BASEADDR + 0x1000 + 0x3) +#define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ +#define CONFIG_BAUDRATE 115200 + +/* The following table includes the supported baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} +#else +#error Undefined uart +#endif + +/* setting reset address */ +/*#define CONFIG_SYS_RESET_ADDRESS TEXT_BASE*/ + +/* ethernet */ +#ifdef XILINX_EMAC_BASEADDR +#define CONFIG_XILINX_EMAC 1 +#define CONFIG_SYS_ENET +#else +#ifdef XILINX_EMACLITE_BASEADDR +#define CONFIG_XILINX_EMACLITE 1 +#define CONFIG_SYS_ENET +#endif +#endif +#undef ET_DEBUG + +/* gpio */ +#ifdef XILINX_GPIO_BASEADDR +#define CONFIG_SYS_GPIO_0 1 +#define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR +#endif + +/* interrupt controller */ +#ifdef XILINX_INTC_BASEADDR +#define CONFIG_SYS_INTC_0 1 +#define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR +#define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS +#endif + +/* timer */ +#ifdef XILINX_TIMER_BASEADDR +#if (XILINX_TIMER_IRQ != -1) +#define CONFIG_SYS_TIMER_0 1 +#define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR +#define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ +#define FREQUENCE XILINX_CLOCK_FREQ +#define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) +#endif +#else +#ifdef XILINX_CLOCK_FREQ +#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ +#else +#error BAD CLOCK FREQ +#endif +#endif +/* FSL */ +/* #define CONFIG_SYS_FSL_2 */ +/* #define FSL_INTR_2 1 */ + +/* + * memory layout - Example + * TEXT_BASE = 0x1200_0000; + * CONFIG_SYS_SRAM_BASE = 0x1000_0000; + * CONFIG_SYS_SRAM_SIZE = 0x0400_0000; + * + * CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000 + * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000 + * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000 + * + * 0x1000_0000 CONFIG_SYS_SDRAM_BASE + * FREE + * 0x1200_0000 TEXT_BASE + * U-BOOT code + * 0x1202_0000 + * FREE + * + * STACK + * 0x13F7_F000 CONFIG_SYS_MALLOC_BASE + * MALLOC_AREA 256kB Alloc + * 0x11FB_F000 CONFIG_SYS_MONITOR_BASE + * MONITOR_CODE 256kB Env + * 0x13FF_F000 CONFIG_SYS_GBL_DATA_OFFSET + * GLOBAL_DATA 4kB bd, gd + * 0x1400_0000 CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE + */ + +/* ddr sdram - main memory */ +#define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START +#define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) + +/* global pointer */ +#define CONFIG_SYS_GBL_DATA_SIZE 0x1000 /* size of global data */ +/* start of global data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) + +/* monitor code */ +#define SIZE 0x40000 +#define CONFIG_SYS_MONITOR_LEN SIZE +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_MONITOR_END (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_MALLOC_LEN SIZE +#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) + +/* stack */ +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MONITOR_BASE + +/*#define RAMENV */ +#define FLASH + +#ifdef FLASH + #define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START + #define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE + #define CONFIG_SYS_FLASH_CFI 1 + #define CONFIG_FLASH_CFI_DRIVER 1 + #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* ?empty sector */ + #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ + #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + #define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */ + + #ifdef RAMENV + #define CONFIG_ENV_IS_NOWHERE 1 + #define CONFIG_ENV_SIZE 0x1000 + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) + + #else /* !RAMENV */ + #define CONFIG_ENV_IS_IN_FLASH 1 + #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) + #define CONFIG_ENV_SIZE 0x40000 + #endif /* !RAMBOOT */ +#else /* !FLASH */ + /* ENV in RAM */ + #define CONFIG_SYS_NO_FLASH 1 + #define CONFIG_ENV_IS_NOWHERE 1 + #define CONFIG_ENV_SIZE 0x1000 + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) + #define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */ +#endif /* !FLASH */ + +/* system ace */ +#ifdef XILINX_SYSACE_BASEADDR + #define CONFIG_SYSTEMACE + /* #define DEBUG_SYSTEMACE */ + #define SYSTEMACE_CONFIG_FPGA + #define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR + #define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH + #define CONFIG_DOS_PARTITION +#endif + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MFSL + +#ifndef CONFIG_SYS_ENET + #undef CONFIG_CMD_NET +#else + #define CONFIG_CMD_PING +#endif + +#if defined(CONFIG_SYSTEMACE) + #define CONFIG_CMD_EXT2 + #define CONFIG_CMD_FAT +#endif + +#if defined(FLASH) + #define CONFIG_CMD_ECHO + #define CONFIG_CMD_FLASH + #define CONFIG_CMD_IMLS + #define CONFIG_CMD_JFFS2 + + #if !defined(RAMENV) + #define CONFIG_CMD_ENV + #define CONFIG_CMD_SAVES + #endif +#else + #undef CONFIG_CMD_FLASH +#endif + +#if defined(CONFIG_CMD_JFFS2) +/* JFFS2 partitions */ +#define CONFIG_JFFS2_CMDLINE /* mtdparts command line support */ +#define MTDIDS_DEFAULT "nor0=ml401-0" + +/* default mtd partition table */ +#define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\ + "256k(env),3m(kernel),1m(romfs),"\ + "1m(cramfs),-(jffs2)" +#endif + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_PROMPT "U-Boot-mONStR> " +#define CONFIG_SYS_CBSIZE 512 /* size of console buffer */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ +#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_LOAD_ADDR 0x12000000 /* default load address */ + +#define CONFIG_BOOTDELAY 30 +#define CONFIG_BOOTARGS "root=romfs" +#define CONFIG_HOSTNAME "ml401" +#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" +#define CONFIG_IPADDR 192.168.0.3 +#define CONFIG_SERVERIP 192.168.0.5 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD + +/* architecture dependent code */ +#define CONFIG_SYS_USR_EXCEP /* user exception */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo" + +#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\ + "nor0=ml401-0\0"\ + "mtdparts=mtdparts=ml401-0:"\ + "256k(u-boot),256k(env),3m(kernel),"\ + "1m(romfs),1m(cramfs),-(jffs2)\0" + +#define CONFIG_CMDLINE_EDITING + +#endif /* __CONFIG_H */ diff --git a/include/configs/ml401.h b/include/configs/ml401.h deleted file mode 100644 index c802dcb6a2a..00000000000 --- a/include/configs/ml401.h +++ /dev/null @@ -1,281 +0,0 @@ -/* - * (C) Copyright 2007-2008 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "../board/xilinx/ml401/xparameters.h" - -#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */ -#define MICROBLAZE_V5 1 -#define CONFIG_ML401 1 /* ML401 Board */ - -/* uart */ -#ifdef XILINX_UARTLITE_BASEADDR -#define CONFIG_XILINX_UARTLITE -#define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR -#define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE -#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } -#elif XILINX_UART16550_BASEADDR -#define CONFIG_SYS_NS16550 1 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 (XILINX_UART16550_BASEADDR + 0x1000 + 0x3) -#define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ -#define CONFIG_BAUDRATE 115200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} -#else -#error Undefined uart -#endif - -/* setting reset address */ -/*#define CONFIG_SYS_RESET_ADDRESS TEXT_BASE*/ - -/* ethernet */ -#ifdef XILINX_EMAC_BASEADDR -#define CONFIG_XILINX_EMAC 1 -#define CONFIG_SYS_ENET -#else -#ifdef XILINX_EMACLITE_BASEADDR -#define CONFIG_XILINX_EMACLITE 1 -#define CONFIG_SYS_ENET -#endif -#endif -#undef ET_DEBUG - -/* gpio */ -#ifdef XILINX_GPIO_BASEADDR -#define CONFIG_SYS_GPIO_0 1 -#define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR -#endif - -/* interrupt controller */ -#ifdef XILINX_INTC_BASEADDR -#define CONFIG_SYS_INTC_0 1 -#define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR -#define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS -#endif - -/* timer */ -#ifdef XILINX_TIMER_BASEADDR -#if (XILINX_TIMER_IRQ != -1) -#define CONFIG_SYS_TIMER_0 1 -#define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR -#define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ -#define FREQUENCE XILINX_CLOCK_FREQ -#define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) -#endif -#else -#ifdef XILINX_CLOCK_FREQ -#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ -#else -#error BAD CLOCK FREQ -#endif -#endif -/* FSL */ -/* #define CONFIG_SYS_FSL_2 */ -/* #define FSL_INTR_2 1 */ - -/* - * memory layout - Example - * TEXT_BASE = 0x1200_0000; - * CONFIG_SYS_SRAM_BASE = 0x1000_0000; - * CONFIG_SYS_SRAM_SIZE = 0x0400_0000; - * - * CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000 - * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000 - * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000 - * - * 0x1000_0000 CONFIG_SYS_SDRAM_BASE - * FREE - * 0x1200_0000 TEXT_BASE - * U-BOOT code - * 0x1202_0000 - * FREE - * - * STACK - * 0x13F7_F000 CONFIG_SYS_MALLOC_BASE - * MALLOC_AREA 256kB Alloc - * 0x11FB_F000 CONFIG_SYS_MONITOR_BASE - * MONITOR_CODE 256kB Env - * 0x13FF_F000 CONFIG_SYS_GBL_DATA_OFFSET - * GLOBAL_DATA 4kB bd, gd - * 0x1400_0000 CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - */ - -/* ddr sdram - main memory */ -#define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START -#define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) - -/* global pointer */ -#define CONFIG_SYS_GBL_DATA_SIZE 0x1000 /* size of global data */ -/* start of global data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) - -/* monitor code */ -#define SIZE 0x40000 -#define CONFIG_SYS_MONITOR_LEN SIZE -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_MONITOR_END (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_MALLOC_LEN SIZE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) - -/* stack */ -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MONITOR_BASE - -/*#define RAMENV */ -#define FLASH - -#ifdef FLASH - #define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START - #define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE - #define CONFIG_SYS_FLASH_CFI 1 - #define CONFIG_FLASH_CFI_DRIVER 1 - #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* ?empty sector */ - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ - #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - #define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */ - - #ifdef RAMENV - #define CONFIG_ENV_IS_NOWHERE 1 - #define CONFIG_ENV_SIZE 0x1000 - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) - - #else /* !RAMENV */ - #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) - #define CONFIG_ENV_SIZE 0x40000 - #endif /* !RAMBOOT */ -#else /* !FLASH */ - /* ENV in RAM */ - #define CONFIG_SYS_NO_FLASH 1 - #define CONFIG_ENV_IS_NOWHERE 1 - #define CONFIG_ENV_SIZE 0x1000 - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) - #define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */ -#endif /* !FLASH */ - -/* system ace */ -#ifdef XILINX_SYSACE_BASEADDR - #define CONFIG_SYSTEMACE - /* #define DEBUG_SYSTEMACE */ - #define SYSTEMACE_CONFIG_FPGA - #define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR - #define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH - #define CONFIG_DOS_PARTITION -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MFSL - -#ifndef CONFIG_SYS_ENET - #undef CONFIG_CMD_NET -#else - #define CONFIG_CMD_PING -#endif - -#if defined(CONFIG_SYSTEMACE) - #define CONFIG_CMD_EXT2 - #define CONFIG_CMD_FAT -#endif - -#if defined(FLASH) - #define CONFIG_CMD_ECHO - #define CONFIG_CMD_FLASH - #define CONFIG_CMD_IMLS - #define CONFIG_CMD_JFFS2 - - #if !defined(RAMENV) - #define CONFIG_CMD_ENV - #define CONFIG_CMD_SAVES - #endif -#else - #undef CONFIG_CMD_FLASH -#endif - -#if defined(CONFIG_CMD_JFFS2) -/* JFFS2 partitions */ -#define CONFIG_JFFS2_CMDLINE /* mtdparts command line support */ -#define MTDIDS_DEFAULT "nor0=ml401-0" - -/* default mtd partition table */ -#define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\ - "256k(env),3m(kernel),1m(romfs),"\ - "1m(cramfs),-(jffs2)" -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_PROMPT "U-Boot-mONStR> " -#define CONFIG_SYS_CBSIZE 512 /* size of console buffer */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ -#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_LOAD_ADDR 0x12000000 /* default load address */ - -#define CONFIG_BOOTDELAY 30 -#define CONFIG_BOOTARGS "root=romfs" -#define CONFIG_HOSTNAME "ml401" -#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" -#define CONFIG_IPADDR 192.168.0.3 -#define CONFIG_SERVERIP 192.168.0.5 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_ETHADDR 00:E0:0C:00:00:FD - -/* architecture dependent code */ -#define CONFIG_SYS_USR_EXCEP /* user exception */ -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo" - -#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\ - "nor0=ml401-0\0"\ - "mtdparts=mtdparts=ml401-0:"\ - "256k(u-boot),256k(env),3m(kernel),"\ - "1m(romfs),1m(cramfs),-(jffs2)\0" - -#define CONFIG_CMDLINE_EDITING - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 5bb907a4925397789c90d074f4f7e92ce6b39402 Mon Sep 17 00:00:00 2001 From: Ron Madrid Date: Thu, 22 Jan 2009 15:05:24 -0800 Subject: mpc83xx: New board support for SIMPC8313 This patch will create a new board, SIMPC8313, from Sheldon Instruments. This board boots from NAND devices and is configureable for either large or small page devices. The board supports non-soldered DDR2, one ethernet port, a Marvell 88E1118 PHY, and PCI host support. The board also has a FPGA connected to the eLBC providing glue logic to a TMS320C67xx DSP. Signed-off-by: Ron Madrid Signed-off-by: Kim Phillips --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 15 + board/sheldon/simpc8313/Makefile | 50 +++ board/sheldon/simpc8313/config.mk | 13 + board/sheldon/simpc8313/sdram.c | 193 ++++++++++ board/sheldon/simpc8313/simpc8313.c | 134 +++++++ doc/README.simpc8313 | 80 ++++ include/configs/SIMPC8313.h | 544 ++++++++++++++++++++++++++++ nand_spl/board/sheldon/simpc8313/Makefile | 100 +++++ nand_spl/board/sheldon/simpc8313/u-boot.lds | 52 +++ 11 files changed, 1186 insertions(+) create mode 100644 board/sheldon/simpc8313/Makefile create mode 100644 board/sheldon/simpc8313/config.mk create mode 100644 board/sheldon/simpc8313/sdram.c create mode 100644 board/sheldon/simpc8313/simpc8313.c create mode 100644 doc/README.simpc8313 create mode 100644 include/configs/SIMPC8313.h create mode 100644 nand_spl/board/sheldon/simpc8313/Makefile create mode 100644 nand_spl/board/sheldon/simpc8313/u-boot.lds (limited to 'Makefile') diff --git a/MAINTAINERS b/MAINTAINERS index d07fe86129f..b774938dca3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -263,6 +263,10 @@ Jon Loeliger MPC8641HPCN MPC8641D +Ron Madrid + + SIMPC8313 MPC8313 + Dan Malek stxgp3 MPC85xx diff --git a/MAKEALL b/MAKEALL index 3e8c56b4fd0..1ca5e58ded0 100755 --- a/MAKEALL +++ b/MAKEALL @@ -353,6 +353,7 @@ LIST_83xx=" \ MPC837XERDB \ MVBLM7 \ sbc8349 \ + SIMPC8313_LP \ TQM834x \ " diff --git a/Makefile b/Makefile index 294efef943f..9f692781560 100644 --- a/Makefile +++ b/Makefile @@ -2328,6 +2328,21 @@ MVBLM7_config: unconfig sbc8349_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349 +SIMPC8313_LP_config \ +SIMPC8313_SP_config: unconfig + @mkdir -p $(obj)include + @mkdir -p $(obj)board/sheldon/simpc8313 + @if [ "$(findstring _LP_,$@)" ] ; then \ + $(XECHO) -n "...Large Page NAND..." ; \ + echo "#define CONFIG_NAND_LP" >> $(obj)include/config.h ; \ + fi ; \ + if [ "$(findstring _SP_,$@)" ] ; then \ + $(XECHO) -n "...Small Page NAND..." ; \ + echo "#define CONFIG_NAND_SP" >> $(obj)include/config.h ; \ + fi ; + @$(MKCONFIG) -a SIMPC8313 ppc mpc83xx simpc8313 sheldon + @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk + TQM834x_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc diff --git a/board/sheldon/simpc8313/Makefile b/board/sheldon/simpc8313/Makefile new file mode 100644 index 00000000000..7c34c5e1641 --- /dev/null +++ b/board/sheldon/simpc8313/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o sdram.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/sheldon/simpc8313/config.mk b/board/sheldon/simpc8313/config.mk new file mode 100644 index 00000000000..ce1c0d8d938 --- /dev/null +++ b/board/sheldon/simpc8313/config.mk @@ -0,0 +1,13 @@ +ifndef NAND_SPL +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp +endif + +ifndef TEXT_BASE +TEXT_BASE = 0x00100000 +endif + +ifdef CONFIG_NAND_LP +PAD_TO = 0xFFF20000 +else +PAD_TO = 0xFFF04000 +endif diff --git a/board/sheldon/simpc8313/sdram.c b/board/sheldon/simpc8313/sdram.c new file mode 100644 index 00000000000..ebb70a2327b --- /dev/null +++ b/board/sheldon/simpc8313/sdram.c @@ -0,0 +1,193 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 + * Copyright (C) Sheldon Instruments, Inc. 2008 + * + * Author: Ron Madrid + * + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static long fixed_sdram(void); + +#if defined(CONFIG_NAND_SPL) +void si_wait_i2c(void) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + + while (!(__raw_readb(&im->i2c[0].sr) & 0x02)) + ; + + __raw_writeb(0x00, &im->i2c[0].sr); + + sync(); + + return; +} + +void si_read_i2c(u32 lbyte, int count, u8 *buffer) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 i; + u8 chip = 0x50 << 1; /* boot sequencer I2C */ + u32 ubyte = (lbyte & 0xff00) >> 8; + + lbyte &= 0xff; + + /* + * Set up controller + */ + __raw_writeb(0x3f, &im->i2c[0].fdr); + __raw_writeb(0x00, &im->i2c[0].adr); + __raw_writeb(0x00, &im->i2c[0].sr); + __raw_writeb(0x00, &im->i2c[0].dr); + + while (__raw_readb(&im->i2c[0].sr) & 0x20) + ; + + /* + * Writing address to device + */ + __raw_writeb(0xb0, &im->i2c[0].cr); + sync(); + __raw_writeb(chip, &im->i2c[0].dr); + si_wait_i2c(); + + __raw_writeb(0xb0, &im->i2c[0].cr); + sync(); + __raw_writeb(ubyte, &im->i2c[0].dr); + si_wait_i2c(); + + __raw_writeb(lbyte, &im->i2c[0].dr); + si_wait_i2c(); + + __raw_writeb(0xb4, &im->i2c[0].cr); + sync(); + __raw_writeb(chip + 1, &im->i2c[0].dr); + si_wait_i2c(); + + __raw_writeb(0xa0, &im->i2c[0].cr); + sync(); + + /* + * Dummy read + */ + __raw_readb(&im->i2c[0].dr); + + si_wait_i2c(); + + /* + * Read actual data + */ + for (i = 0; i < count; i++) + { + if (i == (count - 2)) /* Reached next to last byte, No ACK */ + __raw_writeb(0xa8, &im->i2c[0].cr); + if (i == (count - 1)) /* Reached last byte, STOP */ + __raw_writeb(0x88, &im->i2c[0].cr); + + /* Read byte of data */ + buffer[i] = __raw_readb(&im->i2c[0].dr); + + if (i == (count - 1)) + break; + si_wait_i2c(); + } + + return; +} +#endif /* CONFIG_NAND_SPL */ + +phys_size_t initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + volatile fsl_lbus_t *lbc= &im->lbus; + u32 msize; + + if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + __raw_writel(CONFIG_SYS_DDR_BASE & LAWBAR_BAR, &im->sysconf.ddrlaw[0].bar); + + msize = fixed_sdram(); + + /* Local Bus setup lbcr and mrtpr */ + __raw_writel(CONFIG_SYS_LBC_LBCR, &lbc->lbcr); + __raw_writel(CONFIG_SYS_LBC_MRTPR, &lbc->mrtpr); + sync(); + + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + +/************************************************************************* + * fixed sdram init -- reads values from boot sequencer I2C + ************************************************************************/ +static long fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msizelog2, msize = 1; +#if defined(CONFIG_NAND_SPL) + u32 i; + const u8 bytecount = 135; + u8 buffer[bytecount]; + u32 addr, data; + + si_read_i2c(0, bytecount, buffer); + + for (i = 18; i < bytecount; i += 7){ + addr = (u32)buffer[i]; + addr <<= 8; + addr |= (u32)buffer[i + 1]; + addr <<= 2; + data = (u32)buffer[i + 2]; + data <<= 8; + data |= (u32)buffer[i + 3]; + data <<= 8; + data |= (u32)buffer[i + 4]; + data <<= 8; + data |= (u32)buffer[i + 5]; + + __raw_writel(data, (u32 *)(CONFIG_SYS_IMMR + addr)); + } + + sync(); + + /* enable DDR controller */ + __raw_writel((__raw_readl(&im->ddr.sdram_cfg) | SDRAM_CFG_MEM_EN), &im->ddr.sdram_cfg); +#endif /* (CONFIG_NAND_SPL) */ + + msizelog2 = ((__raw_readl(&im->sysconf.ddrlaw[0].ar) & LAWAR_SIZE) + 1); + msize <<= (msizelog2 - 20); + + return msize; +} diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c new file mode 100644 index 00000000000..25e5c2409dc --- /dev/null +++ b/board/sheldon/simpc8313/simpc8313.c @@ -0,0 +1,134 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 + * Copyright (C) Sheldon Instruments, Inc. 2008 + * + * Author: Ron Madrid + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: Sheldon Instruments SIMPC8313\n"); + return 0; +} + +#ifndef CONFIG_NAND_SPL +static struct pci_region pci_regions[] = { + { + bus_start: CONFIG_SYS_PCI1_MEM_BASE, + phys_start: CONFIG_SYS_PCI1_MEM_PHYS, + size: CONFIG_SYS_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CONFIG_SYS_PCI1_MMIO_BASE, + phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, + size: CONFIG_SYS_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CONFIG_SYS_PCI1_IO_BASE, + phys_start: CONFIG_SYS_PCI1_IO_PHYS, + size: CONFIG_SYS_PCI1_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +void pci_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + struct pci_region *reg[] = { pci_regions }; + int warmboot; + + /* Enable all 3 PCI_CLK_OUTPUTs. */ + clk->occr |= 0xe0000000; + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; + + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; + + mpc83xx_pci_init(1, reg, warmboot); +} + +/* + * Miscellaneous late-boot configurations + */ +int misc_init_r(void) +{ + int rc = 0; + + return rc; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} +#endif +#else /* CONFIG_NAND_SPL */ +void board_init_f(ulong bootflag) +{ + NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), + CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + puts("NAND boot... "); + init_timebase(); + initdram(0); + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (gd->flags & GD_FLG_SILENT) + return; + + if (c == '\n') + NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r'); + + NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c); +} +#endif diff --git a/doc/README.simpc8313 b/doc/README.simpc8313 new file mode 100644 index 00000000000..b362c6aeea0 --- /dev/null +++ b/doc/README.simpc8313 @@ -0,0 +1,80 @@ +Sheldon Instruments SIMPC8313 Board +----------------------------------------- + +1. Board Switches and Jumpers + + S2 is used to set CFG_RESET_SOURCE. + + To boot the image in Large page NAND flash, use these DIP + switch settings for S2: + + +----------+ ON + | * * **** | + | * * | + +----------+ + 12345678 + + To boot the image in Small page NAND flash, use these DIP + switch settings for S2: + + +----------+ ON + | *** **** | + | * | + +----------+ + 12345678 + (where the '*' indicates the position of the tab of the switch.) + +2. Memory Map + The memory map looks like this: + + 0x0000_0000 0x1fff_ffff DDR 512M + 0x8000_0000 0x8fff_ffff PCI MEM 256M + 0x9000_0000 0x9fff_ffff PCI_MMIO 256M + 0xe000_0000 0xe00f_ffff IMMR 1M + 0xe200_0000 0xe20f_ffff PCI IO 16M + 0xe280_0000 0xe280_7fff NAND FLASH (CS0) 32K + or + 0xe280_0000 0xe281_ffff NAND FLASH (CS0) 128K + 0xff00_0000 0xff00_7fff FPGA (CS1) 1M + +3. Compilation + + Assuming you're using BASH (or similar) as your shell: + + export CROSS_COMPILE=your-cross-compiler-prefix- + make distclean + make SIMPC8313_LP_config + (or make SIMPC8313_SP_config, depending on the page size + of your NAND flash) + make + +4. Downloading and Flashing Images + +4.1 Reflash U-boot Image using U-boot + + =>run update_uboot + + You may want to try + =>tftp $loadaddr $uboot + first, to make sure that the TFTP load will succeed before it + goes ahead and wipes out your current firmware. And of course, + if the new u-boot doesn't boot, you can plug the board into + your PCI slot and with the supplied driver and sample app + you can reburn a working u-boot. + +4.2 Downloading and Booting Linux Kernel + + Ensure that all networking-related environment variables are set + properly (including ipaddr, serverip, gatewayip (if needed), + netmask, ethaddr, eth1addr, fdtfile, and bootfile). + + =>tftp $loadaddr uImage + =>nand write $loadaddr kernel $filesize + =>tftp $loadaddr $fdtfile + =>nand write $loadaddr 7e0000 1800 + + =>boot + +5 Notes + + The console baudrate for SIMPC8313 is 115200bps. diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h new file mode 100644 index 00000000000..a616236b770 --- /dev/null +++ b/include/configs/SIMPC8313.h @@ -0,0 +1,544 @@ +/* + * Copyright (C) Sheldon Instruments, Inc. 2008 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * simpc8313 board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_NAND_U_BOOT + +#define CONFIG_E300 1 +#define CONFIG_MPC83XX 1 +#define CONFIG_MPC831X 1 +#define CONFIG_MPC8313 1 + +#define CONFIG_PCI +#define CONFIG_83XX_GENERIC_PCI + +#define CONFIG_MISC_INIT_R + +/* + * On-board devices + * + * TSEC1 is Marvell PHY 88E1118 + */ + +#define CONFIG_SYS_33MHZ + +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ + +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +#define CONFIG_SYS_IMMR 0xE0000000 + +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR +#endif + +#define CONFIG_SYS_MEMTEST_START 0x00001000 +#define CONFIG_SYS_MEMTEST_END 0x07f00000 + +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ + +/* + * Device configurations + */ +#define CONFIG_TSEC1 + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE + +#define CONFIG_VERY_BIG_RAM +#define CONFIG_MAX_MEM_MAPPED (512 << 20) + +#define CONFIG_SYS_DDRCDR ( DDRCDR_EN \ + | DDRCDR_PZ_NOMZ \ + | DDRCDR_NZ_NOMZ \ + | DDRCDR_M_ODR ) + /* 0x73000002 TODO ODR & DRN ? */ + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + */ +#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ + | (0xFF << LBCR_BMT_SHIFT) \ + | 0xF ) /* 0x0004ff0f */ + +#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ + +/* drivers/mtd/nand/nand.c */ +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_NAND_BASE 0xFFF00000 +#else +#define CONFIG_SYS_NAND_BASE 0xE2800000 +#endif + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_ELBC 1 + +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 + +#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ + | (2< " + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#define CONFIG_FSL_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +/* + * TSEC + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ + +#define CONFIG_NET_MULTI +#define CONFIG_GMII /* MII PHY management */ + +#ifdef CONFIG_TSEC1 +#define CONFIG_HAS_ETH0 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define TSEC1_PHY_ADDR 0x0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC1_PHYIDX 0 +#endif + +#ifdef CONFIG_TSEC2 +#define CONFIG_HAS_ETH1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define TSEC2_PHY_ADDR 4 +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC2_PHYIDX 0 +#endif + + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC1" + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * Environment + */ +#if defined(CONFIG_NAND_U_BOOT) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET (768 * 1024) + #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE + #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) + #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) +#elif !defined(CONFIG_SYS_RAMBOOT) + #define CONFIG_ENV_IS_IN_FLASH 1 + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ + #define CONFIG_ENV_SIZE 0x2000 + +/* Address and size of Redundant Environment Sector */ +#else + #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_FLASH + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PCI +#define CONFIG_CMD_JFFS2 + +#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS +#endif + +#define CONFIG_CMDLINE_EDITING 1 + + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_PBSIZE ( CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) \ + + 16 ) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#define CONFIG_SYS_HRCW_LOW ( HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \ + | 0x20000000 /* reserved */ \ + | HRCWL_DDR_TO_SCB_CLK_2X1 \ + | HRCWL_CSB_TO_CLKIN_4X1 \ + | HRCWL_CORE_TO_CSB_2_5X1 ) + +#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4) + +#define CONFIG_SYS_HRCW_HIGH_BASE ( HRCWH_PCI_HOST \ + | HRCWH_PCI1_ARBITER_ENABLE \ + | HRCWH_CORE_ENABLE \ + | HRCWH_BOOTSEQ_DISABLE \ + | HRCWH_SW_WATCHDOG_DISABLE \ + | HRCWH_TSEC1M_IN_RGMII \ + | HRCWH_TSEC2M_IN_RGMII \ + | HRCWH_BIG_ENDIAN \ + | HRCWH_LALE_NORMAL ) + +#ifdef CONFIG_NAND_LP +#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \ + | HRCWH_FROM_0XFFF00100 \ + | HRCWH_ROM_LOC_NAND_LP_8BIT \ + | HRCWH_RL_EXT_NAND) +#else +#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \ + | HRCWH_FROM_0XFFF00100 \ + | HRCWH_ROM_LOC_NAND_SP_8BIT \ + | HRCWH_RL_EXT_NAND ) +#endif + +/* System IO Config */ +#define CONFIG_SYS_SICRH ( SICRH_ETSEC2_B \ + | SICRH_ETSEC2_C \ + | SICRH_ETSEC2_D \ + | SICRH_ETSEC2_E \ + | SICRH_ETSEC2_F \ + | SICRH_ETSEC2_G \ + | SICRH_TSOBI1 \ + | SICRH_TSOBI2 ) +#define CONFIG_SYS_SICRL (SICRL_USBDR \ + | SICRL_ETSEC2_A ) + +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ + | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT ) + +#define CONFIG_SYS_HID2 HID2_HBE + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR @ 0x00000000 */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10) +#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI @ 0x80000000 */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI2 not supported on 8313 */ +#define CONFIG_SYS_IBAT4L (0) +#define CONFIG_SYS_IBAT4U (0) + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) + +/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10) +#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) + +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U +#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_NETDEV eth1 + +#define CONFIG_HOSTNAME simpc8313 +#define CONFIG_ROOTPATH /tftpboot/ +#define CONFIG_BOOTFILE /tftpboot/uImage +#define CONFIG_UBOOTPATH u-boot-nand.bin /* U-Boot image on TFTP server */ +#define CONFIG_FDTFILE simpc8313.dtb + +#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ +#define CONFIG_BOOTDELAY 5 /* 5 second delay */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr" + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "ethprime=TSEC1\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "fdtaddr=ae0000\0" \ + "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ + "console=ttyS0\0" \ + "setbootargs=setenv bootargs " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ + "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ + "load_uboot=tftp 100000 u-boot-nand.bin\0" \ + "burn_uboot=nand erase u-boot 80000; " \ + "nand write 100000 u-boot $filesize\0" \ + "update_uboot=run load_uboot;run burn_uboot\0" \ + "mtdids=nand0=nand0\0" \ + "mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \ + "console=ttyS0,115200\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv rootdev /dev/nfs;" \ + "run setbootargs;" \ + "run setipargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv rootdev /dev/ram;" \ + "run setbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#undef MK_STR +#undef XMK_STR + +#endif /* __CONFIG_H */ diff --git a/nand_spl/board/sheldon/simpc8313/Makefile b/nand_spl/board/sheldon/simpc8313/Makefile new file mode 100644 index 00000000000..b0967a30b15 --- /dev/null +++ b/nand_spl/board/sheldon/simpc8313/Makefile @@ -0,0 +1,100 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# (C) Copyright 2008 Freescale Semiconductor +# (C) Copyright Sheldon Instruments, Inc. 2008 +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +NAND_SPL := y +TEXT_BASE := 0xfff00000 + +include $(TOPDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o ticks.o +COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o time.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files + +$(obj)start.S: + ln -sf $(SRCTREE)/cpu/mpc83xx/start.S $< + +$(obj)nand_boot_fsl_elbc.c: + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $< + +$(obj)sdram.c: + ln -sf $(SRCTREE)/board/$(BOARDDIR)/sdram.c $< + +$(obj)$(BOARD).c: + ln -sf $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $< + +$(obj)ns16550.c: + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $< + +$(obj)nand_init.c: + ln -sf $(SRCTREE)/cpu/mpc83xx/nand_init.c $< + +$(obj)time.c: + ln -sf $(SRCTREE)/lib_ppc/time.c $< + +$(obj)ticks.S: + ln -sf $(SRCTREE)/lib_ppc/ticks.S $< + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/sheldon/simpc8313/u-boot.lds b/nand_spl/board/sheldon/simpc8313/u-boot.lds new file mode 100644 index 00000000000..40c414549ca --- /dev/null +++ b/nand_spl/board/sheldon/simpc8313/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + . = 0xfff00000; + .text : { + *(.text*) + . = ALIGN(16); + *(.rodata*) + *(.eh_frame) + } + + . = ALIGN(8); + .data : { + *(.data*) + *(.sdata*) + _GOT2_TABLE_ = .; + *(.got2) + __got2_entries = (. - _GOT2_TABLE_) >> 2; + } + + . = ALIGN(8); + __bss_start = .; + .bss (NOLOAD) : { *(.*bss) } + _end = .; +} +ENTRY(_start) +ASSERT(_end <= 0xfff01000, "NAND bootstrap too big"); -- cgit v1.3.1 From 18af1c5f0f7402dc0d6a71b012c68025dd97cf72 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 23 Jan 2009 14:22:14 -0600 Subject: 85xx: Add a 36-bit physical configuration for MPC8572DS We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary to allow for larger memory sizes. Signed-off-by: Kumar Gala --- MAKEALL | 1 + Makefile | 8 +++++++- include/configs/MPC8572DS.h | 47 ++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 54 insertions(+), 2 deletions(-) (limited to 'Makefile') diff --git a/MAKEALL b/MAKEALL index f6271a29f1f..49d5d2f7694 100755 --- a/MAKEALL +++ b/MAKEALL @@ -372,6 +372,7 @@ LIST_85xx=" \ MPC8560ADS \ MPC8568MDS \ MPC8572DS \ + MPC8572DS_36BIT \ PM854 \ PM856 \ sbc8540 \ diff --git a/Makefile b/Makefile index 5cc950dea5f..ad79a2a6a12 100644 --- a/Makefile +++ b/Makefile @@ -2398,8 +2398,14 @@ MPC8555CDS_config: unconfig MPC8568MDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale +MPC8572DS_36BIT_config \ MPC8572DS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8572ds freescale + @mkdir -p $(obj)include + @if [ "$(findstring _36BIT_,$@)" ] ; then \ + echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \ + $(XECHO) "... enabling 36-bit physical addressing." ; \ + fi + @$(MKCONFIG) -a MPC8572DS ppc mpc85xx mpc8572ds freescale PM854_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854 diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index a0f4fcccbf6..ac0a4641e9e 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -75,6 +75,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_ENABLE_36BIT_PHYS 1 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x7fffffff #define CONFIG_PANIC_HANG /* do not reset board on panic */ @@ -85,7 +90,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ +#else #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) @@ -170,7 +179,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Local Bus Definitions */ #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#else #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 @@ -178,7 +191,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -199,7 +212,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#ifdef CONFIG_PHYS_64BIT +#define PIXIS_BASE_PHYS 0xfffdf0000ull +#else #define PIXIS_BASE_PHYS PIXIS_BASE +#endif #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ @@ -264,7 +281,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ #define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull +#else #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ CONFIG_SYS_NAND_BASE + 0x40000, \ CONFIG_SYS_NAND_BASE + 0x80000,\ @@ -383,31 +404,55 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* controller 3, direct to uli, tgtid 3, Base address 8000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull +#else #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 +#endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull +#else #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 +#endif #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull +#else #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 +#endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull +#else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 +#endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #if defined(CONFIG_PCI) -- cgit v1.3.1 From de0443614af4d16675ab436665aeb11ddc9f7214 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 20 Nov 2008 09:57:47 +0100 Subject: powerpc: 83xx: add support for the kmeter1 board This patch adds support for the kmeter1 board from Keymile, based on a Freescale MPC8360 CPU. - serial console on UART 1 - 256 MB DDR2 RAM - 64 MB NOR Flash - Ethernet RMII Mode over UCC4 - PHY SMSC LAN8700 Signed-off-by: Heiko Schocher --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/keymile/kmeter1/Makefile | 51 ++++ board/keymile/kmeter1/config.mk | 24 ++ board/keymile/kmeter1/kmeter1.c | 153 ++++++++++++ doc/README.kmeter1 | 91 +++++++ include/configs/kmeter1.h | 523 ++++++++++++++++++++++++++++++++++++++++ 8 files changed, 847 insertions(+) create mode 100644 board/keymile/kmeter1/Makefile create mode 100644 board/keymile/kmeter1/config.mk create mode 100644 board/keymile/kmeter1/kmeter1.c create mode 100644 doc/README.kmeter1 create mode 100644 include/configs/kmeter1.h (limited to 'Makefile') diff --git a/MAINTAINERS b/MAINTAINERS index dfe54a7cb72..ef53a79055d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -374,6 +374,7 @@ Heiko Schocher ids8247 MPC8247 jupiter MPC5200 + kmeter1 MPC8360 mgcoge MPC8247 mgsuvd MPC852 mucmc52 MPC5200 diff --git a/MAKEALL b/MAKEALL index f6271a29f1f..485fb884a7f 100755 --- a/MAKEALL +++ b/MAKEALL @@ -335,6 +335,7 @@ LIST_8260=" \ ######################################################################### LIST_83xx=" \ + kmeter1 \ MPC8313ERDB_33 \ MPC8313ERDB_NAND_66 \ MPC8315ERDB \ diff --git a/Makefile b/Makefile index 5cc950dea5f..685c8ae4391 100644 --- a/Makefile +++ b/Makefile @@ -2186,6 +2186,9 @@ TASREG_config : unconfig ## MPC83xx Systems ######################################################################### +kmeter1_config: unconfig + @$(MKCONFIG) kmeter1 ppc mpc83xx kmeter1 keymile + MPC8313ERDB_33_config \ MPC8313ERDB_66_config \ MPC8313ERDB_NAND_33_config \ diff --git a/board/keymile/kmeter1/Makefile b/board/keymile/kmeter1/Makefile new file mode 100644 index 00000000000..88b79f3f0fe --- /dev/null +++ b/board/keymile/kmeter1/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/keymile/kmeter1/config.mk b/board/keymile/kmeter1/config.mk new file mode 100644 index 00000000000..20f298bdb93 --- /dev/null +++ b/board/keymile/kmeter1/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2008 +# Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xF0000000 diff --git a/board/keymile/kmeter1/kmeter1.c b/board/keymile/kmeter1/kmeter1.c new file mode 100644 index 00000000000..f9a59a6443e --- /dev/null +++ b/board/keymile/kmeter1/kmeter1.c @@ -0,0 +1,153 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* port pin dir open_drain assign */ + + /* MDIO */ + {0, 1, 3, 0, 2}, /* MDIO */ + {0, 2, 1, 0, 1}, /* MDC */ + + /* UCC4 - UEC */ + {1, 14, 1, 0, 1}, /* TxD0 */ + {1, 15, 1, 0, 1}, /* TxD1 */ + {1, 20, 2, 0, 1}, /* RxD0 */ + {1, 21, 2, 0, 1}, /* RxD1 */ + {1, 18, 1, 0, 1}, /* TX_EN */ + {1, 26, 2, 0, 1}, /* RX_DV */ + {1, 27, 2, 0, 1}, /* RX_ER */ + {1, 24, 2, 0, 1}, /* COL */ + {1, 25, 2, 0, 1}, /* CRS */ + {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */ + {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */ + + /* DUART - UART2 */ + {5, 0, 1, 0, 2}, /* UART2_SOUT */ + {5, 2, 1, 0, 1}, /* UART2_RTS */ + {5, 3, 2, 0, 2}, /* UART2_SIN */ + {5, 1, 2, 0, 3}, /* UART2_CTS */ + + /* END of table */ + {0, 0, 0, 0, QE_IOP_TAB_END}, +}; + +int board_early_init_r (void) +{ + void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8); + u32 val; + + /* + * Because of errata in the UCCs, we have to write to the reserved + * registers to slow the clocks down. + */ + val = in_be32 (reg); + /* UCC1 */ + val |= 0x00003000; + /* UCC2 */ + val |= 0x0c000000; + out_be32 (reg, val); + /* enable the PHY on the PIGGY */ + setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01); + + return 0; +} + +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + msize = CONFIG_SYS_DDR_SIZE; + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { + if (ddr_size & 1) + return -1; + } + + im->sysconf.ddrlaw[0].ar = + LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); + + im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; + udelay (200); + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + + return msize; +} + +phys_size_t initdram (int board_type) +{ +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) + extern void ddr_enable_ecc (unsigned int dram_size); +#endif + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + msize = fixed_sdram (); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) + /* + * Initialize DDR ECC byte + */ + ddr_enable_ecc (msize * 1024 * 1024); +#endif + + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + +int checkboard (void) +{ + puts ("Board: Keymile kmeter1\n"); + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup (void *blob, bd_t *bd) +{ + ft_cpu_setup (blob, bd); +} +#endif diff --git a/doc/README.kmeter1 b/doc/README.kmeter1 new file mode 100644 index 00000000000..44ebb7a7811 --- /dev/null +++ b/doc/README.kmeter1 @@ -0,0 +1,91 @@ +Keymile kmeter1 Board +----------------------------------------- +1. Alternative Boot EEPROM + + Upon the kmeter1 startup the I2C_1 controller is used to fetch the boot + configuration from a serial EEPROM. During the development and debugging + phase it might be helpful to apply an alternative boot configuration in + a simple way. Therefore it is an alternative boot eeprom on the PIGGY, + which can be activated by setting the "ST" jumper on the PIGGY board. + +2. Memory Map + + BaseAddr PortSz Size Device + ----------- ------ ----- ------ + 0x0000_0000 64 bit 256MB DDR + 0x8000_0000 8 bit 256KB GPIO/PIGGY on CS1 + 0xa000_0000 8 bit 256MB PAXE on CS3 + 0xe000_0000 2MB Int Mem Reg Space + 0xf000_0000 16 bit 256MB FLASH on CS0 + + + DDR-SDRAM: + The current realization is made with four 16-bits memory devices. + Mounting options have been foreseen for device architectures from + 4Mx16 to 512Mx16. The kmeter1 is equipped with four 32Mx16 devices + thus resulting in a total capacity of 256MBytes. + +3. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make kmeter1_config + make + +4. Downloading and Flashing Images + +4.0 Download over serial line using Kermit: + + loadb + [Drop to kermit: + ^\c + send + c + ] + + + Or via tftp: + + tftp 10000 u-boot.bin + => run load + Using FSL UEC0 device + TFTP from server 192.168.1.1; our IP address is 192.168.205.4 + Filename '/tftpboot/kmeter1/u-boot.bin'. + Load address: 0x200000 + Loading: ############## + done + Bytes transferred = 204204 (31dac hex) + => + +4.1 Reflash U-boot Image using U-boot + + => run update + ..... done + Un-Protected 5 sectors + + ..... done + Erased 5 sectors + Copy to Flash... done + ..... done + Protected 5 sectors + Total of 204204 bytes were the same + Saving Environment to Flash... + . done + Un-Protected 1 sectors + . done + Un-Protected 1 sectors + Erasing Flash... + . done + Erased 1 sectors + Writing to Flash... done + . done + Protected 1 sectors + . done + Protected 1 sectors + => + +5. Notes + 1) The console baudrate for kmeter1 is 115200bps. diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h new file mode 100644 index 00000000000..e105c3bd2a9 --- /dev/null +++ b/include/configs/kmeter1.h @@ -0,0 +1,523 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ +#define CONFIG_KMETER1 1 /* KMETER1 board specific */ + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_CSB_TO_CLKIN_4X1 | \ + HRCWL_CORE_TO_CSB_2X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X6 ) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_NORMAL | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LDP_CLEAR ) + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH 0x00000006 +#define CONFIG_SYS_SICRL 0x00000000 + +#define CONFIG_BOARD_EARLY_INIT_R + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +#undef CONFIG_DDR_ECC + +/* + * DDRCDR - DDR Control Driver Register + */ + +#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */ + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS) + +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_SREN) +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x100 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x406 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_MODE 0x04440242 +#define CONFIG_SYS_DDR_MODE2 0x00800000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_40) | \ + ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \ + ( 1 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + ( 2 << TIMING_CFG1_WRREC_SHIFT) | \ + ( 2 << TIMING_CFG1_REFREC_SHIFT) | \ + ( 2 << TIMING_CFG1_ACTTORW_SHIFT) | \ + ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + ( 2 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((5 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (4 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +/* + * Memory test + */ +#define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */ +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x00F00000 + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 +#define CONFIG_SYS_FLASH_BASE_1 0xF2000000 +#define CONFIG_SYS_PIGGY_BASE 0x80000000 +#define CONFIG_SYS_PAXE_BASE 0xA0000000 +#define CONFIG_SYS_PAXE_SIZE 256 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 256KB GPIO/PIGGY + * 3 Local GPCM 8 bit 256MB PAXE + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ +#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */ + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 } + +#undef CONFIG_SYS_FLASH_CHECKSUM + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWAR1_PRELIM 0x80000011 /* 256KB window size */ + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \ + (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (0xfffc0000 | /* 256KB */ \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX | OR_GPCM_EAD) + +/* + * PAXE on the local bus CS3 + */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001b /* 256MB window size */ + +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \ + (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ + BR_V) +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200,} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#undef CONFIG_PCI /* No PCI */ + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "FSL UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_RAMBOOT */ +#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ +#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_RAMBOOT */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#endif + +#if defined(CFG_RAMBOOT) +#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_LOADS +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +#define CONFIG_SYS_HZ 1000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_256K | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* PAXE: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256K | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else /* CONFIG_PCI */ +#define CONFIG_SYS_IBAT6L (0) +#define CONFIG_SYS_IBAT6U (0) +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U +#endif /* CONFIG_PCI */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=ttyS0,${baudrate}\0" \ + "fdt_addr=f0080000\0" \ + "kernel_addr=f00a0000\0" \ + "ramdisk_addr=f03a0000\0" \ + "kernel_addr_r=400000\0" \ + "fdt_addr_r=800000\0" \ + "ramdisk_addr_r=810000\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${boot_file}; " \ + "tftp ${fdt_addr_r} ${fdt_file}; " \ + "run nfsargs addip addtty;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "fdt_file=/tftpboot/kmeter1/kmeter1.dtb\0" \ + "boot_file=/tftpboot/kmeter1/uImage\0" \ + "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0" \ + "u-boot=/tftpboot/kmeter1/u-boot.bin\0" \ + "loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \ + "load=tftp $loadaddr ${u-boot}\0" \ + "update=protect off " MK_STR(TEXT_BASE) " +$filesize;" \ + "erase " MK_STR(TEXT_BASE) " +$filesize;" \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;" \ + "protect on " MK_STR(TEXT_BASE) " +$filesize;" \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;" \ + "setenv filesize;saveenv\0" \ + "upd=run load update\0" \ + "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0" \ + "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0" \ + "loadkernel=tftp ${kernel_addr_r} ${boot_file}\0" \ + "unlock=yes\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From c620c01e96814558470698ed5cab1bf2f504d1b5 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 7 Dec 2008 10:28:57 +1100 Subject: Added initial eNET board support Signed-off-by: Graeme Russ --- MAKEALL | 1 + Makefile | 3 + board/eNET/Makefile | 57 +++++++++++ board/eNET/config.mk | 24 +++++ board/eNET/eNET.c | 167 +++++++++++++++++++++++++++++++ board/eNET/eNET_start.S | 50 ++++++++++ board/eNET/eNET_start16.S | 90 +++++++++++++++++ board/eNET/hardware.h | 35 +++++++ board/eNET/u-boot.lds | 90 +++++++++++++++++ include/configs/eNET.h | 249 ++++++++++++++++++++++++++++++++++++++++++++++ 10 files changed, 766 insertions(+) create mode 100644 board/eNET/Makefile create mode 100644 board/eNET/config.mk create mode 100644 board/eNET/eNET.c create mode 100644 board/eNET/eNET_start.S create mode 100644 board/eNET/eNET_start16.S create mode 100644 board/eNET/hardware.h create mode 100644 board/eNET/u-boot.lds create mode 100644 include/configs/eNET.h (limited to 'Makefile') diff --git a/MAKEALL b/MAKEALL index 485fb884a7f..0733dfc743e 100755 --- a/MAKEALL +++ b/MAKEALL @@ -659,6 +659,7 @@ LIST_mips_el=" \ LIST_I486=" \ sc520_cdp \ + sc520_eNET \ sc520_spunk \ sc520_spunk_rel \ " diff --git a/Makefile b/Makefile index 685c8ae4391..eeb913cb550 100644 --- a/Makefile +++ b/Makefile @@ -2996,6 +2996,9 @@ smdk6400_config : unconfig sc520_cdp_config : unconfig @$(MKCONFIG) $(@:_config=) i386 i386 sc520_cdp +eNET_config : unconfig + @$(MKCONFIG) $(@:_config=) i386 i386 eNET + sc520_spunk_config : unconfig @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk diff --git a/board/eNET/Makefile b/board/eNET/Makefile new file mode 100644 index 00000000000..4813b4b53a3 --- /dev/null +++ b/board/eNET/Makefile @@ -0,0 +1,57 @@ +# +# (C) Copyright 2008 +# Graeme Russ, graeme.russ@gmail.com. +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := eNET.o +SOBJS := eNET_start16.o eNET_start.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/eNET/config.mk b/board/eNET/config.mk new file mode 100644 index 00000000000..a76384130dd --- /dev/null +++ b/board/eNET/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x38040000 diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c new file mode 100644 index 00000000000..57dd6359e78 --- /dev/null +++ b/board/eNET/eNET.c @@ -0,0 +1,167 @@ +/* + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_HW_WATCHDOG +#include +#endif + +#include "hardware.h" + +DECLARE_GLOBAL_DATA_PTR; + +#undef SC520_CDP_DEBUG + +#ifdef SC520_CDP_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; + +void init_sc520_enet (void) +{ + /* Set CPU Speed to 100MHz */ + write_mmcr_byte(SC520_CPUCTL, 1); + gd->cpu_clk = 100000000; + + /* wait at least one millisecond */ + asm("movl $0x2000,%%ecx\n" + "wait_loop: pushl %%ecx\n" + "popl %%ecx\n" + "loop wait_loop\n": : : "ecx"); + + /* turn on the SDRAM write buffer */ + write_mmcr_byte(SC520_DBCTL, 0x11); + + /* turn on the cache and disable write through */ + asm("movl %%cr0, %%eax\n" + "andl $0x9fffffff, %%eax\n" + "movl %%eax, %%cr0\n" : : : "eax"); +} + +/* + * Miscellaneous platform dependent initializations + */ +int board_init(void) +{ + init_sc520_enet(); + + write_mmcr_byte(SC520_GPCSRT, 0x01); /* GP Chip Select Recovery Time */ + write_mmcr_byte(SC520_GPCSPW, 0x07); /* GP Chip Select Pulse Width */ + write_mmcr_byte(SC520_GPCSOFF, 0x00); /* GP Chip Select Offset */ + write_mmcr_byte(SC520_GPRDW, 0x05); /* GP Read pulse width */ + write_mmcr_byte(SC520_GPRDOFF, 0x01); /* GP Read offset */ + write_mmcr_byte(SC520_GPWRW, 0x05); /* GP Write pulse width */ + write_mmcr_byte(SC520_GPWROFF, 0x01); /* GP Write offset */ + + write_mmcr_word(SC520_PIODATA15_0, 0x0630); /* PIO15_PIO0 Data */ + write_mmcr_word(SC520_PIODATA31_16, 0x2000); /* PIO31_PIO16 Data */ + write_mmcr_word(SC520_PIODIR31_16, 0x2000); /* GPIO Direction */ + write_mmcr_word(SC520_PIODIR15_0, 0x87b5); /* GPIO Direction */ + write_mmcr_word(SC520_PIOPFS31_16, 0x0dfe); /* GPIO pin function 31-16 reg */ + write_mmcr_word(SC520_PIOPFS15_0, 0x200a); /* GPIO pin function 15-0 reg */ + write_mmcr_byte(SC520_CSPFS, 0x00f8); /* Chip Select Pin Function Select */ + + write_mmcr_long(SC520_PAR2, 0x200713f8); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */ + write_mmcr_long(SC520_PAR3, 0x2c0712f8); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */ + write_mmcr_long(SC520_PAR4, 0x300711f8); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */ + write_mmcr_long(SC520_PAR5, 0x340710f8); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */ + write_mmcr_long(SC520_PAR6, 0xe3ffc000); /* SDRAM (0x00000000, 128MB) */ + write_mmcr_long(SC520_PAR7, 0xaa3fd000); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */ + write_mmcr_long(SC520_PAR8, 0xca3fd100); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */ + write_mmcr_long(SC520_PAR9, 0x4203d900); /* SRAM (GPCS0, 0x19000000, 1MB) */ + write_mmcr_long(SC520_PAR10, 0x4e03d910); /* SRAM (GPCS3, 0x19100000, 1MB) */ + write_mmcr_long(SC520_PAR11, 0x50018100); /* DP-RAM (GPCS4, 0x18100000, 4kB) */ + write_mmcr_long(SC520_PAR12, 0x54020000); /* CFLASH1 (0x200000000, 4kB) */ + write_mmcr_long(SC520_PAR13, 0x5c020001); /* CFLASH2 (0x200010000, 4kB) */ +/* write_mmcr_long(SC520_PAR14, 0x8bfff800); */ /* BOOTCS at 0x18000000 */ +/* write_mmcr_long(SC520_PAR15, 0x38201000); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */ + + /* Disable Watchdog */ + write_mmcr_word(0x0cb0, 0x3333); + write_mmcr_word(0x0cb0, 0xcccc); + write_mmcr_word(0x0cb0, 0x0000); + + /* Chip Select Configuration */ + write_mmcr_word(SC520_BOOTCSCTL, 0x0033); + write_mmcr_word(SC520_ROMCS1CTL, 0x0615); + write_mmcr_word(SC520_ROMCS2CTL, 0x0615); + + write_mmcr_byte(SC520_ADDDECCTL, 0x02); + write_mmcr_byte(SC520_UART1CTL, 0x07); + write_mmcr_byte(SC520_SYSARBCTL,0x06); + write_mmcr_word(SC520_SYSARBMENB, 0x0003); + + /* Crystal is 33.000MHz */ + gd->bus_clk = 33000000; + + return 0; +} + +int dram_init(void) +{ + init_sc520_dram(); + return 0; +} + +void show_boot_progress(int val) +{ + uchar led_mask; + + led_mask = 0x00; + + if (val < 0) + led_mask |= LED_ERR_BITMASK; + + led_mask |= (uchar)(val & 0x001f); + outb(led_mask, LED_LATCH_ADDRESS); +} + + +int last_stage_init(void) +{ + int minor; + int major; + + major = minor = 0; + + printf("Serck Controls eNET\n"); + + return 0; +} + +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = FLASH_CFI_8BIT; + info->chipwidth = FLASH_CFI_BY8; + info->interface = FLASH_CFI_X8; + return 1; + } else + return 0; +} diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S new file mode 100644 index 00000000000..1b07d622f7f --- /dev/null +++ b/board/eNET/eNET_start.S @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "hardware.h" + +/* board early intialization */ +.globl early_board_init +early_board_init: + /* No 32-bit board specific initialisation */ + jmp *%ebp /* return to caller */ + +.globl show_boot_progress_asm +show_boot_progress_asm: + + movb %al, %dl /* Create Working Copy */ + andb $0x80, %dl /* Mask in only Error bit */ + shrb $0x02, %dl /* Shift Error bit to Error LED */ + andb $0x0f, %al /* Mask out 'Error' bit */ + orb %dl, %al /* Mask in ERR LED */ + movw $LED_LATCH_ADDRESS, %dx + outb %al, %dx + jmp *%ebp /* return to caller */ + +.globl cpu_halt_asm +cpu_halt_asm: + movb $0x0f, %al + movw $LED_LATCH_ADDRESS, %dx + outb %al, %dx + hlt + jmp cpu_halt_asm diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S new file mode 100644 index 00000000000..48e4d83a138 --- /dev/null +++ b/board/eNET/eNET_start16.S @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * 16bit initialization code. + * This code have to map the area of the boot flash + * that is used by U-boot to its final destination. + */ + +/* #include */ + +#include "hardware.h" + +.text +.section .start16, "ax" +.code16 +.globl board_init16 +board_init16: + /* Alias MMCR to 0xdf000 */ + movw $0xfffc, %dx + movl $0x800df0cb, %eax + outl %eax, %dx + + /* Set ds to point to MMCR alias */ + movw $0xdf00, %ax + movw %ax, %ds + + /* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */ + movl $0x00c0, %edi /* SC520_PAR14 */ + movl $0x8bfff800, %eax /* TODO: Check this */ + movl %eax, (%di) + + /* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */ + movl $0x00c4, %edi /* SC520_PAR15 */ + movl $0x38201000, %eax + movl %eax, (%di) + + /* Disable SDRAM write buffer */ + movw $0x0040, %di /* SC520_DBCTL */ + xorw %ax, %ax + movb %al, (%di) + + /* Disabe MMCR alias */ + movw $0xfffc, %dx + movl $0x000000cb, %eax + outl %eax, %dx + + /* the return address is stored in bp */ + jmp *%bp + +.section .bios, "ax" +.code16 +.globl realmode_reset +realmode_reset: + /* Alias MMCR to 0xdf000 */ + movw $0xfffc, %dx + movl $0x800df0cb, %eax + outl %eax, %dx + + /* Set ds to point to MMCR alias */ + movw $0xdf00, %ax + movw %ax, %ds + + /* issue software reset thorugh MMCR */ + movl $0xd72, %edi + movb $0x01, %al + movb %al, (%di) + +1: hlt + jmp 1 diff --git a/board/eNET/hardware.h b/board/eNET/hardware.h new file mode 100644 index 00000000000..42474a62fab --- /dev/null +++ b/board/eNET/hardware.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef HARDWARE_H_ +#define HARDWARE_H_ + +#define LED_LATCH_ADDRESS 0x1002 +#define LED_RUN_BITMASK 0x01 +#define LED_1_BITMASK 0x02 +#define LED_2_BITMASK 0x04 +#define LED_RX_BITMASK 0x08 +#define LED_TX_BITMASK 0x10 +#define LED_ERR_BITMASK 0x20 + +#endif /* HARDWARE_H_ */ diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds new file mode 100644 index 00000000000..f3d28ef9450 --- /dev/null +++ b/board/eNET/u-boot.lds @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) +ENTRY(_start) + +SECTIONS +{ + . = 0x38040000; /* Location of bootcode in flash */ + .text : { *(.text); } + + . = ALIGN(4); + .rodata : { *(.rodata) *(.rodata.str1.1) *(.rodata.str1.32) } + + _i386boot_text_size = SIZEOF(.text) + SIZEOF(.rodata); + + . = 0x03FF0000; /* Ram data segment to use */ + _i386boot_romdata_dest = ABSOLUTE(.); + .data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) } + _i386boot_romdata_start = LOADADDR(.data); + + . = ALIGN(4); + .got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + _i386boot_cmd_start = LOADADDR(.u_boot_cmd); + + _i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got) + SIZEOF(.u_boot_cmd); + + . = ALIGN(4); + _i386boot_bss_start = ABSOLUTE(.); + .bss (NOLOAD) : { *(.bss) } + _i386boot_bss_size = SIZEOF(.bss); + + /* 16bit realmode trampoline code */ + .realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) + SIZEOF(.u_boot_cmd)) { *(.realmode) } + + _i386boot_realmode = LOADADDR(.realmode); + _i386boot_realmode_size = SIZEOF(.realmode); + + /* 16bit BIOS emulation code (just enough to boot Linux) */ + .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) } + + _i386boot_bios = LOADADDR(.bios); + _i386boot_bios_size = SIZEOF(.bios); + + /* The load addresses below assumes that the flash + * will be mapped so that 0x387f0000 == 0xffff0000 + * at reset time + * + * The fe00 and ff00 offsets of the start32 and start16 + * segments are arbitrary, the just have to be mapped + * at reset and the code have to fit. + * The fff0 offset of reset is important, however. + */ + + . = 0xfffffe00; + .start32 : AT (0x3807fe00) { *(.start32); } + + . = 0xf800; + .start16 : AT (0x3807f800) { *(.start16); } + + . = 0xfff0; + .reset : AT (0x3807fff0) { *(.reset); } + _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) ); +} diff --git a/include/configs/eNET.h b/include/configs/eNET.h new file mode 100644 index 00000000000..87d2908a3b0 --- /dev/null +++ b/include/configs/eNET.h @@ -0,0 +1,249 @@ +/* + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Stuff still to be dealt with - + */ +#define CONFIG_RTC_MC146818 + +/* + * High Level Configuration Options + * (easy to change) + */ +#define DEBUG_PARSER + +#define CONFIG_X86 1 /* Intel X86 CPU */ +#define CONFIG_SC520 1 /* AMD SC520 */ +#define CONFIG_SC520_SSI +#define CONFIG_SHOW_BOOT_PROGRESS 1 +#define CONFIG_LAST_STAGE_INIT 1 + +/* + * If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the + * bottom (processor) board MUST be removed! + */ +#undef CONFIG_WATCHDOG +#undef CONFIG_HW_WATCHDOG + + /*----------------------------------------------------------------------- + * Video Configuration + */ +#undef CONFIG_VIDEO /* No Video Hardware */ +#undef CONFIG_CFB_CONSOLE + +/* + * Size of malloc() pool + */ +#define CONFIG_MALLOC_SIZE (CONFIG_SYS_ENV_SIZE + 128*1024) + +#define CONFIG_BAUDRATE 9600 + +/*----------------------------------------------------------------------- + * Command line configuration. + */ +#include + +#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */ +#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_BOOTD /* bootd */ +#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_ECHO /* echo arguments */ +#define CONFIG_CMD_ENV /* saveenv */ +#define CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#define CONFIG_CMD_FPGA /* FPGA configuration Support */ +#define CONFIG_CMD_IMI /* iminfo */ +#define CONFIG_CMD_IMLS /* List all found images */ +#define CONFIG_CMD_ITEST /* Integer (and string) test */ +#define CONFIG_CMD_LOADB /* loadb */ +#define CONFIG_CMD_LOADS /* loads */ +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#undef CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ +#define CONFIG_CMD_XIMG /* Load part of Multi Image */ +#undef CONFIG_CMD_IRQ /* IRQ Information */ + +#define CONFIG_BOOTDELAY 15 +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600" +/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + \ + 16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */ + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ + +#define CONFIG_SYS_HZ 1024 /* incrementer freq: 1kHz */ + + /* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * SDRAM Configuration + */ +#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18 +#define CONFIG_NR_DRAM_BANKS 4 + +/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/ +#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY +#undef CONFIG_SYS_SDRAM_REFRESH_RATE +#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY +#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T +#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T + +/*----------------------------------------------------------------------- + * CPU Features + */ +#define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */ +#define CONFIG_SYS_RESET_GENERIC /* use triple-fault to reset cpu */ +#undef CONFIG_SYS_RESET_SC520 /* use SC520 MMCR's to reset cpu */ +#define CONFIG_SYS_TIMER_SC520 /* use SC520 swtimers */ +#undef CONFIG_SYS_TIMER_GENERIC /* use the i8254 PIT timers */ +#undef CONFIG_SYS_TIMER_TSC /* use the Pentium TSC timers */ +#define CONFIG_SYS_USE_SIO_UART 0 /* prefer the uarts on the SIO to those + * in the SC520 on the CDP */ + +/*----------------------------------------------------------------------- + * Memory organization + */ +#define CONFIG_SYS_STACK_SIZE 0x8000 /* Size of bootloader stack */ +#define CONFIG_SYS_BL_START_FLASH 0x38040000 /* Address of relocated code */ +#define CONFIG_SYS_BL_START_RAM 0x03fd0000 /* Address of relocated code */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_FLASH_BASE 0x38000000 /* Boot Flash */ +#define CONFIG_SYS_FLASH_BASE_1 0x10000000 /* StrataFlash 1 */ +#define CONFIG_SYS_FLASH_BASE_2 0x11000000 /* StrataFlash 2 */ + +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + + /*----------------------------------------------------------------------- + * FLASH configuration + */ +#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */ +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */ +#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_FLASH_BASE_1, \ + CONFIG_SYS_FLASH_BASE_2} +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CONFIG_SYS_FLASH_LEGACY_512Kx8 + + /*----------------------------------------------------------------------- + * Environment configuration + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ +#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE_1 + \ + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + + + /*----------------------------------------------------------------------- + * PCI configuration + */ +#undef CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* pci plug-and-play */ +#undef CONFIG_PCI_SCAN_SHOW +#undef CONFIG_SYS_FIRST_PCI_IRQ +#undef CONFIG_SYS_SECOND_PCI_IRQ +#undef CONFIG_SYS_THIRD_PCI_IRQ +#undef CONFIG_SYS_FORTH_PCI_IRQ + +/*----------------------------------------------------------------------- + * Hardware watchdog configuration + */ +#define CONFIG_SYS_WATCHDOG_PIO_BIT 0x8000 +#define CONFIG_SYS_WATCHDIG_PIO_DATA SC520_PIODATA15_0 +#define CONFIG_SYS_WATCHDIG_PIO_CLR SC520_PIOCLR15_0 +#define CONFIG_SYS_WATCHDIG_PIO_SET SC520_PIOSET15_0 + +/*----------------------------------------------------------------------- + * FPGA configuration + */ +#define CONFIG_SYS_FPGA_PROGRAM_PIO_BIT 0x2000 +#define CONFIG_SYS_FPGA_INIT_PIO_BIT 0x4000 +#define CONFIG_SYS_FPGA_DONE_PIO_BIT 0x8000 +#define CONFIG_SYS_FPGA_PIO_DATA SC520_PIODATA31_16 +#define CONFIG_SYS_FPGA_PIO_DIRECTION SC520_PIODIR31_16 +#define CONFIG_SYS_FPGA_PIO_CLR SC520_PIOCLR31_16 +#define CONFIG_SYS_FPGA_PIO_SET SC520_PIOSET31_16 +#define CONFIG_SYS_FPGA_PROGRAM_BIT_DROP_TIME 1 /* milliseconds */ +#define CONFIG_SYS_FPGA_MAX_INIT_TIME 10 /* milliseconds */ +#define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */ +#define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */ + +#ifndef __ASSEMBLER__ +extern unsigned long ip; + +#define PRINTIP asm ("call next_line\n" \ + "next_line:\n" \ + "pop %%eax\n" \ + "movl %%eax, %0\n" \ + :"=r"(ip) \ + : /* No Input Registers */ \ + :"%eax"); \ + printf("IP: 0x%08lx (File: %s, Line: %d)\n", ip, __FILE__, __LINE__); + +#endif +#endif /* __CONFIG_H */ -- cgit v1.3.1 From a3f4c123f569474e80ea012b8db0de46afdb6443 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 24 Jan 2009 01:01:49 +0100 Subject: Makefile: keep lists sorted. Signed-off-by: Wolfgang Denk --- Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Makefile') diff --git a/Makefile b/Makefile index eeb913cb550..b9925210030 100644 --- a/Makefile +++ b/Makefile @@ -2993,12 +2993,12 @@ smdk6400_config : unconfig ######################################################################### ## AMD SC520 CDP ######################################################################### -sc520_cdp_config : unconfig - @$(MKCONFIG) $(@:_config=) i386 i386 sc520_cdp - eNET_config : unconfig @$(MKCONFIG) $(@:_config=) i386 i386 eNET +sc520_cdp_config : unconfig + @$(MKCONFIG) $(@:_config=) i386 i386 sc520_cdp + sc520_spunk_config : unconfig @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk -- cgit v1.3.1 From 85ffbbd51914925a542d8528be7f072e5ab02157 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 7 Dec 2008 10:28:58 +1100 Subject: Renamed cpu/i386/reset.S to resetvec.S Brings i386 in line with other CPUs with a reset vector and frees up reset.c for CPU reset functions Signed-off-by: Graeme Russ --- Makefile | 2 +- board/eNET/u-boot.lds | 6 +++--- board/sc520_cdp/u-boot.lds | 6 +++--- board/sc520_spunk/u-boot.lds | 6 +++--- cpu/i386/Makefile | 2 +- cpu/i386/reset.S | 37 ------------------------------------- cpu/i386/resetvec.S | 37 +++++++++++++++++++++++++++++++++++++ 7 files changed, 48 insertions(+), 48 deletions(-) delete mode 100644 cpu/i386/reset.S create mode 100644 cpu/i386/resetvec.S (limited to 'Makefile') diff --git a/Makefile b/Makefile index b9925210030..b859bcbd0d6 100644 --- a/Makefile +++ b/Makefile @@ -197,7 +197,7 @@ include $(TOPDIR)/config.mk OBJS = cpu/$(CPU)/start.o ifeq ($(CPU),i386) OBJS += cpu/$(CPU)/start16.o -OBJS += cpu/$(CPU)/reset.o +OBJS += cpu/$(CPU)/resetvec.o endif ifeq ($(CPU),ppc4xx) OBJS += cpu/$(CPU)/resetvec.o diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds index f3d28ef9450..671305ac9ae 100644 --- a/board/eNET/u-boot.lds +++ b/board/eNET/u-boot.lds @@ -75,7 +75,7 @@ SECTIONS * The fe00 and ff00 offsets of the start32 and start16 * segments are arbitrary, the just have to be mapped * at reset and the code have to fit. - * The fff0 offset of reset is important, however. + * The fff0 offset of resetvec is important, however. */ . = 0xfffffe00; @@ -85,6 +85,6 @@ SECTIONS .start16 : AT (0x3807f800) { *(.start16); } . = 0xfff0; - .reset : AT (0x3807fff0) { *(.reset); } - _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) ); + .resetvec : AT (0x3807fff0) { *(.resetvec); } + _i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) ); } diff --git a/board/sc520_cdp/u-boot.lds b/board/sc520_cdp/u-boot.lds index 719ecbaa101..0f5011ae36c 100644 --- a/board/sc520_cdp/u-boot.lds +++ b/board/sc520_cdp/u-boot.lds @@ -75,7 +75,7 @@ SECTIONS * The fe00 and ff00 offsets of the start32 and start16 * segments are arbitrary, the just have to be mapped * at reset and the code have to fit. - * The fff0 offset of reset is important, however. + * The fff0 offset of resetvec is important, however. */ @@ -86,6 +86,6 @@ SECTIONS .start16 : AT (0x387fff00) { *(.start16); } . = 0xfff0; - .reset : AT (0x387ffff0) { *(.reset); } - _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) ); + .resetvec : AT (0x387ffff0) { *(.resetvec); } + _i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) ); } diff --git a/board/sc520_spunk/u-boot.lds b/board/sc520_spunk/u-boot.lds index 4d6603cb5ec..d2436bce417 100644 --- a/board/sc520_spunk/u-boot.lds +++ b/board/sc520_spunk/u-boot.lds @@ -76,7 +76,7 @@ SECTIONS * The fe00 and ff00 offsets of the start32 and start16 * segments are arbitrary, the just have to be mapped * at reset and the code have to fit. - * The fff0 offset of reset is important, however. + * The fff0 offset of resetvec is important, however. */ @@ -87,6 +87,6 @@ SECTIONS .start16 : AT (0x387fff00) { *(.start16); } . = 0xfff0; - .reset : AT (0x387ffff0) { *(.reset); } - _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) ); + .resetvec : AT (0x387ffff0) { *(.resetvec); } + _i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) ); } diff --git a/cpu/i386/Makefile b/cpu/i386/Makefile index 50534b615b9..f20675af19c 100644 --- a/cpu/i386/Makefile +++ b/cpu/i386/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o start16.o reset.o +START = start.o start16.o resetvec.o COBJS = serial.o interrupts.o cpu.o timer.o sc520.o SOBJS = sc520_asm.o diff --git a/cpu/i386/reset.S b/cpu/i386/reset.S deleted file mode 100644 index 07a73849278..00000000000 --- a/cpu/i386/reset.S +++ /dev/null @@ -1,37 +0,0 @@ -/* - * U-boot - i386 Startup Code - * - * Copyright (c) 2002 Omicron Ceti AB, Daniel Engström - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* Reset vector, jumps to start16.S */ - -.extern start16 - -.section .reset, "ax" -.code16 -reset_vector: - cli - cld - jmp start16 - - .org 0xf - nop diff --git a/cpu/i386/resetvec.S b/cpu/i386/resetvec.S new file mode 100644 index 00000000000..d9222dd2fc6 --- /dev/null +++ b/cpu/i386/resetvec.S @@ -0,0 +1,37 @@ +/* + * U-boot - i386 Startup Code + * + * Copyright (c) 2002 Omicron Ceti AB, Daniel Engström + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Reset vector, jumps to start16.S */ + +.extern start16 + +.section .resetvec, "ax" +.code16 +reset_vector: + cli + cld + jmp start16 + + .org 0xf + nop -- cgit v1.3.1 From 407976185e0dda2c90e89027121a1071b9c77bfb Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 7 Dec 2008 10:29:00 +1100 Subject: Moved sc520 specific code into new cpu/i386/sc520 folder Signed-off-by: Graeme Russ Signed-off-by: Wolfgang Denk --- Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'Makefile') diff --git a/Makefile b/Makefile index b859bcbd0d6..121e096b194 100644 --- a/Makefile +++ b/Makefile @@ -2994,16 +2994,16 @@ smdk6400_config : unconfig ## AMD SC520 CDP ######################################################################### eNET_config : unconfig - @$(MKCONFIG) $(@:_config=) i386 i386 eNET + @$(MKCONFIG) $(@:_config=) i386 i386 eNET NULL sc520 sc520_cdp_config : unconfig - @$(MKCONFIG) $(@:_config=) i386 i386 sc520_cdp + @$(MKCONFIG) $(@:_config=) i386 i386 sc520_cdp NULL sc520 sc520_spunk_config : unconfig - @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk + @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk NULL sc520 sc520_spunk_rel_config : unconfig - @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk + @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk NULL sc520 #======================================================================== # MIPS -- cgit v1.3.1