From fb9462522991a50b95ea00fdbc495634bb6a7cca Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Thu, 12 Sep 2019 09:17:10 +0000 Subject: arm: mxs: fix comments in arch_cpu_init to match the code The comment says to clear the bypass bit, but in fact it sets it, thus selecting ref_xtal. And the next line of code does not set the divider to 12, but to (the reset value of) 1. Signed-off-by: Rasmus Villemoes --- arch/arm/cpu/arm926ejs/mxs/mxs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 85c65dcb449..585c53baf65 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -98,11 +98,11 @@ int arch_cpu_init(void) /* * Enable NAND clock */ - /* Clear bypass bit */ + /* Set bypass bit */ writel(CLKCTRL_CLKSEQ_BYPASS_GPMI, &clkctrl_regs->hw_clkctrl_clkseq_set); - /* Set GPMI clock to ref_gpmi / 12 */ + /* Set GPMI clock to ref_xtal / 1 */ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1); -- cgit v1.3.1 From abaf5c98047338c8d8774ff0a5cbc9efffda92f0 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Thu, 12 Sep 2019 09:17:11 +0000 Subject: arm: mxs: be more careful when enabling gpmi_clk The data sheet says that the DIV field cannot change while the CLKGATE bit is set or modified. So do it a little more carefully, by first clearing the bit, waiting for that to appear, then setting the DIV field. Signed-off-by: Rasmus Villemoes --- arch/arm/cpu/arm926ejs/mxs/mxs.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 585c53baf65..183aa40b6d1 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -103,8 +103,11 @@ int arch_cpu_init(void) &clkctrl_regs->hw_clkctrl_clkseq_set); /* Set GPMI clock to ref_xtal / 1 */ + clrbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_CLKGATE); + while (readl(&clkctrl_regs->hw_clkctrl_gpmi) & CLKCTRL_GPMI_CLKGATE) + ; clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, - CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1); + CLKCTRL_GPMI_DIV_MASK, 1); udelay(1000); -- cgit v1.3.1 From b6e7ef4bf71bc0927dea35fdec0a653a82ae57a7 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Tue, 10 Sep 2019 08:32:01 +0000 Subject: ARM: mxs: spl_boot.c: make early_delay more robust It's true that booting normally doesn't take long enough for the register to roll (which actually happens in a little over an hour, not just a few seconds). However, the counter starts at power-on, and if the board is held in reset to be booted over USB, one actually risks hitting wrap-around during boot, which can both result in too short delays (if the "st += delay" calculation makes st small) and theoretically also unbound delays (if st ends up being UINT_MAX and one just misses sampling digctl_microseconds at that point). It doesn't take more code to DTRT, and once bitten, twice shy. Signed-off-by: Rasmus Villemoes --- arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 5b3b51ce15f..9168b91f27a 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -25,9 +25,7 @@ static bd_t bdata __section(".data"); /* * This delay function is intended to be used only in early stage of boot, where - * clock are not set up yet. The timer used here is reset on every boot and - * takes a few seconds to roll. The boot doesn't take that long, so to keep the - * code simple, it doesn't take rolling into consideration. + * clock are not set up yet. */ void early_delay(int delay) { @@ -35,8 +33,7 @@ void early_delay(int delay) (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; uint32_t st = readl(&digctl_regs->hw_digctl_microseconds); - st += delay; - while (st > readl(&digctl_regs->hw_digctl_microseconds)) + while (readl(&digctl_regs->hw_digctl_microseconds) - st <= delay) ; } -- cgit v1.3.1