From 1289ff7bd7e4429aabbc33d37c4a93fd1e437d07 Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin Date: Mon, 24 Jan 2022 21:48:09 +0100 Subject: imx8m: lock id_swap_bypass bit in tzc380 enable According to TRM for i.MX8M Nano and Plus, GPR10 register contains lock bit for TZASC_ID_SWAP_BYPASS bit. This bit is required to be set in order to avoid AXI bus errors when GPU is enabled on the platform. TZASC_ID_SWAP_BYPASS bit is alread set for all imx8m applicable derivatives, but is missing a lock settings to be applied. Set the TZASC_ID_SWAP_BYPASS_LOCK bit for those derivatives which have it implemented. Since we're here, provide also names to bits from TRM instead of using BIT() macro in the code. Fixes: deca6cfbf5d7 ("imx8mn: set BYPASS ID SWAP to avoid AXI bus errors") Fixes: a07c7181296f ("imx8mp: set BYPASS ID SWAP to avoid AXI bus errors") Signed-off-by: Andrey Zhizhikin Cc: Peng Fan --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index b800da13a1e..45d95a7c197 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -80,8 +80,10 @@ #include #include -#define GPR_TZASC_EN BIT(0) -#define GPR_TZASC_EN_LOCK BIT(16) +#define GPR_TZASC_EN BIT(0) +#define GPR_TZASC_ID_SWAP_BYPASS BIT(1) +#define GPR_TZASC_EN_LOCK BIT(16) +#define GPR_TZASC_ID_SWAP_BYPASS_LOCK BIT(17) #define SRC_SCR_M4_ENABLE_OFFSET 3 #define SRC_SCR_M4_ENABLE_MASK BIT(3) -- cgit v1.3.1