From bbc8e053bad16366fc74943ce4c69a910c31b8b8 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Tue, 2 Feb 2016 11:28:03 +0800 Subject: armv8/ls1043a: Implement workaround for erratum A009660 Memory controller performance is not optimal with default internal target queue register value, write required value for optimal DDR performance. Signed-off-by: Mingkai Hu Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index a4eb096a64e..0ef7c9dd957 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -178,6 +178,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A009663 #define CONFIG_SYS_FSL_ERRATUM_A009929 #define CONFIG_SYS_FSL_ERRATUM_A009942 +#define CONFIG_SYS_FSL_ERRATUM_A009660 #else #error SoC not defined #endif -- cgit v1.3.1