From 7544ad0303013e625c9500a4d87d4e5bfe369ee4 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Tue, 8 May 2018 20:32:01 +0200
Subject: ARM: socfpga: Disable D cache in SPL

The bootrom seems to leave the D-cache in messed up state, make sure
the SPL disables it so it can not interfere with operation.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/spl_a10.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'arch/arm')

diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index c97eacb424f..c8e73d47c0b 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -77,6 +77,8 @@ void spl_board_init(void)
 
 void board_init_f(ulong dummy)
 {
+	dcache_disable();
+
 	socfpga_init_security_policies();
 	socfpga_sdram_remap_zero();
 
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