From d3cacb79e7062772e54cb4a2f5a23f873a630b0e Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 28 Oct 2024 20:00:34 +0100 Subject: board: rockchip: add support for Qnap TS433 devices The Qnap TS433 is a 4-bay NAS based around the RK3568. Two SATA bays are connected to the RK3568's own SATA controllers while the other two are connected to a JMicron SATA controller living on the PCIe bus. It provides one 2.5Gb and one 1Gb ethernet port as well as 3 usb ports. Signed-off-by: Heiko Stuebner Reviewed-by: Kever Yang --- arch/arm/dts/rk3568-qnap-ts433-u-boot.dtsi | 6 ++++++ arch/arm/mach-rockchip/rk3568/Kconfig | 14 ++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 arch/arm/dts/rk3568-qnap-ts433-u-boot.dtsi (limited to 'arch/arm') diff --git a/arch/arm/dts/rk3568-qnap-ts433-u-boot.dtsi b/arch/arm/dts/rk3568-qnap-ts433-u-boot.dtsi new file mode 100644 index 00000000000..19acbceb468 --- /dev/null +++ b/arch/arm/dts/rk3568-qnap-ts433-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2024 Heiko Stuebner + */ + +#include "rk356x-u-boot.dtsi" diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index e646f714c92..ce327ed6f9e 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -32,6 +32,19 @@ config TARGET_POWKIDDY_X55_RK3566 help Powkiddy X55 handheld gaming console with an RK3566 SoC. +config TARGET_QNAP_TS433_RK3568 + bool "QNAP-TS433" + help + Qnap TS433 4-bay NAS with a RK3568 SoC. + + It provides the following featureset: + * 4GB LPDDR4 + * 4GB eMMC + * 2 SATA ports connected to two RK3568's SATA controllers + * 2 SATA ports connected to a JMicron JMB58x AHCI SATA controller + * 1 1G network controller + * 1 2.5G Realtek RTL8125 network controller + config TARGET_QUARTZ64_RK3566 bool "Pine64 Quartz64" help @@ -70,6 +83,7 @@ source "board/hardkernel/odroid_m1/Kconfig" source "board/hardkernel/odroid_m1s/Kconfig" source "board/pine64/quartz64_rk3566/Kconfig" source "board/powkiddy/x55/Kconfig" +source "board/qnap/ts433/Kconfig" source "board/radxa/zero3-rk3566/Kconfig" source "board/xunlong/orangepi-3b-rk3566/Kconfig" -- cgit v1.3.1 From dfcd4afd4cc0801358f9741d6d6388928a091498 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Mon, 4 Nov 2024 20:23:00 +0800 Subject: board: rockchip: Add support for rk3588 GenBook Add support for Cool Pi GenBook, it works as a carrier board connect with CM5 SOM. Specification: - Rockchip RK3588 - LPDDR5X 8/32 GB - eMMC 64 GB - HDMI Type A out x 1 - USB 3.0 Host x 1 - USB-C 3.0 with DisplayPort AltMode - PCIE M.2 E Key for RTL8852BE Wireless connection - PCIE M.2 M Key for NVME connection - eDP panel with 1920x1080 Tested by Armbian boot on USB disk. Change-Id: I4d9b8572dc7c400077dde666633f3fea1b47dd03 Signed-off-by: Andy Yan Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-coolpi-cm5-genbook-u-boot.dtsi | 20 ++++ arch/arm/mach-rockchip/rk3588/Kconfig | 19 ++++ board/coolpi/genbook_cm5_rk3588/Kconfig | 12 +++ board/coolpi/genbook_cm5_rk3588/MAINTAINERS | 7 ++ configs/coolpi-cm5-genbook-rk3588_defconfig | 101 +++++++++++++++++++++ doc/board/coolpi/genbook_cm5_rk3588.rst | 68 ++++++++++++++ doc/board/coolpi/index.rst | 9 ++ doc/board/index.rst | 1 + doc/board/rockchip/rockchip.rst | 1 + include/configs/genbook-cm5-rk3588.h | 19 ++++ 10 files changed, 257 insertions(+) create mode 100644 arch/arm/dts/rk3588-coolpi-cm5-genbook-u-boot.dtsi create mode 100644 board/coolpi/genbook_cm5_rk3588/Kconfig create mode 100644 board/coolpi/genbook_cm5_rk3588/MAINTAINERS create mode 100644 configs/coolpi-cm5-genbook-rk3588_defconfig create mode 100644 doc/board/coolpi/genbook_cm5_rk3588.rst create mode 100644 doc/board/coolpi/index.rst create mode 100644 include/configs/genbook-cm5-rk3588.h (limited to 'arch/arm') diff --git a/arch/arm/dts/rk3588-coolpi-cm5-genbook-u-boot.dtsi b/arch/arm/dts/rk3588-coolpi-cm5-genbook-u-boot.dtsi new file mode 100644 index 00000000000..5a3073d6e7f --- /dev/null +++ b/arch/arm/dts/rk3588-coolpi-cm5-genbook-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-u-boot.dtsi" + +&fspim2_pins { + bootph-pre-ram; + bootph-some-ram; +}; + +&sfc { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; + +/* USB A out */ +&usb_host1_xhci { + snps,dis_u3_susphy_quirk; +}; diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 6f28a313325..b5a0e624a53 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -29,6 +29,24 @@ config TARGET_CM3588_NAS_RK3588 - 3.5mm Headphone out, 2.0mm PH-2A Mic in - 5V Fan connector, PWM beeper, IR receiver, RTC battery connector +config TARGET_GENBOOK_CM5_RK3588 + bool "Cool Pi CM5 GenBook" + select BOARD_LATE_INIT + help + GeenBook is a notebook based on Rockchip RK3588, and works as a carrier + board connect with CM5 SOM. + + Specification: + - Rockchip RK3588 + - LPDDR5X 8/32 GB + - eMMC 64 GB + - HDMI Type A out x 1 + - USB 3.0 Host x 1 + - USB-C 3.0 with DisplayPort AltMode + - PCIE M.2 E Key for RTL8852BE Wireless connection + - PCIE M.2 M Key for NVME connection + - eDP panel with 1920x1080 + config TARGET_JAGUAR_RK3588 bool "Theobroma Systems SBC-RK3588-AMR (Jaguar)" select BOARD_LATE_INIT @@ -367,6 +385,7 @@ config TEXT_BASE default 0x00a00000 source "board/armsom/sige7-rk3588/Kconfig" +source "board/coolpi/genbook_cm5_rk3588/Kconfig" source "board/edgeble/neural-compute-module-6/Kconfig" source "board/friendlyelec/cm3588-nas-rk3588/Kconfig" source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" diff --git a/board/coolpi/genbook_cm5_rk3588/Kconfig b/board/coolpi/genbook_cm5_rk3588/Kconfig new file mode 100644 index 00000000000..67086ea6297 --- /dev/null +++ b/board/coolpi/genbook_cm5_rk3588/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GENBOOK_CM5_RK3588 + +config SYS_BOARD + default "genbook_cm5_rk3588" + +config SYS_VENDOR + default "coolpi" + +config SYS_CONFIG_NAME + default "genbook-cm5-rk3588" + +endif diff --git a/board/coolpi/genbook_cm5_rk3588/MAINTAINERS b/board/coolpi/genbook_cm5_rk3588/MAINTAINERS new file mode 100644 index 00000000000..0496cc93b59 --- /dev/null +++ b/board/coolpi/genbook_cm5_rk3588/MAINTAINERS @@ -0,0 +1,7 @@ +GENBOOK-CM5-RK3588 +M: Andy Yan +S: Maintained +F: board/coolpi/genbook-cm5-rk3588 +F: include/configs/genbook-cm5-rk3588.h +F: configs/coolpi-cm5-genbook-rk3588_defconfig +F: arch/arm/dts/rk3588-coolpi-cm5-genbook-u-boot.dtsi diff --git a/configs/coolpi-cm5-genbook-rk3588_defconfig b/configs/coolpi-cm5-genbook-rk3588_defconfig new file mode 100644 index 00000000000..3eb5dc968af --- /dev/null +++ b/configs/coolpi-cm5-genbook-rk3588_defconfig @@ -0,0 +1,101 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-coolpi-cm5-genbook" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_GENBOOK_CM5_RK3588=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-genbook.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +# CONFIG_CMD_BIND is not set +# CONFIG_CMD_FASTBOOT is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_SPL_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/coolpi/genbook_cm5_rk3588.rst b/doc/board/coolpi/genbook_cm5_rk3588.rst new file mode 100644 index 00000000000..a02e561051a --- /dev/null +++ b/doc/board/coolpi/genbook_cm5_rk3588.rst @@ -0,0 +1,68 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +GenBook +======= +Cool Pi GenBook is a laptop powered by RK3588, it works with a +carrier board connect with CM5. + +Specification: +* Rockchip RK3588 +* LPDDR5X 8/32 GB +* eMMC 64 GB +* SPI Nor 8 MB +* HDMI Type A out x 1 +* USB 3.0 Host x 1 +* USB-C 3.0 with DisplayPort AltMode +* PCIE M.2 E Key for RTL8852BE Wireless connection +* PCIE M.2 M Key for NVME connection +* eDP panel with 1920x1080 + +Here is the step-by-step to compile and boot to U-Boot on GenBook. + +Get the TF-A and DDR init (TPL) binaries +---------------------------------------- + +.. prompt:: bash + + > cd u-boot + > export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.17.bin + > export BL31=../rkbin/bin/rk35/rk3588_bl31_v1.46.elf + > make coolpi-genbook-cm5-rk3588_defconfig + > make CROSS_COMPILE=aarch64-linux-gnu- + +This will build ``u-boot-rockchip.bin`` for eMMC and ``u-boot-rockchip-spi.bin`` for SPI Nor. + +Write u-boot to eMMC or SPI Nor from a Linux system on the laptop +----------------------------------------------------------------- + +Copy ``u-boot-rockchip.bin`` and ``u-boot-rockchip-spi.bin`` to the laptop. + +eMMC +~~~~ + +.. prompt:: bash + + dd if=u-boot-rockchip.bin of=/dev/mmcblk0 bs=512 seek=64 + +SPI Nor +~~~~~~~ + +.. prompt:: bash + + dd if=u-boot-rockchip-spi.bin of=/dev/mtdblock0 + +``upgrade_tool`` allows to flash the on-board SPI Nor via the USB TypeC interface +with help of the Rockchip loader binary. + +To enter the USB flashing mode, connect the laptop and your HOST PC with a USB-C +cable, reset the laptop with ``Loader Key`` pressed. +On your PC, check with ``lsusb -d 2207:350b``). + +To flash U-Boot on the SPI Nor with ``upgrade_tool``: + +.. prompt:: bash + + upgrade_tool db rk3588/MiniLoaderAll.bin + upgrade_tool ssd // Input 5 for SPINOR download mode + upgrade_tool wl 0 u-boot-rockchip-spi.bin + upgrade_tool rd diff --git a/doc/board/coolpi/index.rst b/doc/board/coolpi/index.rst new file mode 100644 index 00000000000..9c9593fd6aa --- /dev/null +++ b/doc/board/coolpi/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Cool Pi +================= + +.. toctree:: + :maxdepth: 2 + + genbook_cm5_rk3588 diff --git a/doc/board/index.rst b/doc/board/index.rst index 0343d9a825e..b54c1748d57 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -23,6 +23,7 @@ Board-specific doc bsh/index cloos/index congatec/index + coolpi/index coreboot/index emcraft/index emulation/index diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 0783603ec50..3056e071f4f 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -148,6 +148,7 @@ List of mainline supported Rockchip boards: - Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588) - Yanyi Tech CoolPi 4 Model B (coolpi-4b-rk3588s) - Yanyi Tech CoolPi CM5 EVB (coolpi-cm5-evb-rk3588) + - Yanyi Tech CoolPi CM5 GenBook (coolpi-cm5-genbook-rk3588) * rv1108 - Rockchip Evb-rv1108 (evb-rv1108) diff --git a/include/configs/genbook-cm5-rk3588.h b/include/configs/genbook-cm5-rk3588.h new file mode 100644 index 00000000000..194f97469df --- /dev/null +++ b/include/configs/genbook-cm5-rk3588.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __GENBOOK_CM5_RK3588_H +#define __GENBOOK_CM5_RK3588_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +/* + * As a laptop, there is no sdmmc, and we want to + * set usb the highest boot priority for third-part + * os installation. + */ +#define BOOT_TARGETS "usb mmc0" + +#include + +#endif /* __GENBOOK_CM5_RK3588_H */ -- cgit v1.3.1 From 3133b7c645157846590f6fc16e26f54d70f5e1d6 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Nov 2024 22:21:30 +0000 Subject: board: rockchip: Add FriendlyElec NanoPi R2S Plus The FriendlyElec NanoPi R2S Plus is a single-board computer based on Rockchip RK3328 SoC. It features e.g. 1 GB DDR4 RAM, 32 GB eMMC, SD-card, 2x GbE LAN, optional M.2 SDIO Wi-Fi and 2x USB 2.0 host. Features tested on a NanoPi R2S Plus 2309: - SD-card boot - eMMC boot - Ethernet - USB gadget - USB host Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3328-nanopi-r2s-plus-u-boot.dtsi | 3 + board/rockchip/evb_rk3328/MAINTAINERS | 6 ++ configs/nanopi-r2s-plus-rk3328_defconfig | 108 ++++++++++++++++++++++++ doc/board/rockchip/rockchip.rst | 1 + 4 files changed, 118 insertions(+) create mode 100644 arch/arm/dts/rk3328-nanopi-r2s-plus-u-boot.dtsi create mode 100644 configs/nanopi-r2s-plus-rk3328_defconfig (limited to 'arch/arm') diff --git a/arch/arm/dts/rk3328-nanopi-r2s-plus-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-plus-u-boot.dtsi new file mode 100644 index 00000000000..2ab32cf00a1 --- /dev/null +++ b/arch/arm/dts/rk3328-nanopi-r2s-plus-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "rk3328-nanopi-r2s-u-boot.dtsi" diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 8f619e54e0e..5f81be55b8e 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -28,6 +28,12 @@ F: configs/nanopi-r2s-rk3328_defconfig F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi F: arch/arm/dts/rk3328-nanopi-r2s.dts +NANOPI-R2S-PLUS-RK3328 +M: Jonas Karlman +S: Maintained +F: configs/nanopi-r2s-plus-rk3328_defconfig +F: arch/arm/dts/rk3328-nanopi-r2s-plus-u-boot.dtsi + ORANGEPI-R1-PLUS-RK3328 M: Tianling Shen S: Maintained diff --git a/configs/nanopi-r2s-plus-rk3328_defconfig b/configs/nanopi-r2s-plus-rk3328_defconfig new file mode 100644 index 00000000000..6e6785fcc88 --- /dev/null +++ b/configs/nanopi-r2s-plus-rk3328_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3328-nanopi-r2s-plus" +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3328=y +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s-plus.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_POWER=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_TPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSINFO=y +CONFIG_SYSRESET=y +# CONFIG_TPL_SYSRESET is not set +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 3056e071f4f..9bab86d2347 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -65,6 +65,7 @@ List of mainline supported Rockchip boards: - FriendlyElec NanoPi R2C (nanopi-r2c-rk3328) - FriendlyElec NanoPi R2C Plus (nanopi-r2c-plus-rk3328) - FriendlyElec NanoPi R2S (nanopi-r2s-rk3328) + - FriendlyElec NanoPi R2S Plus (nanopi-r2s-plus-rk3328) - Pine64 Rock64 (rock64-rk3328) - Radxa ROCK Pi E (rock-pi-e-rk3328) - Xunlong Orange Pi R1 Plus (orangepi-r1-plus-rk3328) -- cgit v1.3.1 From b21fd44c84fd5053a350de6138fb832839c04b67 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 6 Nov 2024 12:29:42 +0100 Subject: rockchip: rk3399: merge CRU check within rk3399_force_power_on_reset To prepare to support forcing power on reset from TPL which would have the exact same logic, just in an earlier stage, let's merge the CRU check that triggers the power on reset with the rest of the logic. Reviewed-by: Paul Kocialkowski Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3399/rk3399.c | 43 +++++++++++++++++----------------- 1 file changed, 21 insertions(+), 22 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index edccb2a3980..7b6a822ed04 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -172,9 +172,29 @@ void board_debug_uart_init(void) #if defined(CONFIG_XPL_BUILD) && !defined(CONFIG_TPL_BUILD) static void rk3399_force_power_on_reset(void) { + const struct rockchip_cru *cru = rockchip_get_cru(); ofnode node; struct gpio_desc sysreset_gpio; + /* + * The RK3399 resets only 'almost all logic' (see also in the + * TRM "3.9.4 Global software reset"), when issuing a software + * reset. This may cause issues during boot-up for some + * configurations of the application software stack. + * + * To work around this, we test whether the last reset reason + * was a power-on reset and (if not) issue an overtemp-reset to + * reset the entire module. + * + * While this was previously fixed by modifying the various + * places that could generate a software reset (e.g. U-Boot's + * sysreset driver, the ATF or Linux), we now have it here to + * ensure that we no longer have to track this through the + * various components. + */ + if (cru->glb_rst_st == 0) + return; + if (!IS_ENABLED(CONFIG_SPL_GPIO)) { debug("%s: trying to force a power-on reset but no GPIO " "support in SPL!\n", __func__); @@ -206,27 +226,6 @@ void spl_board_init(void) { led_setup(); - if (IS_ENABLED(CONFIG_SPL_GPIO)) { - struct rockchip_cru *cru = rockchip_get_cru(); - - /* - * The RK3399 resets only 'almost all logic' (see also in the - * TRM "3.9.4 Global software reset"), when issuing a software - * reset. This may cause issues during boot-up for some - * configurations of the application software stack. - * - * To work around this, we test whether the last reset reason - * was a power-on reset and (if not) issue an overtemp-reset to - * reset the entire module. - * - * While this was previously fixed by modifying the various - * places that could generate a software reset (e.g. U-Boot's - * sysreset driver, the ATF or Linux), we now have it here to - * ensure that we no longer have to track this through the - * various components. - */ - if (cru->glb_rst_st != 0) - rk3399_force_power_on_reset(); - } + rk3399_force_power_on_reset(); } #endif -- cgit v1.3.1 From 7461d55ca7d1a55d5f90c5d33501a369eabd4277 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 6 Nov 2024 12:29:43 +0100 Subject: rockchip: tpl: allow to call board/SoC-specific code before DRAM init This defines a weak tpl_board_init function that can be used for running board/SoC-specific code before the DRAM init happens, similarly to spl_board_init() for SPL. Reviewed-by: Paul Kocialkowski Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/tpl.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c index bbb9329e725..6b880f19f84 100644 --- a/arch/arm/mach-rockchip/tpl.c +++ b/arch/arm/mach-rockchip/tpl.c @@ -21,6 +21,10 @@ #include #endif +__weak void tpl_board_init(void) +{ +} + void board_init_f(ulong dummy) { struct udevice *dev; @@ -54,6 +58,8 @@ void board_init_f(ulong dummy) if (IS_ENABLED(CONFIG_SYS_ARCH_TIMER)) timer_init(); + tpl_board_init(); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { printf("DRAM init failed: %d\n", ret); -- cgit v1.3.1 From 0a17123dedf827f4ca9b158252279adf03906307 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 6 Nov 2024 12:29:44 +0100 Subject: rockchip: rk3399: move sysreset-gpio logic to TPL If TPL_GPIO and TPL_PINCTRL_ROCKCHIP are enabled and a sysreset-gpio is provided in the TPL Device Tree, this will trigger a system reset similar to what's currently been done in SPL whenever the RK3399 "warm" boots. Because there's currently only one user of sysreset-gpio logic, and TPL is enabled on that board, so let's migrate the logic and that board to do it in TPL. There are three reasons for moving this earlier: - faster boot time as we don't need to reach SPL to be able to reset the system on a condition we know is already met in TPL, - have less code to be impacted by the issue this system reset works around (that is, "unclean" SoC registers after a reboot), - less confusion around the reason for restarting. Indeed when done from SPL, the following log can be observed: """ U-Boot TPL 2025.01-rc1-00165-gd79216ca9878-dirty (Nov 05 2024 - 15:31:45) Channel 0: DDR3, 666MHz BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB Channel 1: DDR3, 666MHz BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB 256B stride Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL 2025.01-rc1-00165-gd79216ca9878-dirty (Nov 05 2024 - 15:31:45 +0100) Trying to boot from MMC2 U-Boot TPL 2025.01-rc1-00165-gd79216ca9878-dirty (Nov 05 2024 - 15:31:45) """ possibly hinting at an issue within the SPL when loading the fitImage from MMC2 instead of the normal course of events (a system reset). Signed-off-by: Quentin Schulz Reviewed-by: Paul Kocialkowski Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3399/rk3399.c | 15 ++++++++++----- configs/puma-rk3399_defconfig | 3 +++ 2 files changed, 13 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 7b6a822ed04..0c28241c603 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -169,7 +169,8 @@ void board_debug_uart_init(void) } #endif -#if defined(CONFIG_XPL_BUILD) && !defined(CONFIG_TPL_BUILD) +#if defined(CONFIG_XPL_BUILD) +#if defined(CONFIG_TPL_BUILD) static void rk3399_force_power_on_reset(void) { const struct rockchip_cru *cru = rockchip_get_cru(); @@ -195,9 +196,9 @@ static void rk3399_force_power_on_reset(void) if (cru->glb_rst_st == 0) return; - if (!IS_ENABLED(CONFIG_SPL_GPIO)) { + if (!IS_ENABLED(CONFIG_TPL_GPIO)) { debug("%s: trying to force a power-on reset but no GPIO " - "support in SPL!\n", __func__); + "support in TPL!\n", __func__); return; } @@ -218,6 +219,11 @@ static void rk3399_force_power_on_reset(void) dm_gpio_set_value(&sysreset_gpio, 1); } +void tpl_board_init(void) +{ + rk3399_force_power_on_reset(); +} +# else void __weak led_setup(void) { } @@ -225,7 +231,6 @@ void __weak led_setup(void) void spl_board_init(void) { led_setup(); - - rk3399_force_power_on_reset(); } #endif +#endif diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 67c0ee72c92..7a180b14130 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_LOAD=y CONFIG_TPL=y +CONFIG_TPL_GPIO=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set @@ -78,6 +79,8 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_TPL_PINCTRL=y +CONFIG_TPL_PINCTRL_FULL=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y CONFIG_SPL_PMIC_RK8XX=y -- cgit v1.3.1