From 3c265bbe4d1c16f7c781c0f99df78c373c2fbd79 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Sat, 16 Feb 2019 11:48:58 +1300 Subject: arm: sync armada-xp dts files from Linux 5.0 Bring in the Armada 370/XP dts/dtsi files from Linux. As U-Boot hasn't got the new NAND driver the updating binding has not been included. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- arch/arm/dts/armada-370-xp.dtsi | 133 ++++++++----------- arch/arm/dts/armada-xp-gp.dts | 167 ++++++++++------------- arch/arm/dts/armada-xp-maxbcm.dts | 24 ++-- arch/arm/dts/armada-xp-mv78230.dtsi | 55 ++------ arch/arm/dts/armada-xp-mv78260.dtsi | 58 +++----- arch/arm/dts/armada-xp-mv78460.dtsi | 58 +++----- arch/arm/dts/armada-xp-synology-ds414.dts | 199 ++++++++++++++------------- arch/arm/dts/armada-xp-theadorable.dts | 69 +++++----- arch/arm/dts/armada-xp.dtsi | 214 +++++++++++++++++------------- 9 files changed, 435 insertions(+), 542 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/armada-370-xp.dtsi b/arch/arm/dts/armada-370-xp.dtsi index 0b2a78d3930..e4c35d4e98f 100644 --- a/arch/arm/dts/armada-370-xp.dtsi +++ b/arch/arm/dts/armada-370-xp.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 370 and Armada XP SoC * @@ -8,50 +9,10 @@ * Thomas Petazzoni * Ben Dooks * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * This file contains the definitions that are common to the Armada * 370 and Armada XP SoC. */ -/include/ "skeleton64.dtsi" - #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) / { @@ -86,7 +47,7 @@ pcie-mem-aperture = <0xf8000000 0x7e00000>; pcie-io-aperture = <0xffe00000 0x100000>; - devbus-bootcs { + devbus_bootcs: devbus-bootcs { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; @@ -96,7 +57,7 @@ status = "disabled"; }; - devbus-cs0 { + devbus_cs0: devbus-cs0 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; @@ -106,7 +67,7 @@ status = "disabled"; }; - devbus-cs1 { + devbus_cs1: devbus-cs1 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; @@ -116,7 +77,7 @@ status = "disabled"; }; - devbus-cs2 { + devbus_cs2: devbus-cs2 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; @@ -126,7 +87,7 @@ status = "disabled"; }; - devbus-cs3 { + devbus_cs3: devbus-cs3 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; @@ -141,34 +102,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - u-boot,dm-pre-reloc; - rtc@10300 { + rtc: rtc@10300 { compatible = "marvell,orion-rtc"; reg = <0x10300 0x20>; interrupts = <50>; }; - spi0: spi@10600 { - reg = <0x10600 0x28>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <30>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - reg = <0x10680 0x28>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <92>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - i2c0: i2c@11000 { compatible = "marvell,mv64xxx-i2c"; #address-cells = <1>; @@ -235,33 +175,38 @@ msi-controller; }; - coherency-fabric@20200 { + coherencyfab: coherency-fabric@20200 { compatible = "marvell,coherency-fabric"; reg = <0x20200 0xb0>, <0x21010 0x1c>; }; - timer@20300 { + timer: timer@20300 { reg = <0x20300 0x30>, <0x21040 0x30>; interrupts = <37>, <38>, <39>, <40>, <5>, <6>; }; - watchdog@20300 { + watchdog: watchdog@20300 { reg = <0x20300 0x34>, <0x20704 0x4>; }; - pmsu@22000 { + cpurst: cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x8>; + }; + + pmsu: pmsu@22000 { compatible = "marvell,armada-370-pmsu"; reg = <0x22000 0x1000>; }; - usb@50000 { + usb0: usb@50000 { compatible = "marvell,orion-ehci"; reg = <0x50000 0x500>; interrupts = <45>; status = "disabled"; }; - usb@51000 { + usb1: usb@51000 { compatible = "marvell,orion-ehci"; reg = <0x51000 0x500>; interrupts = <46>; @@ -275,7 +220,7 @@ status = "disabled"; }; - mdio: mdio { + mdio: mdio@72004 { #address-cells = <1>; #size-cells = <0>; compatible = "marvell,orion-mdio"; @@ -290,7 +235,7 @@ status = "disabled"; }; - sata@a0000 { + sata: sata@a0000 { compatible = "marvell,armada-370-sata"; reg = <0xa0000 0x5000>; interrupts = <55>; @@ -309,7 +254,7 @@ status = "disabled"; }; - mvsdio@d4000 { + sdio: mvsdio@d4000 { compatible = "marvell,orion-sdio"; reg = <0xd4000 0x200>; interrupts = <54>; @@ -321,6 +266,42 @@ status = "disabled"; }; }; + + spi0: spi@10600 { + reg = , /* control */ + , /* CS0 */ + , /* CS1 */ + , /* CS2 */ + , /* CS3 */ + , /* CS4 */ + , /* CS5 */ + , /* CS6 */ + ; /* CS7 */ + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <30>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + reg = , /* control */ + , /* CS0 */ + , /* CS1 */ + , /* CS2 */ + , /* CS3 */ + , /* CS4 */ + , /* CS5 */ + , /* CS6 */ + ; /* CS7 */ + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <92>; + clocks = <&coreclk 0>; + status = "disabled"; + }; }; clocks { diff --git a/arch/arm/dts/armada-xp-gp.dts b/arch/arm/dts/armada-xp-gp.dts index 27799d1254e..1139e9469a8 100644 --- a/arch/arm/dts/armada-xp-gp.dts +++ b/arch/arm/dts/armada-xp-gp.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Marvell Armada XP development board * (DB-MV784MP-GP) @@ -8,44 +9,6 @@ * Gregory CLEMENT * Thomas Petazzoni * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Note: this Device Tree assumes that the bootloader has remapped the * internal registers to 0xf1000000 (instead of the default * 0xd0000000). The 0xf1000000 is the default used by the recent, @@ -68,11 +31,7 @@ stdout-path = "serial0:115200n8"; }; - aliases { - spi0 = &spi0; - }; - - memory { + memory@0 { device_type = "memory"; /* * 8 GB of plug-in RAM modules by default.The amount @@ -98,7 +57,10 @@ soc { ranges = ; + MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000 + MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 + MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000 + MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>; devbus-bootcs { status = "okay"; @@ -128,31 +90,9 @@ }; }; - pcie-controller { - status = "okay"; - - /* - * The 3 slots are physically present as - * standard PCIe slots on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - pcie@9,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - pcie@10,0 { - /* Port 3, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { serial@12000 { status = "okay"; - u-boot,dm-pre-reloc; }; serial@12100 { status = "okay"; @@ -177,43 +117,33 @@ status = "okay"; }; - mdio { - phy0: ethernet-phy@0 { - reg = <16>; - }; - - phy1: ethernet-phy@1 { - reg = <17>; - }; - - phy2: ethernet-phy@2 { - reg = <18>; - }; - - phy3: ethernet-phy@3 { - reg = <19>; - }; - }; - ethernet@70000 { status = "okay"; phy = <&phy0>; phy-mode = "qsgmii"; + buffer-manager = <&bm>; + bm,pool-long = <0>; }; ethernet@74000 { status = "okay"; phy = <&phy1>; phy-mode = "qsgmii"; + buffer-manager = <&bm>; + bm,pool-long = <1>; }; ethernet@30000 { status = "okay"; phy = <&phy2>; phy-mode = "qsgmii"; + buffer-manager = <&bm>; + bm,pool-long = <2>; }; ethernet@34000 { status = "okay"; phy = <&phy3>; phy-mode = "qsgmii"; + buffer-manager = <&bm>; + bm,pool-long = <3>; }; /* Front-side USB slot */ @@ -226,27 +156,72 @@ status = "okay"; }; - spi0: spi@10600 { + bm@c0000 { status = "okay"; - u-boot,dm-pre-reloc; - - spi-flash@0 { - u-boot,dm-pre-reloc; - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; }; nand@d0000 { status = "okay"; + label = "pxa3xx_nand-0"; num-cs = <1>; marvell,nand-keep-config; - marvell,nand-enable-arbiter; nand-on-flash-bbt; }; }; + + bm-bppi { + status = "okay"; + }; + }; +}; + +&pciec { + status = "okay"; + + /* + * The 3 slots are physically present as + * standard PCIe slots on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + pcie@9,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + pcie@a,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg = <16>; + }; + + phy1: ethernet-phy@1 { + reg = <17>; + }; + + phy2: ethernet-phy@2 { + reg = <18>; + }; + + phy3: ethernet-phy@3 { + reg = <19>; + }; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; }; }; diff --git a/arch/arm/dts/armada-xp-maxbcm.dts b/arch/arm/dts/armada-xp-maxbcm.dts index d7d7f65c85f..921eb708625 100644 --- a/arch/arm/dts/armada-xp-maxbcm.dts +++ b/arch/arm/dts/armada-xp-maxbcm.dts @@ -225,18 +225,6 @@ status = "okay"; }; - spi0: spi@10600 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; - }; - nand@d0000 { status = "okay"; num-cs = <1>; @@ -247,3 +235,15 @@ }; }; }; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; +}; diff --git a/arch/arm/dts/armada-xp-mv78230.dtsi b/arch/arm/dts/armada-xp-mv78230.dtsi index f6bab9fb20a..8558bf6bb54 100644 --- a/arch/arm/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/dts/armada-xp-mv78230.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada XP family SoC * @@ -5,44 +6,6 @@ * * Thomas Petazzoni * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Contains definitions specific to the Armada XP MV78230 SoC that are not * common to all Armada XP SoCs. */ @@ -207,25 +170,33 @@ internal-regs { gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18100 0x40>, <0x181c0 0x08>; + reg-names = "gpio", "pwm"; ngpios = <32>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <82>, <83>, <84>, <85>; + clocks = <&coreclk 0>; }; gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18140 0x40>, <0x181c8 0x08>; + reg-names = "gpio", "pwm"; ngpios = <17>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <87>, <88>, <89>; + clocks = <&coreclk 0>; }; }; }; diff --git a/arch/arm/dts/armada-xp-mv78260.dtsi b/arch/arm/dts/armada-xp-mv78260.dtsi index d39231f69d9..2d85fe8ac32 100644 --- a/arch/arm/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/dts/armada-xp-mv78260.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada XP family SoC * @@ -5,44 +6,6 @@ * * Thomas Petazzoni * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Contains definitions specific to the Armada XP MV78260 SoC that are not * common to all Armada XP SoCs. */ @@ -294,29 +257,38 @@ internal-regs { gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18100 0x40>, <0x181c0 0x08>; + reg-names = "gpio", "pwm"; ngpios = <32>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <82>, <83>, <84>, <85>; + clocks = <&coreclk 0>; }; gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18140 0x40>, <0x181c8 0x08>; + reg-names = "gpio", "pwm"; ngpios = <32>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <87>, <88>, <89>, <90>; + clocks = <&coreclk 0>; }; gpio2: gpio@18180 { - compatible = "marvell,orion-gpio"; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; reg = <0x18180 0x40>; ngpios = <3>; gpio-controller; diff --git a/arch/arm/dts/armada-xp-mv78460.dtsi b/arch/arm/dts/armada-xp-mv78460.dtsi index c642565d1bc..230a3fd36b3 100644 --- a/arch/arm/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/dts/armada-xp-mv78460.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada XP family SoC * @@ -5,44 +6,6 @@ * * Thomas Petazzoni * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Contains definitions specific to the Armada XP MV78460 SoC that are not * common to all Armada XP SoCs. */ @@ -333,29 +296,38 @@ internal-regs { gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18100 0x40>, <0x181c0 0x08>; + reg-names = "gpio", "pwm"; ngpios = <32>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <82>, <83>, <84>, <85>; + clocks = <&coreclk 0>; }; gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18140 0x40>, <0x181c8 0x08>; + reg-names = "gpio", "pwm"; ngpios = <32>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = <87>, <88>, <89>, <90>; + clocks = <&coreclk 0>; }; gpio2: gpio@18180 { - compatible = "marvell,orion-gpio"; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; reg = <0x18180 0x40>; ngpios = <3>; gpio-controller; diff --git a/arch/arm/dts/armada-xp-synology-ds414.dts b/arch/arm/dts/armada-xp-synology-ds414.dts index 0a60ddfa414..861967cd7e8 100644 --- a/arch/arm/dts/armada-xp-synology-ds414.dts +++ b/arch/arm/dts/armada-xp-synology-ds414.dts @@ -1,13 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree file for Synology DS414 * * Copyright (C) 2014, Arnaud EBALARD * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * * Note: this Device Tree assumes that the bootloader has remapped the * internal registers to 0xf1000000 (instead of the old 0xd0000000). * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot @@ -42,36 +38,16 @@ spi0 = &spi0; }; - memory { + memory@0 { device_type = "memory"; reg = <0 0x00000000 0 0x40000000>; /* 1GB */ }; soc { ranges = ; - - pcie-controller { - status = "okay"; - - /* - * Connected to Marvell 88SX7042 SATA-II controller - * handling the four disks. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* - * Connected to EtronTech EJ168A XHCI controller - * providing the two rear USB 3.0 ports. - */ - pcie@5,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 + MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 + MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; internal-regs { @@ -80,64 +56,6 @@ status = "disabled"; }; - spi0: spi@10600 { - status = "okay"; - u-boot,dm-pre-reloc; - - spi-flash@0 { - u-boot,dm-pre-reloc; - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q064"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - - /* - * Warning! - * - * Synology u-boot uses its compiled-in environment - * and it seems Synology did not care to change u-boot - * default configuration in order to allow saving a - * modified environment at a sensible location. So, - * if you do a 'saveenv' under u-boot, your modified - * environment will be saved at 1MB after the start - * of the flash, i.e. in the middle of the uImage. - * For that reason, it is strongly advised not to - * change the default environment, unless you know - * what you are doing. - */ - partition@00000000 { /* u-boot */ - label = "RedBoot"; - reg = <0x00000000 0x000d0000>; /* 832KB */ - }; - - partition@000c0000 { /* uImage */ - label = "zImage"; - reg = <0x000d0000 0x002d0000>; /* 2880KB */ - }; - - partition@003a0000 { /* uInitramfs */ - label = "rd.gz"; - reg = <0x003a0000 0x00430000>; /* 4250KB */ - }; - - partition@007d0000 { /* MAC address and serial number */ - label = "vendor"; - reg = <0x007d0000 0x00010000>; /* 64KB */ - }; - - partition@007e0000 { - label = "RedBoot config"; - reg = <0x007e0000 0x00010000>; /* 64KB */ - }; - - partition@007f0000 { - label = "FIS directory"; - reg = <0x007f0000 0x00010000>; /* 64KB */ - }; - }; - }; - i2c@11000 { clock-frequency = <400000>; status = "okay"; @@ -179,16 +97,6 @@ status = "okay"; }; - mdio { - phy0: ethernet-phy@0 { /* Marvell 88E1512 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { /* Marvell 88E1512 */ - reg = <1>; - }; - }; - ethernet@70000 { status = "okay"; pinctrl-0 = <&ge0_rgmii_pins>; @@ -215,7 +123,7 @@ &sata3_pwr_pin &sata4_pwr_pin>; pinctrl-names = "default"; - sata1_regulator: sata1-regulator { + sata1_regulator: sata1-regulator@1 { compatible = "regulator-fixed"; reg = <1>; regulator-name = "SATA1 Power"; @@ -228,7 +136,7 @@ gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; - sata2_regulator: sata2-regulator { + sata2_regulator: sata2-regulator@2 { compatible = "regulator-fixed"; reg = <2>; regulator-name = "SATA2 Power"; @@ -241,7 +149,7 @@ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; }; - sata3_regulator: sata3-regulator { + sata3_regulator: sata3-regulator@3 { compatible = "regulator-fixed"; reg = <3>; regulator-name = "SATA3 Power"; @@ -254,7 +162,7 @@ gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; - sata4_regulator: sata4-regulator { + sata4_regulator: sata4-regulator@4 { compatible = "regulator-fixed"; reg = <4>; regulator-name = "SATA4 Power"; @@ -269,6 +177,39 @@ }; }; +&pciec { + status = "okay"; + + /* + * Connected to Marvell 88SX7042 SATA-II controller + * handling the four disks. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* + * Connected to EtronTech EJ168A XHCI controller + * providing the two rear USB 3.0 ports. + */ + pcie@5,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + + +&mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1512 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1512 */ + reg = <1>; + }; +}; + &pinctrl { sata1_pwr_pin: sata1-pwr-pin { marvell,pins = "mpp42"; @@ -335,3 +276,59 @@ marvell,function = "gpio"; }; }; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q064", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + + /* + * Warning! + * + * Synology u-boot uses its compiled-in environment + * and it seems Synology did not care to change u-boot + * default configuration in order to allow saving a + * modified environment at a sensible location. So, + * if you do a 'saveenv' under u-boot, your modified + * environment will be saved at 1MB after the start + * of the flash, i.e. in the middle of the uImage. + * For that reason, it is strongly advised not to + * change the default environment, unless you know + * what you are doing. + */ + partition@0 { /* u-boot */ + label = "RedBoot"; + reg = <0x00000000 0x000d0000>; /* 832KB */ + }; + + partition@c0000 { /* uImage */ + label = "zImage"; + reg = <0x000d0000 0x002d0000>; /* 2880KB */ + }; + + partition@3a0000 { /* uInitramfs */ + label = "rd.gz"; + reg = <0x003a0000 0x00430000>; /* 4250KB */ + }; + + partition@7d0000 { /* MAC address and serial number */ + label = "vendor"; + reg = <0x007d0000 0x00010000>; /* 64KB */ + }; + + partition@7e0000 { + label = "RedBoot config"; + reg = <0x007e0000 0x00010000>; /* 64KB */ + }; + + partition@7f0000 { + label = "FIS directory"; + reg = <0x007f0000 0x00010000>; /* 64KB */ + }; + }; +}; diff --git a/arch/arm/dts/armada-xp-theadorable.dts b/arch/arm/dts/armada-xp-theadorable.dts index 5695e9b7585..bcb4bfdd5c1 100644 --- a/arch/arm/dts/armada-xp-theadorable.dts +++ b/arch/arm/dts/armada-xp-theadorable.dts @@ -126,40 +126,6 @@ status = "okay"; }; - spi0: spi@10600 { - status = "okay"; - u-boot,dm-pre-reloc; - - spi-flash@0 { - u-boot,dm-pre-reloc; - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor", "spi-flash"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <27777777>; - }; - - fpga@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-generic-device"; - reg = <1>; /* Chip select 1 */ - spi-max-frequency = <27777777>; - }; - }; - - spi1: spi@10680 { - status = "okay"; - - fpga@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-generic-device"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <27777777>; - }; - }; - /* The LCD controller is only used on this board */ lcd0: lcd-controller@e0000 { compatible = "marvell,armada-xp-lcd"; @@ -188,6 +154,41 @@ }; }; +&spi0 { + status = "okay"; + u-boot,dm-pre-reloc; + + spi-flash@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", "jedec,spi-nor", "spi-flash"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <27777777>; + }; + + fpga@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-generic-device"; + reg = <1>; /* Chip select 1 */ + spi-max-frequency = <27777777>; + }; +}; + +&spi1 { + status = "okay"; + + fpga@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-generic-device"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <27777777>; + }; +}; + + &pciec { status = "okay"; diff --git a/arch/arm/dts/armada-xp.dtsi b/arch/arm/dts/armada-xp.dtsi index 3fac39e41d7..d856d960227 100644 --- a/arch/arm/dts/armada-xp.dtsi +++ b/arch/arm/dts/armada-xp.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada XP family SoC * @@ -8,44 +9,6 @@ * Thomas Petazzoni * Ben Dooks * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * * Contains definitions specific to the Armada XP SoC that are not * common to all Armada SoCs. */ @@ -53,6 +16,9 @@ #include "armada-370-xp.dtsi" / { + #address-cells = <2>; + #size-cells = <2>; + model = "Marvell Armada XP family SoC"; compatible = "marvell,armadaxp", "marvell,armada-370-xp"; @@ -71,12 +37,12 @@ }; internal-regs { - sdramc@1400 { + sdramc: sdramc@1400 { compatible = "marvell,armada-xp-sdram-controller"; reg = <0x1400 0x500>; }; - L2: l2-cache { + L2: l2-cache@8000 { compatible = "marvell,aurora-system-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; @@ -85,29 +51,6 @@ wt-override; }; - spi0: spi@10600 { - compatible = "marvell,armada-xp-spi", - "marvell,orion-spi"; - pinctrl-0 = <&spi0_pins>; - pinctrl-names = "default"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-xp-spi", - "marvell,orion-spi"; - }; - - - i2c0: i2c@11000 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11000 0x100>; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11100 0x100>; - }; - uart2: serial@12200 { compatible = "snps,dw-apb-uart"; pinctrl-0 = <&uart2_pins>; @@ -132,7 +75,7 @@ status = "disabled"; }; - system-controller@18200 { + systemc: system-controller@18200 { compatible = "marvell,armada-370-xp-system-controller"; reg = <0x18200 0x500>; }; @@ -150,7 +93,7 @@ #clock-cells = <1>; }; - thermal@182b0 { + thermal: thermal@182b0 { compatible = "marvell,armadaxp-thermal"; reg = <0x182b0 0x4 0x184d0 0x4>; @@ -164,25 +107,9 @@ clocks = <&coreclk 1>; }; - interrupt-controller@20a00 { - reg = <0x20a00 0x2d0>, <0x21070 0x58>; - }; - - timer@20300 { - compatible = "marvell,armada-xp-timer"; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - watchdog@20300 { - compatible = "marvell,armada-xp-wdt"; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; - }; - - cpurst@20800 { - compatible = "marvell,armada-370-cpu-reset"; - reg = <0x20800 0x20>; + cpu-config@21000 { + compatible = "marvell,armada-xp-cpu-config"; + reg = <0x21000 0x8>; }; eth2: ethernet@30000 { @@ -193,15 +120,7 @@ status = "disabled"; }; - usb@50000 { - clocks = <&gateclk 18>; - }; - - usb@51000 { - clocks = <&gateclk 19>; - }; - - usb@52000 { + usb2: usb@52000 { compatible = "marvell,orion-ehci"; reg = <0x52000 0x500>; interrupts = <47>; @@ -209,7 +128,7 @@ status = "disabled"; }; - xor@60900 { + xor1: xor@60900 { compatible = "marvell,orion-xor"; reg = <0x60900 0x100 0x60b00 0x100>; @@ -237,7 +156,27 @@ compatible = "marvell,armada-xp-neta"; }; - xor@f0900 { + cesa: crypto@90000 { + compatible = "marvell,armada-xp-crypto"; + reg = <0x90000 0x10000>; + reg-names = "regs"; + interrupts = <48>, <49>; + clocks = <&gateclk 23>, <&gateclk 23>; + clock-names = "cesa0", "cesa1"; + marvell,crypto-srams = <&crypto_sram0>, + <&crypto_sram1>; + marvell,crypto-sram-size = <0x800>; + }; + + bm: bm@c0000 { + compatible = "marvell,armada-380-neta-bm"; + reg = <0xc0000 0xac>; + clocks = <&gateclk 13>; + internal-mem = <&bm_bppi>; + status = "disabled"; + }; + + xor0: xor@f0900 { compatible = "marvell,orion-xor"; reg = <0xF0900 0x100 0xF0B00 0x100>; @@ -257,6 +196,35 @@ }; }; }; + + crypto_sram0: sa-sram0 { + compatible = "mmio-sram"; + reg = ; + clocks = <&gateclk 23>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>; + }; + + crypto_sram1: sa-sram1 { + compatible = "mmio-sram"; + reg = ; + clocks = <&gateclk 23>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; + }; + + bm_bppi: bm-bppi { + compatible = "mmio-sram"; + reg = ; + ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gateclk 13>; + no-memory-wc; + status = "disabled"; + }; }; clocks { @@ -269,6 +237,44 @@ }; }; +&i2c0 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11000 0x100>; +}; + +&i2c1 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11100 0x100>; +}; + +&mpic { + reg = <0x20a00 0x2d0>, <0x21070 0x58>; +}; + +&timer { + compatible = "marvell,armada-xp-timer"; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; +}; + +&watchdog { + compatible = "marvell,armada-xp-wdt"; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; +}; + +&cpurst { + reg = <0x20800 0x20>; +}; + +&usb0 { + clocks = <&gateclk 18>; +}; + +&usb1 { + clocks = <&gateclk 19>; +}; + &pinctrl { ge0_gmii_pins: ge0-gmii-pins { marvell,pins = @@ -309,6 +315,12 @@ marvell,function = "spi0"; }; + spi1_pins: spi1-pins { + marvell,pins = "mpp13", "mpp14", + "mpp16", "mpp17"; + marvell,function = "spi1"; + }; + uart2_pins: uart2-pins { marvell,pins = "mpp42", "mpp43"; marvell,function = "uart2"; @@ -319,3 +331,15 @@ marvell,function = "uart3"; }; }; + +&spi0 { + compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; +}; + +&spi1 { + compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; +}; -- cgit v1.2.3 From 7ceefcbaca0a5ee5bbf92e97423584d186e052fa Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Mon, 18 Feb 2019 10:30:54 +1300 Subject: arm: mvebu: x530: Enable watchdog in SPL and U-Boot Enable the hardware watchdog to guard against system lock ups when running in the SPL or U-Boot. Stop the watchdog just before booting so that the OS can re-enable it if needed. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- arch/arm/dts/armada-385-atl-x530-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/armada-385-atl-x530-u-boot.dtsi b/arch/arm/dts/armada-385-atl-x530-u-boot.dtsi index 7074a73537f..79b694cb84b 100644 --- a/arch/arm/dts/armada-385-atl-x530-u-boot.dtsi +++ b/arch/arm/dts/armada-385-atl-x530-u-boot.dtsi @@ -11,3 +11,7 @@ &uart0 { u-boot,dm-pre-reloc; }; + +&watchdog { + u-boot,dm-pre-reloc; +}; -- cgit v1.2.3 From d131ac48450c0373efa500cc800fa58ffab33baf Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 13 Mar 2019 20:47:01 +1300 Subject: ARM: kirkwood: rename KW_CPU_WIN_BASE to MVEBU_CPU_WIN_BASE This will allow the kirkwood platforms to use more common code with the other mvebu SoCs. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- arch/arm/mach-kirkwood/cpu.c | 2 +- arch/arm/mach-kirkwood/include/mach/soc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index d54de53f31d..1e733dc5fbc 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -62,7 +62,7 @@ unsigned int kw_winctrl_calcsize(unsigned int sizeval) int kw_config_adr_windows(void) { struct kwwin_registers *winregs = - (struct kwwin_registers *)KW_CPU_WIN_BASE; + (struct kwwin_registers *)MVEBU_CPU_WIN_BASE; /* Window 0: PCIE MEM address space */ writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE, diff --git a/arch/arm/mach-kirkwood/include/mach/soc.h b/arch/arm/mach-kirkwood/include/mach/soc.h index 227707ae4c9..1d7f2828cd3 100644 --- a/arch/arm/mach-kirkwood/include/mach/soc.h +++ b/arch/arm/mach-kirkwood/include/mach/soc.h @@ -31,7 +31,7 @@ #define KW_RTC_BASE (KW_REGISTER(0x10300)) #define KW_NANDF_BASE (KW_REGISTER(0x10418)) #define MVEBU_SPI_BASE (KW_REGISTER(0x10600)) -#define KW_CPU_WIN_BASE (KW_REGISTER(0x20000)) +#define MVEBU_CPU_WIN_BASE (KW_REGISTER(0x20000)) #define KW_CPU_REG_BASE (KW_REGISTER(0x20100)) #define MVEBU_TIMER_BASE (KW_REGISTER(0x20300)) #define KW_REG_PCIE_BASE (KW_REGISTER(0x40000)) -- cgit v1.2.3 From 35f1ee64749db4a1e6f1915446ccf39f4f8afbeb Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 13 Mar 2019 20:47:02 +1300 Subject: ARM: kirkwood: remove KW_DEFADR_PCI_IO_REMAP KW_DEFADR_PCI_IO_REMAP has the same value as KW_DEFADR_PCI_IO and is only used to set up a 1:1 mapping. Remove it and update the mapping to use KW_DEFADR_PCI_IO. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- arch/arm/mach-kirkwood/cpu.c | 2 +- arch/arm/mach-kirkwood/include/mach/cpu.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 1e733dc5fbc..95dd07f840c 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -76,7 +76,7 @@ int kw_config_adr_windows(void) writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl); writel(KW_DEFADR_PCI_IO, &winregs[1].base); - writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo); + writel(KW_DEFADR_PCI_IO, &winregs[1].remap_lo); writel(0x0, &winregs[1].remap_hi); /* Window 2: NAND Flash address space */ diff --git a/arch/arm/mach-kirkwood/include/mach/cpu.h b/arch/arm/mach-kirkwood/include/mach/cpu.h index 91d21518d85..c35cace844a 100644 --- a/arch/arm/mach-kirkwood/include/mach/cpu.h +++ b/arch/arm/mach-kirkwood/include/mach/cpu.h @@ -63,7 +63,6 @@ enum kwcpu_attrib { */ #define KW_DEFADR_PCI_MEM 0x90000000 #define KW_DEFADR_PCI_IO 0xC0000000 -#define KW_DEFADR_PCI_IO_REMAP 0xC0000000 #define KW_DEFADR_SASRAM 0xC8010000 #define KW_DEFADR_NANDF 0xD8000000 #define KW_DEFADR_SPIF 0xE8000000 -- cgit v1.2.3 From 8ef078b4be784e9668524d083eec7ba2292c1259 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 13 Mar 2019 20:47:03 +1300 Subject: ARM: kirkwood: switch to using mvebu mbus The mvebu mbus code already had most of the support required for kirkwood. The only difference is that unlike the other mvebu targets kirkwood doesn't have a bridge control block so the code related to managing that needs to be compiled out. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- arch/arm/mach-kirkwood/cpu.c | 33 ++++++++++++++++++++++++++++--- arch/arm/mach-kirkwood/include/mach/cpu.h | 11 +++++++++++ arch/arm/mach-mvebu/Makefile | 1 + arch/arm/mach-mvebu/mbus.c | 4 ++++ 4 files changed, 46 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 95dd07f840c..009b49287b7 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -110,6 +110,32 @@ int kw_config_adr_windows(void) return 0; } +static struct mbus_win windows[] = { + /* Window 0: PCIE MEM address space */ + { KW_DEFADR_PCI_MEM, 1024 * 1024 * 256, + KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM }, + + /* Window 1: PCIE IO address space */ + { KW_DEFADR_PCI_IO, 1024 * 64, + KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_IO }, + + /* Window 2: NAND Flash address space */ + { KW_DEFADR_NANDF, 1024 * 1024 * 128, + KWCPU_TARGET_MEMORY, KWCPU_ATTR_NANDFLASH }, + + /* Window 3: SPI Flash address space */ + { KW_DEFADR_SPIF, 1024 * 1024 * 128, + KWCPU_TARGET_MEMORY, KWCPU_ATTR_SPIFLASH }, + + /* Window 4: BOOT Memory address space */ + { KW_DEFADR_BOOTROM, 1024 * 1024 * 128, + KWCPU_TARGET_MEMORY, KWCPU_ATTR_BOOTROM }, + + /* Window 5: Security SRAM address space */ + { KW_DEFADR_SASRAM, 1024 * 64, + KWCPU_TARGET_SASRAM, KWCPU_ATTR_SASRAM }, +}; + /* * SYSRSTn Duration Counter Support * @@ -221,15 +247,13 @@ int arch_cpu_init(void) struct kwcpu_registers *cpureg = (struct kwcpu_registers *)KW_CPU_REG_BASE; - /* Linux expects` the internal registers to be at 0xf1000000 */ + /* Linux expects the internal registers to be at 0xf1000000 */ writel(KW_REGS_PHY_BASE, KW_OFFSET_REG); /* Enable and invalidate L2 cache in write through mode */ writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg); invalidate_l2_cache(); - kw_config_adr_windows(); - #ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* * Configures the I/O voltage of the pads connected to Egigabit @@ -296,6 +320,9 @@ int arch_misc_init(void) temp = get_cr(); set_cr(temp & ~CR_V); + /* Configure mbus windows */ + mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); + /* checks and execute resset to factory event */ kw_sysrst_check(); diff --git a/arch/arm/mach-kirkwood/include/mach/cpu.h b/arch/arm/mach-kirkwood/include/mach/cpu.h index c35cace844a..3d6b15568a8 100644 --- a/arch/arm/mach-kirkwood/include/mach/cpu.h +++ b/arch/arm/mach-kirkwood/include/mach/cpu.h @@ -68,6 +68,13 @@ enum kwcpu_attrib { #define KW_DEFADR_SPIF 0xE8000000 #define KW_DEFADR_BOOTROM 0xF8000000 +struct mbus_win { + u32 base; + u32 size; + u8 target; + u8 attr; +}; + /* * read feroceon/sheeva core extra feature register * using co-proc instruction @@ -134,6 +141,9 @@ struct kwgpio_registers { u32 irq_level; }; +/* Needed for dynamic (board-specific) mbus configuration */ +extern struct mvebu_mbus_state mbus_state; + /* * functions */ @@ -141,6 +151,7 @@ unsigned int mvebu_sdram_bar(enum memory_bank bank); unsigned int mvebu_sdram_bs(enum memory_bank bank); void mvebu_sdram_size_adjust(enum memory_bank bank); int kw_config_adr_windows(void); +int mvebu_mbus_probe(struct mbus_win windows[], int count); void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, unsigned int gpp0_oe, unsigned int gpp1_oe); int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index ee2eca91348..c0274a6f09a 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -14,6 +14,7 @@ ifdef CONFIG_KIRKWOOD obj-y = dram.o obj-y += gpio.o +obj-y += mbus.o obj-y += timer.o else # CONFIG_KIRKWOOD diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index df4c5cb2d71..7be67b7d499 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -405,6 +405,7 @@ int mvebu_mbus_del_window(phys_addr_t base, size_t size) return 0; } +#ifndef CONFIG_KIRKWOOD static void mvebu_mbus_get_lowest_base(struct mvebu_mbus_state *mbus, phys_addr_t *base) { @@ -451,6 +452,7 @@ static void mvebu_config_mbus_bridge(struct mvebu_mbus_state *mbus) val = (size / (64 << 10)) - 1; writel((val << 16) | 0x1, MBUS_BRIDGE_WIN_CTRL_REG); } +#endif int mbus_dt_setup_win(struct mvebu_mbus_state *mbus, u32 base, u32 size, u8 target, u8 attr) @@ -471,12 +473,14 @@ int mbus_dt_setup_win(struct mvebu_mbus_state *mbus, return -ENOMEM; } +#ifndef CONFIG_KIRKWOOD /* * Re-configure the mbus bridge registers each time this function * is called. Since it may get called from the board code in * later boot stages as well. */ mvebu_config_mbus_bridge(mbus); +#endif return 0; } -- cgit v1.2.3 From fa8d96f625fadde73acd8243ad3c847c614f9225 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 13 Mar 2019 20:47:04 +1300 Subject: ARM: kirkwood: remove kw_config_adr_windows Now that kirkwood is using the mvebu mbus this function is no longer needed. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- arch/arm/mach-kirkwood/cpu.c | 64 ------------------------------- arch/arm/mach-kirkwood/include/mach/cpu.h | 1 - 2 files changed, 65 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 009b49287b7..8b21db10715 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -46,70 +46,6 @@ unsigned int kw_winctrl_calcsize(unsigned int sizeval) return (0x0000ffff & j); } -/* - * kw_config_adr_windows - Configure address Windows - * - * There are 8 address windows supported by Kirkwood Soc to addess different - * devices. Each window can be configured for size, BAR and remap addr - * Below configuration is standard for most of the cases - * - * If remap function not used, remap_lo must be set as base - * - * Reference Documentation: - * Mbus-L to Mbus Bridge Registers Configuration. - * (Sec 25.1 and 25.3 of Datasheet) - */ -int kw_config_adr_windows(void) -{ - struct kwwin_registers *winregs = - (struct kwwin_registers *)MVEBU_CPU_WIN_BASE; - - /* Window 0: PCIE MEM address space */ - writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE, - KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl); - - writel(KW_DEFADR_PCI_MEM, &winregs[0].base); - writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo); - writel(0x0, &winregs[0].remap_hi); - - /* Window 1: PCIE IO address space */ - writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE, - KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl); - writel(KW_DEFADR_PCI_IO, &winregs[1].base); - writel(KW_DEFADR_PCI_IO, &winregs[1].remap_lo); - writel(0x0, &winregs[1].remap_hi); - - /* Window 2: NAND Flash address space */ - writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY, - KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl); - writel(KW_DEFADR_NANDF, &winregs[2].base); - writel(KW_DEFADR_NANDF, &winregs[2].remap_lo); - writel(0x0, &winregs[2].remap_hi); - - /* Window 3: SPI Flash address space */ - writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY, - KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl); - writel(KW_DEFADR_SPIF, &winregs[3].base); - writel(KW_DEFADR_SPIF, &winregs[3].remap_lo); - writel(0x0, &winregs[3].remap_hi); - - /* Window 4: BOOT Memory address space */ - writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY, - KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl); - writel(KW_DEFADR_BOOTROM, &winregs[4].base); - - /* Window 5: Security SRAM address space */ - writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM, - KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl); - writel(KW_DEFADR_SASRAM, &winregs[5].base); - - /* Window 6-7: Disabled */ - writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl); - writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl); - - return 0; -} - static struct mbus_win windows[] = { /* Window 0: PCIE MEM address space */ { KW_DEFADR_PCI_MEM, 1024 * 1024 * 256, diff --git a/arch/arm/mach-kirkwood/include/mach/cpu.h b/arch/arm/mach-kirkwood/include/mach/cpu.h index 3d6b15568a8..ea42182cf9c 100644 --- a/arch/arm/mach-kirkwood/include/mach/cpu.h +++ b/arch/arm/mach-kirkwood/include/mach/cpu.h @@ -150,7 +150,6 @@ extern struct mvebu_mbus_state mbus_state; unsigned int mvebu_sdram_bar(enum memory_bank bank); unsigned int mvebu_sdram_bs(enum memory_bank bank); void mvebu_sdram_size_adjust(enum memory_bank bank); -int kw_config_adr_windows(void); int mvebu_mbus_probe(struct mbus_win windows[], int count); void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, unsigned int gpp0_oe, unsigned int gpp1_oe); -- cgit v1.2.3 From 4b11e5f6b3cbe86e214ee9cee2985e6efb2273fd Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Sun, 24 Mar 2019 13:27:43 +0200 Subject: ARM: mvebu: define board_ahci_enable() for A38x This allows the ahci_mvebu driver to do A38x platform specific configuration at initialization. Signed-off-by: Baruch Siach Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- arch/arm/mach-mvebu/cpu.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 919d05c88c7..5d3f553b5dd 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -501,7 +501,6 @@ int board_mmc_init(bd_t *bis) } #endif -#ifdef CONFIG_SCSI_AHCI_PLAT #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0 #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4 @@ -545,11 +544,19 @@ static void ahci_mvebu_regret_option(void __iomem *base) writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA); } -void scsi_init(void) +int board_ahci_enable(void) { - printf("MVEBU SATA INIT\n"); ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE); ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE); + + return 0; +} + +#ifdef CONFIG_SCSI_AHCI_PLAT +void scsi_init(void) +{ + printf("MVEBU SATA INIT\n"); + board_ahci_enable(); ahci_init((void __iomem *)MVEBU_SATA0_BASE); } #endif -- cgit v1.2.3 From 0a590243d17c197fafa52be96db4cfaa7676ce69 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 8 Apr 2019 14:51:49 +0200 Subject: arm: mvebu: AXP: Enhance PCIe port capability configuration This patch enables the PCIe port specific link capabilities configuration for Armada XP. The weak function board_sat_r_get() was used to return a common flag for PCIe Gen1 vs Gen2 capability for all PCIe ports. This is now changed with this patch to return a bit per PCIe port (4 bits in this case, bit 0 for PCIe port 0, etc). The theadorable board uses this new feature to configure PCIe port 0 as Gen1 and all other PCIe ports as Gen2 capable. All other AXP boards using this function are not changed in the configuration and still configure all ports as PCIe Gen2. This patch also removes the parameter "pex_mode" from board_serdes_cfg_get() as this parameter was not used in any of the implementations. Signed-off-by: Stefan Roese Cc: Phil Sutter --- arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c index 569840ff471..c8c92988645 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c @@ -35,7 +35,7 @@ int pex_local_dev_num_set(u32 pex_if, u32 dev_num); #define ETM_MODULE_DETECT 2 #define PEX_MODE_GET(satr) ((satr & 0x6) >> 1) -#define PEX_CAPABILITY_GET(satr) (satr & 1) +#define PEX_CAPABILITY_GET(satr, port) ((satr >> port) & 1) #define MV_PEX_UNIT_TO_IF(pex_unit) ((pex_unit < 3) ? (pex_unit * 4) : 9) /* Static parametes */ @@ -176,7 +176,7 @@ u8 board_cpu_freq_get(void) return ((sar_msb & 0x100000) >> 17) | ((sar & 0xe00000) >> 21); } -__weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) +__weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(void) { u32 board_id; u32 serdes_cfg_val = 0; /* default */ @@ -352,7 +352,7 @@ int serdes_phy_config(void) DEBUG_WR_REG(CPU_AVS_CONTROL2_REG, cpu_avs); } - info = board_serdes_cfg_get(PEX_MODE_GET(satr11)); + info = board_serdes_cfg_get(); if (info == NULL) { DEBUG_INIT_S("Hight speed PHY Error #1\n"); @@ -675,7 +675,7 @@ int serdes_phy_config(void) tmp |= (0x1 << 4); if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) tmp |= (0x4 << 4); - if (0 == PEX_CAPABILITY_GET(satr11)) + if (0 == PEX_CAPABILITY_GET(satr11, pex_unit)) tmp |= 0x1; else tmp |= 0x2; -- cgit v1.2.3 From 237b629e4cd8fd8ffa9664a1b71b7eda1d2f2179 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 11 Apr 2019 08:58:32 +0200 Subject: arm: mvebu: Fix Kconfig dependency warnings We now have MEVBU boards without SPL support (e.g. db-xc3-24g4xg). Because of this, a new compile time warning from Kconfig is show: WARNING: unmet direct dependencies detected for SPL_OF_CONTROL Depends on [n]: SUPPORT_OF_CONTROL [=y] && SPL [=n] && OF_CONTROL [=y] Selected by [y]: - ARMADA_32BIT [=y] && ARM [=y] && ARCH_MVEBU [=y] WARNING: unmet direct dependencies detected for SPL_DM Depends on [n]: DM [=y] && SPL [=n] Selected by [y]: - ARMADA_32BIT [=y] && ARM [=y] && ARCH_MVEBU [=y] ... This patch fixes this issue and removes these warnings. Signed-off-by: Stefan Roese Cc: Chris Packham Reviewed-by: Chris Packham --- arch/arm/mach-mvebu/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 7dda04e0e34..a46f13b1b7e 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -9,10 +9,10 @@ config ARMADA_32BIT select ARCH_MISC_INIT select BOARD_EARLY_INIT_F select CPU_V7A - select SPL_DM - select SPL_DM_SEQ_ALIAS - select SPL_OF_CONTROL - select SPL_SIMPLE_BUS + select SPL_DM if SPL + select SPL_DM_SEQ_ALIAS if SPL + select SPL_OF_CONTROL if SPL + select SPL_SIMPLE_BUS if SPL select SUPPORT_SPL config ARMADA_64BIT -- cgit v1.2.3 From 0d0df46ee7323506df2e38738c52d68699c2abca Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 11 Apr 2019 22:22:50 +1200 Subject: arm: mvebu: Add Marvell's integrated CPUs Marvell's switch chips with integrated CPUs (collectively referred to as MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks (e.g. xor) are located at different addresses and DFX server exists as a separate target on the MBUS (on Armada-38x it's just part of the core complex registers). Signed-off-by: Chris Packham Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- arch/arm/mach-mvebu/Kconfig | 18 +++++++++++++++++- arch/arm/mach-mvebu/Makefile | 1 + arch/arm/mach-mvebu/cpu.c | 31 +++++++++++++++++++++++++++++-- arch/arm/mach-mvebu/include/mach/config.h | 2 +- arch/arm/mach-mvebu/include/mach/cpu.h | 3 +++ arch/arm/mach-mvebu/include/mach/soc.h | 20 ++++++++++++++++++++ arch/arm/mach-mvebu/mbus.c | 5 +++++ 7 files changed, 76 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index a46f13b1b7e..bb4ca56a585 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -46,7 +46,7 @@ config ARMADA_8K # Armada PLL frequency (used for NAND clock generation) config SYS_MVEBU_PLL_CLOCK int - default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K + default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K || ARMADA_MSYS default "1000000000" if ARMADA_38X || ARMADA_375 # Armada XP/38x SoC types... @@ -63,6 +63,22 @@ config MV78460 bool select ARMADA_XP +config ARMADA_MSYS + bool + select ARMADA_32BIT + +config 98DX4251 + bool + select ARMADA_MSYS + +config 98DX3336 + bool + select ARMADA_MSYS + +config 98DX3236 + bool + select ARMADA_MSYS + config 88F6820 bool select ARMADA_38X diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index c0274a6f09a..02d3ce27ee7 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -25,6 +25,7 @@ ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o +obj-$(CONFIG_ARMADA_MSYS) += ../../../drivers/ddr/marvell/axp/xor.o obj-$(CONFIG_MVEBU_EFUSE) += efuse.o extra-y += kwbimage.cfg diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 5d3f553b5dd..98684628670 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -23,6 +23,11 @@ static struct mbus_win windows[] = { /* NOR */ { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE, CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM }, + +#ifdef CONFIG_ARMADA_MSYS + /* DFX */ + { MBUS_DFX_BASE, MBUS_DFX_SIZE, CPU_TARGET_DFX, 0 }, +#endif }; void lowlevel_init(void) @@ -121,6 +126,14 @@ static const struct sar_freq_modes sar_freq_tab[] = { { 0x13, 0x0, 2000, 1000, 933 }, { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ }; +#elif defined(CONFIG_ARMADA_MSYS) +static const struct sar_freq_modes sar_freq_tab[] = { + { 0x0, 0x0, 400, 400, 400 }, + { 0x2, 0x0, 667, 333, 667 }, + { 0x3, 0x0, 800, 400, 800 }, + { 0x5, 0x0, 800, 400, 800 }, + { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ +}; #else /* SAR frequency values for Armada XP */ static const struct sar_freq_modes sar_freq_tab[] = { @@ -144,7 +157,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq) u32 freq; int i; -#if defined(CONFIG_ARMADA_375) +#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS) val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */ #else val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ @@ -160,7 +173,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq) #endif for (i = 0; sar_freq_tab[i].val != 0xff; i++) { if (sar_freq_tab[i].val == freq) { -#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) +#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS) *sar_freq = sar_freq_tab[i]; return; #else @@ -270,6 +283,20 @@ int print_cpuinfo(void) } } + if (mvebu_soc_family() == MVEBU_SOC_MSYS) { + switch (revid) { + case 3: + puts("A0"); + break; + case 4: + puts("A1"); + break; + default: + printf("?? (%x)", revid); + break; + } + } + get_sar_freq(&sar_freq); printf(" at %d MHz\n", sar_freq.p_clk); diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 71c4f70efc9..bbcfcfd1419 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -17,7 +17,7 @@ #include #if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_375) \ - || defined(CONFIG_ARMADA_38X) + || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS) /* * Set this for the common xor register definitions needed in dram.c * for A38x as well here. diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 9e23043a485..b9153d86c66 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -34,6 +34,7 @@ enum cpu_target { CPU_TARGET_PCIE02 = 0x4, CPU_TARGET_ETH01 = 0x7, CPU_TARGET_PCIE13 = 0x8, + CPU_TARGET_DFX = 0x8, CPU_TARGET_SASRAM = 0x9, CPU_TARGET_SATA01 = 0xa, /* A38X */ CPU_TARGET_NAND = 0xd, @@ -79,6 +80,8 @@ enum { #define MBUS_PCI_IO_SIZE (64 << 10) #define MBUS_SPI_BASE 0xF4000000 #define MBUS_SPI_SIZE (8 << 20) +#define MBUS_DFX_BASE 0xF6000000 +#define MBUS_DFX_SIZE (1 << 20) #define MBUS_BOOTROM_BASE 0xF8000000 #define MBUS_BOOTROM_SIZE (8 << 20) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 01577f469b0..2d88c410b88 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -76,7 +76,11 @@ #define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000)) #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000)) #define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000)) +#ifdef CONFIG_ARMADA_MSYS +#define MVEBU_DFX_BASE (MBUS_DFX_BASE) +#else #define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000)) +#endif #define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200)) #define MBUS_ERR_PROP_EN (1 << 8) @@ -149,6 +153,22 @@ #define BOOT_FROM_SPI 0x32 #define BOOT_FROM_MMC 0x30 #define BOOT_FROM_MMC_ALT 0x31 +#elif defined(CONFIG_ARMADA_MSYS) +/* SAR values for MSYS */ +#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200) +#define CONFIG_SAR2_REG (MBUS_DFX_BASE + 0xf8204) + +#define SAR_CPU_FREQ_OFFS 18 +#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) +#define SAR_BOOT_DEVICE_OFFS 11 +#define SAR_BOOT_DEVICE_MASK (0x7 << SAR_BOOT_DEVICE_OFFS) + +#define BOOT_DEV_SEL_OFFS 11 +#define BOOT_DEV_SEL_MASK (0x7 << BOOT_DEV_SEL_OFFS) + +#define BOOT_FROM_NAND 0x1 +#define BOOT_FROM_UART 0x2 +#define BOOT_FROM_SPI 0x3 #else /* SAR values for Armada XP */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index 7be67b7d499..c68e93ba100 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -344,6 +344,11 @@ static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus) } } mbus_dram_info.num_cs = cs; + +#if defined(CONFIG_ARMADA_MSYS) + /* Disable MBUS Err Prop - in order to avoid data aborts */ + clrbits_le32(mbus->mbuswins_base + 0x200, BIT(8)); +#endif } static const struct mvebu_mbus_soc_data -- cgit v1.2.3 From 689f9cf6aa9edff89c4d4d3b843f500fc5582300 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 11 Apr 2019 22:22:51 +1200 Subject: arm: mvebu: NAND clock support for MSYS devices One difference with the integrated CPUs is that they use a different clock control block to the Armada devices. Update mvebu_get_nand_clock() accordingly. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- arch/arm/mach-mvebu/cpu.c | 2 ++ arch/arm/mach-mvebu/include/mach/soc.h | 11 +++++++++++ 2 files changed, 13 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 98684628670..c5b3df46aab 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -499,6 +499,8 @@ u32 mvebu_get_nand_clock(void) if (mvebu_soc_family() == MVEBU_SOC_A38X) reg = MVEBU_DFX_DIV_CLK_CTRL(1); + else if (mvebu_soc_family() == MVEBU_SOC_MSYS) + reg = MVEBU_DFX_DIV_CLK_CTRL(8); else reg = MVEBU_CORE_DIV_CLK_CTRL(1); diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 2d88c410b88..f666ee24243 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -100,9 +100,20 @@ #define SPI_PUP_EN BIT(5) #define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8)) +#ifdef CONFIG_ARMADA_MSYS +#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0xf8000 + 0x250 + ((i) * 0x4)) +#define NAND_ECC_DIVCKL_RATIO_OFFS 6 +#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS) +#else #define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4)) +#endif +#ifdef CONFIG_ARMADA_MSYS +#define NAND_ECC_DIVCKL_RATIO_OFFS 6 +#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS) +#else #define NAND_ECC_DIVCKL_RATIO_OFFS 8 #define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS) +#endif #define SDRAM_MAX_CS 4 #define SDRAM_ADDR_MASK 0xFF000000 -- cgit v1.2.3 From 4db944ab44a7bc8b495eece6afb124c632b02ef5 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 11 Apr 2019 22:22:53 +1200 Subject: arm: mvebu: Add DB-XC3-24G4XG board The DB-XC3-24G4XG is a switch development board from Marvell. It can either use and external CPU card such as the db-88f6820-amc or the internal CPU that is integrated into the switch. Add support for running U-Boot on the internal CPU and enable the USB, SPI and NAND peripherals. For now this needs the bin_hdr from the Marvell U-Boot for this board. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/armada-xp-98dx3236.dtsi | 343 +++++++++++++++++++++++ arch/arm/dts/armada-xp-98dx3336.dtsi | 39 +++ arch/arm/dts/armada-xp-98dx4251.dtsi | 54 ++++ arch/arm/dts/armada-xp-db-xc3-24g4xg-u-boot.dtsi | 24 ++ arch/arm/dts/armada-xp-db-xc3-24g4xg.dts | 110 ++++++++ arch/arm/mach-mvebu/Kconfig | 8 + 7 files changed, 580 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/armada-xp-98dx3236.dtsi create mode 100644 arch/arm/dts/armada-xp-98dx3336.dtsi create mode 100644 arch/arm/dts/armada-xp-98dx4251.dtsi create mode 100644 arch/arm/dts/armada-xp-db-xc3-24g4xg-u-boot.dtsi create mode 100644 arch/arm/dts/armada-xp-db-xc3-24g4xg.dts (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 86a01c2c702..524c1ee0dbd 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -151,7 +151,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-xp-theadorable.dtb \ armada-38x-controlcenterdc.dtb \ armada-385-atl-x530.dtb \ - armada-385-atl-x530DP.dtb + armada-385-atl-x530DP.dtb \ + armada-xp-db-xc3-24g4xg.dtb dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \ uniphier-ld11-global.dtb \ diff --git a/arch/arm/dts/armada-xp-98dx3236.dtsi b/arch/arm/dts/armada-xp-98dx3236.dtsi new file mode 100644 index 00000000000..5df1d1848db --- /dev/null +++ b/arch/arm/dts/armada-xp-98dx3236.dtsi @@ -0,0 +1,343 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell 98dx3236 family SoC + * + * Copyright (C) 2016 Allied Telesis Labs + * + * Contains definitions specific to the 98dx3236 SoC that are not + * common to all Armada XP SoCs. + */ + +#include "armada-370-xp.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + + model = "Marvell 98DX3236 SoC"; + compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,98dx3236-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <0>; + clocks = <&cpuclk 0>; + clock-latency = <1000000>; + }; + }; + + soc { + compatible = "marvell,armadaxp-mbus", "simple-bus"; + + ranges = ; + + bootrom { + compatible = "marvell,bootrom"; + reg = ; + }; + + /* + * 98DX3236 has 1 x1 PCIe unit Gen2.0 + */ + pciec: pcie@82000000 { + compatible = "marvell,armada-xp-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; + + pcie1: pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &mpic 58>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 5>; + status = "disabled"; + }; + }; + + internal-regs { + sdramc: sdramc@1400 { + compatible = "marvell,armada-xp-sdram-controller"; + reg = <0x1400 0x500>; + }; + + L2: l2-cache@8000 { + compatible = "marvell,aurora-system-cache"; + reg = <0x08000 0x1000>; + cache-id-part = <0x100>; + cache-level = <2>; + cache-unified; + wt-override; + }; + + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; + }; + + /* does not exist */ + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; + reg = <0x18140 0x40>; + status = "disabled"; + }; + + gpio2: gpio@18180 { /* rework some properties */ + compatible = "marvell,orion-gpio"; + reg = <0x18180 0x40>; + ngpios = <1>; /* only gpio #32 */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>; + }; + + systemc: system-controller@18200 { + compatible = "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x500>; + }; + + gateclk: clock-gating-control@18220 { + compatible = "marvell,mv98dx3236-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; + }; + + cpuclk: clock-complex@18700 { + #clock-cells = <1>; + compatible = "marvell,mv98dx3236-cpu-clock"; + reg = <0x18700 0x24>, <0x1c054 0x10>; + clocks = <&coreclk 1>; + }; + + corediv-clock@18740 { + status = "disabled"; + }; + + cpu-config@21000 { + compatible = "marvell,armada-xp-cpu-config"; + reg = <0x21000 0x8>; + }; + + ethernet@70000 { + compatible = "marvell,armada-xp-neta"; + }; + + ethernet@74000 { + compatible = "marvell,armada-xp-neta"; + }; + + xor1: xor@f0800 { + compatible = "marvell,orion-xor"; + reg = <0xf0800 0x100 + 0xf0a00 0x100>; + clocks = <&gateclk 22>; + status = "okay"; + + xor10 { + interrupts = <51>; + dmacap,memcpy; + dmacap,xor; + }; + xor11 { + interrupts = <52>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + + nand_controller: nand@d0000 { + clocks = <&dfx_coredivclk 0>; + }; + + xor0: xor@f0900 { + compatible = "marvell,orion-xor"; + reg = <0xF0900 0x100 + 0xF0B00 0x100>; + clocks = <&gateclk 28>; + status = "okay"; + + xor00 { + interrupts = <94>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <95>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; + }; + }; + + dfx: dfx-server@ac000000 { + compatible = "marvell,dfx-server", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; + reg = ; + + thermal: thermal@f8078 { + compatible = "marvell,armada380-thermal"; + reg = <0xf8078 0x4>, <0xf8074 0x4>; + status = "okay"; + }; + + coreclk: mvebu-sar@f8204 { + compatible = "marvell,mv98dx3236-core-clock"; + reg = <0xf8204 0x4>; + #clock-cells = <1>; + }; + + dfx_coredivclk: corediv-clock@f8268 { + compatible = "marvell,mv98dx3236-corediv-clock"; + reg = <0xf8268 0xc>; + #clock-cells = <1>; + clocks = <&mainpll>; + clock-output-names = "nand"; + }; + }; + + switch: switch@a8000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>; + + pp0: packet-processor@0 { + compatible = "marvell,prestera-98dx3236", "marvell,prestera"; + reg = <0 0x4000000>; + interrupts = <33>, <34>, <35>; + dfx = <&dfx>; + }; + }; + }; + + clocks { + /* 25 MHz reference crystal */ + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + }; +}; + +&i2c0 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11000 0x100>; +}; + +&i2c1 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11100 0x100>; +}; + +&mpic { + reg = <0x20a00 0x2d0>, <0x21070 0x58>; +}; + +&rtc { + status = "disabled"; +}; + +&timer { + compatible = "marvell,armada-xp-timer"; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; +}; + +&watchdog { + compatible = "marvell,armada-xp-wdt"; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; +}; + +&cpurst { + reg = <0x20800 0x20>; +}; + +&usb0 { + clocks = <&gateclk 18>; +}; + +&usb1 { + clocks = <&gateclk 19>; +}; + +&pinctrl { + compatible = "marvell,98dx3236-pinctrl"; + + nand_pins: nand-pins { + marvell,pins = "mpp20", "mpp21", "mpp22", + "mpp23", "mpp24", "mpp25", + "mpp26", "mpp27", "mpp28", + "mpp29", "mpp30"; + marvell,function = "dev"; + }; + + nand_rb: nand-rb { + marvell,pins = "mpp19"; + marvell,function = "nand"; + }; + + spi0_pins: spi0-pins { + marvell,pins = "mpp0", "mpp1", + "mpp2", "mpp3"; + marvell,function = "spi0"; + }; +}; + +&spi0 { + compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; +}; + +&sdio { + status = "disabled"; +}; diff --git a/arch/arm/dts/armada-xp-98dx3336.dtsi b/arch/arm/dts/armada-xp-98dx3336.dtsi new file mode 100644 index 00000000000..1d9d8a8ea60 --- /dev/null +++ b/arch/arm/dts/armada-xp-98dx3336.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell 98dx3336 family SoC + * + * Copyright (C) 2016 Allied Telesis Labs + * + * Contains definitions specific to the 98dx3236 SoC that are not + * common to all Armada XP SoCs. + */ + +#include "armada-xp-98dx3236.dtsi" + +/ { + model = "Marvell 98DX3336 SoC"; + compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; + + cpus { + cpu@1 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <1>; + clocks = <&cpuclk 1>; + clock-latency = <1000000>; + }; + }; + + soc { + internal-regs { + resume@20980 { + compatible = "marvell,98dx3336-resume-ctrl"; + reg = <0x20980 0x10>; + }; + }; + }; +}; + +&pp0 { + compatible = "marvell,prestera-98dx3336", "marvell,prestera"; +}; diff --git a/arch/arm/dts/armada-xp-98dx4251.dtsi b/arch/arm/dts/armada-xp-98dx4251.dtsi new file mode 100644 index 00000000000..48ffdc72bfc --- /dev/null +++ b/arch/arm/dts/armada-xp-98dx4251.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Include file for Marvell 98dx4521 family SoC + * + * Copyright (C) 2016 Allied Telesis Labs + * + * Contains definitions specific to the 98dx4521 SoC that are not + * common to all Armada XP SoCs. + */ + +#include "armada-xp-98dx3236.dtsi" + +/ { + model = "Marvell 98DX4251 SoC"; + compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; + + cpus { + cpu@1 { + device_type = "cpu"; + compatible = "marvell,sheeva-v7"; + reg = <1>; + clocks = <&cpuclk 1>; + clock-latency = <1000000>; + }; + }; + + soc { + internal-regs { + resume@20980 { + compatible = "marvell,98dx3336-resume-ctrl"; + reg = <0x20980 0x10>; + }; + }; + }; +}; + +&sdio { + status = "okay"; +}; + +&pinctrl { + compatible = "marvell,98dx4251-pinctrl"; + + sdio_pins: sdio-pins { + marvell,pins = "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10"; + marvell,function = "sd0"; + }; +}; + +&pp0 { + compatible = "marvell,prestera-98dx4251", "marvell,prestera"; + interrupts = <33>, <34>, <35>, <36>; +}; diff --git a/arch/arm/dts/armada-xp-db-xc3-24g4xg-u-boot.dtsi b/arch/arm/dts/armada-xp-db-xc3-24g4xg-u-boot.dtsi new file mode 100644 index 00000000000..90cad85506d --- /dev/null +++ b/arch/arm/dts/armada-xp-db-xc3-24g4xg-u-boot.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&nand_controller { + compatible="marvell,mvebu-pxa3xx-nand"; + status = "okay"; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; +}; + +&spi0 { + u-boot,dm-pre-reloc; + + spi-flash@0 { + u-boot,dm-pre-reloc; + }; +}; diff --git a/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts new file mode 100644 index 00000000000..d4b52881e6f --- /dev/null +++ b/arch/arm/dts/armada-xp-db-xc3-24g4xg.dts @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for DB-XC3-24G4XG board + * + * Copyright (C) 2016 Allied Telesis Labs + * + * Based on armada-xp-db.dts + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include "armada-xp-98dx3336.dtsi" +#include "armada-xp-db-xc3-24g4xg-u-boot.dtsi" + +/ { + model = "DB-XC3-24G4XG"; + compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + aliases { + spi0 = &spi0; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x40000000>; /* 1 GB */ + }; +}; + +&L2 { + arm,parity-enable; + marvell,ecc-enable; +}; + +&devbus_bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x00100000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x00100000 0x00040000>; + label = "u-boot-env"; + }; + partition@unused { + reg = <0x00140000 0x00ec0000>; + label = "unused"; + }; + + }; +}; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index bb4ca56a585..f5fd60d7845 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -152,6 +152,10 @@ config TARGET_X530 bool "Support Allied Telesis x530" select 88F6820 +config TARGET_DB_XC3_24G4XG + bool "Support DB-XC3-24G4XG" + select 98DX3336 + endchoice config SYS_BOARD @@ -170,6 +174,7 @@ config SYS_BOARD default "theadorable" if TARGET_THEADORABLE default "a38x" if TARGET_CONTROLCENTERDC default "x530" if TARGET_X530 + default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG config SYS_CONFIG_NAME default "clearfog" if TARGET_CLEARFOG @@ -187,6 +192,7 @@ config SYS_CONFIG_NAME default "turris_mox" if TARGET_TURRIS_MOX default "controlcenterdc" if TARGET_CONTROLCENTERDC default "x530" if TARGET_X530 + default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG config SYS_VENDOR default "Marvell" if TARGET_DB_MV784MP_GP @@ -195,6 +201,8 @@ config SYS_VENDOR default "Marvell" if TARGET_DB_88F6820_GP default "Marvell" if TARGET_DB_88F6820_AMC default "Marvell" if TARGET_MVEBU_ARMADA_8K + default "Marvell" if TARGET_DB_XC3_24G4XG + default "Marvell" if TARGET_MVEBU_DB_88F7040 default "solidrun" if TARGET_CLEARFOG default "kobol" if TARGET_HELIOS4 default "Synology" if TARGET_DS414 -- cgit v1.2.3 From 93b3e812122a1a52ca00cbe6f6f71324c8127a85 Mon Sep 17 00:00:00 2001 From: Leigh Brown Date: Tue, 19 Mar 2019 14:50:09 +0000 Subject: ARM: kirkwood: remove obsolete call to icache_enable Commit 93b283d49f93 ("ARM: CPU: arm926ejs: Consolidate cache routines to common file") changed cache setup for Kirkwood such that icache_enable() is now called from enable_caches() which is called from initr_caches() which is in the list of functions in init_sequence_r[] prior to arch_misc_init(). This means the call to icache_enable() in arch_misc_init() is no longer required, so remove it. Signed-off-by: Leigh Brown Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- arch/arm/mach-kirkwood/cpu.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 8b21db10715..8f8e3003854 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -251,7 +251,6 @@ int arch_misc_init(void) temp |= (1 << 22); writefr_extra_feature_reg(temp); - icache_enable(); /* Change reset vector to address 0x0 */ temp = get_cr(); set_cr(temp & ~CR_V); -- cgit v1.2.3 From 205c75e88ce44636bb1958cb50eda24797423909 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 12 Apr 2019 08:47:04 +1200 Subject: ARM: mvebu: rename armada-385-amc.dts to armada-385-db-88f6820-amc.dts This board was added to u-boot first but the Linux maintainers requested a more descriptive name. Rename the file to match the Linux usage and update the board defconfig. Signed-off-by: Chris Packham Signed-off-by: Stefan Roese --- arch/arm/dts/Makefile | 2 +- arch/arm/dts/armada-385-amc.dts | 166 ----------------------------- arch/arm/dts/armada-385-db-88f6820-amc.dts | 166 +++++++++++++++++++++++++++++ 3 files changed, 167 insertions(+), 167 deletions(-) delete mode 100644 arch/arm/dts/armada-385-amc.dts create mode 100644 arch/arm/dts/armada-385-db-88f6820-amc.dts (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 524c1ee0dbd..0bed99b2e2e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -138,7 +138,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-388-clearfog.dtb \ armada-388-gp.dtb \ armada-388-helios4.dtb \ - armada-385-amc.dtb \ + armada-385-db-88f6820-amc.dtb \ armada-385-turris-omnia.dtb \ armada-7040-db.dtb \ armada-7040-db-nand.dtb \ diff --git a/arch/arm/dts/armada-385-amc.dts b/arch/arm/dts/armada-385-amc.dts deleted file mode 100644 index c9ccbb57fff..00000000000 --- a/arch/arm/dts/armada-385-amc.dts +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Device Tree file for Marvell Armada 385 development board - * (DB-88F6820-AMC) - * - * Copyright (C) 2014 Marvell - * - * Gregory CLEMENT - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "armada-385.dtsi" -#include - -/ { - model = "Marvell Armada 385 AMC"; - compatible = "marvell,a385-amc", "marvell,armada385", "marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - ethernet0 = ð0; - ethernet1 = ð2; - i2c0 = &i2c0; - spi1 = &spi1; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2 GB */ - }; - - soc { - ranges = ; - - internal-regs { - i2c@11000 { - clock-frequency = <100000>; - u-boot,i2c-slave-addr = <0x0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - }; - - serial@12000 { - /* - * Exported on the micro USB connector CON16 - * through an FTDI - */ - - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; - u-boot,dm-pre-reloc; - }; - - ethernet@34000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "sgmii"; - }; - - usb@58000 { - status = "okay"; - }; - - ethernet@70000 { - pinctrl-names = "default"; - /* - * The Reference Clock 0 is used to provide a - * clock to the PHY - */ - pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; - - - mdio@72004 { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - - phy1: ethernet-phy@0 { - reg = <0>; - }; - }; - - flash@d0000 { - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - }; - }; - - pcie { - status = "okay"; - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - }; - }; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - status = "okay"; - u-boot,dm-pre-reloc; - - spi-flash@0 { - u-boot,dm-pre-reloc; - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor", "spi-flash"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - m25p,fast-read; - }; -}; - -&refclk { - clock-frequency = <20000000>; -}; diff --git a/arch/arm/dts/armada-385-db-88f6820-amc.dts b/arch/arm/dts/armada-385-db-88f6820-amc.dts new file mode 100644 index 00000000000..c9ccbb57fff --- /dev/null +++ b/arch/arm/dts/armada-385-db-88f6820-amc.dts @@ -0,0 +1,166 @@ +/* + * Device Tree file for Marvell Armada 385 development board + * (DB-88F6820-AMC) + * + * Copyright (C) 2014 Marvell + * + * Gregory CLEMENT + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "armada-385.dtsi" +#include + +/ { + model = "Marvell Armada 385 AMC"; + compatible = "marvell,a385-amc", "marvell,armada385", "marvell,armada380"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = ð0; + ethernet1 = ð2; + i2c0 = &i2c0; + spi1 = &spi1; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2 GB */ + }; + + soc { + ranges = ; + + internal-regs { + i2c@11000 { + clock-frequency = <100000>; + u-boot,i2c-slave-addr = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + }; + + serial@12000 { + /* + * Exported on the micro USB connector CON16 + * through an FTDI + */ + + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + ethernet@34000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "sgmii"; + }; + + usb@58000 { + status = "okay"; + }; + + ethernet@70000 { + pinctrl-names = "default"; + /* + * The Reference Clock 0 is used to provide a + * clock to the PHY + */ + pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + + mdio@72004 { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + phy0: ethernet-phy@1 { + reg = <1>; + }; + + phy1: ethernet-phy@0 { + reg = <0>; + }; + }; + + flash@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + }; + }; + + pcie { + status = "okay"; + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + }; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "okay"; + u-boot,dm-pre-reloc; + + spi-flash@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor", "spi-flash"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + m25p,fast-read; + }; +}; + +&refclk { + clock-frequency = <20000000>; +}; -- cgit v1.2.3 From 937cb9d0a671b1df01955edd515ebf4a65e45f85 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 12 Apr 2019 08:47:05 +1200 Subject: ARM: mvebu: sync db-88f6820-amc.dts with Linux v5.0 Sync armada-385-db-88f6820-amc.dts with Linux. Retain the u-boot,dm-pre-reloc and nand differences. Signed-off-by: Chris Packham Signed-off-by: Stefan Roese --- arch/arm/dts/armada-385-db-88f6820-amc.dts | 184 +++++++++++++---------------- 1 file changed, 82 insertions(+), 102 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/armada-385-db-88f6820-amc.dts b/arch/arm/dts/armada-385-db-88f6820-amc.dts index c9ccbb57fff..59a425f6b15 100644 --- a/arch/arm/dts/armada-385-db-88f6820-amc.dts +++ b/arch/arm/dts/armada-385-db-88f6820-amc.dts @@ -1,51 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* - * Device Tree file for Marvell Armada 385 development board + * Device Tree file for Marvell Armada 385 AMC board * (DB-88F6820-AMC) * - * Copyright (C) 2014 Marvell - * - * Gregory CLEMENT - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright (C) 2017 Allied Telesis Labs */ /dts-v1/; #include "armada-385.dtsi" + #include / { model = "Marvell Armada 385 AMC"; - compatible = "marvell,a385-amc", "marvell,armada385", "marvell,armada380"; + compatible = "marvell,a385-db-amc", "marvell,armada385", "marvell,armada380"; chosen { stdout-path = "serial0:115200n8"; @@ -60,90 +28,88 @@ memory { device_type = "memory"; - reg = <0x00000000 0x80000000>; /* 2 GB */ + reg = <0x00000000 0x80000000>; /* 2GB */ }; soc { ranges = ; + }; +}; - internal-regs { - i2c@11000 { - clock-frequency = <100000>; - u-boot,i2c-slave-addr = <0x0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - }; - - serial@12000 { - /* - * Exported on the micro USB connector CON16 - * through an FTDI - */ +&i2c0 { + u-boot,i2c-slave-addr = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; +}; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; - u-boot,dm-pre-reloc; - }; +&uart0 { + /* + * Exported on the micro USB connector CON3 + * through an FTDI + */ - ethernet@34000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "sgmii"; - }; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; + u-boot,dm-pre-reloc; +}; - usb@58000 { - status = "okay"; - }; - ethernet@70000 { - pinctrl-names = "default"; - /* - * The Reference Clock 0 is used to provide a - * clock to the PHY - */ - pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; - }; +ð0 { + pinctrl-names = "default"; + /* + * The Reference Clock 0 is used to provide a + * clock to the PHY + */ + pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; +ð2 { + status = "okay"; + phy = <&phy1>; + phy-mode = "sgmii"; +}; - mdio@72004 { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; +&usb0 { + status = "okay"; +}; - phy0: ethernet-phy@1 { - reg = <1>; - }; - phy1: ethernet-phy@0 { - reg = <0>; - }; - }; - flash@d0000 { - status = "okay"; - num-cs = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - nand-on-flash-bbt; - }; - }; +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; - pcie { - status = "okay"; - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; + phy0: ethernet-phy@1 { + reg = <1>; + }; - }; + phy1: ethernet-phy@0 { + reg = <0>; }; }; +&nand_controller { + status = "okay"; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; +}; + +&pciec { + status = "okay"; +}; + +&pcie1 { + /* Port 0, Lane 0 */ + status = "okay"; +}; + &spi1 { pinctrl-names = "default"; pinctrl-0 = <&spi1_pins>; @@ -154,10 +120,24 @@ u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor", "spi-flash"; + compatible = "jedec,spi-nor"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <50000000>; m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + reg = <0x00000000 0x00100000>; + label = "u-boot"; + }; + partition@100000 { + reg = <0x00100000 0x00040000>; + label = "u-boot-env"; + }; + }; }; }; -- cgit v1.2.3