From 5e2de83f7115aaad6ea32ae8cb41b08a2c2f7a50 Mon Sep 17 00:00:00 2001 From: Josip Kelecic Date: Thu, 13 Feb 2020 14:38:49 +0100 Subject: arm: mvebu: dts: Sort Armada series dts alphabetically MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sort the Armada series dts in the Makefile alphabetically prior to adding new board support. Signed-off-by: Josip Kelečić Reviewed-by: Luka Kovacic Reviewed-by: Stefan Roese --- arch/arm/dts/Makefile | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2a89da2ce9e..6d1e8668e7e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -191,25 +191,25 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-3720-turris-mox.dtb \ armada-3720-uDPU.dtb \ armada-375-db.dtb \ + armada-385-atl-x530.dtb \ + armada-385-atl-x530DP.dtb \ + armada-385-db-88f6820-amc.dtb \ + armada-385-turris-omnia.dtb \ armada-388-clearfog.dtb \ armada-388-gp.dtb \ armada-388-helios4.dtb \ - armada-385-db-88f6820-amc.dtb \ - armada-385-turris-omnia.dtb \ - armada-7040-db.dtb \ + armada-38x-controlcenterdc.dtb \ armada-7040-db-nand.dtb \ + armada-7040-db.dtb \ + armada-8040-clearfog-gt-8k.dtb \ armada-8040-db.dtb \ armada-8040-mcbin.dtb \ - armada-8040-clearfog-gt-8k.dtb \ + armada-xp-crs305-1g-4s.dtb \ + armada-xp-db-xc3-24g4xg.dtb \ armada-xp-gp.dtb \ armada-xp-maxbcm.dtb \ armada-xp-synology-ds414.dtb \ - armada-xp-theadorable.dtb \ - armada-38x-controlcenterdc.dtb \ - armada-385-atl-x530.dtb \ - armada-385-atl-x530DP.dtb \ - armada-xp-db-xc3-24g4xg.dtb \ - armada-xp-crs305-1g-4s.dtb + armada-xp-theadorable.dtb dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \ uniphier-ld11-global.dtb \ -- cgit v1.3.1 From ad91fdfff0bd6ea471afe838e0f6d58ed898694e Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 26 Feb 2020 19:53:50 +1300 Subject: arm: mvebu: update RTC values for PCIe memory wrappers Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/include/mach/cpu.h | 2 ++ arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c | 17 +++++++++++++++++ arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h | 13 +++++++++++++ arch/arm/mach-mvebu/spl.c | 3 +++ 4 files changed, 35 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 2e2d72aac89..fa7c81754b8 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -166,8 +166,10 @@ int ddr3_init(void); /* Auto Voltage Scaling */ #if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) void mv_avs_init(void); +void mv_rtc_config(void); #else static inline void mv_avs_init(void) {} +static inline void mv_rtc_config(void) {} #endif /* diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c index e9dd096ad0f..3c4c7e01a1c 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c @@ -257,6 +257,23 @@ u8 sys_env_device_rev_get(void) return (value & (REVISON_ID_MASK)) >> REVISON_ID_OFFS; } +void mv_rtc_config(void) +{ + u32 i, val; + + if (!(IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARMADA_39X))) + return; + + /* Activate pipe0 for read/write transaction, and set XBAR client number #1 */ + val = 0x1 << DFX_PIPE_SELECT_PIPE0_ACTIVE_OFFS | + 0x1 << DFX_PIPE_SELECT_XBAR_CLIENT_SEL_OFFS; + writel(val, MVEBU_DFX_BASE); + + /* Set new RTC value for all memory wrappers */ + for (i = 0; i < RTC_MEMORY_WRAPPER_COUNT; i++) + reg_write(RTC_MEMORY_WRAPPER_REG(i), RTC_MEMORY_WRAPPER_CTRL_VAL); +} + void mv_avs_init(void) { u32 sar_freq; diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h index 1774a5b780c..17cd811331d 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h @@ -150,6 +150,19 @@ #define MPP_UART1_SET_MASK (~(0xff000)) #define MPP_UART1_SET_DATA (0x66000) +#define DFX_PIPE_SELECT_PIPE0_ACTIVE_OFFS 0 +/* DFX_PIPE_SELECT_XBAR_CLIENT_SEL_OFFS: Since address completion in 14bit + * address mode, and given that [14:8] => [19:13], the 2 lower bits [9:8] => + * [14:13] are dismissed. hence field offset is also shifted to 10 + */ +#define DFX_PIPE_SELECT_XBAR_CLIENT_SEL_OFFS 10 + +#define RTC_MEMORY_CTRL_REG_BASE 0xE6000 +#define RTC_MEMORY_WRAPPER_COUNT 8 +#define RTC_MEMORY_WRAPPER_REG(i) (RTC_MEMORY_CTRL_REG_BASE + ((i) * 0x40)) +#define RTC_MEMORY_CTRL_PDLVMC_FIELD_OFFS 6 +#define RTC_MEMORY_WRAPPER_CTRL_VAL (0x1 << RTC_MEMORY_CTRL_PDLVMC_FIELD_OFFS) + #define AVS_DEBUG_CNTR_REG 0xe4124 #define AVS_DEBUG_CNTR_DEFAULT_VALUE 0x08008073 diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index a99bf166fd8..70fef3b573d 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -130,6 +130,9 @@ void board_init_f(ulong dummy) /* Initialize Auto Voltage Scaling */ mv_avs_init(); + /* Update read timing control for PCIe */ + mv_rtc_config(); + /* * Return to the BootROM to continue the Marvell xmodem * UART boot protocol. As initiated by the kwboot tool. -- cgit v1.3.1 From 4f7991ee1c34f2f0d80a680146aeff867d688dd9 Mon Sep 17 00:00:00 2001 From: Joel Johnson Date: Mon, 23 Mar 2020 14:21:29 -0600 Subject: arm: mvebu: fix SerDes table alignment Tested on Solidrun ClearFog Base. Table alignment was: | Lane # | Speed | Type | -------------------------------- | 0 | 3 | SATA0 | | 1 | 0 | SGMII1 | | 2 | 3 | SATA1 | | 3 | 5 | USB3 HOST1 | | 4 | 5 | USB3 HOST0 | | 5 | 4 | SGMII2 | -------------------------------- After the change, it's correctly aligned as: | Lane # | Speed | Type | -------------------------------- | 0 | 3 | SATA0 | | 1 | 0 | SGMII1 | | 2 | 5 | PCIe1 | | 3 | 5 | USB3 HOST1 | | 4 | 5 | PCIe2 | | 5 | 0 | SGMII2 | -------------------------------- Signed-off-by: Joel Johnson Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index 33e70569bc4..66409a50c0f 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -1366,16 +1366,16 @@ static void print_topology_details(const struct serdes_map *serdes_map, DEBUG_INIT_S("board SerDes lanes topology details:\n"); - DEBUG_INIT_S(" | Lane # | Speed | Type |\n"); + DEBUG_INIT_S(" | Lane # | Speed | Type |\n"); DEBUG_INIT_S(" --------------------------------\n"); for (lane_num = 0; lane_num < count; lane_num++) { if (serdes_map[lane_num].serdes_type == DEFAULT_SERDES) continue; DEBUG_INIT_S(" | "); DEBUG_INIT_D(hws_get_physical_serdes_num(lane_num), 1); - DEBUG_INIT_S(" | "); + DEBUG_INIT_S(" | "); DEBUG_INIT_D(serdes_map[lane_num].serdes_speed, 2); - DEBUG_INIT_S(" | "); + DEBUG_INIT_S(" | "); DEBUG_INIT_S((char *) serdes_type_to_string[serdes_map[lane_num]. serdes_type]); -- cgit v1.3.1 From a8d0aa31bd213160bf9cb689df1040db0377cc66 Mon Sep 17 00:00:00 2001 From: Joel Johnson Date: Mon, 23 Mar 2020 14:21:30 -0600 Subject: arm: mvebu: solidrun: remove hardcoded DTS MAC address Using a consistent hardcoded MAC address from the DTS file causes issues when using multiple devices on the same network segment. Instead rely on environment configuration or random generation. Signed-off-by: Joel Johnson Reviewed-by: Stefan Roese --- arch/arm/dts/armada-38x-solidrun-microsom.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi index a322a28c215..9bbeafc53bf 100644 --- a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi +++ b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi @@ -39,7 +39,6 @@ ð0 { /* ethernet@70000 */ - mac-address = [00 50 43 02 02 01]; pinctrl-0 = <&ge0_rgmii_pins>; pinctrl-names = "default"; phy = <&phy_dedicated>; -- cgit v1.3.1 From 9f205d658da33bf2462baa1608aed996c48473af Mon Sep 17 00:00:00 2001 From: Joel Johnson Date: Mon, 23 Mar 2020 14:21:32 -0600 Subject: arm: mvebu: clearfog: initial ClearFog Base variant Add a unique entry for ClearFog Base variant, reflected in the board name and adjusted SerDes topology. Signed-off-by: Joel Johnson Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/Kconfig | 2 ++ board/solidrun/clearfog/Kconfig | 18 ++++++++++++++++++ board/solidrun/clearfog/clearfog.c | 38 ++++++++++++++++++++++++++++++++------ 3 files changed, 52 insertions(+), 6 deletions(-) create mode 100644 board/solidrun/clearfog/Kconfig (limited to 'arch') diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index bc5eaa5a767..161dee937fa 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -280,4 +280,6 @@ config SECURED_MODE_CSK_INDEX default 0 depends on SECURED_MODE_IMAGE +source "board/solidrun/clearfog/Kconfig" + endif diff --git a/board/solidrun/clearfog/Kconfig b/board/solidrun/clearfog/Kconfig new file mode 100644 index 00000000000..936d5918f8a --- /dev/null +++ b/board/solidrun/clearfog/Kconfig @@ -0,0 +1,18 @@ +menu "ClearFog configuration" + depends on TARGET_CLEARFOG + +config TARGET_CLEARFOG_BASE + bool "Use ClearFog Base static configuration" + help + Use the ClearFog Base as the static configuration instead of the + default which uses the ClearFog Pro. + + Runtime board detection is always attempted and used if available. The + static configuration is used as a fallback in cases where runtime + detection is disabled, is not available in hardware, or otherwise fails. + + Only newer revisions of the ClearFog product line support runtime + detection via additional EEPROM hardware. This option enables selecting + the Base variant for older hardware revisions. + +endmenu diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index 9b31902c704..11d3a7f877b 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -42,6 +42,7 @@ static void cf_read_tlv_data(void) read_tlv_data(&cf_tlv_data); } +/* The starting board_serdes_map reflects original Clearfog Pro usage */ static struct serdes_map board_serdes_map[] = { {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}, {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, @@ -51,6 +52,13 @@ static struct serdes_map board_serdes_map[] = { {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, }; +void config_cfbase_serdes_map(void) +{ + board_serdes_map[4].serdes_type = USB3_HOST0; + board_serdes_map[4].serdes_speed = SERDES_SPEED_5_GBPS; + board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE; +} + int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) { cf_read_tlv_data(); @@ -59,12 +67,26 @@ int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) board_serdes_map[0].serdes_type = PEX0; board_serdes_map[0].serdes_speed = SERDES_SPEED_5_GBPS; board_serdes_map[0].serdes_mode = PEX_ROOT_COMPLEX_X1; - } - - if (sr_product_is(&cf_tlv_data, "Clearfog Base")) { - board_serdes_map[4].serdes_type = USB3_HOST0; - board_serdes_map[4].serdes_speed = SERDES_SPEED_5_GBPS; - board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE; + } else if (sr_product_is(&cf_tlv_data, "Clearfog Pro")) { + /* handle recognized product as noop, no adjustment required */ + } else if (sr_product_is(&cf_tlv_data, "Clearfog Base")) { + config_cfbase_serdes_map(); + } else { + /* + * Fallback to static default. EEPROM TLV support is not + * enabled, runtime detection failed, hardware support is not + * present, EEPROM is corrupt, or an unrecognized product name + * is present. + */ + if (IS_ENABLED(CONFIG_SPL_CMD_TLV_EEPROM)) + puts("EEPROM TLV detection failed: "); + puts("Using static config for "); + if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE)) { + puts("Clearfog Base.\n"); + config_cfbase_serdes_map(); + } else { + puts("Clearfog Pro.\n"); + } } *serdes_map_array = board_serdes_map; @@ -171,6 +193,8 @@ int board_init(void) int checkboard(void) { char *board = "Clearfog Pro"; + if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE)) + board = "Clearfog Base"; cf_read_tlv_data(); if (strlen(cf_tlv_data.tlv_product_name[0]) > 0) @@ -200,6 +224,8 @@ int board_late_init(void) env_set("fdtfile", "armada-385-clearfog-gtr-s4.dtb"); else if (sr_product_is(&cf_tlv_data, "Clearfog GTR L8")) env_set("fdtfile", "armada-385-clearfog-gtr-l8.dtb"); + else if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE)) + env_set("fdtfile", "armada-388-clearfog-base.dtb"); return 0; } -- cgit v1.3.1 From eddd6f90c99a19b3290590c0eb041f95002b4f4c Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Wed, 8 Apr 2020 12:02:04 +0200 Subject: arm: mvebu: dts: turris_mox: update sdhci properties MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With recent changes to the mmc subsystem (chip detect code etc) update the sdhci node of the Turris Mox device tree. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese --- arch/arm/dts/armada-3720-turris-mox.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/armada-3720-turris-mox.dts b/arch/arm/dts/armada-3720-turris-mox.dts index c36a5b8895a..4c65c3e32cd 100644 --- a/arch/arm/dts/armada-3720-turris-mox.dts +++ b/arch/arm/dts/armada-3720-turris-mox.dts @@ -45,6 +45,20 @@ regulator-boot-on; }; + vsdc_reg: vsdc-reg { + compatible = "regulator-gpio"; + regulator-name = "vsdc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1 + 3300000 0x0>; + enable-active-high; + }; + mdio { #address-cells = <1>; #size-cells = <0>; @@ -93,7 +107,11 @@ }; &sdhci1 { + wp-inverted; bus-width = <4>; + cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>; + vqmmc-supply = <&vsdc_reg>; + marvell,pad-type = "sd"; status = "okay"; }; -- cgit v1.3.1 From 9e4cdbabac1b38da30838701dca9f70935c7e095 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Wed, 8 Apr 2020 12:02:06 +0200 Subject: arm: mvebu: dts: turris_mox: fix USB3 regulator MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit e8e9715df2d4 requires the USB3 regulator node to have the enable-active-high property for the regulator to work properly. The GPIO_ACTIVE_HIGH constant is not enough anymore. Signed-off-by: Marek Behún Fixes: e8e9715df2d4 ("regulator: fixed: Modify enable-active-high...") Reviewed-by: Stefan Roese --- arch/arm/dts/armada-3720-turris-mox.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/dts/armada-3720-turris-mox.dts b/arch/arm/dts/armada-3720-turris-mox.dts index 4c65c3e32cd..a1e0ad50204 100644 --- a/arch/arm/dts/armada-3720-turris-mox.dts +++ b/arch/arm/dts/armada-3720-turris-mox.dts @@ -42,6 +42,7 @@ startup-delay-us = <2000000>; shutdown-delay-us = <1000000>; gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>; + enable-active-high; regulator-boot-on; }; -- cgit v1.3.1 From f075b425a72c095a1e11ff855c3ba8b060feec20 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Wed, 8 Apr 2020 19:25:18 +0200 Subject: arm64: mvebu: armada-8k: move dram init code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move Armada-8k specific DRAM init code into armada-8k specific directory. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/arm64-common.c | 46 ++---------------------------- arch/arm/mach-mvebu/armada8k/Makefile | 3 +- arch/arm/mach-mvebu/armada8k/dram.c | 52 ++++++++++++++++++++++++++++++++++ arch/arm/mach-mvebu/include/mach/cpu.h | 4 +++ 4 files changed, 59 insertions(+), 46 deletions(-) create mode 100644 arch/arm/mach-mvebu/armada8k/dram.c (limited to 'arch') diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index 40b98dbf08b..244ea49d8a3 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -45,54 +45,12 @@ const struct mbus_dram_target_info *mvebu_mbus_dram_info(void) return NULL; } -/* DRAM init code ... */ - -#define MV_SIP_DRAM_SIZE 0x82000010 - -static u64 a8k_dram_scan_ap_sz(void) -{ - struct pt_regs pregs; - - pregs.regs[0] = MV_SIP_DRAM_SIZE; - pregs.regs[1] = SOC_REGS_PHY_BASE; - smc_call(&pregs); - - return pregs.regs[0]; -} - -static void a8k_dram_init_banksize(void) -{ - /* - * The firmware (ATF) leaves a 1G whole above the 3G mark for IO - * devices. Higher RAM is mapped at 4G. - * - * Config 2 DRAM banks: - * Bank 0 - max size 4G - 1G - * Bank 1 - ram size - 4G + 1G - */ - phys_size_t max_bank0_size = SZ_4G - SZ_1G; - - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size <= max_bank0_size) { - gd->bd->bi_dram[0].size = gd->ram_size; - return; - } - - gd->bd->bi_dram[0].size = max_bank0_size; - if (CONFIG_NR_DRAM_BANKS > 1) { - gd->bd->bi_dram[1].start = SZ_4G; - gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size; - } -} - __weak int dram_init_banksize(void) { if (CONFIG_IS_ENABLED(ARMADA_8K)) - a8k_dram_init_banksize(); + return a8k_dram_init_banksize(); else - fdtdec_setup_memory_banksize(); - - return 0; + return fdtdec_setup_memory_banksize(); } __weak int dram_init(void) diff --git a/arch/arm/mach-mvebu/armada8k/Makefile b/arch/arm/mach-mvebu/armada8k/Makefile index 82cb25b4173..0a4756717a3 100644 --- a/arch/arm/mach-mvebu/armada8k/Makefile +++ b/arch/arm/mach-mvebu/armada8k/Makefile @@ -2,5 +2,4 @@ # # Copyright (C) 2016 Stefan Roese -obj-y = cpu.o -obj-y += cache_llc.o +obj-y = cpu.o cache_llc.o dram.o diff --git a/arch/arm/mach-mvebu/armada8k/dram.c b/arch/arm/mach-mvebu/armada8k/dram.c new file mode 100644 index 00000000000..265a8b0ae8a --- /dev/null +++ b/arch/arm/mach-mvebu/armada8k/dram.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Stefan Roese + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define MV_SIP_DRAM_SIZE 0x82000010 + +u64 a8k_dram_scan_ap_sz(void) +{ + struct pt_regs pregs; + + pregs.regs[0] = MV_SIP_DRAM_SIZE; + pregs.regs[1] = SOC_REGS_PHY_BASE; + smc_call(&pregs); + + return pregs.regs[0]; +} + +int a8k_dram_init_banksize(void) +{ + /* + * The firmware (ATF) leaves a 1G whole above the 3G mark for IO + * devices. Higher RAM is mapped at 4G. + * + * Config 2 DRAM banks: + * Bank 0 - max size 4G - 1G + * Bank 1 - ram size - 4G + 1G + */ + phys_size_t max_bank0_size = SZ_4G - SZ_1G; + + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + if (gd->ram_size <= max_bank0_size) { + gd->bd->bi_dram[0].size = gd->ram_size; + return 0; + } + + gd->bd->bi_dram[0].size = max_bank0_size; + if (CONFIG_NR_DRAM_BANKS > 1) { + gd->bd->bi_dram[1].start = SZ_4G; + gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size; + } + + return 0; +} diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index fa7c81754b8..16d825220e0 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -172,6 +172,10 @@ static inline void mv_avs_init(void) {} static inline void mv_rtc_config(void) {} #endif +/* A8K dram functions */ +u64 a8k_dram_scan_ap_sz(void); +int a8k_dram_init_banksize(void); + /* * get_ref_clk * -- cgit v1.3.1 From a129f64fb0f817178955e234c0a4f8b415b38759 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Wed, 8 Apr 2020 19:25:19 +0200 Subject: arm64: mvebu: a37xx: improve code determining memory info structures MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently on Armada-37xx the mem_map structure is statically defined to map first 2 GB of memory as RAM region, and system registers and PCIe region device region. This is insufficient for when there is more RAM or when for example the PCIe windows is mapped to another address by the CPU Address Decoder. In the case when the board has 4 GB RAM, on some boards the ARM Trusted Firmware can move the PCIe window to another address, in order to maximize possible usable RAM. Also the dram_init and dram_init_banksize looks for information in device-tree, and therefore different device trees are needed for boards with different RAM sizes. Therefore we add code that looks at how the ARM Trusted Firmware has configured the CPU Address Decoder windows, and then we update the mem_map structure and compute gd->ram_size and gd->bd->bi_dram bank base addresses and sizes accordingly. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/arm64-common.c | 5 + arch/arm/mach-mvebu/armada3700/cpu.c | 252 +++++++++++++++++++++++++++++---- arch/arm/mach-mvebu/include/mach/cpu.h | 4 + 3 files changed, 235 insertions(+), 26 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index 244ea49d8a3..34cc0479a8b 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -49,6 +49,8 @@ __weak int dram_init_banksize(void) { if (CONFIG_IS_ENABLED(ARMADA_8K)) return a8k_dram_init_banksize(); + else if (CONFIG_IS_ENABLED(ARMADA_3700)) + return a3700_dram_init_banksize(); else return fdtdec_setup_memory_banksize(); } @@ -61,6 +63,9 @@ __weak int dram_init(void) return 0; } + if (CONFIG_IS_ENABLED(ARMADA_3700)) + return a3700_dram_init(); + if (fdtdec_setup_mem_size_base() != 0) return -EINVAL; diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c index c83268181b9..959a909d8af 100644 --- a/arch/arm/mach-mvebu/armada3700/cpu.c +++ b/arch/arm/mach-mvebu/armada3700/cpu.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2016 Stefan Roese + * Copyright (C) 2020 Marek Behun */ #include @@ -13,6 +14,7 @@ #include #include #include +#include /* Armada 3700 */ #define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800)) @@ -26,39 +28,237 @@ #define MVEBU_NB_WARM_RST_REG (MVEBU_GPIO_NB_REG_BASE + 0x40) #define MVEBU_NB_WARM_RST_MAGIC_NUM 0x1d1e -static struct mm_region mvebu_mem_map[] = { - { - /* RAM */ - .phys = 0x0UL, - .virt = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, +/* Armada 3700 CPU Address Decoder registers */ +#define MVEBU_CPU_DEC_WIN_REG_BASE (size_t)(MVEBU_REGISTER(0xcf00)) +#define MVEBU_CPU_DEC_WIN_CTRL(w) \ + (MVEBU_CPU_DEC_WIN_REG_BASE + ((w) << 4)) +#define MVEBU_CPU_DEC_WIN_CTRL_EN BIT(0) +#define MVEBU_CPU_DEC_WIN_CTRL_TGT_MASK 0xf +#define MVEBU_CPU_DEC_WIN_CTRL_TGT_OFFS 4 +#define MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM 0 +#define MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE 2 +#define MVEBU_CPU_DEC_WIN_SIZE(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0x4) +#define MVEBU_CPU_DEC_WIN_BASE(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0x8) +#define MVEBU_CPU_DEC_WIN_REMAP(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0xc) +#define MVEBU_CPU_DEC_WIN_GRANULARITY 16 +#define MVEBU_CPU_DEC_WINS 5 + +#define MAX_MEM_MAP_REGIONS (MVEBU_CPU_DEC_WINS + 2) + +#define A3700_PTE_BLOCK_NORMAL \ + (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE) +#define A3700_PTE_BLOCK_DEVICE \ + (PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE) + +DECLARE_GLOBAL_DATA_PTR; + +static struct mm_region mvebu_mem_map[MAX_MEM_MAP_REGIONS] = { { - /* SRAM, MMIO regions */ - .phys = 0xd0000000UL, - .virt = 0xd0000000UL, + /* + * SRAM, MMIO regions + * Don't remove this, a3700_build_mem_map needs it. + */ + .phys = SOC_REGS_PHY_BASE, + .virt = SOC_REGS_PHY_BASE, .size = 0x02000000UL, /* 32MiB internal registers */ - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE - }, - { - /* PCI regions */ - .phys = 0xe8000000UL, - .virt = 0xe8000000UL, - .size = 0x02000000UL, /* 32MiB master PCI space */ - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE + .attrs = A3700_PTE_BLOCK_DEVICE }, - { - /* List terminator */ - 0, - } }; struct mm_region *mem_map = mvebu_mem_map; +static int get_cpu_dec_win(int win, u32 *tgt, u32 *base, u32 *size) +{ + u32 reg; + + reg = readl(MVEBU_CPU_DEC_WIN_CTRL(win)); + if (!(reg & MVEBU_CPU_DEC_WIN_CTRL_EN)) + return -1; + + if (tgt) { + reg >>= MVEBU_CPU_DEC_WIN_CTRL_TGT_OFFS; + reg &= MVEBU_CPU_DEC_WIN_CTRL_TGT_MASK; + *tgt = reg; + } + + if (base) { + reg = readl(MVEBU_CPU_DEC_WIN_BASE(win)); + *base = reg << MVEBU_CPU_DEC_WIN_GRANULARITY; + } + + if (size) { + /* + * Window size is encoded as the number of 1s from LSB to MSB, + * followed by 0s. The number of 1s specifies the size in 64 KiB + * granularity. + */ + reg = readl(MVEBU_CPU_DEC_WIN_SIZE(win)); + *size = ((reg + 1) << MVEBU_CPU_DEC_WIN_GRANULARITY); + } + + return 0; +} + +/* + * Builds mem_map according to CPU Address Decoder settings, which were set by + * the TIMH image on the Cortex-M3 secure processor, or by ARM Trusted Firmware + */ +static void build_mem_map(void) +{ + int win, region; + + region = 1; + for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) { + u32 base, tgt, size; + u64 attrs; + + /* skip disabled windows */ + if (get_cpu_dec_win(win, &tgt, &base, &size)) + continue; + + if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM) + attrs = A3700_PTE_BLOCK_NORMAL; + else if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE) + attrs = A3700_PTE_BLOCK_DEVICE; + else + /* skip windows with other targets */ + continue; + + mvebu_mem_map[region].phys = base; + mvebu_mem_map[region].virt = base; + mvebu_mem_map[region].size = size; + mvebu_mem_map[region].attrs = attrs; + ++region; + } + + /* add list terminator */ + mvebu_mem_map[region].size = 0; + mvebu_mem_map[region].attrs = 0; +} + +void enable_caches(void) +{ + build_mem_map(); + + icache_enable(); + dcache_enable(); +} + +int a3700_dram_init(void) +{ + int win; + + gd->ram_size = 0; + for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) { + u32 base, tgt, size; + + /* skip disabled windows */ + if (get_cpu_dec_win(win, &tgt, &base, &size)) + continue; + + /* skip non-DRAM windows */ + if (tgt != MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM) + continue; + + /* + * It is possible that one image was built for boards with + * different RAM sizes, for example 512 MiB and 1 GiB. + * We therefore try to determine the actual RAM size in the + * window with get_ram_size. + */ + gd->ram_size += get_ram_size((void *)(size_t)base, size); + } + + return 0; +} + +struct a3700_dram_window { + size_t base, size; +}; + +static int dram_win_cmp(const void *a, const void *b) +{ + size_t ab, bb; + + ab = ((const struct a3700_dram_window *)a)->base; + bb = ((const struct a3700_dram_window *)b)->base; + + if (ab < bb) + return -1; + else if (ab > bb) + return 1; + else + return 0; +} + +int a3700_dram_init_banksize(void) +{ + struct a3700_dram_window dram_wins[MVEBU_CPU_DEC_WINS]; + int bank, win, ndram_wins; + u32 last_end; + size_t size; + + ndram_wins = 0; + for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) { + u32 base, tgt, size; + + /* skip disabled windows */ + if (get_cpu_dec_win(win, &tgt, &base, &size)) + continue; + + /* skip non-DRAM windows */ + if (tgt != MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM) + continue; + + dram_wins[win].base = base; + dram_wins[win].size = size; + ++ndram_wins; + } + + qsort(dram_wins, ndram_wins, sizeof(dram_wins[0]), dram_win_cmp); + + bank = 0; + last_end = -1; + + for (win = 0; win < ndram_wins; ++win) { + /* again determining actual RAM size as in a3700_dram_init */ + size = get_ram_size((void *)dram_wins[win].base, + dram_wins[win].size); + + /* + * Check if previous window ends as the current starts. If yes, + * merge these windows into one "bank". This is possible by this + * simple check thanks to mem_map regions being qsorted in + * build_mem_map. + */ + if (last_end == dram_wins[win].base) { + gd->bd->bi_dram[bank - 1].size += size; + last_end += size; + } else { + if (bank == CONFIG_NR_DRAM_BANKS) { + printf("Need more CONFIG_NR_DRAM_BANKS\n"); + return -ENOBUFS; + } + + gd->bd->bi_dram[bank].start = dram_wins[win].base; + gd->bd->bi_dram[bank].size = size; + last_end = dram_wins[win].base + size; + ++bank; + } + } + + /* + * If there is more place for DRAM BANKS definitions than needed, fill + * the rest with zeros. + */ + for (; bank < CONFIG_NR_DRAM_BANKS; ++bank) { + gd->bd->bi_dram[bank].start = 0; + gd->bd->bi_dram[bank].size = 0; + } + + return 0; +} + void reset_cpu(ulong ignored) { /* diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 16d825220e0..3bb541b6ca1 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -176,6 +176,10 @@ static inline void mv_rtc_config(void) {} u64 a8k_dram_scan_ap_sz(void); int a8k_dram_init_banksize(void); +/* A3700 dram functions */ +int a3700_dram_init(void); +int a3700_dram_init_banksize(void); + /* * get_ref_clk * -- cgit v1.3.1 From cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7 Mon Sep 17 00:00:00 2001 From: Marek Behún Date: Wed, 8 Apr 2020 19:25:21 +0200 Subject: arm64: mvebu: a37xx: add device-tree fixer for PCIe regions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In case when ARM Trusted Firmware changes the default address of PCIe regions (which can be done for devices with 4 GB RAM to maximize the amount of RAM the device can use) we add code that looks at how ATF changed the PCIe windows in the CPU Address Decoder and changes given device-tree blob accordingly. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/armada3700/cpu.c | 52 ++++++++++++++++++++++++++++++++++ arch/arm/mach-mvebu/include/mach/cpu.h | 3 ++ 2 files changed, 55 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c index 959a909d8af..17d2d43babb 100644 --- a/arch/arm/mach-mvebu/armada3700/cpu.c +++ b/arch/arm/mach-mvebu/armada3700/cpu.c @@ -50,6 +50,8 @@ #define A3700_PTE_BLOCK_DEVICE \ (PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE) +#define PCIE_PATH "/soc/pcie@d0070000" + DECLARE_GLOBAL_DATA_PTR; static struct mm_region mvebu_mem_map[MAX_MEM_MAP_REGIONS] = { @@ -259,6 +261,56 @@ int a3700_dram_init_banksize(void) return 0; } +static u32 find_pcie_window_base(void) +{ + int win; + + for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) { + u32 base, tgt; + + /* skip disabled windows */ + if (get_cpu_dec_win(win, &tgt, &base, NULL)) + continue; + + if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE) + return base; + } + + return -1; +} + +int a3700_fdt_fix_pcie_regions(void *blob) +{ + u32 new_ranges[14], base; + const u32 *ranges; + int node, len; + + node = fdt_path_offset(blob, PCIE_PATH); + if (node < 0) + return node; + + ranges = fdt_getprop(blob, node, "ranges", &len); + if (!ranges) + return -ENOENT; + + if (len != sizeof(new_ranges)) + return -EINVAL; + + memcpy(new_ranges, ranges, len); + + base = find_pcie_window_base(); + if (base == -1) + return -ENOENT; + + new_ranges[2] = cpu_to_fdt32(base); + new_ranges[4] = new_ranges[2]; + + new_ranges[9] = cpu_to_fdt32(base + 0x1000000); + new_ranges[11] = new_ranges[9]; + + return fdt_setprop_inplace(blob, node, "ranges", new_ranges, len); +} + void reset_cpu(ulong ignored) { /* diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 3bb541b6ca1..c3f8ad85065 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -180,6 +180,9 @@ int a8k_dram_init_banksize(void); int a3700_dram_init(void); int a3700_dram_init_banksize(void); +/* A3700 PCIe regions fixer for device tree */ +int a3700_fdt_fix_pcie_regions(void *blob); + /* * get_ref_clk * -- cgit v1.3.1