From 30e486f3a501cbfdce178433fa66bdc001ab7e05 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 31 Dec 2020 09:52:15 -0700 Subject: x86: coral: Update an unused pin to reduce power GPIO_25 is not used on coral, so set it up in deep sleep. Signed-off-by: Simon Glass --- arch/x86/dts/chromebook_coral.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index a8460220957..965f59276af 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -637,6 +637,7 @@ PAD_CFG0_TX_DISABLE | PAD_CFG0_ROUTE_IOAPIC | PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT) (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TXD_RXE) + PAD_CFG_GPI(GPIO_25, UP_20K, DEEP) /* unused */ /* * WLAN_PE_RST - default to deasserted just in case FSP -- cgit v1.2.3 From a0df924928906b9da095dcbfa63dd5503e3ac3df Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 22 Dec 2020 07:53:03 +0100 Subject: x86: typo segement %s/segement/segment/ Signed-off-by: Heinrich Schuchardt Reviewed-by: Bin Meng --- arch/x86/cpu/i386/cpu.c | 2 +- arch/x86/cpu/start.S | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 7517b756f43..6fa0f4d32ba 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -175,7 +175,7 @@ void arch_setup_gd(gd_t *new_gd) * Per Intel FSP external architecture specification, before calling any FSP * APIs, we need make sure the system is in flat 32-bit mode and both the code * and data selectors should have full 4GB access range. Here we reuse the one - * we used in arch/x86/cpu/start16.S, and reload the segement registers. + * we used in arch/x86/cpu/start16.S, and reload the segment registers. */ void setup_fsp_gdt(void) { diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 3b6ed37bc07..3d0d95295f6 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -77,7 +77,7 @@ _start: lgdt gdt_ptr2 #endif - /* Load the segement registers to match the GDT loaded in start16.S */ + /* Load the segment registers to match the GDT loaded in start16.S */ movl $(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax movw %ax, %fs movw %ax, %ds -- cgit v1.2.3 From b680c5539a4b29889a2d248aaa2c14e2669046fd Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Fri, 25 Dec 2020 16:04:26 +0100 Subject: sandbox: fix sandbox_cmdline_cb_test_fdt() fmt does not foresee any parameter. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- arch/sandbox/cpu/start.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 2d18d9debcd..25425809747 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -215,7 +215,7 @@ static int sandbox_cmdline_cb_test_fdt(struct sandbox_state *state, if (!p) p = fname + strlen(fname); len -= p - fname; - snprintf(p, len, fmt, p); + snprintf(p, len, fmt); state->fdt_fname = fname; return 0; -- cgit v1.2.3 From d8e9a93895fb3ad710963ddef6a4cc7c43bd65f6 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 16 Jan 2021 14:52:22 -0700 Subject: cros_ec: Add a function for the hello message This is used several times in this file. Put it in a function to avoid code duplication. Also add a test for this function. There are no cros_ec tests at present, so it is time to update the code. Signed-off-by: Simon Glass --- arch/sandbox/include/asm/test.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index 05f66f700ca..8363ca73195 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -57,6 +57,12 @@ enum { SYSCON_COUNT }; +/** + */ +enum cros_ec_test_t { + CROSECT_BREAK_HELLO = BIT(1), +}; + /** * sandbox_i2c_set_test_mode() - set test mode for running unit tests * @@ -260,4 +266,12 @@ uint sandbox_pci_read_bar(u32 barval, int type, uint size); */ void sandbox_set_enable_memio(bool enable); +/** + * sandbox_cros_ec_set_test_flags() - Set behaviour for testing purposes + * + * @dev: Device to check + * @flags: Flags to control behaviour (CROSECT_...) + */ +void sandbox_cros_ec_set_test_flags(struct udevice *dev, uint flags); + #endif -- cgit v1.2.3 From 3a6c994f3896d66e617acdf9bb58ffc4def08b71 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 16 Jan 2021 14:52:28 -0700 Subject: cros_ec: Add support for switches On x86 platforms the EC provides a way to read 'switches', which are on/off values determined by the EC. Add a new driver method for this and implement it for LPC. Signed-off-by: Simon Glass --- arch/sandbox/include/asm/test.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index 8363ca73195..1cb960ac240 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -61,6 +61,7 @@ enum { */ enum cros_ec_test_t { CROSECT_BREAK_HELLO = BIT(1), + CROSECT_LID_OPEN = BIT(2), }; /** -- cgit v1.2.3 From 442e6305b5b02d689774a0bf73311643ffa0df6f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 21 Jan 2021 13:57:07 -0700 Subject: x86: coral: Support TPM and RTC in SPL Update the devicetree so that the TPM and RTC can be used in SPL. Also enable the pins used for getting the memory configuration settings while we are here. Signed-off-by: Simon Glass --- arch/x86/dts/chromebook_coral.dts | 20 +++++++++++++++++++- arch/x86/include/asm/arch-apollolake/iomap.h | 3 +++ 2 files changed, 22 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 965f59276af..9319123c0c4 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /dts-v1/; +#include #include /include/ "skeleton.dtsi" @@ -99,6 +100,7 @@ clk: clock { compatible = "intel,apl-clk"; #clock-cells = <1>; + u-boot,dm-pre-reloc; }; cpus { @@ -139,6 +141,7 @@ }; acpi_gpe: general-purpose-events { + u-boot,dm-pre-reloc; reg = ; compatible = "intel,acpi-gpe"; interrupt-controller; @@ -417,8 +420,10 @@ }; i2c_2: i2c2@16,2 { - compatible = "intel,apl-i2c"; + compatible = "intel,apl-i2c", "snps,designware-i2c-pci"; reg = <0x0200b210 0 0 0 0>; + early-regs = ; + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <0>; clock-frequency = <400000>; @@ -429,6 +434,7 @@ tpm: tpm@50 { reg = <0x50>; compatible = "google,cr50"; + u-boot,dm-pre-reloc; u-boot,i2c-offset-len = <0>; ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>; interrupts-extended = <&acpi_gpe GPIO_28_IRQ @@ -583,6 +589,7 @@ u-boot,dm-pre-reloc; cros_ec: cros-ec { u-boot,dm-pre-proper; + u-boot,dm-vpl; compatible = "google,cros-ec-lpc"; reg = <0x204 1 0x200 1 0x880 0x80>; @@ -658,6 +665,11 @@ PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */ PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */ PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */ + + PAD_CFG_GPI(GPIO_101, NONE, DEEP) /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_GPI(GPIO_102, NONE, DEEP) /* FST_IO3 -- MEM_CONFIG1 */ + PAD_CFG_GPI(GPIO_38, NONE, DEEP) /* LPSS_UART0_RXD - MEM_CONFIG2*/ + PAD_CFG_GPI(GPIO_45, NONE, DEEP) /* LPSS_UART1_CTS - MEM_CONFIG3 */ >; }; @@ -1211,3 +1223,9 @@ PAD_CFG_GPI(GPIO_73, UP_20K, DEEP) /* GP_CAMERASB11 */ >; }; + +&rtc { + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; +}; diff --git a/arch/x86/include/asm/arch-apollolake/iomap.h b/arch/x86/include/asm/arch-apollolake/iomap.h index 21c5f33021a..a4ea1507073 100644 --- a/arch/x86/include/asm/arch-apollolake/iomap.h +++ b/arch/x86/include/asm/arch-apollolake/iomap.h @@ -33,6 +33,9 @@ #define SRAM_SIZE_2 (4 * KiB) #endif +/* Early address for I2C port 2 */ +#define IOMAP_I2C2_BASE (0xfe020000 + 2 * 0x1000) + /* * Use UART2. To use UART1 you need to set '2' to '1', change device tree serial * node name and 'reg' property, and update CONFIG_DEBUG_UART_BASE. -- cgit v1.2.3 From d85f2c4f2970d0ec2f5f075de734afd11200d153 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 21 Jan 2021 13:57:09 -0700 Subject: sandbox: Disable I2C emulators in SPL These cannot work with of-platdata since they currently need the devicetree at runtime. Disable the emulators and the sandbox I2C driver that needs them. We can enable these later, if needed for testing. Switch the of_plat_parent test over to use a simple bus instead. Signed-off-by: Simon Glass Reviewed-by: Heiko Schocher --- arch/sandbox/dts/sandbox.dtsi | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi index d842f021760..dc933f3bfc7 100644 --- a/arch/sandbox/dts/sandbox.dtsi +++ b/arch/sandbox/dts/sandbox.dtsi @@ -260,10 +260,14 @@ stringarray = "pre-proper"; }; - spl-test7 { + test-bus { + compatible = "simple-bus"; u-boot,dm-spl; - compatible = "sandbox,spl-test"; - stringarray = "spl"; + spl-test7 { + u-boot,dm-spl; + compatible = "sandbox,spl-test"; + stringarray = "spl"; + }; }; square { -- cgit v1.2.3 From ff5fa7d62655ae6c1873e17057c057566c81df0d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 21 Jan 2021 13:57:14 -0700 Subject: dm: core: Update ofnode_read_fmap_entry() to read hashes At present this function uses the old format for reading hashes. Add support for the current format. Add a test while we are here. Signed-off-by: Simon Glass --- arch/sandbox/dts/test.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index f86cd0d3b27..e95f4631bf2 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -90,6 +90,16 @@ wp-ro { image-pos = <0xf000>; size = <0x1000>; + used = <0x884>; + compress = "lz4"; + uncomp-size = <0xcf8>; + hash { + algo = "sha256"; + value = [00 01 02 03 04 05 06 07 + 08 09 0a 0b 0c 0d 0e 0f + 10 11 12 13 14 15 16 17 + 18 19 1a 1b 1c 1d 1e 1f]; + }; }; rw { image-pos = <0x10000>; -- cgit v1.2.3 From 43db07507abdb54b6575345300c171b0486e46be Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 30 Dec 2020 18:07:48 +0100 Subject: sandbox: keep time offset when resetting The UEFI Self Certification Test (SCT) checks the SetTime() service with the following steps: * set date * reset * check date matches To be compliant the sandbox should keep the offset to the host RTC during resets. The implementation uses the environment variable UBOOT_SB_TIME_OFFSET to persist the offset. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- arch/sandbox/cpu/os.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch') diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 80996a91ce7..3d8af0a52bb 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -32,6 +32,9 @@ #include #include +/* Environment variable for time offset */ +#define ENV_TIME_OFFSET "UBOOT_SB_TIME_OFFSET" + /* Operating System Interface */ struct os_mem_hdr { @@ -798,6 +801,28 @@ int os_spl_to_uboot(const char *fname) return os_jump_to_file(fname); } +long os_get_time_offset(void) +{ + const char *offset; + + offset = getenv(ENV_TIME_OFFSET); + if (offset) + return strtol(offset, NULL, 0); + return 0; +} + +void os_set_time_offset(long offset) +{ + char buf[21]; + int ret; + + snprintf(buf, sizeof(buf), "%ld", offset); + ret = setenv(ENV_TIME_OFFSET, buf, true); + if (ret) + printf("Could not set environment variable %s\n", + ENV_TIME_OFFSET); +} + void os_localtime(struct rtc_time *rt) { time_t t = time(NULL); -- cgit v1.2.3