From 0f8106f8e0c03839b371eaee1d7459b810d569ec Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 2 Dec 2020 18:47:30 +0100 Subject: treewide: Update email address Patrick Delaunay and Patrice Chotard Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/include/asm/arch-stih410/sdhci.h | 2 +- arch/arm/include/asm/arch-stih410/sys_proto.h | 2 +- arch/arm/include/asm/arch-stm32/stm32f.h | 2 +- arch/arm/include/asm/arch-stm32f4/stm32_pwr.h | 2 +- arch/arm/include/asm/arch-stm32f7/stm32_pwr.h | 2 +- arch/arm/include/asm/arch-stm32h7/gpio.h | 2 +- arch/arm/include/asm/arch-stm32h7/stm32.h | 2 +- arch/arm/mach-stm32/soc.c | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-stih410/sdhci.h b/arch/arm/include/asm/arch-stih410/sdhci.h index d5557b89fcb..1735c0e3918 100644 --- a/arch/arm/include/asm/arch-stih410/sdhci.h +++ b/arch/arm/include/asm/arch-stih410/sdhci.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef __STI_SDHCI_H__ diff --git a/arch/arm/include/asm/arch-stih410/sys_proto.h b/arch/arm/include/asm/arch-stih410/sys_proto.h index f9e8d3704a8..30e7f398ebe 100644 --- a/arch/arm/include/asm/arch-stih410/sys_proto.h +++ b/arch/arm/include/asm/arch-stih410/sys_proto.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef _ASM_ARCH_SYS_PROTO_H diff --git a/arch/arm/include/asm/arch-stm32/stm32f.h b/arch/arm/include/asm/arch-stm32/stm32f.h index bd3f4fd30ae..a1ce81ecadd 100644 --- a/arch/arm/include/asm/arch-stm32/stm32f.h +++ b/arch/arm/include/asm/arch-stm32/stm32f.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef _ASM_ARCH_STM32F_H diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h index 8af6de220d8..fe6ca03d2df 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef __STM32_PWR_H_ diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h index 02faaeb663c..5cd6553d04d 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef __STM32_PWR_H_ diff --git a/arch/arm/include/asm/arch-stm32h7/gpio.h b/arch/arm/include/asm/arch-stm32h7/gpio.h index 2dad52a4002..4f57f175ff6 100644 --- a/arch/arm/include/asm/arch-stm32h7/gpio.h +++ b/arch/arm/include/asm/arch-stm32h7/gpio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef _STM32_GPIO_H_ diff --git a/arch/arm/include/asm/arch-stm32h7/stm32.h b/arch/arm/include/asm/arch-stm32h7/stm32.h index 458baca458b..2b0a6700080 100644 --- a/arch/arm/include/asm/arch-stm32h7/stm32.h +++ b/arch/arm/include/asm/arch-stm32h7/stm32.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef _ASM_ARCH_HARDWARE_H diff --git a/arch/arm/mach-stm32/soc.c b/arch/arm/mach-stm32/soc.c index 1f12da401c1..0bd8d7b22c4 100644 --- a/arch/arm/mach-stm32/soc.c +++ b/arch/arm/mach-stm32/soc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include -- cgit v1.3.1 From 845c6720eca92be09127f7d306349ab31dbf372d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 1 Dec 2020 11:29:17 +0100 Subject: ARM: dts: stm32: Enable internal pull-ups for SDMMC1 on DHCOM SoM The default state of SD bus and clock line is logical HI. SD card IO is open-drain and pulls the bus lines LO. Always enable the SD bus pull ups to guarantee this behavior on DHCOM SoM. Note that on SoMs with SD bus voltage level shifter, the pull ups are built into the level shifter, however that has no negative impact. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcom.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi index f022d8395c6..9049245c5ba 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi @@ -339,6 +339,20 @@ status = "okay"; }; +&sdmmc1_b4_pins_a { + /* + * SD bus pull-up resistors: + * - optional on SoMs with SD voltage translator + * - mandatory on SoMs without SD voltage translator + */ + pins1 { + bias-pull-up; + }; + pins2 { + bias-pull-up; + }; +}; + &sdmmc2 { pinctrl-names = "default"; pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; -- cgit v1.3.1 From 75df748b87f86e87a4393d8ebc274e5806f2079a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 1 Dec 2020 11:29:18 +0100 Subject: ARM: dts: stm32: Disable SDMMC1 CKIN feedback clock The STM32MP1 DHCOM SoM can be built with either bus voltage level shifter or without one on the SDMMC1 interface. Because the SDMMC1 interface is limited to 50 MHz and hence SD high-speed anyway, disable the SD feedback clock to permit operation of the same U-Boot image on both SoM with and without voltage level shifter. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcom.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi index 9049245c5ba..dafcce43239 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi @@ -333,7 +333,6 @@ disable-wp; st,sig-dir; st,neg-edge; - st,use-ckin; bus-width = <4>; vmmc-supply = <&vdd_sd>; status = "okay"; -- cgit v1.3.1 From 1399be91cb57a480d5ff7bb084b40b4787be9f22 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 1 Dec 2020 11:29:19 +0100 Subject: ARM: dts: stm32: Enable SDMMC3 on DH DRC02 The DH DRC02 board has an on-board microSD slot, add DT properties to enable the slot. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcom-drc02.dts | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts index 5a237a3b7bf..e8508aa4d5a 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts +++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts @@ -105,9 +105,18 @@ * On DRC02, the SoM does not have SDIO WiFi. The pins * are used for on-board microSD slot instead. */ - /delete-property/broken-cd; - cd-gpios = <&gpioi 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; + status = "okay"; }; &spi1 { -- cgit v1.3.1 From 9b36b7dc96baedc0ed506246a9822c745cc65b45 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 1 Dec 2020 11:29:20 +0100 Subject: ARM: dts: stm32: Add USB OTG ID pin on DH AV96 Add USB OTG ID pin mux and switch the USB OTG port from peripheral to OTG mode. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts index 88f25d89b22..9b5dda318ec 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts @@ -192,7 +192,8 @@ }; &usbotg_hs { - dr_mode = "peripheral"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; phys = <&usbphyc_port1 0>; phy-names = "usb2-phy"; status = "okay"; -- cgit v1.3.1