From 2b8dc36b4c515979da330a96d9fcc9bbbe5385fa Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Tue, 14 May 2024 17:50:11 +0800 Subject: andes: Unify naming policy for Andes related source Signed-off-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 4 +- arch/riscv/cpu/andes/Kconfig | 17 ++++++ arch/riscv/cpu/andes/Makefile | 8 +++ arch/riscv/cpu/andes/cache.c | 129 ++++++++++++++++++++++++++++++++++++++++ arch/riscv/cpu/andes/cpu.c | 64 ++++++++++++++++++++ arch/riscv/cpu/andes/spl.c | 26 ++++++++ arch/riscv/cpu/andesv5/Kconfig | 17 ------ arch/riscv/cpu/andesv5/Makefile | 8 --- arch/riscv/cpu/andesv5/cache.c | 129 ---------------------------------------- arch/riscv/cpu/andesv5/cpu.c | 64 -------------------- arch/riscv/cpu/andesv5/spl.c | 26 -------- 11 files changed, 246 insertions(+), 246 deletions(-) create mode 100644 arch/riscv/cpu/andes/Kconfig create mode 100644 arch/riscv/cpu/andes/Makefile create mode 100644 arch/riscv/cpu/andes/cache.c create mode 100644 arch/riscv/cpu/andes/cpu.c create mode 100644 arch/riscv/cpu/andes/spl.c delete mode 100644 arch/riscv/cpu/andesv5/Kconfig delete mode 100644 arch/riscv/cpu/andesv5/Makefile delete mode 100644 arch/riscv/cpu/andesv5/cache.c delete mode 100644 arch/riscv/cpu/andesv5/cpu.c delete mode 100644 arch/riscv/cpu/andesv5/spl.c (limited to 'arch') diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 7e20ef63bba..fa3b016c527 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -80,7 +80,7 @@ config SPL_ZERO_MEM_BEFORE_USE Sifive core devices that uses L2 cache to store SPL. # board-specific options below -source "board/AndesTech/ae350/Kconfig" +source "board/andestech/ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/openpiton/riscv64/Kconfig" @@ -93,7 +93,7 @@ source "board/thead/th1520_lpi4a/Kconfig" source "board/xilinx/mbv/Kconfig" # platform-specific options below -source "arch/riscv/cpu/andesv5/Kconfig" +source "arch/riscv/cpu/andes/Kconfig" source "arch/riscv/cpu/cv1800b/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" diff --git a/arch/riscv/cpu/andes/Kconfig b/arch/riscv/cpu/andes/Kconfig new file mode 100644 index 00000000000..120fec5e540 --- /dev/null +++ b/arch/riscv/cpu/andes/Kconfig @@ -0,0 +1,17 @@ +config RISCV_ANDES + bool + select ARCH_EARLY_INIT_R + select SYS_CACHE_SHIFT_6 + imply CPU + imply CPU_RISCV + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply ANDES_PLMT_TIMER + imply SPL_ANDES_PLMT_TIMER + imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE) + imply ANDES_L2_CACHE + imply SPL_CPU + imply SPL_OPENSBI + imply SPL_LOAD_FIT + help + Run U-Boot on AndeStar V5 platforms and use some specific features + which are provided by Andes Technology AndeStar V5 families. diff --git a/arch/riscv/cpu/andes/Makefile b/arch/riscv/cpu/andes/Makefile new file mode 100644 index 00000000000..35a1a2fb836 --- /dev/null +++ b/arch/riscv/cpu/andes/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2017 Andes Technology Corporation +# Rick Chen, Andes Technology Corporation + +obj-y := cpu.o +obj-y += cache.o +obj-y += spl.o diff --git a/arch/riscv/cpu/andes/cache.c b/arch/riscv/cpu/andes/cache.c new file mode 100644 index 00000000000..7d3df8722dd --- /dev/null +++ b/arch/riscv/cpu/andes/cache.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_ANDES_L2_CACHE +void enable_caches(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CACHE, + DM_DRIVER_GET(andes_l2_cache), + &dev); + if (ret) { + log_debug("Cannot enable Andes L2 cache\n"); + } else { + ret = cache_enable(dev); + if (ret) + log_debug("Failed to enable Andes L2 cache\n"); + } +} + +static void cache_ops(int (*ops)(struct udevice *dev)) +{ + struct udevice *dev = NULL; + + uclass_find_first_device(UCLASS_CACHE, &dev); + + if (dev) + ops(dev); +} +#endif + +void flush_dcache_all(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); +#endif +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + flush_dcache_all(); +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ + flush_dcache_all(); +} + +void icache_enable(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrsi %0, 0x1" :: "i"(CSR_MCACHE_CTL)); +#endif +} + +void icache_disable(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrci %0, 0x1" :: "i"(CSR_MCACHE_CTL)); +#endif +} + +void dcache_enable(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL)); +#endif + +#ifdef CONFIG_ANDES_L2_CACHE + cache_ops(cache_enable); +#endif +} + +void dcache_disable(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL)); +#endif + +#ifdef CONFIG_ANDES_L2_CACHE + cache_ops(cache_disable); +#endif +} + +int icache_status(void) +{ + int ret = 0; + +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile ( + "csrr t1, %1\n\t" + "andi %0, t1, 0x01\n\t" + : "=r" (ret) + : "i"(CSR_MCACHE_CTL) + : "memory" + ); +#endif + + return !!ret; +} + +int dcache_status(void) +{ + int ret = 0; + +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile ( + "csrr t1, %1\n\t" + "andi %0, t1, 0x02\n\t" + : "=r" (ret) + : "i" (CSR_MCACHE_CTL) + : "memory" + ); +#endif + + return !!ret; +} diff --git a/arch/riscv/cpu/andes/cpu.c b/arch/riscv/cpu/andes/cpu.c new file mode 100644 index 00000000000..d25ecba0e88 --- /dev/null +++ b/arch/riscv/cpu/andes/cpu.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ + +/* CPU specific code */ +#include +#include +#include +#include +#include + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + + cache_flush(); + + return 0; +} + +void harts_early_init(void) +{ + /* Enable I/D-cache in SPL */ + if (CONFIG_IS_ENABLED(RISCV_MMODE)) { + unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); + unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL); + + mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \ + MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \ + MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \ + MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN); + + if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF)) + mcache_ctl_val |= MCACHE_CTL_IC_EN; + + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + mcache_ctl_val |= (MCACHE_CTL_DC_EN | MCACHE_CTL_DC_COHEN); + + csr_write(CSR_MCACHE_CTL, mcache_ctl_val); + + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { + /* + * Check mcache_ctl.DC_COHEN, we assume this platform does + * not support CM if the bit is hard-wired to 0. + */ + if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) { + /* Wait for DC_COHSTA bit to be set */ + while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)); + } + } + + mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN; + + csr_write(CSR_MMISC_CTL, mmisc_ctl_val); + } +} diff --git a/arch/riscv/cpu/andes/spl.c b/arch/riscv/cpu/andes/spl.c new file mode 100644 index 00000000000..a13dc4095a4 --- /dev/null +++ b/arch/riscv/cpu/andes/spl.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if CONFIG_IS_ENABLED(RAM_SUPPORT) +struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) +{ + return (void *)(CONFIG_SPL_LOAD_FIT_ADDRESS + offset); +} + +void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) +{ + return spl_get_load_buffer(0, sectors * bl_len); +} +#endif diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andesv5/Kconfig deleted file mode 100644 index e3efb0de8f0..00000000000 --- a/arch/riscv/cpu/andesv5/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -config RISCV_NDS - bool - select ARCH_EARLY_INIT_R - select SYS_CACHE_SHIFT_6 - imply CPU - imply CPU_RISCV - imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) - imply ANDES_PLMT_TIMER - imply SPL_ANDES_PLMT_TIMER - imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE) - imply V5L2_CACHE - imply SPL_CPU - imply SPL_OPENSBI - imply SPL_LOAD_FIT - help - Run U-Boot on AndeStar V5 platforms and use some specific features - which are provided by Andes Technology AndeStar V5 families. diff --git a/arch/riscv/cpu/andesv5/Makefile b/arch/riscv/cpu/andesv5/Makefile deleted file mode 100644 index 35a1a2fb836..00000000000 --- a/arch/riscv/cpu/andesv5/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2017 Andes Technology Corporation -# Rick Chen, Andes Technology Corporation - -obj-y := cpu.o -obj-y += cache.o -obj-y += spl.o diff --git a/arch/riscv/cpu/andesv5/cache.c b/arch/riscv/cpu/andesv5/cache.c deleted file mode 100644 index 269bb27f75a..00000000000 --- a/arch/riscv/cpu/andesv5/cache.c +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2023 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ - -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_V5L2_CACHE -void enable_caches(void) -{ - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_CACHE, - DM_DRIVER_GET(v5l2_cache), - &dev); - if (ret) { - log_debug("Cannot enable v5l2 cache\n"); - } else { - ret = cache_enable(dev); - if (ret) - log_debug("v5l2 cache enable failed\n"); - } -} - -static void cache_ops(int (*ops)(struct udevice *dev)) -{ - struct udevice *dev = NULL; - - uclass_find_first_device(UCLASS_CACHE, &dev); - - if (dev) - ops(dev); -} -#endif - -void flush_dcache_all(void) -{ -#if CONFIG_IS_ENABLED(RISCV_MMODE) - csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); -#endif -} - -void flush_dcache_range(unsigned long start, unsigned long end) -{ - flush_dcache_all(); -} - -void invalidate_dcache_range(unsigned long start, unsigned long end) -{ - flush_dcache_all(); -} - -void icache_enable(void) -{ -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile("csrsi %0, 0x1" :: "i"(CSR_MCACHE_CTL)); -#endif -} - -void icache_disable(void) -{ -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile("csrci %0, 0x1" :: "i"(CSR_MCACHE_CTL)); -#endif -} - -void dcache_enable(void) -{ -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL)); -#endif - -#ifdef CONFIG_V5L2_CACHE - cache_ops(cache_enable); -#endif -} - -void dcache_disable(void) -{ -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL)); -#endif - -#ifdef CONFIG_V5L2_CACHE - cache_ops(cache_disable); -#endif -} - -int icache_status(void) -{ - int ret = 0; - -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, %1\n\t" - "andi %0, t1, 0x01\n\t" - : "=r" (ret) - : "i"(CSR_MCACHE_CTL) - : "memory" - ); -#endif - - return !!ret; -} - -int dcache_status(void) -{ - int ret = 0; - -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, %1\n\t" - "andi %0, t1, 0x02\n\t" - : "=r" (ret) - : "i" (CSR_MCACHE_CTL) - : "memory" - ); -#endif - - return !!ret; -} diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c deleted file mode 100644 index d25ecba0e88..00000000000 --- a/arch/riscv/cpu/andesv5/cpu.c +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2023 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ - -/* CPU specific code */ -#include -#include -#include -#include -#include - -/* - * cleanup_before_linux() is called just before we call linux - * it prepares the processor for linux - * - * we disable interrupt and caches. - */ -int cleanup_before_linux(void) -{ - disable_interrupts(); - - cache_flush(); - - return 0; -} - -void harts_early_init(void) -{ - /* Enable I/D-cache in SPL */ - if (CONFIG_IS_ENABLED(RISCV_MMODE)) { - unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); - unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL); - - mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \ - MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \ - MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \ - MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN); - - if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF)) - mcache_ctl_val |= MCACHE_CTL_IC_EN; - - if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) - mcache_ctl_val |= (MCACHE_CTL_DC_EN | MCACHE_CTL_DC_COHEN); - - csr_write(CSR_MCACHE_CTL, mcache_ctl_val); - - if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { - /* - * Check mcache_ctl.DC_COHEN, we assume this platform does - * not support CM if the bit is hard-wired to 0. - */ - if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) { - /* Wait for DC_COHSTA bit to be set */ - while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)); - } - } - - mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN; - - csr_write(CSR_MMISC_CTL, mmisc_ctl_val); - } -} diff --git a/arch/riscv/cpu/andesv5/spl.c b/arch/riscv/cpu/andesv5/spl.c deleted file mode 100644 index a13dc4095a4..00000000000 --- a/arch/riscv/cpu/andesv5/spl.c +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2023 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if CONFIG_IS_ENABLED(RAM_SUPPORT) -struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) -{ - return (void *)(CONFIG_SPL_LOAD_FIT_ADDRESS + offset); -} - -void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) -{ - return spl_get_load_buffer(0, sectors * bl_len); -} -#endif -- cgit v1.3.1