From 6478848d165b63293f7021db9b70ce25a1e1062c Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Fri, 15 Mar 2019 15:14:33 +0100 Subject: arm: asm: io.h: define readX_relaxed and writeX_relaxed This patch port the function readX_relaxed and writeX_relaxed from kernel 4.18. Signed-off-by: Philippe Reynes --- arch/arm/include/asm/io.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 12bc7fbe06e..e6d27b69f93 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -122,6 +122,27 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) #define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) #define readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; }) +/* + * Relaxed I/O memory access primitives. These follow the Device memory + * ordering rules but do not guarantee any ordering relative to Normal memory + * accesses. + */ +#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; }) +#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \ + __raw_readw(c)); __r; }) +#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ + __raw_readl(c)); __r; }) +#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \ + __raw_readq(c)); __r; }) + +#define writeb_relaxed(v, c) ((void)__raw_writeb((v), (c))) +#define writew_relaxed(v, c) ((void)__raw_writew((__force u16) \ + cpu_to_le16(v), (c))) +#define writel_relaxed(v, c) ((void)__raw_writel((__force u32) \ + cpu_to_le32(v), (c))) +#define writeq_relaxed(v, c) ((void)__raw_writeq((__force u64) \ + cpu_to_le64(v), (c))) + /* * The compiler seems to be incapable of optimising constants * properly. Spell it out to the compiler in some cases. -- cgit v1.3.1 From d8d9bfb90b772de28c2dea3a1e9338eb46ba42c2 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Fri, 15 Mar 2019 15:14:39 +0100 Subject: dt: bcm6838: add nand controller Add the nand controller in the bcm6838 device tree. Signed-off-by: Philippe Reynes --- arch/mips/dts/brcm,bcm6838.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch') diff --git a/arch/mips/dts/brcm,bcm6838.dtsi b/arch/mips/dts/brcm,bcm6838.dtsi index c060802e8a4..6676f83b2aa 100644 --- a/arch/mips/dts/brcm,bcm6838.dtsi +++ b/arch/mips/dts/brcm,bcm6838.dtsi @@ -125,5 +125,18 @@ status = "disabled"; }; + + nand: nand-controller@14e02200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm6838", + "brcm,brcmnand-v5.0", + "brcm,brcmnand"; + reg-names = "nand", "nand-int-base", "nand-cache"; + reg = <0x14e02200 0x180>, + <0x14e000f0 0x10>, + <0x14e02600 0x180>; + status = "disabled"; + }; }; }; -- cgit v1.3.1 From 92cd0047a9d4bbd2c0495a68c47c36075211dbaf Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Fri, 15 Mar 2019 15:14:40 +0100 Subject: dt: bcm968380gerg: enable nand controller Enable the nand controller in the device tree of the board bcm96838gerg. Signed-off-by: Philippe Reynes --- arch/mips/dts/brcm,bcm968380gerg.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/mips/dts/brcm,bcm968380gerg.dts b/arch/mips/dts/brcm,bcm968380gerg.dts index 98471e3894d..5a5ac0ea7d9 100644 --- a/arch/mips/dts/brcm,bcm968380gerg.dts +++ b/arch/mips/dts/brcm,bcm968380gerg.dts @@ -50,3 +50,15 @@ &gpio_mid1 { status = "okay"; }; + +&nand { + status = "okay"; + + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + brcm,nand-oob-sector-size = <16>; + }; +}; -- cgit v1.3.1 From 24e27a180ab7b253848a950c6991341a78704580 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Fri, 15 Mar 2019 15:14:42 +0100 Subject: dt: bcm6858: add nand controller Add the nand controller in the bcm6858 device tree. Signed-off-by: Philippe Reynes --- arch/arm/dts/bcm6858.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi index 5d5e64db081..8fd825b4c33 100644 --- a/arch/arm/dts/bcm6858.dtsi +++ b/arch/arm/dts/bcm6858.dtsi @@ -178,5 +178,18 @@ status = "disabled"; }; + + nand: nand-controller@ff801800 { + compatible = "brcm,nand-bcm6858", + "brcm,brcmnand-v5.0", + "brcm,brcmnand"; + reg-names = "nand", "nand-int-base", "nand-cache"; + reg = <0x0 0xff801800 0x0 0x180>, + <0x0 0xff802000 0x0 0x10>, + <0x0 0xff801c00 0x0 0x200>; + parameter-page-big-endian = <0>; + + status = "disabled"; + }; }; }; -- cgit v1.3.1 From 2463ad34b031911e14da4935e006d5c18bf9a8bd Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Fri, 15 Mar 2019 15:14:43 +0100 Subject: dt: bcm968580xref: enable nand controller Enable the nand controller in the device tree of the board bcm968580xref. Signed-off-by: Philippe Reynes --- arch/arm/dts/bcm968580xref.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/bcm968580xref.dts b/arch/arm/dts/bcm968580xref.dts index 15febb030f1..8ef9338d06f 100644 --- a/arch/arm/dts/bcm968580xref.dts +++ b/arch/arm/dts/bcm968580xref.dts @@ -61,3 +61,18 @@ &gpio7 { status = "okay"; }; + +&nand { + status = "okay"; + write-protect = <0>; + #address-cells = <1>; + #size-cells = <0>; + + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + brcm,nand-oob-sector-size = <16>; + }; +}; -- cgit v1.3.1 From 6242e9a82ab8c9707eebd6474cb7078a417a28a6 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Fri, 15 Mar 2019 15:14:45 +0100 Subject: dt: bcm63158: add nand controller Add the nand controller in the bcm63158 device tree. Signed-off-by: Philippe Reynes --- arch/arm/dts/bcm63158.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi index 4f41f627387..482da948706 100644 --- a/arch/arm/dts/bcm63158.dtsi +++ b/arch/arm/dts/bcm63158.dtsi @@ -178,5 +178,18 @@ status = "disabled"; }; + + nand: nand-controller@ff801800 { + compatible = "brcm,nand-bcm63158", + "brcm,brcmnand-v5.0", + "brcm,brcmnand"; + reg-names = "nand", "nand-int-base", "nand-cache"; + reg = <0x0 0xff801800 0x0 0x180>, + <0x0 0xff802000 0x0 0x10>, + <0x0 0xff801c00 0x0 0x200>; + parameter-page-big-endian = <0>; + + status = "disabled"; + }; }; }; -- cgit v1.3.1 From b2aa518a622c2416a8f9a5fe7da14afd0f23def2 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Fri, 15 Mar 2019 15:14:46 +0100 Subject: dt: bcm963158: enable nand controller Enable the nand controller in the device tree of the board bcm963158. Signed-off-by: Philippe Reynes --- arch/arm/dts/bcm963158.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/bcm963158.dts b/arch/arm/dts/bcm963158.dts index b5c825b052b..c318fbe04e3 100644 --- a/arch/arm/dts/bcm963158.dts +++ b/arch/arm/dts/bcm963158.dts @@ -61,3 +61,18 @@ &gpio7 { status = "okay"; }; + +&nand { + status = "okay"; + write-protect = <0>; + #address-cells = <1>; + #size-cells = <0>; + + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + brcm,nand-oob-sector-size = <16>; + }; +}; -- cgit v1.3.1 From f6b0115a966cc0f0eb816a1570ccd99dd5611b3f Mon Sep 17 00:00:00 2001 From: Chee Hong Ang Date: Tue, 12 Feb 2019 00:27:02 -0800 Subject: ARMv8: Allow SiP service extensions on top of PSCI code Allow PSCI layer to handle any SiP service functions added by platform vendors. PSCI layer will look for SiP service function in the SiP function table located in '._secure_svc_tbl_entries' section if the SMC function identifier is not found in the PSCI standard functions table. Use DECLARE_SECURE_SVC macro to declare and add platform specific SiP service function. This new section '._secure_svc_tbl_entries' is located next to '._secure.text' section. Refer to arch/arm/cpu/armv8/u-boot.lds. Signed-off-by: Chee Hong Ang --- arch/arm/cpu/armv8/psci.S | 33 +++++++++++++++++++++++++++------ arch/arm/cpu/armv8/u-boot.lds | 4 ++++ arch/arm/include/asm/secure.h | 31 +++++++++++++++++++++++++++++++ 3 files changed, 62 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S index 358df8fee9c..fc42d807b52 100644 --- a/arch/arm/cpu/armv8/psci.S +++ b/arch/arm/cpu/armv8/psci.S @@ -8,6 +8,7 @@ #include #include #include +#include /* Default PSCI function, return -1, Not Implemented */ #define PSCI_DEFAULT(__fn) \ @@ -147,18 +148,38 @@ handle_psci: 3: mov x0, #ARM_PSCI_RET_NI psci_return -unknown_smc_id: - ldr x0, =0xFFFFFFFF +/* + * Handle SiP service functions defined in SiP service function table. + * Use DECLARE_SECURE_SVC(_name, _id, _fn) to add platform specific SiP + * service function into the SiP service function table. + * SiP service function table is located in '._secure_svc_tbl_entries' section, + * which is next to '._secure.text' section. + */ +handle_svc: + adr x9, __secure_svc_tbl_start + adr x10, __secure_svc_tbl_end + subs x12, x10, x9 /* Get number of entries in table */ + b.eq 2f /* Make sure SiP function table is not empty */ + psci_enter +1: ldr x10, [x9] /* Load SiP function table */ + ldr x11, [x9, #8] + cmp w10, w0 + b.eq 2b /* SiP service function found */ + add x9, x9, #SECURE_SVC_TBL_OFFSET /* Move to next entry */ + subs x12, x12, #SECURE_SVC_TBL_OFFSET + b.eq 3b /* If reach the end, bail out */ + b 1b +2: ldr x0, =0xFFFFFFFF eret handle_smc32: /* SMC function ID 0x84000000-0x8400001F: 32 bits PSCI */ ldr w9, =0x8400001F cmp w0, w9 - b.gt unknown_smc_id + b.gt handle_svc ldr w9, =0x84000000 cmp w0, w9 - b.lt unknown_smc_id + b.lt handle_svc adr x9, _psci_32_table b handle_psci @@ -171,10 +192,10 @@ handle_smc64: /* SMC function ID 0xC4000000-0xC400001F: 64 bits PSCI */ ldr x9, =0xC400001F cmp x0, x9 - b.gt unknown_smc_id + b.gt handle_svc ldr x9, =0xC4000000 cmp x0, x9 - b.lt unknown_smc_id + b.lt handle_svc adr x9, _psci_64_table b handle_psci diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds index 53de80f745e..2554980595b 100644 --- a/arch/arm/cpu/armv8/u-boot.lds +++ b/arch/arm/cpu/armv8/u-boot.lds @@ -58,6 +58,10 @@ SECTIONS AT(ADDR(.__secure_start) + SIZEOF(.__secure_start)) { *(._secure.text) + . = ALIGN(8); + __secure_svc_tbl_start = .; + KEEP(*(._secure_svc_tbl_entries)) + __secure_svc_tbl_end = .; } .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text)) diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h index d23044a1c36..50582c972b7 100644 --- a/arch/arm/include/asm/secure.h +++ b/arch/arm/include/asm/secure.h @@ -6,6 +6,37 @@ #define __secure __attribute__ ((section ("._secure.text"))) #define __secure_data __attribute__ ((section ("._secure.data"))) +#ifndef __ASSEMBLY__ + +typedef struct secure_svc_tbl { + u32 id; +#ifdef CONFIG_ARMV8_PSCI + u8 pad[4]; +#endif + void *func; +} secure_svc_tbl_t; + +/* + * Macro to declare a SiP function service in '_secure_svc_tbl_entries' section + */ +#define DECLARE_SECURE_SVC(_name, _id, _fn) \ + static const secure_svc_tbl_t __secure_svc_ ## _name \ + __attribute__((used, section("._secure_svc_tbl_entries"))) \ + = { \ + .id = _id, \ + .func = _fn } + +#else + +#ifdef CONFIG_ARMV8_PSCI +#define SECURE_SVC_TBL_OFFSET 16 +#else +#define SECURE_SVC_TBL_OFFSET 8 + +#endif + +#endif /* __ASSEMBLY__ */ + #if defined(CONFIG_ARMV7_SECURE_BASE) || defined(CONFIG_ARMV8_SECURE_BASE) /* * Warning, horror ahead. -- cgit v1.3.1 From fd50eac9100e8dd04f657960f05a92a0d1a3f663 Mon Sep 17 00:00:00 2001 From: "Ang, Chee Hong" Date: Tue, 12 Feb 2019 00:27:03 -0800 Subject: ARMv8: Disable fwcall when PSCI is enabled When PSCI is enabled, we are expecting U-Boot which now act as EL3 software will handle all the PSCI calls. We won't need fwcall as no further HVC or SMC are needed. Signed-off-by: Ang, Chee Hong --- arch/arm/cpu/armv8/Makefile | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index a5f54330e38..b349b13f497 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -19,7 +19,9 @@ endif obj-y += cache.o obj-y += tlb.o obj-y += transition.o +ifndef CONFIG_ARMV8_PSCI obj-y += fwcall.o +endif obj-y += cpu-dt.o obj-$(CONFIG_ARM_SMCCC) += smccc-call.o -- cgit v1.3.1 From 1721b82c1f98f36d90e10cbd4c7f35209c0ac137 Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Mon, 25 Feb 2019 10:11:45 +0000 Subject: arm: fix hvc call HVC call makes use of 6 mandatory arguments rather than 7 in the same way as SMC calls. The 7th argument is optional (Client ID) for both HVC and SMC but is implemented as 16-bit parameter and register R7 or W7. The aim of this patch is just fix compilation error due to an invalid asm code in the HVC call so that's why the 7th argument is removed. The issue does not report any error in a normal build as hvc_call is not used at all and is optimized by the compiler. Using -O0 triggers the error so the patch is intended to fix issues on a ongoing effor to build U-Boot with -O0. Signed-off-by: Ibai Erkiaga --- arch/arm/cpu/armv8/fwcall.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c index 9957c2974bc..b0aca1b72a3 100644 --- a/arch/arm/cpu/armv8/fwcall.c +++ b/arch/arm/cpu/armv8/fwcall.c @@ -28,7 +28,6 @@ static void hvc_call(struct pt_regs *args) "ldr x4, %4\n" "ldr x5, %5\n" "ldr x6, %6\n" - "ldr x7, %7\n" "hvc #0\n" "str x0, %0\n" "str x1, %1\n" @@ -37,7 +36,7 @@ static void hvc_call(struct pt_regs *args) : "+m" (args->regs[0]), "+m" (args->regs[1]), "+m" (args->regs[2]), "+m" (args->regs[3]) : "m" (args->regs[4]), "m" (args->regs[5]), - "m" (args->regs[6]), "m" (args->regs[7]) + "m" (args->regs[6]) : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17"); -- cgit v1.3.1 From 98ffbb78e12646a1d06236ad6a1893217f255aae Mon Sep 17 00:00:00 2001 From: Ibai Erkiaga Date: Fri, 15 Mar 2019 12:18:41 +0000 Subject: arm: arm64 32bit address relocation Current relocation code is limited to 21bit PC-relative addressing which might not be enough for bigger code sizes. The following patch increases the addressing to 32bit PC-relative. This feature is specially interesting if U-Boot is build without optimiation (-O0) as the text section is increased significativelly. Signed-off-by: Ibai Erkiaga --- arch/arm/lib/relocate_64.S | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S index 7603f527748..26d29c5324a 100644 --- a/arch/arm/lib/relocate_64.S +++ b/arch/arm/lib/relocate_64.S @@ -26,9 +26,10 @@ ENTRY(relocate_code) /* * Copy u-boot from flash to RAM */ - adr x1, __image_copy_start /* x1 <- Run &__image_copy_start */ - subs x9, x0, x1 /* x8 <- Run to copy offset */ - b.eq relocate_done /* skip relocation */ + adrp x1, __image_copy_start /* x1 <- address bits [31:12] */ + add x1, x1, :lo12:__image_copy_start/* x1 <- address bits [11:00] */ + subs x9, x0, x1 /* x9 <- Run to copy offset */ + b.eq relocate_done /* skip relocation */ /* * Don't ldr x1, __image_copy_start here, since if the code is already * running at an address other than it was linked to, that instruction @@ -42,8 +43,10 @@ ENTRY(relocate_code) ldr x1, _TEXT_BASE /* x1 <- Linked &__image_copy_start */ subs x9, x0, x1 /* x9 <- Link to copy offset */ - adr x1, __image_copy_start /* x1 <- Run &__image_copy_start */ - adr x2, __image_copy_end /* x2 <- Run &__image_copy_end */ + adrp x1, __image_copy_start /* x1 <- address bits [31:12] */ + add x1, x1, :lo12:__image_copy_start/* x1 <- address bits [11:00] */ + adrp x2, __image_copy_end /* x2 <- address bits [31:12] */ + add x2, x2, :lo12:__image_copy_end /* x2 <- address bits [11:00] */ copy_loop: ldp x10, x11, [x1], #16 /* copy from source address [x1] */ stp x10, x11, [x0], #16 /* copy to target address [x0] */ @@ -54,8 +57,10 @@ copy_loop: /* * Fix .rela.dyn relocations */ - adr x2, __rel_dyn_start /* x2 <- Run &__rel_dyn_start */ - adr x3, __rel_dyn_end /* x3 <- Run &__rel_dyn_end */ + adrp x2, __rel_dyn_start /* x2 <- address bits [31:12] */ + add x2, x2, :lo12:__rel_dyn_start /* x2 <- address bits [11:00] */ + adrp x3, __rel_dyn_end /* x3 <- address bits [31:12] */ + add x3, x3, :lo12:__rel_dyn_end /* x3 <- address bits [11:00] */ fixloop: ldp x0, x1, [x2], #16 /* (x0,x1) <- (SRC location, fixup) */ ldr x4, [x2], #8 /* x4 <- addend */ -- cgit v1.3.1 From 7526582441c23e3a10765cf242dedecf34601661 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Fri, 22 Mar 2019 17:02:02 +0100 Subject: dt: bcm6858: add led controller Add the led controller in the bcm6858 device tree. Signed-off-by: Philippe Reynes --- arch/arm/dts/bcm6858.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi index 8fd825b4c33..76ba0ea1675 100644 --- a/arch/arm/dts/bcm6858.dtsi +++ b/arch/arm/dts/bcm6858.dtsi @@ -82,6 +82,13 @@ status = "disabled"; }; + leds: led-controller@ff800800 { + compatible = "brcm,bcm6858-leds"; + reg = <0x0 0xff800800 0x0 0xe4>; + + status = "disabled"; + }; + wdt1: watchdog@ff802780 { compatible = "brcm,bcm6345-wdt"; reg = <0x0 0xff802780 0x0 0x14>; -- cgit v1.3.1 From 96899219216c5740d2aac13fc72de510bb9dea73 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Fri, 22 Mar 2019 17:02:03 +0100 Subject: dt: bcm968580xref: enable led controller Enable the led controller in the device tree of the board bcm968580xref. Signed-off-by: Philippe Reynes --- arch/arm/dts/bcm968580xref.dts | 48 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/bcm968580xref.dts b/arch/arm/dts/bcm968580xref.dts index 8ef9338d06f..861e9891a78 100644 --- a/arch/arm/dts/bcm968580xref.dts +++ b/arch/arm/dts/bcm968580xref.dts @@ -76,3 +76,51 @@ brcm,nand-oob-sector-size = <16>; }; }; + +&leds { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + brcm,serial-led-en-pol; + brcm,serial-led-data-ppol; + + led@2 { + reg = <2>; + label = "green:inet"; + }; + + led@5 { + reg = <5>; + label = "red:alarm"; + }; + + led@8 { + reg = <8>; + label = "green:wlan_link"; + }; + + led@11 { + reg = <11>; + label = "green:fxs1"; + }; + + led@14 { + reg = <14>; + label = "green:fxs2"; + }; + + led@15 { + reg = <15>; + label = "green:usb0"; + }; + + led@16 { + reg = <16>; + label = "green:usb1"; + }; + + led@17 { + reg = <17>; + label = "green:wps"; + }; +}; -- cgit v1.3.1 From cfbb03be1c461e61fcbfccd7983a946e4a383c29 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Fri, 22 Mar 2019 17:02:06 +0100 Subject: dt: bcm63158: add led controller Add the led controller in the bcm63158 device tree. Signed-off-by: Philippe Reynes --- arch/arm/dts/bcm63158.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi index 482da948706..4b2eaeea2eb 100644 --- a/arch/arm/dts/bcm63158.dtsi +++ b/arch/arm/dts/bcm63158.dtsi @@ -82,6 +82,13 @@ status = "disabled"; }; + leds: led-controller@ff800800 { + compatible = "brcm,bcm6858-leds"; + reg = <0x0 0xff800800 0x0 0xe4>; + + status = "disabled"; + }; + wdt1: watchdog@ff800480 { compatible = "brcm,bcm6345-wdt"; reg = <0x0 0xff800480 0x0 0x14>; -- cgit v1.3.1 From 4ae0542de77f756a50d511bb2e3b3832a0fa97fa Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Fri, 22 Mar 2019 17:02:07 +0100 Subject: dt: bcm963158: enable led controller Enable the led controller in the device tree of the board bcm963158. Signed-off-by: Philippe Reynes --- arch/arm/dts/bcm963158.dts | 49 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/bcm963158.dts b/arch/arm/dts/bcm963158.dts index c318fbe04e3..85659440dae 100644 --- a/arch/arm/dts/bcm963158.dts +++ b/arch/arm/dts/bcm963158.dts @@ -76,3 +76,52 @@ brcm,nand-oob-sector-size = <16>; }; }; + +&leds { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + brcm,serial-led-en-pol; + brcm,serial-led-data-ppol; + + led@16 { + reg = <16>; + label = "red:dsl2"; + }; + + led@17 { + reg = <17>; + label = "green:dsl1"; + }; + + led@18 { + reg = <18>; + label = "green:fxs2"; + }; + + led@19 { + reg = <19>; + label = "green:fxs1"; + }; + + led@26 { + reg = <26>; + label = "green:wan1_act"; + }; + + led@27 { + reg = <27>; + label = "green:wps"; + }; + + led@28 { + reg = <28>; + active-low; + label = "green:aggregate_act"; + }; + + led@29 { + reg = <29>; + label = "green:aggregate_link"; + }; +}; -- cgit v1.3.1 From 7c798a11d499dbf5c1c12eedec6bd7299b906b2b Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 20 Mar 2019 15:32:41 +0800 Subject: poplar: enable Ethernet driver support The 'phy' reset of gmac device in kernel device tree is not generic enough for u-boot to use, so we need to overwrite the 'resets' property as needed. With this device tree fixup and poplar_defconfig changes, Ethernet starts working on Poplar board. Signed-off-by: Shawn Guo Acked-by: Joe Hershberger --- arch/arm/dts/hi3798cv200-u-boot.dtsi | 14 ++++++++++++++ configs/poplar_defconfig | 3 +++ 2 files changed, 17 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/hi3798cv200-u-boot.dtsi b/arch/arm/dts/hi3798cv200-u-boot.dtsi index 7844c5208c5..2de06d95291 100644 --- a/arch/arm/dts/hi3798cv200-u-boot.dtsi +++ b/arch/arm/dts/hi3798cv200-u-boot.dtsi @@ -8,7 +8,15 @@ * (C) Copyright 2017 Jorge Ramirez-Ortiz */ +#include + &soc { + rst: reset-controller@8a22000 { + compatible = "hisilicon,hi3798cv200-reset"; + reg = <0x8a22000 0x1000>; + #reset-cells = <3>; + }; + usb2: ehci@9890000 { compatible = "generic-ehci"; reg = <0x9890000 0x100>; @@ -16,6 +24,12 @@ }; }; +&gmac1 { + resets = <&rst 0xcc 9 ASSERT_SET>, + <&rst 0xcc 11 ASSERT_SET>, + <&rst 0xcc 13 DEASSERT_SET>; +}; + &uart0 { clock = <75000000>; status = "okay"; diff --git a/configs/poplar_defconfig b/configs/poplar_defconfig index 81bd3702e42..76ab5eb70e7 100644 --- a/configs/poplar_defconfig +++ b/configs/poplar_defconfig @@ -19,6 +19,9 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_DM_MMC=y CONFIG_MMC_DW=y CONFIG_MMC_DW_K3=y +CONFIG_DM_ETH=y +CONFIG_HIGMACV300_ETH=y +CONFIG_RESET_HISILICON=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y -- cgit v1.3.1 From def2fc05f6f47b883fa9de96275c0350bd31248e Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Sun, 24 Mar 2019 16:46:38 +0100 Subject: ARM: MediaTek: Add support for MT8516 SoC Add support for MediaTek MT8516 SoC. This include the file that will initialize the SoC after boot and its device tree. Signed-off-by: Fabien Parent Reviewed-by: Tom Rini --- arch/arm/dts/mt8516-u-boot.dtsi | 25 ++++++ arch/arm/dts/mt8516.dtsi | 136 +++++++++++++++++++++++++++++++++ arch/arm/mach-mediatek/Kconfig | 10 +++ arch/arm/mach-mediatek/Makefile | 1 + arch/arm/mach-mediatek/mt8516/Makefile | 3 + arch/arm/mach-mediatek/mt8516/init.c | 120 +++++++++++++++++++++++++++++ 6 files changed, 295 insertions(+) create mode 100644 arch/arm/dts/mt8516-u-boot.dtsi create mode 100644 arch/arm/dts/mt8516.dtsi create mode 100644 arch/arm/mach-mediatek/mt8516/Makefile create mode 100644 arch/arm/mach-mediatek/mt8516/init.c (limited to 'arch') diff --git a/arch/arm/dts/mt8516-u-boot.dtsi b/arch/arm/dts/mt8516-u-boot.dtsi new file mode 100644 index 00000000000..3c0d843f35e --- /dev/null +++ b/arch/arm/dts/mt8516-u-boot.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2019 BayLibre, SAS + * Author: Fabien Parent + */ + +&infracfg { + u-boot,dm-pre-reloc; +}; + +&topckgen_ { + u-boot,dm-pre-reloc; +}; + +&topckgen_cg { + u-boot,dm-pre-reloc; +}; + +&apmixedsys { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/mt8516.dtsi b/arch/arm/dts/mt8516.dtsi new file mode 100644 index 00000000000..1c335820861 --- /dev/null +++ b/arch/arm/dts/mt8516.dtsi @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2019 BayLibre, SAS + * Author: Fabien Parent + */ + +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt8516"; + interrupt-parent = <&sysirq>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "mediatek,mt8516-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0>; + clock-frequency = <1300000000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x1>; + clock-frequency = <1300000000>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x2>; + clock-frequency = <1300000000>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x3>; + clock-frequency = <1300000000>; + }; + }; + + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt8516-topckgen"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; + + topckgen_cg: clock-controller-cg@10000000 { + compatible = "mediatek,mt8516-topckgen-cg"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; + + infracfg: clock-controller@10001000 { + compatible = "mediatek,mt8516-infracfg"; + reg = <0x10001000 0x1000>; + #clock-cells = <1>; + }; + + apmixedsys: clock-controller@10018000 { + compatible = "mediatek,mt8516-apmixedsys"; + reg = <0x10018000 0x710>; + #clock-cells = <1>; + }; + + gic: interrupt-controller@10310000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10310000 0x1000>, + <0x10320000 0x1000>, + <0x10340000 0x2000>, + <0x10360000 0x2000>; + interrupts = ; + }; + + sysirq: interrupt-controller@10200620 { + compatible = "mediatek,sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10200620 0x20>; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,wdt"; + reg = <0x10007000 0x1000>; + interrupts = ; + #reset-cells = <1>; + status = "disabled"; + }; + + pinctrl: pinctrl@10005000 { + compatible = "mediatek,mt8516-pinctrl"; + reg = <0x10005000 0x1000>; + + gpio: gpio-controller { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + mmc0: mmc@11120000 { + compatible = "mediatek,mt8516-mmc"; + reg = <0x11120000 0x1000>; + interrupts = ; + clocks = <&topckgen_cg CLK_TOP_MSDC0>, + <&topckgen CLK_TOP_AHB_INFRA_SEL>, + <&topckgen_cg CLK_TOP_MSDC0_INFRA>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + uart0: serial@11005000 { + compatible = "mediatek,hsuart"; + reg = <0x11005000 0x1000>; + reg-shift = <2>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UART0_SEL>, + <&topckgen_cg CLK_TOP_UART0>; + clock-names = "baud","bus"; + status = "disabled"; + }; +}; diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 7a733e95df3..b5e91d4a7d4 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -31,6 +31,16 @@ config TARGET_MT7629 including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet, switch, USB3.0, PCIe, UART, SPI, I2C and PWM. +config TARGET_MT8516 + bool "MediaTek MT8516 SoC" + select ARM64 + select ARCH_MISC_INIT + help + The MediaTek MT8516 is a ARM64-based SoC with a quad-core Cortex-A35. + including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM, + Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo + chip and several DDR3 and DDR4 options. + endchoice source "board/mediatek/mt7623/Kconfig" diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index b5d3a379bcc..ea414dc407b 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_TARGET_MT7623) += mt7623/ obj-$(CONFIG_TARGET_MT7629) += mt7629/ +obj-$(CONFIG_TARGET_MT8516) += mt8516/ diff --git a/arch/arm/mach-mediatek/mt8516/Makefile b/arch/arm/mach-mediatek/mt8516/Makefile new file mode 100644 index 00000000000..886ab7e4eb9 --- /dev/null +++ b/arch/arm/mach-mediatek/mt8516/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o diff --git a/arch/arm/mach-mediatek/mt8516/init.c b/arch/arm/mach-mediatek/mt8516/init.c new file mode 100644 index 00000000000..26a215a8b1a --- /dev/null +++ b/arch/arm/mach-mediatek/mt8516/init.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Copyright (C) 2019 BayLibre, SAS + * Author: Fabien Parent + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define WDOG_SWRST 0x10007014 +#define WDOG_SWRST_KEY 0x1209 + +int dram_init(void) +{ + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + +int mtk_pll_early_init(void) +{ + unsigned long pll_rates[] = { + [CLK_APMIXED_ARMPLL] = 1300000000, + [CLK_APMIXED_MAINPLL] = 1501000000, + [CLK_APMIXED_UNIVPLL] = 1248000000, + [CLK_APMIXED_MMPLL] = 380000000, + }; + struct udevice *dev; + int ret, i; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(mtk_clk_apmixedsys), &dev); + if (ret) + return ret; + + /* configure default rate then enable apmixedsys */ + for (i = 0; i < ARRAY_SIZE(pll_rates); i++) { + struct clk clk = { .id = i, .dev = dev }; + + ret = clk_set_rate(&clk, pll_rates[i]); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + } + + return 0; +} + +int mtk_soc_early_init(void) +{ + int ret; + + /* initialize early clocks */ + ret = mtk_pll_early_init(); + if (ret) + return ret; + + return 0; +} + +void reset_cpu(ulong addr) +{ + while (1) { + writel(WDOG_SWRST_KEY, WDOG_SWRST); + mdelay(5); + } +} + +int print_cpuinfo(void) +{ + printf("CPU: MediaTek MT8516\n"); + return 0; +} + +static struct mm_region mt8516_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; +struct mm_region *mem_map = mt8516_mem_map; -- cgit v1.3.1 From 25c07c72fd817b084c128f84ea0862668ceb2127 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Thu, 4 Apr 2019 14:38:50 +0200 Subject: ARMv8: PSCI: Fix PSCI_TABLE relocation issue This fixes relaction isses with the PSCI_TABLE entries in the psci_32_table and psci_64_table. When using 32-bit adress pointers relocation was not being applied to the tables, causing PSCI handlers to point to the un-relocated code area. By using 64-bit data relocation is properly applied. The handlers are thus in the "secure data" area, which is protected by /memreserve/ in the FDT. Signed-off-by: Lars Povlsen --- arch/arm/cpu/armv8/psci.S | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S index fc42d807b52..7ffc8dbadbe 100644 --- a/arch/arm/cpu/armv8/psci.S +++ b/arch/arm/cpu/armv8/psci.S @@ -20,8 +20,8 @@ /* PSCI function and ID table definition*/ #define PSCI_TABLE(__id, __fn) \ - .word __id; \ - .word __fn + .quad __id; \ + .quad __fn .pushsection ._secure.text, "ax" @@ -133,16 +133,15 @@ PSCI_TABLE(0, 0) /* Caller must put PSCI function-ID table base in x9 */ handle_psci: psci_enter -1: ldr x10, [x9] /* Load PSCI function table */ - ubfx x11, x10, #32, #32 - ubfx x10, x10, #0, #32 +1: ldr x10, [x9] /* Load PSCI function table */ cbz x10, 3f /* If reach the end, bail out */ cmp x10, x0 b.eq 2f /* PSCI function found */ - add x9, x9, #8 /* If not match, try next entry */ + add x9, x9, #16 /* If not match, try next entry */ b 1b -2: blr x11 /* Call PSCI function */ +2: ldr x11, [x9, #8] /* Load PSCI function */ + blr x11 /* Call PSCI function */ psci_return 3: mov x0, #ARM_PSCI_RET_NI -- cgit v1.3.1