From 0d74bbfda38816dcb9b3e1b0fd63324849948443 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Wed, 13 Aug 2025 10:09:27 +0000 Subject: dts: th1520: Switch to upstream devicetree Imply OF_UPSTREAM in platform Kconfig option and adapt existing boards to use the correct upstream devicetree paths. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/th1520/Kconfig | 1 + arch/riscv/dts/Makefile | 1 - arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi | 10 + arch/riscv/dts/th1520-lichee-module-4a.dtsi | 164 ------- arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi | 27 ++ arch/riscv/dts/th1520-lichee-pi-4a.dts | 33 -- arch/riscv/dts/th1520-u-boot.dtsi | 44 ++ arch/riscv/dts/th1520.dtsi | 530 --------------------- 8 files changed, 82 insertions(+), 728 deletions(-) create mode 100644 arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi delete mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi delete mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts create mode 100644 arch/riscv/dts/th1520-u-boot.dtsi delete mode 100644 arch/riscv/dts/th1520.dtsi (limited to 'arch') diff --git a/arch/riscv/cpu/th1520/Kconfig b/arch/riscv/cpu/th1520/Kconfig index c73462c04b8..a02f5f24906 100644 --- a/arch/riscv/cpu/th1520/Kconfig +++ b/arch/riscv/cpu/th1520/Kconfig @@ -21,3 +21,4 @@ config THEAD_TH1520 imply SPL_CPU imply SPL_OPENSBI imply SPL_LOAD_FIT + imply OF_UPSTREAM diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index a637727b76b..9b347fc3b50 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -12,7 +12,6 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb -dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-binman.dtb diff --git a/arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi b/arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi new file mode 100644 index 00000000000..bbfa3c499cf --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Yao Zi + */ + +#include "th1520-u-boot.dtsi" + +&{/memory@0} { + bootph-pre-ram; +}; diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi deleted file mode 100644 index eecd3e9832a..00000000000 --- a/arch/riscv/dts/th1520-lichee-module-4a.dtsi +++ /dev/null @@ -1,164 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2023 Jisheng Zhang - */ - -/dts-v1/; - -#include "th1520.dtsi" - -/ { - model = "Sipeed Lichee Module 4A"; - compatible = "sipeed,lichee-module-4a", "thead,th1520"; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x2 0x00000000>; - bootph-pre-ram; - }; -}; - -&osc { - clock-frequency = <24000000>; -}; - -&osc_32k { - clock-frequency = <32768>; -}; - -&emmc { - bus-width = <8>; - max-frequency = <198000000>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - no-sdio; - no-sd; - status = "okay"; -}; - -&gmac0 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_pins>, <&mdio0_pins>; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&gmac1 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac1_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&mdio0 { - phy0: ethernet-phy@1 { - reg = <1>; - }; - - phy1: ethernet-phy@2 { - reg = <2>; - }; -}; - -&padctrl0_apsys { - gmac0_pins: gmac0-0 { - tx-pins { - pins = "GMAC0_TX_CLK", - "GMAC0_TXEN", - "GMAC0_TXD0", - "GMAC0_TXD1", - "GMAC0_TXD2", - "GMAC0_TXD3"; - function = "gmac0"; - bias-disable; - drive-strength = <25>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - - rx-pins { - pins = "GMAC0_RX_CLK", - "GMAC0_RXDV", - "GMAC0_RXD0", - "GMAC0_RXD1", - "GMAC0_RXD2", - "GMAC0_RXD3"; - function = "gmac0"; - bias-disable; - drive-strength = <1>; - input-enable; - input-schmitt-disable; - slew-rate = <0>; - }; - }; - - gmac1_pins: gmac1-0 { - tx-pins { - pins = "GPIO2_18", /* GMAC1_TX_CLK */ - "GPIO2_20", /* GMAC1_TXEN */ - "GPIO2_21", /* GMAC1_TXD0 */ - "GPIO2_22", /* GMAC1_TXD1 */ - "GPIO2_23", /* GMAC1_TXD2 */ - "GPIO2_24"; /* GMAC1_TXD3 */ - function = "gmac1"; - bias-disable; - drive-strength = <25>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - - rx-pins { - pins = "GPIO2_19", /* GMAC1_RX_CLK */ - "GPIO2_25", /* GMAC1_RXDV */ - "GPIO2_30", /* GMAC1_RXD0 */ - "GPIO2_31", /* GMAC1_RXD1 */ - "GPIO3_0", /* GMAC1_RXD2 */ - "GPIO3_1"; /* GMAC1_RXD3 */ - function = "gmac1"; - bias-disable; - drive-strength = <1>; - input-enable; - input-schmitt-disable; - slew-rate = <0>; - }; - }; - - mdio0_pins: mdio0-0 { - mdc-pins { - pins = "GMAC0_MDC"; - function = "gmac0"; - bias-disable; - drive-strength = <13>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - - mdio-pins { - pins = "GMAC0_MDIO"; - function = "gmac0"; - bias-disable; - drive-strength = <13>; - input-enable; - input-schmitt-enable; - slew-rate = <0>; - }; - }; -}; - -&sdio0 { - bus-width = <4>; - max-frequency = <198000000>; - status = "okay"; -}; diff --git a/arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi b/arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi new file mode 100644 index 00000000000..06d4a70d1ea --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Yao Zi + */ + +#include "th1520-lichee-module-4a-u-boot.dtsi" +#include "thead-th1520-binman.dtsi" + +&clk { + bootph-some-ram; +}; + +&padctrl0_apsys { + bootph-some-ram; +}; + +&uart0_pins { + bootph-some-ram; + + tx-pins { + bootph-some-ram; + }; + + rx-pins { + bootph-some-ram; + }; +}; diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts deleted file mode 100644 index 49af88b7adf..00000000000 --- a/arch/riscv/dts/th1520-lichee-pi-4a.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2023 Jisheng Zhang - */ - -#include "th1520-lichee-module-4a.dtsi" -#include "thead-th1520-binman.dtsi" - -/ { - model = "Sipeed Lichee Pi 4A"; - compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/riscv/dts/th1520-u-boot.dtsi b/arch/riscv/dts/th1520-u-boot.dtsi new file mode 100644 index 00000000000..45ffccbb847 --- /dev/null +++ b/arch/riscv/dts/th1520-u-boot.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Yao Zi + */ + +&{/soc} { + ddrc: ddrc@fffd000000 { + compatible = "thead,th1520-ddrc"; + reg = <0xff 0xfd000000 0x0 0x1000000>, + <0xff 0xfe000000 0x0 0x1000000>, + <0xff 0xff000000 0x0 0x4000>, + <0xff 0xff005000 0x0 0x1000>; + reg-names = "phy-0", "phy-1", "ctrl", "sys"; + bootph-pre-ram; + }; +}; + +&cpus { + bootph-pre-ram; +}; + +&c910_0 { + bootph-pre-ram; +}; + +&c910_1 { + bootph-pre-ram; +}; + +&c910_2 { + bootph-pre-ram; +}; + +&c910_3 { + bootph-pre-ram; +}; + +&clint { + bootph-pre-ram; +}; + +&uart0 { + bootph-pre-ram; +}; diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi deleted file mode 100644 index c46925a132a..00000000000 --- a/arch/riscv/dts/th1520.dtsi +++ /dev/null @@ -1,530 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - * Copyright (C) 2023 Jisheng Zhang - */ - -#include -#include - -/ { - compatible = "thead,th1520"; - #address-cells = <2>; - #size-cells = <2>; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - bootph-pre-ram; - timebase-frequency = <3000000>; - - c910_0: cpu@0 { - compatible = "thead,c910", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; - reg = <0>; - bootph-pre-ram; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; - d-cache-block-size = <64>; - d-cache-size = <65536>; - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; - - cpu0_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - c910_1: cpu@1 { - compatible = "thead,c910", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; - reg = <1>; - bootph-pre-ram; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; - d-cache-block-size = <64>; - d-cache-size = <65536>; - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; - - cpu1_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - c910_2: cpu@2 { - compatible = "thead,c910", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; - reg = <2>; - bootph-pre-ram; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; - d-cache-block-size = <64>; - d-cache-size = <65536>; - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; - - cpu2_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - c910_3: cpu@3 { - compatible = "thead,c910", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; - reg = <3>; - bootph-pre-ram; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; - d-cache-block-size = <64>; - d-cache-size = <65536>; - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; - - cpu3_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - l2_cache: l2-cache { - compatible = "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-size = <1048576>; - cache-sets = <1024>; - cache-unified; - }; - }; - - osc: oscillator { - compatible = "fixed-clock"; - clock-output-names = "osc_24m"; - #clock-cells = <0>; - }; - - osc_32k: 32k-oscillator { - compatible = "fixed-clock"; - clock-output-names = "osc_32k"; - #clock-cells = <0>; - }; - - aonsys_clk: clock-73728000 { - compatible = "fixed-clock"; - clock-frequency = <73728000>; - clock-output-names = "aonsys_clk"; - #clock-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&plic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - plic: interrupt-controller@ffd8000000 { - compatible = "thead,th1520-plic", "thead,c900-plic"; - reg = <0xff 0xd8000000 0x0 0x01000000>; - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, - <&cpu1_intc 11>, <&cpu1_intc 9>, - <&cpu2_intc 11>, <&cpu2_intc 9>, - <&cpu3_intc 11>, <&cpu3_intc 9>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <2>; - riscv,ndev = <240>; - }; - - clint: timer@ffdc000000 { - compatible = "thead,th1520-clint", "thead,c900-clint"; - reg = <0xff 0xdc000000 0x0 0x00010000>; - bootph-pre-ram; - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, - <&cpu1_intc 3>, <&cpu1_intc 7>, - <&cpu2_intc 3>, <&cpu2_intc 7>, - <&cpu3_intc 3>, <&cpu3_intc 7>; - }; - - uart0: serial@ffe7014000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7014000 0x0 0x100>; - bootph-pre-ram; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>; - clock-names = "buadclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - gmac1: ethernet@ffe7060000 { - compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; - reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; - reg-names = "dwmac", "apb"; - interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>; - clock-names = "stmmaceth", "pclk"; - snps,pbl = <32>; - snps,fixed-burst; - snps,multicast-filter-bins = <64>; - snps,perfect-filter-entries = <32>; - status = "disabled"; - - mdio1: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gmac0: ethernet@ffe7070000 { - compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; - reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>; - reg-names = "dwmac", "apb"; - interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>; - clock-names = "stmmaceth", "pclk"; - snps,pbl = <32>; - snps,fixed-burst; - snps,multicast-filter-bins = <64>; - snps,perfect-filter-entries = <32>; - status = "disabled"; - - mdio0: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - emmc: mmc@ffe7080000 { - compatible = "thead,th1520-dwcmshc"; - reg = <0xff 0xe7080000 0x0 0x10000>; - interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_EMMC_SDIO>; - clock-names = "core"; - status = "disabled"; - }; - - sdio0: mmc@ffe7090000 { - compatible = "thead,th1520-dwcmshc"; - reg = <0xff 0xe7090000 0x0 0x10000>; - interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_EMMC_SDIO>; - clock-names = "core"; - status = "disabled"; - }; - - sdio1: mmc@ffe70a0000 { - compatible = "thead,th1520-dwcmshc"; - reg = <0xff 0xe70a0000 0x0 0x10000>; - interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_EMMC_SDIO>; - clock-names = "core"; - status = "disabled"; - }; - - uart1: serial@ffe7f00000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7f00000 0x0 0x100>; - interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>; - clock-names = "buadclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart3: serial@ffe7f04000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7f04000 0x0 0x100>; - interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>; - clock-names = "buadclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - gpio2: gpio@ffe7f34000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xe7f34000 0x0 0x1000>; - clocks = <&clk CLK_GPIO2>; - clock-names = "bus"; - #address-cells = <1>; - #size-cells = <0>; - - portc: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio3: gpio@ffe7f38000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xe7f38000 0x0 0x1000>; - clocks = <&clk CLK_GPIO3>; - clock-names = "bus"; - #address-cells = <1>; - #size-cells = <0>; - - portd: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - padctrl1_apsys: pinctrl@ffe7f3c000 { - compatible = "thead,th1520-pinctrl"; - reg = <0xff 0xe7f3c000 0x0 0x1000>; - clocks = <&clk CLK_PADCTRL1>; - thead,pad-group = <2>; - }; - - gpio0: gpio@ffec005000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xec005000 0x0 0x1000>; - clocks = <&clk CLK_GPIO0>; - clock-names = "bus"; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio1: gpio@ffec006000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xec006000 0x0 0x1000>; - clocks = <&clk CLK_GPIO1>; - clock-names = "bus"; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - padctrl0_apsys: pinctrl@ffec007000 { - compatible = "thead,th1520-pinctrl"; - reg = <0xff 0xec007000 0x0 0x1000>; - clocks = <&clk CLK_PADCTRL0>; - thead,pad-group = <3>; - }; - - uart2: serial@ffec010000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xec010000 0x0 0x4000>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>; - clock-names = "buadclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - clk: clock-controller@ffef010000 { - compatible = "thead,th1520-clk-ap"; - reg = <0xff 0xef010000 0x0 0x1000>; - clocks = <&osc>; - #clock-cells = <1>; - }; - - timer0: timer@ffefc32000 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32000 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer1: timer@ffefc32014 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32014 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer2: timer@ffefc32028 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32028 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer3: timer@ffefc3203c { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc3203c 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - uart4: serial@fff7f08000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xf7f08000 0x0 0x4000>; - interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>; - clock-names = "buadclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart5: serial@fff7f0c000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xf7f0c000 0x0 0x4000>; - interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>; - clock-names = "buadclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - ddrc: ddrc@fffd000000 { - compatible = "thead,th1520-ddrc"; - reg = <0xff 0xfd000000 0x0 0x1000000>, - <0xff 0xfe000000 0x0 0x1000000>, - <0xff 0xff000000 0x0 0x4000>, - <0xff 0xff005000 0x0 0x1000>; - reg-names = "phy-0", "phy-1", "ctrl", "sys"; - bootph-pre-ram; - }; - - timer4: timer@ffffc33000 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33000 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer5: timer@ffffc33014 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33014 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer6: timer@ffffc33028 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33028 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer7: timer@ffffc3303c { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc3303c 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - ao_gpio0: gpio@fffff41000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xfff41000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - porte: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - padctrl_aosys: pinctrl@fffff4a000 { - compatible = "thead,th1520-pinctrl"; - reg = <0xff 0xfff4a000 0x0 0x2000>; - clocks = <&aonsys_clk>; - thead,pad-group = <1>; - }; - - ao_gpio1: gpio@fffff52000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xfff52000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - portf: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; -}; -- cgit v1.3.1 From fde7702c9b5a440fe86b4a8f35485f1920744ba7 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 2 Sep 2025 08:19:30 +0000 Subject: riscv: Add Kconfig options to distinguish Zaamo and Zalrsc Ratified on Apr. 2024, the original RISC-V "A" extension is now split into two separate extensions, "Zaamo" for atomic operations and "Zalrsc" for load-reserved/store-conditional instructions. For now, we've already seen real-world designs implement the Zalrsc extension only[2]. As U-Boot mainly runs with only one HART, we could easily support these designs by not using AMO instructions in the hard-written assembly if necessary, for which this patch introduces two new Kconfig options to indicate the availability of "Zaamo" and "Zalrsc". Note that even with this patch, "A" extension is specified in the ISA string passed to the compiler as long as one of "Zaamo" or "Zalrsc" is available, since they're only recognized with a quite recent version of GCC/Clang. The compiler usually doesn't automatically generate atomic instructions unless the source explicitly instructs it to do so, thus this should be safe. Link: https://github.com/riscv/riscv-zaamo-zalrsc/commit/d94c64c63e9120d56bdeb540caf2e5dae60a8126 # [1] Link: https://lore.kernel.org/u-boot/20250729162035.209849-9-uros.stajic@htecgroup.com/ # [2] Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 17 +++++++++++++++++ arch/riscv/Makefile | 7 ++++++- 2 files changed, 23 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 04eb0e6f23c..f0d2c904349 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -343,10 +343,27 @@ endmenu config RISCV_ISA_A bool "Standard extension for Atomic Instructions" + depends on RISCV_ISA_ZAAMO && RISCV_ISA_ZALRSC default y help Adds "A" to the ISA string passed to the compiler. +config RISCV_ISA_ZAAMO + bool "Standard extension for Atomic Memory Operations" + default y + help + Indicates the platform supports Zaamo extension for atomic memory + operations. Hand-written Assembly routines won't use AMO + instructions if set to n. + +config RISCV_ISA_ZALRSC + bool "Standard extension for LR/SC instructions" + default y + help + Indicates the platform supports Zalrsc extension for load-reserved + and store-conditional isntructions. Hand-written assembly routines + won't use LR/SC instructions if set to n. + config RISCV_ISA_ZICBOM bool "Zicbom support" depends on !SYS_DISABLE_DCACHE_OPS diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 6f80f4a7108..fdda6da1df3 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -11,7 +11,12 @@ ifeq ($(CONFIG_ARCH_RV32I),y) ARCH_BASE = rv32im ABI_BASE = ilp32 endif -ifeq ($(CONFIG_RISCV_ISA_A),y) +# GCC starts to recognize "Zaamo" and "Zalrsc" from version 15, which is quite +# recent. We don't bother checking the exact compiler version, but pass "A" +# extension for -march as long as one of "Zaamo" or "Zalrsc" is available. +ifeq ($(findstring y,$(CONFIG_RISCV_ISA_A) \ + $(CONFIG_RISCV_ISA_ZAAMO) \ + $(CONFIG_RISCV_ISA_ZALRSC)),y) ARCH_A = a endif ifeq ($(CONFIG_RISCV_ISA_F),y) -- cgit v1.3.1 From a681cfecb4346107212f377e2075f6eb1bdc6a2b Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 2 Sep 2025 08:19:32 +0000 Subject: riscv: Add a Zalrsc-only alternative for synchronization in start.S Add an alternative implementation that use Zalrsc extension only for HART lottery and SMP locking to support SMP on cores without "Zaamo" extension available. The Zaamo implementation is still prioritized if both of them are available, since it takes fewer instructions. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/start.S | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 7bafdfd390a..6324ff585d4 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -151,8 +151,15 @@ call_harts_early_init: */ la t0, hart_lottery li t1, 1 +#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO) amoswap.w s2, t1, 0(t0) bnez s2, wait_for_gd_init +#else + lr.w s2, (t0) + bnez s2, wait_for_gd_init + sc.w s2, t1, (t0) + bnez s2, wait_for_gd_init +#endif #else /* * FIXME: gp is set before it is initialized. If an XIP U-Boot ever @@ -177,7 +184,12 @@ call_harts_early_init: #if !CONFIG_IS_ENABLED(XIP) #ifdef CONFIG_AVAILABLE_HARTS la t0, available_harts_lock +#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO) amoswap.w.rl zero, zero, 0(t0) +#else + fence rw, w + sw zero, 0(t0) +#endif #endif wait_for_gd_init: @@ -190,7 +202,14 @@ wait_for_gd_init: #ifdef CONFIG_AVAILABLE_HARTS la t0, available_harts_lock li t1, 1 -1: amoswap.w.aq t1, t1, 0(t0) +1: +#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO) + amoswap.w.aq t1, t1, 0(t0) +#else + lr.w.aq t1, 0(t0) + bnez t1, 1b + sc.w.rl t1, t1, 0(t0) +#endif bnez t1, 1b /* register available harts in the available_harts mask */ @@ -200,7 +219,12 @@ wait_for_gd_init: or t2, t2, t1 SREG t2, GD_AVAILABLE_HARTS(gp) +#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO) amoswap.w.rl zero, zero, 0(t0) +#else + fence rw, w + sw zero, 0(t0) +#endif #endif /* -- cgit v1.3.1 From d141a41feb005a9f6a830006f1a4b66d1a3a3cd2 Mon Sep 17 00:00:00 2001 From: Jamie Gibbons Date: Tue, 2 Sep 2025 11:10:58 +0100 Subject: board: microchip: icicle: rename all icicle files to generic Make all Icicle Kit files generic. This supports the addition of upcoming support for other MPFS boards. Signed-off-by: Jamie Gibbons Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 6 +- board/microchip/mpfs_generic/Kconfig | 67 +++++++++ board/microchip/mpfs_generic/MAINTAINERS | 7 + board/microchip/mpfs_generic/Makefile | 7 + board/microchip/mpfs_generic/mpfs_generic.c | 204 ++++++++++++++++++++++++++++ board/microchip/mpfs_icicle/Kconfig | 67 --------- board/microchip/mpfs_icicle/MAINTAINERS | 7 - board/microchip/mpfs_icicle/Makefile | 7 - board/microchip/mpfs_icicle/mpfs_icicle.c | 204 ---------------------------- configs/microchip_mpfs_generic_defconfig | 29 ++++ configs/microchip_mpfs_icicle_defconfig | 29 ---- include/configs/microchip_mpfs_generic.h | 32 +++++ include/configs/microchip_mpfs_icicle.h | 32 ----- 13 files changed, 349 insertions(+), 349 deletions(-) create mode 100644 board/microchip/mpfs_generic/Kconfig create mode 100644 board/microchip/mpfs_generic/MAINTAINERS create mode 100644 board/microchip/mpfs_generic/Makefile create mode 100644 board/microchip/mpfs_generic/mpfs_generic.c delete mode 100644 board/microchip/mpfs_icicle/Kconfig delete mode 100644 board/microchip/mpfs_icicle/MAINTAINERS delete mode 100644 board/microchip/mpfs_icicle/Makefile delete mode 100644 board/microchip/mpfs_icicle/mpfs_icicle.c create mode 100644 configs/microchip_mpfs_generic_defconfig delete mode 100644 configs/microchip_mpfs_icicle_defconfig create mode 100644 include/configs/microchip_mpfs_generic.h delete mode 100644 include/configs/microchip_mpfs_icicle.h (limited to 'arch') diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f0d2c904349..265b5320777 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -23,8 +23,8 @@ config TARGET_K230_CANMV config TARGET_LICHEERV_NANO bool "Support LicheeRV Nano Board" -config TARGET_MICROCHIP_ICICLE - bool "Support Microchip PolarFire-SoC Icicle Board" +config TARGET_MICROCHIP_GENERIC + bool "Support Microchip PolarFire-SoC Boards" config TARGET_MILKV_DUO bool "Support Milk-v Duo Board" @@ -108,7 +108,7 @@ source "board/andestech/voyager/Kconfig" source "board/aspeed/ibex_ast2700/Kconfig" source "board/canaan/k230_canmv/Kconfig" source "board/emulation/qemu-riscv/Kconfig" -source "board/microchip/mpfs_icicle/Kconfig" +source "board/microchip/mpfs_generic/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" diff --git a/board/microchip/mpfs_generic/Kconfig b/board/microchip/mpfs_generic/Kconfig new file mode 100644 index 00000000000..8dcf55a0311 --- /dev/null +++ b/board/microchip/mpfs_generic/Kconfig @@ -0,0 +1,67 @@ +if TARGET_MICROCHIP_GENERIC + +config SYS_BOARD + default "mpfs_generic" + +config SYS_VENDOR + default "microchip" + +config SYS_CPU + default "generic" + +config SYS_CONFIG_NAME + default "microchip_mpfs_generic" + +config TEXT_BASE + default 0x80000000 if !RISCV_SMODE + default 0x80200000 if RISCV_SMODE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select GENERIC_RISCV + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + imply SMP + imply CLK_CCF + imply CLK_MPFS + imply REGMAP + imply SYSCON + imply SYS_NS16550 + imply CMD_DHCP + imply CMD_EXT2 + imply CMD_EXT4 + imply CMD_FAT + imply CMD_FS_GENERIC + imply CMD_NET + imply CMD_PING + imply CMD_MMC + imply DOS_PARTITION + imply EFI_PARTITION + imply IP_DYN + imply ISO_PARTITION + imply MACB + imply MII + imply PHY_LIB + imply PHY_VITESSE + imply MMC + imply MMC_WRITE + imply MMC_SDHCI + imply MMC_SDHCI_CADENCE + imply MMC_SDHCI_ADMA + imply MMC_HS200_SUPPORT + imply CMD_I2C + imply DM_I2C + imply SYS_I2C_MICROCHIP + imply MTD + imply SPI + imply DM_SPI + imply MICROCHIP_COREQSPI + imply MTD_SPI_NAND + imply CMD_MTD + imply CMD_MTDPARTS + imply DM_MAILBOX + imply MPFS_MBOX + imply MISC + imply MPFS_SYSCONTROLLER + +endif diff --git a/board/microchip/mpfs_generic/MAINTAINERS b/board/microchip/mpfs_generic/MAINTAINERS new file mode 100644 index 00000000000..3de99144c41 --- /dev/null +++ b/board/microchip/mpfs_generic/MAINTAINERS @@ -0,0 +1,7 @@ +Microchip MPFS Generic +M: Conor Dooley +M: Jamie Gibbons +S: Maintained +F: board/microchip/mpfs_generic/ +F: include/configs/microchip_mpfs_generic.h +F: configs/microchip_mpfs_generic_defconfig diff --git a/board/microchip/mpfs_generic/Makefile b/board/microchip/mpfs_generic/Makefile new file mode 100644 index 00000000000..dfe4b2634e6 --- /dev/null +++ b/board/microchip/mpfs_generic/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Microchip Technology Inc. +# Padmarao Begari +# + +obj-y += mpfs_generic.o diff --git a/board/microchip/mpfs_generic/mpfs_generic.c b/board/microchip/mpfs_generic/mpfs_generic.c new file mode 100644 index 00000000000..739a9b6cd76 --- /dev/null +++ b/board/microchip/mpfs_generic/mpfs_generic.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Microchip Technology Inc. + * Padmarao Begari + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) +#define PERIPH_RESET_VALUE 0x1e8u + +static unsigned char mac_addr[6]; + +#if defined(CONFIG_MULTI_DTB_FIT) +int board_fit_config_name_match(const char *name) +{ + const void *fdt; + int list_len; + + /* + * If there's not a HSS provided dtb, there's no point re-selecting + * since we'd just end up re-selecting the same dtb again. + */ + if (!gd->arch.firmware_fdt_addr) + return -EINVAL; + + fdt = (void *)gd->arch.firmware_fdt_addr; + + list_len = fdt_stringlist_count(fdt, 0, "compatible"); + if (list_len < 1) + return -EINVAL; + + for (int i = 0; i < list_len; i++) { + int len, match; + const char *compat; + char copy[64]; + char *devendored; + + compat = fdt_stringlist_get(fdt, 0, "compatible", i, &len); + if (!compat) + return -EINVAL; + + /* + * The naming scheme for compatibles doesn't produce anything + * close to this long. + */ + if (len >= 64) + return -EINVAL; + + strncpy(copy, compat, 64); + strtok(copy, ","); + + devendored = strtok(NULL, ","); + if (!devendored) + return -EINVAL; + + match = strcmp(devendored, name); + if (!match) + return 0; + } + + return -EINVAL; +} +#endif + +int board_fdt_blob_setup(void **fdtp) +{ + fdtp = (void *)_end; + + /* + * The devicetree provided by the previous stage is very minimal due to + * severe space constraints. The firmware performs no fixups etc. + * U-Boot, if providing a devicetree, almost certainly has a better + * more complete one than the firmware so that provided by the firmware + * is ignored for OF_SEPARATE. + */ + if (IS_ENABLED(CONFIG_OF_BOARD) && !IS_ENABLED(CONFIG_MULTI_DTB_FIT)) { + if (gd->arch.firmware_fdt_addr) + fdtp = (void *)(uintptr_t)gd->arch.firmware_fdt_addr; + } + + return 0; +} + +int board_init(void) +{ + /* For now nothing to do here. */ + + return 0; +} + +int board_early_init_f(void) +{ + unsigned int val; + + /* Reset uart, mmc peripheral */ + val = readl(MPFS_SYSREG_SOFT_RESET); + val = (val & ~(PERIPH_RESET_VALUE)); + writel(val, MPFS_SYSREG_SOFT_RESET); + + return 0; +} + +int board_late_init(void) +{ + u32 ret; + int node; + u8 device_serial_number[16] = {0}; + void *blob = (void *)gd->fdt_blob; + struct udevice *dev; + struct mpfs_sys_serv *sys_serv_priv; + + ret = uclass_get_device_by_name(UCLASS_MISC, "syscontroller", &dev); + if (ret) { + debug("%s: system controller setup failed\n", __func__); + return ret; + } + + sys_serv_priv = kzalloc(sizeof(*sys_serv_priv), GFP_KERNEL); + if (!sys_serv_priv) + return -ENOMEM; + + sys_serv_priv->dev = dev; + + sys_serv_priv->sys_controller = mpfs_syscontroller_get(dev); + ret = IS_ERR(sys_serv_priv->sys_controller); + if (ret) { + debug("%s: Failed to register system controller sub device ret=%d\n", __func__, ret); + return -ENODEV; + } + + ret = mpfs_syscontroller_read_sernum(sys_serv_priv, device_serial_number); + if (ret) { + printf("Cannot read device serial number\n"); + return -EINVAL; + } + + /* Update MAC address with device serial number */ + mac_addr[0] = 0x00; + mac_addr[1] = 0x04; + mac_addr[2] = 0xA3; + mac_addr[3] = device_serial_number[2]; + mac_addr[4] = device_serial_number[1]; + mac_addr[5] = device_serial_number[0]; + + node = fdt_path_offset(blob, "/soc/ethernet@20112000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20112000\n"); + return -ENODEV; + } + } + + mac_addr[5] = device_serial_number[0] + 1; + + node = fdt_path_offset(blob, "/soc/ethernet@20110000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20110000\n"); + return -ENODEV; + } + } + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u32 ret; + int node; + + node = fdt_path_offset(blob, "/soc/ethernet@20110000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20110000\n"); + return -ENODEV; + } + } + + mac_addr[5] -= 1; + + node = fdt_path_offset(blob, "/soc/ethernet@20112000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20112000\n"); + return -ENODEV; + } + } + + return 0; +} diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig deleted file mode 100644 index 760dffc488b..00000000000 --- a/board/microchip/mpfs_icicle/Kconfig +++ /dev/null @@ -1,67 +0,0 @@ -if TARGET_MICROCHIP_ICICLE - -config SYS_BOARD - default "mpfs_icicle" - -config SYS_VENDOR - default "microchip" - -config SYS_CPU - default "generic" - -config SYS_CONFIG_NAME - default "microchip_mpfs_icicle" - -config TEXT_BASE - default 0x80000000 if !RISCV_SMODE - default 0x80200000 if RISCV_SMODE - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select GENERIC_RISCV - select BOARD_EARLY_INIT_F - select BOARD_LATE_INIT - imply SMP - imply CLK_CCF - imply CLK_MPFS - imply REGMAP - imply SYSCON - imply SYS_NS16550 - imply CMD_DHCP - imply CMD_EXT2 - imply CMD_EXT4 - imply CMD_FAT - imply CMD_FS_GENERIC - imply CMD_NET - imply CMD_PING - imply CMD_MMC - imply DOS_PARTITION - imply EFI_PARTITION - imply IP_DYN - imply ISO_PARTITION - imply MACB - imply MII - imply PHY_LIB - imply PHY_VITESSE - imply MMC - imply MMC_WRITE - imply MMC_SDHCI - imply MMC_SDHCI_CADENCE - imply MMC_SDHCI_ADMA - imply MMC_HS200_SUPPORT - imply CMD_I2C - imply DM_I2C - imply SYS_I2C_MICROCHIP - imply MTD - imply SPI - imply DM_SPI - imply MICROCHIP_COREQSPI - imply MTD_SPI_NAND - imply CMD_MTD - imply CMD_MTDPARTS - imply DM_MAILBOX - imply MPFS_MBOX - imply MISC - imply MPFS_SYSCONTROLLER - -endif diff --git a/board/microchip/mpfs_icicle/MAINTAINERS b/board/microchip/mpfs_icicle/MAINTAINERS deleted file mode 100644 index d092b5a8111..00000000000 --- a/board/microchip/mpfs_icicle/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -Microchip MPFS icicle -M: Conor Dooley -M: Cyril Jean -S: Maintained -F: board/microchip/mpfs_icicle/ -F: include/configs/microchip_mpfs_icicle.h -F: configs/microchip_mpfs_icicle_defconfig diff --git a/board/microchip/mpfs_icicle/Makefile b/board/microchip/mpfs_icicle/Makefile deleted file mode 100644 index 72b0410dda8..00000000000 --- a/board/microchip/mpfs_icicle/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2019 Microchip Technology Inc. -# Padmarao Begari -# - -obj-y += mpfs_icicle.o diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c deleted file mode 100644 index 739a9b6cd76..00000000000 --- a/board/microchip/mpfs_icicle/mpfs_icicle.c +++ /dev/null @@ -1,204 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2019 Microchip Technology Inc. - * Padmarao Begari - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) -#define PERIPH_RESET_VALUE 0x1e8u - -static unsigned char mac_addr[6]; - -#if defined(CONFIG_MULTI_DTB_FIT) -int board_fit_config_name_match(const char *name) -{ - const void *fdt; - int list_len; - - /* - * If there's not a HSS provided dtb, there's no point re-selecting - * since we'd just end up re-selecting the same dtb again. - */ - if (!gd->arch.firmware_fdt_addr) - return -EINVAL; - - fdt = (void *)gd->arch.firmware_fdt_addr; - - list_len = fdt_stringlist_count(fdt, 0, "compatible"); - if (list_len < 1) - return -EINVAL; - - for (int i = 0; i < list_len; i++) { - int len, match; - const char *compat; - char copy[64]; - char *devendored; - - compat = fdt_stringlist_get(fdt, 0, "compatible", i, &len); - if (!compat) - return -EINVAL; - - /* - * The naming scheme for compatibles doesn't produce anything - * close to this long. - */ - if (len >= 64) - return -EINVAL; - - strncpy(copy, compat, 64); - strtok(copy, ","); - - devendored = strtok(NULL, ","); - if (!devendored) - return -EINVAL; - - match = strcmp(devendored, name); - if (!match) - return 0; - } - - return -EINVAL; -} -#endif - -int board_fdt_blob_setup(void **fdtp) -{ - fdtp = (void *)_end; - - /* - * The devicetree provided by the previous stage is very minimal due to - * severe space constraints. The firmware performs no fixups etc. - * U-Boot, if providing a devicetree, almost certainly has a better - * more complete one than the firmware so that provided by the firmware - * is ignored for OF_SEPARATE. - */ - if (IS_ENABLED(CONFIG_OF_BOARD) && !IS_ENABLED(CONFIG_MULTI_DTB_FIT)) { - if (gd->arch.firmware_fdt_addr) - fdtp = (void *)(uintptr_t)gd->arch.firmware_fdt_addr; - } - - return 0; -} - -int board_init(void) -{ - /* For now nothing to do here. */ - - return 0; -} - -int board_early_init_f(void) -{ - unsigned int val; - - /* Reset uart, mmc peripheral */ - val = readl(MPFS_SYSREG_SOFT_RESET); - val = (val & ~(PERIPH_RESET_VALUE)); - writel(val, MPFS_SYSREG_SOFT_RESET); - - return 0; -} - -int board_late_init(void) -{ - u32 ret; - int node; - u8 device_serial_number[16] = {0}; - void *blob = (void *)gd->fdt_blob; - struct udevice *dev; - struct mpfs_sys_serv *sys_serv_priv; - - ret = uclass_get_device_by_name(UCLASS_MISC, "syscontroller", &dev); - if (ret) { - debug("%s: system controller setup failed\n", __func__); - return ret; - } - - sys_serv_priv = kzalloc(sizeof(*sys_serv_priv), GFP_KERNEL); - if (!sys_serv_priv) - return -ENOMEM; - - sys_serv_priv->dev = dev; - - sys_serv_priv->sys_controller = mpfs_syscontroller_get(dev); - ret = IS_ERR(sys_serv_priv->sys_controller); - if (ret) { - debug("%s: Failed to register system controller sub device ret=%d\n", __func__, ret); - return -ENODEV; - } - - ret = mpfs_syscontroller_read_sernum(sys_serv_priv, device_serial_number); - if (ret) { - printf("Cannot read device serial number\n"); - return -EINVAL; - } - - /* Update MAC address with device serial number */ - mac_addr[0] = 0x00; - mac_addr[1] = 0x04; - mac_addr[2] = 0xA3; - mac_addr[3] = device_serial_number[2]; - mac_addr[4] = device_serial_number[1]; - mac_addr[5] = device_serial_number[0]; - - node = fdt_path_offset(blob, "/soc/ethernet@20112000"); - if (node >= 0) { - ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); - if (ret) { - printf("Error setting local-mac-address property for ethernet@20112000\n"); - return -ENODEV; - } - } - - mac_addr[5] = device_serial_number[0] + 1; - - node = fdt_path_offset(blob, "/soc/ethernet@20110000"); - if (node >= 0) { - ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); - if (ret) { - printf("Error setting local-mac-address property for ethernet@20110000\n"); - return -ENODEV; - } - } - - return 0; -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - u32 ret; - int node; - - node = fdt_path_offset(blob, "/soc/ethernet@20110000"); - if (node >= 0) { - ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); - if (ret) { - printf("Error setting local-mac-address property for ethernet@20110000\n"); - return -ENODEV; - } - } - - mac_addr[5] -= 1; - - node = fdt_path_offset(blob, "/soc/ethernet@20112000"); - if (node >= 0) { - ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); - if (ret) { - printf("Error setting local-mac-address property for ethernet@20112000\n"); - return -ENODEV; - } - } - - return 0; -} diff --git a/configs/microchip_mpfs_generic_defconfig b/configs/microchip_mpfs_generic_defconfig new file mode 100644 index 00000000000..0ed0cae93eb --- /dev/null +++ b/configs/microchip_mpfs_generic_defconfig @@ -0,0 +1,29 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="microchip/mpfs-icicle-kit" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_LOAD_ADDR=0x80200000 +CONFIG_SYS_MEM_TOP_HIDE=0x400000 +# CONFIG_DEBUG_UART is not set +CONFIG_TARGET_MICROCHIP_GENERIC=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="microchip/mpfs-icicle-kit.dtb" +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_OF_UPSTREAM=y +CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_DM_MTD=y +CONFIG_SYSRESET=y diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig deleted file mode 100644 index 9f933592c9d..00000000000 --- a/configs/microchip_mpfs_icicle_defconfig +++ /dev/null @@ -1,29 +0,0 @@ -CONFIG_RISCV=y -CONFIG_SYS_MALLOC_LEN=0x800000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_DEFAULT_DEVICE_TREE="microchip/mpfs-icicle-kit" -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SYS_LOAD_ADDR=0x80200000 -CONFIG_SYS_MEM_TOP_HIDE=0x400000 -# CONFIG_DEBUG_UART is not set -CONFIG_TARGET_MICROCHIP_ICICLE=y -CONFIG_ARCH_RV64I=y -CONFIG_RISCV_SMODE=y -CONFIG_FIT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_DEFAULT_FDT_FILE="microchip/mpfs-icicle-kit.dtb" -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=282 -CONFIG_DISPLAY_CPUINFO=y -CONFIG_DISPLAY_BOARDINFO=y -CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_OF_UPSTREAM=y -CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y -CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_BOOTP_SEND_HOSTNAME=y -CONFIG_DM_MTD=y -CONFIG_SYSRESET=y diff --git a/include/configs/microchip_mpfs_generic.h b/include/configs/microchip_mpfs_generic.h new file mode 100644 index 00000000000..0077f6a5f95 --- /dev/null +++ b/include/configs/microchip_mpfs_generic.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Microchip Technology Inc. + * Padmarao Begari + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CFG_SYS_SDRAM_BASE 0x80000000 + +/* Environment options */ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) + +#include + +#define CFG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x84000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "scriptaddr=0x88100000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + BOOTENV + +#endif /* __CONFIG_H */ diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h deleted file mode 100644 index 0077f6a5f95..00000000000 --- a/include/configs/microchip_mpfs_icicle.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2019 Microchip Technology Inc. - * Padmarao Begari - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CFG_SYS_SDRAM_BASE 0x80000000 - -/* Environment options */ - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) - -#include - -#define CFG_EXTRA_ENV_SETTINGS \ - "bootm_size=0x10000000\0" \ - "kernel_addr_r=0x84000000\0" \ - "fdt_addr_r=0x88000000\0" \ - "scriptaddr=0x88100000\0" \ - "pxefile_addr_r=0x88200000\0" \ - "ramdisk_addr_r=0x88300000\0" \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - BOOTENV - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 36d9587fa8b3590ae07ca16a2fe2aa6c905fc102 Mon Sep 17 00:00:00 2001 From: Greentime Hu Date: Mon, 15 Sep 2025 15:44:27 +0800 Subject: arch/riscv: Remove unused macro in encoding.h This patch remove the unused macro DRAM_BASE. Signed-off-by: Greentime Hu Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/include/asm/encoding.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index 56c5da86e86..ae3e5bce5c1 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -95,7 +95,6 @@ #define DEFAULT_MTVEC 0x00001010 #define CFG_STRING_ADDR 0x0000100C #define EXT_IO_BASE 0x40000000 -#define DRAM_BASE 0x80000000 // page table entry (PTE) fields #define PTE_V 0x001 // Valid -- cgit v1.3.1 From 27f617019dd070cb61f220c67244be834065aa30 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Tue, 16 Sep 2025 17:02:22 -0700 Subject: riscv: dts: starfive: prune redundant jh7110-common overrides Prune jh7110-common-u-boot.dtsi (clocks, qspi flash, eeprom, and bootph-pre-ram hints now upstream since devicetree-rebasing v6.16). In preparation for removal of per-dts jh7110-*-u-boot.dtsi replace include by next dependency jh7110-u-boot.dtsi in automatic dtsi inclusion order. Signed-off-by: E Shattow Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/jh7110-common-u-boot.dtsi | 99 ---------------------- .../dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi | 2 +- arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi | 2 +- arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi | 2 +- .../jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi | 2 +- .../jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi | 2 +- 6 files changed, 5 insertions(+), 104 deletions(-) delete mode 100644 arch/riscv/dts/jh7110-common-u-boot.dtsi (limited to 'arch') diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi deleted file mode 100644 index 049b0a7ce28..00000000000 --- a/arch/riscv/dts/jh7110-common-u-boot.dtsi +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2023 StarFive Technology Co., Ltd. - */ - -#include "jh7110-u-boot.dtsi" -/ { - aliases { - spi0 = &qspi; - }; - - chosen { - bootph-pre-ram; - }; - - firmware { - spi0 = &qspi; - bootph-pre-ram; - }; - - memory@40000000 { - bootph-pre-ram; - }; -}; - -&uart0 { - bootph-pre-ram; - reg-offset = <0>; - current-speed = <115200>; -}; - -&mmc0 { - bootph-pre-ram; -}; - -&mmc1 { - bootph-pre-ram; -}; - -&qspi { - bootph-pre-ram; - - flash@0 { - bootph-pre-ram; - cdns,read-delay = <2>; - spi-max-frequency = <100000000>; - }; -}; - -&syscrg { - assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, - <&syscrg JH7110_SYSCLK_BUS_ROOT>, - <&syscrg JH7110_SYSCLK_PERH_ROOT>, - <&syscrg JH7110_SYSCLK_QSPI_REF>; - assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>, - <&pllclk JH7110_PLLCLK_PLL2_OUT>, - <&pllclk JH7110_PLLCLK_PLL2_OUT>, - <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; - assigned-clock-rates = <0>, <0>, <0>, <0>; -}; - -&sysgpio { - bootph-pre-ram; -}; - -&mmc0_pins { - bootph-pre-ram; - rst-pins { - bootph-pre-ram; - }; -}; - -&mmc1_pins { - bootph-pre-ram; - clk-pins { - bootph-pre-ram; - }; - - mmc-pins { - bootph-pre-ram; - }; -}; - -&i2c5_pins { - bootph-pre-ram; - i2c-pins { - bootph-pre-ram; - }; -}; - -&i2c5 { - bootph-pre-ram; - eeprom@50 { - bootph-pre-ram; - compatible = "atmel,24c04"; - reg = <0x50>; - pagesize = <16>; - }; -}; diff --git a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi index ab882d07f6f..b9202f2acce 100644 --- a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi @@ -3,5 +3,5 @@ * Copyright (C) 2024 StarFive Technology Co., Ltd. */ -#include "jh7110-common-u-boot.dtsi" +#include "jh7110-u-boot.dtsi" #include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi index ab882d07f6f..b9202f2acce 100644 --- a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi @@ -3,5 +3,5 @@ * Copyright (C) 2024 StarFive Technology Co., Ltd. */ -#include "jh7110-common-u-boot.dtsi" +#include "jh7110-u-boot.dtsi" #include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi index ab882d07f6f..b9202f2acce 100644 --- a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi @@ -3,5 +3,5 @@ * Copyright (C) 2024 StarFive Technology Co., Ltd. */ -#include "jh7110-common-u-boot.dtsi" +#include "jh7110-u-boot.dtsi" #include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi index ab882d07f6f..b9202f2acce 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi @@ -3,5 +3,5 @@ * Copyright (C) 2024 StarFive Technology Co., Ltd. */ -#include "jh7110-common-u-boot.dtsi" +#include "jh7110-u-boot.dtsi" #include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi index 874074174ff..848ed8225ac 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi @@ -3,5 +3,5 @@ * Copyright (C) 2023 StarFive Technology Co., Ltd. */ -#include "jh7110-common-u-boot.dtsi" +#include "jh7110-u-boot.dtsi" #include "starfive-visionfive2-binman.dtsi" -- cgit v1.3.1 From 3e6d5b205d11eae088945c7aed838f281621e353 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Tue, 16 Sep 2025 17:02:23 -0700 Subject: riscv: dts: starfive: sync visionfive2 overrides with upstream Linux for-next Sync automatic dtsi inclusion overrides for JH7110 CPU with upstream "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader" from upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21 Signed-off-by: E Shattow Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/jh7110-u-boot.dtsi | 81 +++++++++++++++------------------------ 1 file changed, 31 insertions(+), 50 deletions(-) (limited to 'arch') diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index f8d13277d24..cc27dd648f8 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -3,36 +3,10 @@ * Copyright (C) 2022 StarFive Technology Co., Ltd. */ -#include - -/ { - timer { - compatible = "riscv,timer"; - interrupts-extended = <&cpu0_intc 5>, - <&cpu1_intc 5>, - <&cpu2_intc 5>, - <&cpu3_intc 5>, - <&cpu4_intc 5>; - }; +// BEGIN "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader" +// From upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21 - soc { - bootph-pre-ram; - - dmc: dmc@15700000 { - bootph-pre-ram; - compatible = "starfive,jh7110-dmc"; - reg = <0x0 0x15700000 0x0 0x10000>, - <0x0 0x13000000 0x0 0x10000>; - resets = <&syscrg JH7110_SYSRST_DDR_AXI>, - <&syscrg JH7110_SYSRST_DDR_OSC>, - <&syscrg JH7110_SYSRST_DDR_APB>; - reset-names = "axi", "osc", "apb"; - clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; - clock-names = "pll1_out"; - clock-frequency = <2133>; - }; - }; -}; +#include &clint { bootph-pre-ram; @@ -58,22 +32,10 @@ bootph-pre-ram; }; -&cpus { - bootph-pre-ram; -}; - &osc { bootph-pre-ram; }; -&gmac0_rgmii_rxin { - bootph-pre-ram; -}; - -&gmac0_rmii_refin { - bootph-pre-ram; -}; - &gmac1_rgmii_rxin { bootph-pre-ram; }; @@ -82,23 +44,42 @@ bootph-pre-ram; }; -&aoncrg { - bootph-pre-ram; +/ { + soc { + memory-controller@15700000 { + compatible = "starfive,jh7110-dmc"; + reg = <0x0 0x15700000 0x0 0x10000>, + <0x0 0x13000000 0x0 0x10000>; + bootph-pre-ram; + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; + clock-names = "pll"; + resets = <&syscrg JH7110_SYSRST_DDR_AXI>, + <&syscrg JH7110_SYSRST_DDR_OSC>, + <&syscrg JH7110_SYSRST_DDR_APB>; + reset-names = "axi", "osc", "apb"; + }; + }; }; -&pllclk { +&syscrg { bootph-pre-ram; }; -&syscrg { - assigned-clock-rates = <0>; /* cpufreq not implemented, use defaults */ +&pllclk { bootph-pre-ram; }; -&stgcrg { - bootph-pre-ram; +// END "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader" + +/ { + soc { + memory-controller@15700000 { + clock-frequency = <2133>; /* FIXME: delete property and implement CCF */ + }; + }; }; -&sys_syscon { - bootph-pre-ram; +&syscrg { + assigned-clock-rates = <0>; /* FIXME: delete property and implement cpufreq */ }; + -- cgit v1.3.1 From b8732d30a44412a346e2ef8c8c541fce8b00b364 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Tue, 16 Sep 2025 17:02:24 -0700 Subject: riscv: dts: starfive: visionfive2 depend on SYS_CPU automatic dtsi inclusion Drop visionfive2 per-board -u-boot.dtsi stubs and instead rely on automatic inclusion of jh7110-u-boot.dtsi Signed-off-by: E Shattow Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi | 7 ------- arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi | 7 ------- arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi | 7 ------- arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi | 7 ------- arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi | 7 ------- arch/riscv/dts/jh7110-u-boot.dtsi | 1 + 6 files changed, 1 insertion(+), 35 deletions(-) delete mode 100644 arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi delete mode 100644 arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi delete mode 100644 arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi (limited to 'arch') diff --git a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi deleted file mode 100644 index b9202f2acce..00000000000 --- a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2024 StarFive Technology Co., Ltd. - */ - -#include "jh7110-u-boot.dtsi" -#include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi deleted file mode 100644 index b9202f2acce..00000000000 --- a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2024 StarFive Technology Co., Ltd. - */ - -#include "jh7110-u-boot.dtsi" -#include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi deleted file mode 100644 index b9202f2acce..00000000000 --- a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2024 StarFive Technology Co., Ltd. - */ - -#include "jh7110-u-boot.dtsi" -#include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi deleted file mode 100644 index b9202f2acce..00000000000 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2024 StarFive Technology Co., Ltd. - */ - -#include "jh7110-u-boot.dtsi" -#include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi deleted file mode 100644 index 848ed8225ac..00000000000 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2023 StarFive Technology Co., Ltd. - */ - -#include "jh7110-u-boot.dtsi" -#include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index cc27dd648f8..0e5dc3685b2 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -83,3 +83,4 @@ assigned-clock-rates = <0>; /* FIXME: delete property and implement cpufreq */ }; +#include "starfive-visionfive2-binman.dtsi" -- cgit v1.3.1 From 10fdc2735da3a4825a5172056090eaf41e061627 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Tue, 16 Sep 2025 17:02:25 -0700 Subject: configs: starfive: Use visionfive2 DEVICE_TREE_INCLUDES dtsi named similar to defconfig Add SYS_CPU automatic inclusion jh7110-u-boot.dtsi to item of config list DEVICE_TREE_INCLUDES as starfive-visionfive2-u-boot.dtsi and rename file. Signed-off-by: E Shattow Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/jh7110-u-boot.dtsi | 86 ------------------------- arch/riscv/dts/starfive-visionfive2-u-boot.dtsi | 86 +++++++++++++++++++++++++ configs/starfive_visionfive2_defconfig | 1 + 3 files changed, 87 insertions(+), 86 deletions(-) delete mode 100644 arch/riscv/dts/jh7110-u-boot.dtsi create mode 100644 arch/riscv/dts/starfive-visionfive2-u-boot.dtsi (limited to 'arch') diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi deleted file mode 100644 index 0e5dc3685b2..00000000000 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - */ - -// BEGIN "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader" -// From upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21 - -#include - -&clint { - bootph-pre-ram; -}; - -&cpu0_intc { - bootph-pre-ram; -}; - -&cpu1_intc { - bootph-pre-ram; -}; - -&cpu2_intc { - bootph-pre-ram; -}; - -&cpu3_intc { - bootph-pre-ram; -}; - -&cpu4_intc { - bootph-pre-ram; -}; - -&osc { - bootph-pre-ram; -}; - -&gmac1_rgmii_rxin { - bootph-pre-ram; -}; - -&gmac1_rmii_refin { - bootph-pre-ram; -}; - -/ { - soc { - memory-controller@15700000 { - compatible = "starfive,jh7110-dmc"; - reg = <0x0 0x15700000 0x0 0x10000>, - <0x0 0x13000000 0x0 0x10000>; - bootph-pre-ram; - clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; - clock-names = "pll"; - resets = <&syscrg JH7110_SYSRST_DDR_AXI>, - <&syscrg JH7110_SYSRST_DDR_OSC>, - <&syscrg JH7110_SYSRST_DDR_APB>; - reset-names = "axi", "osc", "apb"; - }; - }; -}; - -&syscrg { - bootph-pre-ram; -}; - -&pllclk { - bootph-pre-ram; -}; - -// END "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader" - -/ { - soc { - memory-controller@15700000 { - clock-frequency = <2133>; /* FIXME: delete property and implement CCF */ - }; - }; -}; - -&syscrg { - assigned-clock-rates = <0>; /* FIXME: delete property and implement cpufreq */ -}; - -#include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/starfive-visionfive2-u-boot.dtsi b/arch/riscv/dts/starfive-visionfive2-u-boot.dtsi new file mode 100644 index 00000000000..0e5dc3685b2 --- /dev/null +++ b/arch/riscv/dts/starfive-visionfive2-u-boot.dtsi @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +// BEGIN "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader" +// From upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21 + +#include + +&clint { + bootph-pre-ram; +}; + +&cpu0_intc { + bootph-pre-ram; +}; + +&cpu1_intc { + bootph-pre-ram; +}; + +&cpu2_intc { + bootph-pre-ram; +}; + +&cpu3_intc { + bootph-pre-ram; +}; + +&cpu4_intc { + bootph-pre-ram; +}; + +&osc { + bootph-pre-ram; +}; + +&gmac1_rgmii_rxin { + bootph-pre-ram; +}; + +&gmac1_rmii_refin { + bootph-pre-ram; +}; + +/ { + soc { + memory-controller@15700000 { + compatible = "starfive,jh7110-dmc"; + reg = <0x0 0x15700000 0x0 0x10000>, + <0x0 0x13000000 0x0 0x10000>; + bootph-pre-ram; + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; + clock-names = "pll"; + resets = <&syscrg JH7110_SYSRST_DDR_AXI>, + <&syscrg JH7110_SYSRST_DDR_OSC>, + <&syscrg JH7110_SYSRST_DDR_APB>; + reset-names = "axi", "osc", "apb"; + }; + }; +}; + +&syscrg { + bootph-pre-ram; +}; + +&pllclk { + bootph-pre-ram; +}; + +// END "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader" + +/ { + soc { + memory-controller@15700000 { + clock-frequency = <2133>; /* FIXME: delete property and implement CCF */ + }; + }; +}; + +&syscrg { + assigned-clock-rates = <0>; /* FIXME: delete property and implement cpufreq */ +}; + +#include "starfive-visionfive2-binman.dtsi" diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 544140c03f7..03fcec7f121 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -78,6 +78,7 @@ CONFIG_CMD_WDT=y CONFIG_CMD_WGET=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_BOARD=y +CONFIG_DEVICE_TREE_INCLUDES="starfive-visionfive2-u-boot.dtsi" CONFIG_OF_LIST="starfive/jh7110-deepcomputing-fml13v01 starfive/jh7110-milkv-mars starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b" CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y -- cgit v1.3.1