From 2dd1092ab8872fc535369e4f29afad0e8d9d0d6d Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Thu, 22 Jun 2023 20:46:00 +0300 Subject: video: tegra20: provide driver support for the HDMI controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tegra platforms feature native HDMI support. Implement a driver to enable functionality. This driver will initially support Tegra 2 and 3, with future extensibility. Co-developed-by: Jonas Schwöbel Signed-off-by: Jonas Schwöbel Signed-off-by: Svyatoslav Ryhel --- arch/arm/include/asm/arch-tegra/dc.h | 46 +++++++++++++++++++++++++++++++++--- 1 file changed, 43 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h index ca3718411ab..2fd07403bdf 100644 --- a/arch/arm/include/asm/arch-tegra/dc.h +++ b/arch/arm/include/asm/arch-tegra/dc.h @@ -448,6 +448,11 @@ enum win_color_depth_id { #define LVS_OUTPUT_POLARITY_LOW BIT(28) #define LSC0_OUTPUT_POLARITY_LOW BIT(24) +/* DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 */ +#define H_PULSE0_ENABLE BIT(8) +#define H_PULSE1_ENABLE BIT(10) +#define H_PULSE2_ENABLE BIT(12) + /* DC_DISP_DISP_WIN_OPTIONS 0x402 */ #define CURSOR_ENABLE BIT(16) #define SOR_ENABLE BIT(25) @@ -504,6 +509,22 @@ enum { DATA_ORDER_BLUE_RED, }; +/* DC_DISP_DISP_COLOR_CONTROL 0x430 */ +#define DITHER_CONTROL_DISABLE (0 << 8) +#define DITHER_CONTROL_ORDERED (2 << 8) +#define DITHER_CONTROL_ERRDIFF (3 << 8) +enum { + BASE_COLOR_SIZE_666, + BASE_COLOR_SIZE_111, + BASE_COLOR_SIZE_222, + BASE_COLOR_SIZE_333, + BASE_COLOR_SIZE_444, + BASE_COLOR_SIZE_555, + BASE_COLOR_SIZE_565, + BASE_COLOR_SIZE_332, + BASE_COLOR_SIZE_888, +}; + /* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */ #define DE_SELECT_SHIFT 0 #define DE_SELECT_MASK (0x3 << DE_SELECT_SHIFT) @@ -570,8 +591,27 @@ enum { #define V_DDA_INC_SHIFT 16 #define V_DDA_INC_MASK (0xFFFF << V_DDA_INC_SHIFT) -#define DC_POLL_TIMEOUT_MS 50 -#define DC_N_WINDOWS 5 -#define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5) +#define DC_POLL_TIMEOUT_MS 50 +#define DC_N_WINDOWS 5 +#define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5) + +#define PULSE_MODE_NORMAL (0 << 3) +#define PULSE_MODE_ONE_CLOCK (1 << 3) +#define PULSE_POLARITY_HIGH (0 << 4) +#define PULSE_POLARITY_LOW (1 << 4) +#define PULSE_QUAL_ALWAYS (0 << 6) +#define PULSE_QUAL_VACTIVE (2 << 6) +#define PULSE_QUAL_VACTIVE1 (3 << 6) +#define PULSE_LAST_START_A (0 << 8) +#define PULSE_LAST_END_A (1 << 8) +#define PULSE_LAST_START_B (2 << 8) +#define PULSE_LAST_END_B (3 << 8) +#define PULSE_LAST_START_C (4 << 8) +#define PULSE_LAST_END_C (5 << 8) +#define PULSE_LAST_START_D (6 << 8) +#define PULSE_LAST_END_D (7 << 8) + +#define PULSE_START(x) (((x) & 0xfff) << 0) +#define PULSE_END(x) (((x) & 0xfff) << 16) #endif /* __ASM_ARCH_TEGRA_DC_H */ -- cgit v1.3.1 From 578126b3694fdb0b43c0ad0f00d7355a0134a39f Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 15 Feb 2025 19:49:23 +0200 Subject: ARM: tegra: lg_x3: upgrade video bindings Upgrade LG P895 and P880 device tree bindings according to preliminary upstream Linux tree. Once Linux catches up, LG X3 can be switched to OF_UPSTREAM without regressions. Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/tegra30-lg-p880.dts | 34 ++++++++++++----- arch/arm/dts/tegra30-lg-p895.dts | 55 ++++++++++++++------------- arch/arm/dts/tegra30-lg-x3.dtsi | 82 ++++++++++++++++++++++++++++++++++++---- configs/x3_t30_defconfig | 1 + 4 files changed, 129 insertions(+), 43 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/tegra30-lg-p880.dts b/arch/arm/dts/tegra30-lg-p880.dts index 1d5ca1459bc..ab5993150b2 100644 --- a/arch/arm/dts/tegra30-lg-p880.dts +++ b/arch/arm/dts/tegra30-lg-p880.dts @@ -101,6 +101,31 @@ }; }; + spi@7000dc00 { + bridge-spi@2 { + /* + * JDI 4.57" 720x1280 DX12D100VM0EAA MIPI DSI panel + */ + panel@0 { + compatible = "jdi,dx12d100vm0eaa"; + reg = <0>; + + reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>; + + vdd-supply = <&vcc_3v0_lcd>; + vddio-supply = <&iovcc_1v8_lcd>; + + backlight = <&backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + }; + }; + sdmmc3: sdhci@78000400 { status = "okay"; bus-width = <4>; @@ -118,13 +143,4 @@ linux,code = ; }; }; - - panel: panel { - compatible = "jdi,dx12d100vm0eaa"; - - enable-gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; - - backlight = <&backlight>; - }; }; diff --git a/arch/arm/dts/tegra30-lg-p895.dts b/arch/arm/dts/tegra30-lg-p895.dts index 43bb373a164..988e772172c 100644 --- a/arch/arm/dts/tegra30-lg-p895.dts +++ b/arch/arm/dts/tegra30-lg-p895.dts @@ -108,36 +108,37 @@ }; }; - panel: panel { - compatible = "hitachi,tx13d100vm0eaa"; - - reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; - - renesas,gamma = <3>; - renesas,inversion; - renesas,contrast; - - vcc-supply = <&vcc_3v0_lcd>; - iovcc-supply = <&iovcc_1v8_lcd>; - - backlight = <&backlight>; + spi@7000dc00 { + bridge-spi@2 { + /* + * HITACHI/KOE 5" 768x1024 TX13D100VM0EAA MIPI DSI panel + */ + panel@0 { + compatible = "koe,tx13d100vm0eaa"; + reg = <0>; + + reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>; + + renesas,gamma = <3>; + renesas,inversion; + renesas,contrast; + + vcc-supply = <&vcc_3v0_lcd>; + iovcc-supply = <&iovcc_1v8_lcd>; + + backlight = <&backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + }; }; - vcc_3v0_lcd: regulator-lcd { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v0_lcd"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; + regulator-lcd3v { gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_HIGH>; enable-active-high; }; - - iovcc_1v8_lcd: regulator-lcdvio { - compatible = "regulator-fixed"; - regulator-name = "iovcc_1v8_lcd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; }; diff --git a/arch/arm/dts/tegra30-lg-x3.dtsi b/arch/arm/dts/tegra30-lg-x3.dtsi index 30d6dcb6548..40b0ee07787 100644 --- a/arch/arm/dts/tegra30-lg-x3.dtsi +++ b/arch/arm/dts/tegra30-lg-x3.dtsi @@ -32,7 +32,12 @@ rgb { status = "okay"; - nvidia,panel = <&bridge>; + port { + dpi_output: endpoint { + remote-endpoint = <&bridge_input>; + bus-width = <24>; + }; + }; }; }; }; @@ -890,12 +895,22 @@ status = "okay"; clock-frequency = <400000>; - backlight: lm3533@36 { + backlight: led-controller@36 { compatible = "ti,lm3533"; reg = <0x36>; enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>; - default-brightness-level = <128>; + + ti,boost-ovp-microvolt = <24000000>; + ti,boost-freq-hz = <500000>; + + backlight-0 { + compatible = "ti,lm3533-backlight"; + + ti,max-current-microamp = <23400>; + ti,linear-mapping-mode; + ti,hardware-controlled; + }; }; muic@44 { @@ -969,18 +984,46 @@ compatible = "solomon,ssd2825"; reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + spi-cpol; spi-cpha; spi-max-frequency = <1000000>; - power-gpios = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_LOW>; + + dvdd-supply = <&vdd_1v2_rgb>; + avdd-supply = <&vdd_1v2_rgb>; + vddio-supply = <&vdd_1v8_vio>; + + solomon,hs-zero-delay-ns = <300>; + solomon,hs-prep-delay-ns = <65>; clocks = <&ssd2825_refclk>; - clock-names = "tx_clk"; - panel = <&panel>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + bus-width = <24>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; }; }; @@ -1036,4 +1079,29 @@ linux,code = ; }; }; + + vdd_1v2_rgb: regulator-rgb1v2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v2_rgb"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc_3v0_lcd: regulator-lcd3v { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v0_lcd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + iovcc_1v8_lcd: regulator-lcd1v8 { + compatible = "regulator-fixed"; + regulator-name = "iovcc_1v8_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; diff --git a/configs/x3_t30_defconfig b/configs/x3_t30_defconfig index 2d72a3bd56f..d0326351488 100644 --- a/configs/x3_t30_defconfig +++ b/configs/x3_t30_defconfig @@ -82,6 +82,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1004 CONFIG_USB_GADGET_PRODUCT_NUM=0x7100 CONFIG_CI_UDC=y CONFIG_VIDEO=y +CONFIG_VIDEO_BRIDGE=y # CONFIG_VIDEO_LOGO is not set CONFIG_BACKLIGHT_LM3533=y CONFIG_VIDEO_BRIDGE_SOLOMON_SSD2825=y -- cgit v1.3.1 From c9fbc404a11b6f3f4c0fbf1e444ee40fae1a30ac Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 1 Mar 2025 14:48:09 +0200 Subject: ARM: tegra: endeavoru: upgrade video bindings Upgrade HTC One X device tree to comply possible upstream Linux device tree. Once Linux catches up, HTC One X can be switched to OF_UPSTREAM. Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/tegra30-htc-endeavoru.dts | 17 ++++------------- configs/endeavoru_defconfig | 1 + 2 files changed, 5 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/tegra30-htc-endeavoru.dts b/arch/arm/dts/tegra30-htc-endeavoru.dts index 8a0ba3c07cc..db8ac457880 100644 --- a/arch/arm/dts/tegra30-htc-endeavoru.dts +++ b/arch/arm/dts/tegra30-htc-endeavoru.dts @@ -33,13 +33,11 @@ host1x@50000000 { dc@54200000 { - clocks = <&tegra_car TEGRA30_CLK_DISP1>, - <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + backlight: backlight { + compatible = "nvidia,tegra-pwm-backlight"; - rgb { - status = "okay"; - - nvidia,panel = <&dsia>; + nvidia,pwm-source = <1>; + nvidia,default-brightness = <0x8E>; }; }; @@ -1265,13 +1263,6 @@ nvidia,xcvr-lsrslew = <2>; }; - backlight: backlight { - compatible = "nvidia,tegra-pwm-backlight"; - - nvidia,pwm-source = <1>; - nvidia,default-brightness = <0x8E>; - }; - /* PMIC has a built-in 32KHz oscillator which is used by PMC */ clk32k_in: clock-32k { compatible = "fixed-clock"; diff --git a/configs/endeavoru_defconfig b/configs/endeavoru_defconfig index cc8777e4d83..a1c11c6435f 100644 --- a/configs/endeavoru_defconfig +++ b/configs/endeavoru_defconfig @@ -79,6 +79,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0bb4 CONFIG_USB_GADGET_PRODUCT_NUM=0x0c02 CONFIG_CI_UDC=y CONFIG_VIDEO=y +CONFIG_VIDEO_BRIDGE=y # CONFIG_VIDEO_LOGO is not set CONFIG_VIDEO_LCD_ENDEAVORU=y CONFIG_VIDEO_DSI_TEGRA30=y -- cgit v1.3.1 From 1f51562cdece5dcad99dda02957a48d5be042f79 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Tue, 4 Mar 2025 19:59:59 +0200 Subject: ARM: tegra: p1801-t: configure HDMI binding Bind HDMI for ASUS AiO P1801-t to provide full panel support and improve usability. Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/tegra30-asus-p1801-t.dts | 12 +----------- configs/transformer_t30_defconfig | 2 ++ 2 files changed, 3 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts index 243ff2bda26..4b7b64b477b 100644 --- a/arch/arm/dts/tegra30-asus-p1801-t.dts +++ b/arch/arm/dts/tegra30-asus-p1801-t.dts @@ -34,20 +34,10 @@ host1x@50000000 { dc@54200000 { - clocks = <&tegra_car TEGRA30_CLK_DISP1>, - <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; - - rgb { - status = "okay"; - - nvidia,panel = <&hdmi>; - }; + status = "disabled"; }; hdmi: hdmi@54280000 { - clocks = <&tegra_car TEGRA30_CLK_HDMI>, - <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; - status = "okay"; hdmi-supply = <&hdmi_5v0_sys>; diff --git a/configs/transformer_t30_defconfig b/configs/transformer_t30_defconfig index 9d63755533a..f5a666d8a17 100644 --- a/configs/transformer_t30_defconfig +++ b/configs/transformer_t30_defconfig @@ -89,6 +89,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0b05 CONFIG_USB_GADGET_PRODUCT_NUM=0x4daf CONFIG_CI_UDC=y CONFIG_VIDEO=y +CONFIG_VIDEO_BRIDGE=y # CONFIG_VIDEO_LOGO is not set CONFIG_VIDEO_BRIDGE_TOSHIBA_TC358768=y CONFIG_VIDEO_TEGRA20=y +CONFIG_VIDEO_HDMI_TEGRA=y -- cgit v1.3.1 From 8a2846e7adeb2c9287ad4ed8c6ea8e7b2a5219c2 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Tue, 4 Mar 2025 20:08:55 +0200 Subject: ARM: tegra: tf700t: upgrade video bindings Align TF700T bindings with existing upstream device trees. OF_UPSTREAM migration is possible already but resulting size of binary exceeds maximum allowed size with full size trees. Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/tegra30-asus-tf700t.dts | 96 +++++++++++++++++++++++++----------- 1 file changed, 67 insertions(+), 29 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/tegra30-asus-tf700t.dts b/arch/arm/dts/tegra30-asus-tf700t.dts index 6dc760b90d6..47606ede9d6 100644 --- a/arch/arm/dts/tegra30-asus-tf700t.dts +++ b/arch/arm/dts/tegra30-asus-tf700t.dts @@ -15,7 +15,14 @@ rgb { status = "okay"; - nvidia,panel = <&tc358768>; + /delete-property/ nvidia,panel; + + port { + dpi_output: endpoint { + remote-endpoint = <&bridge_input>; + bus-width = <24>; + }; + }; }; }; }; @@ -118,38 +125,69 @@ vddio-supply = <&vdd_1v8_vio>; vddmipi-supply = <&vdd_1v2_mipi>; - panel = <&panel>; + /* + * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1 + * LCD SuperIPS+ Full HD panel. + */ + panel@1 { + compatible = "panasonic,vvx10f004b00"; + reg = <1>; + + power-supply = <&vdd_pnl_reg>; + backlight = <&backlight>; + + display-timings { + timing@0 { + /* 1920x1200@60Hz */ + clock-frequency = <154000000>; + + hactive = <1920>; + hfront-porch = <48>; + hback-porch = <80>; + hsync-len = <32>; + hsync-active = <1>; + + vactive = <1200>; + vfront-porch = <3>; + vback-porch = <26>; + vsync-len = <6>; + vsync-active = <1>; + }; + }; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + bus-width = <24>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; }; }; }; - panel: panel { - compatible = "panasonic,vvx10f004b00"; - - power-supply = <&vdd_pnl_reg>; - backlight = <&backlight>; - - /delete-property/ enable-gpios; - - display-timings { - timing@0 { - /* 1920x1200@60Hz */ - clock-frequency = <154000000>; - - hactive = <1920>; - hfront-porch = <48>; - hback-porch = <80>; - hsync-len = <32>; - hsync-active = <1>; - - vactive = <1200>; - vfront-porch = <3>; - vback-porch = <26>; - vsync-len = <6>; - vsync-active = <1>; - }; - }; - }; + /delete-node/ panel; vdd_1v2_mipi: regulator-mipi { compatible = "regulator-fixed"; -- cgit v1.3.1 From 65e4869a10dc7484924172149e9d7757a9ae5702 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Thu, 13 Mar 2025 11:02:35 +0200 Subject: pinctrl: tegra: adjust pin state lists Modify the pin state lists for lock, io-reset, rcv-sel, and e-io-hv properties by repositioning the default value to the end. This change addresses conflicts with device tree representations of TEGRA_PIN_DISABLE and TEGRA_PIN_ENABLE. Signed-off-by: Svyatoslav Ryhel --- arch/arm/include/asm/arch-tegra/pinmux.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index 4b6e8419504..9a5cc93884c 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -34,41 +34,41 @@ enum pmux_pin_io { #ifdef TEGRA_PMX_PINS_HAVE_LOCK enum pmux_pin_lock { - PMUX_PIN_LOCK_DEFAULT = 0, - PMUX_PIN_LOCK_DISABLE, + PMUX_PIN_LOCK_DISABLE = 0, PMUX_PIN_LOCK_ENABLE, + PMUX_PIN_LOCK_DEFAULT, }; #endif #ifdef TEGRA_PMX_PINS_HAVE_OD enum pmux_pin_od { - PMUX_PIN_OD_DEFAULT = 0, - PMUX_PIN_OD_DISABLE, + PMUX_PIN_OD_DISABLE = 0, PMUX_PIN_OD_ENABLE, + PMUX_PIN_OD_DEFAULT, }; #endif #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET enum pmux_pin_ioreset { - PMUX_PIN_IO_RESET_DEFAULT = 0, - PMUX_PIN_IO_RESET_DISABLE, + PMUX_PIN_IO_RESET_DISABLE = 0, PMUX_PIN_IO_RESET_ENABLE, + PMUX_PIN_IO_RESET_DEFAULT, }; #endif #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL enum pmux_pin_rcv_sel { - PMUX_PIN_RCV_SEL_DEFAULT = 0, - PMUX_PIN_RCV_SEL_NORMAL, + PMUX_PIN_RCV_SEL_NORMAL = 0, PMUX_PIN_RCV_SEL_HIGH, + PMUX_PIN_RCV_SEL_DEFAULT, }; #endif #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV enum pmux_pin_e_io_hv { - PMUX_PIN_E_IO_HV_DEFAULT = 0, - PMUX_PIN_E_IO_HV_NORMAL, + PMUX_PIN_E_IO_HV_NORMAL = 0, PMUX_PIN_E_IO_HV_HIGH, + PMUX_PIN_E_IO_HV_DEFAULT, }; #endif -- cgit v1.3.1 From 6494be8c722aa5e1d7bc9ea8d9e0b29d6dfe9b04 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 14 Mar 2025 12:29:28 +0200 Subject: pinctrl: tegra20: fix function naming mismatches The names used for displaya, displayb and i2c1 do not align with their corresponding Linux counterparts. This inconsistency can cause pins to be configured incorrectly, potentially breaking existing functionality. Signed-off-by: Svyatoslav Ryhel --- arch/arm/include/asm/arch-tegra20/pinmux.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h index 8c8579e87e3..9598851b100 100644 --- a/arch/arm/include/asm/arch-tegra20/pinmux.h +++ b/arch/arm/include/asm/arch-tegra20/pinmux.h @@ -467,14 +467,14 @@ static const char * const tegra_pinctrl_to_func[] = { [PMUX_FUNC_DAP3] = "dap3", [PMUX_FUNC_DAP4] = "dap4", [PMUX_FUNC_DAP5] = "dap5", - [PMUX_FUNC_DISPA] = "dispa", - [PMUX_FUNC_DISPB] = "dispb", + [PMUX_FUNC_DISPA] = "displaya", + [PMUX_FUNC_DISPB] = "displayb", [PMUX_FUNC_EMC_TEST0_DLL] = "emc_test0_dll", [PMUX_FUNC_EMC_TEST1_DLL] = "emc_test1_dll", [PMUX_FUNC_GMI] = "gmi", [PMUX_FUNC_GMI_INT] = "gmi_int", [PMUX_FUNC_HDMI] = "hdmi", - [PMUX_FUNC_I2C] = "i2c", + [PMUX_FUNC_I2C] = "i2c1", [PMUX_FUNC_I2C2] = "i2c2", [PMUX_FUNC_I2C3] = "i2c3", [PMUX_FUNC_IDE] = "ide", -- cgit v1.3.1 From 13af58edb29d3ef840ff06e23fd7311b8c8aad9f Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Thu, 13 Mar 2025 13:11:00 +0200 Subject: ARM: tegra: dts: fix lock, io-reset and open-drain properties Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/tegra124-xiaomi-mocha.dts | 14 ++++---- arch/arm/dts/tegra30-asus-p1801-t.dts | 28 +++++++-------- arch/arm/dts/tegra30-asus-tf600t.dts | 44 +++++++++++------------ arch/arm/dts/tegra30-asus-transformer.dtsi | 26 +++++++------- arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts | 46 ++++++++++++------------- arch/arm/dts/tegra30-microsoft-surface-rt.dts | 38 ++++++++++---------- arch/arm/dts/tegra30-wexler-qc750.dts | 10 +++--- 7 files changed, 103 insertions(+), 103 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/tegra124-xiaomi-mocha.dts b/arch/arm/dts/tegra124-xiaomi-mocha.dts index 6cb1781566f..64386f2b7b7 100644 --- a/arch/arm/dts/tegra124-xiaomi-mocha.dts +++ b/arch/arm/dts/tegra124-xiaomi-mocha.dts @@ -215,8 +215,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,open-drain = <1>; + nvidia,lock = ; + nvidia,open-drain = ; }; gen2-i2c { nvidia,pins = "gen2_i2c_scl_pt5", @@ -225,8 +225,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,open-drain = <1>; + nvidia,lock = ; + nvidia,open-drain = ; }; cam-i2c { nvidia,pins = "cam_i2c_scl_pbb1", @@ -235,8 +235,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,open-drain = <1>; + nvidia,lock = ; + nvidia,open-drain = ; }; ddc-i2c { nvidia,pins = "ddc_scl_pv4", @@ -253,7 +253,7 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,open-drain = <1>; + nvidia,open-drain = ; }; dsi-b { diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts index 4b7b64b477b..58f1499cb92 100644 --- a/arch/arm/dts/tegra30-asus-p1801-t.dts +++ b/arch/arm/dts/tegra30-asus-p1801-t.dts @@ -108,8 +108,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; /* SDMMC3 pinmux */ @@ -193,7 +193,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <1>; + nvidia,lock = ; }; gen2_i2c { nvidia,pins = "gen2_i2c_scl_pt5", @@ -203,7 +203,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <1>; + nvidia,lock = ; }; cam_i2c { nvidia,pins = "cam_i2c_scl_pbb1", @@ -213,7 +213,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <1>; + nvidia,lock = ; }; ddc_i2c { nvidia,pins = "ddc_scl_pv4", @@ -222,7 +222,7 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; + nvidia,lock = ; }; pwr_i2c { nvidia,pins = "pwr_i2c_scl_pz6", @@ -232,7 +232,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <1>; + nvidia,lock = ; }; hotplug_i2c { nvidia,pins = "pu4"; @@ -250,7 +250,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <1>; + nvidia,lock = ; }; hdmi_hpd { nvidia,pins = "hdmi_int_pn7"; @@ -622,8 +622,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; /* GPIO keys pinmux */ @@ -708,8 +708,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; vi_d10_pt2 { nvidia,pins = "vi_d10_pt2", @@ -828,8 +828,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; vi_mclk_pt1 { nvidia,pins = "vi_mclk_pt1"; diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts index 3ddd78b3df6..1b5729c65f4 100644 --- a/arch/arm/dts/tegra30-asus-tf600t.dts +++ b/arch/arm/dts/tegra30-asus-tf600t.dts @@ -90,8 +90,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; /* SDMMC2 pinmux */ @@ -107,8 +107,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; /* SDMMC3 pinmux */ @@ -142,8 +142,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; sdmmc4_cmd { nvidia,pins = "sdmmc4_cmd_pt7", @@ -159,8 +159,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; sdmmc4_rst_n { nvidia,pins = "sdmmc4_rst_n_pcc3"; @@ -186,7 +186,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <0>; + nvidia,lock = ; }; gen2_i2c { nvidia,pins = "gen2_i2c_scl_pt5", @@ -196,7 +196,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <0>; + nvidia,lock = ; }; cam_i2c { nvidia,pins = "cam_i2c_scl_pbb1", @@ -206,7 +206,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <0>; + nvidia,lock = ; }; ddc_i2c { nvidia,pins = "ddc_scl_pv4", @@ -215,7 +215,7 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <0>; + nvidia,lock = ; }; pwr_i2c { nvidia,pins = "pwr_i2c_scl_pz6", @@ -225,7 +225,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <0>; + nvidia,lock = ; }; hotplug_i2c { nvidia,pins = "pu4"; @@ -243,7 +243,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <0>; + nvidia,lock = ; }; hdmi_hpd { nvidia,pins = "hdmi_int_pn7"; @@ -613,8 +613,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; /* GPIO keys pinmux */ @@ -701,8 +701,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; pbb0 { nvidia,pins = "pbb0"; @@ -827,8 +827,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; vi_mclk_pt1 { nvidia,pins = "vi_mclk_pt1"; @@ -836,8 +836,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; jtag { diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi index 03ba8fb9604..032fb3d00ac 100644 --- a/arch/arm/dts/tegra30-asus-transformer.dtsi +++ b/arch/arm/dts/tegra30-asus-transformer.dtsi @@ -99,8 +99,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; /* SDMMC3 pinmux */ @@ -189,7 +189,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <1>; + nvidia,lock = ; }; gen2_i2c { @@ -200,7 +200,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <1>; + nvidia,lock = ; }; cam_i2c { @@ -211,7 +211,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <1>; + nvidia,lock = ; }; ddc_i2c { @@ -221,7 +221,7 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; + nvidia,lock = ; }; pwr_i2c { @@ -232,7 +232,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <1>; + nvidia,lock = ; }; hotplug_i2c { @@ -647,8 +647,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; /* GPIO keys pinmux */ @@ -741,8 +741,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; vi_d10_pt2 { @@ -879,8 +879,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; vi_mclk_pt1 { diff --git a/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts b/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts index 9a1e8c0601e..876fac7b661 100644 --- a/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts +++ b/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts @@ -109,8 +109,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; sdmmc4-cmd { nvidia,pins = "sdmmc4_cmd_pt7", @@ -127,8 +127,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; cam-mclk { nvidia,pins = "cam_mclk_pcc0"; @@ -147,7 +147,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <1>; + nvidia,lock = ; }; gen2-i2c { nvidia,pins = "gen2_i2c_scl_pt5", @@ -157,7 +157,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <1>; + nvidia,lock = ; }; cam-i2c { nvidia,pins = "cam_i2c_scl_pbb1", @@ -167,7 +167,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <1>; + nvidia,lock = ; }; ddc-i2c { nvidia,pins = "ddc_scl_pv4", @@ -176,7 +176,7 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; + nvidia,lock = ; }; pwr-i2c { nvidia,pins = "pwr_i2c_scl_pz6", @@ -186,7 +186,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <1>; + nvidia,lock = ; }; /* HDMI pinmux */ @@ -724,8 +724,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; vi-vsync-pd6 { nvidia,pins = "vi_vsync_pd6", @@ -736,8 +736,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <2>; + nvidia,lock = ; + nvidia,io-reset = ; }; vi-hsync-pd7 { nvidia,pins = "vi_hsync_pd7", @@ -749,8 +749,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; vi-d2-pl0 { nvidia,pins = "vi_d2_pl0", @@ -760,8 +760,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; vi-mclk-pt1 { nvidia,pins = "vi_mclk_pt1"; @@ -769,8 +769,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <2>; + nvidia,lock = ; + nvidia,io-reset = ; }; vi-d11-pt3 { nvidia,pins = "vi_d11_pt3"; @@ -778,8 +778,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; vi-d5-pl3 { nvidia,pins = "vi_d5_pl3"; @@ -787,8 +787,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; /* PORT U */ diff --git a/arch/arm/dts/tegra30-microsoft-surface-rt.dts b/arch/arm/dts/tegra30-microsoft-surface-rt.dts index 6810350a90b..2d22d3e0bb1 100644 --- a/arch/arm/dts/tegra30-microsoft-surface-rt.dts +++ b/arch/arm/dts/tegra30-microsoft-surface-rt.dts @@ -103,8 +103,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; sdmmc4-cmd { nvidia,pins = "sdmmc4_cmd_pt7", @@ -121,8 +121,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; cam-mclk { nvidia,pins = "cam_mclk_pcc0"; @@ -141,7 +141,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <0>; + nvidia,lock = ; }; gen2-i2c { nvidia,pins = "gen2_i2c_scl_pt5", @@ -151,7 +151,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <0>; + nvidia,lock = ; }; cam-i2c { nvidia,pins = "cam_i2c_scl_pbb1", @@ -161,7 +161,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <0>; + nvidia,lock = ; }; ddc-i2c { nvidia,pins = "ddc_scl_pv4", @@ -170,7 +170,7 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <0>; + nvidia,lock = ; }; pwr-i2c { nvidia,pins = "pwr_i2c_scl_pz6", @@ -180,7 +180,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <0>; + nvidia,lock = ; }; /* HDMI pinmux */ @@ -703,8 +703,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; vi-d3-pl1 { nvidia,pins = "vi_d3_pl1"; @@ -712,8 +712,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; vi-hsync-pd7 { nvidia,pins = "vi_hsync_pd7", @@ -724,8 +724,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; vi-mclk-pt1 { nvidia,pins = "vi_mclk_pt1"; @@ -733,8 +733,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; vi-d11-pt3 { nvidia,pins = "vi_d11_pt3"; @@ -742,8 +742,8 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <1>; - nvidia,io-reset = <1>; + nvidia,lock = ; + nvidia,io-reset = ; }; /* PORT U */ diff --git a/arch/arm/dts/tegra30-wexler-qc750.dts b/arch/arm/dts/tegra30-wexler-qc750.dts index 87c2a4072e1..b376b91a7fa 100644 --- a/arch/arm/dts/tegra30-wexler-qc750.dts +++ b/arch/arm/dts/tegra30-wexler-qc750.dts @@ -157,7 +157,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <0>; + nvidia,lock = ; }; gen2-i2c { nvidia,pins = "gen2_i2c_scl_pt5", @@ -167,7 +167,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <0>; + nvidia,lock = ; }; cam-i2c { nvidia,pins = "cam_i2c_scl_pbb1", @@ -177,7 +177,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <0>; + nvidia,lock = ; }; ddc-i2c { nvidia,pins = "ddc_scl_pv4", @@ -186,7 +186,7 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,lock = <0>; + nvidia,lock = ; }; pwr-i2c { nvidia,pins = "pwr_i2c_scl_pz6", @@ -196,7 +196,7 @@ nvidia,tristate = ; nvidia,enable-input = ; nvidia,open-drain = ; - nvidia,lock = <0>; + nvidia,lock = ; }; /* HDMI pinmux */ -- cgit v1.3.1 From 03f61b153965101f21783e8e6a1e5e86496598ff Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Wed, 5 Mar 2025 15:05:30 +0200 Subject: board: ouya: add Ouya Game Console support The Ouya microconsole is build on Nvidia Tegra 3 (T33) SoC, featuring a quad-core 1.7 GHz ARM Cortex-A9 CPU and a ULP GeForce GPU, paired with 1GB of DDR3 RAM and 8GB of internal flash storage. Running a modified Android 4.1 (Jelly Bean) OS with a custom launcher, it aimed for open-source gaming via a digital storefront. This implementation is mostly based on upstream Linux device tree and fragments of work done by previous developers. Co-developed-by: Peter Geis Signed-off-by: Peter Geis Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra30-ouya.dts | 2063 +++++++++++++++++++++++++++++++++++ arch/arm/mach-tegra/tegra30/Kconfig | 5 + board/ouya/ouya/Kconfig | 12 + board/ouya/ouya/MAINTAINERS | 8 + board/ouya/ouya/Makefile | 11 + board/ouya/ouya/ouya-spl.c | 41 + board/ouya/ouya/ouya.c | 21 + board/ouya/ouya/ouya.env | 12 + configs/ouya_defconfig | 86 ++ doc/board/index.rst | 1 + doc/board/ouya/index.rst | 9 + doc/board/ouya/ouya.rst | 124 +++ include/configs/ouya.h | 23 + include/env/nvidia/prod_upd.env | 5 +- 15 files changed, 2420 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/tegra30-ouya.dts create mode 100644 board/ouya/ouya/Kconfig create mode 100644 board/ouya/ouya/MAINTAINERS create mode 100644 board/ouya/ouya/Makefile create mode 100644 board/ouya/ouya/ouya-spl.c create mode 100644 board/ouya/ouya/ouya.c create mode 100644 board/ouya/ouya/ouya.env create mode 100644 configs/ouya_defconfig create mode 100644 doc/board/ouya/index.rst create mode 100644 doc/board/ouya/ouya.rst create mode 100644 include/configs/ouya.h (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 73231824526..bad582c66b0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -113,6 +113,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += \ tegra30-lg-p880.dtb \ tegra30-lg-p895.dtb \ tegra30-microsoft-surface-rt.dtb \ + tegra30-ouya.dtb \ tegra30-tec-ng.dtb \ tegra30-wexler-qc750.dtb \ tegra114-dalmore.dtb \ diff --git a/arch/arm/dts/tegra30-ouya.dts b/arch/arm/dts/tegra30-ouya.dts new file mode 100644 index 00000000000..04453eb2432 --- /dev/null +++ b/arch/arm/dts/tegra30-ouya.dts @@ -0,0 +1,2063 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "tegra30.dtsi" + +/ { + model = "Ouya Game Console"; + compatible = "ouya,ouya", "nvidia,tegra30"; + + chosen { + stdout-path = &uartd; + }; + + aliases { + i2c0 = &pwr_i2c; + i2c1 = &hdmi_ddc; + + mmc0 = &sdmmc4; + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + usb0 = µ_usb; + usb1 = ðernet_usb; + usb2 = &fullsize_usb; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + status = "disabled"; + }; + + hdmi: hdmi@54280000 { + status = "okay"; + + hdmi-supply = <&sys_3v3_reg>; + pll-supply = <&ldo7_reg>; + vdd-supply = <&vdd_vid_reg>; + + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + }; + }; + + gpio@6000d000 { + fan-en-hog { + gpio-hog; + gpios = ; + output-high; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a18_pb1 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_pclk_pb3 { + nvidia,pins = "lcd_pclk_pb3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_pwr1_pc1 { + nvidia,pins = "lcd_pwr1_pc1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat5_pd0 { + nvidia,pins = "sdmmc3_dat5_pd0"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat4_pd1 { + nvidia,pins = "sdmmc3_dat4_pd1"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat6_pd3 { + nvidia,pins = "sdmmc3_dat6_pd3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc3_dat7_pd4 { + nvidia,pins = "sdmmc3_dat7_pd4"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_hsync_pd7 { + nvidia,pins = "vi_hsync_pd7"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d0_pe0 { + nvidia,pins = "lcd_d0_pe0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d1_pe1 { + nvidia,pins = "lcd_d1_pe1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d2_pe2 { + nvidia,pins = "lcd_d2_pe2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d3_pe3 { + nvidia,pins = "lcd_d3_pe3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d4_pe4 { + nvidia,pins = "lcd_d4_pe4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d5_pe5 { + nvidia,pins = "lcd_d5_pe5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d6_pe6 { + nvidia,pins = "lcd_d6_pe6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d7_pe7 { + nvidia,pins = "lcd_d7_pe7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d8_pf0 { + nvidia,pins = "lcd_d8_pf0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d9_pf1 { + nvidia,pins = "lcd_d9_pf1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d10_pf2 { + nvidia,pins = "lcd_d10_pf2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d11_pf3 { + nvidia,pins = "lcd_d11_pf3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d12_pf4 { + nvidia,pins = "lcd_d12_pf4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d13_pf5 { + nvidia,pins = "lcd_d13_pf5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d14_pf6 { + nvidia,pins = "lcd_d14_pf6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d15_pf7 { + nvidia,pins = "lcd_d15_pf7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad1_pg1 { + nvidia,pins = "gmi_ad1_pg1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad2_pg2 { + nvidia,pins = "gmi_ad2_pg2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad3_pg3 { + nvidia,pins = "gmi_ad3_pg3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad4_pg4 { + nvidia,pins = "gmi_ad4_pg4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad5_pg5 { + nvidia,pins = "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad6_pg6 { + nvidia,pins = "gmi_ad6_pg6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad7_pg7 { + nvidia,pins = "gmi_ad7_pg7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad11_ph3 { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_ad14_ph6 { + nvidia,pins = "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wr_n_pi0 { + nvidia,pins = "gmi_wr_n_pi0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_oe_n_pi1 { + nvidia,pins = "gmi_oe_n_pi1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_dqs_pi2 { + nvidia,pins = "gmi_dqs_pi2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs7_n_pi6 { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_wait_pi7 { + nvidia,pins = "gmi_wait_pi7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_de_pj1 { + nvidia,pins = "lcd_de_pj1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs1_n_pj2 { + nvidia,pins = "gmi_cs1_n_pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_hsync_pj3 { + nvidia,pins = "lcd_hsync_pj3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_vsync_pj4 { + nvidia,pins = "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_adv_n_pk0 { + nvidia,pins = "gmi_adv_n_pk0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_clk_pk1 { + nvidia,pins = "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs2_n_pk3 { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_cs3_n_pk4 { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d2_pl0 { + nvidia,pins = "vi_d2_pl0"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d3_pl1 { + nvidia,pins = "vi_d3_pl1"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d5_pl3 { + nvidia,pins = "vi_d5_pl3"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d7_pl5 { + nvidia,pins = "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d9_pl7 { + nvidia,pins = "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d16_pm0 { + nvidia,pins = "lcd_d16_pm0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d17_pm1 { + nvidia,pins = "lcd_d17_pm1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d18_pm2 { + nvidia,pins = "lcd_d18_pm2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d19_pm3 { + nvidia,pins = "lcd_d19_pm3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d20_pm4 { + nvidia,pins = "lcd_d20_pm4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d21_pm5 { + nvidia,pins = "lcd_d21_pm5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d22_pm6 { + nvidia,pins = "lcd_d22_pm6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_d23_pm7 { + nvidia,pins = "lcd_d23_pm7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_cs0_n_pn4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_sdout_pn5 { + nvidia,pins = "lcd_sdout_pn5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_dc0_pn6 { + nvidia,pins = "lcd_dc0_pn6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d11_pt3 { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + vi_d0_pt4 { + nvidia,pins = "vi_d0_pt4"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "clk_12m_out"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + crt_vsync_pv7 { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_cs1_n_pw0 { + nvidia,pins = "lcd_cs1_n_pw0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_m1_pw1 { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_cs0_n_px6 { + nvidia,pins = "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_sdin_pz2 { + nvidia,pins = "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_wr_n_pz3 { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + lcd_sck_pz4 { + nvidia,pins = "lcd_sck_pz4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_clkreq_n_pcc7 { + nvidia,pins = "pex_l2_clkreq_n_pcc7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l0_prsnt_n_pdd0 { + nvidia,pins = "pex_l0_prsnt_n_pdd0"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_prsnt_n_pdd4 { + nvidia,pins = "pex_l1_prsnt_n_pdd4"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pex_l2_prsnt_n_pdd7 { + nvidia,pins = "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC4 pinmux */ + sdmmc4_clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,io-reset = ; + }; + sdmmc4_cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,io-reset = ; + }; + sdmmc4_rst_n { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + drive_groups { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + uartd: serial@70006300 { + status = "okay"; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + wakeup-source; + + ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>; + ti,system-power-controller; + ti,sleep-keep-ck32k; + ti,sleep-enable; + + #gpio-cells = <2>; + gpio-controller; + + regulators { + vdd_1v8: vddio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo7_reg: ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + }; + }; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&sys_3v3_reg>; + vqmmc-supply = <&vdd_1v8>; + }; + + micro_usb: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@7d000000 { + status = "okay"; + }; + + ethernet_usb: usb@7d004000 { + status = "okay"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + /* SMSC 10/100T Ethernet Controller */ + ethernet@2 { + compatible = "usb424,9e00"; + reg = <2>; + local-mac-address = [00 11 22 33 44 55]; + }; + }; + + usb-phy@7d004000 { + status = "okay"; + }; + + fullsize_usb: usb@7d008000 { + status = "okay"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; + }; + + usb-phy@7d008000 { + status = "okay"; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-power { + label = "power-led"; + gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + retain-state-suspended; + }; + }; + + sys_3v3_reg: regulator-sys-3v3 { + compatible = "regulator-fixed"; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_vid_reg: regulator-vdd-vid { + compatible = "regulator-fixed"; + regulator-name = "vddio_vid"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig index e0f054af8e0..b5099ce67fc 100644 --- a/arch/arm/mach-tegra/tegra30/Kconfig +++ b/arch/arm/mach-tegra/tegra30/Kconfig @@ -32,6 +32,10 @@ config TARGET_IDEAPAD_YOGA_11 bool "Lenovo Ideapad Yoga 11 board" select BOARD_LATE_INIT +config TARGET_OUYA + bool "Ouya Game Console board" + select BOARD_LATE_INIT + config TARGET_QC750 bool "Wexler QC750 board" select BOARD_LATE_INIT @@ -64,6 +68,7 @@ source "board/toradex/colibri_t30/Kconfig" source "board/htc/endeavoru/Kconfig" source "board/asus/grouper/Kconfig" source "board/lenovo/ideapad-yoga-11/Kconfig" +source "board/ouya/ouya/Kconfig" source "board/wexler/qc750/Kconfig" source "board/microsoft/surface-rt/Kconfig" source "board/avionic-design/tec-ng/Kconfig" diff --git a/board/ouya/ouya/Kconfig b/board/ouya/ouya/Kconfig new file mode 100644 index 00000000000..6bab40ce933 --- /dev/null +++ b/board/ouya/ouya/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OUYA + +config SYS_BOARD + default "ouya" + +config SYS_VENDOR + default "ouya" + +config SYS_CONFIG_NAME + default "ouya" + +endif diff --git a/board/ouya/ouya/MAINTAINERS b/board/ouya/ouya/MAINTAINERS new file mode 100644 index 00000000000..7f664b2e65f --- /dev/null +++ b/board/ouya/ouya/MAINTAINERS @@ -0,0 +1,8 @@ +OUYA BOARD +M: Svyatoslav Ryhel +M: Peter Geis +S: Maintained +F: board/ouya/ouya/ +F: configs/ouya_defconfig +F: doc/board/ouya/ouya.rst +F: include/configs/ouya.h diff --git a/board/ouya/ouya/Makefile b/board/ouya/ouya/Makefile new file mode 100644 index 00000000000..d479ec83e5e --- /dev/null +++ b/board/ouya/ouya/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation +# +# (C) Copyright 2021 +# Svyatoslav Ryhel + +obj-$(CONFIG_XPL_BUILD) += ouya-spl.o + +obj-y += ouya.o diff --git a/board/ouya/ouya/ouya-spl.c b/board/ouya/ouya/ouya-spl.c new file mode 100644 index 00000000000..1f45853c8be --- /dev/null +++ b/board/ouya/ouya/ouya-spl.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * T30 Ouya SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * (C) Copyright 2025 + * Svyatoslav Ryhel + */ + +#include +#include +#include + +#define TPS65911_I2C_ADDR (0x2D << 1) +#define TPS65911_VDDCTRL_OP_REG 0x28 +#define TPS65911_VDDCTRL_SR_REG 0x27 +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) + +#define TPS62361B_I2C_ADDR (0x60 << 1) +#define TPS62361B_SET3_REG 0x03 +#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG) + +void pmic_enable_cpu_vdd(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA); + + udelay(1000); + + /* + * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. + * First set VDD to 1.0125V, then enable the VDD regulator. + */ + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA); + udelay(10 * 1000); +} diff --git a/board/ouya/ouya/ouya.c b/board/ouya/ouya/ouya.c new file mode 100644 index 00000000000..6d6eb54afe2 --- /dev/null +++ b/board/ouya/ouya/ouya.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * (C) Copyright 2025 + * Svyatoslav Ryhel + */ + +#include + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* Remove TrustZone nodes */ + fdt_del_node_and_alias(blob, "/firmware"); + fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000"); + + return 0; +} +#endif diff --git a/board/ouya/ouya/ouya.env b/board/ouya/ouya/ouya.env new file mode 100644 index 00000000000..6ec881b910a --- /dev/null +++ b/board/ouya/ouya/ouya.env @@ -0,0 +1,12 @@ +#include + +partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs} +boot_interface=usb + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_2=update bootloader=run flash_uboot +bootmenu_3=reboot RCM=enterrcm +bootmenu_4=reboot=reset +bootmenu_5=power off=poweroff +bootmenu_delay=-1 diff --git a/configs/ouya_defconfig b/configs/ouya_defconfig new file mode 100644 index 00000000000..ccd6ae4d36f --- /dev/null +++ b/configs/ouya_defconfig @@ -0,0 +1,86 @@ +CONFIG_ARM=y +CONFIG_ARCH_TEGRA=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x80110000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="ouya" +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xFFFFD000 +CONFIG_DEFAULT_DEVICE_TREE="tegra30-ouya" +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SPL_TEXT_BASE=0x80108000 +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_TEGRA30=y +CONFIG_TARGET_OUYA=y +CONFIG_TEGRA_ENABLE_UARTD=y +CONFIG_CMD_EBTUPDATE=y +CONFIG_BUTTON_CMD=y +CONFIG_BOOTDELAY=3 +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff" +CONFIG_USE_PREBOOT=y +CONFIG_SYS_PBSIZE=2084 +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x10000 +CONFIG_SYS_PROMPT="Tegra30 (Ouya) # " +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PAUSE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_BUTTON=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x91000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_GPIO_HOG=y +CONFIG_SYS_I2C_TEGRA=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_TPS65910=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_TPS65911=y +CONFIG_PWM_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET_TPS65910=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +CONFIG_I2C_EDID_STANDARD=y +CONFIG_VIDEO_BRIDGE=y +CONFIG_VIDEO_HDMI_TEGRA=y diff --git a/doc/board/index.rst b/doc/board/index.rst index 84c135e02c1..7ad1137c94a 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -43,6 +43,7 @@ Board-specific doc microsoft/index nxp/index openpiton/index + ouya/index phytec/index purism/index qualcomm/index diff --git a/doc/board/ouya/index.rst b/doc/board/ouya/index.rst new file mode 100644 index 00000000000..7413240a1b8 --- /dev/null +++ b/doc/board/ouya/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +OUYA +==== + +.. toctree:: + :maxdepth: 2 + + ouya diff --git a/doc/board/ouya/ouya.rst b/doc/board/ouya/ouya.rst new file mode 100644 index 00000000000..641affc6294 --- /dev/null +++ b/doc/board/ouya/ouya.rst @@ -0,0 +1,124 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the Ouya Game Console (ouya) +======================================= + +``DISCLAMER!`` Moving your Ouya to use U-Boot assumes replacement of the +vendor bootloader. Vendor android firmwares will no longer be able to run on the +device. This replacement IS reversible. + +Quick Start +----------- + +- Build U-Boot +- Process U-Boot +- Flashing U-Boot into the eMMC +- Boot +- Self Upgrading + +Build U-Boot +------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-none-eabi- + $ make ouya_defconfig + $ make + +After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` +image, ready for further processing. + +Process U-Boot +-------------- + +``DISCLAMER!`` All questions related to the re-crypt work should be asked +in re-crypt repo issues. NOT HERE! + +re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form +usable by device. This process is required only on the first installation or +to recover the device in case of a failed update. + +Permanent installation can be performed either by using the nv3p protocol or by +pre-loading just built U-Boot into RAM. + +Processing for the NV3P protocol +******************************** + +.. code-block:: bash + + $ git clone https://gitlab.com/grate-driver/re-crypt.git + $ cd re-crypt # place your u-boot-dtb-tegra.bin here + $ ./re-crypt.py --dev ouya + +The script will produce a ``repart-block.bin`` ready to flash. + +Processing for pre-loaded U-Boot +******************************** + +The procedure is the same, but the ``--split`` argument is used with the +``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready +to flash. + +Flashing U-Boot into the eMMC +----------------------------- + +Permanent installation can be performed either by using the nv3p protocol or by +pre-loading just built U-Boot into RAM. Regardless of the method bct and bootloader +will end up in boot0 and boot1 partitions of eMMC. + +Flashing with the NV3P protocol +******************************* + +``DISCLAMER!`` All questions related to NvFlash should be asked in the proper +place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before! + +Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can +enter it by pre-loading vendor bootloader with the Fusée Gelée. + +With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in +encrypted state in form, which can just be written RAW at the start of eMMC. + +.. code-block:: bash + + $ ./run_bootloader.sh -s T30 -t ./bct/ouya.bct -b android_bootloader.bin + $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin + +When flashing is done, reboot the device. + +Flashing with a pre-loaded U-Boot +********************************* + +U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently +U-Boot supports bootmenu entry fastboot, which allows to write a processed copy +of U-Boot permanently into eMMC. + +While pre-loading U-Boot, interrupt bootflow by pressing ``CTRL + C`` (USB keyboard +must be plugged in before U-Boot is preloaded, else it will not work), input +``bootmenu`` from the keyboard and hit enter. The bootmenu will appear. There, select +``fastboot`` using the up and down arrows and enter key. After, on host PC, do: + +.. code-block:: bash + + $ fastboot flash 0.1 bct.img + $ fastboot flash 0.2 ebt.img + $ fastboot reboot + +Device will reboot. + +Boot +---- + +To boot Linux, U-Boot will look for an ``extlinux.conf`` on eMMC. Additionally, +bootmenu provides entries to mount eMMC as mass storage, fastboot, reboot, +reboot RCM, poweroff, enter U-Boot console and update bootloader (check +the next chapter). + +Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows +the user to use/partition it in any way the user desires. + +Self Upgrading +-------------- + +Place your ``u-boot-dtb-tegra.bin`` on the first partition of the USB. Enter +bootmenu, choose update bootloader option with Enter and U-Boot should update +itself. Once the process is completed, U-Boot will ask to press any button to reboot. diff --git a/include/configs/ouya.h b/include/configs/ouya.h new file mode 100644 index 00000000000..cc86c1002e3 --- /dev/null +++ b/include/configs/ouya.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2010,2012 + * NVIDIA Corporation + * + * (C) Copyright 2025 + * Svyatoslav Ryhel + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra30-common.h" + +/* High-level configuration options */ +#define CFG_TEGRA_BOARD_STRING "Ouya Game Console" + +/* Board-specific serial config */ +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/env/nvidia/prod_upd.env b/include/env/nvidia/prod_upd.env index f4e381994be..6a457d1b75b 100644 --- a/include/env/nvidia/prod_upd.env +++ b/include/env/nvidia/prod_upd.env @@ -3,6 +3,7 @@ boot_block_size=0x1000 bootloader_file=u-boot-dtb-tegra.bin spi_size=0x400000 boot_dev=0 +boot_interface=mmc flash_uboot=echo Preparing RAM; mw ${kernel_addr_r} 0 ${boot_block_size_r}; @@ -11,9 +12,9 @@ flash_uboot=echo Preparing RAM; mmc dev 0 1; mmc read ${kernel_addr_r} 0 ${boot_block_size}; echo Reading bootloader; - if load mmc ${boot_dev}:1 ${ramdisk_addr_r} ${bootloader_file}; + if load ${boot_interface} ${boot_dev}:1 ${ramdisk_addr_r} ${bootloader_file}; then echo Calculating bootloader size; - size mmc ${boot_dev}:1 ${bootloader_file}; + size ${boot_interface} ${boot_dev}:1 ${bootloader_file}; ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize}; echo Writing bootloader to eMMC; mmc dev 0 1; -- cgit v1.3.1