From 6df8029c9e744dcacfdde784c7aa556e3bfa331b Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 3 Aug 2024 10:40:38 +0200 Subject: clk: mediatek: mt7986: drop 1/1 infracfg spurious factor Now that we can have advanced parent handling for mux, we can drop spurious infracfg 1/1 factor. This is in preparation to make the clk ID match the ID in upstream include for mt7986. Drop the factor entry from mt7986-clk.h and reference to them in mt7981.dtsi. Muxes and gates are updated to reference the topckgen clk following how it's done in upstream kernel linux. Add relevant clk type flag in clk_tree for infracfg and topckgen. Signed-off-by: Christian Marangi --- arch/arm/dts/mt7986.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi index 276f82f2065..e26b85b8266 100644 --- a/arch/arm/dts/mt7986.dtsi +++ b/arch/arm/dts/mt7986.dtsi @@ -78,7 +78,7 @@ compatible = "mediatek,mt7986-timer"; reg = <0x10008000 0x1000>; interrupts = ; - clocks = <&infracfg CK_INFRA_CK_F26M>; + clocks = <&topckgen CK_TOP_F26M_SEL>; clock-names = "gpt-clk"; bootph-all; }; @@ -154,7 +154,7 @@ #clock-cells = <1>; #pwm-cells = <2>; interrupts = ; - clocks = <&infracfg CK_INFRA_PWM>, + clocks = <&topckgen CK_TOP_PWM_SEL>, <&infracfg_ao CK_INFRA_PWM_BSEL>, <&infracfg_ao CK_INFRA_PWM1_CK>, <&infracfg_ao CK_INFRA_PWM2_CK>; @@ -163,9 +163,9 @@ <&infracfg CK_INFRA_PWM1_SEL>, <&infracfg CK_INFRA_PWM2_SEL>; assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>, - <&infracfg CK_INFRA_PWM>, - <&infracfg CK_INFRA_PWM>, - <&infracfg CK_INFRA_PWM>; + <&topckgen CK_TOP_PWM_SEL>, + <&topckgen CK_TOP_PWM_SEL>, + <&topckgen CK_TOP_PWM_SEL>; clock-names = "top", "main", "pwm1", "pwm2"; status = "disabled"; bootph-all; @@ -179,7 +179,7 @@ assigned-clocks = <&topckgen CK_TOP_UART_SEL>, <&infracfg_ao CK_INFRA_UART0_SEL>; assigned-clock-parents = <&topckgen CK_TOP_XTAL>, - <&infracfg CK_INFRA_UART>; + <&topckgen CK_TOP_UART_SEL>; mediatek,force-highspeed; status = "disabled"; bootph-all; @@ -191,7 +191,7 @@ interrupts = ; clocks = <&infracfg_ao CK_INFRA_UART1_CK>; assigned-clocks = <&infracfg CK_INFRA_UART1_SEL>; - assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>; + assigned-clock-parents = <&topckgen CK_TOP_F26M_SEL>; mediatek,force-highspeed; status = "disabled"; }; @@ -202,7 +202,7 @@ interrupts = ; clocks = <&infracfg_ao CK_INFRA_UART2_CK>; assigned-clocks = <&infracfg CK_INFRA_UART2_SEL>; - assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>; + assigned-clock-parents = <&topckgen CK_TOP_F26M_SEL>; mediatek,force-highspeed; status = "disabled"; }; @@ -263,7 +263,7 @@ assigned-clocks = <&topckgen CK_TOP_SPI_SEL>, <&infracfg CK_INFRA_SPI0_SEL>; assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>, - <&topckgen CK_INFRA_ISPI0>; + <&topckgen CK_TOP_SPI_SEL>; clock-names = "sel-clk", "spi-clk"; interrupts = ; status = "disabled"; -- cgit v1.3.1