From cf8df34015fcbd6b85a8ebadd22382d68c57f4e5 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 7 Apr 2020 16:07:46 +0200 Subject: arm: stm32mp: cleanup test on eth_env_set_enetaddr result Remove the unnecessary inversion on the eth_env_set_enetaddr() result which only make complex the code of setup_mac_address() and display an invalid value in the associated pr_err. Signed-off-by: Patrick Delaunay Reviewed-by: Marek Vasut --- arch/arm/mach-stm32mp/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index b7fcee2b367..f19e5c3f33a 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -580,8 +580,8 @@ __weak int setup_mac_address(void) return -EINVAL; } pr_debug("OTP MAC address = %pM\n", enetaddr); - ret = !eth_env_set_enetaddr("ethaddr", enetaddr); - if (!ret) + ret = eth_env_set_enetaddr("ethaddr", enetaddr); + if (ret) pr_err("Failed to set mac address %pM from OTP: %d\n", enetaddr, ret); #endif -- cgit v1.3.1 From 43e2d1dd47a7e9b126659dc17a10f351e49bc53b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 22 Aug 2020 22:45:36 +0200 Subject: ARM: dts: stm32: Pull UART4 RX high on AV96 There is no dedicated pull resistor on the AV96 UART4 (console UART) pin. In case there is no UART adapter installed on the AV96, the line is floating and can trigger reception of garbage characters, which in turn can abort U-Boot autoboot. Add default pull up to mitigate this problem. Signed-off-by: Marek Vasut Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi index cb92fc9c141..1ae57e18542 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi @@ -75,6 +75,8 @@ }; pins2 { u-boot,dm-pre-reloc; + /delete-property/ bias-disable; + bias-pull-up; }; }; -- cgit v1.3.1 From b6055945d66d0f4e3b1ecb82af476232067a4ee4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 22 Aug 2020 22:45:25 +0200 Subject: ARM: dts: stm32: Adjust PLL4 settings on AV96 again PLL4Q is supplying both FDCAN and LTDC. In case HDMI is in use, the 50 MHz generated from PLL4Q cannot be divided well enough to produce accurate clock for HDMI pixel clock. Adjust it to generate 74.25 MHz instead. The PLL4P/PLL4R are generating 99 MHz instead of 100 MHz, which is in tolerance for the SDMMC. Signed-off-by: Marek Vasut Cc: Gerald Baeza Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 7529068c517..c73318488d0 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -132,11 +132,11 @@ u-boot,dm-pre-reloc; }; - /* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */ + /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>; - cfg = < 1 49 5 11 5 PQR(1,1,1) >; + cfg = < 3 98 5 7 5 PQR(1,1,1) >; u-boot,dm-pre-reloc; }; }; -- cgit v1.3.1 From 75fb7b9163b9dc01828a3a519d2de0b19a6f23f2 Mon Sep 17 00:00:00 2001 From: Mingming Lee Date: Fri, 4 Sep 2020 13:35:22 +0800 Subject: ARM: MediaTek: amend IC description for MediaTek MT8512 The description for MT8512 has some mistake, so correct it. Signed-off-by: Mingming Lee --- arch/arm/mach-mediatek/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 0042e57017f..7f40ba93190 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -47,10 +47,10 @@ config TARGET_MT8512 select ARM64 select MT8512 help - The MediaTek MT8512 is a ARM64-based SoC with a quad-core Cortex-A53. + The MediaTek MT8512 is a ARM64-based SoC with a dual-core Cortex-A53. including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM, - Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo - chip and several DDR3 and DDR4 options. + IR RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth digital + and several LPDDR3 and LPDDR4 options. config TARGET_MT8516 bool "MediaTek MT8516 SoC" -- cgit v1.3.1 From 6b9966e1aa362e97e9b33b7b82ff713f2ddea2c1 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 10 Sep 2020 07:47:39 +0200 Subject: riscv: define function set_gd() Function set_gd() is needed in the UEFI sub-system if the global data pointer is stored in a register. Signed-off-by: Heinrich Schuchardt --- arch/riscv/include/asm/global_data.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 2eb14815bcf..b711fcc44d1 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -39,4 +39,13 @@ struct arch_global_data { #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("gp") +static inline void set_gd(volatile gd_t *gd_ptr) +{ +#ifdef CONFIG_64BIT + asm volatile("ld gp, %0\n" : : "m"(gd_ptr)); +#else + asm volatile("lw gp, %0\n" : : "m"(gd_ptr)); +#endif +} + #endif /* __ASM_GBL_DATA_H */ -- cgit v1.3.1 From fe4931c09ac77c775786c12148e8fd47ce4bb833 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Mon, 13 Apr 2020 09:38:31 +0800 Subject: rockchip: rv1108: Enable grf as pre-reloc node The grf node will be used before relocate, enable it in dts. Signed-off-by: Kever Yang --- arch/arm/dts/rv1108-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/rv1108-u-boot.dtsi b/arch/arm/dts/rv1108-u-boot.dtsi index 41ac054b81e..6a2098b8d41 100644 --- a/arch/arm/dts/rv1108-u-boot.dtsi +++ b/arch/arm/dts/rv1108-u-boot.dtsi @@ -4,3 +4,7 @@ */ #include "rockchip-u-boot.dtsi" + +&grf { + u-boot,dm-pre-reloc; +}; -- cgit v1.3.1 From 5b861eea7927da63f016b75265e454a19ab19d0b Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 15 Sep 2020 03:43:29 +0200 Subject: rockchip: make_fit_atf: ignore empty PT_LOAD segment The linker sometimes creates PT_LOAD segments with length (p_filesz) zero as described in https://man7.org/linux/man-pages/man5/elf.5.html. This leads to build failures. We should ignore empty segments. Signed-off-by: Heinrich Schuchardt Tested-by: Tom Rini Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/make_fit_atf.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py index d15c32b3032..f3224d25552 100755 --- a/arch/arm/mach-rockchip/make_fit_atf.py +++ b/arch/arm/mach-rockchip/make_fit_atf.py @@ -189,8 +189,9 @@ def unpack_elf(filename): p_type, p_flags, p_offset = struct.unpack_from(' 0: + p_data = elf[p_offset:p_offset + p_filesz] + segments.append((index, e_entry, p_paddr, p_data)) return segments def main(): -- cgit v1.3.1 From 95bae9ff920b6120bd2c21437517ed99a2d54b61 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 16 Sep 2020 15:17:18 +0800 Subject: imx7: ccm: correct target interface num According to i.MX 7Dual Applications Processor Reference Manual, Rev. 1 The target interface CCM root index ranges [0,124], so the number should be 125. Reported-by: Coverity 18045 Signed-off-by: Peng Fan Reviewed-by: Ye Li --- arch/arm/include/asm/arch-mx7/crm_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h index f3515fab031..bfa68a9d2a0 100644 --- a/arch/arm/include/asm/arch-mx7/crm_regs.h +++ b/arch/arm/include/asm/arch-mx7/crm_regs.h @@ -57,7 +57,7 @@ struct mxc_ccm_reg { uint32_t reserved_0[4092]; struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */ uint32_t reserved_1[3332]; - struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */ + struct mxc_ccm_root_slice root[125]; /* offset 0x8000 */ }; -- cgit v1.3.1 From d81e8cf6eaebbb0a67857224781f6f7470785422 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 16 Sep 2020 15:17:19 +0800 Subject: imx8mq: fix FRAC_PLL_REFCLK_SEL_MASK Coverity reported dead code, however it is FRAC_PLL_REFCLK_SEL_MASK was wrongly set. Reported-by: Coverity 10045172 Signed-off-by: Peng Fan Reviewed-by: Ye Li --- arch/arm/include/asm/arch-imx8m/clock_imx8mq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h index 742cbf3bf80..7109d334fa8 100644 --- a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h @@ -316,7 +316,7 @@ enum clk_src_index { #define FRAC_PLL_LOCK_MASK BIT(31) #define FRAC_PLL_CLKE_MASK BIT(21) #define FRAC_PLL_PD_MASK BIT(19) -#define FRAC_PLL_REFCLK_SEL_MASK BIT(16) +#define FRAC_PLL_REFCLK_SEL_MASK (0x3 << 16) #define FRAC_PLL_LOCK_SEL_MASK BIT(15) #define FRAC_PLL_BYPASS_MASK BIT(14) #define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13) -- cgit v1.3.1 From ece7844d8fbd67d078e1cb2d6807b913a2025a0c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 16 Sep 2020 15:17:20 +0800 Subject: imx8mq: fix SSCG_PLL_REFCLK_SEL_x Fix SSCG_PLL_REFCLK_SEL_x, the offset starts from 0, not 16 Reported-by: Coverity 3448860 Signed-off-by: Peng Fan Reviewed-by: Ye Li --- arch/arm/include/asm/arch-imx8m/clock_imx8mq.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h index 7109d334fa8..340a61e55bd 100644 --- a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h @@ -358,10 +358,10 @@ enum clk_src_index { #define SSCG_PLL_LOCK_SEL_MASK BIT(3) #define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2) #define SSCG_PLL_REFCLK_SEL_MASK 0x3 -#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16) -#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16) -#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16) -#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16) +#define SSCG_PLL_REFCLK_SEL_OSC_25M (0) +#define SSCG_PLL_REFCLK_SEL_OSC_27M (1) +#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2) +#define SSCG_PLL_REFCLK_SEL_CLK_PN (3) #define SSCG_PLL_SSDS_MASK BIT(8) #define SSCG_PLL_SSMD_MASK (0x7 << 5) -- cgit v1.3.1 From a3e7d51fd554dd5ad18a94e32ba674b451d7e0d1 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 16 Sep 2020 15:17:21 +0800 Subject: imx8m: clock_imx8mm: add missed return Add missed return Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 3610f5b2fca..9dde11cdedf 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -360,6 +360,7 @@ void init_clk_ecspi(u32 index) clock_enable(CCGR_ECSPI2, 0); clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); clock_enable(CCGR_ECSPI2, 1); + return; case 2: clock_enable(CCGR_ECSPI3, 0); clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0)); -- cgit v1.3.1 From 0098222dacd6fd2bdc6f99adc366397a7ed8bb6a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 16 Sep 2020 15:17:22 +0800 Subject: imx8mp: Remove parts MIMX8ML7 and MIMX8ML5 support Latest datasheet revE has removed MIMX8ML7D/5D/7C/5C parts, so update u-boot to remove decoding and support for those parts. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx/cpu.h | 2 -- arch/arm/include/asm/mach-imx/sys_proto.h | 5 +---- arch/arm/mach-imx/cpu.c | 4 ---- arch/arm/mach-imx/imx8m/soc.c | 12 ++++-------- 4 files changed, 5 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 75ff991248c..f37fe214460 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -41,9 +41,7 @@ #define MXC_CPU_IMX8MNDL 0x8f /* dummy ID */ #define MXC_CPU_IMX8MNSL 0x181 /* dummy ID */ #define MXC_CPU_IMX8MP 0x182/* dummy ID */ -#define MXC_CPU_IMX8MP7 0x183 /* dummy ID */ #define MXC_CPU_IMX8MP6 0x184 /* dummy ID */ -#define MXC_CPU_IMX8MP5 0x185 /* dummy ID */ #define MXC_CPU_IMX8MPL 0x186 /* dummy ID */ #define MXC_CPU_IMX8MPD 0x187 /* dummy ID */ #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 15d1cba8e74..5f0c1ae2182 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -67,13 +67,10 @@ struct bd_info; #define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL)) #define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL)) #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \ - is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP7) || \ - is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MP5)) + is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6)) #define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD)) #define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL)) -#define is_imx8mp7() (is_cpu_type(MXC_CPU_IMX8MP7)) #define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6)) -#define is_imx8mp5() (is_cpu_type(MXC_CPU_IMX8MP5)) #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index fe8d5947cce..4a175cb86f4 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -102,12 +102,8 @@ const char *get_imx_type(u32 imxtype) return "8MP Dual[3]"; /* Dual-core version of the imx8mp */ case MXC_CPU_IMX8MPL: return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */ - case MXC_CPU_IMX8MP7: - return "8MP[7]"; /* Quad-core version of the imx8mp, VPU fused */ case MXC_CPU_IMX8MP6: return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */ - case MXC_CPU_IMX8MP5: - return "8MP[5]"; /* Quad-core version of the imx8mp, ISP fused */ case MXC_CPU_IMX8MN: return "8MNano Quad"; /* Quad-core version */ case MXC_CPU_IMX8MND: diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 8dfc8645fc0..9bca5bf9727 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -343,12 +343,8 @@ static u32 get_cpu_variant_type(u32 type) switch (flag) { case 7: return MXC_CPU_IMX8MPL; - case 6: - return MXC_CPU_IMX8MP5; case 2: return MXC_CPU_IMX8MP6; - case 1: - return MXC_CPU_IMX8MP7; default: break; } @@ -889,16 +885,16 @@ usb_modify_speed: disable_cpu_nodes(blob, 3); #elif defined(CONFIG_IMX8MP) - if (is_imx8mpl() || is_imx8mp7()) + if (is_imx8mpl()) disable_vpu_nodes(blob); - if (is_imx8mpl() || is_imx8mp6() || is_imx8mp5()) + if (is_imx8mpl() || is_imx8mp6()) disable_npu_nodes(blob); - if (is_imx8mpl() || is_imx8mp5()) + if (is_imx8mpl()) disable_isp_nodes(blob); - if (is_imx8mpl() || is_imx8mp7() || is_imx8mp6() || is_imx8mp5()) + if (is_imx8mpl() || is_imx8mp6()) disable_dsp_nodes(blob); if (is_imx8mpd()) -- cgit v1.3.1 From d1a7205532a34bad2b83451258ca4ccacb9085e4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 13 Sep 2020 01:35:08 +0200 Subject: ARM: mx6: ddr: Add support for iMX6UL/ULL/SL/SDL This patch adds support for iMX6UL/ULL/SL/SDL MMDC into the DDR calibration code. The difference between MX6DQ and MX6UL/ULL/SL is that the later SoCs have 2 SDQS registers, just like MX6SX, while the MX6DQ/MX6SDL has 8. Fixes: 4f4c128c65 ("ARM: mx6: ddr: Add support for iMX6SX") Signed-off-by: Marek Vasut Cc: Eric Nelson Cc: Fabio Estevam Cc: Stefano Babic Reviewed-by: Fabio Estevam --- arch/arm/mach-imx/mx6/ddr.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c index 16df71083db..f872bfdab31 100644 --- a/arch/arm/mach-imx/mx6/ddr.c +++ b/arch/arm/mach-imx/mx6/ddr.c @@ -250,16 +250,31 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo) static void mmdc_set_sdqs(bool set) { + struct mx6sdl_iomux_ddr_regs *mx6sdl_ddr_iomux = + (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE; struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE; struct mx6sx_iomux_ddr_regs *mx6sx_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE; + struct mx6sl_iomux_ddr_regs *mx6sl_ddr_iomux = + (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE; + struct mx6ul_iomux_ddr_regs *mx6ul_ddr_iomux = + (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE; int i, sdqs_cnt; u32 sdqs; if (is_mx6sx()) { sdqs = (u32)(&mx6sx_ddr_iomux->dram_sdqs0); sdqs_cnt = 2; + } else if (is_mx6sl()) { + sdqs = (u32)(&mx6sl_ddr_iomux->dram_sdqs0); + sdqs_cnt = 2; + } else if (is_mx6ul() || is_mx6ull()) { + sdqs = (u32)(&mx6ul_ddr_iomux->dram_sdqs0); + sdqs_cnt = 2; + } else if (is_mx6sdl()) { + sdqs = (u32)(&mx6sdl_ddr_iomux->dram_sdqs0); + sdqs_cnt = 8; } else { /* MX6DQ */ sdqs = (u32)(&mx6dq_ddr_iomux->dram_sdqs0); sdqs_cnt = 8; -- cgit v1.3.1 From 08b6a60ee8aaf0856aef86173e5b8b617f35a24a Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Fri, 28 Aug 2020 21:08:05 +0300 Subject: colibri-imx8qxp: rename all occurences to colibri-imx8x The Toradex product is called colibri-imx8x consisting of SoM with i.MX8QXP and i.MX8DX SoCs. Signed-off-by: Philippe Schenker Reviewed-by: Igor Opaniuk --- arch/arm/dts/fsl-imx8qxp-colibri.dts | 6 +- board/toradex/colibri-imx8x/MAINTAINERS | 2 +- .../colibri-imx8x/colibri-imx8qxp-imximage.cfg | 24 -------- .../colibri-imx8x/colibri-imx8x-imximage.cfg | 24 ++++++++ configs/colibri-imx8qxp_defconfig | 65 ---------------------- configs/colibri-imx8x_defconfig | 65 ++++++++++++++++++++++ doc/board/toradex/colibri-imx8x.rst | 2 +- 7 files changed, 94 insertions(+), 94 deletions(-) delete mode 100644 board/toradex/colibri-imx8x/colibri-imx8qxp-imximage.cfg create mode 100644 board/toradex/colibri-imx8x/colibri-imx8x-imximage.cfg delete mode 100644 configs/colibri-imx8qxp_defconfig create mode 100644 configs/colibri-imx8x_defconfig (limited to 'arch') diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts index 0c20edf2cf3..11ece34c024 100644 --- a/arch/arm/dts/fsl-imx8qxp-colibri.dts +++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts @@ -9,8 +9,8 @@ #include "fsl-imx8qxp-colibri-u-boot.dtsi" / { - model = "Toradex Colibri iMX8QXP"; - compatible = "toradex,colibri-imx8qxp", "fsl,imx8qxp"; + model = "Toradex Colibri iMX8X"; + compatible = "toradex,colibri-imx8x", "fsl,imx8qxp"; chosen { bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200"; @@ -32,7 +32,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>; - colibri-imx8qxp { + colibri-imx8x { pinctrl_lpuart0: lpuart0grp { fsl,pins = < SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 diff --git a/board/toradex/colibri-imx8x/MAINTAINERS b/board/toradex/colibri-imx8x/MAINTAINERS index f6853586c8b..de62f87a560 100644 --- a/board/toradex/colibri-imx8x/MAINTAINERS +++ b/board/toradex/colibri-imx8x/MAINTAINERS @@ -5,6 +5,6 @@ S: Maintained F: arch/arm/dts/fsl-imx8x-colibri.dts F: arch/arm/dts/fsl-imx8x-colibri-u-boot.dtsi F: board/toradex/colibri-imx8x/ -F: configs/colibri-imx8qxp_defconfig +F: configs/colibri-imx8x_defconfig F: doc/board/toradex/colibri-imx8x.rst F: include/configs/colibri-imx8x.h diff --git a/board/toradex/colibri-imx8x/colibri-imx8qxp-imximage.cfg b/board/toradex/colibri-imx8x/colibri-imx8qxp-imximage.cfg deleted file mode 100644 index 44f6c0c4554..00000000000 --- a/board/toradex/colibri-imx8x/colibri-imx8qxp-imximage.cfg +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 Toradex - * - * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure - * and create imx8image boot image - */ - -#define __ASSEMBLY__ - -/* Boot from SD, sector size 0x400 */ -BOOT_FROM EMMC_FASTBOOT 0x400 -/* SoC type IMX8QX */ -SOC_TYPE IMX8QX -/* Append seco container image */ -APPEND mx8qx-ahab-container.img -/* Create the 2nd container */ -CONTAINER -/* Add scfw image with exec attribute */ -IMAGE SCU mx8qx-colibri-scfw-tcm.bin -/* Add ATF image with exec attribute */ -IMAGE A35 bl31.bin 0x80000000 -/* Add U-Boot image with load attribute */ -DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/board/toradex/colibri-imx8x/colibri-imx8x-imximage.cfg b/board/toradex/colibri-imx8x/colibri-imx8x-imximage.cfg new file mode 100644 index 00000000000..44f6c0c4554 --- /dev/null +++ b/board/toradex/colibri-imx8x/colibri-imx8x-imximage.cfg @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Toradex + * + * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure + * and create imx8image boot image + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM EMMC_FASTBOOT 0x400 +/* SoC type IMX8QX */ +SOC_TYPE IMX8QX +/* Append seco container image */ +APPEND mx8qx-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qx-colibri-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 bl31.bin 0x80000000 +/* Add U-Boot image with load attribute */ +DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri-imx8qxp_defconfig deleted file mode 100644 index 719e7473e19..00000000000 --- a/configs/colibri-imx8qxp_defconfig +++ /dev/null @@ -1,65 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_IMX8=y -CONFIG_SYS_TEXT_BASE=0x80020000 -CONFIG_SYS_MALLOC_F_LEN=0x4000 -CONFIG_NR_DRAM_BANKS=3 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xFFFFDE00 -CONFIG_DM_GPIO=y -CONFIG_TARGET_COLIBRI_IMX8X=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri" -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx8x/colibri-imx8qxp-imximage.cfg" -CONFIG_LOG=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_CMD_CPU=y -# CONFIG_BOOTM_NETBSD is not set -CONFIG_CMD_ASKENV=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x88000000 -CONFIG_SYS_MEMTEST_END=0x89000000 -CONFIG_CMD_CLK=y -CONFIG_CMD_DM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_UUID=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 -CONFIG_IP_DEFRAG=y -CONFIG_TFTP_BLOCKSIZE=4096 -CONFIG_CLK_IMX8=y -CONFIG_CPU=y -CONFIG_MXC_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_IMX_LPI2C=y -CONFIG_MISC=y -CONFIG_DM_MMC=y -CONFIG_FSL_USDHC=y -CONFIG_PHYLIB=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_PHY_MICREL=y -CONFIG_DM_ETH=y -CONFIG_FEC_MXC_SHARE_MDIO=y -CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 -CONFIG_FEC_MXC=y -CONFIG_MII=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX8=y -CONFIG_POWER_DOMAIN=y -CONFIG_IMX8_POWER_DOMAIN=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_DM_SERIAL=y -CONFIG_FSL_LPUART=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_SCU_THERMAL=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig new file mode 100644 index 00000000000..92dc103ce3b --- /dev/null +++ b/configs/colibri-imx8x_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=3 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_TARGET_COLIBRI_IMX8X=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx8x/colibri-imx8x-imximage.cfg" +CONFIG_LOG=y +CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x88000000 +CONFIG_SYS_MEMTEST_END=0x89000000 +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_UUID=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_IP_DEFRAG=y +CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +# CONFIG_EFI_LOADER is not set diff --git a/doc/board/toradex/colibri-imx8x.rst b/doc/board/toradex/colibri-imx8x.rst index 244e5a4c047..616f40ae0f0 100644 --- a/doc/board/toradex/colibri-imx8x.rst +++ b/doc/board/toradex/colibri-imx8x.rst @@ -52,7 +52,7 @@ Build U-Boot .. code-block:: bash - $ make colibri-imx8qxp_defconfig + $ make colibri-imx8x_defconfig $ make u-boot-dtb.imx Load the U-Boot Binary Using UUU -- cgit v1.3.1 From bf46474e21ed353574610ea6db0375ff69965a0f Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Fri, 28 Aug 2020 21:08:06 +0300 Subject: apalis-imx8qm: rename all occurences to apalis-imx8 The Toradex product is called apalis-imx8 consisting of SoM with i.MX8QM and i.MX8QP SoCs. Signed-off-by: Philippe Schenker Reviewed-by: Igor Opaniuk --- arch/arm/dts/fsl-imx8qm-apalis.dts | 6 +- board/toradex/apalis-imx8/MAINTAINERS | 2 +- board/toradex/apalis-imx8/apalis-imx8-imximage.cfg | 24 ++++++++ .../toradex/apalis-imx8/apalis-imx8qm-imximage.cfg | 24 -------- configs/apalis-imx8_defconfig | 68 ++++++++++++++++++++++ configs/apalis-imx8qm_defconfig | 68 ---------------------- doc/board/toradex/apalix-imx8.rst | 2 +- 7 files changed, 97 insertions(+), 97 deletions(-) create mode 100644 board/toradex/apalis-imx8/apalis-imx8-imximage.cfg delete mode 100644 board/toradex/apalis-imx8/apalis-imx8qm-imximage.cfg create mode 100644 configs/apalis-imx8_defconfig delete mode 100644 configs/apalis-imx8qm_defconfig (limited to 'arch') diff --git a/arch/arm/dts/fsl-imx8qm-apalis.dts b/arch/arm/dts/fsl-imx8qm-apalis.dts index 9b1f8aa32d0..5187b794527 100644 --- a/arch/arm/dts/fsl-imx8qm-apalis.dts +++ b/arch/arm/dts/fsl-imx8qm-apalis.dts @@ -12,8 +12,8 @@ #include "fsl-imx8qm-apalis-u-boot.dtsi" / { - model = "Toradex Apalis iMX8QM"; - compatible = "toradex,apalis-imx8qm", "fsl,imx8qm"; + model = "Toradex Apalis iMX8"; + compatible = "toradex,apalis-imx8", "fsl,imx8qm"; chosen { bootargs = "console=ttyLP1,115200 earlycon=lpuart32,0x5a070000,115200"; @@ -38,7 +38,7 @@ <&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>, <&pinctrl_sim0_gpios>, <&pinctrl_usdhc1_gpios>; - apalis-imx8qm { + apalis-imx8 { pinctrl_gpio12: gpio12grp { fsl,pins = < /* Apalis GPIO1 */ diff --git a/board/toradex/apalis-imx8/MAINTAINERS b/board/toradex/apalis-imx8/MAINTAINERS index feacf7eded6..7fbd1be10f9 100644 --- a/board/toradex/apalis-imx8/MAINTAINERS +++ b/board/toradex/apalis-imx8/MAINTAINERS @@ -5,6 +5,6 @@ S: Maintained F: arch/arm/dts/fsl-imx8-apalis.dts F: arch/arm/dts/fsl-imx8-apalis-u-boot.dtsi F: board/toradex/apalis-imx8/ -F: configs/apalis-imx8qm_defconfig +F: configs/apalis-imx8_defconfig F: doc/board/toradex/apalix-imx8.rst F: include/configs/apalis-imx8.h diff --git a/board/toradex/apalis-imx8/apalis-imx8-imximage.cfg b/board/toradex/apalis-imx8/apalis-imx8-imximage.cfg new file mode 100644 index 00000000000..b8f0f3dc10f --- /dev/null +++ b/board/toradex/apalis-imx8/apalis-imx8-imximage.cfg @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Toradex + * + * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure + * and create imx8image boot image + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM EMMC_FASTBOOT 0x400 +/* SoC type IMX8QM */ +SOC_TYPE IMX8QM +/* Append seco container image */ +APPEND mx8qm-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qm-apalis-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 bl31.bin 0x80000000 +/* Add U-Boot image with load attribute */ +DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/board/toradex/apalis-imx8/apalis-imx8qm-imximage.cfg b/board/toradex/apalis-imx8/apalis-imx8qm-imximage.cfg deleted file mode 100644 index b8f0f3dc10f..00000000000 --- a/board/toradex/apalis-imx8/apalis-imx8qm-imximage.cfg +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 Toradex - * - * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure - * and create imx8image boot image - */ - -#define __ASSEMBLY__ - -/* Boot from SD, sector size 0x400 */ -BOOT_FROM EMMC_FASTBOOT 0x400 -/* SoC type IMX8QM */ -SOC_TYPE IMX8QM -/* Append seco container image */ -APPEND mx8qm-ahab-container.img -/* Create the 2nd container */ -CONTAINER -/* Add scfw image with exec attribute */ -IMAGE SCU mx8qm-apalis-scfw-tcm.bin -/* Add ATF image with exec attribute */ -IMAGE A35 bl31.bin 0x80000000 -/* Add U-Boot image with load attribute */ -DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig new file mode 100644 index 00000000000..72e58216bd4 --- /dev/null +++ b/configs/apalis-imx8_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=3 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_TARGET_APALIS_IMX8=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8/apalis-imx8-imximage.cfg" +CONFIG_LOG=y +CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x88000000 +CONFIG_SYS_MEMTEST_END=0x89000000 +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_UUID=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_IP_DEFRAG=y +CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/apalis-imx8qm_defconfig b/configs/apalis-imx8qm_defconfig deleted file mode 100644 index 5cf0e2b017b..00000000000 --- a/configs/apalis-imx8qm_defconfig +++ /dev/null @@ -1,68 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_IMX8=y -CONFIG_SYS_TEXT_BASE=0x80020000 -CONFIG_SYS_MALLOC_F_LEN=0x4000 -CONFIG_NR_DRAM_BANKS=3 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xFFFFDE00 -CONFIG_DM_GPIO=y -CONFIG_TARGET_APALIS_IMX8=y -CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-apalis" -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_OF_SYSTEM_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8/apalis-imx8qm-imximage.cfg" -CONFIG_LOG=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_CMD_CPU=y -# CONFIG_BOOTM_NETBSD is not set -CONFIG_CMD_ASKENV=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_MEMTEST_START=0x88000000 -CONFIG_SYS_MEMTEST_END=0x89000000 -CONFIG_CMD_CLK=y -CONFIG_CMD_DM=y -CONFIG_CMD_FUSE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_UUID=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 -CONFIG_IP_DEFRAG=y -CONFIG_TFTP_BLOCKSIZE=4096 -CONFIG_CLK_IMX8=y -CONFIG_CPU=y -CONFIG_MXC_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_IMX_LPI2C=y -CONFIG_MISC=y -CONFIG_DM_MMC=y -CONFIG_FSL_USDHC=y -CONFIG_PHYLIB=y -CONFIG_PHY_ADDR_ENABLE=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_DM_ETH=y -CONFIG_FEC_MXC_SHARE_MDIO=y -CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 -CONFIG_FEC_MXC=y -CONFIG_MII=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX8=y -CONFIG_POWER_DOMAIN=y -CONFIG_IMX8_POWER_DOMAIN=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_DM_SERIAL=y -CONFIG_FSL_LPUART=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_SCU_THERMAL=y -# CONFIG_EFI_LOADER is not set diff --git a/doc/board/toradex/apalix-imx8.rst b/doc/board/toradex/apalix-imx8.rst index 4b7ea65d31b..29593faf1a0 100644 --- a/doc/board/toradex/apalix-imx8.rst +++ b/doc/board/toradex/apalix-imx8.rst @@ -51,7 +51,7 @@ Build U-Boot ------------ .. code-block:: bash - $ make apalis-imx8qm_defconfig + $ make apalis-imx8_defconfig $ make u-boot-dtb.imx Load the U-Boot Binary Using UUU -- cgit v1.3.1 From 674c58c7b73db3a1e1297b87397c61e09915e7d7 Mon Sep 17 00:00:00 2001 From: Wolfgang Wallner Date: Fri, 11 Sep 2020 16:52:28 +0200 Subject: x86: fsp: Replace e-mmc with emmc in devicetree bindings The term eMMC is used inconsistently within the FSP devicetree bindings (e-mmc and emmc), especially for "emmc-host-max-speed" documentation and code disagree. Change all eMMC instances within the FSP bindings to consistently use "emmc". The term "emmc" is already used a lot within U-Boot, while "e-mmc" is only used in the FSP bindings. Signed-off-by: Wolfgang Wallner Reviewed-by: Simon Glass Reviewed-by: Bin Meng [bmeng: correct one typo in the commit message] Signed-off-by: Bin Meng --- arch/x86/cpu/apollolake/fsp_bindings.c | 6 +++--- doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt | 2 +- doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c b/arch/x86/cpu/apollolake/fsp_bindings.c index bbf04b5009f..319c78b95a3 100644 --- a/arch/x86/cpu/apollolake/fsp_bindings.c +++ b/arch/x86/cpu/apollolake/fsp_bindings.c @@ -555,7 +555,7 @@ const struct fsp_binding fsp_m_bindings[] = { }, { .type = FSP_UINT8, .offset = offsetof(struct fsp_m_config, e_mmc_trace_len), - .propname = "fspm,e-mmc-trace-len", + .propname = "fspm,emmc-trace-len", }, { .type = FSP_UINT8, .offset = offsetof(struct fsp_m_config, skip_cse_rbp), @@ -1465,11 +1465,11 @@ const struct fsp_binding fsp_s_bindings[] = { }, { .type = FSP_UINT8, .offset = offsetof(struct fsp_s_config, e_mmc_enabled), - .propname = "fsps,e-mmc-enabled", + .propname = "fsps,emmc-enabled", }, { .type = FSP_UINT8, .offset = offsetof(struct fsp_s_config, e_mmc_host_max_speed), - .propname = "fsps,e-mmc-host-max-speed", + .propname = "fsps,emmc-host-max-speed", }, { .type = FSP_UINT8, .offset = offsetof(struct fsp_s_config, ufs_enabled), diff --git a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt index 666400e0858..36936f2eb60 100644 --- a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt +++ b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt @@ -174,7 +174,7 @@ Optional properties: - fspm,oem-loading-base: OEM File Loading Address - fspm,oem-file-name: OEM File Name to Load - fspm,mrc-boot-data-ptr: -- fspm,e-mmc-trace-len: eMMC Trace Length +- fspm,emmc-trace-len: eMMC Trace Length 0x0: Long 0x1: Short - fspm,skip-cse-rbp: Skip CSE RBP to support zero sized IBB diff --git a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt index 731a310cf89..b605ed00565 100644 --- a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt +++ b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt @@ -318,7 +318,7 @@ Optional properties: 0x6: warm reset (default) 0xE: cold reset - fsps,sdcard-enabled: SD Card Support (D27:F0) -- fsps,e-mmc-enabled: SeMMC Support (D28:F0) +- fsps,emmc-enabled: SeMMC Support (D28:F0) - fsps,emmc-host-max-speed: eMMC Max Speed 0: HS400(default) 1: HS200 -- cgit v1.3.1 From 3f6966ab2b9a2264c05d699353e61b276b1a85bd Mon Sep 17 00:00:00 2001 From: Wolfgang Wallner Date: Wed, 16 Sep 2020 16:57:52 +0200 Subject: x86: acpi: Fix calculation of DSDT length Currently, the calculation for the length of the DSDT table includes any bytes that are added for alignment, but those bytes are not initialized. This is because the DSDT length is calculated after a call to acpi_inc_align(). Split this up into the following sequence: * acpi_inc() * Calculate DSDT length * acpi_align() Signed-off-by: Wolfgang Wallner Reviewed-by: Andy Shevchenko Reviewed-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/lib/acpi_table.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 3a93fedfc3e..6b827bfa3f6 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -427,7 +427,7 @@ ulong write_acpi_tables(ulong start_addr) (char *)&AmlCode + sizeof(struct acpi_table_header), dsdt->length - sizeof(struct acpi_table_header)); - acpi_inc_align(ctx, dsdt->length - sizeof(struct acpi_table_header)); + acpi_inc(ctx, dsdt->length - sizeof(struct acpi_table_header)); /* Pack GNVS into the ACPI table area */ for (i = 0; i < dsdt->length; i++) { @@ -450,6 +450,8 @@ ulong write_acpi_tables(ulong start_addr) dsdt->checksum = 0; dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length); + acpi_align(ctx); + /* * Fill in platform-specific global NVS variables. If this fails we * cannot return the error but this should only happen while debugging. -- cgit v1.3.1 From 40edea3a07ebb89e86c9bde8c94000c8f6613be7 Mon Sep 17 00:00:00 2001 From: Wolfgang Wallner Date: Wed, 16 Sep 2020 16:57:53 +0200 Subject: x86: acpi: Add memset to initialize SPCR table Add a missing memset to acpi_create_spcr(). The other acpi_create_xxxx() functions perform a memset on their structures, acpi_create_spcr() does not and as a result the contents of this table are partly uninitialized (and thus random after every reset). Fixes: b288cd960072 ("x86: acpi: Generate SPCR table") Signed-off-by: Wolfgang Wallner Reviewed-by: Andy Shevchenko Reviewed-by: Simon Glass Reviewed-by: Bin Meng [bmeng: fix the tags format in the commit message] Signed-off-by: Bin Meng --- arch/x86/lib/acpi_table.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 6b827bfa3f6..c445aa68703 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -252,6 +252,8 @@ static void acpi_create_spcr(struct acpi_spcr *spcr) int space_id; int ret = -ENODEV; + memset((void *)spcr, 0, sizeof(struct acpi_spcr)); + /* Fill out header fields */ acpi_fill_header(header, "SPCR"); header->length = sizeof(struct acpi_spcr); -- cgit v1.3.1