From b515d7ae0de51a26f73b2ddb5ea4db0d95b67d7a Mon Sep 17 00:00:00 2001 From: Jonas Schwöbel Date: Mon, 22 Jan 2024 14:40:27 +0200 Subject: Tegra30: Add funcmux for UART over SD slot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tegra 3 has UART-E exposable via SD card slot which may be handy for debugging. This change only adds funcmux part, to use UART-E on the device you additionally would need: - set stdout-path to serial@70006400 (uarte) - configure sdmmc1_dat3_py4 and sdmmc1_dat2_py5 pinmux for uarte - disable or remove sdhci@7800000 node - enable CONFIG_TEGRA_ENABLE_UARTE in defconfig - set CFG_SYS_NS16550_COM to NV_PA_APB_UARTE_BASE in device header Signed-off-by: Jonas Schwöbel Signed-off-by: Svyatoslav Ryhel --- arch/arm/include/asm/arch-tegra30/funcmux.h | 1 + arch/arm/mach-tegra/board.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra30/funcmux.h b/arch/arm/include/asm/arch-tegra30/funcmux.h index 2e8b3359161..05414061a23 100644 --- a/arch/arm/include/asm/arch-tegra30/funcmux.h +++ b/arch/arm/include/asm/arch-tegra30/funcmux.h @@ -16,5 +16,6 @@ enum { /* UART configs */ FUNCMUX_UART1_ULPI = 0, + FUNCMUX_UART5_SDMMC1 = 1, }; #endif /* _TEGRA30_FUNCMUX_H_ */ diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index c382e042860..be739c75877 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -181,7 +181,7 @@ static int uart_configs[] = { -1, -1, -1, - -1, + FUNCMUX_UART5_SDMMC1, /* UARTE */ #elif defined(CONFIG_TEGRA114) -1, -1, -- cgit v1.3.1 From 539800bf9257d637831d3e8dfa04f95cdc43fa58 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 3 Aug 2024 20:01:29 +0300 Subject: ARM: tegra: board2: add common dtb reselect logic Add common logic for dynamic dtb switch and DM reload if board features multi-dtb support. Signed-off-by: Svyatoslav Ryhel --- arch/arm/mach-tegra/board2.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 5c5838629b2..1704b021c5a 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -457,3 +458,18 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); } + +#if IS_ENABLED(CONFIG_DTB_RESELECT) +int embedded_dtb_select(void) +{ + int ret, rescan; + + ret = fdtdec_resetup(&rescan); + if (!ret && rescan) { + dm_uninit(); + dm_init_and_scan(true); + } + + return 0; +} +#endif -- cgit v1.3.1 From d7c98f20307b8e50ffc8dc9aab305bb7fb6e76f2 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 2 Aug 2024 15:51:41 +0300 Subject: ARM: tegra-u-boot: add recipe for multi-dtb image Buildman has difficulties with constructing multi-dtb images, so let's add a temporary custom recipe for it. Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/tegra-u-boot.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/tegra-u-boot.dtsi b/arch/arm/dts/tegra-u-boot.dtsi index b3d0dec7757..c200f2d3a0b 100644 --- a/arch/arm/dts/tegra-u-boot.dtsi +++ b/arch/arm/dts/tegra-u-boot.dtsi @@ -19,6 +19,27 @@ }; }; +#ifdef CONFIG_MULTI_DTB_FIT + image2 { + filename = "u-boot-dtb-tegra.bin"; + pad-byte = <0xff>; + u-boot-spl { + }; + u-boot-nodtb { + offset = <(U_BOOT_OFFSET)>; + }; + fit-dtb { +#ifdef CONFIG_MULTI_DTB_FIT_LZO + filename = "fit-dtb.blob.lzo"; +#elif CONFIG_MULTI_DTB_FIT_GZIP + filename = "fit-dtb.blob.gz"; +#else + filename = "fit-dtb.blob"; +#endif + type = "blob"; + }; + }; +#else /* Same as image1 - some tools still expect the -dtb suffix */ image2 { filename = "u-boot-dtb-tegra.bin"; @@ -29,6 +50,7 @@ offset = <(U_BOOT_OFFSET)>; }; }; +#endif image3 { filename = "u-boot-nodtb-tegra.bin"; -- cgit v1.3.1 From 2b323dce572e8c3ab686841b2fe99a3f1d0b143f Mon Sep 17 00:00:00 2001 From: Ion Agorria Date: Thu, 3 Oct 2024 10:52:12 +0300 Subject: arm: tegra: fix typo in logging functions Change %02X to %02x since it always displayed 00 otherwise. Signed-off-by: Ion Agorria Signed-off-by: Svyatoslav Ryhel --- arch/arm/mach-tegra/ap.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index 1ea620e4ab5..a9875227da0 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -32,7 +32,7 @@ int tegra_get_chip(void) * Tegra30, 0x35 for T114, and 0x40 for Tegra124. */ rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; - debug("%s: CHIPID is 0x%02X\n", __func__, rev); + debug("%s: CHIPID is 0x%02x\n", __func__, rev); return rev; } @@ -43,7 +43,7 @@ int tegra_get_sku_info(void) struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; sku_id = readl(&fuse->sku_info) & 0xff; - debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id); + debug("%s: SKU info byte is 0x%02x\n", __func__, sku_id); return sku_id; } @@ -103,8 +103,8 @@ int tegra_get_chip_sku(void) } /* unknown chip/sku id */ - printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n", - __func__, chip_id, sku_id); + printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02x/0x%02x)\n", + __func__, chip_id, sku_id); return TEGRA_SOC_UNKNOWN; } -- cgit v1.3.1 From 539633805d0c6aa9ee5f4dbc89dcef18d13174ba Mon Sep 17 00:00:00 2001 From: Ion Agorria Date: Tue, 24 Sep 2024 21:46:45 +0200 Subject: arm: tegra: add AP20 and AP20H SKU Add previously undocumented SKU - AP20H found in LG Optimus 2X (P990). Correct existing T20_7 name as it's proper name is AP20. Signed-off-by: Ion Agorria Signed-off-by: Svyatoslav Ryhel --- arch/arm/include/asm/arch-tegra/tegra.h | 3 ++- arch/arm/mach-tegra/ap.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index 7a4e0972fb7..a399c94213b 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -68,8 +68,9 @@ struct timerus { /* These are the available SKUs (product types) for Tegra */ enum { - SKU_ID_T20_7 = 0x7, + SKU_ID_AP20 = 0x7, SKU_ID_T20 = 0x8, + SKU_ID_AP20H = 0xf, SKU_ID_T25SE = 0x14, SKU_ID_AP25 = 0x17, SKU_ID_T25 = 0x18, diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index a9875227da0..f35bdba4d48 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -58,8 +58,9 @@ int tegra_get_chip_sku(void) switch (chip_id) { case CHIPID_TEGRA20: switch (sku_id) { - case SKU_ID_T20_7: + case SKU_ID_AP20: case SKU_ID_T20: + case SKU_ID_AP20H: return TEGRA_SOC_T20; case SKU_ID_T25SE: case SKU_ID_AP25: -- cgit v1.3.1 From 43800d7f6d7e38ecfd12889276851b1d1a9fc07f Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Thu, 17 Aug 2023 20:15:18 +0300 Subject: usb: host: tegra: get usb phy configuration from phy node Obtain USB phy configuration from phy node if such exists and is enabled. If no, set default values. Signed-off-by: Svyatoslav Ryhel --- arch/arm/include/asm/arch-tegra/usb.h | 11 ++- drivers/usb/host/ehci-tegra.c | 136 ++++++++++++++++++++++++++++------ 2 files changed, 121 insertions(+), 26 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h index 6e6ea1443cb..2ae109ab6c1 100644 --- a/arch/arm/include/asm/arch-tegra/usb.h +++ b/arch/arm/include/asm/arch-tegra/usb.h @@ -336,10 +336,13 @@ struct usb_ctlr { #define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25 #define UTMIP_XCVR_HSSLEW_MSB_MASK \ (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT) -#define UTMIP_XCVR_SETUP_MSB_SHIFT 22 -#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT) -#define UTMIP_XCVR_SETUP_SHIFT 0 -#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT) + +#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) +#define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22) +#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) +#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) +#define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4) +#define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25) /* USBx_UTMIP_XCVR_CFG1_0 */ #define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18 diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 343893b9f19..7c73eb66b60 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -66,9 +66,24 @@ enum usb_ctlr_type { USB_CTRL_COUNT, }; +struct tegra_utmip_config { + u32 hssync_start_delay; + u32 elastic_limit; + u32 idle_wait_delay; + u32 term_range_adj; + bool xcvr_setup_use_fuses; + u32 xcvr_setup; + u32 xcvr_lsfslew; + u32 xcvr_lsrslew; + u32 xcvr_hsslew; + u32 hssquelch_level; + u32 hsdiscon_level; +}; + /* Information about a USB port */ struct fdt_usb { struct ehci_ctrl ehci; + struct tegra_utmip_config utmip_config; struct usb_ctlr *reg; /* address of registers in physical memory */ unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ @@ -192,15 +207,6 @@ static const unsigned T210_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 65000, 5 } }; -/* UTMIP Idle Wait Delay */ -static const u8 utmip_idle_wait_delay = 17; - -/* UTMIP Elastic limit */ -static const u8 utmip_elastic_limit = 16; - -/* UTMIP High Speed Sync Start Delay */ -static const u8 utmip_hs_sync_start_delay = 9; - struct fdt_usb_controller { /* flag to determine whether controller supports hostpc register */ u32 has_hostpc:1; @@ -377,6 +383,7 @@ static int init_utmi_usb_controller(struct fdt_usb *config, u32 b_sess_valid_mask, val; int loop_count; const unsigned *timing; + struct tegra_utmip_config *utmip_config = &config->utmip_config; struct usb_ctlr *usbctlr = config->reg; struct clk_rst_ctlr *clkrst; struct usb_ctlr *usb1ctlr; @@ -463,16 +470,29 @@ static int init_utmi_usb_controller(struct fdt_usb *config, /* Recommended PHY settings for EYE diagram */ val = readl(&usbctlr->utmip_xcvr_cfg0); - clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, - 0x4 << UTMIP_XCVR_SETUP_SHIFT); - clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, - 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); - clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, - 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); + + if (!utmip_config->xcvr_setup_use_fuses) { + clrsetbits_le32(&val, UTMIP_XCVR_SETUP(~0), + UTMIP_XCVR_SETUP(utmip_config->xcvr_setup)); + clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB(~0), + UTMIP_XCVR_SETUP_MSB(utmip_config->xcvr_setup)); + } + + clrsetbits_le32(&val, UTMIP_XCVR_LSFSLEW(~0), + UTMIP_XCVR_LSFSLEW(utmip_config->xcvr_lsfslew)); + clrsetbits_le32(&val, UTMIP_XCVR_LSRSLEW(~0), + UTMIP_XCVR_LSRSLEW(utmip_config->xcvr_lsrslew)); + + clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW(~0), + UTMIP_XCVR_HSSLEW(utmip_config->xcvr_hsslew)); + clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB(~0), + UTMIP_XCVR_HSSLEW_MSB(utmip_config->xcvr_hsslew)); writel(val, &usbctlr->utmip_xcvr_cfg0); + clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_XCVR_TERM_RANGE_ADJ_MASK, - 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); + utmip_config->term_range_adj << + UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); /* Some registers can be controlled from USB1 only. */ if (config->periph_id != PERIPH_ID_USBD) { @@ -485,9 +505,11 @@ static int init_utmi_usb_controller(struct fdt_usb *config, val = readl(&usb1ctlr->utmip_bias_cfg0); setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, - 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); + utmip_config->hsdiscon_level << + UTMIP_HSDISCON_LEVEL_SHIFT); clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, - 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); + utmip_config->hssquelch_level << + UTMIP_HSSQUELCH_LEVEL_SHIFT); writel(val, &usb1ctlr->utmip_bias_cfg0); /* Miscellaneous setting mentioned in Programming Guide */ @@ -521,7 +543,11 @@ static int init_utmi_usb_controller(struct fdt_usb *config, setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); - setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); + + if (utmip_config->xcvr_setup_use_fuses) + setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); + else + clrbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); /* * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT @@ -535,15 +561,16 @@ static int init_utmi_usb_controller(struct fdt_usb *config, /* Set PLL enable delay count and Crystal frequency count */ val = readl(&usbctlr->utmip_hsrx_cfg0); clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, - utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); + utmip_config->idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, - utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); + utmip_config->elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); writel(val, &usbctlr->utmip_hsrx_cfg0); /* Configure the UTMIP_HS_SYNC_START_DLY */ clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, UTMIP_HS_SYNC_START_DLY_MASK, - utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); + utmip_config->hssync_start_delay << + UTMIP_HS_SYNC_START_DLY_SHIFT); /* Preceed the crystal clock disable by >100ns delay. */ udelay(1); @@ -763,6 +790,69 @@ static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config) return 0; } +static void fdt_decode_usb_phy(struct udevice *dev) +{ + struct fdt_usb *priv = dev_get_priv(dev); + struct tegra_utmip_config *utmip_config = &priv->utmip_config; + u32 usb_phy_phandle; + ofnode usb_phy_node; + int ret; + + ret = ofnode_read_u32(dev_ofnode(dev), "nvidia,phy", &usb_phy_phandle); + if (ret) + log_debug("%s: required usb phy node isn't provided\n", __func__); + + usb_phy_node = ofnode_get_by_phandle(usb_phy_phandle); + if (!ofnode_valid(usb_phy_node) || !ofnode_is_enabled(usb_phy_node)) { + log_debug("%s: failed to find usb phy node or it is disabled\n", __func__); + utmip_config->xcvr_setup_use_fuses = true; + } else { + utmip_config->xcvr_setup_use_fuses = + ofnode_read_bool(usb_phy_node, "nvidia,xcvr-setup-use-fuses"); + } + + utmip_config->hssync_start_delay = + ofnode_read_u32_default(usb_phy_node, + "nvidia,hssync-start-delay", 0x9); + + utmip_config->elastic_limit = + ofnode_read_u32_default(usb_phy_node, + "nvidia,elastic-limit", 0x10); + + utmip_config->idle_wait_delay = + ofnode_read_u32_default(usb_phy_node, + "nvidia,idle-wait-delay", 0x11); + + utmip_config->term_range_adj = + ofnode_read_u32_default(usb_phy_node, + "nvidia,term-range-adj", 0x7); + + utmip_config->xcvr_lsfslew = + ofnode_read_u32_default(usb_phy_node, + "nvidia,xcvr-lsfslew", 0x0); + + utmip_config->xcvr_lsrslew = + ofnode_read_u32_default(usb_phy_node, + "nvidia,xcvr-lsrslew", 0x3); + + utmip_config->xcvr_hsslew = + ofnode_read_u32_default(usb_phy_node, + "nvidia,xcvr-hsslew", 0x8); + + utmip_config->hssquelch_level = + ofnode_read_u32_default(usb_phy_node, + "nvidia,hssquelch-level", 0x2); + + utmip_config->hsdiscon_level = + ofnode_read_u32_default(usb_phy_node, + "nvidia,hsdiscon-level", 0x1); + + if (!utmip_config->xcvr_setup_use_fuses) { + ofnode_read_u32(usb_phy_node, "nvidia,xcvr-setup", + &utmip_config->xcvr_setup); + } +} + int usb_common_init(struct fdt_usb *config, enum usb_init_type init) { int ret = 0; @@ -850,6 +940,8 @@ static int ehci_usb_of_to_plat(struct udevice *dev) priv->type = dev_get_driver_data(dev); + fdt_decode_usb_phy(dev); + return 0; } -- cgit v1.3.1