From 8900e2bbecd021b16eee7c344cd6ca0e1ee901f3 Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Tue, 14 Feb 2023 20:42:49 +0800 Subject: riscv: Rename Andes cpu and board names The current ae350-related defconfigs could also support newer Andes CPU IP, so modify the names of CPU from ax25 to andesv5, and board name from ax25-ae350 to ae350. Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin Reviewed-by: Rick Chen --- arch/riscv/Kconfig | 8 +-- arch/riscv/cpu/andesv5/Kconfig | 15 +++++ arch/riscv/cpu/andesv5/Makefile | 8 +++ arch/riscv/cpu/andesv5/cache.c | 130 ++++++++++++++++++++++++++++++++++++++++ arch/riscv/cpu/andesv5/cpu.c | 50 ++++++++++++++++ arch/riscv/cpu/andesv5/spl.c | 27 +++++++++ arch/riscv/cpu/ax25/Kconfig | 15 ----- arch/riscv/cpu/ax25/Makefile | 8 --- arch/riscv/cpu/ax25/cache.c | 130 ---------------------------------------- arch/riscv/cpu/ax25/cpu.c | 50 ---------------- arch/riscv/cpu/ax25/spl.c | 27 --------- arch/riscv/dts/Makefile | 2 +- 12 files changed, 235 insertions(+), 235 deletions(-) create mode 100644 arch/riscv/cpu/andesv5/Kconfig create mode 100644 arch/riscv/cpu/andesv5/Makefile create mode 100644 arch/riscv/cpu/andesv5/cache.c create mode 100644 arch/riscv/cpu/andesv5/cpu.c create mode 100644 arch/riscv/cpu/andesv5/spl.c delete mode 100644 arch/riscv/cpu/ax25/Kconfig delete mode 100644 arch/riscv/cpu/ax25/Makefile delete mode 100644 arch/riscv/cpu/ax25/cache.c delete mode 100644 arch/riscv/cpu/ax25/cpu.c delete mode 100644 arch/riscv/cpu/ax25/spl.c (limited to 'arch') diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ebc4bef220e..48ca4ff4c4e 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -8,8 +8,8 @@ choice prompt "Target select" optional -config TARGET_AX25_AE350 - bool "Support ax25-ae350" +config TARGET_AE350 + bool "Support ae350" config TARGET_MICROCHIP_ICICLE bool "Support Microchip PolarFire-SoC Icicle Board" @@ -58,7 +58,7 @@ config SPL_SYS_DCACHE_OFF Do not enable data cache in SPL. # board-specific options below -source "board/AndesTech/ax25-ae350/Kconfig" +source "board/AndesTech/ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/unleashed/Kconfig" @@ -67,7 +67,7 @@ source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" # platform-specific options below -source "arch/riscv/cpu/ax25/Kconfig" +source "arch/riscv/cpu/andesv5/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andesv5/Kconfig new file mode 100644 index 00000000000..82bb5a2a532 --- /dev/null +++ b/arch/riscv/cpu/andesv5/Kconfig @@ -0,0 +1,15 @@ +config RISCV_NDS + bool + select ARCH_EARLY_INIT_R + imply CPU + imply CPU_RISCV + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE) + imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE) + imply V5L2_CACHE + imply SPL_CPU + imply SPL_OPENSBI + imply SPL_LOAD_FIT + help + Run U-Boot on AndeStar V5 platforms and use some specific features + which are provided by Andes Technology AndeStar V5 families. diff --git a/arch/riscv/cpu/andesv5/Makefile b/arch/riscv/cpu/andesv5/Makefile new file mode 100644 index 00000000000..35a1a2fb836 --- /dev/null +++ b/arch/riscv/cpu/andesv5/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2017 Andes Technology Corporation +# Rick Chen, Andes Technology Corporation + +obj-y := cpu.o +obj-y += cache.o +obj-y += spl.o diff --git a/arch/riscv/cpu/andesv5/cache.c b/arch/riscv/cpu/andesv5/cache.c new file mode 100644 index 00000000000..40d77f671c8 --- /dev/null +++ b/arch/riscv/cpu/andesv5/cache.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_V5L2_CACHE +void enable_caches(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CACHE, + DM_DRIVER_GET(v5l2_cache), + &dev); + if (ret) { + log_debug("Cannot enable v5l2 cache\n"); + } else { + ret = cache_enable(dev); + if (ret) + log_debug("v5l2 cache enable failed\n"); + } +} + +static void cache_ops(int (*ops)(struct udevice *dev)) +{ + struct udevice *dev = NULL; + + uclass_find_first_device(UCLASS_CACHE, &dev); + + if (dev) + ops(dev); +} +#endif + +void flush_dcache_all(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); +#endif +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + flush_dcache_all(); +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ + flush_dcache_all(); +} + +void icache_enable(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrsi %0, 0x1" :: "i"(CSR_MCACHE_CTL)); +#endif +} + +void icache_disable(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrci %0, 0x1" :: "i"(CSR_MCACHE_CTL)); +#endif +} + +void dcache_enable(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL)); +#endif + +#ifdef CONFIG_V5L2_CACHE + cache_ops(cache_enable); +#endif +} + +void dcache_disable(void) +{ +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL)); +#endif + +#ifdef CONFIG_V5L2_CACHE + cache_ops(cache_disable); +#endif +} + +int icache_status(void) +{ + int ret = 0; + +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile ( + "csrr t1, %1\n\t" + "andi %0, t1, 0x01\n\t" + : "=r" (ret) + : "i"(CSR_MCACHE_CTL) + : "memory" + ); +#endif + + return !!ret; +} + +int dcache_status(void) +{ + int ret = 0; + +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile ( + "csrr t1, %1\n\t" + "andi %0, t1, 0x02\n\t" + : "=r" (ret) + : "i" (CSR_MCACHE_CTL) + : "memory" + ); +#endif + + return !!ret; +} diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c new file mode 100644 index 00000000000..06e379bcb1f --- /dev/null +++ b/arch/riscv/cpu/andesv5/cpu.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ + +/* CPU specific code */ +#include +#include +#include +#include +#include +#include + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + + cache_flush(); + + return 0; +} + +void harts_early_init(void) +{ + /* Enable I/D-cache in SPL */ + if (CONFIG_IS_ENABLED(RISCV_MMODE)) { + unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); + + mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN | + MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN); + + csr_write(CSR_MCACHE_CTL, mcache_ctl_val); + + /* + * Check mcache_ctl.DC_COHEN, we assume this platform does + * not support CM if the bit is hard-wired to 0. + */ + if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) { + /* Wait for DC_COHSTA bit to be set */ + while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)); + } + } +} diff --git a/arch/riscv/cpu/andesv5/spl.c b/arch/riscv/cpu/andesv5/spl.c new file mode 100644 index 00000000000..413849043b1 --- /dev/null +++ b/arch/riscv/cpu/andesv5/spl.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if CONFIG_IS_ENABLED(RAM_SUPPORT) +struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) +{ + return (void *)(CONFIG_SPL_LOAD_FIT_ADDRESS + offset); +} + +void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) +{ + return spl_get_load_buffer(0, sectors * bl_len); +} +#endif diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig deleted file mode 100644 index 82bb5a2a532..00000000000 --- a/arch/riscv/cpu/ax25/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -config RISCV_NDS - bool - select ARCH_EARLY_INIT_R - imply CPU - imply CPU_RISCV - imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) - imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE) - imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE) - imply V5L2_CACHE - imply SPL_CPU - imply SPL_OPENSBI - imply SPL_LOAD_FIT - help - Run U-Boot on AndeStar V5 platforms and use some specific features - which are provided by Andes Technology AndeStar V5 families. diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/ax25/Makefile deleted file mode 100644 index 35a1a2fb836..00000000000 --- a/arch/riscv/cpu/ax25/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2017 Andes Technology Corporation -# Rick Chen, Andes Technology Corporation - -obj-y := cpu.o -obj-y += cache.o -obj-y += spl.o diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c deleted file mode 100644 index 40d77f671c8..00000000000 --- a/arch/riscv/cpu/ax25/cache.c +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2023 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_V5L2_CACHE -void enable_caches(void) -{ - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_CACHE, - DM_DRIVER_GET(v5l2_cache), - &dev); - if (ret) { - log_debug("Cannot enable v5l2 cache\n"); - } else { - ret = cache_enable(dev); - if (ret) - log_debug("v5l2 cache enable failed\n"); - } -} - -static void cache_ops(int (*ops)(struct udevice *dev)) -{ - struct udevice *dev = NULL; - - uclass_find_first_device(UCLASS_CACHE, &dev); - - if (dev) - ops(dev); -} -#endif - -void flush_dcache_all(void) -{ -#if CONFIG_IS_ENABLED(RISCV_MMODE) - csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); -#endif -} - -void flush_dcache_range(unsigned long start, unsigned long end) -{ - flush_dcache_all(); -} - -void invalidate_dcache_range(unsigned long start, unsigned long end) -{ - flush_dcache_all(); -} - -void icache_enable(void) -{ -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile("csrsi %0, 0x1" :: "i"(CSR_MCACHE_CTL)); -#endif -} - -void icache_disable(void) -{ -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile("csrci %0, 0x1" :: "i"(CSR_MCACHE_CTL)); -#endif -} - -void dcache_enable(void) -{ -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL)); -#endif - -#ifdef CONFIG_V5L2_CACHE - cache_ops(cache_enable); -#endif -} - -void dcache_disable(void) -{ -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL)); -#endif - -#ifdef CONFIG_V5L2_CACHE - cache_ops(cache_disable); -#endif -} - -int icache_status(void) -{ - int ret = 0; - -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, %1\n\t" - "andi %0, t1, 0x01\n\t" - : "=r" (ret) - : "i"(CSR_MCACHE_CTL) - : "memory" - ); -#endif - - return !!ret; -} - -int dcache_status(void) -{ - int ret = 0; - -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, %1\n\t" - "andi %0, t1, 0x02\n\t" - : "=r" (ret) - : "i" (CSR_MCACHE_CTL) - : "memory" - ); -#endif - - return !!ret; -} diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c deleted file mode 100644 index 06e379bcb1f..00000000000 --- a/arch/riscv/cpu/ax25/cpu.c +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2023 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ - -/* CPU specific code */ -#include -#include -#include -#include -#include -#include - -/* - * cleanup_before_linux() is called just before we call linux - * it prepares the processor for linux - * - * we disable interrupt and caches. - */ -int cleanup_before_linux(void) -{ - disable_interrupts(); - - cache_flush(); - - return 0; -} - -void harts_early_init(void) -{ - /* Enable I/D-cache in SPL */ - if (CONFIG_IS_ENABLED(RISCV_MMODE)) { - unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); - - mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN | - MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN); - - csr_write(CSR_MCACHE_CTL, mcache_ctl_val); - - /* - * Check mcache_ctl.DC_COHEN, we assume this platform does - * not support CM if the bit is hard-wired to 0. - */ - if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) { - /* Wait for DC_COHSTA bit to be set */ - while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)); - } - } -} diff --git a/arch/riscv/cpu/ax25/spl.c b/arch/riscv/cpu/ax25/spl.c deleted file mode 100644 index 413849043b1..00000000000 --- a/arch/riscv/cpu/ax25/spl.c +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2023 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if CONFIG_IS_ENABLED(RAM_SUPPORT) -struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) -{ - return (void *)(CONFIG_SPL_LOAD_FIT_ADDRESS + offset); -} - -void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) -{ - return spl_get_load_buffer(0, sectors * bl_len); -} -#endif diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 5c15a0f303a..c576c55767f 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb -- cgit v1.3.1