From 9c18c695f820198c37aad812ce82e6a78195051e Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Feb 2022 13:38:39 -0500 Subject: armv8: fsl-layerscape: Respect Kconfig for erratum A009007 There is a Kconfig for this erratum, but it is ignored for armv8. Respect it. Signed-off-by: Sean Anderson Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index d3a5cfaac19..926f8f21b63 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -206,6 +206,9 @@ static void erratum_a008997(void) static void erratum_a009007(void) { + if (!IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A009007)) + return; + #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ defined(CONFIG_ARCH_LS1012A) void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1; -- cgit v1.3.1 From 881284b36a3785328ac611bab4aedd9a2a8563e6 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 22 Apr 2022 14:01:36 +0530 Subject: arm: layerscape: Disable erratum A009007 on LS1021A, LS1043A, and LS1046A This erratum is reported to cause problems on these processors [1-3]. The problem is usually with the clocking, which is supposed to be configured by the RCW [4]. However, if it is not set, or if the default clocking is not correct, then this erratum will cause an SError. However, according to Ran Wang in [1]: " ... this erratum is used to pass USB compliance test only, you could disable this workaround on your board if you don't any USB issue on normal use case, I think it's fine." So just disable this erratum by default for these processors. [1] https://lore.kernel.org/all/761ddd61-05c1-d9b8-ac90-b8f425afde6c@denx.de/ [2] https://community.nxp.com/t5/Layerscape/LS1046A-U-BOOT-HALT-AT-ERRATUM-A0090078/m-p/742993 [3] https://community.nxp.com/t5/QorIQ/Why-does-the-LS1043A-U-Boot-hang-at-code-that-fixes-erratum/m-p/644412 [4] https://source.codeaurora.org/external/qoriq/qoriq-components/rcw/tree/ls1046ardb/usb_phy_freq.rcw Signed-off-by: Sean Anderson Acked-by: Ran Wang [Rebased] Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv7/ls102xa/Kconfig | 1 - arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 -- 2 files changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index ef1f45650f3..c496e643919 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -7,7 +7,6 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A008407 select SYS_FSL_ERRATUM_A008850 if SYS_FSL_DDR select SYS_FSL_ERRATUM_A008997 if USB - select SYS_FSL_ERRATUM_A009007 if USB select SYS_FSL_ERRATUM_A009008 if USB select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009798 if USB diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 5ea99c459ce..dd953803dcd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -74,7 +74,6 @@ config ARCH_LS1043A select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008850 if !TFABOOT select SYS_FSL_ERRATUM_A008997 - select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009660 if !TFABOOT select SYS_FSL_ERRATUM_A009663 if !TFABOOT @@ -112,7 +111,6 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A008511 if !TFABOOT select SYS_FSL_ERRATUM_A008850 if !TFABOOT select SYS_FSL_ERRATUM_A008997 - select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009801 -- cgit v1.3.1 From eb217200efab6c400f96fb039474dcc840bb8404 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 28 Feb 2022 13:48:37 +0100 Subject: armv8: include psci_update_dt() unconditionally psci_update_dt() is also required if CONFIG_ARMV8_PSCI is set, that is, if u-boot is the PSCI provider. Guard the check which is intended to call into the PSCI implementation in the secure firmware, by the proper macro SEC_FIRMWARE_ARMV8_PSCI. Mark the function as weak because - unfortunately - there is already a stub of the same function in arch/arm/mach-rmobile/psci-r8a779a0.c which does not the same as the common one. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/cpu-dt.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c index 61c38b17cbf..9bfe3815e51 100644 --- a/arch/arm/cpu/armv8/cpu-dt.c +++ b/arch/arm/cpu/armv8/cpu-dt.c @@ -8,9 +8,9 @@ #include #include #include +#include -#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) -int psci_update_dt(void *fdt) +__weak int psci_update_dt(void *fdt) { /* * If the PSCI in SEC Firmware didn't work, avoid to update the @@ -18,8 +18,10 @@ int psci_update_dt(void *fdt) * number to support detecting PSCI dynamically and then switching * the SMP boot method between PSCI and spin-table. */ - if (sec_firmware_support_psci_version() == PSCI_INVALID_VER) + if (CONFIG_IS_ENABLED(SEC_FIRMWARE_ARMV8_PSCI) && + sec_firmware_support_psci_version() == PSCI_INVALID_VER) return 0; + fdt_psci(fdt); #if defined(CONFIG_ARMV8_PSCI) && !defined(CONFIG_ARMV8_SECURE_BASE) @@ -30,4 +32,3 @@ int psci_update_dt(void *fdt) return 0; } -#endif -- cgit v1.3.1 From cb14cc8867cde068aa798375ba14eaef12cff6c4 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 22 Apr 2022 14:53:27 +0530 Subject: armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle [Rebased] Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 + arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 49 ++++++++++++------------------- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 11 ++----- arch/arm/cpu/armv8/sec_firmware.c | 19 +++++------- 4 files changed, 31 insertions(+), 49 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index dd953803dcd..6f8d5cb72fd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -333,6 +333,7 @@ menu "Layerscape architecture" config FSL_LAYERSCAPE bool + select ARM_SMCCC config HAS_FEATURE_GIC64K_ALIGN bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index cf469804c51..a71ee636afe 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -768,7 +769,7 @@ enum boot_src __get_boot_src(u32 porsr1) enum boot_src get_boot_src(void) { - struct pt_regs regs; + struct arm_smccc_res res; u32 porsr1 = 0; #if defined(CONFIG_FSL_LSCH3) @@ -778,11 +779,9 @@ enum boot_src get_boot_src(void) #endif if (current_el() == 2) { - regs.regs[0] = SIP_SVC_RCW; - - smc_call(®s); - if (!regs.regs[0]) - porsr1 = regs.regs[1]; + arm_smccc_smc(SIP_SVC_RCW, 0, 0, 0, 0, 0, 0, 0, &res); + if (!res.a0) + porsr1 = res.a1; } if (current_el() == 3 || !porsr1) { @@ -1081,9 +1080,9 @@ static void config_core_prefetch(void) char *buf = NULL; char buffer[HWCONFIG_BUFFER_SIZE]; const char *prefetch_arg = NULL; + struct arm_smccc_res res; size_t arglen; unsigned int mask; - struct pt_regs regs; if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; @@ -1101,11 +1100,10 @@ static void config_core_prefetch(void) } #define SIP_PREFETCH_DISABLE_64 0xC200FF13 - regs.regs[0] = SIP_PREFETCH_DISABLE_64; - regs.regs[1] = mask; - smc_call(®s); + arm_smccc_smc(SIP_PREFETCH_DISABLE_64, mask, 0, 0, 0, 0, 0, 0, + &res); - if (regs.regs[0]) + if (res.a0) printf("Prefetch disable config failed for mask "); else printf("Prefetch disable config passed for mask "); @@ -1345,25 +1343,20 @@ phys_size_t get_effective_memsize(void) #ifdef CONFIG_TFABOOT phys_size_t tfa_get_dram_size(void) { - struct pt_regs regs; - phys_size_t dram_size = 0; - - regs.regs[0] = SMC_DRAM_BANK_INFO; - regs.regs[1] = -1; + struct arm_smccc_res res; - smc_call(®s); - if (regs.regs[0]) + arm_smccc_smc(SMC_DRAM_BANK_INFO, -1, 0, 0, 0, 0, 0, 0, &res); + if (res.a0) return 0; - dram_size = regs.regs[1]; - return dram_size; + return res.a1; } static int tfa_dram_init_banksize(void) { int i = 0, ret = 0; - struct pt_regs regs; phys_size_t dram_size = tfa_get_dram_size(); + struct arm_smccc_res res; debug("dram_size %llx\n", dram_size); @@ -1371,19 +1364,15 @@ static int tfa_dram_init_banksize(void) return -EINVAL; do { - regs.regs[0] = SMC_DRAM_BANK_INFO; - regs.regs[1] = i; - - smc_call(®s); - if (regs.regs[0]) { + arm_smccc_smc(SMC_DRAM_BANK_INFO, i, 0, 0, 0, 0, 0, 0, &res); + if (res.a0) { ret = -EINVAL; break; } - debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1], - regs.regs[2]); - gd->bd->bi_dram[i].start = regs.regs[1]; - gd->bd->bi_dram[i].size = regs.regs[2]; + debug("bank[%d]: start %lx, size %lx\n", i, res.a1, res.a2); + gd->bd->bi_dram[i].start = res.a1; + gd->bd->bi_dram[i].size = res.a2; dram_size -= gd->bd->bi_dram[i].size; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index 2e2688eadca..72221191493 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -302,6 +302,7 @@ int cpu_release(u32 nr, int argc, char *const argv[]) u64 boot_addr; u64 *table = get_spin_tbl_addr(); int pos; + int ret; boot_addr = simple_strtoull(argv[0], NULL, 16); @@ -326,16 +327,10 @@ int cpu_release(u32 nr, int argc, char *const argv[]) asm volatile("sev"); } else { /* Use PSCI to kick the core */ - struct pt_regs regs; - printf("begin to kick cpu core #%d to address %llx\n", nr, boot_addr); - regs.regs[0] = PSCI_0_2_FN64_CPU_ON; - regs.regs[1] = nr; - regs.regs[2] = boot_addr; - regs.regs[3] = 0; - smc_call(®s); - if (regs.regs[0]) + ret = invoke_psci_fn(PSCI_0_2_FN64_CPU_ON, nr, boot_addr, 0); + if (ret) return -1; } diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index 267894fbcb3..7e6e4064ffe 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -374,29 +375,25 @@ bool sec_firmware_support_hwrng(void) */ int sec_firmware_get_random(uint8_t *rand, int bytes) { + struct arm_smccc_res res; unsigned long long num; - struct pt_regs regs; int param1; if (!bytes || bytes > 8) { printf("Max Random bytes genration supported is 8\n"); return -1; } -#define SIP_RNG_64 0xC200FF11 - regs.regs[0] = SIP_RNG_64; - if (bytes <= 4) param1 = 0; else param1 = 1; - regs.regs[1] = param1; - - smc_call(®s); - if (regs.regs[0]) +#define SIP_RNG_64 0xC200FF11 + arm_smccc_smc(SIP_RNG_64, param1, 0, 0, 0, 0, 0, 0, &res); + if (res.a0) return -1; - num = regs.regs[1]; + num = res.a1; memcpy(rand, &num, bytes); return 0; @@ -473,8 +470,8 @@ int fdt_fixup_kaslr(void *fdt) return 0; } - ret = sec_firmware_get_random(rand, 8); - if (ret < 0) { + err = sec_firmware_get_random(rand, 8); + if (err < 0) { printf("WARNING: No random number to set kaslr-seed\n"); return 0; } -- cgit v1.3.1 From de58ac49a5d941a053008bf395c862efc34b5595 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 28 Feb 2022 13:48:39 +0100 Subject: armv8: psci: skip setup code if we are not EL3 If we are running in EL2 skip PSCI implementation setup. This avoids an exception if CONFIG_ARMV8_PSCI is set, but u-boot is started by TF-A. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/cpu.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c index ea40c55dd2c..db5d460eb46 100644 --- a/arch/arm/cpu/armv8/cpu.c +++ b/arch/arm/cpu/armv8/cpu.c @@ -79,6 +79,9 @@ static void relocate_secure_section(void) void armv8_setup_psci(void) { + if (current_el() != 3) + return; + relocate_secure_section(); secure_ram_addr(psci_setup_vectors)(); secure_ram_addr(psci_arch_init)(); -- cgit v1.3.1 From 49bb245f1dc447152a80b522cce7b964e0972517 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 28 Feb 2022 13:48:40 +0100 Subject: armv8: psci: add ARMV8_PSCI_RELOCATE Kconfig option There is an user-selectable SYS_HAS_ARMV8_SECURE_BASE, which has the same meaning but is just for the ls1043ardb board. As no in-tree config uses this, drop it and replace it with something more sophiticated: ARMV8_PSCI_RELOCATE. This option will then enable the ARMV8_SECURE_BASE option which is used as the base to relocate the PSCI code (or any code in the secure region, but that is only PSCI). A SoC (or board) can now opt-in into having such a secure region by enabling SYS_HAS_ARMV8_SECURE_BASE. Enable it for the LS1043A SoC, where it was possible to relocate the PSCI code before as well as on the LS1028A SoC where there will be PSCI support soon. Additionally, make ARMV8_PSCI and SEC_FIRMWARE_ARMV8_PSCI exclusive. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/Kconfig | 30 +++++++++++++++++++----------- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 ++ board/freescale/ls1043ardb/Kconfig | 8 -------- 3 files changed, 21 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 4d4469c8843..09f3f50fa22 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -90,6 +90,7 @@ config SPL_RECOVER_DATA_SECTION config SEC_FIRMWARE_ARMV8_PSCI bool "PSCI implementation in secure monitor firmware" depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT + depends on ARMV8_PSCI=n help This config enables the ARMv8 PSCI implementation in secure monitor firmware. This is a private PSCI implementation and different from @@ -131,6 +132,9 @@ config PSCI_RESET Select Y here to make use of PSCI calls for system reset +config SYS_HAS_ARMV8_SECURE_BASE + bool + config ARMV8_PSCI bool "Enable PSCI support" if EXPERT help @@ -158,23 +162,27 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER A value 0 or no definition of it works for single cluster system. System with multi-cluster should difine their own exact value. -config ARMV8_EA_EL3_FIRST - bool "External aborts and SError interrupt exception are taken in EL3" +config ARMV8_PSCI_RELOCATE + bool "Relocate PSCI code" + depends on ARMV8_PSCI + depends on SYS_HAS_ARMV8_SECURE_BASE help - Exception handling at all exception levels for External Abort and - SError interrupt exception are taken in EL3. - -if SYS_HAS_ARMV8_SECURE_BASE + Relocate PSCI code, for example to a secure memory on the SoC. If not + set, the PSCI sections are placed together with the u-boot and the + regions will be marked as reserved before linux is started. config ARMV8_SECURE_BASE hex "Secure address for PSCI image" - depends on ARMV8_PSCI + depends on ARMV8_PSCI_RELOCATE + default 0x18000000 if ARCH_LS1028A help Address for placing the PSCI text, data and stack sections. - If not defined, the PSCI sections are placed together with the u-boot - but platform can choose to place PSCI code image separately in other - places such as some secure RAM built-in SOC etc. -endif + +config ARMV8_EA_EL3_FIRST + bool "External aborts and SError interrupt exception are taken in EL3" + help + Exception handling at all exception levels for External Abort and + SError interrupt exception are taken in EL3. endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 6f8d5cb72fd..80a1642447d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -55,6 +55,7 @@ config ARCH_LS1028A select SYS_FSL_ERRATUM_A011334 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND select RESV_RAM if GIC_V3_ITS + select SYS_HAS_ARMV8_SECURE_BASE imply PANIC_HANG config ARCH_LS1043A @@ -90,6 +91,7 @@ config ARCH_LS1043A select SYS_I2C_MXC_I2C2 if !DM_I2C select SYS_I2C_MXC_I2C3 if !DM_I2C select SYS_I2C_MXC_I2C4 if !DM_I2C + select SYS_HAS_ARMV8_SECURE_BASE imply CMD_PCI imply ID_EEPROM diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig index 778b8d8d5a5..d66c7804b13 100644 --- a/board/freescale/ls1043ardb/Kconfig +++ b/board/freescale/ls1043ardb/Kconfig @@ -13,14 +13,6 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1043ardb" -config SYS_HAS_ARMV8_SECURE_BASE - bool "Enable secure address for PSCI image" - depends on ARMV8_PSCI - help - PSCI image can be re-located to secure RAM. - If enabled, please also define the value for ARMV8_SECURE_BASE, - for LS1043ARDB, it could be some address in OCRAM. - if FSL_LS_PPA config SYS_LS_PPA_FW_ADDR hex "PPA Firmware Addr" -- cgit v1.3.1 From aaaa1be8f043ff9412f9c35c62a05bcf218eda34 Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Wed, 9 Mar 2022 15:37:22 +0800 Subject: armv8: layerscape: fix the function mismatch issue Signed-off-by: Yuantian Tang Reviewed-by: Andre Przywara Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 2fb4e404a24..87410c73a92 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2014-2015 Freescale Semiconductor - * Copyright 2019 NXP + * Copyright 2019-2022 NXP * * Extracted from armv8/start.S */ @@ -344,7 +344,7 @@ ENTRY(fsl_ocram_clear_ecc_err) ldr x0, =DCSR_DCFG_MBEESR2 str w1, [x0] ret -ENDPROC(fsl_ocram_init) +ENDPROC(fsl_ocram_clear_ecc_err) #endif #ifdef CONFIG_FSL_LSCH3 -- cgit v1.3.1 From 3b06577ab4eefd954348f1dc0f5abb3408d10d0c Mon Sep 17 00:00:00 2001 From: Stephen Carlson Date: Tue, 29 Mar 2022 14:51:10 -0700 Subject: armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index fad7a935662..181bd9c1b4e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -147,10 +147,14 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, cfg >>= sd_prctl_shift; cfg = serdes_get_number(sd, cfg); - printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); + if (cfg == 0) { + printf("SERDES%d is disabled\n", sd + 1); + } else { + printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); - if (!is_serdes_prtcl_valid(sd, cfg)) - printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); + if (!is_serdes_prtcl_valid(sd, cfg)) + printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); + } for (lane = 0; lane < SRDS_MAX_LANES; lane++) { enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); -- cgit v1.3.1 From 2dcf776ebcf7f224f2a2e6720e863aca493a5cd9 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Mon, 25 Apr 2022 09:29:08 +0530 Subject: powerpc: mpc85xx: Drop _start symbol MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit _start symbol contains only 32-bit data number 0x27051956 despite it is marked as text section. This magic number is IH_MAGIC which is used for marking uboot image header. mpc85xx start.S code does not define valid uboot image header, so IH_MAGIC number in _start symbol is useless there. Moreover this _start symbol is not used at all. Entry point is at symbol _start_e500. So because this _start symbol is not used for anything, completely remove it with IH_MAGIC number. After _start symbol was _start_cont symbol, so replace all relative address calculations by _start_cont. Signed-off-by: Pali Rohár [Rebased] Signed-off-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/start.S | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 9ddd3711190..07e855e89b4 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -46,7 +46,6 @@ GOT_ENTRY(_FIXUP_TABLE_) #ifndef MINIMAL_SPL - GOT_ENTRY(_start) GOT_ENTRY(_start_of_vectors) GOT_ENTRY(_end_of_vectors) GOT_ENTRY(transfer_to_handler) @@ -1128,16 +1127,12 @@ switch_as: /*--------------------------------------------------------------*/ lis r3,CONFIG_VAL(SYS_MONITOR_BASE)@h ori r3,r3,CONFIG_VAL(SYS_MONITOR_BASE)@l - addi r3,r3,_start_cont - _start + addi r3,r3,_start_cont - _start_cont mtlr r3 blr #endif .text - .globl _start -_start: - .long 0x27051956 /* U-BOOT Magic Number */ - .globl _start_cont _start_cont: /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ @@ -1604,7 +1599,7 @@ relocate_code: * initialization, now running from RAM. */ - addi r0,r10,in_ram - _start + addi r0,r10,in_ram - _start_cont /* * As IVPR is going to point RAM address, -- cgit v1.3.1 From de14a5a95c14b0a5349c430ea35b8b07975f7ce5 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Sun, 3 Apr 2022 00:05:09 +0200 Subject: powerpc: mpc85xx: Rename _start_e500 symbol to _start MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The real entry point is _start_e500. There is no _start symbol at all. So rename _start_e500 to _start for convension that _start symbol is used as entry point. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/resetvec.S | 2 +- arch/powerpc/cpu/mpc85xx/start.S | 4 ++-- arch/powerpc/cpu/mpc85xx/u-boot.lds | 2 +- doc/README.mpc85xx | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/resetvec.S b/arch/powerpc/cpu/mpc85xx/resetvec.S index 29555d4a009..9a552f6624e 100644 --- a/arch/powerpc/cpu/mpc85xx/resetvec.S +++ b/arch/powerpc/cpu/mpc85xx/resetvec.S @@ -1,2 +1,2 @@ .section .resetvec,"ax" - b _start_e500 + b _start diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 07e855e89b4..2b2ad973599 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -70,9 +70,9 @@ */ .section .bootpg,"ax" - .globl _start_e500 + .globl _start -_start_e500: +_start: /* Enable debug exception */ li r1,MSR_DE mtmsr r1 diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 22bbac51aa3..17a0e631ca3 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -16,7 +16,7 @@ #endif OUTPUT_ARCH(powerpc) -ENTRY(_start_e500) +ENTRY(_start) PHDRS { diff --git a/doc/README.mpc85xx b/doc/README.mpc85xx index 8464e7f4d8a..3c6ebbdb0e6 100644 --- a/doc/README.mpc85xx +++ b/doc/README.mpc85xx @@ -45,7 +45,7 @@ Note: Sequence number is in order of execution A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot 1) TLB entry to overcome e500 v1/v2 debug restriction - Location : Label "_start_e500" + Location : Label "_start" TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE Properties : 256K, AS0, I, IPROT @@ -91,7 +91,7 @@ A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot 1) TLB entry to overcome e500 v1/v2 debug restriction - Location : Label "_start_e500" + Location : Label "_start" TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB #if defined(CONFIG_NXP_ESBC) EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW -- cgit v1.3.1 From efd9914ffa05dc89f7d2830267b27ba2f06ecad1 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Sun, 3 Apr 2022 00:05:10 +0200 Subject: powerpc: mpc85xx: Show e500 core version MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Distinguish between e500v1 and e500v2. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index cc1d02df811..a82516a75bd 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -143,8 +143,10 @@ int checkcpu (void) printf("Core: "); switch(ver) { case PVR_VER_E500_V1: + puts("e500v1"); + break; case PVR_VER_E500_V2: - puts("e500"); + puts("e500v2"); break; case PVR_VER_E500MC: puts("e500mc"); -- cgit v1.3.1 From 77b0c4a6c6eeab642107c6d5051b8484db7cf723 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Sun, 3 Apr 2022 00:42:25 +0200 Subject: powerpc: dts: p2020: Add fsl/p2020si-pre.dtsi and fsl/p2020si-post.dtsi symlinks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit P2020 DTS files in upstream Linux kernel use fsl/p2020si-pre.dtsi and fsl/p2020si-post.dtsi include device tree files. Add symlinks for these include device tree files into U-Boot powerpc directory and points them to U-Boot inline device tree files p2020.dtsi and p2020-post.dtsi. This allows to use P2020 DTS files from upstream Linux kernel in U-Boot. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/fsl/p2020si-post.dtsi | 1 + arch/powerpc/dts/fsl/p2020si-pre.dtsi | 1 + 2 files changed, 2 insertions(+) create mode 120000 arch/powerpc/dts/fsl/p2020si-post.dtsi create mode 120000 arch/powerpc/dts/fsl/p2020si-pre.dtsi (limited to 'arch') diff --git a/arch/powerpc/dts/fsl/p2020si-post.dtsi b/arch/powerpc/dts/fsl/p2020si-post.dtsi new file mode 120000 index 00000000000..b51ebf58b7a --- /dev/null +++ b/arch/powerpc/dts/fsl/p2020si-post.dtsi @@ -0,0 +1 @@ +../p2020-post.dtsi \ No newline at end of file diff --git a/arch/powerpc/dts/fsl/p2020si-pre.dtsi b/arch/powerpc/dts/fsl/p2020si-pre.dtsi new file mode 120000 index 00000000000..1e4b16fbe46 --- /dev/null +++ b/arch/powerpc/dts/fsl/p2020si-pre.dtsi @@ -0,0 +1 @@ +../p2020.dtsi \ No newline at end of file -- cgit v1.3.1 From cfbf84330f2669a8c6570aec71e2af0ad2ea055b Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Sun, 3 Apr 2022 00:42:26 +0200 Subject: powerpc: dts: p2020: Add serial0 and serial1 via pq3-duart-0.dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Import pq3-duart-0.dtsi device tree include file from upstream Linux kernel for P2020. This allows U-Boot to use P2020 device tree files from upstream Linux kernel which reference serial0 or serial1 devices. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 1 + arch/powerpc/dts/pq3-duart-0.dtsi | 51 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) create mode 100644 arch/powerpc/dts/pq3-duart-0.dtsi (limited to 'arch') diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 6d46f7d8dd7..8d30fa212c4 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -49,6 +49,7 @@ /include/ "pq3-i2c-0.dtsi" /include/ "pq3-i2c-1.dtsi" +/include/ "pq3-duart-0.dtsi" /include/ "pq3-etsec1-0.dtsi" /include/ "pq3-etsec1-1.dtsi" diff --git a/arch/powerpc/dts/pq3-duart-0.dtsi b/arch/powerpc/dts/pq3-duart-0.dtsi new file mode 100644 index 00000000000..5e268fdb9d1 --- /dev/null +++ b/arch/powerpc/dts/pq3-duart-0.dtsi @@ -0,0 +1,51 @@ +/* + * PQ3 DUART device tree stub [ controller @ offset 0x4000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 2 0 0>; +}; + +serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <42 2 0 0>; +}; -- cgit v1.3.1 From 7d1d31db91d897380bbbd88d448ddb72f8e816a2 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Tue, 5 Apr 2022 11:15:21 +0200 Subject: powerpc: dts: p2020: Add localbus node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This node is required for NAND and NOR support. Node is taken from the upstream Linux kernel DTS file. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 7 +++++++ arch/powerpc/dts/p2020rdb-pc.dts | 4 ++++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 4 ++++ 3 files changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 8d30fa212c4..0a9e81a4248 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -85,3 +85,10 @@ device_type = "pci"; bus-range = <0x0 0xff>; }; + +&lbc { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus"; + interrupts = <19 2 0 0>; +}; diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts index b37931ac449..67fa340d09d 100644 --- a/arch/powerpc/dts/p2020rdb-pc.dts +++ b/arch/powerpc/dts/p2020rdb-pc.dts @@ -15,6 +15,10 @@ #size-cells = <2>; interrupt-parent = <&mpic>; + lbc: localbus@ffe05000 { + reg = <0 0xffe05000 0 0x1000>; + }; + soc: soc@ffe00000 { ranges = <0x0 0x0 0xffe00000 0x100000>; }; diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts index ecdc022d997..6f251960031 100644 --- a/arch/powerpc/dts/p2020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts @@ -15,6 +15,10 @@ #size-cells = <2>; interrupt-parent = <&mpic>; + lbc: localbus@fffe05000 { + reg = <0xf 0xffe05000 0 0x1000>; + }; + soc: soc@fffe00000 { ranges = <0x0 0xf 0xffe00000 0x100000>; }; -- cgit v1.3.1 From 74b7d69e613ac8fb7dcc21ea5248237e60b2cf1e Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Tue, 5 Apr 2022 11:23:25 +0200 Subject: powerpc: dts: p1020/p2020: Fix esdhc node name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For compatibility with Linux kernel DTS files and also with other U-Boot powerpc DTS files, rename esdhc@2e000 node to sdhc@2e000 in p1020-post.dtsi and p2020-post.dtsi include files. Linux kernel DTS files which include these dtsi files, expect that esdhc node has name sdhc@2e000 and do not work with other node names. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p1020-post.dtsi | 2 +- arch/powerpc/dts/p2020-post.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index 03b68869918..668ca0fa07e 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -37,7 +37,7 @@ last-interrupt-source = <255>; }; - esdhc: esdhc@2e000 { + esdhc: sdhc@2e000 { compatible = "fsl,esdhc"; reg = <0x2e000 0x1000>; /* Filled in by U-Boot */ diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 0a9e81a4248..6debae7720a 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -31,7 +31,7 @@ last-interrupt-source = <255>; }; - esdhc: esdhc@2e000 { + esdhc: sdhc@2e000 { compatible = "fsl,esdhc"; reg = <0x2e000 0x1000>; /* Filled in by U-Boot */ -- cgit v1.3.1 From e8c0e0064c8a7b0665fd1393c2e3266f80e884a8 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Tue, 5 Apr 2022 15:12:30 +0200 Subject: powerpc: mpc85xx: Fix CONFIG_OF_SEPARATE support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently CONFIG_OF_SEPARATE is completely broken and U-Boot for some mpc85xx board (e.g. P2020) has to be compiled with CONFIG_OF_EMBED. Otherwise it crashes during early init. When debug console is enabled and all debug logging options are turned on then U-Boot on P2020 with CONFIG_OF_SEPARATE prints following error: No valid device tree binary found at 110dc300 initcall sequence 110d3560 failed at call 1109535c (err=-1) ### ERROR ### Please RESET the board ### Problem is with appended DTB. When CONFIG_SYS_MPC85XX_NO_RESETVEC is set U-Boot binary image without DTB ends immediately after the .u_boot_list section. At this position is defined _end symbol at which U-Boot expects start of the appended DTB. Problem is that after .u_boot_list section are in linker script defined another sections with 256 byte long padding which are completely empty. During conversion of U-Boot ELF binary to RAW binary u-boot-nodtb.bin, objcopy removes trailing zero padding and therefore DTB is appended at wrong position. Changing alignment from 256 bytes to 4 bytes fixes this issue. And appended DTB is finally at he correct position. With this fix U-Boot on P2020 with CONFIG_OF_SEPARATE option starts working again. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/u-boot.lds | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 17a0e631ca3..48509dbdae0 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -75,11 +75,11 @@ SECTIONS __ex_table : { *(__ex_table) } __stop___ex_table = .; - . = ALIGN(256); + . = ALIGN(4); __init_begin = .; .text.init : { *(.text.init) } .data.init : { *(.data.init) } - . = ALIGN(256); + . = ALIGN(4); __init_end = .; _end = .; -- cgit v1.3.1 From 0038f2362a24478a6c9a7fb186887851f2b32512 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Mon, 25 Apr 2022 09:32:03 +0530 Subject: powerpc: mpc85xx: Remove u-boot-nand_spl.lds MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit mpc85xx SPL NAND linker script u-boot-nand_spl.lds is not used since Jun 2014 commit 0234446fd171 ("nand_spl: remove MPC8536DS support"). Remove it. Signed-off-by: Pali Rohár [Rebased] Signed-off-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds | 68 ---------------------------- 1 file changed, 68 deletions(-) delete mode 100644 arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds deleted file mode 100644 index a2193bf7680..00000000000 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de - * - * Copyright 2009 Freescale Semiconductor, Inc. - */ - -#include "config.h" - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - . = 0xfff00000; - .text : { - *(.text*) - } - _etext = .; - - .reloc : { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - . = ALIGN(8); - .data : { - *(.rodata*) - *(.data*) - *(.sdata*) - } - _edata = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN(8); - __init_begin = .; - __init_end = .; - _end = .; -#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ - .bootpg ADDR(.text) + 0x1000 : - { - start.o (.bootpg) - } -#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */ -#elif defined(CONFIG_FSL_ELBC) -#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */ -#else -#error unknown NAND controller -#endif - .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : { - KEEP(*(.resetvec)) - } = 0xffff - - __bss_start = .; - .bss : { - *(.sbss*) - *(.bss*) - } - __bss_end = .; -} -ASSERT(__init_end <= (0xfff00000 + RESET_VECTOR_OFFSET), "NAND bootstrap too big"); -- cgit v1.3.1 From ab37df9d221e12adf709c7391c001b9dd5d33606 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Mon, 25 Apr 2022 14:21:20 +0530 Subject: powerpc: mpc85xx: Remove duplicate u-boot-nand.lds Signed-off-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/u-boot-nand.lds | 97 -------------------------------- configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 - configs/P1010RDB-PA_NAND_defconfig | 2 - configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 - configs/P1010RDB-PB_NAND_defconfig | 2 - configs/P1020RDB-PC_36BIT_NAND_defconfig | 2 - configs/P1020RDB-PC_NAND_defconfig | 2 - configs/P1020RDB-PD_NAND_defconfig | 2 - configs/P2020RDB-PC_36BIT_NAND_defconfig | 2 - configs/P2020RDB-PC_NAND_defconfig | 2 - configs/T1024RDB_NAND_defconfig | 2 - configs/T1042D4RDB_NAND_defconfig | 2 - configs/T2080QDS_NAND_defconfig | 2 - configs/T2080RDB_NAND_defconfig | 2 - configs/T2080RDB_revD_NAND_defconfig | 2 - include/configs/P1010RDB.h | 4 ++ include/configs/T102xRDB.h | 3 + include/configs/T104xRDB.h | 3 + include/configs/T208xQDS.h | 3 + include/configs/T208xRDB.h | 3 + include/configs/p1_p2_rdb_pc.h | 4 ++ 21 files changed, 20 insertions(+), 125 deletions(-) delete mode 100644 arch/powerpc/cpu/mpc85xx/u-boot-nand.lds (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds deleted file mode 100644 index 75b0285e4e5..00000000000 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009-2012 Freescale Semiconductor, Inc. - */ - -#include "config.h" - -#ifndef CONFIG_SYS_MONITOR_LEN -#define CONFIG_SYS_MONITOR_LEN 0x80000 -#endif - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -PHDRS -{ - text PT_LOAD; - bss PT_LOAD; -} - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .text : - { - *(.text*) - } :text - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } :text - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - _end = .; - - .bootpg ADDR(.text) - 0x1000 : - { - KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) - } :text = 0xffff - - . = ADDR(.text) + CONFIG_SYS_MONITOR_LEN; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss*) - *(.bss*) - *(COMMON) - } :bss - - . = ALIGN(4); - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index de67892a456..b44264f41d6 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -16,8 +16,6 @@ CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_PHYS_64BIT=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index c980adffffc..9cb7f55ecf4 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -15,8 +15,6 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index ac56d416670..67659cfc906 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -16,8 +16,6 @@ CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_PHYS_64BIT=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 0954e76bb80..18215d8f358 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -15,8 +15,6 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index f739ca0977f..56b984e5ae6 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -16,8 +16,6 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_PHYS_64BIT=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index be29f9eac4f..00d847d50af 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -15,8 +15,6 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 38e5633f82c..0d713624d48 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -15,8 +15,6 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 905b1edc2b2..e167468ed38 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -16,8 +16,6 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_PHYS_64BIT=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 5b140525f02..29d90c91400 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -15,8 +15,6 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index a5d80c9857b..c86c5c15309 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -14,8 +14,6 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T1024RDB=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 1ec838aaa0f..978c6c0bb65 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -11,8 +11,6 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T1042D4RDB=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 4721795c5eb..f5fc3e19b58 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -18,8 +18,6 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080QDS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index bef6fe8f59a..1c73bfb3d01 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -17,8 +17,6 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index 10f7e2cd18b..e9d78e92c95 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -18,8 +18,6 @@ CONFIG_TARGET_T2080RDB=y CONFIG_T2080RDB_REV_D=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 0d8f13eeb06..0c19b92940e 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -81,6 +81,10 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 +#else +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #define CONFIG_SPL_PAD_TO 0x20000 #define CONFIG_TPL_PAD_TO 0x20000 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index bedd931b186..e7cc39e78a9 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -36,6 +36,9 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #ifdef CONFIG_SPIFLASH diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 8ef6068cb91..de31f695c60 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -40,6 +40,9 @@ #endif #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #ifdef CONFIG_SPIFLASH diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 5a338f743a3..82e0fc46c7b 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -44,6 +44,9 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #ifdef CONFIG_SPIFLASH diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 3c13905729a..94385443253 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -39,6 +39,9 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #ifdef CONFIG_SPIFLASH diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 17b9021fbf8..81dc0177c0c 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -111,6 +111,10 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 +#else +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif /* not CONFIG_TPL_BUILD */ #define CONFIG_SPL_PAD_TO 0x20000 -- cgit v1.3.1 From c45f000f294e096f6f5060bd528b65d14f6c6f12 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Tue, 5 Apr 2022 15:12:33 +0200 Subject: powerpc: mpc85xx: Remove useless SIZEOF_HEADERS and .interp from ld script MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit .interp section is not available in output ELF binary and SIZEOF_HEADERS is needed at all. There is no change in generated u-boot.bin binary. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/u-boot.lds | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 48509dbdae0..565d5deb530 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -27,8 +27,6 @@ PHDRS SECTIONS { /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } .text : { *(.text*) -- cgit v1.3.1 From 1b780b654f20055f40a049da4f2ef12207757690 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Tue, 5 Apr 2022 15:12:34 +0200 Subject: powerpc: mpc85xx: Put bss after image when not including reset vector MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Linker knows exact size of the image, so there is no need to use CONFIG_SYS_MONITOR_LEN macro (which should be upper limit). Remove usage of CONFIG_SYS_MONITOR_LEN macro to simplify setup. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/u-boot.lds | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 565d5deb530..9d0f0d58d80 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -11,10 +11,6 @@ #define RESET_VECTOR_ADDRESS 0xfffffffc #endif -#ifndef CONFIG_SYS_MONITOR_LEN -#define CONFIG_SYS_MONITOR_LEN 0x80000 -#endif - OUTPUT_ARCH(powerpc) ENTRY(_start) @@ -86,7 +82,7 @@ SECTIONS { KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) } :text = 0xffff - . = ADDR(.text) + CONFIG_SYS_MONITOR_LEN; + . = _end; #else .bootpg RESET_VECTOR_ADDRESS - 0xffc : { -- cgit v1.3.1 From 1245c6e2582cb67db2a84e60a61cfe5a8d77e068 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Tue, 5 Apr 2022 15:12:35 +0200 Subject: powerpc: mpc85xx: Define linker sections in ascending order MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is too confusing if sections are defined in non-ascending order. Also linker has to go backward and then again forward when generating final binary. To make future changes easier, define all linker sections in ascending order. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 20 +++++++++++--------- arch/powerpc/cpu/mpc85xx/u-boot.lds | 15 ++++++++------- 2 files changed, 19 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 27a5fe6306a..1b4d1e05a4a 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -18,6 +18,13 @@ PHDRS #endif SECTIONS { +/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */ +#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC + .bootpg IMAGE_TEXT_BASE - 0x1000 : + { + KEEP(*(.bootpg)) + } :text = 0xffff +#endif . = IMAGE_TEXT_BASE; .text : { *(.text*) @@ -67,18 +74,13 @@ SECTIONS __bss_end = .; #endif -/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */ -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC - .bootpg ADDR(.text) - 0x1000 : - { - KEEP(*(.bootpg)) - } :text = 0xffff -#else +/* For nor and nand is needed the SPL with section .resetvec */ +#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ #ifndef BOOT_PAGE_OFFSET #define BOOT_PAGE_OFFSET 0x1000 #endif - .bootpg ADDR(.text) + BOOT_PAGE_OFFSET : + .bootpg IMAGE_TEXT_BASE + BOOT_PAGE_OFFSET : { arch/powerpc/cpu/mpc85xx/start.o (.bootpg) } @@ -90,7 +92,7 @@ SECTIONS #else #error unknown NAND controller #endif - .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : { + .resetvec IMAGE_TEXT_BASE + RESET_VECTOR_OFFSET : { KEEP(*(.resetvec)) } = 0xffff #endif diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 9d0f0d58d80..e1bbee43bcb 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -23,6 +23,13 @@ PHDRS SECTIONS { /* Read-only sections, merged into text segment: */ +#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC + .bootpg CONFIG_SYS_TEXT_BASE - 0x1000 : + { + KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) + } :text = 0xffff + . = CONFIG_SYS_TEXT_BASE; +#endif .text : { *(.text*) @@ -77,13 +84,7 @@ SECTIONS __init_end = .; _end = .; -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC - .bootpg ADDR(.text) - 0x1000 : - { - KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) - } :text = 0xffff - . = _end; -#else +#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC .bootpg RESET_VECTOR_ADDRESS - 0xffc : { arch/powerpc/cpu/mpc85xx/start.o (.bootpg) -- cgit v1.3.1 From ec52b55b93dda92b50a24662ce7a5c9a01e4229b Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Fri, 8 Apr 2022 14:39:50 +0200 Subject: powerpc: dts: p2020: Add gpio-controller@fc00 node via pq3-gpio-0.dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Import pq3-gpio-0.dtsi device tree include file from upstream Linux kernel for P2020. This allows U-Boot to use P2020 device tree files from upstream Linux kernel which reference gpio-controller@fc00 device. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 1 + arch/powerpc/dts/pq3-gpio-0.dtsi | 41 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) create mode 100644 arch/powerpc/dts/pq3-gpio-0.dtsi (limited to 'arch') diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 6debae7720a..804db73c377 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -50,6 +50,7 @@ /include/ "pq3-i2c-0.dtsi" /include/ "pq3-i2c-1.dtsi" /include/ "pq3-duart-0.dtsi" +/include/ "pq3-gpio-0.dtsi" /include/ "pq3-etsec1-0.dtsi" /include/ "pq3-etsec1-1.dtsi" diff --git a/arch/powerpc/dts/pq3-gpio-0.dtsi b/arch/powerpc/dts/pq3-gpio-0.dtsi new file mode 100644 index 00000000000..a1b48546b02 --- /dev/null +++ b/arch/powerpc/dts/pq3-gpio-0.dtsi @@ -0,0 +1,41 @@ +/* + * PQ3 GPIO device tree stub [ controller @ offset 0xfc00 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +gpio-controller@fc00 { + #gpio-cells = <2>; + compatible = "fsl,pq3-gpio"; + reg = <0xfc00 0x100>; + interrupts = <47 0x2 0 0>; + gpio-controller; +}; -- cgit v1.3.1 From 1a0800ac40c0bd65fbd12b2e00ad2b2f2067530b Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Fri, 8 Apr 2022 14:39:51 +0200 Subject: powerpc: dts: p2020: Make PCIe nodes compatible for Linux kernel driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Linux P2020 PCIe kernel driver uses compatible string fsl,mpc8548-pcie and needs more DT properties. Copy P2020 PCIe nodes and definitions from upstream Linux kernel. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 65 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 62 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 804db73c377..6eb6fedd415 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -59,32 +59,91 @@ /* PCIe controller base address 0x8000 */ &pci2 { - compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie"; law_trgt_if = <0>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x0 0xff>; + clock-frequency = <33333333>; + interrupts = <24 2 0 0>; + + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <24 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0 + 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0 + 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0 + 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0 + >; + }; }; /* PCIe controller base address 0x9000 */ &pci1 { - compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie"; law_trgt_if = <1>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x0 0xff>; + clock-frequency = <33333333>; + interrupts = <25 2 0 0>; + + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <25 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 + 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 + 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 + 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 + >; + }; }; /* PCIe controller base address 0xa000 */ &pci0 { - compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie"; law_trgt_if = <2>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x0 0xff>; + clock-frequency = <33333333>; + interrupts = <26 2 0 0>; + + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <26 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 + 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 + 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 + 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 + >; + }; }; &lbc { -- cgit v1.3.1 From 0e33f68b239988a10ecef5fea691d9bfd05b2ad2 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Fri, 8 Apr 2022 14:39:52 +0200 Subject: powerpc: dts: p2020: Add ptp_clock@24e00 node via pq3-etsec1-timer-0.dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Import pq3-etsec1-timer-0.dtsi device tree include file from upstream Linux kernel for P2020. This allows U-Boot to use P2020 device tree files from upstream Linux kernel which reference ptp_clock@24e00 device. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 6 +++++ arch/powerpc/dts/pq3-etsec1-timer-0.dtsi | 39 ++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) create mode 100644 arch/powerpc/dts/pq3-etsec1-timer-0.dtsi (limited to 'arch') diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 6eb6fedd415..7709f3f9ade 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -53,6 +53,12 @@ /include/ "pq3-gpio-0.dtsi" /include/ "pq3-etsec1-0.dtsi" +/include/ "pq3-etsec1-timer-0.dtsi" + + ptp_clock@24e00 { + interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>; + }; + /include/ "pq3-etsec1-1.dtsi" /include/ "pq3-etsec1-2.dtsi" }; diff --git a/arch/powerpc/dts/pq3-etsec1-timer-0.dtsi b/arch/powerpc/dts/pq3-etsec1-timer-0.dtsi new file mode 100644 index 00000000000..efe2ca04bce --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-timer-0.dtsi @@ -0,0 +1,39 @@ +/* + * PQ3 eTSEC Timer (IEEE 1588) device tree stub [ @ offsets 0x24e00 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +ptp_clock@24e00 { + compatible = "fsl,etsec-ptp"; + reg = <0x24e00 0xb0>; + interrupts = <68 2 0 0 69 2 0 0>; +}; -- cgit v1.3.1 From d1721ea6d96c8d29b666278ca326fdc9a0b27023 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Fri, 8 Apr 2022 14:39:53 +0200 Subject: powerpc: dts: p2020: Add Linux compatible string and property for eSDHC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Linux kernel eSDHC driver for P2020 requires additional compatible string fsl,p2020-esdhc and interrupts property. Add them to p2020-post.dtsi file to make U-Boot board DTS files compatible for Linux kernel. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 7709f3f9ade..d1559739404 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -32,8 +32,9 @@ }; esdhc: sdhc@2e000 { - compatible = "fsl,esdhc"; + compatible = "fsl,p2020-esdhc", "fsl,esdhc"; reg = <0x2e000 0x1000>; + interrupts = <72 0x2 0 0>; /* Filled in by U-Boot */ clock-frequency = <0>; }; -- cgit v1.3.1 From 15d086ded9f2f7fcbf8e163d95f2740b00414eff Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Fri, 8 Apr 2022 14:39:54 +0200 Subject: powerpc: dts: p2020: Do not automatically disable spi@7000 node in p2020-post.dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Device tree include file p2020-post.dtsi should be included after the board device tree file and overrides settings of the board. So it should not disable some node as board cannot enable it via normal way (it has to enable it after inclusion of p2020-post.dtsi file). Fix it by removal of explicit disable in p2020-post.dtsi file and then remove explicit post-post enable in all P2020 board device tree files. Currently no P2020 board has spi@7000 node disabled. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 1 - arch/powerpc/dts/p2020rdb-pc.dts | 1 - arch/powerpc/dts/p2020rdb-pc_36b.dts | 1 - 3 files changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index d1559739404..248b504b8fc 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -45,7 +45,6 @@ #size-cells = <0>; reg = <0x7000 0x1000>; fsl,espi-num-chipselects = <4>; - status = "disabled"; }; /include/ "pq3-i2c-0.dtsi" diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts index 67fa340d09d..84d32360baa 100644 --- a/arch/powerpc/dts/p2020rdb-pc.dts +++ b/arch/powerpc/dts/p2020rdb-pc.dts @@ -49,7 +49,6 @@ /include/ "p2020-post.dtsi" &espi0 { - status = "okay"; flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts index 6f251960031..c847417df99 100644 --- a/arch/powerpc/dts/p2020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts @@ -49,7 +49,6 @@ /include/ "p2020-post.dtsi" &espi0 { - status = "okay"; flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; -- cgit v1.3.1 From 7b074129ad5701500d33d22a8492e1577b1209ac Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Fri, 8 Apr 2022 14:39:55 +0200 Subject: powerpc: dts: p2020: Add missing interrupts property to spi@7000 node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit interrupts property for spi@7000 node is needed for compatibility with Linux kernel. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 248b504b8fc..2135710ccc3 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -44,6 +44,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x7000 0x1000>; + interrupts = < 0x3b 0x02 0x00 0x00 >; fsl,espi-num-chipselects = <4>; }; -- cgit v1.3.1 From 787d2c024bb43bb99cda20c38629a3aa6b3ac376 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Fri, 8 Apr 2022 14:39:56 +0200 Subject: powerpc: dts: p2020: Make usb@22000 node compatible for Linux kernel driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Linux P2020 USB kernel driver uses compatible string fsl-usb2-dr-v1.6 and needs more DT properties. Copy P2020 usb@22000 properties from upstream Linux kernel. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 2135710ccc3..0a296cffe56 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -14,8 +14,11 @@ bus-frequency = <0x0>; usb@22000 { - compatible = "fsl-usb2-dr"; + compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; reg = <0x22000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <28 0x2 0 0>; phy_type = "ulpi"; }; -- cgit v1.3.1 From fd3dc72945474ca3665cd76c96350f7c0e7d95cf Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Fri, 8 Apr 2022 14:39:57 +0200 Subject: powerpc: dts: p2020: Define L2 cache node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Copy definition of L2 cache node from upstream Linux kernel P2020 dts files. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 8 ++++++++ arch/powerpc/dts/p2020.dtsi | 2 ++ 2 files changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 0a296cffe56..1c3f78798ef 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -56,6 +56,14 @@ /include/ "pq3-duart-0.dtsi" /include/ "pq3-gpio-0.dtsi" + L2: l2-cache-controller@20000 { + compatible = "fsl,p2020-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; /* 32 bytes */ + cache-size = <0x80000>; /* L2,512K */ + interrupts = <16 2 0 0>; + }; + /include/ "pq3-etsec1-0.dtsi" /include/ "pq3-etsec1-timer-0.dtsi" diff --git a/arch/powerpc/dts/p2020.dtsi b/arch/powerpc/dts/p2020.dtsi index 7c4c2061d4c..7fdcb85c809 100644 --- a/arch/powerpc/dts/p2020.dtsi +++ b/arch/powerpc/dts/p2020.dtsi @@ -22,10 +22,12 @@ cpu0: PowerPC,P2020@0 { device_type = "cpu"; reg = <0>; + next-level-cache = <&L2>; }; cpu1: PowerPC,P2020@1 { device_type = "cpu"; reg = <1>; + next-level-cache = <&L2>; }; }; }; -- cgit v1.3.1 From e8c9148bc90e83b809cc8ecd8db73304b4755eae Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Fri, 8 Apr 2022 14:39:58 +0200 Subject: powerpc: dts: p2020: Set dfsrr property for i2c nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Linux kernel dts files pq3-i2c-*.dtsi also sets this dfsrr property for i2c nodes. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/pq3-i2c-0.dtsi | 1 + arch/powerpc/dts/pq3-i2c-1.dtsi | 1 + 2 files changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/dts/pq3-i2c-0.dtsi b/arch/powerpc/dts/pq3-i2c-0.dtsi index 86a91e63365..0ed519c2e53 100644 --- a/arch/powerpc/dts/pq3-i2c-0.dtsi +++ b/arch/powerpc/dts/pq3-i2c-0.dtsi @@ -12,4 +12,5 @@ i2c@3000 { u-boot,dm-pre-reloc; reg = <0x3000 0x100>; interrupts = <43 2 0 0>; + dfsrr; }; diff --git a/arch/powerpc/dts/pq3-i2c-1.dtsi b/arch/powerpc/dts/pq3-i2c-1.dtsi index 5d79b1fb4c3..78b0fcf81dc 100644 --- a/arch/powerpc/dts/pq3-i2c-1.dtsi +++ b/arch/powerpc/dts/pq3-i2c-1.dtsi @@ -12,4 +12,5 @@ i2c@3100 { u-boot,dm-pre-reloc; reg = <0x3100 0x100>; interrupts = <43 2 0 0>; + dfsrr; }; -- cgit v1.3.1 From 95f8dfe8fb94d8de8abe8f5f7088c7c5ec234dd0 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Thu, 14 Apr 2022 22:52:03 +0200 Subject: pci: fsl: Change compatible string for mpc8548 to "fsl, mpc8548-pcie" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream Linux kernel uses for mpc8548-based PCIe controllers compatible string "fsl,mpc8548-pcie". So change U-Boot fsl PCIe driver and all DTS files to use "fsl,mpc8548-pcie" instead of "fsl,pcie-mpc8548" to be compatible with Linux kernel. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/mpc8548-post.dtsi | 2 +- drivers/pci/pcie_fsl.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/dts/mpc8548-post.dtsi b/arch/powerpc/dts/mpc8548-post.dtsi index 2206f2da9fe..97c3ce6e74d 100644 --- a/arch/powerpc/dts/mpc8548-post.dtsi +++ b/arch/powerpc/dts/mpc8548-post.dtsi @@ -27,7 +27,7 @@ }; &pcie { - compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq"; + compatible = "fsl,mpc8548-pcie", "fsl,pcie-fsl-qoriq"; law_trgt_if = <2>; #address-cells = <3>; #size-cells = <2>; diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index f5ba34970f1..59c38f90577 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -646,7 +646,7 @@ static struct fsl_pcie_data t2080_data = { }; static const struct udevice_id fsl_pcie_ids[] = { - { .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data }, + { .compatible = "fsl,mpc8548-pcie", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data }, -- cgit v1.3.1