From e2bc87d41ce866b30721d5b8ee395efefecd9bef Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Sat, 13 May 2017 20:11:30 -0400
Subject: sandbox: Fix comparison of unsigned enum expression warning

In os_dirent_get_typename() we are checking that type falls within the
known values of the enum os_dirent_t.  With clang-3.8 testing this value
as being >= 0 results in a warning as it will always be true.  This
assumes of course that we are only given valid data.  Given that we want
to sanity check the input, we change this to check that it falls within
the range of the first to the last entry in the given enum.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 arch/sandbox/cpu/os.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'arch')

diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 35ea00ce3ca..7243bfc1b1f 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -395,7 +395,7 @@ const char *os_dirent_typename[OS_FILET_COUNT] = {
 
 const char *os_dirent_get_typename(enum os_dirent_t type)
 {
-	if (type >= 0 && type < OS_FILET_COUNT)
+	if (type >= OS_FILET_REG && type < OS_FILET_COUNT)
 		return os_dirent_typename[type];
 
 	return os_dirent_typename[OS_FILET_UNKNOWN];
-- 
cgit v1.3.1


From 1c2d2727d17a5a81caa3c611603a9e1c92ee86e1 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Wed, 31 May 2017 17:57:11 -0600
Subject: arm: arm720t: Support CONFIG_SKIP_LOWLEVEL_INIT_ONLY

This option allows skipping the call to lowlevel() while still performing
CP15 init. Support this on ARM720T so it can be used with Tegra.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/arm/cpu/arm720t/start.S | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'arch')

diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index 0bb3441fb8f..365d8f08cb0 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -38,7 +38,8 @@ reset:
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+		!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
 	bl	cpu_init_crit
 #endif
 
@@ -62,7 +63,8 @@ c_runtime_cpu_setup:
  *************************************************************************
  */
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+		!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
 cpu_init_crit:
 
 	mov	ip, lr
-- 
cgit v1.3.1


From 579dfca2ef2fdff93ae78a942fef49f3d1da3f8c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Wed, 31 May 2017 17:57:12 -0600
Subject: arm: Rename HCTR to HTCR

This appears to be a typo. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/arm/lib/cache-cp15.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'arch')

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index e9bbcf51220..0f7020a3151 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -147,7 +147,7 @@ static inline void mmu_setup(void)
 #endif
 
 	if (is_hyp()) {
-		/* Set HCTR to enable LPAE */
+		/* Set HTCR to enable LPAE */
 		asm volatile("mcr p15, 4, %0, c2, c0, 2"
 			: : "r" (reg) : "memory");
 		/* Set HTTBR0 */
-- 
cgit v1.3.1


From 10d602ac8b6f576d545e35a951e1a714de0158a3 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Wed, 31 May 2017 17:57:13 -0600
Subject: arm: Don't try to support CONFIG_ARMV7_LPAE on ARMv4T

At present if CONFIG_ARMV7_LPAE is defined then mmu_setup() will use
instructions which are invalid on ARMv4T. This happens on Tegra since it
has an ARMv4T boot CPU. Add a check for the architecture version to allow
the code to be built. It will not actually be executed by the boot CPU,
but needs to compile.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/arm/lib/cache-cp15.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'arch')

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 0f7020a3151..f2935736014 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -129,7 +129,7 @@ static inline void mmu_setup(void)
 		dram_bank_mmu_setup(i);
 	}
 
-#ifdef CONFIG_ARMV7_LPAE
+#if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4
 	/* Set up 4 PTE entries pointing to our 4 1GB page tables */
 	for (i = 0; i < 4; i++) {
 		u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
-- 
cgit v1.3.1


From 50a4886b3b8579a5d3dad337906de9b5a3fef6d1 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Wed, 31 May 2017 17:57:14 -0600
Subject: arm: Disable LPAE if not enabled

If CONFIG_ARMV7_LPAE is not defined we should make sure that the feature
is disabled. This can happen if U-Boot is chain-loaded from another boot
loader which does enable LPAE.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/arm/lib/cache-cp15.c | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'arch')

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index f2935736014..cf852c061b4 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -172,6 +172,15 @@ static inline void mmu_setup(void)
 			: : "r" (MEMORY_ATTRIBUTES) : "memory");
 	}
 #elif defined(CONFIG_CPU_V7)
+	if (is_hyp()) {
+		/* Set HTCR to disable LPAE */
+		asm volatile("mcr p15, 4, %0, c2, c0, 2"
+			: : "r" (0) : "memory");
+	} else {
+		/* Set TTBCR to disable LPAE */
+		asm volatile("mcr p15, 0, %0, c2, c0, 2"
+			: : "r" (0) : "memory");
+	}
 	/* Set TTBR0 */
 	reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
-- 
cgit v1.3.1


From 46864cc8e82ade3523f4c474b7451bb960e4ad70 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Wed, 31 May 2017 17:57:16 -0600
Subject: tegra: Init clocks even when SPL did not run

At present early clock init happens in SPL. If SPL did not run (because
for example U-Boot is chain-loaded from another boot loader) then the
clocks are not set as U-Boot expects.

Add a function to detect this and call the early clock init in U-Boot
proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/arm/include/asm/arch-tegra/clock.h |  3 +++
 arch/arm/mach-tegra/board2.c            |  3 +++
 arch/arm/mach-tegra/clock.c             |  5 +++++
 arch/arm/mach-tegra/tegra124/clock.c    | 18 ++++++++++++++++++
 4 files changed, 29 insertions(+)

(limited to 'arch')

diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index 388afcb7231..f62b2a43788 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -288,6 +288,9 @@ void clock_init(void);
 /* Initialize the PLLs */
 void clock_early_init(void);
 
+/* @return true if hardware indicates that clock_early_init() was called */
+bool clock_early_init_done(void);
+
 /* Returns a pointer to the clock source register for a peripheral */
 u32 *get_periph_source_reg(enum periph_id periph_id);
 
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 84f1ee5035f..1e627ba6037 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -191,6 +191,9 @@ void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
 
 int board_early_init_f(void)
 {
+	if (!clock_early_init_done())
+		clock_early_init();
+
 #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
 #define USBCMD_FS2 (1 << 15)
 	{
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 3bb72331a42..76436d8d911 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -825,3 +825,8 @@ int clock_external_output(int clk_id)
 
 	return 0;
 }
+
+__weak bool clock_early_init_done(void)
+{
+	return true;
+}
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c
index 5e4406102f1..5ae718b3426 100644
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -891,6 +891,24 @@ void clock_early_init(void)
 	udelay(2);
 }
 
+/*
+ * clock_early_init_done - Check if clock_early_init() has been called
+ *
+ * Check a register that we set up to see if clock_early_init() has already
+ * been called.
+ *
+ * @return true if clock_early_init() was called, false if not
+ */
+bool clock_early_init_done(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 val;
+
+	val = readl(&clkrst->crc_sclk_brst_pol);
+
+	return val == 0x20002222;
+}
+
 void arch_timer_init(void)
 {
 	struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
-- 
cgit v1.3.1


From c415dda8df1134ba60ff031110649ca4e2735174 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Wed, 31 May 2017 17:57:17 -0600
Subject: tegra: dts: Add cros-ec SPI settings

At present the interrupt does not work and the SPI bus runs much less
quickly than it should. Add settings to fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/arm/dts/tegra124-nyan-big-u-boot.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'arch')

diff --git a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
index fff1d781694..65c3851affa 100644
--- a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
+++ b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
@@ -12,4 +12,13 @@
 			u-boot,dm-pre-reloc;
 		};
 	};
+
+	spi@7000d400 {
+		spi-deactivate-delay = <200>;
+		spi-max-frequency = <3000000>;
+
+		cros_ec: cros-ec@0 {
+			ec-interrupt = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
+		};
+	};
 };
-- 
cgit v1.3.1


From 1c6c7b6bd8961373a506cf7908e9fe61f6042341 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Wed, 31 May 2017 17:57:22 -0600
Subject: tegra: clock: Avoid a divide-by-zero error

The clock fix-up for tegra is still present in the code. It causes a
divide-by-zero bug after relocation when chain-loading U-Boot from
coreboot. Fix this by adding a check.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 7468676 (ARM: tegra: fix clock_get_periph_rate() for UART clocks)
---
 arch/arm/mach-tegra/clock.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'arch')

diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 76436d8d911..bac42119cdc 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -339,8 +339,11 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id,
 		 * return value doesn't help. In summary this clock driver is
 		 * quite broken but I'm afraid I have no idea how to fix it
 		 * without completely replacing it.
+		 *
+		 * Be careful to avoid a divide by zero error.
 		 */
-		div -= 2;
+		if (div >= 1)
+			div -= 2;
 		break;
 #endif
 	default:
-- 
cgit v1.3.1


From 3238474b8f60b17e8a2ccd3e19dee9d836e7a277 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Wed, 31 May 2017 17:57:26 -0600
Subject: rockchip: Fix regualtor typo in veyron

This typo doesn't actually cause any problems, but is wrong. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/arm/dts/rk3288-veyron-jerry.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'arch')

diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts
index 8aab607cc52..2e6272b81b0 100644
--- a/arch/arm/dts/rk3288-veyron-jerry.dts
+++ b/arch/arm/dts/rk3288-veyron-jerry.dts
@@ -21,7 +21,7 @@
                 stdout-path = &uart2;
         };
 
-	panel_regulator: panel-regualtor {
+	panel_regulator: panel-regulator {
 		compatible = "regulator-fixed";
 		enable-active-high;
 		gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
-- 
cgit v1.3.1


From 6f06ef57bb9031e322752343f7cf8f2408904452 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Wed, 31 May 2017 17:57:27 -0600
Subject: rockchip: rk3288: Add error debugging to veyron_init()

Add a debug() statement so we can see when something goes wrong with the
regulator.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/arm/mach-rockchip/rk3288-board.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'arch')

diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c
index 9894a25e080..18fd0dcd207 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -86,8 +86,10 @@ static int veyron_init(void)
 	int ret;
 
 	ret = regulator_get_by_platname("vdd_arm", &dev);
-	if (ret)
+	if (ret) {
+		debug("Cannot set regulator name\n");
 		return ret;
+	}
 
 	/* Slowly raise to max CPU voltage to prevent overshoot */
 	ret = regulator_set_value(dev, 1200000);
-- 
cgit v1.3.1


From b223c1aeade5b29c13347354edd1ce4e66f60b7f Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Wed, 31 May 2017 17:57:31 -0600
Subject: rockchip: rk3288: Convert clock driver to use shifted masks

Shifted masks are the standard approach with rockchip since it allows
use of the mask without shifting it each time. Update the definitions and
the driver to match.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/arm/include/asm/arch-rockchip/cru_rk3288.h |  74 ++++++++-------
 drivers/clk/rockchip/clk_rk3288.c               | 121 ++++++++++--------------
 2 files changed, 90 insertions(+), 105 deletions(-)

(limited to 'arch')

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
index d575f4a1639..cb0a935edce 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -64,135 +64,137 @@ check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
 /* CRU_CLKSEL11_CON */
 enum {
 	HSICPHY_DIV_SHIFT	= 8,
-	HSICPHY_DIV_MASK	= 0x3f,
+	HSICPHY_DIV_MASK	= 0x3f << HSICPHY_DIV_SHIFT,
 
 	MMC0_PLL_SHIFT		= 6,
-	MMC0_PLL_MASK		= 3,
+	MMC0_PLL_MASK		= 3 << MMC0_PLL_SHIFT,
 	MMC0_PLL_SELECT_CODEC	= 0,
 	MMC0_PLL_SELECT_GENERAL,
 	MMC0_PLL_SELECT_24MHZ,
 
 	MMC0_DIV_SHIFT		= 0,
-	MMC0_DIV_MASK		= 0x3f,
+	MMC0_DIV_MASK		= 0x3f << MMC0_DIV_SHIFT,
 };
 
 /* CRU_CLKSEL12_CON */
 enum {
 	EMMC_PLL_SHIFT		= 0xe,
-	EMMC_PLL_MASK		= 3,
+	EMMC_PLL_MASK		= 3 << EMMC_PLL_SHIFT,
 	EMMC_PLL_SELECT_CODEC	= 0,
 	EMMC_PLL_SELECT_GENERAL,
 	EMMC_PLL_SELECT_24MHZ,
 
 	EMMC_DIV_SHIFT		= 8,
-	EMMC_DIV_MASK		= 0x3f,
+	EMMC_DIV_MASK		= 0x3f < EMMC_DIV_SHIFT,
 
 	SDIO0_PLL_SHIFT		= 6,
-	SDIO0_PLL_MASK		= 3,
+	SDIO0_PLL_MASK		= 3 << SDIO0_PLL_SHIFT,
 	SDIO0_PLL_SELECT_CODEC	= 0,
 	SDIO0_PLL_SELECT_GENERAL,
 	SDIO0_PLL_SELECT_24MHZ,
 
 	SDIO0_DIV_SHIFT		= 0,
-	SDIO0_DIV_MASK		= 0x3f,
+	SDIO0_DIV_MASK		= 0x3f << SDIO0_DIV_SHIFT,
 };
 
 /* CRU_CLKSEL21_CON */
 enum {
-	MAC_DIV_CON_SHIFT = 0xf,
-	MAC_DIV_CON_MASK = 0x1f,
+	MAC_DIV_CON_SHIFT	= 0xf,
+	MAC_DIV_CON_MASK	= 0x1f << MAC_DIV_CON_SHIFT,
 
-	RMII_EXTCLK_SHIFT = 4,
-	RMII_EXTCLK_MASK = 1,
+	RMII_EXTCLK_SHIFT	= 4,
+	RMII_EXTCLK_MASK	= 1 << RMII_EXTCLK_SHIFT,
 	RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
 	RMII_EXTCLK_SELECT_EXT_CLK = 1,
 
-	EMAC_PLL_SHIFT = 0,
-	EMAC_PLL_MASK = 0x3,
-	EMAC_PLL_SELECT_NEW = 0x0,
-	EMAC_PLL_SELECT_CODEC = 0x1,
-	EMAC_PLL_SELECT_GENERAL = 0x2,
+	EMAC_PLL_SHIFT		= 0,
+	EMAC_PLL_MASK		= 0x3 << EMAC_PLL_SHIFT,
+	EMAC_PLL_SELECT_NEW	= 0x0,
+	EMAC_PLL_SELECT_CODEC	= 0x1,
+	EMAC_PLL_SELECT_GENERAL	= 0x2,
 };
 
 /* CRU_CLKSEL25_CON */
 enum {
 	SPI1_PLL_SHIFT		= 0xf,
-	SPI1_PLL_MASK		= 1,
+	SPI1_PLL_MASK		= 1 << SPI1_PLL_SHIFT,
 	SPI1_PLL_SELECT_CODEC	= 0,
 	SPI1_PLL_SELECT_GENERAL,
 
 	SPI1_DIV_SHIFT		= 8,
-	SPI1_DIV_MASK		= 0x7f,
+	SPI1_DIV_MASK		= 0x7f << SPI1_DIV_SHIFT,
 
 	SPI0_PLL_SHIFT		= 7,
-	SPI0_PLL_MASK		= 1,
+	SPI0_PLL_MASK		= 1 << SPI0_PLL_SHIFT,
 	SPI0_PLL_SELECT_CODEC	= 0,
 	SPI0_PLL_SELECT_GENERAL,
 
 	SPI0_DIV_SHIFT		= 0,
-	SPI0_DIV_MASK		= 0x7f,
+	SPI0_DIV_MASK		= 0x7f << SPI0_DIV_SHIFT,
 };
 
 /* CRU_CLKSEL37_CON */
 enum {
 	PCLK_CORE_DBG_DIV_SHIFT	= 9,
-	PCLK_CORE_DBG_DIV_MASK	= 0x1f,
+	PCLK_CORE_DBG_DIV_MASK	= 0x1f << PCLK_CORE_DBG_DIV_SHIFT,
 
 	ATCLK_CORE_DIV_CON_SHIFT = 4,
-	ATCLK_CORE_DIV_CON_MASK	= 0x1f,
+	ATCLK_CORE_DIV_CON_MASK	= 0x1f << ATCLK_CORE_DIV_CON_SHIFT,
 
 	CLK_L2RAM_DIV_SHIFT	= 0,
-	CLK_L2RAM_DIV_MASK	= 7,
+	CLK_L2RAM_DIV_MASK	= 7 << CLK_L2RAM_DIV_SHIFT,
 };
 
 /* CRU_CLKSEL39_CON */
 enum {
 	ACLK_HEVC_PLL_SHIFT	= 0xe,
-	ACLK_HEVC_PLL_MASK	= 3,
+	ACLK_HEVC_PLL_MASK	= 3 << ACLK_HEVC_PLL_SHIFT,
 	ACLK_HEVC_PLL_SELECT_CODEC = 0,
 	ACLK_HEVC_PLL_SELECT_GENERAL,
 	ACLK_HEVC_PLL_SELECT_NEW,
 
 	ACLK_HEVC_DIV_SHIFT	= 8,
-	ACLK_HEVC_DIV_MASK	= 0x1f,
+	ACLK_HEVC_DIV_MASK	= 0x1f << ACLK_HEVC_DIV_SHIFT,
 
 	SPI2_PLL_SHIFT		= 7,
-	SPI2_PLL_MASK		= 1,
+	SPI2_PLL_MASK		= 1 << SPI2_PLL_SHIFT,
 	SPI2_PLL_SELECT_CODEC	= 0,
 	SPI2_PLL_SELECT_GENERAL,
 
 	SPI2_DIV_SHIFT		= 0,
-	SPI2_DIV_MASK		= 0x7f,
+	SPI2_DIV_MASK		= 0x7f << SPI2_DIV_SHIFT,
 };
 
 /* CRU_MODE_CON */
 enum {
+	CRU_MODE_MASK		= 3,
+
 	NPLL_MODE_SHIFT		= 0xe,
-	NPLL_MODE_MASK		= 3,
+	NPLL_MODE_MASK		= CRU_MODE_MASK << NPLL_MODE_SHIFT,
 	NPLL_MODE_SLOW		= 0,
 	NPLL_MODE_NORMAL,
 	NPLL_MODE_DEEP,
 
 	GPLL_MODE_SHIFT		= 0xc,
-	GPLL_MODE_MASK		= 3,
+	GPLL_MODE_MASK		= CRU_MODE_MASK << GPLL_MODE_SHIFT,
 	GPLL_MODE_SLOW		= 0,
 	GPLL_MODE_NORMAL,
 	GPLL_MODE_DEEP,
 
 	CPLL_MODE_SHIFT		= 8,
-	CPLL_MODE_MASK		= 3,
+	CPLL_MODE_MASK		= CRU_MODE_MASK << CPLL_MODE_SHIFT,
 	CPLL_MODE_SLOW		= 0,
 	CPLL_MODE_NORMAL,
 	CPLL_MODE_DEEP,
 
 	DPLL_MODE_SHIFT		= 4,
-	DPLL_MODE_MASK		= 3,
+	DPLL_MODE_MASK		= CRU_MODE_MASK << DPLL_MODE_SHIFT,
 	DPLL_MODE_SLOW		= 0,
 	DPLL_MODE_NORMAL,
 	DPLL_MODE_DEEP,
 
 	APLL_MODE_SHIFT		= 0,
-	APLL_MODE_MASK		= 3,
+	APLL_MODE_MASK		= CRU_MODE_MASK << APLL_MODE_SHIFT,
 	APLL_MODE_SLOW		= 0,
 	APLL_MODE_NORMAL,
 	APLL_MODE_DEEP,
@@ -201,21 +203,21 @@ enum {
 /* CRU_APLL_CON0 */
 enum {
 	CLKR_SHIFT		= 8,
-	CLKR_MASK		= 0x3f,
+	CLKR_MASK		= 0x3f << CLKR_SHIFT,
 
 	CLKOD_SHIFT		= 0,
-	CLKOD_MASK		= 0xf,
+	CLKOD_MASK		= 0xf << CLKOD_SHIFT,
 };
 
 /* CRU_APLL_CON1 */
 enum {
 	LOCK_SHIFT		= 0x1f,
-	LOCK_MASK		= 1,
+	LOCK_MASK		= 1 << LOCK_SHIFT,
 	LOCK_UNLOCK		= 0,
 	LOCK_LOCK,
 
 	CLKF_SHIFT		= 0,
-	CLKF_MASK		= 0x1fff,
+	CLKF_MASK		= 0x1fff << CLKF_SHIFT,
 };
 
 #endif
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index 14851ca5aa2..f6ef7ecd7a1 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -59,14 +59,14 @@ enum {
 	PLL_RESET_SHIFT		= 5,
 
 	/* CLKSEL0 */
-	CORE_SEL_PLL_MASK	= 1,
 	CORE_SEL_PLL_SHIFT	= 15,
-	A17_DIV_MASK		= 0x1f,
+	CORE_SEL_PLL_MASK	= 1 << CORE_SEL_PLL_SHIFT,
 	A17_DIV_SHIFT		= 8,
-	MP_DIV_MASK		= 0xf,
+	A17_DIV_MASK		= 0x1f << A17_DIV_SHIFT,
 	MP_DIV_SHIFT		= 4,
-	M0_DIV_MASK		= 0xf,
+	MP_DIV_MASK		= 0xf << MP_DIV_SHIFT,
 	M0_DIV_SHIFT		= 0,
+	M0_DIV_MASK		= 0xf << M0_DIV_SHIFT,
 
 	/* CLKSEL1: pd bus clk pll sel: codec or general */
 	PD_BUS_SEL_PLL_MASK	= 15,
@@ -75,41 +75,41 @@ enum {
 
 	/* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
 	PD_BUS_PCLK_DIV_SHIFT	= 12,
-	PD_BUS_PCLK_DIV_MASK	= 7,
+	PD_BUS_PCLK_DIV_MASK	= 7 << PD_BUS_PCLK_DIV_SHIFT,
 
 	/* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
 	PD_BUS_HCLK_DIV_SHIFT	= 8,
-	PD_BUS_HCLK_DIV_MASK	= 3,
+	PD_BUS_HCLK_DIV_MASK	= 3 << PD_BUS_HCLK_DIV_SHIFT,
 
 	/* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
 	PD_BUS_ACLK_DIV0_SHIFT	= 3,
-	PD_BUS_ACLK_DIV0_MASK	= 0x1f,
+	PD_BUS_ACLK_DIV0_MASK	= 0x1f << PD_BUS_ACLK_DIV0_SHIFT,
 	PD_BUS_ACLK_DIV1_SHIFT	= 0,
-	PD_BUS_ACLK_DIV1_MASK	= 0x7,
+	PD_BUS_ACLK_DIV1_MASK	= 0x7 << PD_BUS_ACLK_DIV1_SHIFT,
 
 	/*
 	 * CLKSEL10
 	 * peripheral bus pclk div:
 	 * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
 	 */
-	PERI_SEL_PLL_MASK	 = 1,
 	PERI_SEL_PLL_SHIFT	 = 15,
+	PERI_SEL_PLL_MASK	 = 1 << PERI_SEL_PLL_SHIFT,
 	PERI_SEL_CPLL		= 0,
 	PERI_SEL_GPLL,
 
 	PERI_PCLK_DIV_SHIFT	= 12,
-	PERI_PCLK_DIV_MASK	= 3,
+	PERI_PCLK_DIV_MASK	= 3 << PERI_PCLK_DIV_SHIFT,
 
 	/* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
 	PERI_HCLK_DIV_SHIFT	= 8,
-	PERI_HCLK_DIV_MASK	= 3,
+	PERI_HCLK_DIV_MASK	= 3 << PERI_HCLK_DIV_SHIFT,
 
 	/*
 	 * peripheral bus aclk div:
 	 *    aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
 	 */
 	PERI_ACLK_DIV_SHIFT	= 0,
-	PERI_ACLK_DIV_MASK	= 0x1f,
+	PERI_ACLK_DIV_MASK	= 0x1f << PERI_ACLK_DIV_SHIFT,
 
 	SOCSTS_DPLL_LOCK	= 1 << 5,
 	SOCSTS_APLL_LOCK	= 1 << 6,
@@ -154,8 +154,7 @@ static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
 	/* enter reset */
 	rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
 
-	rk_clrsetreg(&pll->con0,
-		     CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
+	rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK,
 		     ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
 	rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
 	rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
@@ -198,7 +197,7 @@ static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
 	}
 
 	/* pll enter slow-mode */
-	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
+	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
 		     DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
 
 	rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
@@ -208,7 +207,7 @@ static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
 		udelay(1);
 
 	/* PLL enter normal-mode */
-	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
+	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
 		     DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
 
 	return 0;
@@ -296,7 +295,7 @@ static int rockchip_mac_set_clk(struct rk3288_cru *cru,
 {
 	/* Assuming mac_clk is fed by an external clock */
 	rk_clrsetreg(&cru->cru_clksel_con[21],
-		     RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT,
+		     RMII_EXTCLK_MASK,
 		     RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
 
 	 return 0;
@@ -313,7 +312,7 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
 	if (ret)
 		return ret;
 
-	rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
+	rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
 		     NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
 	rkclk_set_pll(cru, CLK_NEW, &npll_config);
 
@@ -324,7 +323,7 @@ static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
 		udelay(1);
 	}
 
-	rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
+	rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
 		     NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
 
 	/* vop dclk source clk: npll,dclk_div: 1 */
@@ -352,8 +351,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
 
 	/* pll enter slow-mode */
 	rk_clrsetreg(&cru->cru_mode_con,
-		     GPLL_MODE_MASK << GPLL_MODE_SHIFT |
-		     CPLL_MODE_MASK << CPLL_MODE_SHIFT,
+		     GPLL_MODE_MASK | CPLL_MODE_MASK,
 		     GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
 		     CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
 
@@ -382,10 +380,8 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
 		PD_BUS_ACLK_HZ && pclk_div < 0x7);
 
 	rk_clrsetreg(&cru->cru_clksel_con[1],
-		     PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT |
-		     PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT |
-		     PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT |
-		     PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT,
+		     PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK |
+		     PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK,
 		     pclk_div << PD_BUS_PCLK_DIV_SHIFT |
 		     hclk_div << PD_BUS_HCLK_DIV_SHIFT |
 		     aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
@@ -407,9 +403,8 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
 		PERI_ACLK_HZ && (pclk_div < 0x4));
 
 	rk_clrsetreg(&cru->cru_clksel_con[10],
-		     PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
-		     PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
-		     PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
+		     PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK |
+		     PERI_ACLK_DIV_MASK,
 		     PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
 		     pclk_div << PERI_PCLK_DIV_SHIFT |
 		     hclk_div << PERI_HCLK_DIV_SHIFT |
@@ -417,8 +412,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
 
 	/* PLL enter normal-mode */
 	rk_clrsetreg(&cru->cru_mode_con,
-		     GPLL_MODE_MASK << GPLL_MODE_SHIFT |
-		     CPLL_MODE_MASK << CPLL_MODE_SHIFT,
+		     GPLL_MODE_MASK | CPLL_MODE_MASK,
 		     GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
 		     CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
 }
@@ -427,8 +421,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
 {
 	/* pll enter slow-mode */
-	rk_clrsetreg(&cru->cru_mode_con,
-		     APLL_MODE_MASK << APLL_MODE_SHIFT,
+	rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
 		     APLL_MODE_SLOW << APLL_MODE_SHIFT);
 
 	rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
@@ -444,10 +437,8 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
 	 * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
 	 */
 	rk_clrsetreg(&cru->cru_clksel_con[0],
-		     CORE_SEL_PLL_MASK << CORE_SEL_PLL_SHIFT |
-		     A17_DIV_MASK << A17_DIV_SHIFT |
-		     MP_DIV_MASK << MP_DIV_SHIFT |
-		     M0_DIV_MASK << M0_DIV_SHIFT,
+		     CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK |
+		     M0_DIV_MASK,
 		     0 << A17_DIV_SHIFT |
 		     3 << MP_DIV_SHIFT |
 		     1 << M0_DIV_SHIFT);
@@ -457,16 +448,14 @@ void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
 	 * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
 	 */
 	rk_clrsetreg(&cru->cru_clksel_con[37],
-		     CLK_L2RAM_DIV_MASK << CLK_L2RAM_DIV_SHIFT |
-		     ATCLK_CORE_DIV_CON_MASK << ATCLK_CORE_DIV_CON_SHIFT |
-		     PCLK_CORE_DBG_DIV_MASK >> PCLK_CORE_DBG_DIV_SHIFT,
+		     CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK |
+		     PCLK_CORE_DBG_DIV_MASK,
 		     1 << CLK_L2RAM_DIV_SHIFT |
 		     3 << ATCLK_CORE_DIV_CON_SHIFT |
 		     3 << PCLK_CORE_DBG_DIV_SHIFT);
 
 	/* PLL enter normal-mode */
-	rk_clrsetreg(&cru->cru_mode_con,
-		     APLL_MODE_MASK << APLL_MODE_SHIFT,
+	rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
 		     APLL_MODE_NORMAL << APLL_MODE_SHIFT);
 }
 
@@ -486,16 +475,16 @@ static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
 
 	con = readl(&cru->cru_mode_con);
 	shift = clk_shift[clk_id];
-	switch ((con >> shift) & APLL_MODE_MASK) {
+	switch ((con >> shift) & CRU_MODE_MASK) {
 	case APLL_MODE_SLOW:
 		return OSC_HZ;
 	case APLL_MODE_NORMAL:
 		/* normal mode */
 		con = readl(&pll->con0);
-		no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
-		nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
+		no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1;
+		nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1;
 		con = readl(&pll->con1);
-		nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
+		nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1;
 
 		return (24 * nf / (nr * no)) * 1000000;
 	case APLL_MODE_DEEP:
@@ -515,20 +504,20 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 	case HCLK_EMMC:
 	case SCLK_EMMC:
 		con = readl(&cru->cru_clksel_con[12]);
-		mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
-		div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
+		mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
+		div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
 		break;
 	case HCLK_SDMMC:
 	case SCLK_SDMMC:
 		con = readl(&cru->cru_clksel_con[11]);
-		mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
-		div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
+		mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
+		div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
 		break;
 	case HCLK_SDIO0:
 	case SCLK_SDIO0:
 		con = readl(&cru->cru_clksel_con[12]);
-		mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
-		div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
+		mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT;
+		div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT;
 		break;
 	default:
 		return -EINVAL;
@@ -561,24 +550,21 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 	case HCLK_EMMC:
 	case SCLK_EMMC:
 		rk_clrsetreg(&cru->cru_clksel_con[12],
-			     EMMC_PLL_MASK << EMMC_PLL_SHIFT |
-			     EMMC_DIV_MASK << EMMC_DIV_SHIFT,
+			     EMMC_PLL_MASK | EMMC_DIV_MASK,
 			     mux << EMMC_PLL_SHIFT |
 			     (src_clk_div - 1) << EMMC_DIV_SHIFT);
 		break;
 	case HCLK_SDMMC:
 	case SCLK_SDMMC:
 		rk_clrsetreg(&cru->cru_clksel_con[11],
-			     MMC0_PLL_MASK << MMC0_PLL_SHIFT |
-			     MMC0_DIV_MASK << MMC0_DIV_SHIFT,
+			     MMC0_PLL_MASK | MMC0_DIV_MASK,
 			     mux << MMC0_PLL_SHIFT |
 			     (src_clk_div - 1) << MMC0_DIV_SHIFT);
 		break;
 	case HCLK_SDIO0:
 	case SCLK_SDIO0:
 		rk_clrsetreg(&cru->cru_clksel_con[12],
-			     SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
-			     SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
+			     SDIO0_PLL_MASK | SDIO0_DIV_MASK,
 			     mux << SDIO0_PLL_SHIFT |
 			     (src_clk_div - 1) << SDIO0_DIV_SHIFT);
 		break;
@@ -598,18 +584,18 @@ static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 	switch (periph) {
 	case SCLK_SPI0:
 		con = readl(&cru->cru_clksel_con[25]);
-		mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK;
-		div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
+		mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT;
+		div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT;
 		break;
 	case SCLK_SPI1:
 		con = readl(&cru->cru_clksel_con[25]);
-		mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK;
-		div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
+		mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT;
+		div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT;
 		break;
 	case SCLK_SPI2:
 		con = readl(&cru->cru_clksel_con[39]);
-		mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK;
-		div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK;
+		mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT;
+		div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT;
 		break;
 	default:
 		return -EINVAL;
@@ -629,22 +615,19 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
 	switch (periph) {
 	case SCLK_SPI0:
 		rk_clrsetreg(&cru->cru_clksel_con[25],
-			     SPI0_PLL_MASK << SPI0_PLL_SHIFT |
-			     SPI0_DIV_MASK << SPI0_DIV_SHIFT,
+			     SPI0_PLL_MASK | SPI0_DIV_MASK,
 			     SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
 			     src_clk_div << SPI0_DIV_SHIFT);
 		break;
 	case SCLK_SPI1:
 		rk_clrsetreg(&cru->cru_clksel_con[25],
-			     SPI1_PLL_MASK << SPI1_PLL_SHIFT |
-			     SPI1_DIV_MASK << SPI1_DIV_SHIFT,
+			     SPI1_PLL_MASK | SPI1_DIV_MASK,
 			     SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
 			     src_clk_div << SPI1_DIV_SHIFT);
 		break;
 	case SCLK_SPI2:
 		rk_clrsetreg(&cru->cru_clksel_con[39],
-			     SPI2_PLL_MASK << SPI2_PLL_SHIFT |
-			     SPI2_DIV_MASK << SPI2_DIV_SHIFT,
+			     SPI2_PLL_MASK | SPI2_DIV_MASK,
 			     SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
 			     src_clk_div << SPI2_DIV_SHIFT);
 		break;
-- 
cgit v1.3.1


From fe974716326ce2eee4bcac710ce7ec007919845e Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Wed, 31 May 2017 17:57:33 -0600
Subject: rockchip: rk3288: Allow setting up clocks in U-Boot proper

If U-Boot is chain-loaded from a previous boot loader we must set up the
clocks the way U-Boot wants them. Add code for this. It will do nothing if
SPL has already done the job.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/arm/mach-rockchip/rk3288-board.c | 35 +++++++++++++++++++++++++++++++++++
 configs/chromebook_jerry_defconfig    |  1 +
 2 files changed, 36 insertions(+)

(limited to 'arch')

diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c
index 18fd0dcd207..a354d992da7 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -309,3 +309,38 @@ U_BOOT_CMD(
 	"display information about clocks",
 	""
 );
+
+#define GRF_SOC_CON2 0xff77024c
+
+int board_early_init_f(void)
+{
+	struct udevice *pinctrl;
+	struct udevice *dev;
+	int ret;
+
+	/*
+	 * This init is done in SPL, but when chain-loading U-Boot SPL will
+	 * have been skipped. Allow the clock driver to check if it needs
+	 * setting up.
+	 */
+	ret = rockchip_get_clk(&dev);
+	if (ret) {
+		debug("CLK init failed: %d\n", ret);
+		return ret;
+	}
+	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+	if (ret) {
+		debug("%s: Cannot find pinctrl device\n", __func__);
+		return ret;
+	}
+
+	/* Enable debug UART */
+	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
+	if (ret) {
+		debug("%s: Failed to set up console UART\n", __func__);
+		return ret;
+	}
+	rk_setreg(GRF_SOC_CON2, 1 << 0);
+
+	return 0;
+}
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 6fc0dcc023f..bb880585e14 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -10,6 +10,7 @@ CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry"
 CONFIG_SILENT_CONSOLE=y
 # CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 # CONFIG_CMD_IMLS is not set
-- 
cgit v1.3.1