From f0baa0a6685db0b59d8e9860c6cfcb942f74697f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 19 Nov 2025 00:17:14 +0100 Subject: stm32mp: Fix handling of OPTEE in the middle of DRAM STM32MP13xx may have OPTEE-OS at 0xdd000000 even on systems with 1 GiB of DRAM at 0xc0000000, which is not the end of DRAM anymore. This puts the OPTEE-OS in the middle of DRAM. Currently, the code sets RAM top to 0xdd000000 and prevents the DRAM range past OPTEE at 0xe0000000..0xffffffff from being set as cacheable and from being usable. The code also sets the area over OPTEE as invalid region in MMU tables, which is not correct. Adjust the code such, that it only ever sets RAM top just before OPTEE in case the OPTEE is really at the end of DRAM, mainly to be backward compatible. Furthermore, adjust the MMU table configuration such, that the regions over the OPTEE are simply skipped and not reconfigured, and the regions between end of OPTEE and RAM top are set as cacheable, if any actually exist. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard Tested-by: Patrice Chotard --- arch/arm/mach-stm32mp/dram_init.c | 4 +++- arch/arm/mach-stm32mp/stm32mp1/cpu.c | 11 ++++++----- 2 files changed, 9 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 34b958d7afd..e36e42e7c61 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -65,6 +65,7 @@ int dram_init(void) phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { + phys_addr_t top = gd->ram_top; phys_size_t size; phys_addr_t reg; u32 optee_start, optee_size; @@ -86,7 +87,8 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) /* Reserved memory for OP-TEE at END of DDR for STM32MP1 SoC */ if (IS_ENABLED(CONFIG_STM32MP13X) || IS_ENABLED(CONFIG_STM32MP15X)) { if (!optee_get_reserved_memory(&optee_start, &optee_size)) - reg = ALIGN(optee_start - size, MMU_SECTION_SIZE); + if (optee_start + optee_size == top) + reg = ALIGN(optee_start - size, MMU_SECTION_SIZE); } /* before relocation, mark the U-Boot memory as cacheable by default */ diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index e0c6f8ba937..252aef1852e 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -82,11 +82,12 @@ void dram_bank_mmu_setup(int bank) i++) { addr = i << MMU_SECTION_SHIFT; option = DCACHE_DEFAULT_OPTION; - if (use_lmb && - (lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP) || - (gd->ram_top && addr >= gd->ram_top)) - ) - option = 0; /* INVALID ENTRY in TLB */ + if (use_lmb) { + if (lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP)) + continue; + if (gd->ram_top && addr >= gd->ram_top) + option = 0; /* INVALID ENTRY in TLB */ + } set_section_dcache(i, option); } } -- cgit v1.3.1 From fd26267b4c2b882363e639c7a1eed97068aaff01 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 19 Nov 2025 00:19:17 +0100 Subject: ARM: dts: stm32: Fix 512 MiB DRAM settings for DH STM32MP13xx DHCOR SoM Update DRAM chip type and density comment for 512 MiB DRAM settings for DH STM32MP13xx DHCOR DHSBC to match the chip on the SoM. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi index 7b344541c3e..b464c04aa2b 100644 --- a/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi @@ -3,13 +3,13 @@ * Copyright (C) 2025, DH electronics - All Rights Reserved * * STM32MP13xx DHSOM configuration - * 1x DDR3L 1Gb, 16-bit, 533MHz, Single Die Package in flyby topology. - * Reference used W631GU6MB15I from Winbond + * 1x DDR3L 4Gb, 16-bit, 533MHz, Single Die Package in flyby topology. + * Reference used W634GU6RB11I from Winbond * * DDR type / Platform DDR3/3L * freq 533MHz * width 16 - * datasheet 0 = W631GU6MB15I / DDR3-1333 + * datasheet 0 = W634GU6RB11I / DDR3-1866 * DDR density 2 * timing mode optimized * address mapping : RBC -- cgit v1.3.1 From 86ff2cfa80e9abb71789b299cfcbfc0b9337174d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 19 Nov 2025 00:19:36 +0100 Subject: ARM: dts: stm32: Add 1 GiB DRAM settings for DH STM32MP13xx DHCOR SoM Add DRAM settings for 1 GiB variant of DH STM32MP13xx DHCOR SoM and support for SoM DRAM coding HW straps decoding and automatic DRAM configuration selection. Enable CONFIG_BOARD_EARLY_INIT_F on all STM32MP1 DHSOM, as it is required for the HW straps decoding. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- .../dts/stm32mp13-ddr3-dhsom-1x4Gb-1066-binG.dtsi | 100 +++++++++++++++++++++ arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi | 1 + board/dhelectronics/dh_stm32mp1/board.c | 30 +++++-- configs/stm32mp15_dhsom.config | 1 - configs/stm32mp_dhsom.config | 1 + 5 files changed, 123 insertions(+), 10 deletions(-) create mode 100644 arch/arm/dts/stm32mp13-ddr3-dhsom-1x4Gb-1066-binG.dtsi (limited to 'arch') diff --git a/arch/arm/dts/stm32mp13-ddr3-dhsom-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x4Gb-1066-binG.dtsi new file mode 100644 index 00000000000..1d268d58b54 --- /dev/null +++ b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x4Gb-1066-binG.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2025, DH electronics - All Rights Reserved + * + * STM32MP13xx DHSOM configuration + * 1x DDR3L 8Gb, 16-bit, 533MHz, Single Die Package in flyby topology. + * Reference used W638GU6QB11I from Winbond + * + * DDR type / Platform DDR3/3L + * freq 533MHz + * width 16 + * datasheet 0 = W638GU6QB11I / DDR3-1866 + * DDR density 4 + * timing mode optimized + * address mapping : RBC + * Tc > + 85C : J + */ +#define DDR_MEM_COMPATIBLE ddr3l-dhsom-1066-888-bin-g-1x4gb-533mhz +#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz" +#define DDR_MEM_SPEED 533000 +#define DDR_MEM_SIZE 0x40000000 + +#define DDR_MSTR 0x00040401 +#define DDR_MRCTRL0 0x00000010 +#define DDR_MRCTRL1 0x00000000 +#define DDR_DERATEEN 0x00000000 +#define DDR_DERATEINT 0x00800000 +#define DDR_PWRCTL 0x00000000 +#define DDR_PWRTMG 0x00400010 +#define DDR_HWLPCTL 0x00000000 +#define DDR_RFSHCTL0 0x00210000 +#define DDR_RFSHCTL3 0x00000000 +#define DDR_RFSHTMG 0x0081008B +#define DDR_CRCPARCTL0 0x00000000 +#define DDR_DRAMTMG0 0x121B2414 +#define DDR_DRAMTMG1 0x000A041B +#define DDR_DRAMTMG2 0x0607080F +#define DDR_DRAMTMG3 0x0050400C +#define DDR_DRAMTMG4 0x07040607 +#define DDR_DRAMTMG5 0x06060403 +#define DDR_DRAMTMG6 0x02020002 +#define DDR_DRAMTMG7 0x00000202 +#define DDR_DRAMTMG8 0x00001005 +#define DDR_DRAMTMG14 0x000000A0 +#define DDR_ZQCTL0 0xC2000040 +#define DDR_DFITMG0 0x02050105 +#define DDR_DFITMG1 0x00000202 +#define DDR_DFILPCFG0 0x07000000 +#define DDR_DFIUPD0 0xC0400003 +#define DDR_DFIUPD1 0x00000000 +#define DDR_DFIUPD2 0x00000000 +#define DDR_DFIPHYMSTR 0x00000000 +#define DDR_ADDRMAP1 0x00080808 +#define DDR_ADDRMAP2 0x00000000 +#define DDR_ADDRMAP3 0x00000000 +#define DDR_ADDRMAP4 0x00001F1F +#define DDR_ADDRMAP5 0x07070707 +#define DDR_ADDRMAP6 0x07070707 +#define DDR_ADDRMAP9 0x00000000 +#define DDR_ADDRMAP10 0x00000000 +#define DDR_ADDRMAP11 0x00000000 +#define DDR_ODTCFG 0x06000600 +#define DDR_ODTMAP 0x00000001 +#define DDR_SCHED 0x00000F01 +#define DDR_SCHED1 0x00000000 +#define DDR_PERFHPR1 0x00000001 +#define DDR_PERFLPR1 0x04000200 +#define DDR_PERFWR1 0x08000400 +#define DDR_DBG0 0x00000000 +#define DDR_DBG1 0x00000000 +#define DDR_DBGCMD 0x00000000 +#define DDR_POISONCFG 0x00000000 +#define DDR_PCCFG 0x00000010 +#define DDR_PCFGR_0 0x00000000 +#define DDR_PCFGW_0 0x00000000 +#define DDR_PCFGQOS0_0 0x00100009 +#define DDR_PCFGQOS1_0 0x00000020 +#define DDR_PCFGWQOS0_0 0x01100B03 +#define DDR_PCFGWQOS1_0 0x01000200 +#define DDR_PGCR 0x01442E02 +#define DDR_PTR0 0x0022AA5B +#define DDR_PTR1 0x04841104 +#define DDR_PTR2 0x042DA068 +#define DDR_ACIOCR 0x10400812 +#define DDR_DXCCR 0x00000C40 +#define DDR_DSGCR 0xF200011F +#define DDR_DCR 0x0000000B +#define DDR_DTPR0 0x36D477D0 +#define DDR_DTPR1 0x098B00D8 +#define DDR_DTPR2 0x10023600 +#define DDR_MR0 0x00000830 +#define DDR_MR1 0x00000000 +#define DDR_MR2 0x00000208 +#define DDR_MR3 0x00000000 +#define DDR_ODTCR 0x00010000 +#define DDR_ZQ0CR1 0x00000038 +#define DDR_DX0GCR 0x0000CE81 +#define DDR_DX1GCR 0x0000CE81 + +#include "stm32mp13-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi index bedb7c600d5..39ac5692e08 100644 --- a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi @@ -6,6 +6,7 @@ #include #include "stm32mp13-u-boot.dtsi" #include "stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi" +#include "stm32mp13-ddr3-dhsom-1x4Gb-1066-binG.dtsi" / { aliases { diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index c18f1911fe4..55526189d5a 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -304,17 +304,29 @@ static void board_get_coding_straps(void) int board_stm32mp1_ddr_config_name_match(struct udevice *dev, const char *name) { - if (ddr3code == 1 && - !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz")) - return 0; + if (IS_ENABLED(CONFIG_TARGET_DH_STM32MP13X)) { + if (ddr3code == 1 && + !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-1x2gb-533mhz")) + return 0; + + if (ddr3code == 2 && + !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-1x4gb-533mhz")) + return 0; + } - if (ddr3code == 2 && - !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz")) - return 0; + if (IS_ENABLED(CONFIG_TARGET_DH_STM32MP15X)) { + if (ddr3code == 1 && + !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz")) + return 0; - if (ddr3code == 3 && - !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz")) - return 0; + if (ddr3code == 2 && + !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz")) + return 0; + + if (ddr3code == 3 && + !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz")) + return 0; + } return -EINVAL; } diff --git a/configs/stm32mp15_dhsom.config b/configs/stm32mp15_dhsom.config index 210ec201bf5..d5ecbac29e0 100644 --- a/configs/stm32mp15_dhsom.config +++ b/configs/stm32mp15_dhsom.config @@ -2,7 +2,6 @@ # CONFIG_ARMV7_VIRT is not set # CONFIG_BINMAN_FDT is not set -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_SIZE_LIMIT=1441792 CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_BOOTDELAY=1 diff --git a/configs/stm32mp_dhsom.config b/configs/stm32mp_dhsom.config index 56a40839d28..31fae2de19d 100644 --- a/configs/stm32mp_dhsom.config +++ b/configs/stm32mp_dhsom.config @@ -6,6 +6,7 @@ # CONFIG_SPL_PARTITION_UUIDS is not set # CONFIG_SPL_PINCTRL_FULL is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_BOOTCOUNT_LIMIT=y CONFIG_CMD_BOOTCOUNT=y -- cgit v1.3.1 From 7da7ca7cf50f4996493b99198e939726e721906d Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 8 Dec 2025 21:47:38 +0100 Subject: Makefile: use --output-target instead of --target The objcopy man-page teaches: --target=bfdname Use bfdname as the object format for both the input and the output file This implies for --target=efi-app-x86_64 that the input file would have to be an EFI app. Objcopy in binutils 2.45 checks this more strictly than previous versions and refuses to accept an ELF file as input with --target=efi-app-x86_64. Replace --target by --output-target for building sandbox and x86 EFI binaries. Signed-off-by: Heinrich Schuchardt Reviewed-by: Tom Rini --- arch/sandbox/config.mk | 4 ++-- arch/x86/config.mk | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index 9a61e803a57..275661a1f3a 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -50,10 +50,10 @@ cmd_u-boot-spl = (cd $(obj) && \ ifeq ($(HOST_ARCH),$(HOST_ARCH_X86_64)) EFI_LDS := ${SRCDIR}/../../../arch/x86/lib/elf_x86_64_efi.lds -EFI_TARGET := --target=efi-app-x86_64 +EFI_TARGET := --output-target=efi-app-x86_64 else ifeq ($(HOST_ARCH),$(HOST_ARCH_X86)) EFI_LDS := ${SRCDIR}/../../../arch/x86/lib/elf_ia32_efi.lds -EFI_TARGET := --target=efi-app-ia32 +EFI_TARGET := --output-target=efi-app-ia32 else ifeq ($(HOST_ARCH),$(HOST_ARCH_AARCH64)) EFI_LDS := ${SRCDIR}/../../../arch/arm/lib/elf_aarch64_efi.lds OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \ diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 6d4839dfb38..c2bb5549b7c 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -69,7 +69,7 @@ endif LDSCRIPT_EFI := $(srctree)/arch/x86/lib/elf_$(EFIARCH)_efi.lds EFISTUB := crt0_$(EFIARCH)_efi.o reloc_$(EFIARCH)_efi.o -OBJCOPYFLAGS_EFI += --target=efi-app-$(EFIARCH) +OBJCOPYFLAGS_EFI += --output-target=efi-app-$(EFIARCH) CPPFLAGS_REMOVE_crt0-efi-$(EFIARCH).o += $(CFLAGS_NON_EFI) CPPFLAGS_crt0-efi-$(EFIARCH).o += $(CFLAGS_EFI) @@ -127,7 +127,7 @@ endif endif ifdef CONFIG_X86_64 -EFI_TARGET := --target=efi-app-x86_64 +EFI_TARGET := --output-target=efi-app-x86_64 else -EFI_TARGET := --target=efi-app-ia32 +EFI_TARGET := --output-target=efi-app-ia32 endif -- cgit v1.3.1 From b57363a2b9b6bbc6a4fa63d93681485b812ccc51 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 2 Aug 2025 22:07:22 +0000 Subject: rockchip: Move TEXT_BASE to 8 MiB offset from start of DRAM Drop SoC specific TEXT_BASE and use a common TEXT_BASE for all SoCs. Move the common TEXT_BASE to 8 MiB offset from start of DRAM to help support RAM boot from maskrom introduced in next patch. RAM boot from maskrom mode will expect the FIT payload to be located at 2 MiB offset from start or DRAM. Signed-off-by: Jonas Karlman Tested-by: Arnaud Patard Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 6 +++--- arch/arm/mach-rockchip/rk3308/Kconfig | 3 --- arch/arm/mach-rockchip/rk3568/Kconfig | 3 --- arch/arm/mach-rockchip/rk3588/Kconfig | 3 --- 4 files changed, 3 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 342933ca509..c9ce3076029 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -768,9 +768,9 @@ config TPL_SYS_MALLOC_F_LEN default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000 config TEXT_BASE - default 0x60200000 if SPL_TEXT_BASE = 0x60000000 - default 0x40200000 if SPL_TEXT_BASE = 0x40000000 - default 0x00200000 if SPL_TEXT_BASE = 0x00000000 + default 0x60800000 if SPL_TEXT_BASE = 0x60000000 + default 0x40800000 if SPL_TEXT_BASE = 0x40000000 + default 0x00800000 if SPL_TEXT_BASE = 0x00000000 config SPL_TEXT_BASE default 0x60000000 if ROCKCHIP_RK3036 || ROCKCHIP_RK3066 || \ diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index 06572d545f6..b8d25c52542 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -17,9 +17,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3308" -config TEXT_BASE - default 0x00600000 - source "board/rockchip/evb_rk3308/Kconfig" source "board/firefly/firefly-rk3308/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index 01b53a47ddb..2730220a18e 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -70,9 +70,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3568" -config TEXT_BASE - default 0x00a00000 - source "board/rockchip/evb_rk3568/Kconfig" source "board/anbernic/rgxx3_rk3566/Kconfig" source "board/hardkernel/odroid_m1/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 9fbe3f225aa..60c16d2f32d 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -417,9 +417,6 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3588" -config TEXT_BASE - default 0x00a00000 - source "board/armsom/sige7-rk3588/Kconfig" source "board/coolpi/genbook_cm5_rk3588/Kconfig" source "board/edgeble/neural-compute-module-6/Kconfig" -- cgit v1.3.1 From e22335a221f88e7f61171e752ca195663f86d81f Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 2 Aug 2025 22:07:23 +0000 Subject: rockchip: Add support for RAM boot from maskrom mode The BootROM in Rockchip SoCs will enter maskrom mode when boot firmware cannot be found in nand/spi/mmc storage. In maskrom mode the USB OTG port can accept one of two custom commands. Initially a 0x471 command to load TPL into SRAM. After TPL has been executed and it has returned back-to-BROM, a 0x472 command to load SPL into start of DRAM. Add two binman images that can be used to RAM boot from maskrom mode: - u-boot-rockchip-usb471.bin that contains TPL to init DRAM. - u-boot-rockchip-usb472.bin that contains SPL and the normal FIT payload with i.e. U-Boot proper, TF-A and FDT. A config fragment rockchip-ramboot.config can be used to enable building of these two binman images, e.g.: make generic-rk3588_defconfig rockchip-ramboot.config These binman images can be used with the proprietary rkbin boot_merger tool to create a special loader image that can be used with tools such as rkdeveloptool or rockusb tools to RAM boot from maskrom, e.g.: Create loader image: $ ../rkbin/tools/boot_merger ./RK3588MINIALL.ini Boot from maskrom: $ rkdeveloptool db u-boot-rockchip-rk3588-loader.bin or $ rockusb download-boot u-boot-rockchip-rk3588-loader.bin Another option that does not require use of proprietary tools is using open source tools such as rkflashtool or rkusbboot that can load the binman images directly without any need to first create a special loader image to RAM boot from maskrom, e.g.: $ rkflashtool l < u-boot-rockchip-usb471.bin $ rkflashtool L < u-boot-rockchip-usb472.bin or $ rkusbboot u-boot-rockchip-usb471.bin u-boot-rockchip-usb472.bin Signed-off-by: Jonas Karlman Tested-by: Arnaud Patard Reviewed-by: Kever Yang --- arch/arm/dts/rockchip-u-boot.dtsi | 33 +++++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/Kconfig | 8 ++++++++ arch/arm/mach-rockchip/spl-boot-order.c | 14 +++++++++++--- board/rockchip/rockchip-ramboot.config | 1 + boot/Kconfig | 3 +++ 5 files changed, 56 insertions(+), 3 deletions(-) create mode 100644 board/rockchip/rockchip-ramboot.config (limited to 'arch') diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi index cc2feed6464..71d7623fe2c 100644 --- a/arch/arm/dts/rockchip-u-boot.dtsi +++ b/arch/arm/dts/rockchip-u-boot.dtsi @@ -226,5 +226,38 @@ }; }; #endif /* CONFIG_ROCKCHIP_SPI_IMAGE */ + +#ifdef CONFIG_ROCKCHIP_MASKROM_IMAGE + simple-bin-usb471 { + filename = "u-boot-rockchip-usb471.bin"; + +#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL + rockchip-tpl { + }; +#elif defined(CONFIG_TPL) + u-boot-tpl { + no-write-symbols; + }; +#endif + }; + + simple-bin-usb472 { + filename = "u-boot-rockchip-usb472.bin"; + pad-byte = <0x00>; + + u-boot-spl { + no-write-symbols; + }; + +#ifdef HAS_FIT + fit { + insert-template = <&fit_template>; +#else + u-boot-img { +#endif + offset = <(CONFIG_SPL_LOAD_FIT_ADDRESS - CFG_SYS_SDRAM_BASE)>; + }; + }; +#endif /* CONFIG_ROCKCHIP_MASKROM_IMAGE */ }; #endif /* CONFIG_SPL */ diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c9ce3076029..e32e49ff59a 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -706,6 +706,14 @@ config ROCKCHIP_SPI_IMAGE option to produce a SPI-flash image containing U-Boot. The image is built by binman. U-Boot sits near the start of the image. +config ROCKCHIP_MASKROM_IMAGE + bool "Build a maskrom mode image for Rockchip" + depends on TPL || ROCKCHIP_EXTERNAL_TPL + select SPL_RAM_DEVICE + help + Rockchip SoCs support maskrom mode boot over USB. Enable this + option to produce maskrom mode boot images containing U-Boot. + config LNX_KRNL_IMG_TEXT_OFFSET_BASE default TEXT_BASE diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 1ea1033b5ea..6572dde29f6 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -98,15 +99,22 @@ __weak const char *board_spl_was_booted_from(void) void board_boot_order(u32 *spl_boot_list) { + int idx = 0; + + /* Add RAM boot for maskrom mode boot over USB */ + if (BROM_BOOTSOURCE_ID_ADDR && CONFIG_IS_ENABLED(RAM_DEVICE) && + read_brom_bootsource_id() == BROM_BOOTSOURCE_USB) { + spl_boot_list[idx++] = BOOT_DEVICE_RAM; + } + /* In case of no fdt (or only plat), use spl_boot_device() */ if (!CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_PLATDATA)) { - spl_boot_list[0] = spl_boot_device(); + spl_boot_list[idx++] = spl_boot_device(); return; } const void *blob = gd->fdt_blob; int chosen_node = fdt_path_offset(blob, "/chosen"); - int idx = 0; int elem; int boot_device; int node; @@ -115,7 +123,7 @@ void board_boot_order(u32 *spl_boot_list) if (chosen_node < 0) { debug("%s: /chosen not found, using spl_boot_device()\n", __func__); - spl_boot_list[0] = spl_boot_device(); + spl_boot_list[idx++] = spl_boot_device(); return; } diff --git a/board/rockchip/rockchip-ramboot.config b/board/rockchip/rockchip-ramboot.config new file mode 100644 index 00000000000..312363e542b --- /dev/null +++ b/board/rockchip/rockchip-ramboot.config @@ -0,0 +1 @@ +CONFIG_ROCKCHIP_MASKROM_IMAGE=y diff --git a/boot/Kconfig b/boot/Kconfig index 85f4d468069..245e120c70b 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -275,6 +275,9 @@ config SPL_LOAD_FIT_ADDRESS hex "load address of fit image" depends on SPL_LOAD_FIT default 0x44000000 if ARCH_IMX8M + default 0x60080000 if ARCH_ROCKCHIP && SPL_TEXT_BASE = 0x60000000 + default 0x40200000 if ARCH_ROCKCHIP && SPL_TEXT_BASE = 0x40000000 + default 0x00200000 if ARCH_ROCKCHIP && SPL_TEXT_BASE = 0x00000000 default 0x0 help Specify the load address of the fit image that will be loaded -- cgit v1.3.1 From 57dc75fb9be8f2508cb8c32dc5909c5b57876ace Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 17:09:27 +0000 Subject: rockchip: sdram: Add rockchip_sdram_type() helper Add a helper function based on rockchip_sdram_size() that return what DRAM type is used on current running board. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/sdram.h | 3 +++ arch/arm/mach-rockchip/sdram.c | 15 +++++++++++++++ 2 files changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h index 4fb45ac5c76..476fc1c4ee3 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram.h +++ b/arch/arm/include/asm/arch-rockchip/sdram.h @@ -87,6 +87,9 @@ enum { #define SYS_REG_CS1_COL_SHIFT(ch) (0 + (ch) * 2) #define SYS_REG_CS1_COL_MASK 3 +/* Get sdram type decode from reg */ +u8 rockchip_sdram_type(phys_addr_t reg); + /* Get sdram size decode from reg */ size_t rockchip_sdram_size(phys_addr_t reg); diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 3bc482331c7..d560f90e873 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -345,6 +345,21 @@ int dram_init_banksize(void) return 0; } +u8 rockchip_sdram_type(phys_addr_t reg) +{ + u32 dram_type, version; + u32 sys_reg2 = readl(reg); + u32 sys_reg3 = readl(reg + 4); + + dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK; + version = (sys_reg3 >> SYS_REG_VERSION_SHIFT) & SYS_REG_VERSION_MASK; + if (version >= 3) + dram_type |= ((sys_reg3 >> SYS_REG_EXTEND_DDRTYPE_SHIFT) & + SYS_REG_EXTEND_DDRTYPE_MASK) << 3; + + return dram_type; +} + size_t rockchip_sdram_size(phys_addr_t reg) { u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; -- cgit v1.3.1 From 2df3666a241b706005ac8130c06188678c32ba39 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 1 Aug 2025 17:09:28 +0000 Subject: rockchip: rock5b-rk3588: Add support for ROCK 5B+ Include FDTs for both ROCK 5B and 5B+ in the FIT and add board selection code to load the 5B+ FDT when the DRAM type is LPDDR5 and ADC channel 5 value is close to 4095. U-Boot 2025.07 (Jul 14 2025 - 21:28:20 +0000) Model: Radxa ROCK 5B+ SoC: RK3588 DRAM: 8 GiB Features tested on a ROCK 5B+ v1.2: - SD-card boot - eMMC boot - SPI flash boot - PCIe/NVMe - Ethernet - USB/TCPM Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi | 3 ++ arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 5 +++ board/radxa/rock5b-rk3588/Kconfig | 5 +++ board/radxa/rock5b-rk3588/MAINTAINERS | 3 +- board/radxa/rock5b-rk3588/rock5b-rk3588.c | 63 ++++++++++++++++++++++++++++ configs/rock5b-rk3588_defconfig | 1 + doc/board/rockchip/rockchip.rst | 2 +- 7 files changed, 79 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi (limited to 'arch') diff --git a/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi new file mode 100644 index 00000000000..c07696c8391 --- /dev/null +++ b/arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-rock-5b-u-boot.dtsi" diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index d51fbf51cb8..e07b549c767 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -46,6 +46,11 @@ }; }; +&saradc { + bootph-pre-ram; + vdd-microvolts = <1800000>; +}; + &sdhci { cap-mmc-highspeed; mmc-hs200-1_8v; diff --git a/board/radxa/rock5b-rk3588/Kconfig b/board/radxa/rock5b-rk3588/Kconfig index 41dfe2402b1..98d63011783 100644 --- a/board/radxa/rock5b-rk3588/Kconfig +++ b/board/radxa/rock5b-rk3588/Kconfig @@ -9,4 +9,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "rock5b-rk3588" +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ADC + select SPL_ADC + endif diff --git a/board/radxa/rock5b-rk3588/MAINTAINERS b/board/radxa/rock5b-rk3588/MAINTAINERS index 4460c9971a9..c8a43769105 100644 --- a/board/radxa/rock5b-rk3588/MAINTAINERS +++ b/board/radxa/rock5b-rk3588/MAINTAINERS @@ -5,5 +5,4 @@ S: Maintained F: board/radxa/rock5b-rk3588 F: include/configs/rock5b-rk3588.h F: configs/rock5b-rk3588_defconfig -F: arch/arm/dts/rk3588-rock-5b.dts -F: arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +F: arch/arm/dts/rk3588-rock-5b* diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c b/board/radxa/rock5b-rk3588/rock5b-rk3588.c index fc2f69db224..6bf4497ce3a 100644 --- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c +++ b/board/radxa/rock5b-rk3588/rock5b-rk3588.c @@ -3,8 +3,71 @@ * Copyright (c) 2023-2024 Collabora Ltd. */ +#include +#include #include #include +#include +#include + +#define PMU1GRF_BASE 0xfd58a000 +#define OS_REG2_REG 0x208 + +#define HW_ID_CHANNEL 5 + +struct board_model { + unsigned int dram; + unsigned int low; + unsigned int high; + const char *fdtfile; +}; + +static const struct board_model board_models[] = { + { LPDDR5, 4005, 4185, "rockchip/rk3588-rock-5b-plus.dtb" }, +}; + +static const struct board_model *get_board_model(void) +{ + unsigned int val, dram_type; + int i, ret; + + dram_type = rockchip_sdram_type(PMU1GRF_BASE + OS_REG2_REG); + + ret = adc_channel_single_shot("adc@fec10000", HW_ID_CHANNEL, &val); + if (ret) + return NULL; + + for (i = 0; i < ARRAY_SIZE(board_models); i++) { + unsigned int dram = board_models[i].dram; + unsigned int min = board_models[i].low; + unsigned int max = board_models[i].high; + + if (dram == dram_type && min <= val && val <= max) + return &board_models[i]; + } + + return NULL; +} + +int rk_board_late_init(void) +{ + const struct board_model *model = get_board_model(); + + if (model) + env_set("fdtfile", model->fdtfile); + + return 0; +} + +int board_fit_config_name_match(const char *name) +{ + const struct board_model *model = get_board_model(); + + if (model && !strcmp(name, model->fdtfile)) + return 0; + + return -EINVAL; +} #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 6349e879145..967cebc2054 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -47,6 +47,7 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y +CONFIG_OF_LIST="rockchip/rk3588-rock-5b rockchip/rk3588-rock-5b-plus" CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 0acccb51ad5..9af701feb5d 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -162,7 +162,7 @@ List of mainline supported Rockchip boards: - Pine64 QuartzPro64 (quartzpro64-rk3588) - Radxa ROCK 5 ITX (rock-5-itx-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) - - Radxa ROCK 5B (rock5b-rk3588) + - Radxa ROCK 5B/5B+ (rock5b-rk3588) - Radxa ROCK 5C (rock-5c-rk3588s) - Rockchip Toybrick TB-RK3588X (toybrick-rk3588) - Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588) -- cgit v1.3.1 From 73159af02d023d01d9c4c08d319eb86cb10f1983 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Fri, 7 Nov 2025 06:47:16 +0000 Subject: rockchip: rock5b-rk3588: Add support for Radxa ROCK 5T Include the FDT for Radxa ROCK 5T in the FIT, in addition to those for 5B and 5B+, and add board selection code to load the 5T FDT when the DRAM type is LPDDR5 and ADC channel 5 value is close to 1016. Signed-off-by: FUKAUMI Naoki Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-rock-5t-u-boot.dtsi | 3 +++ board/radxa/rock5b-rk3588/rock5b-rk3588.c | 1 + configs/rock5b-rk3588_defconfig | 2 +- doc/board/rockchip/rockchip.rst | 2 +- 4 files changed, 6 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/rk3588-rock-5t-u-boot.dtsi (limited to 'arch') diff --git a/arch/arm/dts/rk3588-rock-5t-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5t-u-boot.dtsi new file mode 100644 index 00000000000..c07696c8391 --- /dev/null +++ b/arch/arm/dts/rk3588-rock-5t-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-rock-5b-u-boot.dtsi" diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c b/board/radxa/rock5b-rk3588/rock5b-rk3588.c index 6bf4497ce3a..2c172d04499 100644 --- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c +++ b/board/radxa/rock5b-rk3588/rock5b-rk3588.c @@ -23,6 +23,7 @@ struct board_model { }; static const struct board_model board_models[] = { + { LPDDR5, 926, 1106, "rockchip/rk3588-rock-5t.dtb" }, { LPDDR5, 4005, 4185, "rockchip/rk3588-rock-5b-plus.dtb" }, }; diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 967cebc2054..567f649ea69 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_LIST="rockchip/rk3588-rock-5b rockchip/rk3588-rock-5b-plus" +CONFIG_OF_LIST="rockchip/rk3588-rock-5b rockchip/rk3588-rock-5b-plus rockchip/rk3588-rock-5t" CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 9af701feb5d..6ae4d4371ff 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -162,7 +162,7 @@ List of mainline supported Rockchip boards: - Pine64 QuartzPro64 (quartzpro64-rk3588) - Radxa ROCK 5 ITX (rock-5-itx-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) - - Radxa ROCK 5B/5B+ (rock5b-rk3588) + - Radxa ROCK 5B/5B+/5T (rock5b-rk3588) - Radxa ROCK 5C (rock-5c-rk3588s) - Rockchip Toybrick TB-RK3588X (toybrick-rk3588) - Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588) -- cgit v1.3.1 From 029e6f250cd5caa166f37c5bbb3d00af2cff9baf Mon Sep 17 00:00:00 2001 From: Tanmay Kathpalia Date: Mon, 15 Dec 2025 03:01:14 -0800 Subject: Revert "arch: arm: dts: agilex5: Set SDIO_SEL GPIO pin as output" Remove GPIO hog configuration for SDIO_SEL pin as it is now handled through the voltage regulator framework for SD ultra high speed mode support. The GPIO pin 3 on portb controller is used to control the level shifter for SD card I/O voltage switching. The regulator-based approach provides proper voltage switching control for UHS-I modes (SDR50, SDR104) while maintaining compatibility with the MMC subsystem's voltage switching protocols. This reverts commit b0dbc9fcb7dfb7522be25ee205997be2fb5e1bdc. Signed-off-by: Tanmay Kathpalia Reviewed-by: Tien Fong Chee --- arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 11 ----------- configs/socfpga_agilex5_defconfig | 3 --- 2 files changed, 14 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index d51a9e2ff7f..35b198b79ef 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -681,17 +681,6 @@ bootph-all; }; -&gpio1 { - /* Configure GPIO 1 pin 3 as output pin with value 0 during GPIO probe */ - portb: gpio-controller@0{ - sdio_sel { - gpio-hog; - gpios = <3 GPIO_ACTIVE_HIGH>; - output-low; - }; - }; -}; - &i2c0 { reset-names = "i2c"; }; diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 64f2f1bf115..799ea910f03 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_ARCH_SOCFPGA=y CONFIG_TEXT_BASE=0x80200000 -CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=3 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000 @@ -79,8 +78,6 @@ CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y -CONFIG_GPIO_HOG=y -CONFIG_SPL_GPIO_HOG=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y -- cgit v1.3.1 From eb367367301ceee26bf94a7a134a894a1a6cd775 Mon Sep 17 00:00:00 2001 From: Tanmay Kathpalia Date: Mon, 15 Dec 2025 03:01:15 -0800 Subject: arm: dts: socfpga: agilex5: Upgrade SDHCI controller from SD4HC to SD6HC Upgrade the SDHCI Cadence controller from SD4HC to SD6HC for Agilex5 platform to support the newer controller version with enhanced features. Key changes: - Remove combophy0 node and associated references as SD6HC doesn't require separate PHY configuration node - Upgrade MMC controller compatible from "cdns,sd4hc" to "cdns,sd6hc" - Add Agilex5-specific compatible string "altr,agilex5-sd6hc" for platform-specific optimizations Hardware configuration updates: - Add voltage regulator support: * sd_emmc_power: Fixed 3.3V regulator for card power supply * sd_io_1v8_reg: GPIO-controlled regulator for 1.8V/3.3V I/O switching - Configure proper reset control with named resets including combophy reset - Add GPIO control via portb pin 3 for voltage switching SD card operation: - Configure for SD card specific operation (no-mmc, cap-sd-highspeed) - Set maximum frequency to 200MHz - Configure timing parameters for SD modes: * Default Speed (DS) and UHS-I SDR12 mode timing: * High Speed and UHS-I SDR25 mode timing: - Add PHY timing delays for optimal signal integrity Signed-off-by: Tanmay Kathpalia Reviewed-by: Tien Fong Chee --- arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 3 +- arch/arm/dts/socfpga_agilex5.dtsi | 29 +++++----- arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 77 ++++++++++++-------------- drivers/mmc/sdhci-cadence.c | 1 + 4 files changed, 54 insertions(+), 56 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index 35b198b79ef..0f0f457de54 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -698,7 +698,8 @@ }; &mmc { - resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; + resets = <&rst COMBOPHY_RESET>, <&rst SDMMC_OCP_RESET>, <&rst SDMMC_RESET>; + reset-names = "combophy", "sdmmc-ocp", "sdhc-reset"; }; &porta { diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi index 7f4266dd5f1..769678af31a 100644 --- a/arch/arm/dts/socfpga_agilex5.dtsi +++ b/arch/arm/dts/socfpga_agilex5.dtsi @@ -303,30 +303,33 @@ status = "disabled"; }; - combophy0: combophy@0 { - #phy-cells = <0>; - phy-type = <1>; - compatible = "cdns,combophy"; - reg = <0x10808000 0x1000>; - resets = <&rst COMBOPHY_RESET>; - reset-names = "reset"; - status = "disabled"; + sd_emmc_power: regulator-fixed-3p3v { + compatible = "regulator-fixed"; + regulator-name = "card-power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sd_io_1v8_reg: regulator-1p8v { + compatible = "regulator-gpio"; + regulator-name = "sd-bus-io-power"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x1>, + <3300000 0x0>; }; mmc: mmc0@10808000 { #address-cells = <1>; #size-cells = <0>; - compatible = "cdns,sd4hc"; + compatible = "altr,agilex5-sd6hc", "cdns,sd6hc"; reg = <0x10808000 0x1000>; interrupts = <0 96 4>; - phys = <&combophy0>; - phy-names = "combo-phy"; clocks = <&clkmgr AGILEX5_L4_MP_CLK>, <&clkmgr AGILEX5_SDMMC_CLK>; clock-names = "biu", "ciu"; fifo-depth = <0x800>; - resets = <&rst SDMMC_RESET>; - reset-names = "reset"; iommus = <&smmu 5>; status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi index 938ddb04c04..5a7aa5841e3 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -91,53 +91,46 @@ bootph-all; }; -&mmc { - status = "okay"; - bus-width = <4>; - sd-uhs-sdr50; - cap-mmc-highspeed; +&gpio1 { + portb: gpio-controller@0 { + bootph-all; + }; +}; + +&sd_emmc_power { bootph-all; }; -&combophy0 { +&sd_io_1v8_reg { + gpios = <&portb 3 GPIO_ACTIVE_HIGH>; + bootph-all; +}; + +&mmc { status = "okay"; + + no-mmc; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + vmmc-supply = <&sd_emmc_power>; + vqmmc-supply = <&sd_io_1v8_reg>; + max-frequency = <200000000>; + + /* SD card default speed (DS) and UHS-I SDR12 mode timing configuration */ + cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>; + cdns,phy-gate-lpbk_ctrl-delay-sd-ds = <0x81a40040>; + cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>; + cdns,phy-dq-timing-delay-sd-ds = <0x28000001>; + + /* SD card high speed and UHS-I SDR25 mode timing configuration */ + cdns,phy-dqs-timing-delay-sd-hs = <0x780001>; + cdns,phy-gate-lpbk_ctrl-delay-sd-hs = <0x81a40040>; + cdns,phy-dq-timing-delay-sd-hs = <0x10000001>; + cdns,ctrl-hrs16-slave-ctrl-sd-hs = <0x101>; + cdns,ctrl-hrs07-timing-delay-sd-hs = <0xA0001>; + bootph-all; - cdns,phy-use-ext-lpbk-dqs = <1>; - cdns,phy-use-lpbk-dqs = <1>; - cdns,phy-use-phony-dqs = <1>; - cdns,phy-use-phony-dqs-cmd = <1>; - cdns,phy-io-mask-always-on = <0>; - cdns,phy-io-mask-end = <5>; - cdns,phy-io-mask-start = <0>; - cdns,phy-data-select-oe-end = <1>; - cdns,phy-sync-method = <1>; - cdns,phy-sw-half-cycle-shift = <0>; - cdns,phy-rd-del-sel = <52>; - cdns,phy-underrun-suppress = <1>; - cdns,phy-gate-cfg-always-on = <1>; - cdns,phy-param-dll-bypass-mode = <1>; - cdns,phy-param-phase-detect-sel = <2>; - cdns,phy-param-dll-start-point = <254>; - cdns,phy-read-dqs-cmd-delay = <0>; - cdns,phy-clk-wrdqs-delay = <0>; - cdns,phy-clk-wr-delay = <0>; - cdns,phy-read-dqs-delay = <0>; - cdns,phy-phony-dqs-timing = <0>; - cdns,hrs09-rddata-en = <1>; - cdns,hrs09-rdcmd-en = <1>; - cdns,hrs09-extended-wr-mode = <1>; - cdns,hrs09-extended-rd-mode = <1>; - cdns,hrs10-hcsdclkadj = <3>; - cdns,hrs16-wrdata1-sdclk-dly = <0>; - cdns,hrs16-wrdata0-sdclk-dly = <0>; - cdns,hrs16-wrcmd1-sdclk-dly = <0>; - cdns,hrs16-wrcmd0-sdclk-dly = <0>; - cdns,hrs16-wrdata1-dly = <0>; - cdns,hrs16-wrdata0-dly = <0>; - cdns,hrs16-wrcmd1-dly = <0>; - cdns,hrs16-wrcmd0-dly = <0>; - cdns,hrs07-rw-compensate = <10>; - cdns,hrs07-idelay-val = <0>; }; &qspi { diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index 7d169efa476..6cdb7f95cc5 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -260,6 +260,7 @@ static int sdhci_cdns_probe(struct udevice *dev) static const struct udevice_id sdhci_cdns_match[] = { { .compatible = "socionext,uniphier-sd4hc" }, { .compatible = "cdns,sd4hc" }, + { .compatible = "altr,agilex5-sd6hc" }, { .compatible = "cdns,sd6hc" }, { /* sentinel */ } }; -- cgit v1.3.1 From ed7725c25e43cbb288cfc35080334db7728e358a Mon Sep 17 00:00:00 2001 From: Tanmay Kathpalia Date: Mon, 15 Dec 2025 03:01:17 -0800 Subject: arm: dts: socfpga: agilex5: Add dedicated eMMC device tree support Add dedicated device tree support for eMMC configuration on the Agilex5 SoCDK board, providing an alternative to the default SD card setup. Changes to socfpga_agilex5.dtsi: - - Configure always-on regulator for stable eMMC operation New device tree files: - socfpga_agilex5_socdk_emmc.dts: Main eMMC device tree configuration * Configure for eMMC operation (no-sd, no-sdio, non-removable) * Set 8-bit bus width and high speed capability * Add timing parameters for legacy and SDR modes * Configure voltage supplies for eMMC power and I/O * Add fixed 1.8V regulator for eMMC I/O voltage supply - socfpga_agilex5_socdk_emmc-u-boot.dtsi: U-Boot specific additions * Include common Agilex5 U-Boot configurations * Set SPL boot order with eMMC support * Enable necessary peripherals for boot-time operation Configuration files: - configs/socfpga_agilex5_emmc_defconfig: eMMC-specific configuration * Inherit from base Agilex5 configuration * Disable GPIO regulator support (not needed for fixed eMMC setup) * Set eMMC-specific device tree Build system integration: - Add socfpga_agilex5_socdk_emmc.dtb target to Makefile Signed-off-by: Tanmay Kathpalia Reviewed-by: Tien Fong Chee --- arch/arm/dts/Makefile | 1 + .../arm/dts/socfpga_agilex5_socdk_emmc-u-boot.dtsi | 172 +++++++++++++++++++++ arch/arm/dts/socfpga_agilex5_socdk_emmc.dts | 49 ++++++ configs/socfpga_agilex5_emmc_defconfig | 6 + 4 files changed, 228 insertions(+) create mode 100644 arch/arm/dts/socfpga_agilex5_socdk_emmc-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk_emmc.dts create mode 100644 configs/socfpga_agilex5_emmc_defconfig (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fcad6fb2fc7..4e39c795e1e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -451,6 +451,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_agilex5_socdk.dtb \ + socfpga_agilex5_socdk_emmc.dtb \ socfpga_arria5_secu1.dtb \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3_270_2.dtb \ diff --git a/arch/arm/dts/socfpga_agilex5_socdk_emmc-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk_emmc-u-boot.dtsi new file mode 100644 index 00000000000..3c03b00c0d9 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_socdk_emmc-u-boot.dtsi @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions for Agilex5 SocDK eMMC + * + * Copyright (C) 2025 Altera Corporation + */ + +#include "socfpga_agilex5-u-boot.dtsi" + +/{ + aliases { + spi0 = &qspi; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@0x20000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0x20000450 0x00000010>; + status = "disabled"; + }; + }; + + /* + * Both Memory base address and size default info is retrieved from HW setting. + * Reconfiguration / Overwrite these info can be done with examples below. + * + * When LPDDR ECC is enabled, the last 1/8 of the memory region must + * be reserved for the Inline ECC buffer. + * + * Example for memory size with 2GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>; + * }; + * + * Example for memory size with 8GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x1 0x80000000>; + * }; + * + * Example for memory size with 32GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x7 0x80000000>; + * }; + * + * Example for memory size with 512GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x7 0x80000000>, + * <0x88 0x00000000 0x78 0x00000000>; + * }; + * + * Example for memory size with 2GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x80000000 0x0 0x70000000>; + * }; + * + * Example for memory size with 8GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x1 0x40000000>; + * }; + */ + + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &mmc,&flash0,&nand,"/memory"; + }; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + bootph-all; + /delete-property/ cdns,read-delay; +}; + +&flash1 { + bootph-all; +}; + +&i3c0 { + bootph-all; +}; + +&i3c1 { + bootph-all; +}; + +&gpio1 { + portb: gpio-controller@0 { + bootph-all; + }; +}; + +&sd_emmc_power { + bootph-all; +}; + +&emmc_io_1v8_reg { + bootph-all; +}; + +&mmc { + bootph-all; +}; + +&qspi { + status = "okay"; +}; + +&nand { + status = "disabled"; + bootph-all; +}; + +&timer0 { + bootph-all; +}; + +&timer1 { + bootph-all; +}; + +&timer2 { + bootph-all; +}; + +&timer3 { + bootph-all; +}; + +&watchdog0 { + bootph-all; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&emac0_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac0_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&emac2_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac2_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts new file mode 100644 index 00000000000..f6848c373cd --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation + */ + +#include "socfpga_agilex5_socdk.dts" + +/ { + soc { + emmc_io_1v8_reg: regulator-fixed-1p8v { + compatible = "regulator-fixed"; + regulator-name = "emmc-io-power"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; +}; + +&mmc { + status = "okay"; + + no-sd; + no-sdio; + disable-wp; + non-removable; + cap-mmc-highspeed; + + bus-width = <8>; + vmmc-supply = <&sd_emmc_power>; + vqmmc-supply = <&emmc_io_1v8_reg>; + max-frequency = <200000000>; + + /* eMMC legacy mode timing configuration */ + cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>; + cdns,phy-gate-lpbk-ctrl-delay-sd-ds = <0x81a40040>; + cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>; + cdns,phy-dq-timing-delay-sd-ds = <0x28000001>; + + /* eMMC SDR mode timing configuration */ + cdns,phy-dqs-timing-delay-emmc-sdr = <0x780001>; + cdns,phy-gate-lpbk-ctrl-delay-emmc-sdr = <0x81a40040>; + cdns,phy-dll-slave-ctrl-emmc-sdr = <0x00000000>; + cdns,phy-dq-timing-delay-emmc-sdr = <0x10000001>; + cdns,ctrl-hrs09-timing-delay-emmc-sdr = <0x1800c>; + cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x30000>; + cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>; + cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0xA0001>; +}; diff --git a/configs/socfpga_agilex5_emmc_defconfig b/configs/socfpga_agilex5_emmc_defconfig new file mode 100644 index 00000000000..9254ab92e0c --- /dev/null +++ b/configs/socfpga_agilex5_emmc_defconfig @@ -0,0 +1,6 @@ +#include + +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk_emmc" +# CONFIG_SPL_DM_REGULATOR_GPIO is not set +# CONFIG_DM_REGULATOR_GPIO is not set +# CONFIG_SPL_DWAPB_GPIO is not set -- cgit v1.3.1 From 1cf1b504f412121aa5929d12beb3d7f6cf3ac50e Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Thu, 11 Dec 2025 17:34:58 +0100 Subject: arch: arm: mach-socfpga: Adjust a raw sectors for MMC loading of U-Boot from SPL If U-Boot is located on MMC, SPL and U-Boot proper are glued together. More precisely, SPL is stored 4 times. Take this and its padding into account and adjust sector number via board_spl_mmc_get_uboot_raw_sector. This allows loading from a partition, without the need to hard-code the offset via SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR Signed-off-by: Jan Kiszka Reviewed-by: Tien Fong Chee --- arch/arm/mach-socfpga/board.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 28554b7a109..7f65aed4540 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -209,3 +210,13 @@ void lmb_arch_add_memory(void) } } #endif + +#if (defined(CONFIG_TARGET_SOCFPGA_ARRIA10) || \ + defined(CONFIG_TARGET_SOCFPGA_GEN5)) && defined(CONFIG_XPL_BUILD) +unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, + unsigned long raw_sect) +{ + /* offset of u-boot proper inside u-boot-with-spl.sfp image */ + return (CONFIG_SPL_PAD_TO * 4) / 512 + raw_sect; +} +#endif -- cgit v1.3.1