From 9850d4e52f7f8da1bab7fae32f90e8eba7b4f6af Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 27 Sep 2019 19:14:28 +0300 Subject: board: ti: am43xx-idk: Configure the CDCE913 clock synthesizer AM43xx-IDK boards contain the CDCE913 clock synthesizer, and their reset crystal capacitance load value of 10pF is wrong leading into lost packets in certain networking tests. Add DT data for this device, and probe it from the board file to program the crystal capacitance load value to 0pF to avoid any problems. Signed-off-by: Tero Kristo --- arch/arm/dts/am437x-idk-evm-u-boot.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/am437x-idk-evm-u-boot.dtsi b/arch/arm/dts/am437x-idk-evm-u-boot.dtsi index 3aa9195e44d..50fe09cfc36 100644 --- a/arch/arm/dts/am437x-idk-evm-u-boot.dtsi +++ b/arch/arm/dts/am437x-idk-evm-u-boot.dtsi @@ -9,6 +9,12 @@ ocp { u-boot,dm-spl; }; + + xtal25mhz: xtal25mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; }; &uart0 { @@ -17,6 +23,14 @@ &i2c0 { u-boot,dm-spl; + + cdce913: cdce913@65 { + compatible = "ti,cdce913"; + reg = <0x65>; + clocks = <&xtal25mhz>; + #clock-cells = <1>; + xtal-load-pf = <0>; + }; }; &mmc1 { -- cgit v1.3.1