From 116d1d0047d7479ea5b72260314d46ebf0927e19 Mon Sep 17 00:00:00 2001 From: Tony Dinh Date: Tue, 26 Nov 2024 16:57:16 -0800 Subject: arm: kirkwood: Enable bootstd and other modernization for OpenRD boards Enable bootstd for OpenRD boards Update defconfigs to the latest u-boot requirements Remove JFFS2 support. See JFFS2 Vulnerability[1]. Move default envs to text-base environment [1] https://lore.kernel.org/u-boot/20241114233005.GN3600562@bill-the-cat/T/#m2fc25da1d2c019bc3cd8676991fdd64b8a21aa9b Signed-off-by: Tony Dinh Reviewed-by: Stefan Roese --- arch/arm/mach-kirkwood/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 031d4e5ecd3..6761a9cb393 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -38,6 +38,7 @@ config TARGET_OPENRD bool "Marvell OpenRD Board" select KW88F6281 select SHEEVA_88SV131 + select KIRKWOOD_COMMON config TARGET_DREAMPLUG bool "DreamPlug Board" -- cgit v1.3.1 From 08b27fce29eb9f07768bdab02bb9dd58e3e0ee36 Mon Sep 17 00:00:00 2001 From: Duje Mihanović Date: Fri, 24 Jan 2025 16:47:49 +0100 Subject: arm: mmp: add initial support for PXA1908 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add initial support for Marvell PXA1908. The SoC has 4 Cortex-A53 cores, a GC7000UL GPU and a variety of peripheral controllers. Signed-off-by: Duje Mihanović Reviewed-by: Stefan Roese --- MAINTAINERS | 8 ++++ arch/arm/Kconfig | 11 +++++ arch/arm/Makefile | 1 + arch/arm/dts/pxa1908.dtsi | 106 +++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-mmp/Kconfig | 6 +++ arch/arm/mach-mmp/Makefile | 1 + arch/arm/mach-mmp/board.c | 84 +++++++++++++++++++++++++++++++++++ arch/arm/mach-mmp/mmu.c | 30 +++++++++++++ include/configs/pxa1908.h | 18 ++++++++ 9 files changed, 265 insertions(+) create mode 100644 arch/arm/dts/pxa1908.dtsi create mode 100644 arch/arm/mach-mmp/Kconfig create mode 100644 arch/arm/mach-mmp/Makefile create mode 100644 arch/arm/mach-mmp/board.c create mode 100644 arch/arm/mach-mmp/mmu.c create mode 100644 include/configs/pxa1908.h (limited to 'arch') diff --git a/MAINTAINERS b/MAINTAINERS index dc8e048dde4..247f525847e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -386,6 +386,14 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git F: drivers/pci/pci-aardvark.c F: drivers/pci/pci_mvebu.c +ARM MARVELL PXA1908 +M: Duje Mihanović +S: Maintained +T: git git://git.dujemihanovic.xyz/u-boot.git +F: arch/arm/dts/pxa1908* +F: arch/arm/mach-mmp/ +F: include/configs/pxa1908.h + ARM MARVELL SERIAL DRIVERS M: Pali Rohár M: Stefan Roese diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 314916527c9..f504d7d0760 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -842,6 +842,15 @@ config ARCH_MEDIATEK Support for the MediaTek SoCs family developed by MediaTek Inc. Please refer to doc/README.mediatek for more information. +config ARCH_MMP + bool "Marvell MMP" + select ARM64 + select DM + select DM_SERIAL + select OF_CONTROL + select SAVE_PREV_BL_FDT_ADDR + select SAVE_PREV_BL_INITRAMFS_START_ADDR + config ARCH_LPC32XX bool "NXP LPC32xx platform" select CPU_ARM926EJS @@ -2310,6 +2319,8 @@ source "arch/arm/mach-meson/Kconfig" source "arch/arm/mach-mediatek/Kconfig" +source "arch/arm/mach-mmp/Kconfig" + source "arch/arm/mach-qemu/Kconfig" source "arch/arm/mach-rockchip/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index cb87a684754..7334e79965f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -69,6 +69,7 @@ machine-$(CONFIG_ARCH_KIRKWOOD) += kirkwood machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx machine-$(CONFIG_ARCH_MEDIATEK) += mediatek machine-$(CONFIG_ARCH_MESON) += meson +machine-$(CONFIG_ARCH_MMP) += mmp machine-$(CONFIG_ARCH_MVEBU) += mvebu machine-$(CONFIG_ARCH_NEXELL) += nexell machine-$(CONFIG_ARCH_NPCM) += npcm diff --git a/arch/arm/dts/pxa1908.dtsi b/arch/arm/dts/pxa1908.dtsi new file mode 100644 index 00000000000..e8ec2606c25 --- /dev/null +++ b/arch/arm/dts/pxa1908.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include + +/ { + model = "Marvell Armada PXA1908"; + compatible = "marvell,pxa1908"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0 0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0 1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0 2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0 3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@d1df9000 { + compatible = "arm,gic-400"; + reg = <0 0xd1df9000 0 0x1000>, + <0 0xd1dfa000 0 0x2000>, + /* The subsequent registers are guesses. */ + <0 0xd1dfc000 0 0x2000>, + <0 0xd1dfe000 0 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + apb@d4000000 { + compatible = "simple-bus"; + reg = <0 0xd4000000 0 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xd4000000 0x200000>; + + uart0: serial@17000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0x17000 0x1000>; + clock-frequency = <14745600>; + reg-shift = <2>; + }; + + uart1: serial@18000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0x18000 0x1000>; + clock-frequency = <14745600>; + reg-shift = <2>; + }; + + uart2: serial@36000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0x36000 0x1000>; + clock-frequency = <117000000>; + reg-shift = <2>; + }; + }; + }; +}; diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig new file mode 100644 index 00000000000..b9438c6facb --- /dev/null +++ b/arch/arm/mach-mmp/Kconfig @@ -0,0 +1,6 @@ +if ARCH_MMP + +config LNX_KRNL_IMG_TEXT_OFFSET_BASE + default TEXT_BASE + +endif diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile new file mode 100644 index 00000000000..99beaed05c2 --- /dev/null +++ b/arch/arm/mach-mmp/Makefile @@ -0,0 +1 @@ +obj-y += board.o mmu.o diff --git a/arch/arm/mach-mmp/board.c b/arch/arm/mach-mmp/board.c new file mode 100644 index 00000000000..3384e5377a7 --- /dev/null +++ b/arch/arm/mach-mmp/board.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 + * Duje Mihanović + */ +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* Timer constants */ +#define APBC_COUNTER_CLK_SEL 0xd4015064 +#define COUNTER_BASE 0xd4101000 +#define COUNTER_EN BIT(0) +#define COUNTER_HALT_ON_DEBUG BIT(1) + +int timer_init(void) +{ + u32 tmp = readl(APBC_COUNTER_CLK_SEL); + + if ((tmp >> 16) != 0x319) + return -1; + + /* Set timer frequency to 26MHz */ + writel(tmp | 1, APBC_COUNTER_CLK_SEL); + writel(COUNTER_EN | COUNTER_HALT_ON_DEBUG, COUNTER_BASE); + + gd->arch.timer_rate_hz = 26000000; + + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_mem_size_base() != 0) + puts("fdtdec_setup_mem_size_base() has failed\n"); + + return 0; +} + +#ifndef CONFIG_SYSRESET +void reset_cpu(void) +{ +} +#endif + +/* Stolen from arch/arm/mach-snapdragon/board.c */ +int board_fdt_blob_setup(void **fdtp) +{ + struct fdt_header *fdt; + bool internal_valid, external_valid; + int ret = 0; + + fdt = (struct fdt_header *)get_prev_bl_fdt_addr(); + external_valid = fdt && !fdt_check_header(fdt); + internal_valid = !fdt_check_header(*fdtp); + + /* + * There is no point returning an error here, U-Boot can't do anything useful in this situation. + * Bail out while we can still print a useful error message. + */ + if (!internal_valid && !external_valid) + panic("Internal FDT is invalid and no external FDT was provided! (fdt=%#llx)\n", + (phys_addr_t)fdt); + + if (internal_valid) { + debug("Using built in FDT\n"); + ret = -EEXIST; + } else { + debug("Using external FDT\n"); + /* So we can use it before returning */ + *fdtp = fdt; + } + + return ret; +} diff --git a/arch/arm/mach-mmp/mmu.c b/arch/arm/mach-mmp/mmu.c new file mode 100644 index 00000000000..ad2f1e3d994 --- /dev/null +++ b/arch/arm/mach-mmp/mmu.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 + * Duje Mihanović + */ +#include +#include + +static struct mm_region pxa1908_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 2UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 2UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { + 0, + } +}; + +struct mm_region *mem_map = pxa1908_mem_map; diff --git a/include/configs/pxa1908.h b/include/configs/pxa1908.h new file mode 100644 index 00000000000..b0d6cdfeb76 --- /dev/null +++ b/include/configs/pxa1908.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024 + * Duje Mihanović + */ + +#ifndef __PXA1908_H +#define __PXA1908_H + +#define CFG_SYS_SDRAM_BASE 0x1000000 +#define CFG_SYS_INIT_RAM_ADDR 0x10000000 +#define CFG_SYS_INIT_RAM_SIZE 0x4000 +#define CFG_SYS_NS16550_IER 0x40 +#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } +#define CFG_EXTRA_ENV_SETTINGS \ + "bootcmd=bootm $prevbl_initrd_start_addr\0" + +#endif -- cgit v1.3.1 From 5983f0ff6128583ee2771d39d45a3e9a15caf470 Mon Sep 17 00:00:00 2001 From: Duje Mihanović Date: Fri, 24 Jan 2025 16:47:50 +0100 Subject: board: samsung: add initial support for coreprimevelte board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Samsung Galaxy Core Prime VE LTE is an entry-level PXA1908-based smartphone. It has 1GB of DRAM, 8GB eMMC and USB connectivity. Signed-off-by: Duje Mihanović Reviewed-by: Stefan Roese --- arch/arm/dts/Makefile | 2 + arch/arm/dts/pxa1908-samsung-coreprimevelte.dts | 74 +++++++++++++++++++++++++ arch/arm/mach-mmp/Kconfig | 6 ++ board/samsung/coreprimevelte/Kconfig | 12 ++++ board/samsung/coreprimevelte/MAINTAINERS | 6 ++ configs/coreprimevelte_defconfig | 18 ++++++ 6 files changed, 118 insertions(+) create mode 100644 arch/arm/dts/pxa1908-samsung-coreprimevelte.dts create mode 100644 board/samsung/coreprimevelte/Kconfig create mode 100644 board/samsung/coreprimevelte/MAINTAINERS create mode 100644 configs/coreprimevelte_defconfig (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b7df72453ac..0bf3697bdbe 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1226,6 +1226,8 @@ dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \ corstone1000-fvp.dtb +dtb-$(CONFIG_TARGET_COREPRIMEVELTE) += pxa1908-samsung-coreprimevelte.dtb + include $(srctree)/scripts/Makefile.dts # Add any required device tree compiler flags here diff --git a/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts b/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts new file mode 100644 index 00000000000..588e39e9265 --- /dev/null +++ b/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "pxa1908.dtsi" + +/ { + pxa,rev-id = <3928 2>; + model = "Samsung Galaxy Core Prime VE LTE"; + compatible = "samsung,coreprimevelte", "marvell,pxa1908"; + + aliases { + serial0 = &uart0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0:115200n8"; + + /* S-Boot places the initramfs here */ + linux,initrd-start = <0x4d70000>; + linux,initrd-end = <0x5000000>; + + fb0: framebuffer@17177000 { + compatible = "simple-framebuffer"; + reg = <0 0x17177000 0 (480 * 800 * 4)>; + width = <480>; + height = <800>; + stride = <(480 * 4)>; + format = "a8r8g8b8"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0x1000000 0 0x3f000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@17000000 { + reg = <0 0x17000000 0 0x1800000>; + no-map; + }; + + gpu@9000000 { + reg = <0 0x9000000 0 0x1000000>; + }; + + /* Communications processor, aka modem */ + cp@5000000 { + reg = <0 0x5000000 0 0x3000000>; + }; + + cm3@a000000 { + reg = <0 0xa000000 0 0x80000>; + }; + + seclog@8000000 { + reg = <0 0x8000000 0 0x100000>; + }; + + ramoops@8100000 { + compatible = "ramoops"; + reg = <0 0x8100000 0 0x40000>; + record-size = <0x8000>; + console-size = <0x20000>; + max-reason = <5>; + }; + }; +}; diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index b9438c6facb..889f127fe82 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig @@ -1,6 +1,12 @@ if ARCH_MMP +config TARGET_COREPRIMEVELTE + bool "Support coreprimevelte" + select LINUX_KERNEL_IMAGE_HEADER + config LNX_KRNL_IMG_TEXT_OFFSET_BASE default TEXT_BASE +source "board/samsung/coreprimevelte/Kconfig" + endif diff --git a/board/samsung/coreprimevelte/Kconfig b/board/samsung/coreprimevelte/Kconfig new file mode 100644 index 00000000000..78a80379605 --- /dev/null +++ b/board/samsung/coreprimevelte/Kconfig @@ -0,0 +1,12 @@ +if TARGET_COREPRIMEVELTE + +config SYS_BOARD + default "coreprimevelte" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "pxa1908" + +endif diff --git a/board/samsung/coreprimevelte/MAINTAINERS b/board/samsung/coreprimevelte/MAINTAINERS new file mode 100644 index 00000000000..0902117e8b3 --- /dev/null +++ b/board/samsung/coreprimevelte/MAINTAINERS @@ -0,0 +1,6 @@ +Samsung Galaxy Core Prime VE LTE support +M: Duje Mihanović +S: Maintained +T: git git://git.dujemihanovic.xyz/u-boot.git +F: board/samsung/coreprimevelte/ +F: configs/coreprimevelte_defconfig diff --git a/configs/coreprimevelte_defconfig b/configs/coreprimevelte_defconfig new file mode 100644 index 00000000000..05116669200 --- /dev/null +++ b/configs/coreprimevelte_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=26000000 +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_MMP=y +CONFIG_TEXT_BASE=0x1000000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_DEFAULT_DEVICE_TREE="pxa1908-samsung-coreprimevelte" +CONFIG_TARGET_COREPRIMEVELTE=y +CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_ARMV8_PSCI=y +CONFIG_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_DM=y +CONFIG_OF_BOARD=y +CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y -- cgit v1.3.1