From 1e0d51a6c4cdd22a75abbdf392484c66ff8a91ea Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 17 Oct 2017 08:00:21 -0700 Subject: powerpc: mpc85xx: Implement CPU erratum A-007907 for secondary cores Commit 06ad970b53a3 ("powerpc: mpc85xx: Implemente workaround for CPU erratum A-007907") clears L1CSR2 for the boot core, but other cores don't run through the workaround. Add similar code for secondary cores to clear DCSTASHID field in L1CSR2 register. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/release.S | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 0e0daf5a44e..e1f12089c33 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -184,12 +184,18 @@ __secondary_start_page: mtspr SPRN_PIR,r4 /* write to PIR register */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907 + mfspr r8, L1CSR2 + clrrwi r8, r8, 10 /* clear bit [54-63] DCSTASHID */ + mtspr L1CSR2, r8 +#else #ifdef CONFIG_SYS_CACHE_STASHING /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ slwi r8,r4,1 addi r8,r8,32 mtspr L1CSR2,r8 #endif +#endif /* CONFIG_SYS_FSL_ERRATUM_A007907 */ #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) -- cgit v1.3.1 From 4417e83495dbc6d047a08eb8fc2ca73ec7dfd704 Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Mon, 23 Oct 2017 10:09:21 +0800 Subject: arm64: layerscape: Move CONFIG_HAS_FSL_XHCI_USB to Kconfig Use Kconfig to select QE-HDLC and USB pin-mux. Signed-off-by: Ran Wang Reviewed-by: Bin Meng Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 +++++++ include/configs/ls1012afrdm.h | 4 ---- include/configs/ls1012aqds.h | 4 ---- include/configs/ls1012ardb.h | 4 ---- include/configs/ls1021aiot.h | 4 ---- include/configs/ls1021aqds.h | 4 ---- include/configs/ls1021atwr.h | 4 ---- include/configs/ls1043aqds.h | 3 --- include/configs/ls1043ardb.h | 3 --- include/configs/ls1046aqds.h | 3 --- include/configs/ls1046ardb.h | 3 --- include/configs/ls2080aqds.h | 1 - include/configs/ls2080ardb.h | 1 - scripts/config_whitelist.txt | 1 - 14 files changed, 7 insertions(+), 39 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 85b7c70937e..8bbc981d43f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -490,3 +490,10 @@ config SYS_MC_RSV_MEM_ALIGN config SPL_LDSCRIPT default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A + +config HAS_FSL_XHCI_USB + bool + default y if ARCH_LS1043A || ARCH_LS1046A + help + For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use + pins, select it when the pins are assigned to USB. diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 6b1ba578e92..2e5af9cc4e2 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -34,12 +34,8 @@ /* * USB */ -#define CONFIG_HAS_FSL_XHCI_USB - -#ifdef CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif #define CONFIG_CMD_MEMINFO #define CONFIG_CMD_MEMTEST diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index b3121d2c21e..e0949d0b53d 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -119,12 +119,8 @@ #endif /*XHCI Support - enabled by default*/ -#define CONFIG_HAS_FSL_XHCI_USB - -#ifdef CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif /* MMC */ #ifdef CONFIG_MMC diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index e9edcd2bc94..66ff0043848 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -22,12 +22,8 @@ /* * USB */ -#define CONFIG_HAS_FSL_XHCI_USB - -#ifdef CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif /* * I2C IO expander diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 63667810bd1..02bfbd0a7db 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -20,12 +20,8 @@ #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE /* XHCI Support - enabled by default */ -#define CONFIG_HAS_FSL_XHCI_USB - -#ifdef CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000 diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index f3d3aa22712..0046ded536f 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -405,12 +405,8 @@ unsigned long get_board_ddr_clk(void); #endif /*XHCI Support - enabled by default*/ -#define CONFIG_HAS_FSL_XHCI_USB - -#ifdef CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif /* * Video diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 852ff57fb6d..0172c9015d3 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -45,12 +45,8 @@ #endif /* XHCI Support - enabled by default */ -#define CONFIG_HAS_FSL_XHCI_USB - -#ifdef CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000 diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 5aadd92efd5..607c289d179 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -371,11 +371,8 @@ unsigned long get_board_ddr_clk(void); #endif /* USB */ -#define CONFIG_HAS_FSL_XHCI_USB -#ifdef CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 -#endif /* * Miscellaneous configurable options diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index f9843f5ebae..34be9960c16 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -286,12 +286,9 @@ /* USB */ #ifndef SPL_NO_USB -#define CONFIG_HAS_FSL_XHCI_USB -#ifdef CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 #endif -#endif /* SATA */ #ifndef SPL_NO_SATA diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 39bd1c38a80..b0d41b401e8 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -137,11 +137,8 @@ unsigned long get_board_ddr_clk(void); #endif /* USB */ -#define CONFIG_HAS_FSL_XHCI_USB -#ifdef CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 -#endif /* SATA */ #define CONFIG_LIBATA diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 7bbd4ada707..32b08d8229a 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -211,12 +211,9 @@ /* USB */ #ifndef SPL_NO_USB -#define CONFIG_HAS_FSL_XHCI_USB -#ifdef CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 #endif -#endif /* SATA */ #ifndef SPL_NO_SATA diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 54d6b51c552..d594cc10687 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -438,7 +438,6 @@ unsigned long get_board_ddr_clk(void); /* * USB */ -#define CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 9e9979e1c7f..c368a566572 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -336,7 +336,6 @@ unsigned long get_board_sys_clk(void); /* * USB */ -#define CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 5ee1601f0e7..76267495bed 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -873,7 +873,6 @@ CONFIG_HAS_ETH7 CONFIG_HAS_FEC CONFIG_HAS_FSL_DR_USB CONFIG_HAS_FSL_MPH_USB -CONFIG_HAS_FSL_XHCI_USB CONFIG_HAS_POST CONFIG_HCLK_FREQ CONFIG_HDBOOT -- cgit v1.3.1 From d4c746c7b1f802685f75fa531a88104b19861a8c Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Mon, 23 Oct 2017 10:09:24 +0800 Subject: armv8: ls1088ardb: Enable USB command RDB qspi-boot Signed-off-by: Ashish Kumar Signed-off-by: Amrita Kumari Signed-off-by: Ran Wang Reviewed-by: Bin Meng Reviewed-by: York Sun --- arch/arm/dts/fsl-ls1088a.dtsi | 14 ++++++++++++++ configs/ls1088ardb_qspi_defconfig | 8 ++++++++ include/linux/usb/xhci-fsl.h | 2 +- 3 files changed, 23 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index d943a9efa32..64b4fcf12b6 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -76,6 +76,20 @@ num-cs = <4>; }; + usb0: usb3@3100000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; /* Level high type */ + dr_mode = "host"; + }; + + usb1: usb3@3110000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; /* Level high type */ + dr_mode = "host"; + }; + pcie@3400000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 0909c0ab350..bd44fa99df0 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -31,3 +31,11 @@ CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_CMD_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_STORAGE=y diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index bd54089722f..a916afb885a 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -58,7 +58,7 @@ struct fsl_xhci { #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 -#elif defined(CONFIG_ARCH_LS2080A) +#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 -- cgit v1.3.1 From 9781d9ff5fafd3c433b426914f9d017ddfe757b5 Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Fri, 1 Sep 2017 13:55:00 +0530 Subject: armv8: layerscape: Allocate 66 MB DDR for secure memory Change DDR allocated for secure memory from 2 MB to 66 MB. This additional 64 MB secure memory is required for trusted OS running in Trusted Execution Environment using ARMv8 TrustZone. Signed-off-by: Sumit Garg Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index a7098be8463..95e27915077 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -16,7 +16,7 @@ * Reserve secure memory * To be aligned with MMU block size */ -#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ +#define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */ #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */ #ifdef CONFIG_ARCH_LS2080A -- cgit v1.3.1 From 9b3f40ad092ff2633eefa7e8a4a713f71c9cb8cb Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Fri, 1 Sep 2017 13:55:01 +0530 Subject: armv8: sec_firmware: Add support for loadables in FIT Enable support for loadables in SEC firmware FIT image. Currently support is added for single loadable image. Brief description of implementation: Add two more address pointers (loadable_h, loadable_l) as arguments to sec_firmware_init() api. Create new api: sec_firmware_checks_copy_loadable() to check if loadables node is present in SEC firmware FIT image. If present, verify loadable image and copies it to secure DDR memory. Populate address pointers with secure DDR memory addresses where loadable is copied. Example use-case could be trusted OS (tee.bin) as loadables node in SEC firmware FIT image. Signed-off-by: Sumit Garg Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 16 +++++- arch/arm/cpu/armv8/sec_firmware.c | 92 +++++++++++++++++++++++++++++-- arch/arm/include/asm/armv8/sec_firmware.h | 4 +- 3 files changed, 104 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c index bbf8bba1120..cddcee964af 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c @@ -35,6 +35,7 @@ int ppa_init(void) unsigned int el = current_el(); void *ppa_fit_addr; u32 *boot_loc_ptr_l, *boot_loc_ptr_h; + u32 *loadable_l, *loadable_h; int ret; #ifdef CONFIG_CHAIN_OF_TRUST @@ -240,9 +241,9 @@ int ppa_init(void) PPA_KEY_HASH, &ppa_img_addr); if (ret != 0) - printf("PPA validation failed\n"); + printf("SEC firmware(s) validation failed\n"); else - printf("PPA validation Successful\n"); + printf("SEC firmware(s) validation Successful\n"); } #if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \ defined(CONFIG_SYS_LS_PPA_FW_IN_NAND) @@ -254,15 +255,24 @@ int ppa_init(void) struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); boot_loc_ptr_l = &gur->bootlocptrl; boot_loc_ptr_h = &gur->bootlocptrh; + + /* Assign addresses to loadable ptrs */ + loadable_l = &gur->scratchrw[4]; + loadable_h = &gur->scratchrw[5]; #elif defined(CONFIG_FSL_LSCH2) struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR); boot_loc_ptr_l = &scfg->scratchrw[1]; boot_loc_ptr_h = &scfg->scratchrw[0]; + + /* Assign addresses to loadable ptrs */ + loadable_l = &scfg->scratchrw[2]; + loadable_h = &scfg->scratchrw[3]; #endif debug("fsl-ppa: boot_loc_ptr_l = 0x%p, boot_loc_ptr_h =0x%p\n", boot_loc_ptr_l, boot_loc_ptr_h); - ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h); + ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h, + loadable_l, loadable_h); #if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \ defined(CONFIG_SYS_LS_PPA_FW_IN_NAND) diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index 0e7483437a9..927eae4f741 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -105,6 +105,74 @@ static int sec_firmware_parse_image(const void *sec_firmware_img, return 0; } +/* + * SEC Firmware FIT image parser to check if any loadable is + * present. If present, verify integrity of the loadable and + * copy loadable to address provided in (loadable_h, loadable_l). + * + * Returns 0 on success and a negative errno on error task fail. + */ +static int sec_firmware_check_copy_loadable(const void *sec_firmware_img, + u32 *loadable_l, u32 *loadable_h) +{ + phys_addr_t sec_firmware_loadable_addr = 0; + int conf_node_off, ld_node_off; + char *conf_node_name = NULL; + const void *data; + size_t size; + ulong load; + + conf_node_name = SEC_FIRMEWARE_FIT_CNF_NAME; + + conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name); + if (conf_node_off < 0) { + printf("SEC Firmware: %s: no such config\n", conf_node_name); + return -ENOENT; + } + + ld_node_off = fit_conf_get_prop_node(sec_firmware_img, conf_node_off, + FIT_LOADABLE_PROP); + if (ld_node_off >= 0) { + printf("SEC Firmware: '%s' present in config\n", + FIT_LOADABLE_PROP); + + /* Verify secure firmware image */ + if (!(fit_image_verify(sec_firmware_img, ld_node_off))) { + printf("SEC Loadable: Bad loadable image (bad CRC)\n"); + return -EINVAL; + } + + if (fit_image_get_data(sec_firmware_img, ld_node_off, + &data, &size)) { + printf("SEC Loadable: Can't get subimage data/size"); + return -ENOENT; + } + + /* Get load address, treated as load offset to secure memory */ + if (fit_image_get_load(sec_firmware_img, ld_node_off, &load)) { + printf("SEC Loadable: Can't get subimage load"); + return -ENOENT; + } + + /* Compute load address for loadable in secure memory */ + sec_firmware_loadable_addr = (sec_firmware_addr - + gd->arch.tlb_size) + load; + + /* Copy loadable to secure memory and flush dcache */ + debug("%s copied to address 0x%p\n", + FIT_LOADABLE_PROP, (void *)sec_firmware_loadable_addr); + memcpy((void *)sec_firmware_loadable_addr, data, size); + flush_dcache_range(sec_firmware_loadable_addr, + sec_firmware_loadable_addr + size); + } + + /* Populate address ptrs for loadable image with loadbale addr */ + out_le32(loadable_l, (sec_firmware_loadable_addr & WORD_MASK)); + out_le32(loadable_h, (sec_firmware_loadable_addr >> WORD_SHIFT)); + + return 0; +} + static int sec_firmware_copy_image(const char *title, u64 image_addr, u32 image_size, u64 sec_firmware) { @@ -117,9 +185,11 @@ static int sec_firmware_copy_image(const char *title, /* * This function will parse the SEC Firmware image, and then load it - * to secure memory. + * to secure memory. Also load any loadable if present along with SEC + * Firmware image. */ -static int sec_firmware_load_image(const void *sec_firmware_img) +static int sec_firmware_load_image(const void *sec_firmware_img, + u32 *loadable_l, u32 *loadable_h) { const void *raw_image_addr; size_t raw_image_size = 0; @@ -172,6 +242,15 @@ static int sec_firmware_load_image(const void *sec_firmware_img) if (ret) goto out; + /* + * Check if any loadable are present along with firmware image, if + * present load them. + */ + ret = sec_firmware_check_copy_loadable(sec_firmware_img, loadable_l, + loadable_h); + if (ret) + goto out; + sec_firmware_addr |= SEC_FIRMWARE_LOADED; debug("SEC Firmware: Entry point: 0x%llx\n", sec_firmware_addr & SEC_FIRMWARE_ADDR_MASK); @@ -289,17 +368,22 @@ int sec_firmware_get_random(uint8_t *rand, int bytes) * @sec_firmware_img: the SEC Firmware image address * @eret_hold_l: the address to hold exception return address low * @eret_hold_h: the address to hold exception return address high + * @loadable_l: the address to hold loadable address low + * @loadable_h: the address to hold loadable address high */ int sec_firmware_init(const void *sec_firmware_img, u32 *eret_hold_l, - u32 *eret_hold_h) + u32 *eret_hold_h, + u32 *loadable_l, + u32 *loadable_h) { int ret; if (!sec_firmware_is_valid(sec_firmware_img)) return -EINVAL; - ret = sec_firmware_load_image(sec_firmware_img); + ret = sec_firmware_load_image(sec_firmware_img, loadable_l, + loadable_h); if (ret) { printf("SEC Firmware: Failed to load image\n"); return ret; diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h index 6d42a7111f2..2ba1847a2ed 100644 --- a/arch/arm/include/asm/armv8/sec_firmware.h +++ b/arch/arm/include/asm/armv8/sec_firmware.h @@ -9,8 +9,10 @@ #define PSCI_INVALID_VER 0xffffffff #define SEC_JR3_OFFSET 0x40000 +#define WORD_MASK 0xffffffff +#define WORD_SHIFT 32 -int sec_firmware_init(const void *, u32 *, u32 *); +int sec_firmware_init(const void *, u32 *, u32 *, u32 *, u32 *); int _sec_firmware_entry(const void *, u32 *, u32 *); bool sec_firmware_is_valid(const void *); bool sec_firmware_support_hwrng(void); -- cgit v1.3.1